/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef __SENINF_CAM_MUX_GCSR_H__
#define __SENINF_CAM_MUX_GCSR_H__

#define SENINF_CAM_MUX_GCSR_CTRL 0x0000
#define RG_SENINF_CAM_MUX_GCSR_SW_RST_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_SW_RST_MASK (0x1 << 0)
#define RG_SENINF_CAM_MUX_GCSR_IRQ_SW_RST_SHIFT 1
#define RG_SENINF_CAM_MUX_GCSR_IRQ_SW_RST_MASK (0x1 << 1)
#define RG_SENINF_CAM_MUX_GCSR_SLICE_FULL_OPT_SHIFT 7
#define RG_SENINF_CAM_MUX_GCSR_SLICE_FULL_OPT_MASK (0x1 << 7)
#define RG_SENINF_CAM_MUX_GCSR_IRQ_CLR_MODE_SHIFT 8
#define RG_SENINF_CAM_MUX_GCSR_IRQ_CLR_MODE_MASK (0x1 << 8)
#define RG_SENINF_CAM_MUX_GCSR_IRQ_VERIF_EN_SHIFT 9
#define RG_SENINF_CAM_MUX_GCSR_IRQ_VERIF_EN_MASK (0x1 << 9)

#define SENINF_CAM_MUX_GCSR_DYN_CTRL 0x0004
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_BSY0_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_BSY0_MASK (0x1 << 0)
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_BSY1_SHIFT 1
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_BSY1_MASK (0x1 << 1)
#define RG_SENINF_CAM_MUX_GCSR_DYN_PAGE_SEL_SHIFT 7
#define RG_SENINF_CAM_MUX_GCSR_DYN_PAGE_SEL_MASK (0x1 << 7)
#define RG_SENINF_CAM_MUX_GCSR_OCC_PG1_EN_SHIFT 8
#define RG_SENINF_CAM_MUX_GCSR_OCC_PG1_EN_MASK (0x1 << 8)

#define SENINF_CAM_MUX_GCSR_IRQ_EN 0x0008
#define RG_SENINF_CAM_MUX_GCSR_ALL_VSYNC_IRQ_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_ALL_VSYNC_IRQ_EN_MASK (0x3 << 0)
#define RG_SENINF_CAM_MUX_GCSR_ALL_VSYNC_NONE_IRQ_EN_SHIFT 4
#define RG_SENINF_CAM_MUX_GCSR_ALL_VSYNC_NONE_IRQ_EN_MASK (0x3 << 4)
#define RG_SENINF_CAM_MUX_GCSR_SKIP_NEXT_FRAME_IRQ_EN_SHIFT 8
#define RG_SENINF_CAM_MUX_GCSR_SKIP_NEXT_FRAME_IRQ_EN_MASK (0x3 << 8)

#define SENINF_CAM_MUX_GCSR_IRQ_STS 0x000c
#define RO_SENINF_CAM_MUX_GCSR_ALL_VSYNC_IRQ_SHIFT 0
#define RO_SENINF_CAM_MUX_GCSR_ALL_VSYNC_IRQ_MASK (0x3 << 0)
#define RO_SENINF_CAM_MUX_GCSR_ALL_VSYNC_NONE_IRQ_SHIFT 4
#define RO_SENINF_CAM_MUX_GCSR_ALL_VSYNC_NONE_IRQ_MASK (0x3 << 4)
#define RO_SENINF_CAM_MUX_GCSR_SKIP_NEXT_FRAME_IRQ_SHIFT 8
#define RO_SENINF_CAM_MUX_GCSR_SKIP_NEXT_FRAME_IRQ_MASK (0x3 << 8)

#define SENINF_CAM_MUX_GCSR_IRQ_TRIG 0x0010
#define RG_SENINF_CAM_MUX_GCSR_GCSR_IRQ_TRIG_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_GCSR_IRQ_TRIG_MASK (0xffffffff << 0)

#define SENINF_CAM_MUX_GCSR_VSYNC_T0_WINDOW_L 0x0018
#define RG_SENINF_CAM_MUX_GCSR_VSYNC_TIMER0_WINDOW_L_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_VSYNC_TIMER0_WINDOW_L_MASK (0xffffffff << 0)

#define SENINF_CAM_MUX_GCSR_VSYNC_T1_WINDOW_L 0x0020
#define RG_SENINF_CAM_MUX_GCSR_VSYNC_TIMER1_WINDOW_L_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_VSYNC_TIMER1_WINDOW_L_MASK (0xffffffff << 0)

#define SENINF_CAM_MUX_GCSR_MUX_EN 0x00c0
#define RG_SENINF_CAM_MUX_GCSR_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_CHK_EN 0x00c4
#define RG_SENINF_CAM_MUX_GCSR_CHK_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_CHK_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_DYN_EN0 0x00c8
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_EN0_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_EN0_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_DYN_EN1 0x00cc
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_EN1_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_DYN_SWITCH_EN1_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_VC_SEL_EN 0x00d0
#define RG_SENINF_CAM_MUX_GCSR_VC_SEL_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_VC_SEL_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_DT_SEL_EN 0x00d4
#define RG_SENINF_CAM_MUX_GCSR_DT_SEL_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_DT_SEL_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_HSIZE_ERR_IRQ_EN 0x00d8
#define RG_SENINF_CAM_MUX_GCSR_HSIZE_ERR_IRQ_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_HSIZE_ERR_IRQ_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_VSIZE_ERR_IRQ_EN 0x00dc
#define RG_SENINF_CAM_MUX_GCSR_VSIZE_ERR_IRQ_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_VSIZE_ERR_IRQ_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_VSYNC_IRQ_EN 0x00e0
#define RG_SENINF_CAM_MUX_GCSR_VSYNC_IRQ_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_VSYNC_IRQ_EN_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_HSIZE_ERR_IRQ_STS 0x00e4
#define RO_SENINF_CAM_MUX_GCSR_HSIZE_ERR_IRQ_SHIFT 0
#define RO_SENINF_CAM_MUX_GCSR_HSIZE_ERR_IRQ_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_VSIZE_ERR_IRQ_STS 0x00e8
#define RO_SENINF_CAM_MUX_GCSR_VSIZE_ERR_IRQ_SHIFT 0
#define RO_SENINF_CAM_MUX_GCSR_VSIZE_ERR_IRQ_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_VSYNC_IRQ_STS 0x00ec
#define RO_SENINF_CAM_MUX_GCSR_VSYNC_IRQ_SHIFT 0
#define RO_SENINF_CAM_MUX_GCSR_VSYNC_IRQ_MASK (0x7fffff << 0)

#define SENINF_CAM_MUX_GCSR_DBG_CTRL 0x00f0
#define RG_SENINF_CAM_MUX_GCSR_DBG_EN_SHIFT 0
#define RG_SENINF_CAM_MUX_GCSR_DBG_EN_MASK (0x1 << 0)
#define RG_SENINF_CAM_MUX_GCSR_DBG_SEL_SHIFT 8
#define RG_SENINF_CAM_MUX_GCSR_DBG_SEL_MASK (0xff << 8)

#define SENINF_CAM_MUX_GCSR_DBG_OUT 0x00f4
#define RO_SENINF_CAM_MUX_GCSR_DBG_OUT_SHIFT 0
#define RO_SENINF_CAM_MUX_GCSR_DBG_OUT_MASK (0xffffffff << 0)

#define SENINF_CAM_MUX_GCSR_SPARE 0x00f8
#define RG_SENINF_TOP_SPARE_0_SHIFT 0
#define RG_SENINF_TOP_SPARE_0_MASK (0xff << 0)
#define RG_SENINF_TOP_SPARE_1_SHIFT 16
#define RG_SENINF_TOP_SPARE_1_MASK (0xff << 16)

#endif
