/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef __CSI0_DPHY_TOP_H__
#define __CSI0_DPHY_TOP_H__

#define DPHY_RX_LANE_EN 0x0000
#define DPHY_RX_LC0_EN_SHIFT 0
#define DPHY_RX_LC0_EN_MASK (0x1 << 0)
#define DPHY_RX_LC1_EN_SHIFT 1
#define DPHY_RX_LC1_EN_MASK (0x1 << 1)
#define DPHY_RX_LD0_EN_SHIFT 8
#define DPHY_RX_LD0_EN_MASK (0x1 << 8)
#define DPHY_RX_LD1_EN_SHIFT 9
#define DPHY_RX_LD1_EN_MASK (0x1 << 9)
#define DPHY_RX_LD2_EN_SHIFT 10
#define DPHY_RX_LD2_EN_MASK (0x1 << 10)
#define DPHY_RX_LD3_EN_SHIFT 11
#define DPHY_RX_LD3_EN_MASK (0x1 << 11)
#define DPHY_RX_SW_RST_SHIFT 31
#define DPHY_RX_SW_RST_MASK (0x1 << 31)

#define DPHY_RX_LANE_SELECT 0x0004
#define RG_DPHY_RX_LC0_SEL_SHIFT 0
#define RG_DPHY_RX_LC0_SEL_MASK (0x7 << 0)
#define RG_DPHY_RX_LC1_SEL_SHIFT 4
#define RG_DPHY_RX_LC1_SEL_MASK (0x7 << 4)
#define RG_DPHY_RX_LD0_SEL_SHIFT 8
#define RG_DPHY_RX_LD0_SEL_MASK (0x7 << 8)
#define RG_DPHY_RX_LD1_SEL_SHIFT 12
#define RG_DPHY_RX_LD1_SEL_MASK (0x7 << 12)
#define RG_DPHY_RX_LD2_SEL_SHIFT 16
#define RG_DPHY_RX_LD2_SEL_MASK (0x7 << 16)
#define RG_DPHY_RX_LD3_SEL_SHIFT 20
#define RG_DPHY_RX_LD3_SEL_MASK (0x7 << 20)
#define DPHY_RX_CK_DATA_MUX_EN_SHIFT 31
#define DPHY_RX_CK_DATA_MUX_EN_MASK (0x1 << 31)

#define DPHY_RX_HS_RX_EN_SW 0x0008
#define RG_DPHY_RX_LC0_HSRX_EN_SW_SHIFT 0
#define RG_DPHY_RX_LC0_HSRX_EN_SW_MASK (0x1 << 0)
#define RG_DPHY_RX_LC1_HSRX_EN_SW_SHIFT 1
#define RG_DPHY_RX_LC1_HSRX_EN_SW_MASK (0x1 << 1)
#define RG_CDPHY_RX_LD0_TRIO0_HSRX_EN_SW_SHIFT 8
#define RG_CDPHY_RX_LD0_TRIO0_HSRX_EN_SW_MASK (0x1 << 8)
#define RG_CDPHY_RX_LD1_TRIO1_HSRX_EN_SW_SHIFT 9
#define RG_CDPHY_RX_LD1_TRIO1_HSRX_EN_SW_MASK (0x1 << 9)
#define RG_CDPHY_RX_LD2_TRIO2_HSRX_EN_SW_SHIFT 10
#define RG_CDPHY_RX_LD2_TRIO2_HSRX_EN_SW_MASK (0x1 << 10)
#define RG_CDPHY_RX_LD2_TRIO3_HSRX_EN_SW_SHIFT 11
#define RG_CDPHY_RX_LD2_TRIO3_HSRX_EN_SW_MASK (0x1 << 11)

#define DPHY_RX_CLOCK_LANE0_HS_PARAMETER 0x0010
#define RG_DPHY_RX_LC0_HS_PREPARE_PARAMETER_SHIFT 0
#define RG_DPHY_RX_LC0_HS_PREPARE_PARAMETER_MASK (0xff << 0)
#define RG_DPHY_RX_LC0_HS_SETTLE_PARAMETER_SHIFT 16
#define RG_DPHY_RX_LC0_HS_SETTLE_PARAMETER_MASK (0xff << 16)
#define RG_DPHY_RX_LC0_HS_PREPARE_EN_SHIFT 28
#define RG_DPHY_RX_LC0_HS_PREPARE_EN_MASK (0x1 << 28)
#define RG_DPHY_RX_LC0_HS_OPTION_SHIFT 30
#define RG_DPHY_RX_LC0_HS_OPTION_MASK (0x1 << 30)

#define DPHY_RX_CLOCK_LANE1_HS_PARAMETER 0x0014
#define RG_DPHY_RX_LC1_HS_PREPARE_PARAMETER_SHIFT 0
#define RG_DPHY_RX_LC1_HS_PREPARE_PARAMETER_MASK (0xff << 0)
#define RG_DPHY_RX_LC1_HS_SETTLE_PARAMETER_SHIFT 16
#define RG_DPHY_RX_LC1_HS_SETTLE_PARAMETER_MASK (0xff << 16)
#define RG_DPHY_RX_LC1_HS_PREPARE_EN_SHIFT 28
#define RG_DPHY_RX_LC1_HS_PREPARE_EN_MASK (0x1 << 28)
#define RG_DPHY_RX_LC1_HS_OPTION_SHIFT 30
#define RG_DPHY_RX_LC1_HS_OPTION_MASK (0x1 << 30)

#define DPHY_RX_DATA_LANE0_HS_PARAMETER 0x0020
#define RG_CDPHY_RX_LD0_TRIO0_HS_PREPARE_PARAMETER_SHIFT 0
#define RG_CDPHY_RX_LD0_TRIO0_HS_PREPARE_PARAMETER_MASK (0xff << 0)
#define RG_DPHY_RX_LD0_HS_TRAIL_PARAMETER_SHIFT 8
#define RG_DPHY_RX_LD0_HS_TRAIL_PARAMETER_MASK (0xff << 8)
#define RG_CDPHY_RX_LD0_TRIO0_HS_SETTLE_PARAMETER_SHIFT 16
#define RG_CDPHY_RX_LD0_TRIO0_HS_SETTLE_PARAMETER_MASK (0xff << 16)
#define RG_CDPHY_RX_LD0_TRIO0_HS_PREPARE_EN_SHIFT 28
#define RG_CDPHY_RX_LD0_TRIO0_HS_PREPARE_EN_MASK (0x1 << 28)
#define RG_DPHY_RX_LD0_HS_TRAIL_EN_SHIFT 29
#define RG_DPHY_RX_LD0_HS_TRAIL_EN_MASK (0x1 << 29)

#define DPHY_RX_DATA_LANE1_HS_PARAMETER 0x0024
#define RG_CDPHY_RX_LD1_TRIO1_HS_PREPARE_PARAMETER_SHIFT 0
#define RG_CDPHY_RX_LD1_TRIO1_HS_PREPARE_PARAMETER_MASK (0xff << 0)
#define RG_DPHY_RX_LD1_HS_TRAIL_PARAMETER_SHIFT 8
#define RG_DPHY_RX_LD1_HS_TRAIL_PARAMETER_MASK (0xff << 8)
#define RG_CDPHY_RX_LD1_TRIO1_HS_SETTLE_PARAMETER_SHIFT 16
#define RG_CDPHY_RX_LD1_TRIO1_HS_SETTLE_PARAMETER_MASK (0xff << 16)
#define RG_CDPHY_RX_LD1_TRIO1_HS_PREPARE_EN_SHIFT 28
#define RG_CDPHY_RX_LD1_TRIO1_HS_PREPARE_EN_MASK (0x1 << 28)
#define RG_DPHY_RX_LD1_HS_TRAIL_EN_SHIFT 29
#define RG_DPHY_RX_LD1_HS_TRAIL_EN_MASK (0x1 << 29)

#define DPHY_RX_DATA_LANE2_HS_PARAMETER 0x0028
#define RG_CDPHY_RX_LD2_TRIO2_HS_PREPARE_PARAMETER_SHIFT 0
#define RG_CDPHY_RX_LD2_TRIO2_HS_PREPARE_PARAMETER_MASK (0xff << 0)
#define RG_DPHY_RX_LD2_HS_TRAIL_PARAMETER_SHIFT 8
#define RG_DPHY_RX_LD2_HS_TRAIL_PARAMETER_MASK (0xff << 8)
#define RG_CDPHY_RX_LD2_TRIO2_HS_SETTLE_PARAMETER_SHIFT 16
#define RG_CDPHY_RX_LD2_TRIO2_HS_SETTLE_PARAMETER_MASK (0xff << 16)
#define RG_CDPHY_RX_LD2_TRIO2_HS_PREPARE_EN_SHIFT 28
#define RG_CDPHY_RX_LD2_TRIO2_HS_PREPARE_EN_MASK (0x1 << 28)
#define RG_DPHY_RX_LD2_HS_TRAIL_EN_SHIFT 29
#define RG_DPHY_RX_LD2_HS_TRAIL_EN_MASK (0x1 << 29)

#define DPHY_RX_DATA_LANE3_HS_PARAMETER 0x002c
#define RG_CDPHY_RX_LD3_TRIO3_HS_PREPARE_PARAMETER_SHIFT 0
#define RG_CDPHY_RX_LD3_TRIO3_HS_PREPARE_PARAMETER_MASK (0xff << 0)
#define RG_DPHY_RX_LD3_HS_TRAIL_PARAMETER_SHIFT 8
#define RG_DPHY_RX_LD3_HS_TRAIL_PARAMETER_MASK (0xff << 8)
#define RG_CDPHY_RX_LD3_TRIO3_HS_SETTLE_PARAMETER_SHIFT 16
#define RG_CDPHY_RX_LD3_TRIO3_HS_SETTLE_PARAMETER_MASK (0xff << 16)
#define RG_CDPHY_RX_LD3_TRIO3_HS_PREPARE_EN_SHIFT 28
#define RG_CDPHY_RX_LD3_TRIO3_HS_PREPARE_EN_MASK (0x1 << 28)
#define RG_DPHY_RX_LD3_HS_TRAIL_EN_SHIFT 29
#define RG_DPHY_RX_LD3_HS_TRAIL_EN_MASK (0x1 << 29)

#define DPHY_RX_CLOCK_LANE_FSM 0x0030
#define RO_DPHY_RX_CL0_FSM_SHIFT 0
#define RO_DPHY_RX_CL0_FSM_MASK (0x3f << 0)
#define RO_DPHY_RX_CL1_FSM_SHIFT 8
#define RO_DPHY_RX_CL1_FSM_MASK (0x3f << 8)

#define DPHY_RX_DATA_LANE_FSM 0x0034
#define RO_DPHY_RX_DL0_FSM_SHIFT 0
#define RO_DPHY_RX_DL0_FSM_MASK (0xff << 0)
#define RO_DPHY_RX_DL1_FSM_SHIFT 8
#define RO_DPHY_RX_DL1_FSM_MASK (0xff << 8)
#define RO_DPHY_RX_DL2_FSM_SHIFT 16
#define RO_DPHY_RX_DL2_FSM_MASK (0xff << 16)
#define RO_DPHY_RX_DL3_FSM_SHIFT 24
#define RO_DPHY_RX_DL3_FSM_MASK (0xff << 24)

#define DPHY_RX_DATA_LANE_SYNC_DETECT_NORMAL 0x0040
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_NORM_SHIFT 0
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_NORM_MASK (0xffff << 0)
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_NORM_SHIFT 16
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_NORM_MASK (0xffff << 16)

#define DPHY_RX_DATA_LANE_SYNC_DETECT_DESKEW 0x0044
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_DESKEW_SHIFT 0
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_DESKEW_MASK (0xffff << 0)
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_DESKEW_SHIFT 16
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_DESKEW_MASK (0xffff << 16)

#define DPHY_RX_DATA_LANE_SYNC_DETECT_ALTCAL 0x0048
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_ALT_CAL_SHIFT 0
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_ALT_CAL_MASK (0xffff << 0)
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_ALT_CAL_SHIFT 16
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_ALT_CAL_MASK (0xffff << 16)

#define DPHY_RX_DATA_LANE_SYNC_DETECT_PRESEQ 0x004c
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_PRE_SEQ_SHIFT 0
#define RG_DPHY_RX_LD_SYNC_SEQ_PAT_PRE_SEQ_MASK (0xffff << 0)
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_PRE_SEQ_SHIFT 16
#define RG_DPHY_RX_LD_SYNC_SEQ_MASK_PRE_SEQ_MASK (0xffff << 16)

#define DPHY_RX_DESKEW_CTRL 0x0050
#define RG_DPHY_RX_DESKEW_INITIAL_SETUP_SHIFT 0
#define RG_DPHY_RX_DESKEW_INITIAL_SETUP_MASK (0xf << 0)
#define RG_DPHY_RX_DESKEW_OFFSET_SHIFT 4
#define RG_DPHY_RX_DESKEW_OFFSET_MASK (0xf << 4)
#define RG_DPHY_RX_DESKEW_EN_SHIFT 8
#define RG_DPHY_RX_DESKEW_EN_MASK (0x1 << 8)
#define RG_DPHY_RX_DESKEW_CODE_UNIT_SEL_SHIFT 9
#define RG_DPHY_RX_DESKEW_CODE_UNIT_SEL_MASK (0x3 << 9)
#define RG_DPHY_RX_DESKEW_HW_DELAY_APPLY_OPT_SHIFT 11
#define RG_DPHY_RX_DESKEW_HW_DELAY_APPLY_OPT_MASK (0x1 << 11)
#define RG_DPHY_RX_DESKEW_ACC_MODE_SHIFT 12
#define RG_DPHY_RX_DESKEW_ACC_MODE_MASK (0xf << 12)
#define RG_DPHY_RX_DESKEW_APPLY_MODE_SHIFT 16
#define RG_DPHY_RX_DESKEW_APPLY_MODE_MASK (0xf << 16)
#define RG_DPHY_RX_DESKEW_LENGTH_SHIFT 24
#define RG_DPHY_RX_DESKEW_LENGTH_MASK (0x3f << 24)
#define DPHY_RX_DESKEW_SW_RST_SHIFT 31
#define DPHY_RX_DESKEW_SW_RST_MASK (0x1 << 31)

#define DPHY_RX_DESKEW_TIMING_CTRL 0x0054
#define RG_DPHY_RX_DESKEW_SETUP_CNT_SHIFT 0
#define RG_DPHY_RX_DESKEW_SETUP_CNT_MASK (0xf << 0)
#define RG_DPHY_RX_DESKEW_HOLD_CNT_SHIFT 8
#define RG_DPHY_RX_DESKEW_HOLD_CNT_MASK (0xf << 8)
#define RG_DPHY_RX_DESKEW_DETECT_CNT_SHIFT 16
#define RG_DPHY_RX_DESKEW_DETECT_CNT_MASK (0x7f << 16)
#define RG_DPHY_RX_DESKEW_CMPLENGTH_SHIFT 24
#define RG_DPHY_RX_DESKEW_CMPLENGTH_MASK (0xf << 24)

#define DPHY_RX_DESKEW_LANE_SWAP 0x0058
#define RG_DPHY_RX_DESKEW_LANE0_SWAP_SHIFT 0
#define RG_DPHY_RX_DESKEW_LANE0_SWAP_MASK (0x3 << 0)
#define RG_DPHY_RX_DESKEW_LANE1_SWAP_SHIFT 2
#define RG_DPHY_RX_DESKEW_LANE1_SWAP_MASK (0x3 << 2)
#define RG_DPHY_RX_DESKEW_LANE2_SWAP_SHIFT 4
#define RG_DPHY_RX_DESKEW_LANE2_SWAP_MASK (0x3 << 4)
#define RG_DPHY_RX_DESKEW_LANE3_SWAP_SHIFT 6
#define RG_DPHY_RX_DESKEW_LANE3_SWAP_MASK (0x3 << 6)
#define RG_MIN_CODE_SHIFT 24
#define RG_MIN_CODE_MASK (0x7 << 24)
#define RG_MIN_CODE_EN_SHIFT 28
#define RG_MIN_CODE_EN_MASK (0x1 << 28)
#define RG_DBG_CLR_SHIFT 29
#define RG_DBG_CLR_MASK (0x1 << 29)
#define RG_APPLY_ONLY_1ST_PAT_SHIFT 30
#define RG_APPLY_ONLY_1ST_PAT_MASK (0x1 << 30)
#define RG_DBGST_OPT_SHIFT 31
#define RG_DBGST_OPT_MASK (0x1 << 31)

#define DPHY_RX_DESKEW_LANE0_CTRL 0x0060
#define DPHY_RX_DESKEW_L0_DELAY_EN_SHIFT 0
#define DPHY_RX_DESKEW_L0_DELAY_EN_MASK (0x1 << 0)
#define RG_DPHY_RX_DESKEW_L0_DELAY_APPLY_SHIFT 1
#define RG_DPHY_RX_DESKEW_L0_DELAY_APPLY_MASK (0x1 << 1)
#define RG_DPHY_RX_DESKEW_L0_DELAY_CODE_SHIFT 8
#define RG_DPHY_RX_DESKEW_L0_DELAY_CODE_MASK (0x3f << 8)
#define RG_DPHY_RX_DESKEW_L0_PERIODIC_SHIFT 16
#define RG_DPHY_RX_DESKEW_L0_PERIODIC_MASK (0x1 << 16)
#define RG_DPHY_RX_DESKEW_L0_PERIODIC_1DIR_ONLY_SHIFT 17
#define RG_DPHY_RX_DESKEW_L0_PERIODIC_1DIR_ONLY_MASK (0x1 << 17)
#define RG_DPHY_RX_DESKEW_L0_PERIODIC_DELAY_CODE_CNT_SHIFT 20
#define RG_DPHY_RX_DESKEW_L0_PERIODIC_DELAY_CODE_CNT_MASK (0xf << 20)

#define DPHY_RX_DESKEW_LANE1_CTRL 0x0064
#define DPHY_RX_DESKEW_L1_DELAY_EN_SHIFT 0
#define DPHY_RX_DESKEW_L1_DELAY_EN_MASK (0x1 << 0)
#define RG_DPHY_RX_DESKEW_L1_DELAY_APPLY_SHIFT 1
#define RG_DPHY_RX_DESKEW_L1_DELAY_APPLY_MASK (0x1 << 1)
#define RG_DPHY_RX_DESKEW_L1_DELAY_CODE_SHIFT 8
#define RG_DPHY_RX_DESKEW_L1_DELAY_CODE_MASK (0x3f << 8)
#define RG_DPHY_RX_DESKEW_L1_PERIODIC_SHIFT 16
#define RG_DPHY_RX_DESKEW_L1_PERIODIC_MASK (0x1 << 16)
#define RG_DPHY_RX_DESKEW_L1_PERIODIC_1DIR_ONLY_SHIFT 17
#define RG_DPHY_RX_DESKEW_L1_PERIODIC_1DIR_ONLY_MASK (0x1 << 17)
#define RG_DPHY_RX_DESKEW_L1_PERIODIC_DELAY_CODE_CNT_SHIFT 20
#define RG_DPHY_RX_DESKEW_L1_PERIODIC_DELAY_CODE_CNT_MASK (0xf << 20)

#define DPHY_RX_DESKEW_LANE2_CTRL 0x0068
#define DPHY_RX_DESKEW_L2_DELAY_EN_SHIFT 0
#define DPHY_RX_DESKEW_L2_DELAY_EN_MASK (0x1 << 0)
#define RG_DPHY_RX_DESKEW_L2_DELAY_APPLY_SHIFT 1
#define RG_DPHY_RX_DESKEW_L2_DELAY_APPLY_MASK (0x1 << 1)
#define RG_DPHY_RX_DESKEW_L2_DELAY_CODE_SHIFT 8
#define RG_DPHY_RX_DESKEW_L2_DELAY_CODE_MASK (0x3f << 8)
#define RG_DPHY_RX_DESKEW_L2_PERIODIC_SHIFT 16
#define RG_DPHY_RX_DESKEW_L2_PERIODIC_MASK (0x1 << 16)
#define RG_DPHY_RX_DESKEW_L2_PERIODIC_1DIR_ONLY_SHIFT 17
#define RG_DPHY_RX_DESKEW_L2_PERIODIC_1DIR_ONLY_MASK (0x1 << 17)
#define RG_DPHY_RX_DESKEW_L2_PERIODIC_DELAY_CODE_CNT_SHIFT 20
#define RG_DPHY_RX_DESKEW_L2_PERIODIC_DELAY_CODE_CNT_MASK (0xf << 20)

#define DPHY_RX_DESKEW_LANE3_CTRL 0x006c
#define DPHY_RX_DESKEW_L3_DELAY_EN_SHIFT 0
#define DPHY_RX_DESKEW_L3_DELAY_EN_MASK (0x1 << 0)
#define RG_DPHY_RX_DESKEW_L3_DELAY_APPLY_SHIFT 1
#define RG_DPHY_RX_DESKEW_L3_DELAY_APPLY_MASK (0x1 << 1)
#define RG_DPHY_RX_DESKEW_L3_DELAY_CODE_SHIFT 8
#define RG_DPHY_RX_DESKEW_L3_DELAY_CODE_MASK (0x3f << 8)
#define RG_DPHY_RX_DESKEW_L3_PERIODIC_SHIFT 16
#define RG_DPHY_RX_DESKEW_L3_PERIODIC_MASK (0x1 << 16)
#define RG_DPHY_RX_DESKEW_L3_PERIODIC_1DIR_ONLY_SHIFT 17
#define RG_DPHY_RX_DESKEW_L3_PERIODIC_1DIR_ONLY_MASK (0x1 << 17)
#define RG_DPHY_RX_DESKEW_L3_PERIODIC_DELAY_CODE_CNT_SHIFT 20
#define RG_DPHY_RX_DESKEW_L3_PERIODIC_DELAY_CODE_CNT_MASK (0xf << 20)

#define DPHY_RX_DESKEW_LANE0_DA_READ 0x0070
#define RO_DA_DPHY_L0_DELAY_EN_SHIFT 0
#define RO_DA_DPHY_L0_DELAY_EN_MASK (0x1 << 0)
#define RO_DA_DPHY_L0_DELAY_APPLY_SHIFT 1
#define RO_DA_DPHY_L0_DELAY_APPLY_MASK (0x1 << 1)
#define RO_DA_DPHY_L0_DELAY_CODE_SHIFT 8
#define RO_DA_DPHY_L0_DELAY_CODE_MASK (0x7f << 8)

#define DPHY_RX_DESKEW_LANE1_DA_READ 0x0074
#define RO_DA_DPHY_L1_DELAY_EN_SHIFT 0
#define RO_DA_DPHY_L1_DELAY_EN_MASK (0x1 << 0)
#define RO_DA_DPHY_L1_DELAY_APPLY_SHIFT 1
#define RO_DA_DPHY_L1_DELAY_APPLY_MASK (0x1 << 1)
#define RO_DA_DPHY_L0_DELAY_CODE_SHIFT 8
#define RO_DA_DPHY_L0_DELAY_CODE_MASK (0x7f << 8)

#define DPHY_RX_DESKEW_LANE2_DA_READ 0x0078
#define RO_DA_DPHY_L2_DELAY_EN_SHIFT 0
#define RO_DA_DPHY_L2_DELAY_EN_MASK (0x1 << 0)
#define RO_DA_DPHY_L2_DELAY_APPLY_SHIFT 1
#define RO_DA_DPHY_L2_DELAY_APPLY_MASK (0x1 << 1)
#define RO_DA_DPHY_L0_DELAY_CODE_SHIFT 8
#define RO_DA_DPHY_L0_DELAY_CODE_MASK (0x7f << 8)

#define DPHY_RX_DESKEW_LANE3_DA_READ 0x007c
#define RO_DA_DPHY_L3_DELAY_EN_SHIFT 0
#define RO_DA_DPHY_L3_DELAY_EN_MASK (0x1 << 0)
#define RO_DA_DPHY_L3_DELAY_APPLY_SHIFT 1
#define RO_DA_DPHY_L3_DELAY_APPLY_MASK (0x1 << 1)
#define RO_DA_DPHY_L0_DELAY_CODE_SHIFT 8
#define RO_DA_DPHY_L0_DELAY_CODE_MASK (0x7f << 8)

#define DPHY_RX_DESKEW_IRQ_EN 0x0080
#define RG_DPHY_RX_DESKEW_IRQ_EN_SHIFT 0
#define RG_DPHY_RX_DESKEW_IRQ_EN_MASK (0xffff << 0)
#define RG_DPHY_RX_DESKEW_IRQ_W1C_EN_SHIFT 31
#define RG_DPHY_RX_DESKEW_IRQ_W1C_EN_MASK (0x1 << 31)

#define DPHY_RX_DESKEW_IRQ_STATUS 0x0084
#define RO_DPHY_RX_DESKEW_IRQ_STATUS_SHIFT 0
#define RO_DPHY_RX_DESKEW_IRQ_STATUS_MASK (0xffff << 0)

#define DPHY_RX_IRQ_EN 0x0088
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L0_IRQ_EN_SHIFT 0
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L0_IRQ_EN_MASK (0x1 << 0)
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L1_IRQ_EN_SHIFT 1
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L1_IRQ_EN_MASK (0x1 << 1)
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L2_IRQ_EN_SHIFT 2
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L2_IRQ_EN_MASK (0x1 << 2)
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L3_IRQ_EN_SHIFT 3
#define RG_DPHY_RX_ERR_SOT_SYNC_HS_L3_IRQ_EN_MASK (0x1 << 3)
#define RG_DPHY_RX_IRQ_W1C_EN_SHIFT 31
#define RG_DPHY_RX_IRQ_W1C_EN_MASK (0x1 << 31)

#define DPHY_RX_IRQ_STATUS 0x008c
#define DPHY_RX_ERR_SOT_SYNC_HS_L0_IRQ_SHIFT 0
#define DPHY_RX_ERR_SOT_SYNC_HS_L0_IRQ_MASK (0x1 << 0)
#define DPHY_RX_ERR_SOT_SYNC_HS_L1_IRQ_SHIFT 1
#define DPHY_RX_ERR_SOT_SYNC_HS_L1_IRQ_MASK (0x1 << 1)
#define DPHY_RX_ERR_SOT_SYNC_HS_L2_IRQ_SHIFT 2
#define DPHY_RX_ERR_SOT_SYNC_HS_L2_IRQ_MASK (0x1 << 2)
#define DPHY_RX_ERR_SOT_SYNC_HS_L3_IRQ_SHIFT 3
#define DPHY_RX_ERR_SOT_SYNC_HS_L3_IRQ_MASK (0x1 << 3)

#define DPHY_RX_STATUS_0 0x00a0
#define RO_DPHY_RX_LD0_SYNC_SEQ_POS_NORM_SHIFT 0
#define RO_DPHY_RX_LD0_SYNC_SEQ_POS_NORM_MASK (0x3f << 0)
#define RO_DPHY_RX_LD1_SYNC_SEQ_POS_NORM_SHIFT 8
#define RO_DPHY_RX_LD1_SYNC_SEQ_POS_NORM_MASK (0x3f << 8)
#define RO_DPHY_RX_LD2_SYNC_SEQ_POS_NORM_SHIFT 16
#define RO_DPHY_RX_LD2_SYNC_SEQ_POS_NORM_MASK (0x3f << 16)
#define RO_DPHY_RX_LD3_SYNC_SEQ_POS_NORM_SHIFT 24
#define RO_DPHY_RX_LD3_SYNC_SEQ_POS_NORM_MASK (0x3f << 24)

#define DPHY_RX_STATUS_1 0x00a4
#define RO_DPHY_RX_LD0_SYNC_SEQ_POS_DESKEW_SHIFT 0
#define RO_DPHY_RX_LD0_SYNC_SEQ_POS_DESKEW_MASK (0x3f << 0)
#define RO_DPHY_RX_LD1_SYNC_SEQ_POS_DESKEW_SHIFT 8
#define RO_DPHY_RX_LD1_SYNC_SEQ_POS_DESKEW_MASK (0x3f << 8)
#define RO_DPHY_RX_LD2_SYNC_SEQ_POS_DESKEW_SHIFT 16
#define RO_DPHY_RX_LD2_SYNC_SEQ_POS_DESKEW_MASK (0x3f << 16)
#define RO_DPHY_RX_LD3_SYNC_SEQ_POS_DESKEW_SHIFT 24
#define RO_DPHY_RX_LD3_SYNC_SEQ_POS_DESKEW_MASK (0x3f << 24)

#define DPHY_RX_DESKEW_DBG_MUX 0x00e0
#define RG_DPHY_RX_DESKEW_DBG_MUX_SHIFT 0
#define RG_DPHY_RX_DESKEW_DBG_MUX_MASK (0xff << 0)

#define DPHY_RX_DESKEW_OUT 0x00e4
#define RG_DPHY_RX_DESKEW_DBG_OUT_SHIFT 0
#define RG_DPHY_RX_DESKEW_DBG_OUT_MASK (0xffffffff << 0)

#define DPHY_RX_SPARE0 0x00f0
#define RG_DPHY_RX_SPARE0_SHIFT 0
#define RG_DPHY_RX_SPARE0_MASK (0x3f << 0)
#define RG_POST_CNT_SHIFT 6
#define RG_POST_CNT_MASK (0x3f << 6)
#define RG_DPHY_RX_SPARE0_2_SHIFT 12
#define RG_DPHY_RX_SPARE0_2_MASK (0xfffff << 12)

#define DPHY_RX_SPARE1 0x00f4
#define RG_DPHY_RX_SPARE1_SHIFT 0
#define RG_DPHY_RX_SPARE1_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_ENABLE 0x0100
#define DPHY_RX_BIST_EN_LANE0_SHIFT 0
#define DPHY_RX_BIST_EN_LANE0_MASK (0x1 << 0)
#define DPHY_RX_BIST_EN_LANE1_SHIFT 1
#define DPHY_RX_BIST_EN_LANE1_MASK (0x1 << 1)
#define DPHY_RX_BIST_EN_LANE2_SHIFT 2
#define DPHY_RX_BIST_EN_LANE2_MASK (0x1 << 2)
#define DPHY_RX_BIST_EN_LANE3_SHIFT 3
#define DPHY_RX_BIST_EN_LANE3_MASK (0x1 << 3)
#define RG_PHY2MAC_CDPHY_GEN_EN_SHIFT 8
#define RG_PHY2MAC_CDPHY_GEN_EN_MASK (0x1 << 8)
#define RG_PHY2MAC_CDPHY_GEN_MODE_SHIFT 9
#define RG_PHY2MAC_CDPHY_GEN_MODE_MASK (0x1 << 9)
#define RG_PHY2MAC_CDPHY_GEN_SEL_SHIFT 10
#define RG_PHY2MAC_CDPHY_GEN_SEL_MASK (0x1 << 10)

#define DPHY_RX_BIST_STATUS 0x0104
#define RO_DPHY_RX_BIST_OK_LANE0_SHIFT 0
#define RO_DPHY_RX_BIST_OK_LANE0_MASK (0x1 << 0)
#define RO_DPHY_RX_BIST_OK_LANE1_SHIFT 1
#define RO_DPHY_RX_BIST_OK_LANE1_MASK (0x1 << 1)
#define RO_DPHY_RX_BIST_OK_LANE2_SHIFT 2
#define RO_DPHY_RX_BIST_OK_LANE2_MASK (0x1 << 2)
#define RO_DPHY_RX_BIST_OK_LANE3_SHIFT 3
#define RO_DPHY_RX_BIST_OK_LANE3_MASK (0x1 << 3)
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE0_SHIFT 8
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE0_MASK (0x1 << 8)
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE1_SHIFT 9
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE1_MASK (0x1 << 9)
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE2_SHIFT 10
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE2_MASK (0x1 << 10)
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE3_SHIFT 11
#define RO_DPHY_RX_BIST_HS_MODE_OK_LANE3_MASK (0x1 << 11)
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE0_SHIFT 16
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE0_MASK (0x1 << 16)
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE1_SHIFT 17
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE1_MASK (0x1 << 17)
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE2_SHIFT 18
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE2_MASK (0x1 << 18)
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE3_SHIFT 19
#define RO_DPHY_RX_BIST_LP_MODE_OK_LANE3_MASK (0x1 << 19)

#define DPHY_RX_BIST_CONFIG_0_LANE0 0x0110
#define RG_DPHY_RX_BIST_MODE_LANE0_SHIFT 0
#define RG_DPHY_RX_BIST_MODE_LANE0_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE0_SHIFT 2
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE0_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE0_SHIFT 4
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE0_MASK (0x7 << 4)
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE0_SHIFT 7
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE0_MASK (0x1 << 7)
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE0_SHIFT 8
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE0_MASK (0xff << 8)
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE0_H15B_SHIFT 16
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE0_H15B_MASK (0x7fff << 16)
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE0_SHIFT 31
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE0_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_1_LANE0 0x0114
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE0_SHIFT 0
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE0_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE0_SHIFT 2
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE0_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE0_SHIFT 4
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE0_MASK (0x3 << 4)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE0_SHIFT 6
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE0_MASK (0x3 << 6)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE0_SHIFT 8
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE0_MASK (0x3 << 8)
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE0_SHIFT 16
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE0_MASK (0x7 << 16)
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE0_SHIFT 31
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE0_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_2_LANE0 0x0118
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE0_L32B_SHIFT 0
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE0_L32B_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_LANE0 0x011c
#define RO_DPHY_RX_BIST_START_LANE0_SHIFT 0
#define RO_DPHY_RX_BIST_START_LANE0_MASK (0x1 << 0)
#define RO_DPHY_RX_BIST_HS_OK_LANE0_SHIFT 1
#define RO_DPHY_RX_BIST_HS_OK_LANE0_MASK (0x1 << 1)
#define RO_DPHY_RX_BIST_DATA_OK_LANE0_SHIFT 2
#define RO_DPHY_RX_BIST_DATA_OK_LANE0_MASK (0x1 << 2)
#define RO_DPHY_RX_BIST_FSM_OK_LANE0_SHIFT 3
#define RO_DPHY_RX_BIST_FSM_OK_LANE0_MASK (0x1 << 3)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE0_SHIFT 8
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE0_MASK (0x7 << 8)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE0_SHIFT 12
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE0_MASK (0x3 << 12)

#define DPHY_RX_BIST_CONFIG_0_LANE1 0x0120
#define RG_DPHY_RX_BIST_MODE_LANE1_SHIFT 0
#define RG_DPHY_RX_BIST_MODE_LANE1_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE1_SHIFT 2
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE1_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE1_SHIFT 4
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE1_MASK (0x7 << 4)
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE1_SHIFT 7
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE1_MASK (0x1 << 7)
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE1_SHIFT 8
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE1_MASK (0xff << 8)
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE1_H15B_SHIFT 16
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE1_H15B_MASK (0x7fff << 16)
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE1_SHIFT 31
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE1_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_1_LANE1 0x0124
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE1_SHIFT 0
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE1_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE1_SHIFT 2
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE1_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE1_SHIFT 4
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE1_MASK (0x3 << 4)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE1_SHIFT 6
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE1_MASK (0x3 << 6)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE1_SHIFT 8
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE1_MASK (0x3 << 8)
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE1_SHIFT 16
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE1_MASK (0x7 << 16)
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE1_SHIFT 31
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE1_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_2_LANE1 0x0128
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE1_L32B_SHIFT 0
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE1_L32B_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_LANE1 0x012c
#define RO_DPHY_RX_BIST_START_LANE1_SHIFT 0
#define RO_DPHY_RX_BIST_START_LANE1_MASK (0x1 << 0)
#define RO_DPHY_RX_BIST_HS_OK_LANE1_SHIFT 1
#define RO_DPHY_RX_BIST_HS_OK_LANE1_MASK (0x1 << 1)
#define RO_DPHY_RX_BIST_DATA_OK_LANE1_SHIFT 2
#define RO_DPHY_RX_BIST_DATA_OK_LANE1_MASK (0x1 << 2)
#define RO_DPHY_RX_BIST_FSM_OK_LANE1_SHIFT 3
#define RO_DPHY_RX_BIST_FSM_OK_LANE1_MASK (0x1 << 3)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE1_SHIFT 8
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE1_MASK (0x7 << 8)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE1_SHIFT 12
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE1_MASK (0x3 << 12)

#define DPHY_RX_BIST_CONFIG_0_LANE2 0x0130
#define RG_DPHY_RX_BIST_MODE_LANE2_SHIFT 0
#define RG_DPHY_RX_BIST_MODE_LANE2_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE2_SHIFT 2
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE2_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE2_SHIFT 4
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE2_MASK (0x7 << 4)
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE2_SHIFT 7
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE2_MASK (0x1 << 7)
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE2_SHIFT 8
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE2_MASK (0xff << 8)
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE2_H15B_SHIFT 16
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE2_H15B_MASK (0x7fff << 16)
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE2_SHIFT 31
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE2_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_1_LANE2 0x0134
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE2_SHIFT 0
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE2_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE2_SHIFT 2
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE2_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE2_SHIFT 4
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE2_MASK (0x3 << 4)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE2_SHIFT 6
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE2_MASK (0x3 << 6)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE2_SHIFT 8
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE2_MASK (0x3 << 8)
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE2_SHIFT 16
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE2_MASK (0x7 << 16)
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE2_SHIFT 31
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE2_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_2_LANE2 0x0138
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE2_L32B_SHIFT 0
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE2_L32B_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_LANE2 0x013c
#define RO_DPHY_RX_BIST_START_LANE2_SHIFT 0
#define RO_DPHY_RX_BIST_START_LANE2_MASK (0x1 << 0)
#define RO_DPHY_RX_BIST_HS_OK_LANE2_SHIFT 1
#define RO_DPHY_RX_BIST_HS_OK_LANE2_MASK (0x1 << 1)
#define RO_DPHY_RX_BIST_DATA_OK_LANE2_SHIFT 2
#define RO_DPHY_RX_BIST_DATA_OK_LANE2_MASK (0x1 << 2)
#define RO_DPHY_RX_BIST_FSM_OK_LANE2_SHIFT 3
#define RO_DPHY_RX_BIST_FSM_OK_LANE2_MASK (0x1 << 3)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE2_SHIFT 8
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE2_MASK (0x7 << 8)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE2_SHIFT 12
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE2_MASK (0x3 << 12)

#define DPHY_RX_BIST_CONFIG_0_LANE3 0x0140
#define RG_DPHY_RX_BIST_MODE_LANE3_SHIFT 0
#define RG_DPHY_RX_BIST_MODE_LANE3_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE3_SHIFT 2
#define RG_DPHY_RX_BIST_PRBS_OUTMODE_LANE3_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE3_SHIFT 4
#define RG_DPHY_RX_BIST_PRBS_PAT_SEL_LANE3_MASK (0x7 << 4)
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE3_SHIFT 7
#define RG_DPHY_RX_BIST_PRBS_REVERSE_LANE3_MASK (0x1 << 7)
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE3_SHIFT 8
#define RG_DPHY_RX_BIST_HS_RAN_PAT_MASK_N_LANE3_MASK (0xff << 8)
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE3_H15B_SHIFT 16
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE3_H15B_MASK (0x7fff << 16)
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE3_SHIFT 31
#define RG_DPHY_RX_BIST_HS_FIX_PAT_LANE3_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_1_LANE3 0x0144
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE3_SHIFT 0
#define RG_DPHY_RX_BIST_LP_MODE_SEQ0_LANE3_MASK (0x3 << 0)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE3_SHIFT 2
#define RG_DPHY_RX_BIST_LP_MODE_SEQ1_LANE3_MASK (0x3 << 2)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE3_SHIFT 4
#define RG_DPHY_RX_BIST_LP_MODE_SEQ2_LANE3_MASK (0x3 << 4)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE3_SHIFT 6
#define RG_DPHY_RX_BIST_LP_MODE_SEQ3_LANE3_MASK (0x3 << 6)
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE3_SHIFT 8
#define RG_DPHY_RX_BIST_LP_MODE_SEQ4_LANE3_MASK (0x3 << 8)
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE3_SHIFT 16
#define RG_DPHY_RX_BIST_LP_MODE_LENGTH_LANE3_MASK (0x7 << 16)
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE3_SHIFT 31
#define RG_DPHY_RX_BIST_HS_SYNC_DET_UNBLOCK_LANE3_MASK (0x1 << 31)

#define DPHY_RX_BIST_CONFIG_2_LANE3 0x0148
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE3_L32B_SHIFT 0
#define RG_DPHY_RX_BIST_HS_LENGTH_LANE3_L32B_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_LANE3 0x014c
#define RO_DPHY_RX_BIST_START_LANE3_SHIFT 0
#define RO_DPHY_RX_BIST_START_LANE3_MASK (0x1 << 0)
#define RO_DPHY_RX_BIST_HS_OK_LANE3_SHIFT 1
#define RO_DPHY_RX_BIST_HS_OK_LANE3_MASK (0x1 << 1)
#define RO_DPHY_RX_BIST_DATA_OK_LANE3_SHIFT 2
#define RO_DPHY_RX_BIST_DATA_OK_LANE3_MASK (0x1 << 2)
#define RO_DPHY_RX_BIST_FSM_OK_LANE3_SHIFT 3
#define RO_DPHY_RX_BIST_FSM_OK_LANE3_MASK (0x1 << 3)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE3_SHIFT 8
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_NUMBER_LANE3_MASK (0x7 << 8)
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE3_SHIFT 12
#define RO_DPHY_RX_BIST_LP_FAIL_SEQ_LANE3_MASK (0x3 << 12)

#define DPHY_RX_BIST_STATUS_WORD_CNT_LANE0 0x0150
#define RO_DPHY_RX_BIST_WORD_CNT_LANE0_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_LANE0_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_H_LANE0 0x0154
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE0_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE0_MASK (0x7fff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_LANE1 0x0158
#define RO_DPHY_RX_BIST_WORD_CNT_LANE1_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_LANE1_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_H_LANE1 0x015c
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE1_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE1_MASK (0x7fff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_LANE2 0x0160
#define RO_DPHY_RX_BIST_WORD_CNT_LANE2_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_LANE2_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_H_LANE2 0x0164
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE2_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE2_MASK (0x7fff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_LANE3 0x0168
#define RO_DPHY_RX_BIST_WORD_CNT_LANE3_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_LANE3_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_CNT_H_LANE3 0x016c
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE3_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_CNT_H_LANE3_MASK (0x7fff << 0)

#define DPHY_RX_BIST_STATUS_WORD_ERR_CNT_LANE0 0x0170
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE0_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE0_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_ERR_CNT_LANE1 0x0174
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE1_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE1_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_ERR_CNT_LANE2 0x0178
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE2_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE2_MASK (0xffffffff << 0)

#define DPHY_RX_BIST_STATUS_WORD_ERR_CNT_LANE3 0x017c
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE3_SHIFT 0
#define RO_DPHY_RX_BIST_WORD_ERR_CNT_LANE3_MASK (0xffffffff << 0)

#define DPHY_DPHYV21_CTRL 0x0180
#define RG_DPHY_CAL_EN_SHIFT 0
#define RG_DPHY_CAL_EN_MASK (0x1 << 0)
#define RG_DPHY_PREAMBLE_EN_SHIFT 1
#define RG_DPHY_PREAMBLE_EN_MASK (0x1 << 1)
#define RG_HSIDLE_EN_SHIFT 2
#define RG_HSIDLE_EN_MASK (0x1 << 2)
#define RG_DPHY_ALP_EN_SHIFT 4
#define RG_DPHY_ALP_EN_MASK (0x1 << 4)
#define RG_DPHY_ALP_EN_SEL_SHIFT 5
#define RG_DPHY_ALP_EN_SEL_MASK (0x1 << 5)
#define RG_DPHYALP_TRAIL_CNT_SHIFT 8
#define RG_DPHYALP_TRAIL_CNT_MASK (0xff << 8)
#define RG_DPHYALP_PKT_END_CNT_SHIFT 16
#define RG_DPHYALP_PKT_END_CNT_MASK (0xff << 16)
#define RG_DPHYALP_SETTLE_CNT_SHIFT 24
#define RG_DPHYALP_SETTLE_CNT_MASK (0xff << 24)

#define DPHY_PRBS_SEED 0x0184
#define CSR_RLRN_PRBS_SEED_SHIFT 0
#define CSR_RLRN_PRBS_SEED_MASK (0xffffffff << 0)

#define DPHY_HS_IDLE_CNT 0x0188
#define RG_CK_DET_BYTE_CK_DIV_SHIFT 0
#define RG_CK_DET_BYTE_CK_DIV_MASK (0xff << 0)
#define RG_CK_DET_CK_CNT_SHIFT 8
#define RG_CK_DET_CK_CNT_MASK (0xff << 8)
#define RG_HSRC_EN_MASK_CNT_SHIFT 16
#define RG_HSRC_EN_MASK_CNT_MASK (0x3f << 16)
#define RG_DIV_CK_DET_SEL_SHIFT 24
#define RG_DIV_CK_DET_SEL_MASK (0x1 << 24)

#define DPHY_DFT_CLR 0x018c
#define RG_DPHY_ERROR_CMP_CLR_LANE0_SHIFT 0
#define RG_DPHY_ERROR_CMP_CLR_LANE0_MASK (0x1 << 0)
#define RG_DPHY_ERROR_CMP_CLR_LANE1_SHIFT 1
#define RG_DPHY_ERROR_CMP_CLR_LANE1_MASK (0x1 << 1)
#define RG_DPHY_ERROR_CMP_CLR_LANE2_SHIFT 2
#define RG_DPHY_ERROR_CMP_CLR_LANE2_MASK (0x1 << 2)
#define RG_DPHY_ERROR_CMP_CLR_LANE3_SHIFT 3
#define RG_DPHY_ERROR_CMP_CLR_LANE3_MASK (0x1 << 3)
#define RG_DPHY_LP00_2_SYNC_CODE_CLR_SHIFT 4
#define RG_DPHY_LP00_2_SYNC_CODE_CLR_MASK (0x1 << 4)

#define DPHY_ALT_CAL_CTRL_LANE0 0x0190
#define RG_ALT_CAL_MODE_LANE0_SHIFT 0
#define RG_ALT_CAL_MODE_LANE0_MASK (0x3f << 0)

#define DPHY_ALT_CAL_WORD_CNT0_LANE0 0x0194
#define RG_ALT_CAL_WORD_CNT1_LANE0_SHIFT 0
#define RG_ALT_CAL_WORD_CNT1_LANE0_MASK (0xffff << 0)
#define DPHY_ALT_CAL_WORD_CNT0_LANE0_RO_ALT_CAL_ERR_CNT_LANE0_SHIFT 16
#define DPHY_ALT_CAL_WORD_CNT0_LANE0_RO_ALT_CAL_ERR_CNT_LANE0_MASK (0xffff << 16)

#define DPHY_ALT_CAL_WORD_CNT1_LANE0 0x0198
#define RG_ALT_CAL_WORD_CNT0_LANE0_SHIFT 0
#define RG_ALT_CAL_WORD_CNT0_LANE0_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_ERR_CNT_LANE0 0x019c
#define RO_ALT_CAL_ERR_CNT1_LANE0_SHIFT 0
#define RO_ALT_CAL_ERR_CNT1_LANE0_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_CTRL_LANE1 0x01a0
#define RG_ALT_CAL_MODE_LANE1_SHIFT 0
#define RG_ALT_CAL_MODE_LANE1_MASK (0x3f << 0)

#define DPHY_ALT_CAL_WORD_CNT0_LANE1 0x01a4
#define RG_ALT_CAL_WORD_CNT1_LANE1_SHIFT 0
#define RG_ALT_CAL_WORD_CNT1_LANE1_MASK (0xffff << 0)
#define DPHY_ALT_CAL_WORD_CNT0_LANE1_RO_ALT_CAL_ERR_CNT_LANE1_SHIFT 16
#define DPHY_ALT_CAL_WORD_CNT0_LANE1_RO_ALT_CAL_ERR_CNT_LANE1_MASK (0xffff << 16)

#define DPHY_ALT_CAL_WORD_CNT1_LANE1 0x01a8
#define RG_ALT_CAL_WORD_CNT0_LANE1_SHIFT 0
#define RG_ALT_CAL_WORD_CNT0_LANE1_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_ERR_CNT_LANE1 0x01ac
#define DPHY_ALT_CAL_ERR_CNT_LANE1_RO_ALT_CAL_ERR_CNT_LANE1_SHIFT 0
#define DPHY_ALT_CAL_ERR_CNT_LANE1_RO_ALT_CAL_ERR_CNT_LANE1_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_CTRL_LANE2 0x01b0
#define RG_ALT_CAL_MODE_LANE2_SHIFT 0
#define RG_ALT_CAL_MODE_LANE2_MASK (0x3f << 0)

#define DPHY_ALT_CAL_WORD_CNT0_LANE2 0x01b4
#define RG_ALT_CAL_WORD_CNT0_LANE2_SHIFT 0
#define RG_ALT_CAL_WORD_CNT0_LANE2_MASK (0xffff << 0)
#define DPHY_ALT_CAL_WORD_CNT0_LANE2_RO_ALT_CAL_ERR_CNT_LANE2_SHIFT 16
#define DPHY_ALT_CAL_WORD_CNT0_LANE2_RO_ALT_CAL_ERR_CNT_LANE2_MASK (0xffff << 16)

#define DPHY_ALT_CAL_WORD_CNT1_LANE2 0x01b8
#define RG_ALT_CAL_WORD_CNT1_LANE2_SHIFT 0
#define RG_ALT_CAL_WORD_CNT1_LANE2_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_ERR_CNT_LANE2 0x01bc
#define DPHY_ALT_CAL_ERR_CNT_LANE2_RO_ALT_CAL_ERR_CNT_LANE2_SHIFT 0
#define DPHY_ALT_CAL_ERR_CNT_LANE2_RO_ALT_CAL_ERR_CNT_LANE2_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_CTRL_LANE3 0x01c0
#define RG_ALT_CAL_MODE_LANE3_SHIFT 0
#define RG_ALT_CAL_MODE_LANE3_MASK (0x3f << 0)

#define DPHY_ALT_CAL_WORD_CNT0_LANE3 0x01c4
#define RG_ALT_CAL_WORD_CNT0_LANE3_SHIFT 0
#define RG_ALT_CAL_WORD_CNT0_LANE3_MASK (0xffff << 0)
#define DPHY_ALT_CAL_WORD_CNT0_LANE3_RO_ALT_CAL_ERR_CNT_LANE3_SHIFT 16
#define DPHY_ALT_CAL_WORD_CNT0_LANE3_RO_ALT_CAL_ERR_CNT_LANE3_MASK (0xffff << 16)

#define DPHY_ALT_CAL_WORD_CNT1_LANE3 0x01c8
#define RG_ALT_CAL_WORD_CNT1_LANE3_SHIFT 0
#define RG_ALT_CAL_WORD_CNT1_LANE3_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_ERR_CNT_LANE3 0x01cc
#define DPHY_ALT_CAL_ERR_CNT_LANE3_RO_ALT_CAL_ERR_CNT_LANE3_SHIFT 0
#define DPHY_ALT_CAL_ERR_CNT_LANE3_RO_ALT_CAL_ERR_CNT_LANE3_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_CNT_LANE0 0x01d0
#define RG_DPHY_PRBS_BURST_CNT_LANE0_SHIFT 0
#define RG_DPHY_PRBS_BURST_CNT_LANE0_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_ERRCNT_LANE0 0x01d4
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE0_SHIFT 0
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE0_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_CNT_LANE1 0x01d8
#define RG_DPHY_PRBS_BURST_CNT_LANE1_SHIFT 0
#define RG_DPHY_PRBS_BURST_CNT_LANE1_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_ERRCNT_LANE1 0x01dc
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE1_SHIFT 0
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE1_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_CNT_LANE2 0x01e0
#define RG_DPHY_PRBS_BURST_CNT_LANE2_SHIFT 0
#define RG_DPHY_PRBS_BURST_CNT_LANE2_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_ERRCNT_LANE2 0x01e4
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE2_SHIFT 0
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE2_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_CNT_LANE3 0x01e8
#define RG_DPHY_PRBS_BURST_CNT_LANE3_SHIFT 0
#define RG_DPHY_PRBS_BURST_CNT_LANE3_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_BURST_ERRCNT_LANE3 0x01ec
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE3_SHIFT 0
#define RO_DPHY_PRBS_BURST_ERR_CNT_LANE3_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_PKT_CNT0 0x01f0
#define RG_ALT_CAL_PKT_CNT0_SHIFT 0
#define RG_ALT_CAL_PKT_CNT0_MASK (0xffffffff << 0)

#define DPHY_ALT_CAL_PKT_CNT1 0x01f4
#define RG_ALT_CAL_PKT_CNT1_SHIFT 0
#define RG_ALT_CAL_PKT_CNT1_MASK (0xffff << 0)

#define DPHY_DFT_DATA_SEL 0x0210
#define DPHY_DFT_DTAT_SEL_SHIFT 0
#define DPHY_DFT_DTAT_SEL_MASK (0x3 << 0)

#define DPHY_HSYNC_DATA 0x0214
#define RO_DPHY_SYNC_DATA_SHIFT 0
#define RO_DPHY_SYNC_DATA_MASK (0xffffffff << 0)

#define DPHY_ERR_DATA 0x0218
#define RO_DPHY_ERR_DATA_SHIFT 0
#define RO_DPHY_ERR_DATA_MASK (0xffffffff << 0)

#define DPHY_LP00_2_SYNCCODE 0x021c
#define RO_LP00_2_SYNC_CODE_MAX_SHIFT 0
#define RO_LP00_2_SYNC_CODE_MAX_MASK (0xffff << 0)
#define RO_LP00_2_SYNC_CODE_MIN_SHIFT 16
#define RO_LP00_2_SYNC_CODE_MIN_MASK (0xffff << 16)

#define DPHY_HSYNC_DATA0 0x0220
#define RO_DPHY_SYNC_DATA_SHIFT 0
#define RO_DPHY_SYNC_DATA_MASK (0xffffffff << 0)

#define DPHY_HSYNC_DATA1 0x0224
#define RO_DPHY_SYNC_DATA_SHIFT 0
#define RO_DPHY_SYNC_DATA_MASK (0xffffffff << 0)

#define DPHY_HSYNC_DATA2 0x0228
#define RO_DPHY_SYNC_DATA_SHIFT 0
#define RO_DPHY_SYNC_DATA_MASK (0xffffffff << 0)

#define DPHY_HSYNC_DATA3 0x022c
#define RO_DPHY_SYNC_DATA_SHIFT 0
#define RO_DPHY_SYNC_DATA_MASK (0xffffffff << 0)

#define DPHY_ERR_DATA0 0x0230
#define RO_DPHY_ERR_DATA_SHIFT 0
#define RO_DPHY_ERR_DATA_MASK (0xffffffff << 0)

#define DPHY_ERR_DATA1 0x0234
#define RO_DPHY_ERR_DATA_SHIFT 0
#define RO_DPHY_ERR_DATA_MASK (0xffffffff << 0)

#define DPHY_ERR_DATA2 0x0238
#define RO_DPHY_ERR_DATA_SHIFT 0
#define RO_DPHY_ERR_DATA_MASK (0xffffffff << 0)

#define DPHY_ERR_DATA3 0x023c
#define RO_DPHY_ERR_DATA_SHIFT 0
#define RO_DPHY_ERR_DATA_MASK (0xffffffff << 0)

#define DPHY_RX_STATE_CHK_EN 0x0260
#define DPHY_RX_STATE_CHK_EN_LANE0_SHIFT 0
#define DPHY_RX_STATE_CHK_EN_LANE0_MASK (0x1 << 0)
#define DPHY_RX_STATE_CHK_EN_LANE1_SHIFT 1
#define DPHY_RX_STATE_CHK_EN_LANE1_MASK (0x1 << 1)
#define DPHY_RX_STATE_CHK_EN_LANE2_SHIFT 2
#define DPHY_RX_STATE_CHK_EN_LANE2_MASK (0x1 << 2)
#define DPHY_RX_STATE_CHK_EN_LANE3_SHIFT 3
#define DPHY_RX_STATE_CHK_EN_LANE3_MASK (0x1 << 3)

#define DPHY_RX_STATE_CHK_TIMER 0x0264
#define RG_DPHY_RX_STATE_CHK_RX_TIMER_CNT_SHIFT 0
#define RG_DPHY_RX_STATE_CHK_RX_TIMER_CNT_MASK (0xffffffff << 0)

#define DPHY_RX_STATE_CHK_STATUS_LANE0 0x0270
#define RO_DPHY_RX_STATE_CHK_ERR_LANE0_SHIFT 0
#define RO_DPHY_RX_STATE_CHK_ERR_LANE0_MASK (0x1 << 0)
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE0_SHIFT 4
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE0_MASK (0x7 << 4)
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE0_SHIFT 16
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE0_MASK (0x7 << 16)
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE0_SHIFT 20
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE0_MASK (0x7 << 20)
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE0_SHIFT 24
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE0_MASK (0x7 << 24)
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE0_SHIFT 28
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE0_MASK (0x7 << 28)

#define DPHY_RX_STATE_CHK_STATUS_LANE1 0x0274
#define RO_DPHY_RX_STATE_CHK_ERR_LANE1_SHIFT 0
#define RO_DPHY_RX_STATE_CHK_ERR_LANE1_MASK (0x1 << 0)
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE1_SHIFT 4
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE1_MASK (0x7 << 4)
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE1_SHIFT 16
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE1_MASK (0x7 << 16)
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE1_SHIFT 20
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE1_MASK (0x7 << 20)
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE1_SHIFT 24
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE1_MASK (0x7 << 24)
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE1_SHIFT 28
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE1_MASK (0x7 << 28)

#define DPHY_RX_STATE_CHK_STATUS_LANE2 0x0278
#define RO_DPHY_RX_STATE_CHK_ERR_LANE2_SHIFT 0
#define RO_DPHY_RX_STATE_CHK_ERR_LANE2_MASK (0x1 << 0)
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE2_SHIFT 4
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE2_MASK (0x7 << 4)
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE2_SHIFT 16
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE2_MASK (0x7 << 16)
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE2_SHIFT 20
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE2_MASK (0x7 << 20)
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE2_SHIFT 24
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE2_MASK (0x7 << 24)
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE2_SHIFT 28
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE2_MASK (0x7 << 28)

#define DPHY_RX_STATE_CHK_STATUS_LANE3 0x027c
#define RO_DPHY_RX_STATE_CHK_ERR_LANE3_SHIFT 0
#define RO_DPHY_RX_STATE_CHK_ERR_LANE3_MASK (0x1 << 0)
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE3_SHIFT 4
#define RO_DPHY_RX_STATE_CHK_ERR_CNT_LANE3_MASK (0x7 << 4)
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE3_SHIFT 16
#define DPHY_RX_STATE_CHK_FAIL_SEQ0_LANE3_MASK (0x7 << 16)
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE3_SHIFT 20
#define DPHY_RX_STATE_CHK_FAIL_SEQ1_LANE3_MASK (0x7 << 20)
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE3_SHIFT 24
#define DPHY_RX_STATE_CHK_FAIL_SEQ2_LANE3_MASK (0x7 << 24)
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE3_SHIFT 28
#define DPHY_RX_STATE_CHK_FAIL_SEQ3_LANE3_MASK (0x7 << 28)

#define CDPHY_DEBUG_PORT_SELECT 0x0280
#define RG_CSI_CDPHY_DBG_PORT_SEL_SHIFT 0
#define RG_CSI_CDPHY_DBG_PORT_SEL_MASK (0xffffffff << 0)

#define CDPHY_DEBUG_MODE_SELECT 0x0284
#define RG_CSI_CDPHY_DBG_MOD_SEL_SHIFT 0
#define RG_CSI_CDPHY_DBG_MOD_SEL_MASK (0xffff << 0)

#define CDPHY_DEBUG_OUT_READ 0x0288
#define RO_CSI_CDPHY_DBG_OUT_READ_SHIFT 0
#define RO_CSI_CDPHY_DBG_OUT_READ_MASK (0xffffffff << 0)

#define DPHY_RX_INIT 0x028c
#define RG_CSI2_TINIT_CNT_SHIFT 0
#define RG_CSI2_TINIT_CNT_MASK (0xfffff << 0)
#define RG_CSI2_TINIT_CNT_EN_SHIFT 31
#define RG_CSI2_TINIT_CNT_EN_MASK (0x1 << 31)

#endif
