// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 MediaTek Inc.
 * Author: Wen Cai <wen.cai@mediatek.com>
 *
 */

#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include "mt8532-asrc-reg.h"
#include "mt8532-asrc-clk.h"

static struct clk *asrc_clocks[MT8532_CLK_NUM];
static unsigned long asrc_clocks_rate[MT8532_CLK_NUM] = {0, 0, 0};
static const char *aud_clks_8532[MT8532_CLK_NUM] = {
	[MT8532_CLK_FASM_H] = "asmh_sel",
	[MT8532_CLK_APLL1] = "apll1",
	[MT8532_CLK_APLL2] = "apll2"
};

int asrc_init_clock(struct device *dev)
{
	int i = 0;

	for (i = 0; i < (int)MT8532_CLK_NUM; i++) {
		asrc_clocks[i] = devm_clk_get(dev, aud_clks_8532[i]);
		if (IS_ERR(aud_clks_8532[i])) {
			pr_debug("%s devm_clk_get %s fail\n",
			__func__, aud_clks_8532[i]);
			return (int)PTR_ERR(aud_clks_8532[i]);
		}
		asrc_clocks_rate[i] = clk_get_rate(asrc_clocks[i]);
	}

	return 0;
}

int asrc_turn_on_asrc_clock(void)
{
	int ret = 0;

	/* Set Mux */
	ret = clk_prepare_enable(asrc_clocks[MT8532_CLK_FASM_H]);
	if (ret != 0) {
		pr_debug("%s clk_prepare_enable %s fail %d\n",
			__func__, aud_clks_8532[MT8532_CLK_FASM_H], ret);
		clk_disable_unprepare(asrc_clocks[MT8532_CLK_FASM_H]);
	}
	// has set default parent in dtsi. so dose not call clk_set_parent.

	return ret;
}


void asrc_turn_off_asrc_clock(void)
{
	clk_disable_unprepare(asrc_clocks[MT8532_CLK_FASM_H]);
}


unsigned long asrc_get_clock_rate(enum audio_system_clock_type_8532 clk_type)
{
	if (clk_type >= MT8532_CLK_NUM)
		return 0;
	if (asrc_clocks_rate[clk_type] != 0)
		return asrc_clocks_rate[clk_type];

	asrc_clocks_rate[clk_type] = clk_get_rate(asrc_clocks[clk_type]);

	return asrc_clocks_rate[clk_type];
}

