/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2020 MediaTek Inc.
 * Author: Shan Lin <shan.lin@mediatek.com>
 *
 */

#ifndef _DT_BINDINGS_GCE_MT8696_H
#define _DT_BINDINGS_GCE_MT8696_H

#define CMDQ_NO_TIMEOUT				0xffffffff

/* GCE HW thread priority */
#define CMDQ_THR_PRIO_LOWEST			0
#define CMDQ_THR_PRIO_1				1
#define CMDQ_THR_PRIO_2				2
#define CMDQ_THR_PRIO_3				3
#define CMDQ_THR_PRIO_4				4
#define CMDQ_THR_PRIO_5				5
#define CMDQ_THR_PRIO_6				6
#define CMDQ_THR_PRIO_HIGHEST			7


/* GCE SUBSYS */
/* no subsys feature supported in MT8696 */

/* GCE HW EVENT */
/* MMSYS EVENT */
#define CMDQ_EVENT_M_VDO_MAIN_SOF			0
#define CMDQ_EVENT_M_VDO_AUX_SOF			1
#define CMDQ_EVENT_M_FE_FIFO_SOF			2
#define CMDQ_EVENT_M_FILM_GRAIN_SOF_0			3
#define CMDQ_EVENT_M_FILM_GRAIN_SOF_1			4
#define CMDQ_EVENT_M_FILM_GRAIN_SOF_2			5
#define CMDQ_EVENT_M_DOLBY_FE_SOF			6
#define CMDQ_EVENT_S_VDO_MAIN_SOF			7
#define CMDQ_EVENT_S_VDO_AUX_SOF			8
#define CMDQ_EVENT_S_FE_FIFO_SOF			9
#define CMDQ_EVENT_S_FILM_GRAIN_SOF_0			10
#define CMDQ_EVENT_S_FILM_GRAIN_SOF_1			11
#define CMDQ_EVENT_S_FILM_GRAIN_SOF_2			12
#define CMDQ_EVENT_S_DOLBY_FE_SOF			13
#define CMDQ_EVENT_UHD_OSD_SOF				14
#define CMDQ_EVENT_UHD_FE_FIFO_SOF			15
#define CMDQ_EVENT_UHD_DOLBY_FE_SOF			16
#define CMDQ_EVENT_FHD_OSD_SOF				17
#define CMDQ_EVENT_FHD_FE_FIFO_SOF			18
#define CMDQ_EVENT_FHD_DOLBY_FE_SOF			19
#define CMDQ_EVENT_DISP_MIX_SOF				20
#define CMDQ_EVENT_DOLBY_BE_SOF				21
#define CMDQ_EVENT_BE_FIFO_SOF				22
#define CMDQ_EVENT_DISP_MENU_LOAD_SOF			23
#define CMDQ_EVENT_MMSYS_MENU_LOAD_SOF			24
#define CMDQ_EVENT_VM_SOF				25
#define CMDQ_EVENT_M_R2R_SOF				26
#define CMDQ_EVENT_M_FILM_GRAIN_SOF_3			27
#define CMDQ_EVENT_M_FILM_GRAIN_SOF_4			28
#define CMDQ_EVENT_S_FILM_GRAIN_SOF_3			29
#define CMDQ_EVENT_S_FILM_GRAIN_SOF_4			30
#define CMDQ_EVENT_FMT_AUX0_IRQ				32
#define CMDQ_EVENT_FMT_AUX1_IRQ				33
#define CMDQ_EVENT_FMT_AUX2_IRQ				34
#define CMDQ_EVENT_FMT_AUX3_IRQ				35
#define CMDQ_EVENT_SCRAMBLE_CLIENT_TRIG			36
#define CMDQ_EVENT_FHD_HDR_GFX_DM_AUTOD_TRIG		37
#define CMDQ_EVENT_FHD_HDR_GFX_THDR_AUTOD_TRIG		38
#define CMDQ_EVENT_UHD_HDR_GFX_THDR_AUTOD_TRIG		39
#define CMDQ_EVENT_UHD_HDR_GFX_DM_AUTOD_TRIG		40
#define CMDQ_EVENT_HDMI_METADATA_IRQ_B			45
#define CMDQ_EVENT_VIDEO_IN_IRQ_B			46
#define CMDQ_EVENT_W2D_IRQ_B				47
#define CMDQ_EVENT_VIDEO_MARK_IRQ_B			48
#define CMDQ_EVENT_FHD_OSD_UNDER_RUN_IRQ_B		49
#define CMDQ_EVENT_FHD_OSD_FRAME_START_IRQ_B		50
#define CMDQ_EVENT_FHD_OSD_FRAME_END_IRQ_B		51
#define CMDQ_EVENT_FHD_OSD_IRQ_B			52
#define CMDQ_EVENT_FHD_OSD_DIV_OVFL_IRQ_B		53
#define CMDQ_EVENT_UHD_GFX_FE_FIFO_IRQ_B		54
#define CMDQ_EVENT_UHD_HDR_GFX_FE_IRQ_B			55
#define CMDQ_EVENT_FHD_OSD_FBDC_IRQ_B			56
#define CMDQ_EVENT_LARB0_IRQ_B				57
#define CMDQ_EVENT_OSD_UHD_DUMMY_IRQ_B			58
#define CMDQ_EVENT_OSD2_UNDER_RUN_IRQ_B			59
#define CMDQ_EVENT_OSD2_FRAME_START_IRQ_B		60
#define CMDQ_EVENT_OSD2_FRAME_END_IRQ_B			61
#define CMDQ_EVENT_OSD2_IRQ_B				62
#define CMDQ_EVENT_OSD2_DIV_OVFL_IRQ_B			63
#define CMDQ_EVENT_FHD_GFX_FE_FIFO_IRQ_B		64
#define CMDQ_EVENT_FHD_HDR_GFX_FE_IRQ_B			65
#define CMDQ_EVENT_OSD2_FBDC_IRQ_B			66
#define CMDQ_EVENT_LARB4_IRQ_B				67
#define CMDQ_EVENT_VDO_BE_IRQ_B				68
#define CMDQ_EVENT_VDO_BE_FIFO_FRAME_DONE_IRQ		69
#define CMDQ_EVENT_VSYNC_IRQ_B				70
#define CMDQ_EVENT_VSYNC_ACT_STA_IRQ_B			71
#define CMDQ_EVENT_VSYNC_ACT_END_IRQ_B			72
#define CMDQ_EVENT_FMT_INT0_IRQ_B			73
#define CMDQ_EVENT_FMT_INT1_IRQ_B			74
#define CMDQ_EVENT_FMT_INT2_IRQ_B			75
#define CMDQ_EVENT_FMT_INT3_IRQ_B			76
#define CMDQ_EVENT_FMT_SOF_MERGE_IRQ_B			77
#define CMDQ_EVENT_DISP_MIX_IRQ_B			78
#define CMDQ_EVENT_FMT_DUMMY0_IRQ_B			79
#define CMDQ_EVENT_VDO_BE_FIFO_RDY2DE_IRQ_B		80
#define CMDQ_EVENT_XIU_TIMEOUT_INT_B			81
#define CMDQ_EVENT_SC_ERROR_RESP_INT_B			82
#define CMDQ_EVENT_DYN_SCL_INT_B			83
#define CMDQ_EVENT_MMSYS_DUMMY2_IRQ_B			84
#define CMDQ_EVENT_MMSYS_DUMMY1_IRQ_B			85
#define CMDQ_EVENT_MMSYS_DUMMY0_IRQ_B			86
#define CMDQ_EVENT_HDMI_TX_EVENT			87
#define CMDQ_EVENT_DISP_MIXER_FRAME_DONE		100

/* DISP EVENT */
#define CMDQ_EVENT_DISP3_END_IRQ_B			128
#define CMDQ_EVENT_VDO3_UNDER_RUN_IRQ_B			129
#define CMDQ_EVENT_DISPFMT3_VSYNC_IRQ_B			130
#define CMDQ_EVENT_SMI_LARB6_IRQ_B			131
#define CMDQ_EVENT_SMI_LARB5_IRQ_B			132
#define CMDQ_EVENT_R2R_IRQ_B				133
#define CMDQ_EVENT_M_VDO_FE_FIFO_IRQ_B			134
#define CMDQ_EVENT_M_FILM_GRAIN_IRQ_B			135
#define CMDQ_EVENT_M_HDR_VDO_FE_IRQB			136
#define CMDQ_EVENT_DISP_MAIN_DUMMY0_IRQ_B		137
#define CMDQ_EVENT_DISP_MAIN_DUMMY1_IRQ_B		138
#define CMDQ_EVENT_DISP_MAIN_DUMMY3_IRQ_B		139
#define CMDQ_EVENT_DISP_MAIN_DUMMY4_IRQ_B		140
#define CMDQ_EVENT_VDO4_DISP_END_IRQ_B			141
#define CMDQ_EVENT_VDO4_UNDER_RUN_IRQ_B			142
#define CMDQ_EVENT_DISPFMT4_VSYNC_IRQ_B			143
#define CMDQ_EVENT_S_VDO_FE_FIFO_IRQ_B			144
#define CMDQ_EVENT_S_FILM_GRAIN_IRQ_B			145
#define CMDQ_EVENT_S_HDR_VDO_FE_IRQ_B			146
#define CMDQ_EVENT_DISP_SUB_DUMMY0_IRQ_B		147
#define CMDQ_EVENT_DISP_SUB_DUMMY1_IRQ_B		148
#define CMDQ_EVENT_DISP_SUB_DUMMY2_IRQ_B		149
#define CMDQ_EVENT_DISP_SUB_DUMMY3_IRQ_B		150
#define CMDQ_EVENT_IMGRZ_INT_CH2			151
#define CMDQ_EVENT_IMGRZ_INT				152
#define CMDQ_EVENT_IRT_DMA_INT				153
#define CMDQ_EVENT_WR_CHNL_FRAME_END_IRQ_B		154
#define CMDQ_EVENT_NR_INT				155
#define CMDQ_EVENT_DISPFMT_DI_VSYNC_INT			156
#define CMDQ_EVENT_DISPFMT_DI_FRAME_END			157
#define CMDQ_EVENT_VDO_DI_DISP_END			158
#define CMDQ_EVENT_VDO_DI_UNDER_RUN			159
#define CMDQ_EVENT_M_HDR_DM_ADL_TRIG			160
#define CMDQ_EVENT_DISP_SUB_ADL_TRIG_0			161
#define CMDQ_EVENT_IRT_DMA_EVENT			162

/* VDEC EVENT */
#define CMDQ_EVENT_LAT_LINE_COUNT_THRESHOLD_INTERRUPT	256
#define CMDQ_EVENT_LAT_VDEC_INT				257
#define CMDQ_EVENT_LAT_VDEC_PAUSE			258
#define CMDQ_EVENT_LAT_VDEC_DEC_ERROR			259
#define CMDQ_EVENT_LAT_MC_BUSY_OVERFLOW_MDEC_TIMEOUT	260
#define CMDQ_EVENT_LAT_VDEC_FRAME_DONE			261
#define CMDQ_EVENT_LAT_INI_FETCH_RDY			262
#define CMDQ_EVENT_LAT_PROCESS_FLAG			263
#define CMDQ_EVENT_LAT_SEARCH_START_CODE_DONE		264
#define CMDQ_EVENT_LAT_REF_REORDER_DONE			265
#define CMDQ_EVENT_LAT_WP_TBLE_DONE			266
#define CMDQ_EVENT_LAT_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	267
#define CMDQ_EVENT_LAT_GCE_CNT_OP_THRESHOLD		271


#define CMDQ_EVENT_CORE_LINE_COUNT_THRESHOLD_INTERRUPT	320
#define CMDQ_EVENT_CORE_VDEC_INT			321
#define CMDQ_EVENT_CORE_VDEC_PAUSE			322
#define CMDQ_EVENT_CORE_VDEC_DEC_ERROR			323
#define CMDQ_EVENT_CORE_MC_BUSY_OVERFLOW_MDEC_TIMEOUT	324
#define CMDQ_EVENT_CORE_VDEC_FRAME_DONE			325
#define CMDQ_EVENT_CORE_INI_FETCH_RDY			326
#define CMDQ_EVENT_CORE_PROCESS_FLAG			327
#define CMDQ_EVENT_CORE_SEARCH_START_CODE_DONE		328
#define CMDQ_EVENT_CORE_REF_REORDER_DONE		329
#define CMDQ_EVENT_CORE_WP_TBLE_DONE			330
#define CMDQ_EVENT_CORE_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	331
#define CMDQ_EVENT_CORE_GCE_CNT_OP_THRESHOLD		335


/* VENC EVENT */
#define CMDQ_EVENT_VENC_FRAME_DONE			385
#define CMDQ_EVENT_VENC_PAUSE_DONE			386
#define CMDQ_EVENT_VENC_MB_DONE				387
#define CMDQ_EVENT_VENC_128BYTE_COUNT_DONE		388
#define CMDQ_EVENT_VENC_PPS_DONE			391
#define CMDQ_EVENT_VENC_SPS_DONE			392
#define CMDQ_EVENT_VENC_VPS_DONE			393

/* end of hw event and begin of sw token */
#define CMDQ_MAX_HW_EVENT				400

/* Config thread notify trigger thread */
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY			401
/* Trigger thread notify config thread */
#define CMDQ_SYNC_TOKEN_STREAM_EOF			402
/* Block Trigger thread until the ESD check finishes. */
#define CMDQ_SYNC_TOKEN_ESD_EOF				403
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK			404
/* check CABC setup finish */
#define CMDQ_SYNC_TOKEN_CABC_EOF			405

/* Notify normal CMDQ there are some secure task done
 * MUST NOT CHANGE, this token sync with secure world
 */
#define CMDQ_SYNC_SECURE_THR_EOF			406

/* CMDQ use sw token */
#define CMDQ_SYNC_TOKEN_USER_0				407
#define CMDQ_SYNC_TOKEN_USER_1				408
#define CMDQ_SYNC_TOKEN_POLL_MONITOR			409
#define CMDQ_SYNC_TOKEN_TPR_LOCK			410

/* GPR access tokens (for register backup)
 * There are 15 32-bit GPR, 3 GPR form a set
 * (64-bit for address, 32-bit for value)
 * MUST NOT CHANGE, these tokens sync with MDP
 */
#define CMDQ_SYNC_TOKEN_GPR_SET_0			700
#define CMDQ_SYNC_TOKEN_GPR_SET_1			701
#define CMDQ_SYNC_TOKEN_GPR_SET_2			702
#define CMDQ_SYNC_TOKEN_GPR_SET_3			703
#define CMDQ_SYNC_TOKEN_GPR_SET_4			704

#define CMDQ_SYNC_RESOURCE_WROT0			710
#define CMDQ_SYNC_RESOURCE_WROT1			711

/* event for gpr timer, used in sleep and poll with timeout */
#define CMDQ_TOKEN_GPR_TIMER_R0				994
#define CMDQ_TOKEN_GPR_TIMER_R1				995
#define CMDQ_TOKEN_GPR_TIMER_R2				996
#define CMDQ_TOKEN_GPR_TIMER_R3				997
#define CMDQ_TOKEN_GPR_TIMER_R4				998
#define CMDQ_TOKEN_GPR_TIMER_R5				999
#define CMDQ_TOKEN_GPR_TIMER_R6				1000
#define CMDQ_TOKEN_GPR_TIMER_R7				1001
#define CMDQ_TOKEN_GPR_TIMER_R8				1002
#define CMDQ_TOKEN_GPR_TIMER_R9				1003
#define CMDQ_TOKEN_GPR_TIMER_R10			1004
#define CMDQ_TOKEN_GPR_TIMER_R11			1005
#define CMDQ_TOKEN_GPR_TIMER_R12			1006
#define CMDQ_TOKEN_GPR_TIMER_R13			1007
#define CMDQ_TOKEN_GPR_TIMER_R14			1008
#define CMDQ_TOKEN_GPR_TIMER_R15			1009

#endif
