/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef __MIPI_RX_ANA_CDPHY_CSI0A_H__
#define __MIPI_RX_ANA_CDPHY_CSI0A_H__

#define CDPHY_RX_ANA_0 0x0000
#define RG_CSI0_BG_CORE_EN_SHIFT 0
#define RG_CSI0_BG_CORE_EN_MASK (0x1 << 0)
#define RG_CSI0_BG_LPF_EN_SHIFT 1
#define RG_CSI0_BG_LPF_EN_MASK (0x1 << 1)
#define RG_CSI0_EQ_PROTECT_EN_SHIFT 4
#define RG_CSI0_EQ_PROTECT_EN_MASK (0x1 << 4)
#define RG_CSI0_BYTE_CK_RSTB_SEL_SHIFT 5
#define RG_CSI0_BYTE_CK_RSTB_SEL_MASK (0x1 << 5)
#define RG_CSI0_DPHY_L0_CKSEL_SHIFT 8
#define RG_CSI0_DPHY_L0_CKSEL_MASK (0x1 << 8)
#define RG_CSI0_DPHY_L1_CKSEL_SHIFT 9
#define RG_CSI0_DPHY_L1_CKSEL_MASK (0x1 << 9)
#define RG_CSI0_DPHY_L2_CKSEL_SHIFT 10
#define RG_CSI0_DPHY_L2_CKSEL_MASK (0x1 << 10)
#define RG_CSI0_DPHY_L0_CKMODE_EN_SHIFT 12
#define RG_CSI0_DPHY_L0_CKMODE_EN_MASK (0x1 << 12)
#define RG_CSI0_DPHY_L1_CKMODE_EN_SHIFT 13
#define RG_CSI0_DPHY_L1_CKMODE_EN_MASK (0x1 << 13)
#define RG_CSI0_DPHY_L2_CKMODE_EN_SHIFT 14
#define RG_CSI0_DPHY_L2_CKMODE_EN_MASK (0x1 << 14)
#define RG_CSI0_CDPHY_L0_T0_BYTECK_INVERT_SHIFT 16
#define RG_CSI0_CDPHY_L0_T0_BYTECK_INVERT_MASK (0x1 << 16)
#define RG_CSI0_DPHY_L1_BYTECK_INVERT_SHIFT 17
#define RG_CSI0_DPHY_L1_BYTECK_INVERT_MASK (0x1 << 17)
#define RG_CSI0_CDPHY_L2_T1_BYTECK_INVERT_SHIFT 18
#define RG_CSI0_CDPHY_L2_T1_BYTECK_INVERT_MASK (0x1 << 18)
#define RG_CSI0_CPHY_EN_SHIFT 20
#define RG_CSI0_CPHY_EN_MASK (0x1 << 20)
#define RG_CSI0_CPHY_T0_CDR_FIRST_EDGE_EN_SHIFT 21
#define RG_CSI0_CPHY_T0_CDR_FIRST_EDGE_EN_MASK (0x1 << 21)
#define RG_CSI0_CPHY_T1_CDR_FIRST_EDGE_EN_SHIFT 22
#define RG_CSI0_CPHY_T1_CDR_FIRST_EDGE_EN_MASK (0x1 << 22)
#define RG_CSI0_CDPHY_L0_T0_FORCE_INIT_SHIFT 24
#define RG_CSI0_CDPHY_L0_T0_FORCE_INIT_MASK (0x1 << 24)
#define RG_CSI0_DPHY_L1_FORCE_INIT_SHIFT 25
#define RG_CSI0_DPHY_L1_FORCE_INIT_MASK (0x1 << 25)
#define RG_CSI0_CDPHY_L2_T1_FORCE_INIT_SHIFT 26
#define RG_CSI0_CDPHY_L2_T1_FORCE_INIT_MASK (0x1 << 26)
#define RG_CSI0_CDPHY_L0_T0_SYNC_INIT_CTRL_SHIFT 28
#define RG_CSI0_CDPHY_L0_T0_SYNC_INIT_CTRL_MASK (0x1 << 28)
#define RG_CSI0_DPHY_L1_SYNC_INIT_CTRL_SHIFT 29
#define RG_CSI0_DPHY_L1_SYNC_INIT_CTRL_MASK (0x1 << 29)
#define RG_CSI0_CDPHY_L2_T1_SYNC_INIT_CTRL_SHIFT 30
#define RG_CSI0_CDPHY_L2_T1_SYNC_INIT_CTRL_MASK (0x1 << 30)
#define RG_CSI0_FORCE_HSRT_EN_SHIFT 31
#define RG_CSI0_FORCE_HSRT_EN_MASK (0x1 << 31)

#define CDPHY_RX_ANA_1 0x0004
#define RG_CSI0_BG_LPRX_VTL_SEL_SHIFT 0
#define RG_CSI0_BG_LPRX_VTL_SEL_MASK (0x7 << 0)
#define RG_CSI0_BG_LPRX_VTH_SEL_SHIFT 4
#define RG_CSI0_BG_LPRX_VTH_SEL_MASK (0x7 << 4)
#define RG_CSI0_BG_VREF_SEL_SHIFT 8
#define RG_CSI0_BG_VREF_SEL_MASK (0xf << 8)
#define RG_CSI0_CDPHY_DELAYCAL_CK_SEL_SHIFT 12
#define RG_CSI0_CDPHY_DELAYCAL_CK_SEL_MASK (0x7 << 12)
#define RG_CSI0_CDPHY_EQ_DES_VREF_SEL_SHIFT 16
#define RG_CSI0_CDPHY_EQ_DES_VREF_SEL_MASK (0x7 << 16)
#define RG_CSI0_CDPHY_DELAY_VREF_SEL_SHIFT 20
#define RG_CSI0_CDPHY_DELAY_VREF_SEL_MASK (0x7 << 20)
#define RG_CSI0_DPHY_L0_DELAYCAL_EN_SHIFT 24
#define RG_CSI0_DPHY_L0_DELAYCAL_EN_MASK (0x1 << 24)
#define RG_CSI0_DPHY_L1_DELAYCAL_EN_SHIFT 25
#define RG_CSI0_DPHY_L1_DELAYCAL_EN_MASK (0x1 << 25)
#define RG_CSI0_DPHY_L2_DELAYCAL_EN_SHIFT 26
#define RG_CSI0_DPHY_L2_DELAYCAL_EN_MASK (0x1 << 26)
#define RG_CSI0_DPHY_L0_DELAYCAL_RSTB_SHIFT 28
#define RG_CSI0_DPHY_L0_DELAYCAL_RSTB_MASK (0x1 << 28)
#define RG_CSI0_DPHY_L1_DELAYCAL_RSTB_SHIFT 29
#define RG_CSI0_DPHY_L1_DELAYCAL_RSTB_MASK (0x1 << 29)
#define RG_CSI0_DPHY_L2_DELAYCAL_RSTB_SHIFT 30
#define RG_CSI0_DPHY_L2_DELAYCAL_RSTB_MASK (0x1 << 30)

#define CDPHY_RX_ANA_2 0x0008
#define RG_CSI0_L0P_T0A_HSRT_CODE_SHIFT 0
#define RG_CSI0_L0P_T0A_HSRT_CODE_MASK (0x1f << 0)
#define RG_CSI0_L0N_T0B_HSRT_CODE_SHIFT 8
#define RG_CSI0_L0N_T0B_HSRT_CODE_MASK (0x1f << 8)
#define RG_CSI0_CPHY_T0_CDR_SELF_CAL_EN_SHIFT 16
#define RG_CSI0_CPHY_T0_CDR_SELF_CAL_EN_MASK (0x1 << 16)
#define RG_CSI0_CPHY_T1_CDR_SELF_CAL_EN_SHIFT 17
#define RG_CSI0_CPHY_T1_CDR_SELF_CAL_EN_MASK (0x1 << 17)
#define RG_CSI0_BG_ALP_RX_VTH_SEL_SHIFT 24
#define RG_CSI0_BG_ALP_RX_VTH_SEL_MASK (0x7 << 24)
#define RG_CSI0_BG_ALP_RX_VTL_SEL_SHIFT 28
#define RG_CSI0_BG_ALP_RX_VTL_SEL_MASK (0x7 << 28)

#define CDPHY_RX_ANA_3 0x000c
#define RG_CSI0_L1P_T0C_HSRT_CODE_SHIFT 0
#define RG_CSI0_L1P_T0C_HSRT_CODE_MASK (0x1f << 0)
#define RG_CSI0_L1N_T1A_HSRT_CODE_SHIFT 8
#define RG_CSI0_L1N_T1A_HSRT_CODE_MASK (0x1f << 8)
#define RG_CSI0_OS_CAL_CNT_SEL_SHIFT 16
#define RG_CSI0_OS_CAL_CNT_SEL_MASK (0x3 << 16)
#define RG_CSI0_EQ_DES_VREF_SEL_SHIFT 20
#define RG_CSI0_EQ_DES_VREF_SEL_MASK (0x3f << 20)

#define CDPHY_RX_ANA_4 0x0010
#define RG_CSI0_L2P_T1B_HSRT_CODE_SHIFT 0
#define RG_CSI0_L2P_T1B_HSRT_CODE_MASK (0x1f << 0)
#define RG_CSI0_L2N_T1C_HSRT_CODE_SHIFT 8
#define RG_CSI0_L2N_T1C_HSRT_CODE_MASK (0x1f << 8)

#define CDPHY_RX_ANA_5 0x0014
#define RG_CSI0_CDPHY_EQ_BW_SHIFT 0
#define RG_CSI0_CDPHY_EQ_BW_MASK (0x3 << 0)
#define RG_CSI0_CDPHY_EQ_IS_SHIFT 2
#define RG_CSI0_CDPHY_EQ_IS_MASK (0x3 << 2)
#define RG_CSI0_CDPHY_EQ_DG0_EN_SHIFT 4
#define RG_CSI0_CDPHY_EQ_DG0_EN_MASK (0x1 << 4)
#define RG_CSI0_CDPHY_EQ_DG1_EN_SHIFT 5
#define RG_CSI0_CDPHY_EQ_DG1_EN_MASK (0x1 << 5)
#define RG_CSI0_CDPHY_EQ_LATCH_EN_SHIFT 6
#define RG_CSI0_CDPHY_EQ_LATCH_EN_MASK (0x1 << 6)
#define RG_CSI0_CDPHY_EQ_SR0_SHIFT 8
#define RG_CSI0_CDPHY_EQ_SR0_MASK (0xf << 8)
#define RG_CSI0_CDPHY_EQ_SR1_SHIFT 12
#define RG_CSI0_CDPHY_EQ_SR1_MASK (0xf << 12)
#define RG_CSI0_L0_T0AB_EQ_MON_EN_SHIFT 16
#define RG_CSI0_L0_T0AB_EQ_MON_EN_MASK (0x1 << 16)
#define RG_CSI0_L1_T1AB_EQ_MON_EN_SHIFT 17
#define RG_CSI0_L1_T1AB_EQ_MON_EN_MASK (0x1 << 17)
#define RG_CSI0_L2_T1BC_EQ_MON_EN_SHIFT 18
#define RG_CSI0_L2_T1BC_EQ_MON_EN_MASK (0x1 << 18)
#define RG_CSI0_XX_T0BC_EQ_MON_EN_SHIFT 24
#define RG_CSI0_XX_T0BC_EQ_MON_EN_MASK (0x1 << 24)
#define RG_CSI0_XX_T0CA_EQ_MON_EN_SHIFT 25
#define RG_CSI0_XX_T0CA_EQ_MON_EN_MASK (0x1 << 25)
#define RG_CSI0_XX_T1CA_EQ_MON_EN_SHIFT 26
#define RG_CSI0_XX_T1CA_EQ_MON_EN_MASK (0x1 << 26)

#define CDPHY_RX_ANA_6 0x0018
#define RG_CSI0_CPHY_T0_CDR_AB_WIDTH_SHIFT 0
#define RG_CSI0_CPHY_T0_CDR_AB_WIDTH_MASK (0x3f << 0)
#define RG_CSI0_CPHY_T0_CDR_BC_WIDTH_SHIFT 8
#define RG_CSI0_CPHY_T0_CDR_BC_WIDTH_MASK (0x3f << 8)
#define RG_CSI0_CPHY_T0_CDR_CA_WIDTH_SHIFT 16
#define RG_CSI0_CPHY_T0_CDR_CA_WIDTH_MASK (0x3f << 16)
#define RG_CSI0_CPHY_T0_CDR_CK_DELAY_SHIFT 24
#define RG_CSI0_CPHY_T0_CDR_CK_DELAY_MASK (0x3f << 24)

#define CDPHY_RX_ANA_7 0x001c
#define RG_CSI0_CPHY_T1_CDR_AB_WIDTH_SHIFT 0
#define RG_CSI0_CPHY_T1_CDR_AB_WIDTH_MASK (0x3f << 0)
#define RG_CSI0_CPHY_T1_CDR_BC_WIDTH_SHIFT 8
#define RG_CSI0_CPHY_T1_CDR_BC_WIDTH_MASK (0x3f << 8)
#define RG_CSI0_CPHY_T1_CDR_CA_WIDTH_SHIFT 16
#define RG_CSI0_CPHY_T1_CDR_CA_WIDTH_MASK (0x3f << 16)
#define RG_CSI0_CPHY_T1_CDR_CK_DELAY_SHIFT 24
#define RG_CSI0_CPHY_T1_CDR_CK_DELAY_MASK (0x3f << 24)

#define CDPHY_RX_ANA_8 0x0020
#define RGS_CSI0_CDPHY_L0_T0AB_OS_CAL_CPLT_SHIFT 0
#define RGS_CSI0_CDPHY_L0_T0AB_OS_CAL_CPLT_MASK (0x1 << 0)
#define RGS_CSI0_CDPHY_L1_T1AB_OS_CAL_CPLT_SHIFT 1
#define RGS_CSI0_CDPHY_L1_T1AB_OS_CAL_CPLT_MASK (0x1 << 1)
#define RGS_CSI0_CDPHY_L2_T1BC_OS_CAL_CPLT_SHIFT 2
#define RGS_CSI0_CDPHY_L2_T1BC_OS_CAL_CPLT_MASK (0x1 << 2)
#define RGS_CSI0_CPHY_T0BC_OS_CAL_CPLT_SHIFT 3
#define RGS_CSI0_CPHY_T0BC_OS_CAL_CPLT_MASK (0x1 << 3)
#define RGS_CSI0_CPHY_T0CA_OS_CAL_CPLT_SHIFT 4
#define RGS_CSI0_CPHY_T0CA_OS_CAL_CPLT_MASK (0x1 << 4)
#define RGS_CSI0_CPHY_T1CA_OS_CAL_CPLT_SHIFT 5
#define RGS_CSI0_CPHY_T1CA_OS_CAL_CPLT_MASK (0x1 << 5)
#define RGS_CSI0_OS_CAL_CODE_SHIFT 8
#define RGS_CSI0_OS_CAL_CODE_MASK (0xff << 8)
#define RG_CSI0_L0_T0AB_EQ_OS_CAL_EN_SHIFT 16
#define RG_CSI0_L0_T0AB_EQ_OS_CAL_EN_MASK (0x1 << 16)
#define RG_CSI0_L1_T1AB_EQ_OS_CAL_EN_SHIFT 17
#define RG_CSI0_L1_T1AB_EQ_OS_CAL_EN_MASK (0x1 << 17)
#define RG_CSI0_L2_T1BC_EQ_OS_CAL_EN_SHIFT 18
#define RG_CSI0_L2_T1BC_EQ_OS_CAL_EN_MASK (0x1 << 18)
#define RG_CSI0_XX_T0BC_EQ_OS_CAL_EN_SHIFT 19
#define RG_CSI0_XX_T0BC_EQ_OS_CAL_EN_MASK (0x1 << 19)
#define RG_CSI0_XX_T0CA_EQ_OS_CAL_EN_SHIFT 20
#define RG_CSI0_XX_T0CA_EQ_OS_CAL_EN_MASK (0x1 << 20)
#define RG_CSI0_XX_T1CA_EQ_OS_CAL_EN_SHIFT 21
#define RG_CSI0_XX_T1CA_EQ_OS_CAL_EN_MASK (0x1 << 21)
#define RG_CSI0_OS_CAL_SEL_SHIFT 24
#define RG_CSI0_OS_CAL_SEL_MASK (0x7 << 24)
#define RG_CSI0_OS_CAL_DIV_SHIFT 28
#define RG_CSI0_OS_CAL_DIV_MASK (0x7 << 28)

#define CDPHY_RX_ANA_9 0x0024
#define RGS_CSI0_CPHY_T0_DLL_CODE_SHIFT 0
#define RGS_CSI0_CPHY_T0_DLL_CODE_MASK (0xf << 0)
#define RGS_CSI0_CPHY_T0_MASK_CAL_CPLT_SHIFT 4
#define RGS_CSI0_CPHY_T0_MASK_CAL_CPLT_MASK (0x1 << 4)
#define RGS_CSI0_CPHY_T0_MASK_CAL_OF_SHIFT 5
#define RGS_CSI0_CPHY_T0_MASK_CAL_OF_MASK (0x1 << 5)
#define RGS_CSI0_CPHY_T1_DLL_CODE_SHIFT 8
#define RGS_CSI0_CPHY_T1_DLL_CODE_MASK (0xf << 8)
#define RGS_CSI0_CPHY_T1_MASK_CAL_CPLT_SHIFT 12
#define RGS_CSI0_CPHY_T1_MASK_CAL_CPLT_MASK (0x1 << 12)
#define RGS_CSI0_CPHY_T1_MASK_CAL_OF_SHIFT 13
#define RGS_CSI0_CPHY_T1_MASK_CAL_OF_MASK (0x1 << 13)
#define RG_CSI0_RESERVE_SHIFT 16
#define RG_CSI0_RESERVE_MASK (0xffff << 16)

#define CDPHY_RX_ANA_FORCE_MODE_0 0x0040
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0P_T0A_LPRX_EN_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0P_T0A_LPRX_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0N_T0B_LPRX_EN_SHIFT 1
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0N_T0B_LPRX_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1P_T0C_LPRX_EN_SHIFT 4
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1P_T0C_LPRX_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1N_T1A_LPRX_EN_SHIFT 5
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1N_T1A_LPRX_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2P_T1B_LPRX_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2P_T1B_LPRX_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2N_T1C_LPRX_EN_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2N_T1C_LPRX_EN_MASK (0x1 << 9)
#define RO_DA_CSI0_CDPHY_L0P_T0A_LPRX_EN_SHIFT 16
#define RO_DA_CSI0_CDPHY_L0P_T0A_LPRX_EN_MASK (0x1 << 16)
#define RO_DA_CSI0_CDPHY_L0N_T0B_LPRX_EN_SHIFT 17
#define RO_DA_CSI0_CDPHY_L0N_T0B_LPRX_EN_MASK (0x1 << 17)
#define RO_DA_CSI0_CDPHY_L1P_T0C_LPRX_EN_SHIFT 20
#define RO_DA_CSI0_CDPHY_L1P_T0C_LPRX_EN_MASK (0x1 << 20)
#define RO_DA_CSI0_CDPHY_L1N_T1A_LPRX_EN_SHIFT 21
#define RO_DA_CSI0_CDPHY_L1N_T1A_LPRX_EN_MASK (0x1 << 21)
#define RO_DA_CSI0_CDPHY_L2P_T1B_LPRX_EN_SHIFT 24
#define RO_DA_CSI0_CDPHY_L2P_T1B_LPRX_EN_MASK (0x1 << 24)
#define RO_DA_CSI0_CDPHY_L2N_T1C_LPRX_EN_SHIFT 25
#define RO_DA_CSI0_CDPHY_L2N_T1C_LPRX_EN_MASK (0x1 << 25)

#define CDPHY_RX_ANA_FORCE_MODE_EN_0 0x0044
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0P_T0A_LPRX_EN_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0P_T0A_LPRX_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0N_T0B_LPRX_EN_SHIFT 1
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0N_T0B_LPRX_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1P_T0C_LPRX_EN_SHIFT 4
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1P_T0C_LPRX_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1N_T1A_LPRX_EN_SHIFT 5
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1N_T1A_LPRX_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2P_T1B_LPRX_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2P_T1B_LPRX_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2N_T1C_LPRX_EN_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2N_T1C_LPRX_EN_MASK (0x1 << 9)

#define CDPHY_RX_ANA_AD_0 0x0048
#define RO_AD_CSI0_CDPHY_L0P_T0A_LPRX_OUT_SHIFT 0
#define RO_AD_CSI0_CDPHY_L0P_T0A_LPRX_OUT_MASK (0x1 << 0)
#define RO_AD_CSI0_CDPHY_L0N_T0B_LPRX_OUT_SHIFT 1
#define RO_AD_CSI0_CDPHY_L0N_T0B_LPRX_OUT_MASK (0x1 << 1)
#define RO_AD_CSI0_CDPHY_L1P_T0C_LPRX_OUT_SHIFT 4
#define RO_AD_CSI0_CDPHY_L1P_T0C_LPRX_OUT_MASK (0x1 << 4)
#define RO_AD_CSI0_CDPHY_L1N_T1A_LPRX_OUT_SHIFT 5
#define RO_AD_CSI0_CDPHY_L1N_T1A_LPRX_OUT_MASK (0x1 << 5)
#define RO_AD_CSI0_CDPHY_L2P_T1B_LPRX_OUT_SHIFT 8
#define RO_AD_CSI0_CDPHY_L2P_T1B_LPRX_OUT_MASK (0x1 << 8)
#define RO_AD_CSI0_CDPHY_L2N_T1C_LPRX_OUT_SHIFT 9
#define RO_AD_CSI0_CDPHY_L2N_T1C_LPRX_OUT_MASK (0x1 << 9)

#define CDPHY_RX_ANA_FORCE_MODE_1 0x0050
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_ALPRX_EN_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_ALPRX_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_ALPRX_EN_SHIFT 4
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_ALPRX_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_ALPRX_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_ALPRX_EN_MASK (0x1 << 8)
#define RO_DA_CSI0_DPHY_L0_ALPRX_EN_SHIFT 16
#define RO_DA_CSI0_DPHY_L0_ALPRX_EN_MASK (0x1 << 16)
#define RO_DA_CSI0_DPHY_L1_ALPRX_EN_SHIFT 20
#define RO_DA_CSI0_DPHY_L1_ALPRX_EN_MASK (0x1 << 20)
#define RO_DA_CSI0_DPHY_L2_ALPRX_EN_SHIFT 24
#define RO_DA_CSI0_DPHY_L2_ALPRX_EN_MASK (0x1 << 24)

#define CDPHY_RX_ANA_FORCE_MODE_EN_1 0x0054
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_ALPRX_EN_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_ALPRX_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_ALPRX_EN_SHIFT 4
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_ALPRX_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_ALPRX_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_ALPRX_EN_MASK (0x1 << 8)

#define CDPHY_RX_ANA_AD_1 0x0058
#define RO_AD_CSI0_DPHY_L0_ALPRX_OUT_SHIFT 0
#define RO_AD_CSI0_DPHY_L0_ALPRX_OUT_MASK (0x1 << 0)
#define RO_AD_CSI0_DPHY_L1_ALPRX_OUT_SHIFT 4
#define RO_AD_CSI0_DPHY_L1_ALPRX_OUT_MASK (0x1 << 4)
#define RO_AD_CSI0_DPHY_L2_ALPRX_OUT_SHIFT 8
#define RO_AD_CSI0_DPHY_L2_ALPRX_OUT_MASK (0x1 << 8)

#define CDPHY_RX_ANA_FORCE_MODE_2 0x0060
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0P_T0A_HSRT_EN_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0P_T0A_HSRT_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0N_T0B_HSRT_EN_SHIFT 1
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0N_T0B_HSRT_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1P_T0C_HSRT_EN_SHIFT 4
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1P_T0C_HSRT_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1N_T1A_HSRT_EN_SHIFT 5
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1N_T1A_HSRT_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2P_T1B_HSRT_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2P_T1B_HSRT_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2N_T1C_HSRT_EN_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2N_T1C_HSRT_EN_MASK (0x1 << 9)
#define RO_DA_CSI0_CDPHY_L0P_T0A_HSRT_EN_SHIFT 16
#define RO_DA_CSI0_CDPHY_L0P_T0A_HSRT_EN_MASK (0x1 << 16)
#define RO_DA_CSI0_CDPHY_L0N_T0B_HSRT_EN_SHIFT 17
#define RO_DA_CSI0_CDPHY_L0N_T0B_HSRT_EN_MASK (0x1 << 17)
#define RO_DA_CSI0_CDPHY_L1P_T0C_HSRT_EN_SHIFT 20
#define RO_DA_CSI0_CDPHY_L1P_T0C_HSRT_EN_MASK (0x1 << 20)
#define RO_DA_CSI0_CDPHY_L1N_T1A_HSRT_EN_SHIFT 21
#define RO_DA_CSI0_CDPHY_L1N_T1A_HSRT_EN_MASK (0x1 << 21)
#define RO_DA_CSI0_CDPHY_L2P_T1B_HSRT_EN_SHIFT 24
#define RO_DA_CSI0_CDPHY_L2P_T1B_HSRT_EN_MASK (0x1 << 24)
#define RO_DA_CSI0_CDPHY_L2N_T1C_HSRT_EN_SHIFT 25
#define RO_DA_CSI0_CDPHY_L2N_T1C_HSRT_EN_MASK (0x1 << 25)

#define CDPHY_RX_ANA_FORCE_MODE_EN_2 0x0064
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0P_T0A_HSRT_EN_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0P_T0A_HSRT_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0N_T0B_HSRT_EN_SHIFT 1
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0N_T0B_HSRT_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1P_T0C_HSRT_EN_SHIFT 4
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1P_T0C_HSRT_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1N_T1A_HSRT_EN_SHIFT 5
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1N_T1A_HSRT_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2P_T1B_HSRT_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2P_T1B_HSRT_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2N_T1C_HSRT_EN_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2N_T1C_HSRT_EN_MASK (0x1 << 9)

#define CDPHY_RX_ANA_FORCE_MODE_3 0x0070
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0_T0AB_EQ_EN_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0_T0AB_EQ_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T0CA_EQ_EN_SHIFT 1
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T0CA_EQ_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T0BC_EQ_EN_SHIFT 4
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T0BC_EQ_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1_T1AB_EQ_EN_SHIFT 5
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L1_T1AB_EQ_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T1CA_EQ_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T1CA_EQ_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2_T1BC_EQ_EN_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2_T1BC_EQ_EN_MASK (0x1 << 9)
#define RO_DA_CSI0_CDPHY_L0_T0AB_EQ_EN_SHIFT 16
#define RO_DA_CSI0_CDPHY_L0_T0AB_EQ_EN_MASK (0x1 << 16)
#define RO_DA_CSI0_CPHY_T0CA_EQ_EN_SHIFT 17
#define RO_DA_CSI0_CPHY_T0CA_EQ_EN_MASK (0x1 << 17)
#define RO_DA_CSI0_CPHY_T0BC_EQ_EN_SHIFT 20
#define RO_DA_CSI0_CPHY_T0BC_EQ_EN_MASK (0x1 << 20)
#define RO_DA_CSI0_CDPHY_L1_T1AB_EQ_EN_SHIFT 21
#define RO_DA_CSI0_CDPHY_L1_T1AB_EQ_EN_MASK (0x1 << 21)
#define RO_DA_CSI0_CPHY_T1CA_EQ_EN_SHIFT 24
#define RO_DA_CSI0_CPHY_T1CA_EQ_EN_MASK (0x1 << 24)
#define RO_DA_CSI0_CDPHY_L2_T1BC_EQ_EN_SHIFT 25
#define RO_DA_CSI0_CDPHY_L2_T1BC_EQ_EN_MASK (0x1 << 25)

#define CDPHY_RX_ANA_FORCE_MODE_EN_3 0x0074
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0_T0AB_EQ_EN_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0_T0AB_EQ_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T0CA_EQ_EN_SHIFT 1
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T0CA_EQ_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T0BC_EQ_EN_SHIFT 4
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T0BC_EQ_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1_T1AB_EQ_EN_SHIFT 5
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L1_T1AB_EQ_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T1CA_EQ_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T1CA_EQ_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2_T1BC_EQ_EN_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2_T1BC_EQ_EN_MASK (0x1 << 9)

#define CDPHY_RX_ANA_FORCE_MODE_4 0x0080
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_SAMP_EN_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_SAMP_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T0_CDR_EN_SHIFT 1
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T0_CDR_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_SAMP_EN_SHIFT 4
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_SAMP_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T1_CDR_EN_SHIFT 5
#define RG_SW_FORCE_VAL_DA_CSI0_CPHY_T1_CDR_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_SAMP_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_SAMP_EN_MASK (0x1 << 8)
#define RO_DA_CSI0_DPHY_L0_SAMP_EN_SHIFT 16
#define RO_DA_CSI0_DPHY_L0_SAMP_EN_MASK (0x1 << 16)
#define RO_DA_CSI0_CPHY_T0_CDR_EN_SHIFT 17
#define RO_DA_CSI0_CPHY_T0_CDR_EN_MASK (0x1 << 17)
#define RO_DA_CSI0_DPHY_L1_SAMP_EN_SHIFT 20
#define RO_DA_CSI0_DPHY_L1_SAMP_EN_MASK (0x1 << 20)
#define RO_DA_CSI0_CPHY_T1_CDR_EN_SHIFT 21
#define RO_DA_CSI0_CPHY_T1_CDR_EN_MASK (0x1 << 21)
#define RO_DA_CSI0_DPHY_L2_SAMP_EN_SHIFT 24
#define RO_DA_CSI0_DPHY_L2_SAMP_EN_MASK (0x1 << 24)

#define CDPHY_RX_ANA_FORCE_MODE_EN_4 0x0084
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_SAMP_EN_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_SAMP_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T0_CDR_EN_SHIFT 1
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T0_CDR_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_SAMP_EN_SHIFT 4
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_SAMP_EN_MASK (0x1 << 4)
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T1_CDR_EN_SHIFT 5
#define RG_SW_FORCE_EN_DA_CSI0_CPHY_T1_CDR_EN_MASK (0x1 << 5)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_SAMP_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_SAMP_EN_MASK (0x1 << 8)

#define CDPHY_RX_ANA_FORCE_MODE_5 0x0090
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0_T0_DES_EN_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0_T0_DES_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DES_EN_SHIFT 1
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DES_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2_T1_DES_EN_SHIFT 2
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2_T1_DES_EN_MASK (0x1 << 2)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0_T0_DES_SYNC_INIT_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L0_T0_DES_SYNC_INIT_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DES_SYNC_INIT_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DES_SYNC_INIT_MASK (0x1 << 9)
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2_T1_DES_SYNC_INIT_SHIFT 10
#define RG_SW_FORCE_VAL_DA_CSI0_CDPHY_L2_T1_DES_SYNC_INIT_MASK (0x1 << 10)
#define RO_DA_CSI0_CDPHY_L0_T0_DES_EN_SHIFT 16
#define RO_DA_CSI0_CDPHY_L0_T0_DES_EN_MASK (0x1 << 16)
#define RO_DA_CSI0_DPHY_L1_DES_EN_SHIFT 17
#define RO_DA_CSI0_DPHY_L1_DES_EN_MASK (0x1 << 17)
#define RO_DA_CSI0_CDPHY_L2_T1_DES_EN_SHIFT 18
#define RO_DA_CSI0_CDPHY_L2_T1_DES_EN_MASK (0x1 << 18)
#define RO_DA_CSI0_CDPHY_L0_T0_DES_SYNC_INIT_SHIFT 24
#define RO_DA_CSI0_CDPHY_L0_T0_DES_SYNC_INIT_MASK (0x1 << 24)
#define RO_DA_CSI0_DPHY_L1_DES_SYNC_INIT_SHIFT 25
#define RO_DA_CSI0_DPHY_L1_DES_SYNC_INIT_MASK (0x1 << 25)
#define RO_DA_CSI0_CDPHY_L2_T1_DES_SYNC_INIT_SHIFT 26
#define RO_DA_CSI0_CDPHY_L2_T1_DES_SYNC_INIT_MASK (0x1 << 26)

#define CDPHY_RX_ANA_FORCE_MODE_EN_5 0x0094
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0_T0_DES_EN_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0_T0_DES_EN_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DES_EN_SHIFT 1
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DES_EN_MASK (0x1 << 1)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2_T1_DES_EN_SHIFT 2
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2_T1_DES_EN_MASK (0x1 << 2)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0_T0_DES_SYNC_INIT_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L0_T0_DES_SYNC_INIT_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DES_SYNC_INIT_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DES_SYNC_INIT_MASK (0x1 << 9)
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2_T1_DES_SYNC_INIT_SHIFT 10
#define RG_SW_FORCE_EN_DA_CSI0_CDPHY_L2_T1_DES_SYNC_INIT_MASK (0x1 << 10)

#define CDPHY_RX_ANA_AD_HS_0 0x00a0
#define RO_AD_CSI0_CPHY_T0CA_SHIFT 0
#define RO_AD_CSI0_CPHY_T0CA_MASK (0xff << 0)
#define RO_AD_CSI0_CPHY_T0BC_SHIFT 8
#define RO_AD_CSI0_CPHY_T0BC_MASK (0xff << 8)
#define RO_AD_CSI0_CDPHY_L0_T0AB_SHIFT 16
#define RO_AD_CSI0_CDPHY_L0_T0AB_MASK (0xff << 16)

#define CDPHY_RX_ANA_AD_HS_1 0x00a4
#define RO_AD_CSI0_DPHY_L1_SHIFT 16
#define RO_AD_CSI0_DPHY_L1_MASK (0xff << 16)

#define CDPHY_RX_ANA_AD_HS_2 0x00a8
#define RO_AD_CSI0_CPHY_T1CA_SHIFT 8
#define RO_AD_CSI0_CPHY_T1CA_MASK (0xff << 8)
#define RO_AD_CSI0_CDPHY_L2_T1BC_SHIFT 16
#define RO_AD_CSI0_CDPHY_L2_T1BC_MASK (0xff << 16)
#define RO_AD_CSI0_CPHY_T1AB_SHIFT 24
#define RO_AD_CSI0_CPHY_T1AB_MASK (0xff << 24)

#define CDPHY_RX_ANA_FORCE_MODE_6 0x00b0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_DELAY_CODE_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_DELAY_CODE_MASK (0x7f << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_DELAY_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_DELAY_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_DELAY_APPLY_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L0_DELAY_APPLY_MASK (0x1 << 9)
#define RO_DA_CSI0_DPHY_L0_DELAY_CODE_SHIFT 16
#define RO_DA_CSI0_DPHY_L0_DELAY_CODE_MASK (0x7f << 16)
#define RO_DA_CSI0_DPHY_L0_DELAY_EN_SHIFT 24
#define RO_DA_CSI0_DPHY_L0_DELAY_EN_MASK (0x1 << 24)
#define RO_DA_CSI0_DPHY_L0_DELAY_APPLY_SHIFT 25
#define RO_DA_CSI0_DPHY_L0_DELAY_APPLY_MASK (0x1 << 25)

#define CDPHY_RX_ANA_FORCE_MODE_EN_6 0x00b4
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_DELAY_CODE_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_DELAY_CODE_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_DELAY_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_DELAY_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_DELAY_APPLY_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L0_DELAY_APPLY_MASK (0x1 << 9)

#define CDPHY_RX_ANA_FORCE_MODE_7 0x00c0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DELAY_CODE_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DELAY_CODE_MASK (0x7f << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DELAY_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DELAY_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DELAY_APPLY_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L1_DELAY_APPLY_MASK (0x1 << 9)
#define RO_DA_CSI0_DPHY_L1_DELAY_CODE_SHIFT 16
#define RO_DA_CSI0_DPHY_L1_DELAY_CODE_MASK (0x7f << 16)
#define RO_DA_CSI0_DPHY_L1_DELAY_EN_SHIFT 24
#define RO_DA_CSI0_DPHY_L1_DELAY_EN_MASK (0x1 << 24)
#define RO_DA_CSI0_DPHY_L1_DELAY_APPLY_SHIFT 25
#define RO_DA_CSI0_DPHY_L1_DELAY_APPLY_MASK (0x1 << 25)

#define CDPHY_RX_ANA_FORCE_MODE_EN_7 0x00c4
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DELAY_CODE_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DELAY_CODE_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DELAY_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DELAY_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DELAY_APPLY_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L1_DELAY_APPLY_MASK (0x1 << 9)

#define CDPHY_RX_ANA_FORCE_MODE_8 0x00d0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_DELAY_CODE_SHIFT 0
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_DELAY_CODE_MASK (0x7f << 0)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_DELAY_EN_SHIFT 8
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_DELAY_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_DELAY_APPLY_SHIFT 9
#define RG_SW_FORCE_VAL_DA_CSI0_DPHY_L2_DELAY_APPLY_MASK (0x1 << 9)
#define RO_DA_CSI0_DPHY_L2_DELAY_CODE_SHIFT 16
#define RO_DA_CSI0_DPHY_L2_DELAY_CODE_MASK (0x7f << 16)
#define RO_DA_CSI0_DPHY_L2_DELAY_EN_SHIFT 24
#define RO_DA_CSI0_DPHY_L2_DELAY_EN_MASK (0x1 << 24)
#define RO_DA_CSI0_DPHY_L2_DELAY_APPLY_SHIFT 25
#define RO_DA_CSI0_DPHY_L2_DELAY_APPLY_MASK (0x1 << 25)

#define CDPHY_RX_ANA_FORCE_MODE_EN_8 0x00d4
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_DELAY_CODE_SHIFT 0
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_DELAY_CODE_MASK (0x1 << 0)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_DELAY_EN_SHIFT 8
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_DELAY_EN_MASK (0x1 << 8)
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_DELAY_APPLY_SHIFT 9
#define RG_SW_FORCE_EN_DA_CSI0_DPHY_L2_DELAY_APPLY_MASK (0x1 << 9)

#define CDPHY_RX_ANA_SETTING_0 0x00f0
#define CSR_CSI_CLK_MON_SHIFT 0
#define CSR_CSI_CLK_MON_MASK (0x1 << 0)
#define CSR_CSI_CLK_EN_SHIFT 1
#define CSR_CSI_CLK_EN_MASK (0x1 << 1)
#define CSR_ASYNC_FIFO_GATING_SEL_SHIFT 4
#define CSR_ASYNC_FIFO_GATING_SEL_MASK (0xf << 4)
#define CSR_CSI_MON_MUX_SHIFT 8
#define CSR_CSI_MON_MUX_MASK (0xff << 8)
#define CSR_CSI_RST_MODE_SHIFT 16
#define CSR_CSI_RST_MODE_MASK (0x3 << 16)
#define CSR_SW_RST_SHIFT 24
#define CSR_SW_RST_MASK (0xf << 24)

#define CDPHY_RX_ANA_SETTING_1 0x00f4
#define RG_CSI0_CDPHY_FMCK_SEL_SHIFT 0
#define RG_CSI0_CDPHY_FMCK_SEL_MASK (0x3 << 0)
#define RG_CSI0_ASYNC_OPTION_SHIFT 4
#define RG_CSI0_ASYNC_OPTION_MASK (0xf << 4)
#define RG_CAL_METHOD_3S_SHIFT 8
#define RG_CAL_METHOD_3S_MASK (0x1 << 8)
#define RG_CSI0_CDPHY_SPARE_REG_SHIFT 16
#define RG_CSI0_CDPHY_SPARE_REG_MASK (0xffff << 16)

#define CDPHY_RX_ANA_DBG_OUT 0x00f8
#define CSI_DEBUG_OUT_SHIFT 0
#define CSI_DEBUG_OUT_MASK (0xffffffff << 0)

#endif
