/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright (c) 2020 MediaTek Inc.
 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 */

#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
#define _DT_BINDINGS_POWER_MT8195_POWER_H

#define MT8195_POWER_DOMAIN_PCIE_MAC_P0		0
#define MT8195_POWER_DOMAIN_PCIE_MAC_P1		1
#define MT8195_POWER_DOMAIN_PCIE_PHY		2
#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY	3
#define MT8195_POWER_DOMAIN_CSI_RX_TOP		4
#define MT8195_POWER_DOMAIN_ETHER		5
#define MT8195_POWER_DOMAIN_ADSP		6
#define MT8195_POWER_DOMAIN_AUDIO		7
#define MT8195_POWER_DOMAIN_AUDIO_ASRC		8
#define MT8195_POWER_DOMAIN_NNA			9
#define MT8195_POWER_DOMAIN_NNA0		10
#define MT8195_POWER_DOMAIN_NNA1		11
#define MT8195_POWER_DOMAIN_MFG0		12
#define MT8195_POWER_DOMAIN_MFG1		13
#define MT8195_POWER_DOMAIN_MFG2		14
#define MT8195_POWER_DOMAIN_MFG3		15
#define MT8195_POWER_DOMAIN_MFG4		16
#define MT8195_POWER_DOMAIN_MFG5		17
#define MT8195_POWER_DOMAIN_MFG6		18
#define MT8195_POWER_DOMAIN_VPPSYS0		19
#define MT8195_POWER_DOMAIN_VDOSYS0		20
#define MT8195_POWER_DOMAIN_VPPSYS1		21
#define MT8195_POWER_DOMAIN_VDOSYS1		22
#define MT8195_POWER_DOMAIN_DP_TX		23
#define MT8195_POWER_DOMAIN_EPD_TX		24
#define MT8195_POWER_DOMAIN_HDMI_TX		25
#define MT8195_POWER_DOMAIN_HDMI_RX		26
#define MT8195_POWER_DOMAIN_WPESYS		27
#define MT8195_POWER_DOMAIN_VDEC0		28
#define MT8195_POWER_DOMAIN_VDEC1		29
#define MT8195_POWER_DOMAIN_VDEC2		30
#define MT8195_POWER_DOMAIN_VENC		31
#define MT8195_POWER_DOMAIN_VENC_CORE1		32
#define MT8195_POWER_DOMAIN_IMG			33
#define MT8195_POWER_DOMAIN_DIP			34
#define MT8195_POWER_DOMAIN_IPE			35
#define MT8195_POWER_DOMAIN_CAM			36
#define MT8195_POWER_DOMAIN_CAM_RAWA		37
#define MT8195_POWER_DOMAIN_CAM_RAWB		38
#define MT8195_POWER_DOMAIN_CAM_MRAW		39

#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */
