/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

#ifndef __LINUX_REGULATOR_MT6368_H
#define __LINUX_REGULATOR_MT6368_H

enum {
	MT6368_ID_VBUCK1,
	MT6368_ID_VBUCK2,
	MT6368_ID_VBUCK3,
	MT6368_ID_VBUCK4,
	MT6368_ID_VBUCK5,
	MT6368_ID_VBUCK6,
	MT6368_ID_VPA,
	MT6368_ID_VUSB,
	MT6368_ID_VAUX18,
	MT6368_ID_VRF13_AIF,
	MT6368_ID_VRF18_AIF,
	MT6368_ID_VANT18,
	MT6368_ID_VIBR,
	MT6368_ID_VIO28,
	MT6368_ID_VFP,
	MT6368_ID_VTP,
	MT6368_ID_VMCH,
	MT6368_ID_VMC,
	MT6368_ID_VAUD18,
	MT6368_ID_VCN33_1,
	MT6368_ID_VCN33_2,
	MT6368_ID_VEFUSE,
	MT6368_ID_VMCH_EINT_HIGH,
	MT6368_ID_VMCH_EINT_LOW,
	MT6368_MAX_REGULATOR,
};

/* Register */
#define MT6368_TOP_CFG_ELR5			    0x14b
#define MT6368_PMIC_RG_BUCK_VBUCK1_EN_ADDR          0x240
#define MT6368_PMIC_RG_BUCK_VBUCK1_EN_SHIFT         1
#define MT6368_PMIC_RG_BUCK_VBUCK2_EN_ADDR          0x240
#define MT6368_PMIC_RG_BUCK_VBUCK2_EN_SHIFT         2
#define MT6368_PMIC_RG_BUCK_VBUCK3_EN_ADDR          0x240
#define MT6368_PMIC_RG_BUCK_VBUCK3_EN_SHIFT         3
#define MT6368_PMIC_RG_BUCK_VBUCK4_EN_ADDR          0x240
#define MT6368_PMIC_RG_BUCK_VBUCK4_EN_SHIFT         4
#define MT6368_PMIC_RG_BUCK_VBUCK5_EN_ADDR          0x240
#define MT6368_PMIC_RG_BUCK_VBUCK5_EN_SHIFT         5
#define MT6368_PMIC_RG_BUCK_VBUCK6_EN_ADDR          0x240
#define MT6368_PMIC_RG_BUCK_VBUCK6_EN_SHIFT         6
#define MT6368_PMIC_RG_BUCK_VPA_EN_ADDR             0x243
#define MT6368_PMIC_RG_BUCK_VPA_EN_SHIFT            3
#define MT6368_PMIC_RG_BUCK_VBUCK1_LP_ADDR          0x246
#define MT6368_PMIC_RG_BUCK_VBUCK1_LP_SHIFT         1
#define MT6368_PMIC_RG_BUCK_VBUCK2_LP_ADDR          0x246
#define MT6368_PMIC_RG_BUCK_VBUCK2_LP_SHIFT         2
#define MT6368_PMIC_RG_BUCK_VBUCK3_LP_ADDR          0x246
#define MT6368_PMIC_RG_BUCK_VBUCK3_LP_SHIFT         3
#define MT6368_PMIC_RG_BUCK_VBUCK4_LP_ADDR          0x246
#define MT6368_PMIC_RG_BUCK_VBUCK4_LP_SHIFT         4
#define MT6368_PMIC_RG_BUCK_VBUCK5_LP_ADDR          0x246
#define MT6368_PMIC_RG_BUCK_VBUCK5_LP_SHIFT         5
#define MT6368_PMIC_RG_BUCK_VBUCK6_LP_ADDR          0x246
#define MT6368_PMIC_RG_BUCK_VBUCK6_LP_SHIFT         6
#define MT6368_PMIC_RG_BUCK_VPA_LP_ADDR             0x249
#define MT6368_PMIC_RG_BUCK_VPA_LP_SHIFT            3
#define MT6368_PMIC_RG_BUCK_VBUCK1_VOSEL_ADDR       0x24d
#define MT6368_PMIC_RG_BUCK_VBUCK1_VOSEL_MASK       0xFF
#define MT6368_PMIC_RG_BUCK_VBUCK2_VOSEL_ADDR       0x24e
#define MT6368_PMIC_RG_BUCK_VBUCK2_VOSEL_MASK       0xFF
#define MT6368_PMIC_RG_BUCK_VBUCK3_VOSEL_ADDR       0x24f
#define MT6368_PMIC_RG_BUCK_VBUCK3_VOSEL_MASK       0xFF
#define MT6368_PMIC_RG_BUCK_VBUCK4_VOSEL_ADDR       0x250
#define MT6368_PMIC_RG_BUCK_VBUCK4_VOSEL_MASK       0xFF
#define MT6368_PMIC_RG_BUCK_VBUCK5_VOSEL_ADDR       0x251
#define MT6368_PMIC_RG_BUCK_VBUCK5_VOSEL_MASK       0xFF
#define MT6368_PMIC_RG_BUCK_VBUCK6_VOSEL_ADDR       0x252
#define MT6368_PMIC_RG_BUCK_VBUCK6_VOSEL_MASK       0xFF
#define MT6368_PMIC_RG_BUCK_VPA_VOSEL_ADDR          0x257
#define MT6368_PMIC_RG_BUCK_VPA_VOSEL_MASK          0x7F
#define MT6368_BUCK_TOP_KEY_PROT_LO                 0x1421
#define MT6368_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR   0x1423
#define MT6368_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR   0x1424
#define MT6368_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR   0x1425
#define MT6368_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR   0x1426
#define MT6368_PMIC_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR   0x1427
#define MT6368_PMIC_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR   0x1428
#define MT6368_PMIC_BUCK_VPA_WDTDBG_VOSEL_ADDR      0x1429
#define MT6368_PMIC_RG_VBUCK1_FCCM_ADDR             0x1833
#define MT6368_PMIC_RG_VBUCK1_FCCM_SHIFT            0
#define MT6368_PMIC_RG_VBUCK2_FCCM_ADDR             0x1833
#define MT6368_PMIC_RG_VBUCK2_FCCM_SHIFT            1
#define MT6368_PMIC_RG_VBUCK3_FCCM_ADDR             0x1833
#define MT6368_PMIC_RG_VBUCK3_FCCM_SHIFT            2
#define MT6368_PMIC_RG_VBUCK4_FCCM_ADDR             0x1833
#define MT6368_PMIC_RG_VBUCK4_FCCM_SHIFT            3
#define MT6368_PMIC_RG_VBUCK5_FCCM_ADDR             0x1893
#define MT6368_PMIC_RG_VBUCK5_FCCM_SHIFT            0
#define MT6368_PMIC_RG_VBUCK6_FCCM_ADDR             0x18a2
#define MT6368_PMIC_RG_VBUCK6_FCCM_SHIFT            0
#define MT6368_PMIC_RG_VPA_MODESET_ADDR             0x18a6
#define MT6368_PMIC_RG_VPA_MODESET_SHIFT	    1
#define MT6368_PMIC_RG_LDO_VSIM1_EN_ADDR            0x1b87
#define MT6368_PMIC_RG_LDO_VSIM1_EN_SHIFT           0
#define MT6368_PMIC_RG_LDO_VSIM1_LP_ADDR            0x1b87
#define MT6368_PMIC_RG_LDO_VSIM1_LP_SHIFT           1
#define MT6368_PMIC_RG_LDO_VSIM2_EN_ADDR            0x1b96
#define MT6368_PMIC_RG_LDO_VSIM2_EN_SHIFT           0
#define MT6368_PMIC_RG_LDO_VSIM2_LP_ADDR            0x1b96
#define MT6368_PMIC_RG_LDO_VSIM2_LP_SHIFT           1
#define MT6368_PMIC_RG_LDO_VMDDR_EN_ADDR            0x1ba5
#define MT6368_PMIC_RG_LDO_VMDDR_EN_SHIFT           0
#define MT6368_PMIC_RG_LDO_VMDDR_LP_ADDR            0x1ba5
#define MT6368_PMIC_RG_LDO_VMDDR_LP_SHIFT           1
#define MT6368_PMIC_RG_LDO_VMDDQ_EN_ADDR            0x1bb3
#define MT6368_PMIC_RG_LDO_VMDDQ_EN_SHIFT           0
#define MT6368_PMIC_RG_LDO_VMDDQ_LP_ADDR            0x1bb3
#define MT6368_PMIC_RG_LDO_VMDDQ_LP_SHIFT           1
#define MT6368_PMIC_RG_LDO_VUSB_EN_ADDR             0x1bc1
#define MT6368_PMIC_RG_LDO_VUSB_EN_SHIFT            0
#define MT6368_PMIC_RG_LDO_VUSB_LP_ADDR             0x1bc1
#define MT6368_PMIC_RG_LDO_VUSB_LP_SHIFT            1
#define MT6368_PMIC_RG_LDO_VAUX18_EN_ADDR           0x1bcf
#define MT6368_PMIC_RG_LDO_VAUX18_EN_SHIFT          0
#define MT6368_PMIC_RG_LDO_VAUX18_LP_ADDR           0x1bcf
#define MT6368_PMIC_RG_LDO_VAUX18_LP_SHIFT          1
#define MT6368_PMIC_RG_LDO_VRF13_AIF_EN_ADDR        0x1c07
#define MT6368_PMIC_RG_LDO_VRF13_AIF_EN_SHIFT       0
#define MT6368_PMIC_RG_LDO_VRF13_AIF_LP_ADDR        0x1c07
#define MT6368_PMIC_RG_LDO_VRF13_AIF_LP_SHIFT       1
#define MT6368_PMIC_RG_LDO_VRF18_AIF_EN_ADDR        0x1c15
#define MT6368_PMIC_RG_LDO_VRF18_AIF_EN_SHIFT       0
#define MT6368_PMIC_RG_LDO_VRF18_AIF_LP_ADDR        0x1c15
#define MT6368_PMIC_RG_LDO_VRF18_AIF_LP_SHIFT       1
#define MT6368_PMIC_RG_LDO_VANT18_EN_ADDR           0x1c23
#define MT6368_PMIC_RG_LDO_VANT18_EN_SHIFT          0
#define MT6368_PMIC_RG_LDO_VANT18_LP_ADDR           0x1c23
#define MT6368_PMIC_RG_LDO_VANT18_LP_SHIFT          1
#define MT6368_PMIC_RG_LDO_VIBR_EN_ADDR             0x1c31
#define MT6368_PMIC_RG_LDO_VIBR_EN_SHIFT            0
#define MT6368_PMIC_RG_LDO_VIBR_LP_ADDR             0x1c31
#define MT6368_PMIC_RG_LDO_VIBR_LP_SHIFT            1
#define MT6368_PMIC_RG_LDO_VIO28_EN_ADDR            0x1c3f
#define MT6368_PMIC_RG_LDO_VIO28_EN_SHIFT           0
#define MT6368_PMIC_RG_LDO_VIO28_LP_ADDR            0x1c3f
#define MT6368_PMIC_RG_LDO_VIO28_LP_SHIFT           1
#define MT6368_PMIC_RG_LDO_VFP_EN_ADDR              0x1c4d
#define MT6368_PMIC_RG_LDO_VFP_EN_SHIFT             0
#define MT6368_PMIC_RG_LDO_VFP_LP_ADDR              0x1c4d
#define MT6368_PMIC_RG_LDO_VFP_LP_SHIFT             1
#define MT6368_PMIC_RG_LDO_VTP_EN_ADDR              0x1c87
#define MT6368_PMIC_RG_LDO_VTP_EN_SHIFT             0
#define MT6368_PMIC_RG_LDO_VTP_LP_ADDR              0x1c87
#define MT6368_PMIC_RG_LDO_VTP_LP_SHIFT             1
#define MT6368_PMIC_RG_LDO_VMCH_EN_ADDR             0x1c95
#define MT6368_PMIC_RG_LDO_VMCH_EN_SHIFT            0
#define MT6368_PMIC_RG_LDO_VMCH_LP_ADDR             0x1c95
#define MT6368_PMIC_RG_LDO_VMCH_LP_SHIFT            1
#define MT6368_PMIC_RG_LDO_VMC_EN_ADDR              0x1ca4
#define MT6368_PMIC_RG_LDO_VMC_EN_SHIFT             0
#define MT6368_PMIC_RG_LDO_VMC_LP_ADDR              0x1ca4
#define MT6368_PMIC_RG_LDO_VMC_LP_SHIFT             1
#define MT6368_PMIC_RG_LDO_VAUD18_EN_ADDR           0x1cb2
#define MT6368_PMIC_RG_LDO_VAUD18_EN_SHIFT          0
#define MT6368_PMIC_RG_LDO_VAUD18_LP_ADDR           0x1cb2
#define MT6368_PMIC_RG_LDO_VAUD18_LP_SHIFT          1
#define MT6368_PMIC_RG_LDO_VCN33_1_EN_ADDR          0x1cc0
#define MT6368_PMIC_RG_LDO_VCN33_1_EN_SHIFT         0
#define MT6368_PMIC_RG_LDO_VCN33_1_LP_ADDR          0x1cc0
#define MT6368_PMIC_RG_LDO_VCN33_1_LP_SHIFT         1
#define MT6368_PMIC_RG_LDO_VCN33_2_EN_ADDR          0x1cce
#define MT6368_PMIC_RG_LDO_VCN33_2_EN_SHIFT         0
#define MT6368_PMIC_RG_LDO_VCN33_2_LP_ADDR          0x1cce
#define MT6368_PMIC_RG_LDO_VCN33_2_LP_SHIFT         1
#define MT6368_PMIC_RG_LDO_VEFUSE_EN_ADDR           0x1d07
#define MT6368_PMIC_RG_LDO_VEFUSE_EN_SHIFT          0
#define MT6368_PMIC_RG_LDO_VEFUSE_LP_ADDR           0x1d07
#define MT6368_PMIC_RG_LDO_VEFUSE_LP_SHIFT          1
#define MT6368_PMIC_RG_VAUX18_VOCAL_ADDR            0x1d88
#define MT6368_PMIC_RG_VAUX18_VOCAL_MASK            0xF
#define MT6368_PMIC_RG_VAUX18_VOSEL_ADDR            0x1d89
#define MT6368_PMIC_RG_VAUX18_VOSEL_MASK            0xF
#define MT6368_PMIC_RG_VSIM1_VOCAL_ADDR             0x1d8c
#define MT6368_PMIC_RG_VSIM1_VOCAL_MASK             0xF
#define MT6368_PMIC_RG_VSIM1_VOSEL_ADDR             0x1d8d
#define MT6368_PMIC_RG_VSIM1_VOSEL_MASK             0xF
#define MT6368_PMIC_RG_VSIM2_VOCAL_ADDR             0x1d90
#define MT6368_PMIC_RG_VSIM2_VOCAL_MASK             0xF
#define MT6368_PMIC_RG_VSIM2_VOSEL_ADDR             0x1d91
#define MT6368_PMIC_RG_VSIM2_VOSEL_MASK             0xF
#define MT6368_PMIC_RG_VUSB_VOCAL_ADDR              0x1d94
#define MT6368_PMIC_RG_VUSB_VOCAL_MASK              0xF
#define MT6368_PMIC_RG_VUSB_VOSEL_ADDR              0x1d95
#define MT6368_PMIC_RG_VUSB_VOSEL_MASK              0xF
#define MT6368_PMIC_RG_VIBR_VOCAL_ADDR              0x1d98
#define MT6368_PMIC_RG_VIBR_VOCAL_MASK              0xF
#define MT6368_PMIC_RG_VIBR_VOSEL_ADDR              0x1d99
#define MT6368_PMIC_RG_VIBR_VOSEL_MASK              0xF
#define MT6368_PMIC_RG_VIO28_VOCAL_ADDR             0x1d9c
#define MT6368_PMIC_RG_VIO28_VOCAL_MASK             0xF
#define MT6368_PMIC_RG_VIO28_VOSEL_ADDR             0x1d9d
#define MT6368_PMIC_RG_VIO28_VOSEL_MASK             0xF
#define MT6368_PMIC_RG_VFP_VOCAL_ADDR               0x1da0
#define MT6368_PMIC_RG_VFP_VOCAL_MASK               0xF
#define MT6368_PMIC_RG_VFP_VOSEL_ADDR               0x1da1
#define MT6368_PMIC_RG_VFP_VOSEL_MASK               0xF
#define MT6368_PMIC_RG_VTP_VOCAL_ADDR               0x1da4
#define MT6368_PMIC_RG_VTP_VOCAL_MASK               0xF
#define MT6368_PMIC_RG_VTP_VOSEL_ADDR               0x1da5
#define MT6368_PMIC_RG_VTP_VOSEL_MASK               0xF
#define MT6368_PMIC_RG_VMCH_VOCAL_ADDR              0x1da8
#define MT6368_PMIC_RG_VMCH_VOCAL_MASK              0xF
#define MT6368_PMIC_RG_VMCH_VOSEL_ADDR              0x1da9
#define MT6368_PMIC_RG_VMCH_VOSEL_MASK              0xF
#define MT6368_PMIC_RG_VMC_VOCAL_ADDR               0x1dac
#define MT6368_PMIC_RG_VMC_VOCAL_MASK               0xF
#define MT6368_PMIC_RG_VMC_VOSEL_ADDR               0x1dad
#define MT6368_PMIC_RG_VMC_VOSEL_MASK               0xF
#define MT6368_PMIC_RG_VCN33_1_VOCAL_ADDR           0x1db0
#define MT6368_PMIC_RG_VCN33_1_VOCAL_MASK           0xF
#define MT6368_PMIC_RG_VCN33_1_VOSEL_ADDR           0x1db1
#define MT6368_PMIC_RG_VCN33_1_VOSEL_MASK           0xF
#define MT6368_PMIC_RG_VCN33_2_VOCAL_ADDR           0x1db4
#define MT6368_PMIC_RG_VCN33_2_VOCAL_MASK           0xF
#define MT6368_PMIC_RG_VCN33_2_VOSEL_ADDR           0x1db5
#define MT6368_PMIC_RG_VCN33_2_VOSEL_MASK           0xF
#define MT6368_PMIC_RG_VAUD18_VOCAL_ADDR            0x1db8
#define MT6368_PMIC_RG_VAUD18_VOCAL_MASK            0xF
#define MT6368_PMIC_RG_VAUD18_VOSEL_ADDR            0x1db9
#define MT6368_PMIC_RG_VAUD18_VOSEL_MASK            0xF
#define MT6368_PMIC_RG_VANT18_VOCAL_ADDR            0x1e08
#define MT6368_PMIC_RG_VANT18_VOCAL_MASK            0xF
#define MT6368_PMIC_RG_VANT18_VOSEL_ADDR            0x1e09
#define MT6368_PMIC_RG_VANT18_VOSEL_MASK            0xF
#define MT6368_PMIC_RG_VEFUSE_VOCAL_ADDR            0x1e0c
#define MT6368_PMIC_RG_VEFUSE_VOCAL_MASK            0xF
#define MT6368_PMIC_RG_VEFUSE_VOSEL_ADDR            0x1e0d
#define MT6368_PMIC_RG_VEFUSE_VOSEL_MASK            0xF
#define MT6368_PMIC_RG_VRF18_AIF_VOCAL_ADDR         0x1e10
#define MT6368_PMIC_RG_VRF18_AIF_VOCAL_MASK         0xF
#define MT6368_PMIC_RG_VRF18_AIF_VOSEL_ADDR         0x1e11
#define MT6368_PMIC_RG_VRF18_AIF_VOSEL_MASK         0xF
#define MT6368_PMIC_RG_VRF13_AIF_VOCAL_ADDR         0x1e19
#define MT6368_PMIC_RG_VRF13_AIF_VOCAL_MASK         0xF
#define MT6368_PMIC_RG_VRF13_AIF_VOSEL_ADDR         0x1e1a
#define MT6368_PMIC_RG_VRF13_AIF_VOSEL_MASK         0xF

#define MT6368_LDO_VMCH_EINT                        0x1ca3
#define MT6368_PMIC_RG_LDO_VMCH_EINT_EN_MASK        0x1
#define MT6368_PMIC_RG_LDO_VMCH_EINT_POL_MASK       0x4
#define MT6368_PMIC_RG_LDO_VMCH_EINT_DB_MASK        0x10

#endif /* __LINUX_REGULATOR_MT6368_H */
