#ifndef CYGONCE_KINPO_G23_H
#define CYGONCE_KINPO_G23_H

//=============================================================================
//
//      Platform specific support (register layout, etc)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
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//
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// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
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//####ECOSGPLCOPYRIGHTEND####
//===========================================================================

#include <cyg/hal/hal_soc.h>        // Hardware definitions
#include <cyg/hal/hal_misc.h>       // SZ_1M

// The vector used by the Ethernet
#define CYGNUM_HAL_INTERRUPT_ETH    (32+16)

#define PMIC_SPI_BASE            CSPI1_BASE_ADDR

#define BOARD_CS_LAN_BASE           (CS4_BASE_ADDR + 0x300)

/* CPLD define (G23 CPLD Descript_080130.doc) */
#define CPLD_BASE             CS1_BASE_ADDR
#define CPLD_REG_START        CPLD_CCR   /* CPLD Register start address      */
#define CPLD_CCR              0x00000000 /* CPU Configure Register.          */
                                         /* Can be read and write.           */
#define CPLD_CCR_USBUARTS     (1 << 7)   /* 1: Enable route UART1 TX / RX    */
                                         /*    to USB connector D+ / D- and  */
                                         /*    set to 0 there select USB.    */
                                         /* Reset value: 0                   */
                                         /* Note: When USB connector been    */
                                         /* plug-in to check USB ID pin when */
                                         /* tie to ground set this bit to 1  */
                                         /* to switch to UART debug          */
                                         /* interface when USB plug-out and  */
                                         /* USB ID back to floating than     */
                                         /* switch back to 0.                */
#define CPLD_CCR_VPLLSW       (1 << 6)   /* 1: To break the bridge of VPLL   */
                                         /*    before set this bit need to   */
                                         /*    enable VDIG to 1.3V in first  */
                                         /*    before software to change the */
                                         /*    MPLL register and waiting at  */
                                         /*    least 10ms after set this bit */
                                         /*    and break VRFDIG and VDIG and */
                                         /*    then put VRFDIG in same       */
                                         /*    voltage (1.5V) and in low     */
                                         /*    power mode.                   */
                                         /* Reset value: 0                   */
#define CPLD_CCR_RESTART      (1 << 5)   /* 1: Software program this bit to  */
                                         /*    Hi after 4 second system will */
                                         /*    begin restart this bit after  */
                                         /*    restart will going Low.	     */
                                         /* Reset value: 0                   */
#define CPLD_CCR_AECEN        (1 << 4)   /* 1: To enable 13MHz AEC clock to  */
                                         /*    AEC block and also turn on    */
                                         /*    the AEC block.                */
                                         /* Reset value: 0                   */
#define CPLD_CCR_GPSRESET     (1 << 3)   /* 1: To terminate the GPS reset    */
                                         /*    and GPS chips will begin      */
                                         /*    working if GPSPROG keep low   */
                                         /*    otherwise GPS chips will      */
                                         /*    enter firmware update.        */
                                         /* Reset value: 0                   */
#define CPLD_CCR_GPSPROG      (1 << 2)   /* 1: Before GPS reset bit send out */
                                         /*    will force GPS chips put into */
                                         /*    firmware update mode.         */
                                         /* Reset value: 0                   */
#define CPLD_CCR_WDI          (1 << 1)   /* 1: Send system OFF after system  */
                                         /*    into OFF mode this bit will   */
                                         /*    auto clear.                   */
                                         /* Reset value: 0                   */
#define CPLD_CCR_RESET        (1 << 0)   /* 1: Send system reset signal      */
                                         /*    reset system this bit will    */
                                         /*    auto return to low after      */
                                         /*    system reset.                 */
                                         /* Reset value: 0                   */
#define CPLD_LCR              0x00004000 /* LCD Configure Register.          */
                                         /* Can be read and write.           */
#define CPLD_LCR_DISCHARGING  (1 << 7)   /* 1: Before clear the discharge    */
                                         /*    interrupt flag and make sure  */
                                         /*    there will enter to discharge */
                                         /*    mode and after discharge      */
                                         /*    (battery under 3.6V).         */
                                         /* 0: After discharge (battery      */
                                         /*    under 3.6V) to noted CPLD     */
                                         /*    exit discharge                */
                                         /* Reset value: 0                   */
#define CPLD_LCR_DISCHARGED   (1 << 6)   /* 1: When after discharge the      */
                                         /*    battery below 3.6V.           */
                                         /* 0: When battery charge over      */
                                         /*    3.8V.                         */
                                         /* Reset value: 0                   */
#define CPLD_LCR_LCDBLKEN     (1 << 5)   /* 1: Enable LCD backlight working. */
                                         /* Reset value: 0                   */
#define CPLD_LCR_PWMFULL      (1 << 4)   /* 1: Follow PWM duty bit0 ~ bit3   */
                                         /*    define.                       */
                                         /* 0: To set PWM to 100% duty.      */
                                         /* Reset value: 0                   */
#define CPLD_LCR_PWM3         (1 << 3)   /* PWM3 ~ PWM0 from 0000 ~ 1111 to  */
                                         /* define the duty 0% to 93.75%.    */
                                         /* Reset value: 0                   */
#define CPLD_LCR_PWM2         (1 << 2)   /* See CPLD_LCR_PWM3.               */
                                         /* Reset value: 0                   */
#define CPLD_LCR_PWM1         (1 << 1)   /* See CPLD_LCR_PWM3.               */
                                         /* Reset value: 0                   */
#define CPLD_LCR_PWM0         (1 << 0)   /* See CPLD_LCR_PWM3.               */
                                         /* Reset value: 0                   */
#define CPLD_SR               0x00008000 /* Status Register                  */
                                         /* Can be read only.                */
                                         /*                                  */
                                         /*                                  */
#define CPLD_SR_RESERVE7      (1 << 7)   /* Reserved.                        */
#define CPLD_SR_LBARDY        (1 << 6)   /* 1: LBA ready.                    */
#define CPLD_SR_NAND          (1 << 5)   /* 1: Nand flash ready.             */
                                         /* 0: Nand flash busy.              */
#define CPLD_SR_RESERVE4      (1 << 4)   /* Reserved.                        */
#define CPLD_SR_OVERTEMP      (1 << 3)   /* 1: The temperature still under   */
                                         /*    55 degree Centigrade.         */
                                         /* 0: The temperature over          */
                                         /*    55 degree Centigrade.         */
                                         /* Note: Real time response the     */
                                         /*       temperature detect.        */
#define CPLD_SR_OVERINT       (1 << 2)   /* 1: The PMIC interrupt comes from */
                                         /*    over temperature need to      */
                                         /*    service and going the         */
                                         /*    discharge service as          */
                                         /*    description in configure      */
                                         /*    register.                     */
                                         /* 0: Clear OVTINT status.          */
#define CPLD_SR_PMICINT       (1 << 1)   /* 1: The PMIC interrupt was comes  */
                                         /*    from PMIC.                    */
                                         /* 0: Clear PMICINT status.         */
#define CPLD_SR_OVP           (1 << 0)   /* 0: For VBUS status in over       */
                                         /*    voltage protect.              */
#define CPLD_VR               0x0000C000 /* Version Register                 */
                                         /* B0~B7 all read only.             */
                                         /*                                  */
                                         /*                                  */
#define CPLD_VR_VC_MASK       (0x07)     /* Version code                     */
                                         /* 000 US/Mexico                    */ 
                                         /* 001 Japan                        */
                                         /*                                  */
#define CPLD_VR_VN_MASK       (0x18)     /* Version Number                   */
                                         /*                                  */
#define CPLD_VR_BP_MASK       (0xE0)     /* Board phase                      */
                                         /* 000 EVB                          */
                                         /* 001 EVT                          */
                                         /* 010 DVT                          */
                                         /* 011 PVT                          */
                                         /* 100 PP                           */
                                         /* 101 MP                           */
                                         /* 110 ~ 111 reserve                */
                                         /*                                  */
#define CPLD_REG_END          CPLD_VR    /* CPLD Register end address        */

// Version code
#define US_Mexico  0
#define Japan      1

// Board phase
#define BOARD_PHASE_EVB        0
#define BOARD_PHASE_EVT        1
#define BOARD_PHASE_DVT        2
#define BOARD_PHASE_PVT        3
#define BOARD_PHASE_PP         4
#define BOARD_PHASE_MP         5

/* for src/board_misc.c hal_mmu_init() */
                              /* Actual Base */
#define CPLD_MMU_AB           ((CPLD_BASE & 0xFFF00000) >> 20)
                              /* Virtual Base */
#define CPLD_MMU_VB           CPLD_MMU_AB
                              /* Size in MB */
#define CPLD_MMU_SIZE         ((CPLD_REG_END - CPLD_REG_START + 1 \
                              + SZ_1M - 1) / (SZ_1M))

#define BOARD_FLASH_START	        CS0_BASE_ADDR
#define REDBOOT_IMAGE_SIZE          0x40000

/* KINPO G23 SDRAM is from 0x80000000, 64M */
#define SDRAM_BASE_ADDR             CSD0_BASE_ADDR
#define SDRAM_SIZE                  0x04000000
#define RAM_BANK0_BASE              SDRAM_BASE_ADDR

#define LED_MAX_NUM	2
#define LED_IS_ON(n)    (readw(PBC_BASE+PBC_BCTRL1_CLR) & (1 << (n+6)))
#define TURN_LED_ON(n)  writew((readw(PBC_BASE+PBC_BCTRL1_CLR) | (1 << (n+6))), PBC_BASE+PBC_BCTRL1)
#define TURN_LED_OFF(n) writew((1<<(n+6)), PBC_BASE+PBC_BCTRL1_CLR)


#define BOARD_DEBUG_LED(n) ;
#endif /* CYGONCE_KINPO_G23_H */
