//==========================================================================
//
//      mxc_spi.h
//
//      SPI support on Freescale MXC platforms
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// for more details.
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//
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// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
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//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Kevin Zhang <k.zhang@freescale.com>
// Contributors:
// Date:         2006-08-24
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//==========================================================================

#ifndef __MXC_SPI_H__
#define __MXC_SPI_H__

#define SPI_RX_REG_OFF              0x0
#define SPI_TX_REG_OFF              0x4
#define SPI_CTRL_REG_OFF            0x8
#define SPI_INT_REG_OFF             0xC
#define SPI_STAT_REG_OFF            0x14
#define CSPI_STATREG_RR             (1 << 3)

#if defined(MXC_SPI_VER_0_4)
#define SPI_DMA_REG_OFF             0x10
#define SPI_PERIOD_REG_OFF          0x18
#define SPI_TEST_REG_OFF            0x1C

#define SPI_CTRL_REG_XCH_BIT        (1 << 2)
#define SPI_CTRL_REG_RATE_SH        16  // start from bit 16
#define SPI_CTRL_REG_RATE_WD        3   // 3-bit width

#define SPI_CTRL_REG_BIT_COUNT32    (0x1F << 8)  // 32-bit xfer
#define SPI_CTRL_CS0                (0 << 24)
#define SPI_CTRL_CS1                (1 << 24)
#define SPI_CTRL_CS2                (2 << 24)
#define SPI_CTRL_CS3                (3 << 24)
#define SPI_CTRL_SSPOL_HIGH         (1 << 7)
#define SPI_CTRL_SSCTL_SET          (1 << 6)
#define SPI_CTRL_SCLK_POL_LOW       (1 << 4)
#define SPI_CTRL_MODE_MASTER        (1 << 1)
#define SPI_CTRL_EN                 (1 << 0)

#elif defined(MXC_SPI_VER_0_7)
#define SPI_DMA_REG_OFF             0x10
#define SPI_PERIOD_REG_OFF          0x18
#define SPI_TEST_REG_OFF            0x1C

#define SPI_CTRL_REG_XCH_BIT        (1 << 2)
#define SPI_CTRL_REG_RATE_SH        16  // start from bit 16
#define SPI_CTRL_REG_RATE_WD        3   // 3-bit width

#define SPI_CTRL_REG_BIT_COUNT32    (0x1F << 20)  // 32-bit xfer
#define SPI_CTRL_CS0                (0 << 12)
#define SPI_CTRL_CS1                (1 << 12)
#define SPI_CTRL_CS2                (2 << 12)
#define SPI_CTRL_CS3                (3 << 12)
#define SPI_CTRL_SSPOL_HIGH         (1 << 7)
#define SPI_CTRL_SSCTL_SET          (1 << 6)
#define SPI_CTRL_SCLK_POL_LOW       (1 << 4)
#define SPI_CTRL_MODE_MASTER        (1 << 1)
#define SPI_CTRL_EN                 (1 << 0)

#else

#define SPI_TEST_REG_OFF            0x10
#define SPI_PERIOD_REG_OFF          0x14
#define SPI_DMA_REG_OFF             0x18
#define SPI_RESET_REG_OFF           0x1C

#define SPI_CTRL_REG_XCH_BIT        (1 << 9)
#define SPI_CTRL_REG_RATE_SH        14  // start from bit 14
#define SPI_CTRL_REG_RATE_WD        5   // 5-bit width

#define SPI_CTRL_BURST_EN           (1 << 23)
#define SPI_CTRL_SDHC_SPI_EN        (1 << 22)
#define SPI_CTRL_SWAP_EN            (1 << 21)
#define SPI_CTRL_CS0                (0 << 19)
#define SPI_CTRL_CS1                (1 << 19)
#define SPI_CTRL_CS2                (2 << 19)
#define SPI_CTRL_SSPOL_HIGH         (1 << 8)
#define SPI_CTRL_SSCTL_SET          (1 << 7)
#define SPI_CTRL_SCLK_POL_LOW       (1 << 5)
#define SPI_CTRL_REG_BIT_COUNT32    0x1F   // 32-bit xfer
#define SPI_CTRL_MODE_MASTER        (1 << 11)
#define SPI_CTRL_EN                 (1 << 10)

#endif

int spi_init(unsigned int base, unsigned int baud, unsigned int ctrl_val);
unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
unsigned int spi_xchg_single(unsigned int data, unsigned int base);

#endif				/* __MXC_SPI_H__ */
