/*
 * Copyright 2004-2005 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

/*
 * @file    mxcfb_epson.h
 *
 * @brief Global header file for the MXC Frame buffer 
 * 
 * @ingroup Framebuffer
 */
#ifndef _INCLUDE_MXCFB_EPSON_H_
#define _INCLUDE_MXCFB_EPSON_H_

#include "../drivers/mxc/ipu/ipu.h"

/*
 * Driver name
 */
#define MXCFB_NAME      "MXCFB_EPSON"

/*
 * Bits per pixel defines
 */
#ifdef CONFIG_FB_MXC_16BPP
#define MXCFB_BPP     16
#elif CONFIG_FB_MXC_24BPP
#define MXCFB_BPP     24
#elif CONFIG_FB_MXC_32BPP
#define MXCFB_BPP     32
#endif

/*
 * Different RGB combinations supported
 */
#define RGB_8   (0)
#define RGB_16  (1)
#define RGB_24  (2)
#define RGB_32  (3)
#define NR_RGB  4

/*
 * These are the bitfields for each display depth that we support.
 */
struct mxcfb_rgb {
    uint32_t                pixel_fmt;
    struct fb_bitfield      red;   
    struct fb_bitfield      green;
    struct fb_bitfield      blue;
    struct fb_bitfield      transp;
};

/*!
 * Structure containing the generic framebuffer information.
 */
struct mxcfb_info {
        struct fb_info          fb;             /*!< Framebuffer information */
        struct mxcfb_rgb        *rgb[NR_RGB];   /*!< Bitfields for each 
                                                     display depth 
                                                     that we support */

        uint32_t                cur_pixel_fmt;
        uint32_t                cur_ipu_buf;
        /*
         * These are the addresses we mapped
         * the framebuffer memory region to.
         */
        unsigned long           phys_addr;      /*!< Physical address of 
                                                     Framebuffer */
        unsigned char           *virt_addr;     /*!< Virtual address of 
                                                     Framebuffer */
        uint32_t                map_size;       /*!< Memory map size */

        uint32_t                snoop_window_size;
        
        struct semaphore        flip_sem;
        spinlock_t              fb_lock;
};

/*!
 * Enum defining Epson panel commands.
 */ 
enum {
        DISON = 0xAF,
        DISOFF = 0xAE,
        DISCTL = 0xCA,
        SD_CSET = 0x15,
        SD_PSET = 0x75,
        DATCTL = 0xBC,
        SLPIN = 0x95,
        SLPOUT = 0x94,
        DISNOR = 0xA6,
        RAMWR = 0x5C,
        VOLCTR = 0xC6,
        GCP16 = 0xCC,
        GCP64 = 0xCB,
};

#endif

// M3IF Snooping Configuration Register 0 (M3IFSCFG0) READ/WRITE
#define M3IFSCFG0 IO_ADDRESS(0xB8003028)
// M3IF Snooping Configuration Register 1 (M3IFSCFG1) READ/WRITE
#define M3IFSCFG1 IO_ADDRESS(0xB800302C)
// M3IF Snooping Configuration Register 2 (M3IFSCFG2) READ/WRITE
#define M3IFSCFG2 IO_ADDRESS(0xB8003030)
// M3IF Snooping Status Register 0 (M3IFSSR0) READ/WRITE
#define M3IFSSR0 IO_ADDRESS(0xB8003034)
// M3IF Snooping Status Register 1 (M3IFSSR1)
#define M3IFSSR1 IO_ADDRESS(0xB8003038)
/* Snooping window size can be set according to FB size*/
#define MEM_512K (512*1024)
#define MEM_256K (256*1024)
/* No of equisize segments in Snooping window */
#define NO_SNOOP_SEGS 64
/*ADC IDMA Channel 1 BUSY status bit */
#define IDMAC_CHAN1_BUSY 0x00040000
