/*
 * File Name       : /drivers/video/LCDC.h
 * Function        : LCDC MMIO definitions
 * Release Version : Ver 1.00
 * Release Date    : 2005/05/25
 *
 * Copyright (C) NEC Electronics Corporation 2005
 *
 *
 * This program is free software;you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by Free Softwere
 * Foundation; either version 2 of License, or (at your option) any later
 * version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warrnty of MERCHANTABILITY or FITNESS
 * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; If not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 */
/* LCDC.h : LCDC MMIO definitions for uPD77601	2004/2/28 */

#ifndef _LCDC_H_
#define _LCDC_H_


/*****************************************************************************
 * LCDC MMIO definitions
 *****************************************************************************/

/* from platform.h for uPD77601 */
#define BANK12_BASE	0xc0000000
#define LCDC_OFFSET	0x00040000
#define LCDC_BASE	(BANK12_BASE+LCDC_OFFSET)
#define LCDC_SIZE	SZ_64K

/* from quhw_lcd_reg.h */
//                                                           R/W   Bit  Reset
// Control for LCDC                                          R/W   8:0  0x000
#define LCD_CONTROL             (0x00)

// Update for LCDC Register                                  R/W   0:0  0x0
#define LCD_UPDATE              (0x04)

// LCD Output                                                R/W   1:0  0x0
#define LCD_LCDOUT              (0x08)

// Status for LCDC                                            R    0:0  0x0
#define LCD_STATUS              (0x0C)

// AREA Address for Frame Buffer A                           R/W  31:2  0x0000_0000
#define LCD_AREAADR_A           (0x10)

// AREA Address for Frame Buffer B                           R/W  31:2  0x0000_0000
#define LCD_AREAADR_B           (0x14)

// AREA Address for Frame Buffer C                           R/W  31:2  0x0000_0000
#define LCD_AREAADR_C           (0x18)

// Horizontal OFFSET Size                                    R/W  12:2  0x0000
#define LCD_HOFFSET             (0x1C)

// Horizontal Synchronizing Signal Total Width               R/W  10:0  0x000
#define LCD_HTOTAL              (0x20)

// Horizontal Display Area Width                             R/W  10:4  0x000
#define LCD_HAREA               (0x24)

// Horizontal Synchronizing Signal Edge Point 1              R/W  10:0  0x000
#define LCD_HEDGE1              (0x28)

// Horizontal Synchronizing Signal Edge Point 2              R/W  10:0  0x000
#define LCD_HEDGE2              (0x2C)

// Vertical Synchronizing Signal Total Width                 R/W  10:0  0x000
#define LCD_VTOTAL              (0x30)

// Vertical Display Area Width                               R/W  10:0  0x000
#define LCD_VAREA               (0x34)

// Vertical Synchronizing Signal Edge Point 1                R/W  10:0  0x000
#define LCD_VEDGE1              (0x38)

// Vertical Synchronizing Signal Edge Point 2                R/W  10:0  0x000
#define LCD_VEDGE2              (0x3C)

// Access Bus Select                                         R/W   1:0  0x0
#define LCD_BUSSEL              (0x40)

// Frame Select                                              R/W   3:0  0x0
#define LCD_FRAMESEL            (0x44)

// 2nd Register Read Mode                                    R/W   0:0  0x0
#define LCD_REGREADMODE         (0x48)

// Interrupt Status                                           R    3:0  0x0
#define LCD_INTSTATUS           (0x60)

// Interrupt Raw Status                                       R    3:0  0x0
#define LCD_INTRAWSTATUS        (0x64)

// Interrupt Enable Set                                      R/W   3:0  0x0
#define LCD_INTENSET            (0x68)

// Interrupt Enable Clear                                     W    3:0  0x0
#define LCD_INTENCLR            (0x6C)

// Interrupt Status Clear                                     W    3:0  0x0
#define LCD_INTFFCLR            (0x70)

// DMA Error Respons Address                                 R/W  31:0  0x0
#define LCD_ERRORADR            (0x74)


// LCD Output		0:stop,1or2:start,3:sync source(but data=0 fixed)
#define LCD_LCDOUT_BIT          0x02
#define LCD_LCDOUT_SYNC         0x03

// Access Bus Select                                         R/W   1:0  0x0
#define LCD_BUSSEL_AHB          0x00
#define LCD_BUSSEL_LOCAL        0x01

// IRQ controls
#define	LCD_LCDSTOPMASK_BIT	0x10
#define	LCD_UNDERRUNMASK_BIT	0x08
#define	LCD_DMASTOPMASK_BIT	0x04
#define	LCD_DMAERRMASK_BIT	0x02
#define	LCD_LCDVSMASK_BIT	0x01

#define	LCD_LCDSTOPCLR_BIT	0x10
#define	LCD_UNDERRUNCLR_BIT	0x08
#define	LCD_DMASTOPCLR_BIT	0x04
#define	LCD_DMAERRCLR_BIT	0x02
#define	LCD_LCDVSCLR_BIT	0x01


//------------------------------
// LCD_INTSTATUS
//------------------------------
#define LCD_DMASTOP_BIT		0x00000004
#define LCD_DMASTOP_SFT		0x02

#define LCD_DMAERR_BIT		0x00000002
#define LCD_DMAERR_SFT		0x01

#define LCD_LCDVS_BIT		0x00000001
#define LCD_LCDVS_SFT		0x00

//------------------------------
// LCD_INTENSET
//------------------------------
#define LCD_DMASTOPEN_BIT	0x00000004
#define LCD_DMASTOPEN_SFT	0x02

#define LCD_DMAERREN_BIT	0x00000002
#define LCD_DMAERREN_SFT	0x01

#define LCD_LCDVSEN_BIT		0x00000001
#define LCD_LCDVSEN_SFT		0x00

//------------------------------
// LCD_FRAMESEL
//------------------------------
#define LCD_AREASTATUS_BIT	0x0000000C
#define LCD_AREASTATUS_SFT	0x02
#define LCD_AREASEL_BIT		0x00000003
#define LCD_AREASEL_SFT		0x00


#endif /* _LCDC_H_ */
