/*
 *  File Name	    : linux/include/asm-arm/arch-mp200/pmu.h
 *  Function	    : pmu
 *  Release Version : Ver 1.02
 *  Release Date    : 2006/07/11
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2006
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

/*
 * Copyright 2006,2007 Sony Corporation. 
 */

#ifndef __ASM_ARM_ARCH_MP200_PMU_H
#define __ASM_ARM_ARCH_MP200_PMU_H

#ifdef CONFIG_MP201
#define SMU_GCLKCTRL0_GROUP		0x00000000
#define SMU_GCLKCTRL1_GROUP		0x01000000
#define SMU_GCLKCTRL2_GROUP		0x02000000
#define SMU_GCLKCTRLTST_GROUP		0x05000000

#define SMU_RESETREQ0_GROUP		0x08000000
#define SMU_RESETREQ1A_GROUP		0x09000000
#define SMU_RESETREQ1B_GROUP		0x0A000000
#define SMU_DSP_GROUP			0x0B000000

#define SMU_AHBCLKCTRL0_GROUP		0x10000000
#define SMU_AHBCLKCTRL1_GROUP		0x20000000
#define SMU_APBCLKCTRL_GROUP		0x30000000
#define SMU_CLKCTRL_GROUP		0x40000000

#define SMU_REG_GROUP_MASK		0xff000000
#define SMU_REG_BIT_MASK		0x0000ffff
#define SMU_REG_MAX_BIT_LEN		32
#else
#define SMU_GCLKCTRL0_GROUP		(0 << 16)
#define SMU_GCLKCTRL1_GROUP		(1 << 16)
#define SMU_GCLKCTRL2_GROUP		(2 << 16)
#define SMU_GCLKCTRL3_GROUP		(3 << 16)
#define SMU_SWTTRACECLK_CTRL_GROUP	(4 << 16)

#define SMU_RESETREQ0_GROUP		(8 << 16)
#define SMU_RESETREQ1_GROUP		(9 << 16)

#define SMU_AHBCLKCTRL0_GROUP		(16 << 16)
#define SMU_AHBCLKCTRL1_GROUP		(17 << 16)
#define SMU_APBCLKCTRL_GROUP		(18 << 16)
#define SMU_CLKCTRL_GROUP		(19 << 16)

#define SMU_REG_GROUP_MASK		0xffff0000
#define SMU_REG_BIT_MASK		0x0000ffff
#define SMU_REG_MAX_BIT_LEN		32
#endif				/* CONFIG_MP201 */

/**********************************************************/
/* gatedclock code                                        */
/**********************************************************/
#ifdef CONFIG_MP201
/* clock suply devices code (CTRL0) */
#define MP200_CLOCKGATE_INT_PCLK          (SMU_GCLKCTRL0_GROUP | 0x001A)
#define MP200_CLOCKGATE_FIF_PCLK          (SMU_GCLKCTRL0_GROUP | 0x0019)
#define MP200_CLOCKGATE_FIF_CLK           (SMU_GCLKCTRL0_GROUP | 0x0018)
#define MP200_CLOCKGATE_PB0_CLK           (SMU_GCLKCTRL0_GROUP | 0x0017)
#define MP200_CLOCKGATE_AB1_CLK           (SMU_GCLKCTRL0_GROUP | 0x0016)
#define MP200_CLOCKGATE_SWT_PCLK          (SMU_GCLKCTRL0_GROUP | 0x0015)
#define MP200_CLOCKGATE_SWT_SLAVE_CLK     (SMU_GCLKCTRL0_GROUP | 0x0014)
#define MP200_CLOCKGATE_SWT_DSP_CLK       (SMU_GCLKCTRL0_GROUP | 0x0013)
#define MP200_CLOCKGATE_SWT_PE0_CLK       (SMU_GCLKCTRL0_GROUP | 0x0012)
#define MP200_CLOCKGATE_DMA_TCLK          (SMU_GCLKCTRL0_GROUP | 0x0011)
#define MP200_CLOCKGATE_DMA_PCH2_CLK      (SMU_GCLKCTRL0_GROUP | 0x0010)
#define MP200_CLOCKGATE_DMA_PCH1_CLK      (SMU_GCLKCTRL0_GROUP | 0x000F)
#define MP200_CLOCKGATE_DMA_PCH0_CLK      (SMU_GCLKCTRL0_GROUP | 0x000E)
#define MP200_CLOCKGATE_DMA_PCLK          (SMU_GCLKCTRL0_GROUP | 0x000D)
#define MP200_CLOCKGATE_USB_CLK           (SMU_GCLKCTRL0_GROUP | 0x000C)
#define MP200_CLOCKGATE_TFD_LCLK          (SMU_GCLKCTRL0_GROUP | 0x000B)
#define MP200_CLOCKGATE_TFD_PCLK          (SMU_GCLKCTRL0_GROUP | 0x000A)
#define MP200_CLOCKGATE_LCD_LCLK          (SMU_GCLKCTRL0_GROUP | 0x0009)
#define MP200_CLOCKGATE_LCD_PCLK          (SMU_GCLKCTRL0_GROUP | 0x0008)
#define MP200_CLOCKGATE_LCD_CLK           (SMU_GCLKCTRL0_GROUP | 0x0007)
#define MP200_CLOCKGATE_SRC_CLK           (SMU_GCLKCTRL0_GROUP | 0x0006)
#define MP200_CLOCKGATE_SRM_CLK           (SMU_GCLKCTRL0_GROUP | 0x0005)
#define MP200_CLOCKGATE_ROT_PCLK          (SMU_GCLKCTRL0_GROUP | 0x0004)
#define MP200_CLOCKGATE_ROT_CLK           (SMU_GCLKCTRL0_GROUP | 0x0003)
#define MP200_CLOCKGATE_IMG_PCLK          (SMU_GCLKCTRL0_GROUP | 0x0002)
#define MP200_CLOCKGATE_IMG_CLK           (SMU_GCLKCTRL0_GROUP | 0x0001)
#define MP200_CLOCKGATE_DSP_CLK           (SMU_GCLKCTRL0_GROUP | 0x0000)

/* clock suply devices code (CTRL1) */
#define MP200_CLOCKGATE_MWI_SCLK          (SMU_GCLKCTRL1_GROUP | 0x001D)
#define MP200_CLOCKGATE_MWI_PCLK          (SMU_GCLKCTRL1_GROUP | 0x001C)
#define MP200_CLOCKGATE_PM1_SCLK          (SMU_GCLKCTRL1_GROUP | 0x001B)
#define MP200_CLOCKGATE_PM0_SCLK          (SMU_GCLKCTRL1_GROUP | 0x001A)
#define MP200_CLOCKGATE_PM1_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0019)
#define MP200_CLOCKGATE_PM0_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0018)
#define MP200_CLOCKGATE_TI1_TIN           (SMU_GCLKCTRL1_GROUP | 0x0017)
#define MP200_CLOCKGATE_TI1_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0016)
#define MP200_CLOCKGATE_TI0_TIN           (SMU_GCLKCTRL1_GROUP | 0x0015)
#define MP200_CLOCKGATE_TI0_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0014)
#define MP200_CLOCKGATE_IIC_SCLK          (SMU_GCLKCTRL1_GROUP | 0x0013)
#define MP200_CLOCKGATE_IIC_CLK           (SMU_GCLKCTRL1_GROUP | 0x0012)
#define MP200_CLOCKGATE_IRD_12M_CLK       (SMU_GCLKCTRL1_GROUP | 0x0011)
#define MP200_CLOCKGATE_U70_SCLK          (SMU_GCLKCTRL1_GROUP | 0x0010)
#define MP200_CLOCKGATE_U70_CLK           (SMU_GCLKCTRL1_GROUP | 0x000F)
#define MP200_CLOCKGATE_SPI1_SCLK         (SMU_GCLKCTRL1_GROUP | 0x000E)
#define MP200_CLOCKGATE_SPI1_PCLK         (SMU_GCLKCTRL1_GROUP | 0x000D)
#define MP200_CLOCKGATE_SPI0_SCLK         (SMU_GCLKCTRL1_GROUP | 0x000C)
#define MP200_CLOCKGATE_SPI0_PCLK         (SMU_GCLKCTRL1_GROUP | 0x000B)
#define MP200_CLOCKGATE_NAND_PCLK         (SMU_GCLKCTRL1_GROUP | 0x000A)
#define MP200_CLOCKGATE_NAND_CLK          (SMU_GCLKCTRL1_GROUP | 0x0009)
#define MP200_CLOCKGATE_ATA_DCLK          (SMU_GCLKCTRL1_GROUP | 0x0008)
#define MP200_CLOCKGATE_ATA_CLK           (SMU_GCLKCTRL1_GROUP | 0x0007)
#define MP200_CLOCKGATE_DTV_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0006)
#define MP200_CLOCKGATE_DTV_CLK           (SMU_GCLKCTRL1_GROUP | 0x0005)
#define MP200_CLOCKGATE_NTS_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0004)
#define MP200_CLOCKGATE_NTS_CLK           (SMU_GCLKCTRL1_GROUP | 0x0003)
#define MP200_CLOCKGATE_CAM_SCLK          (SMU_GCLKCTRL1_GROUP | 0x0002)
#define MP200_CLOCKGATE_CAM_PCLK          (SMU_GCLKCTRL1_GROUP | 0x0001)
#define MP200_CLOCKGATE_CAM_CLK           (SMU_GCLKCTRL1_GROUP | 0x0000)

/* clock suply devices code (CTRL2) */
#define MP200_CLOCKGATE_AB0_CLKEN         (SMU_GCLKCTRL2_GROUP | 0x001C)
#define MP200_CLOCKGATE_FIF_CLKEN         (SMU_GCLKCTRL2_GROUP | 0x001B)
#define MP200_CLOCKGATE_SRC_CLKEN         (SMU_GCLKCTRL2_GROUP | 0x001A)
#define MP200_CLOCKGATE_DSP_CLKEN         (SMU_GCLKCTRL2_GROUP | 0x0019)
#define MP200_CLOCKGATE_PE0_CLKEN         (SMU_GCLKCTRL2_GROUP | 0x0018)
/* reserved bit23-19 */
#define MP200_CLOCKGATE_MSP_RTCK          (SMU_GCLKCTRL2_GROUP | 0x0012)
#define MP200_CLOCKGATE_SDR_UDCLK         (SMU_GCLKCTRL2_GROUP | 0x0011)
#define MP200_CLOCKGATE_SDR_LDCLK         (SMU_GCLKCTRL2_GROUP | 0x0010)
#define MP200_CLOCKGATE_REFCLKO           (SMU_GCLKCTRL2_GROUP | 0x000F)
#define MP200_CLOCKGATE_DCV_PCLK          (SMU_GCLKCTRL2_GROUP | 0x000E)
#define MP200_CLOCKGATE_DCV_CLK           (SMU_GCLKCTRL2_GROUP | 0x000D)
#define MP200_CLOCKGATE_CPI_CLK           (SMU_GCLKCTRL2_GROUP | 0x000C)
#define MP200_CLOCKGATE_SDR_ICLK          (SMU_GCLKCTRL2_GROUP | 0x000B)
#define MP200_CLOCKGATE_SDR_CLK           (SMU_GCLKCTRL2_GROUP | 0x000A)
#define MP200_CLOCKGATE_FLA_CLK           (SMU_GCLKCTRL2_GROUP | 0x0009)
#define MP200_CLOCKGATE_STM_SCLK          (SMU_GCLKCTRL2_GROUP | 0x0008)
#define MP200_CLOCKGATE_STM_PCLK          (SMU_GCLKCTRL2_GROUP | 0x0007)
#define MP200_CLOCKGATE_PWM_SCLK          (SMU_GCLKCTRL2_GROUP | 0x0006)
#define MP200_CLOCKGATE_PWM_CLK           (SMU_GCLKCTRL2_GROUP | 0x0005)
#define MP200_CLOCKGATE_MMM_CLK           (SMU_GCLKCTRL2_GROUP | 0x0004)
#define MP200_CLOCKGATE_MSP_PCLK          (SMU_GCLKCTRL2_GROUP | 0x0003)
#define MP200_CLOCKGATE_MSP_SCLK          (SMU_GCLKCTRL2_GROUP | 0x0002)
#define MP200_CLOCKGATE_SDM_CLK           (SMU_GCLKCTRL2_GROUP | 0x0001)
#define MP200_CLOCKGATE_SDM_SCLK          (SMU_GCLKCTRL2_GROUP | 0x0000)

#define MP200_CLOCKGATE_SWT_TRACE_CLK	(SMU_GROUP_SWTTRACECLK_CTRL | 0)

/* clock supply devices code (GCLKCTRLTST) */
#define MP200_CLOCKGATE_GIO_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0009)
#define MP200_CLOCKGATE_GIO_INT_CLK	(SMU_GCLKCTRLTST_GROUP | 0x0008)
#define MP200_CLOCKGATE_PMU_32K_CLK	(SMU_GCLKCTRLTST_GROUP | 0x0007)
#define MP200_CLOCKGATE_PMU_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0006)
#define MP200_CLOCKGATE_SMU_PCLK	(SMU_GCLKCTRLTST_GROUP | 0x0005)
#define MP200_CLOCKGATE_SMU_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0004)
#define MP200_CLOCKGATE_INT_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0003)
#define MP200_CLOCKGATE_PB1_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0002)
#define MP200_CLOCKGATE_AB0_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0001)
#define MP200_CLOCKGATE_PE0_CLK		(SMU_GCLKCTRLTST_GROUP | 0x0000)
#else
#define MP200_CLOCKGATE_CCP_PCLK	(SMU_GCLKCTRL0_GROUP | 31)
#define MP200_CLOCKGATE_CCP_CLK 	(SMU_GCLKCTRL0_GROUP | 30)
#define MP200_CLOCKGATE_NTS_PCLK	(SMU_GCLKCTRL0_GROUP | 29)
#define MP200_CLOCKGATE_NTS_CLK 	(SMU_GCLKCTRL0_GROUP | 28)
#define MP200_CLOCKGATE_DTV_PCLK	(SMU_GCLKCTRL0_GROUP | 27)
#define MP200_CLOCKGATE_CAM_SCLK	(SMU_GCLKCTRL0_GROUP | 26)
#define MP200_CLOCKGATE_DTV_CLK 	(SMU_GCLKCTRL0_GROUP | 25)
#define MP200_CLOCKGATE_DMA_TCLK	(SMU_GCLKCTRL0_GROUP | 24)
#define MP200_CLOCKGATE_DMA_PCH3_CLK	(SMU_GCLKCTRL0_GROUP | 23)
#define MP200_CLOCKGATE_DMA_PCH2_CLK	(SMU_GCLKCTRL0_GROUP | 22)
#define MP200_CLOCKGATE_DMA_PCH1_CLK	(SMU_GCLKCTRL0_GROUP | 21)
#define MP200_CLOCKGATE_DMA_PCH0_CLK	(SMU_GCLKCTRL0_GROUP | 20)
#define MP200_CLOCKGATE_DMA_PCLK	(SMU_GCLKCTRL0_GROUP | 19)
#define MP200_CLOCKGATE_LCD_LCLK	(SMU_GCLKCTRL0_GROUP | 18)
#define MP200_CLOCKGATE_LCD_PCLK	(SMU_GCLKCTRL0_GROUP | 17)
#define MP200_CLOCKGATE_LCD_CLK 	(SMU_GCLKCTRL0_GROUP | 16)
#define MP200_CLOCKGATE_CAM_PCLK	(SMU_GCLKCTRL0_GROUP | 15)
#define MP200_CLOCKGATE_CAM_CLK 	(SMU_GCLKCTRL0_GROUP | 14)
#define MP200_CLOCKGATE_ROT_PCLK	(SMU_GCLKCTRL0_GROUP | 13)
#define MP200_CLOCKGATE_ROT_CLK 	(SMU_GCLKCTRL0_GROUP | 12)
#define MP200_CLOCKGATE_IMG_PCLK	(SMU_GCLKCTRL0_GROUP | 11)
#define MP200_CLOCKGATE_IMG_CLK 	(SMU_GCLKCTRL0_GROUP | 10)
#define MP200_CLOCKGATE_A3D_PCLK	(SMU_GCLKCTRL0_GROUP | 9)
#define MP200_CLOCKGATE_A3D_3DCLK	(SMU_GCLKCTRL0_GROUP | 8)
#define MP200_CLOCKGATE_A3D_CLK 	(SMU_GCLKCTRL0_GROUP | 7)
#define MP200_CLOCKGATE_S1_IM_CLK	(SMU_GCLKCTRL0_GROUP | 6)
#define MP200_CLOCKGATE_DSP_CLKENA	(SMU_GCLKCTRL0_GROUP | 5)
#define MP200_CLOCKGATE_DSP_CLK 	(SMU_GCLKCTRL0_GROUP | 4)
#define MP200_CLOCKGATE_PE2_CLKENA	(SMU_GCLKCTRL0_GROUP | 3)
#define MP200_CLOCKGATE_PE2_CLK 	(SMU_GCLKCTRL0_GROUP | 2)
#define MP200_CLOCKGATE_PE1_CLKENA	(SMU_GCLKCTRL0_GROUP | 1)
#define MP200_CLOCKGATE_PE1_CLK 	(SMU_GCLKCTRL0_GROUP | 0)

#define MP200_CLOCKGATE_MOD1_PCLK	(SMU_GCLKCTRL1_GROUP | 31)
#define MP200_CLOCKGATE_MOD1_SCLK	(SMU_GCLKCTRL1_GROUP | 30)
#define MP200_CLOCKGATE_RMT_CLK 	(SMU_GCLKCTRL1_GROUP | 29)
#define MP200_CLOCKGATE_IRD_12M_CLK	(SMU_GCLKCTRL1_GROUP | 28)
#define MP200_CLOCKGATE_TI3_TIN 	(SMU_GCLKCTRL1_GROUP | 27)
#define MP200_CLOCKGATE_TI2_TIN 	(SMU_GCLKCTRL1_GROUP | 26)
#define MP200_CLOCKGATE_TI1_TIN 	(SMU_GCLKCTRL1_GROUP | 25)
#define MP200_CLOCKGATE_TI1_PCLK	(SMU_GCLKCTRL1_GROUP | 24)
#define MP200_CLOCKGATE_TI0_TIN 	(SMU_GCLKCTRL1_GROUP | 23)
#define MP200_CLOCKGATE_TI0_PCLK	(SMU_GCLKCTRL1_GROUP | 22)
#define MP200_CLOCKGATE_IIC_SCLK	(SMU_GCLKCTRL1_GROUP | 21)
#define MP200_CLOCKGATE_IIC_CLK 	(SMU_GCLKCTRL1_GROUP | 20)
#define MP200_CLOCKGATE_USB_SCLK	(SMU_GCLKCTRL1_GROUP | 19)
#define MP200_CLOCKGATE_USB_CLK 	(SMU_GCLKCTRL1_GROUP | 18)
#define MP200_CLOCKGATE_U73_SCLK	(SMU_GCLKCTRL1_GROUP | 17)
#define MP200_CLOCKGATE_U72_SCLK	(SMU_GCLKCTRL1_GROUP | 16)
#define MP200_CLOCKGATE_U71_SCLK	(SMU_GCLKCTRL1_GROUP | 15)
#define MP200_CLOCKGATE_U70_SCLK	(SMU_GCLKCTRL1_GROUP | 14)
#define MP200_CLOCKGATE_U70_CLK 	(SMU_GCLKCTRL1_GROUP | 13)
#define MP200_CLOCKGATE_INT_PCLK	(SMU_GCLKCTRL1_GROUP | 12)
#define MP200_CLOCKGATE_SRM_CLK 	(SMU_GCLKCTRL1_GROUP | 11)
#define MP200_CLOCKGATE_SRC_CLK 	(SMU_GCLKCTRL1_GROUP | 10)
#define MP200_CLOCKGATE_FIF_PCLK	(SMU_GCLKCTRL1_GROUP | 9)
#define MP200_CLOCKGATE_FIF_CLK 	(SMU_GCLKCTRL1_GROUP | 8)
#define MP200_CLOCKGATE_PB0_CLK 	(SMU_GCLKCTRL1_GROUP | 7)
#define MP200_CLOCKGATE_AB1_CLK 	(SMU_GCLKCTRL1_GROUP | 6)
#define MP200_CLOCKGATE_SWT_PCLK	(SMU_GCLKCTRL1_GROUP | 5)
#define MP200_CLOCKGATE_SWT_SLAVE_CLK	(SMU_GCLKCTRL1_GROUP | 4)
#define MP200_CLOCKGATE_SWT_DSP_CLK	(SMU_GCLKCTRL1_GROUP | 3)
#define MP200_CLOCKGATE_SWT_PE2_CLK	(SMU_GCLKCTRL1_GROUP | 2)
#define MP200_CLOCKGATE_SWT_PE1_CLK	(SMU_GCLKCTRL1_GROUP | 1)
#define MP200_CLOCKGATE_SWT_PE0_CLK	(SMU_GCLKCTRL1_GROUP | 0)

#define MP200_CLOCKGATE_CK12_OUT	(SMU_GCLKCTRL2_GROUP | 31)
#define MP200_CLOCKGATE_LCD_MCMADS_CLK	(SMU_GCLKCTRL2_GROUP | 30)
#define MP200_CLOCKGATE_SP2_SCLK	(SMU_GCLKCTRL2_GROUP | 29)
#define MP200_CLOCKGATE_SP2_PCLK	(SMU_GCLKCTRL2_GROUP | 28)
#define MP200_CLOCKGATE_SP1_SCLK	(SMU_GCLKCTRL2_GROUP | 27)
#define MP200_CLOCKGATE_SP1_PCLK	(SMU_GCLKCTRL2_GROUP | 26)
#define MP200_CLOCKGATE_SP0_SCLK	(SMU_GCLKCTRL2_GROUP | 25)
#define MP200_CLOCKGATE_SP0_PCLK	(SMU_GCLKCTRL2_GROUP | 24)
#define MP200_CLOCKGATE_MOD0_CLK	(SMU_GCLKCTRL2_GROUP | 23)
#define MP200_CLOCKGATE_MOD0_SCLK	(SMU_GCLKCTRL2_GROUP | 22)
#define MP200_CLOCKGATE_SRC_CLKENA	(SMU_GCLKCTRL2_GROUP | 21)
#define MP200_CLOCKGATE_FIF_CLKENA	(SMU_GCLKCTRL2_GROUP | 20)
#define MP200_CLOCKGATE_FLA_CLK 	(SMU_GCLKCTRL2_GROUP | 19)
#define MP200_CLOCKGATE_DDR_DQS_O_F	(SMU_GCLKCTRL2_GROUP | 18)
#define MP200_CLOCKGATE_DDR_DQS_O3	(SMU_GCLKCTRL2_GROUP | 17)
#define MP200_CLOCKGATE_DDR_DQS_O2	(SMU_GCLKCTRL2_GROUP | 16)
#define MP200_CLOCKGATE_DDR_DQS_O1	(SMU_GCLKCTRL2_GROUP | 15)
#define MP200_CLOCKGATE_DDR_DQS_O0	(SMU_GCLKCTRL2_GROUP | 14)
#define MP200_CLOCKGATE_DDR_MCLK	(SMU_GCLKCTRL2_GROUP | 13)
#define MP200_CLOCKGATE_DDR_M4CLKW	(SMU_GCLKCTRL2_GROUP | 12)
#define MP200_CLOCKGATE_DDR_M1CLKR	(SMU_GCLKCTRL2_GROUP | 11)
#define MP200_CLOCKGATE_DDR_CLK 	(SMU_GCLKCTRL2_GROUP | 10)
#define MP200_CLOCKGATE_MMM_CLK 	(SMU_GCLKCTRL2_GROUP | 9)
#define MP200_CLOCKGATE_MWI_SCLK	(SMU_GCLKCTRL2_GROUP | 8)
#define MP200_CLOCKGATE_MWI_PCLK	(SMU_GCLKCTRL2_GROUP | 7)
#define MP200_CLOCKGATE_SI1_SCLK	(SMU_GCLKCTRL2_GROUP | 6)
#define MP200_CLOCKGATE_SI0_SCLK	(SMU_GCLKCTRL2_GROUP | 5)
#define MP200_CLOCKGATE_SI0_PCLK	(SMU_GCLKCTRL2_GROUP | 4)
#define MP200_CLOCKGATE_PM2_SCLK	(SMU_GCLKCTRL2_GROUP | 3)
#define MP200_CLOCKGATE_PM1_SCLK	(SMU_GCLKCTRL2_GROUP | 2)
#define MP200_CLOCKGATE_PM0_SCLK	(SMU_GCLKCTRL2_GROUP | 1)
#define MP200_CLOCKGATE_PM0_PCLK	(SMU_GCLKCTRL2_GROUP | 0)

#define MP200_CLOCKGATE_TG5_TIN 	(SMU_GCLKCTRL3_GROUP | 5)
#define MP200_CLOCKGATE_TG4_TIN 	(SMU_GCLKCTRL3_GROUP | 4)
#define MP200_CLOCKGATE_TG3_TIN 	(SMU_GCLKCTRL3_GROUP | 3)
#define MP200_CLOCKGATE_TG2_TIN 	(SMU_GCLKCTRL3_GROUP | 2)
#define MP200_CLOCKGATE_TG1_TIN 	(SMU_GCLKCTRL3_GROUP | 1)
#define MP200_CLOCKGATE_TG0_TIN 	(SMU_GCLKCTRL3_GROUP | 0)

#define MP200_CLOCKGATE_SWT_TRACE_CLK	(SMU_SWTTRACECLK_CTRL_GROUP | 0)
#endif				/* CONFIG_MP201 */

/**********************************************************/
/* reset device code                                      */
/**********************************************************/
#ifdef CONFIG_MP201
/* L0 devices */
#define MP200_RESETDEVICE_USB		(SMU_RESETREQ0_GROUP | 0x0009)
#define MP200_RESETDEVICE_TFD		(SMU_RESETREQ0_GROUP | 0x0008)
#define MP200_RESETDEVICE_GIO		(SMU_RESETREQ0_GROUP | 0x0007)
#define MP200_RESETDEVICE_PMU		(SMU_RESETREQ0_GROUP | 0x0006)
#define MP200_RESETDEVICE_INT		(SMU_RESETREQ0_GROUP | 0x0005)
#define MP200_RESETDEVICE_PWM		(SMU_RESETREQ0_GROUP | 0x0004)
#define MP200_RESETDEVICE_MWI		(SMU_RESETREQ0_GROUP | 0x0003)
#define MP200_RESETDEVICE_TW0		(SMU_RESETREQ0_GROUP | 0x0002)
#define MP200_RESETDEVICE_TI0		(SMU_RESETREQ0_GROUP | 0x0001)
#define MP200_RESETDEVICE_LCD		(SMU_RESETREQ0_GROUP | 0x0000)

/* L1A devices */
#define MP200_RESETDEVICE_DCV		(SMU_RESETREQ1A_GROUP | 0x0012)
#define MP200_RESETDEVICE_SDR		(SMU_RESETREQ1A_GROUP | 0x0011)
#define MP200_RESETDEVICE_CPI		(SMU_RESETREQ1A_GROUP | 0x0010)
#define MP200_RESETDEVICE_NAND		(SMU_RESETREQ1A_GROUP | 0x000F)
#define MP200_RESETDEVICE_ATA		(SMU_RESETREQ1A_GROUP | 0x000E)
#define MP200_RESETDEVICE_DTV		(SMU_RESETREQ1A_GROUP | 0x000D)
#define MP200_RESETDEVICE_NTS		(SMU_RESETREQ1A_GROUP | 0x000C)
#define MP200_RESETDEVICE_CAM		(SMU_RESETREQ1A_GROUP | 0x000B)
#define MP200_RESETDEVICE_FIF		(SMU_RESETREQ1A_GROUP | 0x000A)
#define MP200_RESETDEVICE_PB1		(SMU_RESETREQ1A_GROUP | 0x0009)
#define MP200_RESETDEVICE_PB0		(SMU_RESETREQ1A_GROUP | 0x0008)
#define MP200_RESETDEVICE_AB1		(SMU_RESETREQ1A_GROUP | 0x0007)
#define MP200_RESETDEVICE_AB0		(SMU_RESETREQ1A_GROUP | 0x0006)
#define MP200_RESETDEVICE_SWT		(SMU_RESETREQ1A_GROUP | 0x0005)
#define MP200_RESETDEVICE_DMA		(SMU_RESETREQ1A_GROUP | 0x0004)
#define MP200_RESETDEVICE_SRC		(SMU_RESETREQ1A_GROUP | 0x0003)
#define MP200_RESETDEVICE_ROT		(SMU_RESETREQ1A_GROUP | 0x0002)
#define MP200_RESETDEVICE_IMG		(SMU_RESETREQ1A_GROUP | 0x0001)
#define MP200_RESETDEVICE_PE0		(SMU_RESETREQ1A_GROUP | 0x0000)

/* L1B devices */
#define MP200_RESETDEVICE_STM		(SMU_RESETREQ1B_GROUP | 0x000F)
#define MP200_RESETDEVICE_MMM		(SMU_RESETREQ1B_GROUP | 0x000E)
#define MP200_RESETDEVICE_MSP		(SMU_RESETREQ1B_GROUP | 0x000D)
#define MP200_RESETDEVICE_SDM		(SMU_RESETREQ1B_GROUP | 0x000C)
#define MP200_RESETDEVICE_PM1		(SMU_RESETREQ1B_GROUP | 0x000B)
#define MP200_RESETDEVICE_PM0		(SMU_RESETREQ1B_GROUP | 0x000A)
#define MP200_RESETDEVICE_TW1		(SMU_RESETREQ1B_GROUP | 0x0009)
#define MP200_RESETDEVICE_TI5		(SMU_RESETREQ1B_GROUP | 0x0008)
#define MP200_RESETDEVICE_TI4		(SMU_RESETREQ1B_GROUP | 0x0007)
#define MP200_RESETDEVICE_TI3		(SMU_RESETREQ1B_GROUP | 0x0006)
#define MP200_RESETDEVICE_TI2		(SMU_RESETREQ1B_GROUP | 0x0005)
#define MP200_RESETDEVICE_TI1		(SMU_RESETREQ1B_GROUP | 0x0004)
#define MP200_RESETDEVICE_IIC		(SMU_RESETREQ1B_GROUP | 0x0003)
#define MP200_RESETDEVICE_U70		(SMU_RESETREQ1B_GROUP | 0x0002)
#define MP200_RESETDEVICE_SPI1		(SMU_RESETREQ1B_GROUP | 0x0001)
#define MP200_RESETDEVICE_SPI0		(SMU_RESETREQ1B_GROUP | 0x0000)
#else
#define MP200_RESETDEVICE_DDR		(SMU_RESETREQ0_GROUP | 29)
#define MP200_RESETDEVICE_IIC		(SMU_RESETREQ0_GROUP | 28)
#define MP200_RESETDEVICE_USB		(SMU_RESETREQ0_GROUP | 27)
#define MP200_RESETDEVICE_U73		(SMU_RESETREQ0_GROUP | 26)
#define MP200_RESETDEVICE_U72		(SMU_RESETREQ0_GROUP | 25)
#define MP200_RESETDEVICE_U71		(SMU_RESETREQ0_GROUP | 24)
#define MP200_RESETDEVICE_U70		(SMU_RESETREQ0_GROUP | 23)
#define MP200_RESETDEVICE_GIO		(SMU_RESETREQ0_GROUP | 22)
#define MP200_RESETDEVICE_INT		(SMU_RESETREQ0_GROUP | 21)
#define MP200_RESETDEVICE_MOD0		(SMU_RESETREQ0_GROUP | 20)
#define MP200_RESETDEVICE_SRC		(SMU_RESETREQ0_GROUP | 19)
#define MP200_RESETDEVICE_FIF		(SMU_RESETREQ0_GROUP | 18)
#define MP200_RESETDEVICE_PB1		(SMU_RESETREQ0_GROUP | 17)
#define MP200_RESETDEVICE_PB0		(SMU_RESETREQ0_GROUP | 16)
#define MP200_RESETDEVICE_AB1		(SMU_RESETREQ0_GROUP | 15)
#define MP200_RESETDEVICE_AB0		(SMU_RESETREQ0_GROUP | 14)
#define MP200_RESETDEVICE_SWT		(SMU_RESETREQ0_GROUP | 13)
#define MP200_RESETDEVICE_DMA		(SMU_RESETREQ0_GROUP | 12)
#define MP200_RESETDEVICE_LCD		(SMU_RESETREQ0_GROUP | 11)
#define MP200_RESETDEVICE_CAM		(SMU_RESETREQ0_GROUP | 10)
#define MP200_RESETDEVICE_ROT		(SMU_RESETREQ0_GROUP | 9)
#define MP200_RESETDEVICE_IMG		(SMU_RESETREQ0_GROUP | 8)
#define MP200_RESETDEVICE_A3D		(SMU_RESETREQ0_GROUP | 7)
#define MP200_RESETDEVICE_DSP_H 	(SMU_RESETREQ0_GROUP | 6)
#define MP200_RESETDEVICE_PE2_ETM	(SMU_RESETREQ0_GROUP | 5)
#define MP200_RESETDEVICE_PE2		(SMU_RESETREQ0_GROUP | 4)
#define MP200_RESETDEVICE_PE1_ETM	(SMU_RESETREQ0_GROUP | 3)
#define MP200_RESETDEVICE_PE1		(SMU_RESETREQ0_GROUP | 2)
#define MP200_RESETDEVICE_PE0_ETM	(SMU_RESETREQ0_GROUP | 1)
#define MP200_RESETDEVICE_PE0		(SMU_RESETREQ0_GROUP | 0)

#define MP200_RESETDEVICE_TG5		(SMU_RESETREQ1_GROUP | 29)
#define MP200_RESETDEVICE_TG4		(SMU_RESETREQ1_GROUP | 28)
#define MP200_RESETDEVICE_TG3		(SMU_RESETREQ1_GROUP | 27)
#define MP200_RESETDEVICE_TG2		(SMU_RESETREQ1_GROUP | 26)
#define MP200_RESETDEVICE_TG1		(SMU_RESETREQ1_GROUP | 25)
#define MP200_RESETDEVICE_TG0		(SMU_RESETREQ1_GROUP | 24)
#define MP200_RESETDEVICE_SP2		(SMU_RESETREQ1_GROUP | 23)
#define MP200_RESETDEVICE_SP1		(SMU_RESETREQ1_GROUP | 22)
#define MP200_RESETDEVICE_SP0		(SMU_RESETREQ1_GROUP | 21)
#define MP200_RESETDEVICE_CCP		(SMU_RESETREQ1_GROUP | 20)
#define MP200_RESETDEVICE_NTS		(SMU_RESETREQ1_GROUP | 19)
#define MP200_RESETDEVICE_DTV		(SMU_RESETREQ1_GROUP | 18)
#define MP200_RESETDEVICE_PMU		(SMU_RESETREQ1_GROUP | 17)
#define MP200_RESETDEVICE_MMM		(SMU_RESETREQ1_GROUP | 16)
#define MP200_RESETDEVICE_MWI		(SMU_RESETREQ1_GROUP | 15)
#define MP200_RESETDEVICE_SI1		(SMU_RESETREQ1_GROUP | 14)
#define MP200_RESETDEVICE_SI0		(SMU_RESETREQ1_GROUP | 13)
#define MP200_RESETDEVICE_PM2		(SMU_RESETREQ1_GROUP | 12)
#define MP200_RESETDEVICE_PM1		(SMU_RESETREQ1_GROUP | 11)
#define MP200_RESETDEVICE_PM0		(SMU_RESETREQ1_GROUP | 10)
#define MP200_RESETDEVICE_MOD1		(SMU_RESETREQ1_GROUP | 9)
#define MP200_RESETDEVICE_RMT		(SMU_RESETREQ1_GROUP | 8)
#define MP200_RESETDEVICE_TW3		(SMU_RESETREQ1_GROUP | 7)
#define MP200_RESETDEVICE_TW2		(SMU_RESETREQ1_GROUP | 6)
#define MP200_RESETDEVICE_TW1		(SMU_RESETREQ1_GROUP | 5)
#define MP200_RESETDEVICE_TW0		(SMU_RESETREQ1_GROUP | 4)
#define MP200_RESETDEVICE_TI3		(SMU_RESETREQ1_GROUP | 3)
#define MP200_RESETDEVICE_TI2		(SMU_RESETREQ1_GROUP | 2)
#define MP200_RESETDEVICE_TI1		(SMU_RESETREQ1_GROUP | 1)
#define MP200_RESETDEVICE_TI0		(SMU_RESETREQ1_GROUP | 0)
#endif				/* CONFIG_MP201 */

#ifdef CONFIG_MP201
/* auto-clock devices code (AHBCLKCTRL0)                  */
#define MP200_CLKCTRL_DCV                                 (SMU_AHBCLKCTRL0_GROUP | 0x000D)
#define MP200_CLKCTRL_CPI                                 (SMU_AHBCLKCTRL0_GROUP | 0x000C)
#define MP200_CLKCTRL_NAND                                (SMU_AHBCLKCTRL0_GROUP | 0x000B)
#define MP200_CLKCTRL_DTV                                 (SMU_AHBCLKCTRL0_GROUP | 0x000A)
#define MP200_CLKCTRL_NTS                                 (SMU_AHBCLKCTRL0_GROUP | 0x0009)
#define MP200_CLKCTRL_CAM                                 (SMU_AHBCLKCTRL0_GROUP | 0x0008)
#define MP200_CLKCTRL_DMAPCH2                             (SMU_AHBCLKCTRL0_GROUP | 0x0007)
#define MP200_CLKCTRL_DMAPCH1                             (SMU_AHBCLKCTRL0_GROUP | 0x0006)
#define MP200_CLKCTRL_DMAPCH0                             (SMU_AHBCLKCTRL0_GROUP | 0x0005)
#define MP200_CLKCTRL_LCD                                 (SMU_AHBCLKCTRL0_GROUP | 0x0004)
#define MP200_CLKCTRL_ROT                                 (SMU_AHBCLKCTRL0_GROUP | 0x0003)
#define MP200_CLKCTRL_IMG                                 (SMU_AHBCLKCTRL0_GROUP | 0x0002)
#define MP200_CLKCTRL_DSP                                 (SMU_AHBCLKCTRL0_GROUP | 0x0001)
#define MP200_CLKCTRL_PE0                                 (SMU_AHBCLKCTRL0_GROUP | 0x0000)

/* auto-clock devices code (AHBCLKCTRL1) */
#define MP200_CLKCTRL_MMM                                 (SMU_AHBCLKCTRL1_GROUP | 0x0008)
#define MP200_CLKCTRL_SRC                                 (SMU_AHBCLKCTRL1_GROUP | 0x0007)
#define MP200_CLKCTRL_SDR                                 (SMU_AHBCLKCTRL1_GROUP | 0x0006)
#define MP200_CLKCTRL_FIF                                 (SMU_AHBCLKCTRL1_GROUP | 0x0005)
#define MP200_CLKCTRL_PB1                                 (SMU_AHBCLKCTRL1_GROUP | 0x0004)
#define MP200_CLKCTRL_PB0                                 (SMU_AHBCLKCTRL1_GROUP | 0x0003)
#define MP200_CLKCTRL_AB1                                 (SMU_AHBCLKCTRL1_GROUP | 0x0002)
#define MP200_CLKCTRL_AB0                                 (SMU_AHBCLKCTRL1_GROUP | 0x0001)
#define MP200_CLKCTRL_SWT                                 (SMU_AHBCLKCTRL1_GROUP | 0x0000)

/* auto-clock devices code (APBCLKCTRL) */
#define MP200_CLKCTRL_PWMCLK                              (SMU_APBCLKCTRL_GROUP | 0x0015 )
#define MP200_CLKCTRL_DCVPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0014 )
#define MP200_CLKCTRL_GIOPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0013 )
#define MP200_CLKCTRL_MWIPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0012 )
#define MP200_CLKCTRL_TI1PCLK                             (SMU_APBCLKCTRL_GROUP | 0x0011 )
#define MP200_CLKCTRL_TI0PCLK                             (SMU_APBCLKCTRL_GROUP | 0x0010 )
#define MP200_CLKCTRL_SPI1PCLK                            (SMU_APBCLKCTRL_GROUP | 0x000F )
#define MP200_CLKCTRL_SPI0PCLK                            (SMU_APBCLKCTRL_GROUP | 0x000E )
#define MP200_CLKCTRL_NANDPCLK                            (SMU_APBCLKCTRL_GROUP | 0x000D )
#define MP200_CLKCTRL_DTVPCLK                             (SMU_APBCLKCTRL_GROUP | 0x000C )
#define MP200_CLKCTRL_NTSPCLK                             (SMU_APBCLKCTRL_GROUP | 0x000B )
#define MP200_CLKCTRL_CAMPCLK                             (SMU_APBCLKCTRL_GROUP | 0x000A )
#define MP200_CLKCTRL_PMUCLK                              (SMU_APBCLKCTRL_GROUP | 0x0009 )
#define MP200_CLKCTRL_SMUPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0008 )
#define MP200_CLKCTRL_INTPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0007 )
#define MP200_CLKCTRL_FIFPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0006 )
#define MP200_CLKCTRL_SWTPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0005 )
#define MP200_CLKCTRL_DMAPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0004 )
#define MP200_CLKCTRL_TFDPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0003 )
#define MP200_CLKCTRL_LCDPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0002 )
#define MP200_CLKCTRL_ROTPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0001 )
#define MP200_CLKCTRL_IMGPCLK                             (SMU_APBCLKCTRL_GROUP | 0x0000 )

/* auto-clock devices code (CLKCTRL) */
#define MP200_CLKCTRL_SPI1SCLKLP                          (SMU_CLKCTRL_GROUP | 0x0002)
#define MP200_CLKCTRL_SPI0SCLKLP                          (SMU_CLKCTRL_GROUP | 0x0001)
#define MP200_CLKCTRL_MWISCLKLP                           (SMU_CLKCTRL_GROUP | 0x0000)
#else
#define MP200_CLKCTRL_CCP		(SMU_AHBCLKCTRL0_GROUP | 16)
#define MP200_CLKCTRL_NTS		(SMU_AHBCLKCTRL0_GROUP | 15)
#define MP200_CLKCTRL_DTV		(SMU_AHBCLKCTRL0_GROUP | 14)
#define MP200_CLKCTRL_DMAPCH3		(SMU_AHBCLKCTRL0_GROUP | 13)
#define MP200_CLKCTRL_DMAPCH2		(SMU_AHBCLKCTRL0_GROUP | 12)
#define MP200_CLKCTRL_DMAPCH1		(SMU_AHBCLKCTRL0_GROUP | 11)
#define MP200_CLKCTRL_DMAPCH0		(SMU_AHBCLKCTRL0_GROUP | 10)
#define MP200_CLKCTRL_LCD		(SMU_AHBCLKCTRL0_GROUP | 9)
#define MP200_CLKCTRL_CAM		(SMU_AHBCLKCTRL0_GROUP | 8)
#define MP200_CLKCTRL_ROT		(SMU_AHBCLKCTRL0_GROUP | 7)
#define MP200_CLKCTRL_IMG		(SMU_AHBCLKCTRL0_GROUP | 6)
#define MP200_CLKCTRL_A3D		(SMU_AHBCLKCTRL0_GROUP | 5)
#define MP200_CLKCTRL_MSE		(SMU_AHBCLKCTRL0_GROUP | 4)
#define MP200_CLKCTRL_DSP		(SMU_AHBCLKCTRL0_GROUP | 3)
#define MP200_CLKCTRL_PE2		(SMU_AHBCLKCTRL0_GROUP | 2)
#define MP200_CLKCTRL_PE1		(SMU_AHBCLKCTRL0_GROUP | 1)
#define MP200_CLKCTRL_PE0		(SMU_AHBCLKCTRL0_GROUP | 0)

#define MP200_CLKCTRL_SRC		(SMU_AHBCLKCTRL1_GROUP | 7)
#define MP200_CLKCTRL_DDR		(SMU_AHBCLKCTRL1_GROUP | 6)
#define MP200_CLKCTRL_FIF		(SMU_AHBCLKCTRL1_GROUP | 5)
#define MP200_CLKCTRL_PB1		(SMU_AHBCLKCTRL1_GROUP | 4)
#define MP200_CLKCTRL_PB0		(SMU_AHBCLKCTRL1_GROUP | 3)
#define MP200_CLKCTRL_AB1		(SMU_AHBCLKCTRL1_GROUP | 2)
#define MP200_CLKCTRL_AB0		(SMU_AHBCLKCTRL1_GROUP | 1)
#define MP200_CLKCTRL_SWT		(SMU_AHBCLKCTRL1_GROUP | 0)

#define MP200_CLKCTRL_GIOPCLK		(SMU_APBCLKCTRL_GROUP | 21)
#define MP200_CLKCTRL_SP2PCLK		(SMU_APBCLKCTRL_GROUP | 20)
#define MP200_CLKCTRL_SP1PCLK		(SMU_APBCLKCTRL_GROUP | 19)
#define MP200_CLKCTRL_PMUCLK		(SMU_APBCLKCTRL_GROUP | 18)
#define MP200_CLKCTRL_SWTPCLK		(SMU_APBCLKCTRL_GROUP | 17)
#define MP200_CLKCTRL_SP0PCLK		(SMU_APBCLKCTRL_GROUP | 16)
#define MP200_CLKCTRL_CCPPCLK		(SMU_APBCLKCTRL_GROUP | 15)
#define MP200_CLKCTRL_SMUPCLK		(SMU_APBCLKCTRL_GROUP | 14)
#define MP200_CLKCTRL_MWIPCLK		(SMU_APBCLKCTRL_GROUP | 13)
#define MP200_CLKCTRL_SI0PCLK		(SMU_APBCLKCTRL_GROUP | 12)
#define MP200_CLKCTRL_NTSPCLK		(SMU_APBCLKCTRL_GROUP | 11)
#define MP200_CLKCTRL_DTVPCLK		(SMU_APBCLKCTRL_GROUP | 10)
#define MP200_CLKCTRL_TI1PCLK		(SMU_APBCLKCTRL_GROUP | 9)
#define MP200_CLKCTRL_TI0PCLK		(SMU_APBCLKCTRL_GROUP | 8)
#define MP200_CLKCTRL_INTPCLK		(SMU_APBCLKCTRL_GROUP | 7)
#define MP200_CLKCTRL_FIFPCLK		(SMU_APBCLKCTRL_GROUP | 6)
#define MP200_CLKCTRL_DMAPCLK		(SMU_APBCLKCTRL_GROUP | 5)
#define MP200_CLKCTRL_LCDPCLK		(SMU_APBCLKCTRL_GROUP | 4)
#define MP200_CLKCTRL_CAMPCLK		(SMU_APBCLKCTRL_GROUP | 3)
#define MP200_CLKCTRL_ROTPCLK		(SMU_APBCLKCTRL_GROUP | 2)
#define MP200_CLKCTRL_IMGPCLK		(SMU_APBCLKCTRL_GROUP | 1)
#define MP200_CLKCTRL_A3DPCLK		(SMU_APBCLKCTRL_GROUP | 0)

#define MP200_CLKCTRL_SP2SCLK		(SMU_CLKCTRL_GROUP | 4)
#define MP200_CLKCTRL_SP1SCLK		(SMU_CLKCTRL_GROUP | 3)
#define MP200_CLKCTRL_SP0SCLK		(SMU_CLKCTRL_GROUP | 2)
#define MP200_CLKCTRL_MWISCLK		(SMU_CLKCTRL_GROUP | 1)
#define MP200_CLKCTRL_DQS		(SMU_CLKCTRL_GROUP | 0)
#endif				/* CONFIG_MP201 */

extern int mp200_pmu_open_clockgate(unsigned int clkbit);
extern int mp200_pmu_close_clockgate(unsigned int clkbit);
extern int mp200_pmu_get_clockgate(unsigned int clkbit);

extern int mp200_pmu_reset_device(unsigned int rstdev);
extern int mp200_pmu_unreset_device(unsigned int rstdev);
extern int mp200_pmu_get_reset_status(unsigned int rstdev);

extern int mp200_pmu_clkctrl_on(unsigned int dev);
extern int mp200_pmu_clkctrl_off(unsigned int dev);
extern int mp200_pmu_get_clkctrl_status(unsigned int dev);

/* 2006.07.13 has */
#ifdef CONFIG_SONY_ICX1087
extern int mp200_pmu_write_reg(unsigned int addr, unsigned int data, unsigned int mask);
extern int mp200_pmu_read_reg(unsigned int addr, unsigned int *data);
#endif


#endif				/* __ASM_ARM_ARCH_MP200_PMU_H */
