/*
 *  File Name       : drivers/mtd/nand/mp200_nand.h
 *  Function        : MP200-NAND interface
 *  Release Version : Ver 0.20
 *  Release Date    : 2006/04/18
 *
 *  Copyright (C) NEC Electronics Corporation 2006
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

/*
 * Copyright 2006,2007 Sony Corporation. 
 */

#ifndef __DRIVERS_MTD_NAND_MP200_NAND_H
#define __DRIVERS_MTD_NAND_MP200_NAND_H

#include <asm/arch/hardware.h>


/* device name */
#define NAND_NAME		"mp200_nand"
#define NAND_DIR		"nand"


/* -------- */

#define NAND_ATBAR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0000)	/* R/W */
#define NAND_ATCR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0004)	/* R   */
#define NAND_ATACR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0008)	/* R   */
#define NAND_MSR		(IO_ADDRESS(MP200_NAND_BASE) + 0x000C)	/* R/W */
#define NAND_INTSTATUS		(IO_ADDRESS(MP200_NAND_BASE) + 0x0010)	/* R   */
#define NAND_RAWINTSTATUS	(IO_ADDRESS(MP200_NAND_BASE) + 0x0014)	/* R   */
#define NAND_INTENSET		(IO_ADDRESS(MP200_NAND_BASE) + 0x0018)	/* R/W */
#define NAND_INTENCLR		(IO_ADDRESS(MP200_NAND_BASE) + 0x001C)	/* W   */
#define NAND_AHB_INTFFCLR	(IO_ADDRESS(MP200_NAND_BASE) + 0x0020)	/* W   */
#define NAND_FRD		(IO_ADDRESS(MP200_NAND_BASE) + 0x0024)	/* R   */

/* -------- */

#define NAND_CONTROL		(IO_ADDRESS(MP200_NAND_BASE) + 0x0200)	/* R/W */
#define NAND_ESR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0204)	/* R   */
#define NAND_EICR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0208)	/* R/W */
#define NAND_EIRSR		(IO_ADDRESS(MP200_NAND_BASE) + 0x020C)	/* R   */
#define NAND_EICLR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0210)	/* W   */
#define NAND_CECR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0214)	/* R/W */
#define NAND_CDR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0218)	/* R/W */
#define NAND_SCCR		(IO_ADDRESS(MP200_NAND_BASE) + 0x021C)	/* R/W  */
#define NAND_CHA_CWR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0220)	/* W   */
#define NAND_CHA_AWR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0224)	/* W   */
#define NAND_CHA_LAWR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0228)	/* W   */
#define NAND_CHA_DWR		(IO_ADDRESS(MP200_NAND_BASE) + 0x022C)	/* W   */
#define NAND_CHA_DRR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0230)	/* W   */
#define NAND_CHA_BDWR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0234)	/* W   */
#define NAND_CHA_BDRR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0238)	/* W   */
#define NAND_CHA_FPSCR		(IO_ADDRESS(MP200_NAND_BASE) + 0x023C)	/* W   */
#define NAND_CHA_FWSR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0240)	/* R   */
/* 0x244-29F reserved */
#define NAND_RSSR		(IO_ADDRESS(MP200_NAND_BASE) + 0x02A0)	/* R   */
/* 0x2A4-2BF reserved */
#define NAND_CHA_RSEV0R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02C0)	/* R   */
#define NAND_CHA_RSEV1R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02C4)	/* R   */
#define NAND_CHA_RSEV2R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02C8)	/* R   */
#define NAND_CHA_RSEV3R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02CC)	/* R   */
#define NAND_CHA_RSEP0R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02D0)	/* R   */
#define NAND_CHA_RSEP1R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02D4)	/* R   */
#define NAND_CHA_RSEP2R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02D8)	/* R   */
#define NAND_CHA_RSEP3R		(IO_ADDRESS(MP200_NAND_BASE) + 0x02DC)	/* R   */
#define NAND_CHA_SDH0R		(IO_ADDRESS(MP200_NAND_BASE) + 0x0300)	/* R/W */
#define NAND_CHA_SDH1R		(IO_ADDRESS(MP200_NAND_BASE) + 0x0304)	/* R/W */
#define NAND_CHA_SDH2R		(IO_ADDRESS(MP200_NAND_BASE) + 0x0308)	/* R/W */
#define NAND_CHA_SDH3R		(IO_ADDRESS(MP200_NAND_BASE) + 0x030C)	/* R   */
#define NAND_CHA_SDH4R		(IO_ADDRESS(MP200_NAND_BASE) + 0x0310)	/* R   */
#define NAND_CHA_SDH5R		(IO_ADDRESS(MP200_NAND_BASE) + 0x0314)	/* R   */
#define NAND_CHA_SDH6R		(IO_ADDRESS(MP200_NAND_BASE) + 0x0318)	/* R   */
#define NAND_CHA_SDH7R		(IO_ADDRESS(MP200_NAND_BASE) + 0x031C)	/* R   */

/* -------- */

#define NAND_PSCR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0400)	/* R/W */
#define NAND_IPR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0404)	/* R/W */
#define NAND_IIDR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0408)	/* R   */
/* 0x40C-41F reserved */
#define NAND_ITR_00H		(IO_ADDRESS(MP200_NAND_BASE) + 0x0420)	/* R/W */
/* 0x424-0x49C ITR01-1F */
#define NAND_ITR_06H		(IO_ADDRESS(MP200_NAND_BASE) + 0x0438)	/* R/W */

/* -------- */

#define NAND_LCR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0600)	/* R/W */
#define NAND_LICR		(IO_ADDRESS(MP200_NAND_BASE) + 0x060C)	/* R/W */
#define NAND_LIRSR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0610)	/* R   */
#define NAND_LICLR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0614)	/* W   */
#define NAND_TCCR		(IO_ADDRESS(MP200_NAND_BASE) + 0x0620)	/* R   */

/* -------- */

/* PSC commands */
#define PSC_CMD_CESEL		0x0a
#define PSC_CMD_OUTCMDA		0x10
#define PSC_CMD_OUTADRSA	0x12
#define PSC_CMD_OUTLTADRSA	0x14
#define PSC_CMD_CHKSTA		0x1e
#define PSC_CMD_DMAST		0xc0
#define PSC_CMD_INT		0xd0
#define PSC_CMD_STOPINT		0xd1
#define PSC_CMD_BTS		0xe0
#define PSC_CMD_WAITFOR		0xf0
#define PSC_CMD_WAITTC		0xf1
#define PSC_CMD_WAITBUSY	0xf2
#define PSC_CMD_WAITRDY		0xf3



#define MASK_PCTL_NAND		0x00000180
#define PCTL_SEL_FLOAT		0x00000000
#define PCTL_SEL_NAND		0x00000080
#define PCTL_SEL_ATA		0x00000100

#define MASK_GCTL_NAND		0x00000078
#define MASK_FCTL_NAND		0x00000007

#define PCTL_NAND_RBZ1_BIT	0x00000040
#ifdef CONFIG_SONY_ICX1087 /* 2006.05.18 yam */
#define PCTL_NAND_DATA_BIT	0x00000008
#define GPIOCORE_GPIO_NAND_XWP		GPIOCORE_GPIO_P47
#endif
#endif

