/*
 *  File Name       : linux/include/asm-arm/arch-mp200/hardware.h
 *  Function        : hardware
 *  Release Version : Ver 1.02
 *  Release Date    : 2006/02/22
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2006
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#ifndef __ASM_ARM_ARCH_MP200_HARDWARE_H
#define __ASM_ARM_ARCH_MP200_HARDWARE_H

#include <asm/sizes.h>
#include <asm/arch/io.h>

#define VA_PEID			IO_ADDRESS(MP200_PEID_BASE)
#define VA_INTC			IO_ADDRESS(MP200_INTC_BASE)

#ifdef CONFIG_MP201
/* ************************************************************************
 *   MP201 address map
 * ***********************************************************************/

/*
 *  MP201 memory map
 */

/* BANK 3 -- DRAM(FIFO0) [SDRAM] */
#define MP200_BANK3_BASE	0x30000000
#define MP200_SDRAM_OFFSET	(0x00000000)
#define MP200_SDRAM_SIZE	SZ_32M

#define MP200_SDRAM_BASE	(MP200_BANK3_BASE+MP200_SDRAM_OFFSET)

/* BANK 4 -- APB0 [Peripherals] */
#define MP200_BANK4_BASE	0x40000000

#define MP200_TI1_OFFSET	0x00000000
#define MP200_TI1_SIZE  	SZ_64K
#define MP200_TI2_OFFSET	0x00010000
#define MP200_TI2_SIZE  	SZ_64K
#define MP200_TI3_OFFSET	0x00020000
#define MP200_TI3_SIZE  	SZ_64K
#define MP200_TI4_OFFSET	0x00030000
#define MP200_TI4_SIZE  	SZ_64K
#define MP200_TI5_OFFSET	0x00040000
#define MP200_TI5_SIZE  	SZ_64K
#define MP200_WDT1_OFFSET	0x00050000
#define MP200_WDT1_SIZE		SZ_64K
#define MP200_DCV_OFFSET	0x00060000
#define MP200_DCV_SIZE		SZ_64K
#define MP200_FIFO_OFFSET	0x00070000
#define MP200_FIFO_SIZE		SZ_64K
#define MP200_ROTATOR_OFFSET	0x00080000
#define MP200_ROTATOR_SIZE  	SZ_64K
#define MP200_DMAC_OFFSET	0x00090000
#define MP200_DMAC_SIZE		SZ_64K
#define MP200_IMAGEPROC_OFFSET	0x000a0000
#define MP200_IMAGEPROC_SIZE	SZ_64K
#define MP200_CAMERA_OFFSET	0x000b0000
#define MP200_CAMERA_SIZE	SZ_64K
#define MP200_PCM0_OFFSET	0x000c0000
#define MP200_PCM0_SIZE		SZ_64K
#define MP200_PCM1_OFFSET	0x000d0000
#define MP200_PCM1_SIZE		SZ_64K
#define MP200_NTSC_OFFSET	0x00100000
#define MP200_NTSC_SIZE		SZ_64K
#define MP200_PB0_OFFSET	0x00110000
#define MP200_PB0_SIZE		SZ_64K
#define MP200_SWT_OFFSET	0x00120000
#define MP200_SWT_SIZE		SZ_64K
#define MP200_SP0_OFFSET	0x00130000
#define MP200_SP0_SIZE		SZ_64K
#define MP200_SP1_OFFSET	0x00140000
#define MP200_SP1_SIZE		SZ_64K
#define MP200_DTV_OFFSET	0x00160000
#define MP200_DTV_SIZE		SZ_64K
#define MP200_NAND_OFFSET	0x00170000
#define MP200_NAND_SIZE		SZ_64K
#define MP200_STM_OFFSET	0x00200000
#define MP200_STM_SIZE		SZ_64K
#define MP200_DMAC_S0_OFFSET	0x08020000
#define MP200_DMAC_S0_SIZE	SZ_64K
#define MP200_FIFO_S1_OFFSET	0x0c000000
#define MP200_FIFO_S1_SIZE	SZ_64K

/* BANK 5 -- ASYNC1 [Peripherals] */
#define MP200_BANK5_BASE	0x50000000

#define MP200_UART0_OFFSET	0x00000000
#define MP200_UART0_SIZE	SZ_64K
#define MP200_I2C_OFFSET	0x00040000
#define MP200_I2C_SIZE		SZ_64K
#define MP200_AB1_OFFSET	0x00070000
#define MP200_AB1_SIZE  	SZ_64K
#define MP200_SDM_S0_OFFSET	0x08000000
#define MP200_SDM_S0_SIZE	SZ_64K

/* BANK 6 -- Reserved */
#define MP200_BANK6_BASE	0x60000000

/* BANK 7 -- Reserved */
#define MP200_BANK7_BASE	0x70000000

/* BANK 8 -- Local */
#define MP200_BANK8_BASE	0x80000000

#define MP200_PEID_OFFSET	0x00000000
#define MP200_PEID_SIZE		SZ_4K
#define MP200_PEID_BASE		(MP200_BANK8_BASE+MP200_PEID_OFFSET)

/* BANK 9 -- Reserved */
#define MP200_BANK9_BASE	0x90000000

/* BANK 10 -- SRAM */
#define MP200_BANK10_BASE	0xa0000000

#define MP200_SSRAM_OFFSET	0x00000000
#define MP200_SSRAM_SIZE	SZ_256K
#define MP200_SSRAM_BASE	(MP200_BANK10_BASE+MP200_SSRAM_OFFSET)

/* BANK 11 -- K602 Slave */
#define MP200_BANK11_BASE	0xb0000000

#define MP200_USB_OFFSET	0x00000000
#define MP200_USB_SIZE		SZ_64K
#define MP200_ATA_OFFSET	0x00010000
#define MP200_ATA_SIZE  	SZ_128K
#define MP200_MSP_OFFSET	0x00030000
#define MP200_MSP_SIZE  	SZ_64K
#define MP200_MMM_OFFSET	0x00040000
#define MP200_MMM_SIZE  	SZ_64K

/* BANK 12 -- APB1 */
#define MP200_BANK12_BASE	0xc0000000

#define MP200_TI0_OFFSET	0x00000000
#define MP200_TI0_SIZE  	SZ_64K
#define MP200_WDT0_OFFSET	0x00010000
#define MP200_WDT0_SIZE		SZ_64K
#define MP200_INTC_OFFSET	0x00020000
#define MP200_INTC_SIZE		SZ_64K
#define MP200_TFD_OFFSET	0x00030000
#define MP200_TFD_SIZE		SZ_64K
#define MP200_LCDC_OFFSET	0x00040000
#define MP200_LCDC_SIZE		SZ_64K
#define MP200_GPIO_OFFSET	0x00050000
#define MP200_GPIO_SIZE		SZ_64K
#define MP200_PWM_OFFSET	0x00060000
#define MP200_PWM_SIZE		SZ_64K
#define MP200_PB1_OFFSET	0x00090000
#define MP200_PB1_SIZE		SZ_64K
#define MP200_PMU_OFFSET	0x08000000
#define MP200_PMU_SIZE		SZ_64K
#define MP200_SMU_S0_OFFSET	0x08010000
#define MP200_SMU_S0_SIZE	SZ_64K
#define MP200_uWIRE_OFFSET	0x08020000
#define MP200_uWIRE_SIZE	SZ_64K
#define MP200_SMU_S1_OFFSET	0x0c000000
#define MP200_SMU_S1_SIZE	SZ_64K
#define MP200_INTC_S1_OFFSET	0x0c010000
#define MP200_INTC_S1_SIZE	SZ_64K

/* BANK 13 -- Reserved */
#define MP200_BANK13_BASE	0xd0000000

/* BANK 14 -- Reserved */
#define MP200_BANK14_BASE	0xe0000000

/* BANK 15 -- PE0 ROM */
#define MP200_BANK15_BASE	0xf0000000

#define MP200_BOOTROM_OFFSET	0x0fff0000
#define MP200_BOOTROM_SIZE	SZ_32K
#define MP200_BOOTROM_BASE	(MP200_BANK15_BASE+MP200_BOOTROM_OFFSET)

/*
 * Peripherals
 */

#define MP200_TI1_BASE  	(MP200_BANK4_BASE+MP200_TI1_OFFSET)
#define MP200_TI2_BASE  	(MP200_BANK4_BASE+MP200_TI2_OFFSET)
#define MP200_TI3_BASE  	(MP200_BANK4_BASE+MP200_TI3_OFFSET)
#define MP200_TI4_BASE  	(MP200_BANK4_BASE+MP200_TI4_OFFSET)
#define MP200_TI5_BASE  	(MP200_BANK4_BASE+MP200_TI5_OFFSET)
#define MP200_WDT1_BASE		(MP200_BANK4_BASE+MP200_WDT1_OFFSET)
#define MP200_DCV_BASE  	(MP200_BANK4_BASE+MP200_DCV_OFFSET)
#define MP200_FIFO_BASE		(MP200_BANK4_BASE+MP200_FIFO_OFFSET)
#define MP200_ROTATOR_BASE	(MP200_BANK4_BASE+MP200_ROTATOR_OFFSET)
#define MP200_DMAC_BASE		(MP200_BANK4_BASE+MP200_DMAC_OFFSET)

#define MP200_IMAGEPROC_BASE	(MP200_BANK4_BASE+MP200_IMAGEPROC_OFFSET)
#define MP200_CAMERA_BASE	(MP200_BANK4_BASE+MP200_CAMERA_OFFSET)
#define MP200_PCM0_BASE		(MP200_BANK4_BASE+MP200_PCM0_OFFSET)
#define MP200_PCM1_BASE		(MP200_BANK4_BASE+MP200_PCM1_OFFSET)
#define MP200_NTSC_BASE		(MP200_BANK4_BASE+MP200_NTSC_OFFSET)
#define MP200_PB0_BASE		(MP200_BANK4_BASE+MP200_PB0_OFFSET)
#define MP200_SWT_BASE		(MP200_BANK4_BASE+MP200_SWT_OFFSET)

#define MP200_SP0_BASE		(MP200_BANK4_BASE+MP200_SP0_OFFSET)
#define MP200_SP1_BASE		(MP200_BANK4_BASE+MP200_SP1_OFFSET)
#define MP200_DTV_BASE		(MP200_BANK4_BASE+MP200_DTV_OFFSET)
#define MP200_NAND_BASE		(MP200_BANK4_BASE+MP200_NAND_OFFSET)
#define MP200_STM_BASE		(MP200_BANK4_BASE+MP200_STM_OFFSET)

#define MP200_DMAC_S0_BASE	(MP200_BANK4_BASE+MP200_DMAC_S0_OFFSET)
#define MP200_FIFO_S1_BASE	(MP200_BANK4_BASE+MP200_FIFO_S1_OFFSET)

#define MP200_UART0_BASE	(MP200_BANK5_BASE+MP200_UART0_OFFSET)
#define MP200_I2C_BASE		(MP200_BANK5_BASE+MP200_I2C_OFFSET)
#define MP200_AB1_BASE  	(MP200_BANK5_BASE+MP200_AB1_OFFSET)
#define MP200_SDM_S0_BASE	(MP200_BANK5_BASE+MP200_SDM_S0_OFFSET)

#define MP200_USB_BASE		(MP200_BANK11_BASE+MP200_USB_OFFSET)
#define MP200_ATA_BASE		(MP200_BANK11_BASE+MP200_ATA_OFFSET)
#define MP200_MSP_BASE		(MP200_BANK11_BASE+MP200_MSP_OFFSET)
#define MP200_MMM_BASE		(MP200_BANK11_BASE+MP200_MMM_OFFSET)

#define MP200_TI0_BASE  	(MP200_BANK12_BASE+MP200_TI0_OFFSET)
#define MP200_WDT0_BASE		(MP200_BANK12_BASE+MP200_WDT0_OFFSET)
#define MP200_INTC_BASE		(MP200_BANK12_BASE+MP200_INTC_OFFSET)
#define MP200_TFD_BASE		(MP200_BANK12_BASE+MP200_TFD_OFFSET)
#define MP200_LCDC_BASE		(MP200_BANK12_BASE+MP200_LCDC_OFFSET)
#define MP200_GPIO_BASE		(MP200_BANK12_BASE+MP200_GPIO_OFFSET)
#define MP200_PWM_BASE		(MP200_BANK12_BASE+MP200_PWM_OFFSET)
#define MP200_PB1_BASE		(MP200_BANK12_BASE+MP200_PB1_OFFSET)
#define MP200_PMU_BASE		(MP200_BANK12_BASE+MP200_PMU_OFFSET)
#define MP200_SMU_S0_BASE	(MP200_BANK12_BASE+MP200_SMU_S0_OFFSET)
#define MP200_uWIRE_BASE	(MP200_BANK12_BASE+MP200_uWIRE_OFFSET)
#define MP200_SMU_S1_BASE	(MP200_BANK12_BASE+MP200_SMU_S1_OFFSET)
#define MP200_INTC_S1_BASE	(MP200_BANK12_BASE+MP200_INTC_S1_OFFSET)

/*
 *  MP201 Interrupt Controller
 */

/* INTC internal offset for CPU, DSP, MSE, CPI. */
#define MP200_INTC_IT0_OFFSET		0x00000000
#define MP200_INTC_ID_OFFSET		0x00004000
#define MP200_INTC_S1_IM_OFFSET		0x0000e000
#define MP200_INTC_IT3_OFFSET		0x00008000

#define MP200_INTC_IT0_BASE		(MP200_INTC_BASE+MP200_INTC_IT0_OFFSET)
#define MP200_INTC_ID_BASE		(MP200_INTC_BASE+MP200_INTC_ID_OFFSET)
#define MP200_INTC_S1_IM_BASE		(MP200_INTC_S1_BASE+MP200_INTC_S1_IM_OFFSET)
#define MP200_INTC_IT3_BASE		(MP200_INTC_BASE+MP200_INTC_IT3_OFFSET)

/*
 * operational register offset
 */
/* interrupt enable */
#define	MP200_INTC_ITy_IEN0_OFFSET	0x00000000
#define	MP200_INTC_ITy_IEN1_OFFSET	0x00000004
/* interrupt enable monitor */
#define	MP200_INTC_ITy_IMN0_OFFSET	0x00000000
#define	MP200_INTC_ITy_IMN1_OFFSET	0x00000004
/* interrupt disable */
#define	MP200_INTC_ITy_IDS0_OFFSET	0x00000008
#define	MP200_INTC_ITy_IDS1_OFFSET	0x0000000c
/* interrupt raw status */
#define	MP200_INTC_ITy_RAW0_OFFSET	0x00000010
#define	MP200_INTC_ITy_RAW1_OFFSET	0x00000014
/* interrupt maskable status */
#define	MP200_INTC_ITy_MST0_OFFSET	0x00000018
#define	MP200_INTC_ITy_MST1_OFFSET	0x0000001c
/* interrupt cause clear */
#define	MP200_INTC_ITy_IIR0_OFFSET	0x00000024
#define	MP200_INTC_ITy_IIR1_OFFSET	0x00000028
/* interrupt status set */
#define	MP200_INTC_ITy_IIS_OFFSET	0x0000002C

/* inter processor communication - set */
#define	MP200_INTC_ITy_IPI0_SET_OFFSET	0x00000030
#define	MP200_INTC_ITy_IPID_SET_OFFSET	0x00000034
#define	MP200_INTC_ITy_IPIM_SET_OFFSET	0x00000038
#define	MP200_INTC_ITy_IPI3_SET_OFFSET	0x0000003c
/* inter processor communication - monitor */
#define	MP200_INTC_ITy_IPI0_MON_OFFSET	0x00000030
#define	MP200_INTC_ITy_IPID_MON_OFFSET	0x00000034
#define	MP200_INTC_ITy_IPIM_MON_OFFSET	0x00000038
#define	MP200_INTC_ITy_IPI3_MON_OFFSET	0x0000003c
/* inter processor communication - clear */
#define	MP200_INTC_IT0_IPIz_CLR_OFFSET	0x00000050
#define	MP200_INTC_ITD_IPIz_CLR_OFFSET	0x00000054
#define	MP200_INTC_ITM_IPIz_CLR_OFFSET	0x00000058
#define	MP200_INTC_IT3_IPIz_CLR_OFFSET	0x0000005c

/* FIQ interrupt enable */
#define	MP200_INTC_ITy_FIE_OFFSET	0x00000080
/* FIQ interrupt monitor */
#define	MP200_INTC_ITy_FIM_OFFSET	0x00000080
/* FIQ interrupt disable */
#define	MP200_INTC_ITy_FID_OFFSET	0x00000084
/* interrupt vector base */
#define	MP200_INTC_ID_VBS_OFFSET	0x00000090
/* interrupt output clear */
#define	MP200_INTC_ID_CLR_OFFSET	0x00000094

/* eg, unsigned long va = IO_ADDRESS (MP200_INTC_BASE) + MP200_INTC_IT0_xxx;*/
/*
 * register map for CPU
 */
#define MP200_INTC_IT0_IEN0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_IT0_IEN1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_IT0_IMN0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_IT0_IMN1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_IT0_IDS0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_IT0_IDS1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_IT0_RAW0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_IT0_RAW1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_IT0_MST0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_IT0_MST1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_IT0_IIR0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IIR0_OFFSET)
#define MP200_INTC_IT0_IIR1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IIR1_OFFSET)
#define MP200_INTC_IT0_IIS	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IIS_OFFSET)
#define MP200_INTC_IT0_IPID_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPID_SET_OFFSET)
#define MP200_INTC_IT0_IPIM_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPIM_SET_OFFSET)
#define MP200_INTC_IT0_IPI3_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPI3_SET_OFFSET)
#define MP200_INTC_IT0_IPID_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPID_MON_OFFSET)
#define MP200_INTC_IT0_IPIM_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPIM_MON_OFFSET)
#define MP200_INTC_IT0_IPI3_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPI3_MON_OFFSET)
#define MP200_INTC_IT0_IPID_CLR	(MP200_INTC_ID_OFFSET +MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_IPIM_CLR	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_IPI3_CLR	(MP200_INTC_IT3_OFFSET+MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_FIE	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_FIE_OFFSET)
#define MP200_INTC_IT0_FID	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_FID_OFFSET)

/*
 * register map for DSP
 */
#define MP200_INTC_ID_IEN0	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_ID_IEN1	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_ID_IMN0	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_ID_IMN1	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_ID_IDS0	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_ID_IDS1	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_ID_RAW0	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_ID_RAW1	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_ID_MST0	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_ID_MST1	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_ID_IIR0	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IIR0_OFFSET)
#define MP200_INTC_ID_IIR1	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IIR1_OFFSET)
#define MP200_INTC_ID_IIS	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IIS_OFFSET)
#define MP200_INTC_ID_IPI0_SET	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_ID_IPI3_SET	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IPI3_SET_OFFSET)
#define MP200_INTC_ID_IPI0_MON	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_ID_IPI3_MON	(MP200_INTC_ID_OFFSET +MP200_INTC_ITy_IPI3_MON_OFFSET)
#define MP200_INTC_ID_IPI0_CLR	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITD_IPIz_CLR_OFFSET)
#define MP200_INTC_ID_IPI3_CLR	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITD_IPIz_CLR_OFFSET)
#define MP200_INTC_ID_VBS	(MP200_INTC_ID_OFFSET +MP200_INTC_ID_VBS_OFFSET)
#define MP200_INTC_ID_CLR	(MP200_INTC_ID_OFFSET +MP200_INTC_ID_CLR_OFFSET)

/*
 * register map for S1_IM
 */
#define MP200_INTC_S1_IM_IEN0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_S1_IM_IEN1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_S1_IM_IMN0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_S1_IM_IMN1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_S1_IM_IDS0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_S1_IM_IDS1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_S1_IM_RAW0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_S1_IM_RAW1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_S1_IM_MST0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_S1_IM_MST1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_S1_IM_IIR0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IIR0_OFFSET)
#define MP200_INTC_S1_IM_IIR1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IIR1_OFFSET)
#define MP200_INTC_S1_IM_IIS		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IIS_OFFSET)
#define MP200_INTC_S1_IM_IPI0_SET	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_S1_IM_IPI0_MON	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_S1_IM_IPI0_CLR	(MP200_INTC_IT0_OFFSET  +MP200_INTC_ITM_IPIz_CLR_OFFSET)

/*
 * register map for CPI
 */
#define MP200_INTC_IT3_IEN0	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_IT3_IEN1	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_IT3_IMN0	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_IT3_IMN1	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_IT3_IDS0	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_IT3_IDS1	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_IT3_RAW0	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_IT3_RAW1	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_IT3_MST0	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_IT3_MST1	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_IT3_IIR0	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IIR0_OFFSET)
#define MP200_INTC_IT3_IIR1	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IIR1_OFFSET)
#define MP200_INTC_IT3_IIS	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IIS_OFFSET)
#define MP200_INTC_IT3_IPI0_SET	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_IT3_IPID_SET	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IPID_SET_OFFSET)
#define MP200_INTC_IT3_IPI0_MON	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_IT3_IPID_MON	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_IPID_MON_OFFSET)
#define MP200_INTC_IT3_IPI0_CLR	(MP200_INTC_IT0_OFFSET+MP200_INTC_IT3_IPIz_CLR_OFFSET)
#define MP200_INTC_IT3_IPID_CLR	(MP200_INTC_ID_OFFSET +MP200_INTC_IT3_IPIz_CLR_OFFSET)
#define MP200_INTC_IT3_FIE	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_FIE_OFFSET)
#define MP200_INTC_IT3_FIM	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_FIM_OFFSET)
#define MP200_INTC_IT3_FID	(MP200_INTC_IT3_OFFSET+MP200_INTC_ITy_FID_OFFSET)

#else
/* ************************************************************************
 *   MP200 address map
 * ***********************************************************************/

/*
 *  MP200 memory map
 */

/* BANK 3 -- DRAM(FIFO0) [SDRAM] */
#define MP200_BANK3_BASE	0x30000000
#define MP200_SDRAM_OFFSET	(0x00000000)
#define MP200_SDRAM_SIZE	SZ_64M

#define MP200_SDRAM_BASE	(MP200_BANK3_BASE+MP200_SDRAM_OFFSET)

/* BANK 4 -- APB0 [Peripherals] */
#define MP200_BANK4_BASE	0x40000000

#define MP200_TIMER1_OFFSET	0x00000000
#define MP200_TIMER1_SIZE	SZ_64K
#define MP200_TIMER2_OFFSET	0x00010000
#define MP200_TIMER2_SIZE	SZ_64K
#define MP200_TIMER3_OFFSET	0x00020000
#define MP200_TIMER3_SIZE	SZ_64K
#define MP200_WDT1_OFFSET	0x00030000
#define MP200_WDT1_SIZE		SZ_64K
#define MP200_WDT2_OFFSET	0x00040000
#define MP200_WDT2_SIZE		SZ_64K
#define MP200_WDT3_OFFSET	0x00050000
#define MP200_WDT3_SIZE		SZ_64K
#define MP200_3DACC_OFFSET	0x00060000
#define MP200_3DACC_SIZE	SZ_64K
#define MP200_FIFO_OFFSET	0x00070000
#define MP200_FIFO_SIZE		SZ_64K
#define MP200_ROTATOR_OFFSET	0x00080000
#define MP200_ROTATOR_SIZE	SZ_64K
#define MP200_DMAC_OFFSET	0x00090000
#define MP200_DMAC_SIZE		SZ_64K
#define MP200_IMAGEPROC_OFFSET	0x000a0000
#define MP200_IMAGEPROC_SIZE	SZ_64K
#define MP200_CAMERA_OFFSET	0x000b0000
#define MP200_CAMERA_SIZE	SZ_64K
#define MP200_PCM0_OFFSET	0x000c0000
#define MP200_PCM0_SIZE		SZ_64K
#define MP200_PCM1_OFFSET	0x000d0000
#define MP200_PCM1_SIZE		SZ_64K
#define MP200_PCM2_OFFSET	0x000e0000
#define MP200_PCM2_SIZE		SZ_64K
#define MP200_MOD1_OFFSET	0x000f0000
#define MP200_MOD1_SIZE		SZ_64K
#define MP200_NTSC_OFFSET	0x00100000
#define MP200_NTSC_SIZE		SZ_64K
#define MP200_PB0_OFFSET	0x00110000
#define MP200_PB0_SIZE		SZ_64K
#define MP200_SWT_OFFSET	0x00120000
#define MP200_SWT_SIZE		SZ_64K
#define MP200_SP1_OFFSET	0x00130000
#define MP200_SP1_SIZE		SZ_64K
#define MP200_SP2_OFFSET	0x00140000
#define MP200_SP2_SIZE		SZ_64K
#define MP200_DTV_OFFSET	0x00150000
#define MP200_DTV_SIZE		SZ_64K
#define MP200_CCP_OFFSET	0x00160000
#define MP200_CCP_SIZE		SZ_64K
#define MP200_RMT_OFFSET	0x00170000
#define MP200_RMT_SIZE		SZ_64K
#define MP200_SP0_OFFSET	0x00180000
#define MP200_SP0_SIZE		SZ_64K
#define MP200_TG0_OFFSET	0x00190000
#define MP200_TG0_SIZE		SZ_64K
#define MP200_TG1_OFFSET	0x001a0000
#define MP200_TG1_SIZE		SZ_64K
#define MP200_TG2_OFFSET	0x001b0000
#define MP200_TG2_SIZE		SZ_64K
#define MP200_TG3_OFFSET	0x001c0000
#define MP200_TG3_SIZE		SZ_64K
#define MP200_TG4_OFFSET	0x001d0000
#define MP200_TG4_SIZE		SZ_64K
#define MP200_TG5_OFFSET	0x001e0000
#define MP200_TG5_SIZE		SZ_64K
#define MP200_MMM_S0_OFFSET	0x08000000
#define MP200_MMM_S0_SIZE	SZ_64K
#define MP200_DMAC_S0_OFFSET	0x08020000
#define MP200_DMAC_S0_SIZE	SZ_64K
#define MP200_FIFO_S1_OFFSET	0x0c000000
#define MP200_FIFO_S1_SIZE	SZ_64K

/* BANK 5 -- ASYNC1 [Peripherals] */
#define MP200_BANK5_BASE	0x50000000

#define MP200_UART0_OFFSET	0x00000000
#define MP200_UART0_SIZE	SZ_64K
#define MP200_UART1_OFFSET	0x00010000
#define MP200_UART1_SIZE	SZ_64K
#define MP200_UART2_OFFSET	0x00020000
#define MP200_UART2_SIZE	SZ_64K
#define MP200_I2C_OFFSET	0x00040000
#define MP200_I2C_SIZE		SZ_64K
#define MP200_ASYNC1_OFFSET	0x00070000
#define MP200_ASYNC1_SIZE	SZ_64K
#define MP200_SDIP_S0_OFFSET	0x08000000
#define MP200_SDIP_S0_SIZE	SZ_64K
#define MP200_UART3_S1_OFFSET	0x0c000000
#define MP200_UART3_S1_SIZE	SZ_64K

/* BANK 6 -- AHB Slave */
#define MP200_BANK6_BASE	0x60000000

#define MP200_USB_OFFSET	0x00000000
#define MP200_USB_SIZE		SZ_64K

/* BANK 7 -- Reserved */
#define MP200_BANK7_BASE	0x70000000

/* BANK 8 -- Local */
#define MP200_BANK8_BASE	0x80000000

#define MP200_PEID_OFFSET	0x00000000
#define MP200_PEID_SIZE		SZ_4K
#define MP200_PEID_BASE		(MP200_BANK8_BASE+MP200_PEID_OFFSET)

/* BANK 9 -- Reserved */
#define MP200_BANK9_BASE	0x90000000

/* BANK 10 -- SRAM */
#define MP200_BANK10_BASE	0xa0000000

#define MP200_SSRAM_OFFSET	0x00000000
#define MP200_SSRAM_SIZE	SZ_512K
#define MP200_SSRAM_BASE	(MP200_BANK10_BASE+MP200_SSRAM_OFFSET)

/* BANK 11 -- K602 Slave */
#define MP200_BANK11_BASE	0xb0000000

#define MP200_DSPINST_OFFSET	0x00000000
#define MP200_DSPINST_SIZE	SZ_64K
#define MP200_DSPMEM_OFFSET	0x00100000
#define MP200_DSPMEM_SIZE	SZ_64K
#define MP200_DSPINST_BASE	(MP200_BANK11_BASE+MP200_DSPINST_OFFSET)
#define MP200_DSPMEM_BASE	(MP200_BANK11_BASE+MP200_DSPMEM_OFFSET)

/* BANK 12 -- APB1 */
#define MP200_BANK12_BASE	0xc0000000

#define MP200_TIMER0_OFFSET	0x00000000
#define MP200_TIMER0_SIZE	SZ_64K
#define MP200_WDT0_OFFSET	0x00010000
#define MP200_WDT0_SIZE		SZ_64K
#define MP200_INTC_OFFSET	0x00020000
#define MP200_INTC_SIZE		SZ_64K
#define MP200_LCDC_OFFSET	0x00040000
#define MP200_LCDC_SIZE		SZ_64K
#define MP200_GPIO_OFFSET	0x00050000
#define MP200_GPIO_SIZE		SZ_64K
#define MP200_SIO0_OFFSET	0x00070000
#define MP200_SIO0_SIZE		SZ_64K
#define MP200_SIO1_OFFSET	0x00080000
#define MP200_SIO1_SIZE		SZ_64K
#define MP200_PB1_OFFSET	0x00090000
#define MP200_PB1_SIZE		SZ_64K
#define MP200_PMU_OFFSET	0x08000000
#define MP200_PMU_SIZE		SZ_64K
#define MP200_SMU_S0_OFFSET	0x08010000
#define MP200_SMU_S0_SIZE	SZ_64K
#define MP200_uWIRE_OFFSET	0x08020000
#define MP200_uWIRE_SIZE	SZ_64K
#define MP200_SMU_S1_OFFSET	0x0c000000
#define MP200_SMU_S1_SIZE	SZ_64K
#define MP200_INTC_S1_OFFSET	0x0c010000
#define MP200_INTC_S1_SIZE	SZ_64K

/* BANK 13 -- Reserved */
#define MP200_BANK13_BASE	0xd0000000

/* BANK 14 -- Reserved */
#define MP200_BANK14_BASE	0xe0000000

/* BANK 15 -- PE0 ROM */
#define MP200_BANK15_BASE	0xf0000000

#define MP200_BOOTROM_OFFSET	0x0fff0000
#define MP200_BOOTROM_SIZE	SZ_64K
#define MP200_BOOTROM_BASE	(MP200_BANK15_BASE+MP200_BOOTROM_OFFSET)

/*
 * Peripherals
 */

#define MP200_TIMER1_BASE	(MP200_BANK4_BASE+MP200_TIMER1_OFFSET)
#define MP200_TIMER2_BASE	(MP200_BANK4_BASE+MP200_TIMER2_OFFSET)
#define MP200_TIMER3_BASE	(MP200_BANK4_BASE+MP200_TIMER3_OFFSET)
#define MP200_WDT1_BASE		(MP200_BANK4_BASE+MP200_WDT1_OFFSET)
#define MP200_WDT2_BASE		(MP200_BANK4_BASE+MP200_WDT2_OFFSET)
#define MP200_WDT3_BASE		(MP200_BANK4_BASE+MP200_WDT3_OFFSET)
#define MP200_3DACC_BASE	(MP200_BANK4_BASE+MP200_3DACC_OFFSET)
#define MP200_FIFO_BASE		(MP200_BANK4_BASE+MP200_FIFO_OFFSET)
#define MP200_ROTATOR_BASE	(MP200_BANK4_BASE+MP200_ROTATOR_OFFSET)
#define MP200_DMAC_BASE		(MP200_BANK4_BASE+MP200_DMAC_OFFSET)

#define MP200_IMAGEPROC_BASE	(MP200_BANK4_BASE+MP200_IMAGEPROC_OFFSET)
#define MP200_CAMERA_BASE	(MP200_BANK4_BASE+MP200_CAMERA_OFFSET)
#define MP200_PCM0_BASE		(MP200_BANK4_BASE+MP200_PCM0_OFFSET)
#define MP200_PCM1_BASE		(MP200_BANK4_BASE+MP200_PCM1_OFFSET)
#define MP200_PCM2_BASE		(MP200_BANK4_BASE+MP200_PCM2_OFFSET)
#define MP200_MOD1_BASE		(MP200_BANK4_BASE+MP200_MOD1_OFFSET)
#define MP200_NTSC_BASE		(MP200_BANK4_BASE+MP200_NTSC_OFFSET)
#define MP200_PB0_BASE		(MP200_BANK4_BASE+MP200_PB0_OFFSET)
#define MP200_SWT_BASE		(MP200_BANK4_BASE+MP200_SWT_OFFSET)

#define MP200_SP1_BASE		(MP200_BANK4_BASE+MP200_SP1_OFFSET)
#define MP200_SP2_BASE		(MP200_BANK4_BASE+MP200_SP2_OFFSET)
#define MP200_DTV_BASE		(MP200_BANK4_BASE+MP200_DTV_OFFSET)
#define MP200_CCP_BASE		(MP200_BANK4_BASE+MP200_CCP_OFFSET)
#define MP200_RMT_BASE		(MP200_BANK4_BASE+MP200_RMT_OFFSET)
#define MP200_SP0_BASE		(MP200_BANK4_BASE+MP200_SP0_OFFSET)

#define MP200_TG0_BASE		(MP200_BANK4_BASE+MP200_TG0_OFFSET)
#define MP200_TG1_BASE		(MP200_BANK4_BASE+MP200_TG1_OFFSET)
#define MP200_TG2_BASE		(MP200_BANK4_BASE+MP200_TG2_OFFSET)
#define MP200_TG3_BASE		(MP200_BANK4_BASE+MP200_TG3_OFFSET)
#define MP200_TG4_BASE		(MP200_BANK4_BASE+MP200_TG4_OFFSET)
#define MP200_TG5_BASE		(MP200_BANK4_BASE+MP200_TG5_OFFSET)

#define MP200_MMM_S0_BASE	(MP200_BANK4_BASE+MP200_MMM_S0_OFFSET)
#define MP200_DMAC_S0_BASE	(MP200_BANK4_BASE+MP200_DMAC_S0_OFFSET)
#define MP200_FIFO_S1_BASE	(MP200_BANK4_BASE+MP200_FIFO_S1_OFFSET)

#define MP200_UART0_BASE	(MP200_BANK5_BASE+MP200_UART0_OFFSET)
#define MP200_UART1_BASE	(MP200_BANK5_BASE+MP200_UART1_OFFSET)
#define MP200_UART2_BASE	(MP200_BANK5_BASE+MP200_UART2_OFFSET)
#define MP200_I2C_BASE		(MP200_BANK5_BASE+MP200_I2C_OFFSET)
#define MP200_ASYNC1_BASE	(MP200_BANK5_BASE+MP200_ASYNC1_OFFSET)
#define MP200_SDIP_S0_BASE	(MP200_BANK5_BASE+MP200_SDIP_S0_OFFSET)
#define MP200_UART3_S1_BASE	(MP200_BANK5_BASE+MP200_UART3_S1_OFFSET)

#define MP200_USB_BASE		(MP200_BANK6_BASE+MP200_USB_OFFSET)

#define MP200_TIMER0_BASE	(MP200_BANK12_BASE+MP200_TIMER0_OFFSET)
#define MP200_WDT0_BASE		(MP200_BANK12_BASE+MP200_WDT0_OFFSET)
#define MP200_INTC_BASE		(MP200_BANK12_BASE+MP200_INTC_OFFSET)
#define MP200_LCDC_BASE		(MP200_BANK12_BASE+MP200_LCDC_OFFSET)
#define MP200_GPIO_BASE		(MP200_BANK12_BASE+MP200_GPIO_OFFSET)
#define MP200_SIO0_BASE		(MP200_BANK12_BASE+MP200_SIO0_OFFSET)
#define MP200_SIO1_BASE		(MP200_BANK12_BASE+MP200_SIO1_OFFSET)
#define MP200_PB1_BASE		(MP200_BANK12_BASE+MP200_PB1_OFFSET)
#define MP200_PMU_BASE		(MP200_BANK12_BASE+MP200_PMU_OFFSET)
#define MP200_SMU_S0_BASE	(MP200_BANK12_BASE+MP200_SMU_S0_OFFSET)
#define MP200_uWIRE_BASE	(MP200_BANK12_BASE+MP200_uWIRE_OFFSET)
#define MP200_SMU_S1_BASE	(MP200_BANK12_BASE+MP200_SMU_S1_OFFSET)
#define MP200_INTC_S1_BASE	(MP200_BANK12_BASE+MP200_INTC_S1_OFFSET)

/*
 *  MP200 Interrupt Controller
 */

/* INTC internal offset for PE0/1/2, DSP. */
#define MP200_INTC_IT0_OFFSET		0x00000000
#define MP200_INTC_IT1_OFFSET		0x00004000
#define MP200_INTC_IT2_OFFSET		0x00008000
#define MP200_INTC_ID_OFFSET		0x0000c000
#define MP200_INTC_S1_IM_OFFSET		0x0000e000

#define MP200_INTC_IT0_BASE		(MP200_INTC_BASE+MP200_INTC_IT0_OFFSET)
#define MP200_INTC_IT1_BASE		(MP200_INTC_BASE+MP200_INTC_IT1_OFFSET)
#define MP200_INTC_IT2_BASE		(MP200_INTC_BASE+MP200_INTC_IT2_OFFSET)
#define MP200_INTC_ID_BASE		(MP200_INTC_BASE+MP200_INTC_ID_OFFSET)
#define MP200_INTC_S1_IM_BASE		(MP200_INTC_S1_BASE+MP200_INTC_S1_IM_OFFSET)

/*
 * operational register offset
 */
/* interrupt enable */
#define	MP200_INTC_ITy_IEN0_OFFSET	0x00000000
#define	MP200_INTC_ITy_IEN1_OFFSET	0x00000004
/* interrupt enable monitor */
#define	MP200_INTC_ITy_IMN0_OFFSET	0x00000000
#define	MP200_INTC_ITy_IMN1_OFFSET	0x00000004
/* interrupt disable */
#define	MP200_INTC_ITy_IDS0_OFFSET	0x00000008
#define	MP200_INTC_ITy_IDS1_OFFSET	0x0000000c
/* interrupt raw status */
#define	MP200_INTC_ITy_RAW0_OFFSET	0x00000010
#define	MP200_INTC_ITy_RAW1_OFFSET	0x00000014
/* interrupt maskable status */
#define	MP200_INTC_ITy_MST0_OFFSET	0x00000018
#define	MP200_INTC_ITy_MST1_OFFSET	0x0000001c
/* interrupt cause clear */
#define	MP200_INTC_ITy_IIR_OFFSET	0x00000024

/* inter processor communication - set */
#define	MP200_INTC_ITy_IPI0_SET_OFFSET	0x00000030
#define	MP200_INTC_ITy_IPI1_SET_OFFSET	0x00000034
#define	MP200_INTC_ITy_IPI2_SET_OFFSET	0x00000038
#define	MP200_INTC_ITy_IPID_SET_OFFSET	0x0000003c
#define	MP200_INTC_ITy_IPIM_SET_OFFSET	0x00000040
/* inter processor communication - monitor */
#define	MP200_INTC_ITy_IPI0_MON_OFFSET	0x00000030
#define	MP200_INTC_ITy_IPI1_MON_OFFSET	0x00000034
#define	MP200_INTC_ITy_IPI2_MON_OFFSET	0x00000038
#define	MP200_INTC_ITy_IPID_MON_OFFSET	0x0000003c
#define	MP200_INTC_ITy_IPIM_MON_OFFSET	0x00000040
/* inter processor communication - clear */
#define	MP200_INTC_IT0_IPIz_CLR_OFFSET	0x00000050
#define	MP200_INTC_IT1_IPIz_CLR_OFFSET	0x00000054
#define	MP200_INTC_IT2_IPIz_CLR_OFFSET	0x00000058
#define	MP200_INTC_ITD_IPIz_CLR_OFFSET	0x0000005c
#define	MP200_INTC_ITM_IPIz_CLR_OFFSET	0x00000060

/* FIQ interrupt enable */
#define	MP200_INTC_ITy_FIE_OFFSET	0x00000080
/* FIQ interrupt monitor */
#define	MP200_INTC_ITy_FIM_OFFSET	0x00000080
/* FIQ interrupt disable */
#define	MP200_INTC_ITy_FID_OFFSET	0x00000084
/* interrupt vector base */
#define	MP200_INTC_ID_VBS_OFFSET	0x0000c090
/* interrupt output clear */
#define	MP200_INTC_ID_CLR_OFFSET	0x0000c094

/* eg, unsigned long va = IO_ADDRESS (MP200_INTC_BASE) + MP200_INTC_IT0_xxx;*/
/*
 * register map for PE0
 */
#define MP200_INTC_IT0_IEN0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_IT0_IEN1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_IT0_IMN0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_IT0_IMN1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_IT0_IDS0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_IT0_IDS1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_IT0_RAW0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_IT0_RAW1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_IT0_MST0	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_IT0_MST1	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_IT0_IIR	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_IT0_IPI1_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPI1_SET_OFFSET)
#define MP200_INTC_IT0_IPI2_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPI2_SET_OFFSET)
#define MP200_INTC_IT0_IPID_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPID_SET_OFFSET)
#define MP200_INTC_IT0_IPIM_SET	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPIM_SET_OFFSET)
#define MP200_INTC_IT0_IPI1_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPI1_MON_OFFSET)
#define MP200_INTC_IT0_IPI2_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPI2_MON_OFFSET)
#define MP200_INTC_IT0_IPID_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPID_MON_OFFSET)
#define MP200_INTC_IT0_IPIM_MON	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_IPIM_MON_OFFSET)
#define MP200_INTC_IT0_IPI1_CLR	(MP200_INTC_IT1_OFFSET+MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_IPI2_CLR	(MP200_INTC_IT2_OFFSET+MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_IPID_CLR	(MP200_INTC_ID_OFFSET+MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_IPIM_CLR	(MP200_INTC_S1_IM_OFFSET+QMUEENS_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_FIE	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_FIE_OFFSET)
#define MP200_INTC_IT0_FIM	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_FIM_OFFSET)
#define MP200_INTC_IT0_FID	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITy_FID_OFFSET)

/*
 * register map for PE1
 */
#define MP200_INTC_IT1_IEN0	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_IT1_IEN1	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_IT1_IMN0	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_IT1_IMN1	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_IT1_IDS0	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_IT1_IDS1	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_IT1_RAW0	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_IT1_RAW1	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_IT1_MST0	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_IT1_MST1	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_IT1_IIR	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_IT1_IPI0_SET	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_IT1_IPI2_SET	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPI2_SET_OFFSET)
#define MP200_INTC_IT1_IPID_SET	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPID_SET_OFFSET)
#define MP200_INTC_IT1_IPIM_SET	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPIM_SET_OFFSET)
#define MP200_INTC_IT1_IPI0_MON	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_IT1_IPI2_MON	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPI2_MON_OFFSET)
#define MP200_INTC_IT1_IPID_MON	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPID_MON_OFFSET)
#define MP200_INTC_IT1_IPIM_MON	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_IPIM_MON_OFFSET)
#define MP200_INTC_IT1_IPI0_CLR	(MP200_INTC_IT0_OFFSET+MP200_INTC_IT1_IPIz_CLR_OFFSET)
#define MP200_INTC_IT1_IPI2_CLR	(MP200_INTC_IT2_OFFSET+MP200_INTC_IT1_IPIz_CLR_OFFSET)
#define MP200_INTC_IT1_IPID_CLR	(MP200_INTC_ID_OFFSET+MP200_INTC_IT1_IPIz_CLR_OFFSET)
#define MP200_INTC_IT1_IPIM_CLR	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_IT1_IPIz_CLR_OFFSET)
#define MP200_INTC_IT1_FIE	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_FIE_OFFSET)
#define MP200_INTC_IT1_FIM	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_FIM_OFFSET)
#define MP200_INTC_IT1_FID	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITy_FID_OFFSET)

/*
 * register map for PE2
 */
#define MP200_INTC_IT2_IEN0	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_IT2_IEN1	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_IT2_IMN0	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_IT2_IMN1	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_IT2_IDS0	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_IT2_IDS1	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_IT2_RAW0	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_IT2_RAW1	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_IT2_MST0	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_IT2_MST1	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_IT2_IIR	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_IT2_IPI0_SET	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_IT2_IPI1_SET	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPI1_SET_OFFSET)
#define MP200_INTC_IT2_IPID_SET	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPID_SET_OFFSET)
#define MP200_INTC_IT2_IPIM_SET	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPIM_SET_OFFSET)
#define MP200_INTC_IT2_IPI0_MON	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_IT2_IPI1_MON	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPI1_MON_OFFSET)
#define MP200_INTC_IT2_IPID_MON	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPID_MON_OFFSET)
#define MP200_INTC_IT2_IPIM_MON	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_IPIM_MON_OFFSET)
#define MP200_INTC_IT2_IPI0_CLR	(MP200_INTC_IT0_OFFSET+MP200_INTC_IT2_IPIz_CLR_OFFSET)
#define MP200_INTC_IT2_IPI1_CLR	(MP200_INTC_IT1_OFFSET+MP200_INTC_IT2_IPIz_CLR_OFFSET)
#define MP200_INTC_IT2_IPID_CLR	(MP200_INTC_ID_OFFSET+MP200_INTC_IT2_IPIz_CLR_OFFSET)
#define MP200_INTC_IT2_IPIM_CLR	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_IT2_IPIz_CLR_OFFSET)
#define MP200_INTC_IT2_FIE	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_FIE_OFFSET)
#define MP200_INTC_IT2_FIM	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_FIM_OFFSET)
#define MP200_INTC_IT2_FID	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITy_FID_OFFSET)

/*
 * register map for DSP
 */
#define MP200_INTC_ID_IEN0	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_ID_IEN1	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_ID_IMN0	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_ID_IMN1	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_ID_IDS0	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_ID_IDS1	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_ID_RAW0	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_ID_RAW1	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_ID_MST0	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_ID_MST1	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_ID_IIR	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_ID_IPI0_SET	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_ID_IPI1_SET	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IPI1_SET_OFFSET)
#define MP200_INTC_ID_IPI2_SET	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IPI2_SET_OFFSET)
#define MP200_INTC_ID_IPI0_MON	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_ID_IPI1_MON	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IPI1_MON_OFFSET)
#define MP200_INTC_ID_IPI2_MON	(MP200_INTC_ID_OFFSET+MP200_INTC_ITy_IPI2_MON_OFFSET)
#define MP200_INTC_ID_IPI0_CLR	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITD_IPIz_CLR_OFFSET)
#define MP200_INTC_ID_IPI1_CLR	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITD_IPIz_CLR_OFFSET)
#define MP200_INTC_ID_IPI2_CLR	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITD_IPIz_CLR_OFFSET)
#define MP200_INTC_ID_VBS	(MP200_INTC_ID_OFFSET+MP200_INTC_ID_VBS_OFFSET)
#define MP200_INTC_ID_CLR	(MP200_INTC_ID_OFFSET+MP200_INTC_ID_CLR_OFFSET)

/*
 * register map for S1_IM
 */
#define MP200_INTC_S1_IM_IEN0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_S1_IM_IEN1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_S1_IM_IMN0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_S1_IM_IMN1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_S1_IM_IDS0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_S1_IM_IDS1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_S1_IM_RAW0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_S1_IM_RAW1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_S1_IM_MST0		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_S1_IM_MST1		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_S1_IM_IIR		(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_S1_IM_IPI0_SET	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_S1_IM_IPI1_SET	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI1_SET_OFFSET)
#define MP200_INTC_S1_IM_IPI2_SET	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI2_SET_OFFSET)
#define MP200_INTC_S1_IM_IPI0_MON	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_S1_IM_IPI1_MON	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI1_MON_OFFSET)
#define MP200_INTC_S1_IM_IPI2_MON	(MP200_INTC_S1_IM_OFFSET+MP200_INTC_ITy_IPI2_MON_OFFSET)
#define MP200_INTC_S1_IM_IPI0_CLR	(MP200_INTC_IT0_OFFSET+MP200_INTC_ITM_IPIz_CLR_OFFSET)
#define MP200_INTC_S1_IM_IPI1_CLR	(MP200_INTC_IT1_OFFSET+MP200_INTC_ITM_IPIz_CLR_OFFSET)
#define MP200_INTC_S1_IM_IPI2_CLR	(MP200_INTC_IT2_OFFSET+MP200_INTC_ITM_IPIz_CLR_OFFSET)
#endif				/* CONFIG_MP201 */

/* 
 *  These are useconds NOT ticks.  
 * 
 */
#define mSEC_1			1000
#define mSEC_5			(mSEC_1 * 5)
#define mSEC_10			(mSEC_1 * 10)
#define mSEC_25			(mSEC_1 * 25)
#define SEC_1			(mSEC_1 * 1000)

/*
 * serial base baud
 */
#define MP200_BASE_BAUD		(184320000 / 16)

/*
 * Include platform-specific definition
 */
#include <asm/arch/mp200_board.h>

/*
 * MAP DESC
 */
#define MP200_MAP_DESC(base, size)	\
	{ IO_ADDRESS(base), base, size, MT_DEVICE }

#endif				/* __ASM_ARM_ARCH_MP200_HARDWARE_H */
