/*
 * linux/arch/arm/mach-argonplus/gpio_priv.h
 *
 * Copyright 2004 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef __GPIO_PRIV_H
#define __GPIO_PRIV_H

#include <asm/sizes.h>
#include <asm/arch/platform.h>
#include <linux/interrupt.h>

/*!
 * @file gpio_priv.h
 * 
 * @brief This file contains the GPIO and IOMUX defines that are only intended
 * to be used internally by the GPIO module. 
 * 
 * @ingroup GPIO
 */

/*! 
 * Maximum number of MUX pins 
 */
#define MUX_PIN_NUM_MAX 0x154

/*!
 * 8 bits for each MUX control field
 */                              
#define MUX_CTL_BIT_LEN         8

/*!
 * 9 bits for each PAD control field
 */
#define MUX_PAD_BIT_LEN         9 

/*!
 * IOMUX register (base) addresses 
 */
enum iomux_reg_addr {
        IOMUXINT_OBS1   = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x000, /*!< Observe interrupts 1 */
        IOMUXINT_OBS2   = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004, /*!< Observe interrupts 2 */
        IOMUXGPR        = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x008, /*!< General purpose */
        IOMUXSW_MUX_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x034, /*!< MUX control actually starts here not 0xC*/
        IOMUXSW_PAD_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x1E4 /*!< Pad control */
};

/* GPIO related defines */

/*!
 * Number of GPIO port as defined in the IC Spec
 */
#define GPIO_PORT_NUM           2

/*!
 * Number of GPIO pins per port
 */
#define GPIO_NUM_PIN            32

/*!
 * Number of GPIO priorities. Two priorities are supported: high and low. If both
 * high and low priority GPIO interrupts are pending, the high priority one will be
 * serviced first.
 */
#define GPIO_INT_PRIO_NUM       2

/*!
 * This type definition is used to define a node in the GPIO interrupt queue for 
 * registered interrupts for GPIO pins. Each node contains the GPIO signal number 
 * associated with the ISR and the actual ISR function pointer.
 */
typedef struct gpio_sig_node {
        signed int sig_num;             /*!< the gpio signal number associated with ISR */
        irqreturn_t (*handler)(int, void *, struct pt_regs *); /*!< the ISR */
        const char *name;               /*!< device associated with the interrupt */
        void *dev_id;                   /*!< some unique information for the ISR */
        __u32 flags;                    /*!< not used */
}t_gpio_sig_node;

/*!
 * This type definition is used to define an interrupt queue for each priority. 
 * It contains data elements for the total number of registered ISRs and the 32 
 * GPIO signal nodes.
 */
typedef struct gpio_int_queue{
        __u32 total_num;                        /*!< total number of registered ISRs */
        t_gpio_sig_node node[GPIO_NUM_PIN];     /*!< GPIO node associated with a queue */
}t_gpio_int_queue;

enum gpio_reg {
        GPIO_DR         = 0x00,
        GPIO_GDIR       = 0x04,
        GPIO_PSR        = 0x08,
        GPIO_ICR1       = 0x0C,
        GPIO_ICR2       = 0x10,
        GPIO_IMR        = 0x14,
        GPIO_ISR        = 0x18,
};

enum edio_reg {
        EDIO_EPPAR      = 0x00,
        EDIO_EPDDR      = 0x02,
        EDIO_EPDR       = 0x04,
        EDIO_EPFR       = 0x06,
};

#define EDIO_MAX_SIG_NO         7       /* only 0-7 are valid */

#endif /* __GPIO_PRIV_H */
