/*
 *  File Name       : linux/arch/arm/mach-mp200/uwire.h
 *  Function        : uwire
 *  Release Version : Ver 1.00
 *  Release Date    : 2005/05/16
 *
 *  Copyright (C) NEC Electronics Corporation 2005
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#ifndef __ARCH_ARM_MACH_MP200_UWIRE_H
#define __ARCH_ARM_MACH_MP200_UWIRE_H

#include <linux/delay.h>

#define UWIRE_MAX_WAIT		((loops_per_jiffy / 200) + 1)	/* wait for ready */
#define UWIRE_MAX_BIT_LEN	32
#define UWIRE_BIT_RX_SHIFT	24
#define UWIRE_BIT_DTX_SHIFT	8

/*
 * devide value of PLL,OSC12M those supply clock
 * recommended value is quarter clock(current 12M) of PWC(FPGA)
 * * if clock is big, there is potential messing clock up 
 */
#define DIV_12M			4	/* 12/4 == 3 */

/*
 * address
 */
#define MWI_ADDRESS		MP200_uWIRE_BASE

/* MWI_CONT */
#define CS1_EN			(1U<<5)
#define CS0_EN			(1U<<4)
#define CS1			(1U<<3)	/* active value of CS1 is 1 */
#define CS0			(1U<<2)	/* active value of CS0 is 1 */

/*
 * MWI
 */

#define MWI_CONT		(IO_ADDRESS (MWI_ADDRESS) + 0x00)
#define MWI_CS0			(IO_ADDRESS (MWI_ADDRESS) + 0x04)
#define MWI_CS1			(IO_ADDRESS (MWI_ADDRESS) + 0x08)
#define MWI_START		(IO_ADDRESS (MWI_ADDRESS) + 0x0C)
#define MWI_INTSTATUS		(IO_ADDRESS (MWI_ADDRESS) + 0x20)
#define MWI_INTRAW		(IO_ADDRESS (MWI_ADDRESS) + 0x24)
#define MWI_INTFFCLR		(IO_ADDRESS (MWI_ADDRESS) + 0x28)
#define MWI_INTENSET		(IO_ADDRESS (MWI_ADDRESS) + 0x2C)
#define MWI_INTENCLR		(IO_ADDRESS (MWI_ADDRESS) + 0x30)
#define MWI_TXQA		(IO_ADDRESS (MWI_ADDRESS) + 0x40)
#define MWI_TXQ			(IO_ADDRESS (MWI_ADDRESS) + 0x50)
#define MWI_RXQ			(IO_ADDRESS (MWI_ADDRESS) + 0x60)

/* MWI_CS */
#define MWI_EDGE		(0x01)	/* RX_EDGE(up) | TX_EDGE(down) */

/* read : BITRX_EN | BITATX_EN | BIT_ATX(8) | RX_EN | TX_EN */
#define MWI_SEQUENTIAL_MODE	(0x20270003)
/* write : BITATX_EN | BIT_ATX(8) | BITDTX_EN | TX_EN */
#define MWI_PACKAGE_MODE	(0x00272001)
/* read-write : BITRX_EN | BITDTX_EN | RX_EN | TX_EN */
#define MWI_SIMULTANEOUS_MODE	(0x20002003)

/* Used for MWI_INTFFCLR */
#define MWI_FFCLR		1	/* Interrupts Clear */

/* Used for MWI_START */
#define MWI_START_FLAG		1	/* Transmit Start */

/* Ued for MWI_INTRAW */
#define MWI_RAW			1	/* Interrupts Data Outbreak */
#endif				/* ARCH_ARM_MACH_MP200_UWIRE_H */
