/*
 * Copyright 2004 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/*!
 * @file mxc_scc.h
 *
 * @brief MXC SCC header file.
 *
 * @ingroup MXC_Security
 */

#ifndef _MXC_SCC_H_
#define _MXC_SCC_H_

#include <asm/arch/platform.h>
#include <asm/arch/mxc_security_api.h>
#include <linux/config.h>

#ifdef CONFIG_SCC_TEST_DEBUG
#include <linux/module.h>
#endif /* SCC_TEST_DEBUG */
/*
 * Used to test the API when used along with Linux as OS
 */
#define         SCC_DEBUG_MODULE

#if             CONFIG_ARCH_SCMA11EVB || CONFIG_ARCH_SCMA11BB

/*
 * Defined differently in SCMA11's platform.h file. To make it
 * compatible for all the platforms this is #defined in this way.
 */
#define     SCC_BASE_ADDR       SCC_AP_BASE_ADDR

#endif /* CONFIG_ARCH_SCMA11EVB || CONFIG_ARCH_SCMA11BB */

#ifdef SCC_TEST_DEBUG
#define SCC_DEBUG(fmt, args...) printk(fmt,## args)
#else
#define SCC_DEBUG(fmt, args...)
#endif /* SCC_TEST_DEBUG */

#define     IIM_BASE_ADDR       0x5001C000
#define     IIM_HWV2_FUSE       0x080C

#define     SCC_FUSE            IO_ADDRESS(IIM_BASE_ADDR + IIM_HWV2_FUSE)
#define     SCC_DISABLED_MASK   0x0010

/*
 * Offset values of the Register map for the SCC Module
 */
#define     SCC_RED_START_ADDR    (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0000)))
#define     SCC_BLACK_START_ADDR  (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0004)))
#define     SCC_LENGTH            (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0008)))
#define     SCC_CONTROL           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x000C)))
#define     SCC_SCM_STATUS        (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0010)))
#define     SCC_ERROR_STATUS      (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0014)))
#define     SCC_INT_CTRL          (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0018)))
#define     SCC_CONFIG            (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x001C)))
#define     SCC_INIT_VECT0        (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0020)))
#define     SCC_INIT_VECT1        (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0024)))
#define     SCC_RED_MEM_ADDR      ((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0400))
#define     SCC_BLACK_MEM_ADDR    ((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x0800))
#define     SCC_SMN_STATUS        (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1000)))
#define     SCC_COMMAND           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1004)))
#define     SCC_SEQ_START         (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1008)))
#define     SCC_SEQ_END           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x100C)))
#define     SCC_SEQ_CHK           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1010)))
#define     SCC_BIT_CNT           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1014)))
#define     SCC_BIT_INCR_SIZE     (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1018)))
#define     SCC_BIT_DECR          (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                      + 0x101C)))
#define     SCC_CMP_SIZE          (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1020)))
#define     SCC_PLN_CHK           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1024)))
#define     SCC_CIP_CHK           (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1028)))
#define     SCC_TIM_IV            (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x102C)))
#define     SCC_TIM_CTRL          (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1030)))
#define     SCC_DBG_DET_STAT      (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1034)))
#define     SCC_TIM_RD            (*((volatile ulong *)IO_ADDRESS(SCC_BASE_ADDR\
                                     + 0x1038)))
/*!
 * @name Security SCM register's bit field data types.
 */

/*! @{ */

/*!
 * Zeroize Secure memory(Red & Black).
 */
#define         SCC_ZEROIZE_MEM                 0x04

/*!
 * Clears the Interrupt of the SCM Module.
 */
#define         SCC_SCM_INT_CLR                 0x02

/*!
 * Clears the Interrupt of the SMN Module.
 */
#define         SCC_SMN_INT_CLR                 0x08

/*!
 * Enables the Interrupt of the SMN Module.
 */
#define         SCC_SMN_INT_ENABLE              0x02

/*!
 * Disables the Interrupt of the SMN Module.
 */
#define         SCC_SMN_INT_DISABLE             (~(0x02))

/*!
 * Sets the alarm bit in the register.
 */
#define         SCC_SET_ALARM                   1

/*!
 * Mask for getting the state information.
 */
#define         SCC_STATE                       0x1F

/*! @} */

/*!
 * @name Security SCM Ciphering bit field data types.
 */

/*! @{ */

/*!
 * Sets the direction of data transfer to Encrypt the data in Secure memory.
 */
#define         SCC_ENCRYPT                     0

/*!
 * Sets the direction of data transfer to Encrypt the data in Secure memory.
 */
#define         SCC_DECRYPT                     1

/*!
 * Start the Ciphering process.
 */
#define         SCC_START_CIPHER                0x04

/*!
 * Stops the Ciphering process.
 */
#define         SCC_STOP_CIPHER                 (~(0x04))

/*!
 * Clears the status bit of zeroize fail in the SMN status register.
 */
#define         SCC_SMN_ZEROIZE_FAIL_CLR       0x40

/*!
 * Resets the Bit Bank counter.
 */
#define         SCC_BIT_BANK_CLR                0x04

/*! @} */

/*!
 * @name Security General purpose bit field data types.
 */

/*! @{ */

/*!
 * Process is successful in the job assigned.
 */
#define         SCC_SUCCESS                     0

/*!
 * Process is unsuccessful in the job assigned.
 */
#define         SCC_FAILURE                     -1

/*!
 * Set the lvalue with 1.
 */
#define         SCC_SET                         0x01

/*!
 * Reset the lvalue with 0.
 */
#define         SCC_RESET                       0x00

/*!
 * Max Ciphering size in bytes used for checking the parameter passed during
 * configuration.
 */
#define         SCC_MAX_CIPHER_LENGTH           0x7F

/*!
 * Max Bit Bank register size used for checking the parameter passed during
 * configuration.
 */
#define         SCC_BIT_BNK_MAX_SIZE            0x7FF

/*!
 * Max Bit Bank compare size used for checking the parameter passed during
 * configuration.
 */
#define         SCC_BIT_BNK_MAX_CMP_SIZE        0x3F

/*! @} */

#endif /* _MXC_SCC_H_ */
