/*
 * File Name       : /drivers/video/ROT.h
 * Function        : ROT MMIO definitions
 * Release Version : Ver 1.00
 * Release Date    : 2005/05/25
 *
 * Copyright (C) NEC Electronics Corporation 2005
 *
 *
 * This program is free software;you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by Free Softwere
 * Foundation; either version 2 of License, or (at your option) any later
 * version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warrnty of MERCHANTABILITY or FITNESS
 * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; If not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 */
/* ROT.h : ROT MMIO definitions for uPD77601	2004/2/28 */

#ifndef _ROT_H_
#define _ROT_H_


/*****************************************************************************
 * ROT MMIO definitions
 *****************************************************************************/

/* from platform.h for uPD77601 */
#define BANK4_BASE			0x40000000
#define ROTATOR_OFFSET	0x00080000
#define ROTATOR_BASE	(BANK4_BASE+ROTATOR_OFFSET)
#define ROTATOR_SIZE	SZ_64K

/* from quhw_rot_reg.h */
//                                                           R/W   Bit  Reset
// Mode for ROTATOR                                          R/W   4:0  0x00
#define RO_MODE                 (0x00)

// Frame Select                                              R/W   3:0  0x5
#define RO_FRAME                (0x04)

// Rotate Request                                            R/W   0:0  0x0
#define RO_REQ                  (0x08)

// Status for ROTATOR                                         R    0:0  0x0
#define RO_STATUS               (0x0C)

// Original Address Size                                     R/W  10:2  0x000
#define RO_SRCSIZE              (0x20)

// Rotate Address Size                                       R/W  10:2  0x000
#define RO_DSTSIZE              (0x24)

// Original Y Address for A Frame                            R/W  31:2  0x0000_0000
#define RO_SRCYADR_A            (0x30)

// Original Y Address for B Frame                            R/W  31:2  0x0000_0000
#define RO_SRCYADR_B            (0x34)

// Original Y Address for C Frame                            R/W  31:2  0x0000_0000
#define RO_SRCYADR_C            (0x38)

// Rotate Y Address for A Frame                              R/W  31:2  0x0000_0000
#define RO_DSTYADR_A            (0x40)

// Rotate Y Address for B Frame                              R/W  31:2  0x0000_0000
#define RO_DSTYADR_B            (0x44)

// Rotate Y Address for C Frame                              R/W  31:2  0x0000_0000
#define RO_DSTYADR_C            (0x48)

// Original UV Address for A Frame                           R/W  31:2  0x0000_0000
#define RO_SRCUVADR_A           (0x60)

// Original UV Address for B Frame                           R/W  31:2  0x0000_0000
#define RO_SRCUVADR_B           (0x64)

// Original UV Address for C Frame                           R/W  31:2  0x0000_0000
#define RO_SRCUVADR_C           (0x68)

// Rotate UV Address for A Frame                             R/W  31:2  0x0000_0000
#define RO_DSTUVADR_A           (0x70)

// Rotate UV Address for B Frame                             R/W  31:2  0x0000_0000
#define RO_DSTUVADR_B           (0x74)

// Rotate UV Address for C Frame                             R/W  31:2  0x0000_0000
#define RO_DSTUVADR_C           (0x78)

// Horizontal Size                                           R/W  10:2  0x008
#define RO_SRCHSIZE             (0x90)

// Vertical Size                                             R/W  10:2  0x008
#define RO_SRCVSIZE             (0xA0)

// Interrupt Status                                           R    2:0  0x0
#define RO_INTSTATUS            (0xB0)

// Interrupt Raw Status                                       R    2:0  0x0
#define RO_INTRAWSTATUS         (0xB4)

// Interrupt Enable Set                                      R/W   2:0  0x0
#define RO_INTENSET             (0xB8)

// Interrupt Enable Clear                                     W    2:0  0x0
#define RO_INTENCLR             (0xBC)

// Interrupt Status Clear                                     W    2:0  0x0
#define RO_INTFFCLR             (0xC0)

// DMA Error Respons Address                                 R/W  31:0  0x0
#define RO_ERRORADR             (0xC4)


//------------------------------
// RO_INTSTATUS
//------------------------------
#define RO_DMASTOP_BIT		0x00000004
#define RO_DMASTOP_SFT		0x02

#define RO_DMAERR_BIT		0x00000002
#define RO_DMAERR_SFT		0x01

#define RO_ROTEND_BIT		0x00000001
#define RO_ROTEND_SFT		0x00

//------------------------------
// RO_INTRAWSTATUS
//------------------------------
#define RO_DMASTOPRAW_BIT	0x00000004
#define RO_DMASTOPRAW_SFT	0x02

#define RO_DMAERRRAW_BIT	0x00000002
#define RO_DMAERRRAW_SFT	0x01

#define RO_ROTENDRAW_BIT	0x00000001
#define RO_ROTENDRAW_SFT	0x00

//------------------------------
// RO_INTENSET
//------------------------------
#define RO_DMASTOPEN_BIT	0x00000004
#define RO_DMASTOPEN_SFT	0x02

#define RO_DMAERREN_BIT		0x00000002
#define RO_DMAERREN_SFT		0x01

#define RO_ROTENDEN_BIT		0x00000001
#define RO_ROTENDEN_SFT		0x00

//------------------------------
// RO_INTENCLR
//------------------------------
#define RO_DMASTOPMASK_BIT	0x00000004
#define RO_DMASTOPMASK_SFT	0x02

#define RO_DMAERRMASK_BIT	0x00000002
#define RO_DMAERRMASK_SFT	0x01

#define RO_ROTENDMASK_BIT	0x00000001
#define RO_ROTENDMASK_SFT	0x00

//------------------------------
// RO_INTFFCLR
//------------------------------
#define RO_DMASTOPCLR_BIT	0x00000004
#define RO_DMASTOPCLR_SFT	0x02

#define RO_DMAERRCLR_BIT	0x00000002
#define RO_DMAERRCLR_SFT	0x01

#define RO_ROTENDCLR_BIT	0x00000001
#define RO_ROTENDCLR_SFT	0x00


#endif /* _ROT_H_ */
