/*
 *  Copyright 2004 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef __MXC_IRQS_H__
#define __MXC_IRQS_H__

/*!
 * @defgroup Interrupt Interrupt Controller (AVIC)
 * @ingroup MSL
 */

/*!
 * @file irqs.h
 * @brief This file defines the number of normal interrupts and fast interrupts
 * 
 * @ingroup Interrupt
 */

#include <asm/arch/platform.h>

/*!
 * REVISIT: document me
 */
#define ARCH_TIMER_IRQ	INT_GPT

/*!
 * Number of normal interrupts
 */
#define NR_IRQS         (MAXIRQNUM + 1)

/*!
 * Number of fast interrupts
 */
#define NR_FIQS		(MAXFIQNUM + 1)

/*
 *****************************************
 * AVIC                                  *
 *****************************************
 */
#define    _reg_AVIC_INTCNTL        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x00)))     /*  32bit AVIC int control reg */
#define    _reg_AVIC_NIMASK         ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x04)))     /*  32bit AVIC int mask reg */
#define    _reg_AVIC_INTENNUM       ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x08)))     /*  32bit AVIC int enable number reg */
#define    _reg_AVIC_INTDISNUM      ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x0C)))     /*  32bit AVIC int disable number reg */
#define    _reg_AVIC_INTENABLEH     ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x10)))     /*  32bit AVIC int enable reg high */
#define    _reg_AVIC_INTENABLEL     ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x14)))     /*  32bit AVIC int enable reg low */
#define    _reg_AVIC_INTTYPEH       ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x18)))     /*  32bit AVIC int type reg high */
#define    _reg_AVIC_INTTYPEL       ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x1C)))     /*  32bit AVIC int type reg low */
#define    _reg_AVIC_NIPRIORITY7    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x20)))     /*  32bit AVIC norm int priority lvl7 */
#define    _reg_AVIC_NIPRIORITY6    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x24)))     /*  32bit AVIC norm int priority lvl6 */
#define    _reg_AVIC_NIPRIORITY5    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x28)))     /*  32bit AVIC norm int priority lvl5 */
#define    _reg_AVIC_NIPRIORITY4    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x2C)))     /*  32bit AVIC norm int priority lvl4 */
#define    _reg_AVIC_NIPRIORITY3    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x30)))     /*  32bit AVIC norm int priority lvl3 */
#define    _reg_AVIC_NIPRIORITY2    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x34)))     /*  32bit AVIC norm int priority lvl2 */
#define    _reg_AVIC_NIPRIORITY1    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x38)))     /*  32bit AVIC norm int priority lvl1 */
#define    _reg_AVIC_NIPRIORITY0    ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x3C)))     /*  32bit AVIC norm int priority lvl0 */
#define    _reg_AVIC_NIVECSR        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x40)))     /*  32bit AVIC norm int vector/status */
#define    _reg_AVIC_FIVECSR        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x44)))     /*  32bit AVIC fast int vector/status */
#define    _reg_AVIC_INTSRCH        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x48)))     /*  32bit AVIC int source reg high */
#define    _reg_AVIC_INTSRCL        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x4C)))     /*  32bit AVIC int source reg low */
#define    _reg_AVIC_INTFRCH        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x50)))     /*  32bit AVIC int force reg high */
#define    _reg_AVIC_INTFRCL        ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x54)))     /*  32bit AVIC int force reg low */
#define    _reg_AVIC_NIPNDH         ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x58)))     /*  32bit AVIC norm int pending high */
#define    _reg_AVIC_NIPNDL         ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x5C)))     /*  32bit AVIC norm int pending low */
#define    _reg_AVIC_FIPNDH         ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x60)))     /*  32bit AVIC fast int pending high */
#define    _reg_AVIC_FIPNDL         ((volatile unsigned long *)(IO_ADDRESS(AVIC_BASE_ADDR + 0x64)))     /*  32bit AVIC fast int pending low */

#endif /* __MXC_IRQS_H__ */
