/* 2012-09-16: File changed by Sony Corporation */
/*
 * Copyright (C) 2010-2012 Renesas Electronics Corporation
 *
 * See file CREDITS for list of people who contributed to this project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA.
 */

#ifndef _REG_H
#define _REG_H

/**************************
 * SMU
 **************************/
#define	SMU_S0_BASE			(0xe0110000)

/* Reset controll */
#define SMU_CPU_RSTCTRL0		(SMU_S0_BASE + 0x0000)

#define SMU_DSP_RSTCTRL			(SMU_S0_BASE + 0x0008)
#define SMU_GIO_RSTCTRL			(SMU_S0_BASE + 0x000C)
#define SMU_INTA_RSTCTRL		(SMU_S0_BASE + 0x0010)
#define SMU_CHG_RSTCTRL			(SMU_S0_BASE + 0x0014)
#define SMU_CHG1_RSTCTRL		(SMU_S0_BASE + 0x0018)
#define SMU_BUS0_RSTCTRL		(SMU_S0_BASE + 0x001C)
#define SMU_BUS1_RSTCTRL		(SMU_S0_BASE + 0x0020)
#define SMU_PBL0_RSTCTRL		(SMU_S0_BASE + 0x0024)
#define SMU_PBL1_RSTCTRL		(SMU_S0_BASE + 0x0028)
#define SMU_AHB_RSTCTRL			(SMU_S0_BASE + 0x002C)
#define SMU_P2M_RSTCTRL			(SMU_S0_BASE + 0x0030)
#define SMU_M2P_RSTCTRL			(SMU_S0_BASE + 0x0034)
#define SMU_M2M_RSTCTRL			(SMU_S0_BASE + 0x0038)
#define SMU_PMU_RSTCTRL			(SMU_S0_BASE + 0x003C)
#define SMU_SRC_RSTCTRL			(SMU_S0_BASE + 0x0040)
#define SMU_ROM_RSTCTRL			(SMU_S0_BASE + 0x0044)
#define SMU_AB0_RSTCTRL			(SMU_S0_BASE + 0x0048)
#define SMU_MEMC_RSTCTRL		(SMU_S0_BASE + 0x004C)
#define SMU_LCD_RSTCTRL			(SMU_S0_BASE + 0x0050)
#define SMU_IMC_RSTCTRL			(SMU_S0_BASE + 0x0054)
#define SMU_IMCW_RSTCTRL		(SMU_S0_BASE + 0x0058)
#define SMU_SIZ_RSTCTRL			(SMU_S0_BASE + 0x005C)
#define SMU_ROT_RSTCTRL			(SMU_S0_BASE + 0x0060)

#define SMU_AVE_RSTCTRL			(SMU_S0_BASE + 0x0068)

#define SMU_DTV_RSTCTRL			(SMU_S0_BASE + 0x0070)
#define SMU_NTS_RSTCTRL			(SMU_S0_BASE + 0x0074)
#define SMU_CAM_RSTCTRL			(SMU_S0_BASE + 0x0078)

#define SMU_IRR_RSTCTRL			(SMU_S0_BASE + 0x0084)
#define SMU_PWM_RSTCTRL			(SMU_S0_BASE + 0x0088)
#define SMU_USIAS0_RSTCTRL		(SMU_S0_BASE + 0x008C)
#define SMU_USIAS1_RSTCTRL		(SMU_S0_BASE + 0x0090)
#define SMU_USIAU0_RSTCTRL		(SMU_S0_BASE + 0x0094)

#define SMU_USIBS2_RSTCTRL		(SMU_S0_BASE + 0x009C)
#define SMU_USIBS3_RSTCTRL		(SMU_S0_BASE + 0x00A0)

#define SMU_USIBU1_RSTCTRL		(SMU_S0_BASE + 0x00AC)
#define SMU_USIBU2_RSTCTRL		(SMU_S0_BASE + 0x00B0)
#define SMU_USIBU3_RSTCTRL		(SMU_S0_BASE + 0x00B4)

#define SMU_SDIO0_RSTCTRL		(SMU_S0_BASE + 0x00BC)
#define SMU_SDIO1_RSTCTRL		(SMU_S0_BASE + 0x00C0)

#define SMU_SDC_RSTCTRL			(SMU_S0_BASE + 0x00C8)
#define SMU_USIBU4_RSTCTRL		(SMU_S0_BASE + 0x00CC)

#define SMU_CFI_RSTCTRL			(SMU_S0_BASE + 0x00D0)
#define SMU_MSP_RSTCTRL			(SMU_S0_BASE + 0x00D4)

#define SMU_IIC0_RSTCTRL		(SMU_S0_BASE + 0x00DC)
#define SMU_IIC1_RSTCTRL		(SMU_S0_BASE + 0x00E0)
#define SMU_USB0_RSTCTRL		(SMU_S0_BASE + 0x00E4)
#define SMU_USB1_RSTCTRL		(SMU_S0_BASE + 0x00E8)
#define SMU_TI0_RSTCTRL			(SMU_S0_BASE + 0x00EC)
#define SMU_TI1_RSTCTRL			(SMU_S0_BASE + 0x00F0)
#define SMU_TI2_RSTCTRL			(SMU_S0_BASE + 0x00F4)
#define SMU_TI3_RSTCTRL			(SMU_S0_BASE + 0x00F8)
#define SMU_TW0_RSTCTRL			(SMU_S0_BASE + 0x00FC)
#define SMU_TW1_RSTCTRL			(SMU_S0_BASE + 0x0100)
#define SMU_TW2_RSTCTRL			(SMU_S0_BASE + 0x0104)
#define SMU_TW3_RSTCTRL			(SMU_S0_BASE + 0x0108)
#define SMU_TG0_RSTCTRL			(SMU_S0_BASE + 0x010C)
#define SMU_TG1_RSTCTRL			(SMU_S0_BASE + 0x0110)
#define SMU_TG2_RSTCTRL			(SMU_S0_BASE + 0x0114)
#define SMU_TG3_RSTCTRL			(SMU_S0_BASE + 0x0118)
#define SMU_TG4_RSTCTRL			(SMU_S0_BASE + 0x011C)
#define SMU_TG5_RSTCTRL			(SMU_S0_BASE + 0x0120)
#define SMU_STI_RSTCTRL			(SMU_S0_BASE + 0x0124)

#define SMU_AFS_RSTCTRL			(SMU_S0_BASE + 0x012C)
#define SMU_MMM_RSTCTRL			(SMU_S0_BASE + 0x0130)

#define SMU_TW4_RSTCTRL			(SMU_S0_BASE + 0x0140)

#define SMU_PDMA_RSTCTRL		(SMU_S0_BASE + 0x0148)
#define SMU_A2D_RSTCTRL			(SMU_S0_BASE + 0x014C)
#define SMU_USIBU5_RSTCTRL		(SMU_S0_BASE + 0x0150)

#define SMU_PLL1CTRL0			(SMU_S0_BASE + 0x0200)
#define SMU_PLL1CTRL1			(SMU_S0_BASE + 0x0204)
#define SMU_PLL2CTRL0			(SMU_S0_BASE + 0x0208)
#define SMU_PLL2CTRL1			(SMU_S0_BASE + 0x020C)
#define SMU_PLL3CTRL0			(SMU_S0_BASE + 0x0210)
#define SMU_PLL3CTRL1			(SMU_S0_BASE + 0x0214)

#define SMU_OSC0CTRL1			(SMU_S0_BASE + 0x0220)
#define SMU_OSC1CTRL1			(SMU_S0_BASE + 0x0224)
#define SMU_PLLLOCKTIME0		(SMU_S0_BASE + 0x0228)
#define SMU_PLLLOCKTIME1		(SMU_S0_BASE + 0x022C)
#define SMU_OSCLOCKTIME			(SMU_S0_BASE + 0x0230)
#define SMU_PLL_STATUS			(SMU_S0_BASE + 0x0234)
#define SMU_ROSCCTRL1			(SMU_S0_BASE + 0x0238)
#define SMU_PLLLOCKTIME_INVALID		(SMU_S0_BASE + 0x023C)
#define SMU_PLLGATE			(SMU_S0_BASE + 0x0240)
#define SMU_PLL_MODE			(SMU_S0_BASE + 0x0244)
#define SMU_OSC_CX			(SMU_S0_BASE + 0x0248)

#define SMU_AUTO_PLL_STANDBY		(SMU_S0_BASE + 0x02F0)
#define SMU_AUTO_MODE_EN		(SMU_S0_BASE + 0x02F4)

#define SMU_CLK_MODE_SEL		(SMU_S0_BASE + 0x0300)
#define SMU_MEMC_HAND_SHAKE_FAKE	(SMU_S0_BASE + 0x0304)

#define SMU_CKMODE_PLLSEL		(SMU_S0_BASE + 0x031C)

#define SMU_NORMALA_DIV			(SMU_S0_BASE + 0x0320)
#define SMU_NORMALB_DIV			(SMU_S0_BASE + 0x0324)
#define SMU_NORMALC_DIV			(SMU_S0_BASE + 0x0328)
#define SMU_NORMALD_DIV			(SMU_S0_BASE + 0x032C)
#define SMU_POWERON_DIV			(SMU_S0_BASE + 0x0330)
#define SMU_ECONOMY_DIV			(SMU_S0_BASE + 0x0334)
#define SMU_SLEEP_DIV			(SMU_S0_BASE + 0x0338)

#define SMU_MEMCCLK270_SEL		(SMU_S0_BASE + 0x0350)
#define SMU_MEMCCLK_MODE		(SMU_S0_BASE + 0x0354)
#define SMU_CPUCLK_SYNCSET		(SMU_S0_BASE + 0x0358)
#define SMU_CPUCLK_ASYNC_MODE		(SMU_S0_BASE + 0x035C)
#define SMU_FLA_CLK_DLY			(SMU_S0_BASE + 0x0360)
#define SMU_FLASHCLK_CTRL		(SMU_S0_BASE + 0x0364)
#define SMU_DSPCLK_ASYNC_MODE		(SMU_S0_BASE + 0x0368)

/* auto clock controll */
#define SMU_AHBCLKCTRL0			(SMU_S0_BASE + 0x0380)
#define SMU_AHBCLKCTRL1			(SMU_S0_BASE + 0x0384)
#define SMU_AHBCLKCTRL2			(SMU_S0_BASE + 0x0388)
#define SMU_AHBCLKCTRL3			(SMU_S0_BASE + 0x038C)
#define SMU_APBCLKCTRL0			(SMU_S0_BASE + 0x0390)
#define SMU_APBCLKCTRL1			(SMU_S0_BASE + 0x0394)
#define SMU_APBCLKCTRL2			(SMU_S0_BASE + 0x0398)
#define SMU_CLKCTRL			(SMU_S0_BASE + 0x039C)
#define SMU_AVECLKCTRL			(SMU_S0_BASE + 0x03A0)

#define SMU_ACNT0			(SMU_S0_BASE + 0x03C8)
#define SMU_ACNT1			(SMU_S0_BASE + 0x03CC)

/* auto clock controll */
#define SMU_CPUGCLKCTRL			(SMU_S0_BASE + 0x0400)
#define SMU_DSPGCLKCTRL			(SMU_S0_BASE + 0x0404)
#define SMU_GIOGCLKCTRL			(SMU_S0_BASE + 0x0408)
#define SMU_INTAGCLKCTRL		(SMU_S0_BASE + 0x040C)
#define SMU_CHGGCLKCTRL			(SMU_S0_BASE + 0x0410)
#define SMU_BUS0GCLKCTRL		(SMU_S0_BASE + 0x0414)
#define SMU_BUS1GCLKCTRL		(SMU_S0_BASE + 0x0418)
#define SMU_PBL0GCLKCTRL		(SMU_S0_BASE + 0x041C)
#define SMU_PBL1GCLKCTRL		(SMU_S0_BASE + 0x0420)
#define SMU_AHBGCLKCTRL			(SMU_S0_BASE + 0x0424)
#define SMU_P2MGCLKCTRL			(SMU_S0_BASE + 0x0428)
#define SMU_M2PGCLKCTRL			(SMU_S0_BASE + 0x042C)
#define SMU_M2MGCLKCTRL			(SMU_S0_BASE + 0x0430)
#define SMU_PMUGCLKCTRL			(SMU_S0_BASE + 0x0434)
#define SMU_SRCGCLKCTRL			(SMU_S0_BASE + 0x0438)
#define SMU_ROMGCLKCTRL			(SMU_S0_BASE + 0x043C)
#define SMU_ABGCLKCTRL			(SMU_S0_BASE + 0x0440)
#define SMU_FLAGCLKCTRL			(SMU_S0_BASE + 0x0444)
#define SMU_MEMCGCLKCTRL		(SMU_S0_BASE + 0x0448)
#define SMU_LCDGCLKCTRL			(SMU_S0_BASE + 0x044C)
#define SMU_IMCGCLKCTRL			(SMU_S0_BASE + 0x0450)
#define SMU_IMCWGCLKCTRL		(SMU_S0_BASE + 0x0454)
#define SMU_SIZGCLKCTRL			(SMU_S0_BASE + 0x0458)
#define SMU_ROTGCLKCTRL			(SMU_S0_BASE + 0x045C)

#define SMU_AVEGCLKCTRL			(SMU_S0_BASE + 0x0464)

#define SMU_DTVGCLKCTRL			(SMU_S0_BASE + 0x046C)
#define SMU_NTSGCLKCTRL			(SMU_S0_BASE + 0x0470)
#define SMU_CAMGCLKCTRL			(SMU_S0_BASE + 0x0474)

#define SMU_IRRGCLKCTRL			(SMU_S0_BASE + 0x0480)
#define SMU_PWMGCLKCTRL			(SMU_S0_BASE + 0x0484)

#define SMU_IIC0GCLKCTRL		(SMU_S0_BASE + 0x048C)
#define SMU_IIC1GCLKCTRL		(SMU_S0_BASE + 0x0490)
#define SMU_USBGCLKCTRL			(SMU_S0_BASE + 0x0494)
#define SMU_USIAS0GCLKCTRL		(SMU_S0_BASE + 0x0498)
#define SMU_USIAS1GCLKCTRL		(SMU_S0_BASE + 0x049C)
#define SMU_USIAU0GCLKCTRL		(SMU_S0_BASE + 0x04A0)

#define SMU_USIBS2GCLKCTRL		(SMU_S0_BASE + 0x04A8)
#define SMU_USIBS3GCLKCTRL		(SMU_S0_BASE + 0x04AC)

#define SMU_USIBU1GCLKCTRL		(SMU_S0_BASE + 0x04B8)
#define SMU_USIBU2GCLKCTRL		(SMU_S0_BASE + 0x04BC)
#define SMU_USIBU3GCLKCTRL		(SMU_S0_BASE + 0x04C0)

#define SMU_SDIO0GCLKCTRL		(SMU_S0_BASE + 0x04C8)
#define SMU_SDIO1GCLKCTRL		(SMU_S0_BASE + 0x04CC)

#define SMU_SDCGCLKCTRL			(SMU_S0_BASE + 0x04D4)
#define SMU_USIBU4GCLKCTRL		(SMU_S0_BASE + 0x04D8)
#define SMU_CFIGCLKCTRL			(SMU_S0_BASE + 0x04DC)

#define SMU_MSPGCLKCTRL			(SMU_S0_BASE + 0x04E8)
#define SMU_TI0GCLKCTRL			(SMU_S0_BASE + 0x04EC)
#define SMU_TI1GCLKCTRL			(SMU_S0_BASE + 0x04F0)
#define SMU_TI2GCLKCTRL			(SMU_S0_BASE + 0x04F4)
#define SMU_TI3GCLKCTRL			(SMU_S0_BASE + 0x04F8)
#define SMU_TG0GCLKCTRL			(SMU_S0_BASE + 0x04FC)
#define SMU_TG1GCLKCTRL			(SMU_S0_BASE + 0x0500)
#define SMU_TG2GCLKCTRL			(SMU_S0_BASE + 0x0504)
#define SMU_TG3GCLKCTRL			(SMU_S0_BASE + 0x0508)
#define SMU_TG4GCLKCTRL			(SMU_S0_BASE + 0x050C)
#define SMU_TG5GCLKCTRL			(SMU_S0_BASE + 0x0510)
#define SMU_TW0GCLKCTRL			(SMU_S0_BASE + 0x0514)
#define SMU_TW1GCLKCTRL			(SMU_S0_BASE + 0x0518)
#define SMU_TW2GCLKCTRL			(SMU_S0_BASE + 0x051C)
#define SMU_TW3GCLKCTRL			(SMU_S0_BASE + 0x0520)
#define SMU_TIMGCLKCTRL			(SMU_S0_BASE + 0x0524)
#define SMU_STIGCLKCTRL			(SMU_S0_BASE + 0x0528)

#define SMU_AFSGCLKCTRL			(SMU_S0_BASE + 0x0530)
#define SMU_MMMGCLKCTRL			(SMU_S0_BASE + 0x0534)

#define SMU_REFGCLKCTRL			(SMU_S0_BASE + 0x053C)
#define SMU_TW4GCLKCTRL			(SMU_S0_BASE + 0x0540)

#define SMU_PDMAGCLKCTRL		(SMU_S0_BASE + 0x0554)
#define SMU_INTDGCLKCTRL		(SMU_S0_BASE + 0x0558)
#define SMU_A2DGCLKCTRL			(SMU_S0_BASE + 0x055C)
#define SMU_USIBU5GCLKCTRL		(SMU_S0_BASE + 0x0560)

#define SMU_TWI0TIN_SEL			(SMU_S0_BASE + 0x0600)
#define SMU_TWI1TIN_SEL			(SMU_S0_BASE + 0x0604)
#define SMU_TWI2TIN_SEL			(SMU_S0_BASE + 0x0608)
#define SMU_TWI3TIN_SEL			(SMU_S0_BASE + 0x060C)
#define SMU_TGNTIN_SEL			(SMU_S0_BASE + 0x0610)
#define SMU_TIMCLKDIV			(SMU_S0_BASE + 0x0614)
#define SMU_USIASCLKDIV			(SMU_S0_BASE + 0x0618)
#define SMU_USIAU0SCLKDIV		(SMU_S0_BASE + 0x061C)

#define SMU_IICSCLKDIV			(SMU_S0_BASE + 0x0624)
#define SMU_USBSCLKDIV			(SMU_S0_BASE + 0x0628)
#define SMU_MEMCRCLKDIV			(SMU_S0_BASE + 0x062C)
#define SMU_LCDLCLKDIV			(SMU_S0_BASE + 0x0630)

#define SMU_CFISCLKDIV			(SMU_S0_BASE + 0x063C)

#define SMU_NTSSCLKDIV			(SMU_S0_BASE + 0x0640)
#define SMU_SDCSCLKDIV			(SMU_S0_BASE + 0x0644)
#define SMU_SDIO0SCLKDIV		(SMU_S0_BASE + 0x0648)
#define SMU_SDIO1SCLKDIV		(SMU_S0_BASE + 0x064C)

#define SMU_USIB0SCLKDIV		(SMU_S0_BASE + 0x0654)

#define SMU_USIB2SCLKDIV		(SMU_S0_BASE + 0x065C)
#define SMU_USIB3SCLKDIV		(SMU_S0_BASE + 0x0660)
#define SMU_MSPSCLKDIV			(SMU_S0_BASE + 0x0664)

#define SMU_PWMPWCLKDIV			(SMU_S0_BASE + 0x066C)
#define SMU_CAMSCLKDIV			(SMU_S0_BASE + 0x0670)

#define SMU_AVECCLKDIV			(SMU_S0_BASE + 0x0680)
#define SMU_QRCLKDIV			(SMU_S0_BASE + 0x0684)
#define SMU_STI_CLKSEL			(SMU_S0_BASE + 0x0688)
#define SMU_REFCLKDIV			(SMU_S0_BASE + 0x068C)

#define SMU_TW4TIN_SEL			(SMU_S0_BASE + 0x0698)
#define SMU_INTA_CLKSEL			(SMU_S0_BASE + 0x069C)

#define SMU_USIB4SCLKDIV		(SMU_S0_BASE + 0x06A8)

#define SMU_CKRQMODE_MASK0		(SMU_S0_BASE + 0x0700)
#define SMU_CKRQMODE_MASK1		(SMU_S0_BASE + 0x0704)
#define SMU_CKRQ_MODE			(SMU_S0_BASE + 0x0708)

#define SMU_DFS_FIFOMODE		(SMU_S0_BASE + 0x0710)
#define SMU_DFS_FIFO_REQMASK		(SMU_S0_BASE + 0x0714)
#define SMU_LCD_FIFOTHRESHOLD		(SMU_S0_BASE + 0x0718)

#define SMU_GENERAL_REG0		(SMU_S0_BASE + 0x07C0)

#define SMU_SEQ_BUSY			(SMU_S0_BASE + 0x0830)

#define SMU_PU_SWON			(SMU_S0_BASE + 0x083C)

#define SMU_PD_SWON			(SMU_S0_BASE + 0x0848)

#define SMU_PG_SWON			(SMU_S0_BASE + 0x0854)

#if defined(CONFIG_ICX) || defined(CONFIG_ICD)
#define SMU_P1_RFF_PARA1		(SMU_S0_BASE + 0x08AC)
#define SMU_P0_SWENA			(SMU_S0_BASE + 0x08E4)
#endif /* CONFIG_ICX || CONFIG_ICD */

#define SMU_QR_WFI			(SMU_S0_BASE + 0x09B8)

#define SMU_PC_PWSW_PARA		(SMU_S0_BASE + 0x09F0)
#define SMU_QR_WAITCNT			(SMU_S0_BASE + 0x09F4)

/* offset 0x1000 */
#define	SMU_S0_BASE_1000		(0xe0111000)
#define SMU_CKRQMODE_MASK2		(SMU_S0_BASE_1000 + 0x0010)

/* offset 0x2000 */
#define	SMU_S0_BASE_2000		(0xe0112000)
#define	SMU_CHIP_REVISION		(SMU_S0_BASE_2000 + 0x0000)

/**************************
 * MEMC
 **************************/
#define	MEMC_BASE			(0xe00a0000)
#define MEMC_CACHE_MODE			(MEMC_BASE + 0x0000)
#define MEMC_DEGFUN			(MEMC_BASE + 0x0008)

#define MEMC_REQSCH			(MEMC_BASE + 0x1000)

#define MEMC_DDR_BASE			(MEMC_BASE + 0x2000)
#define MEMC_DDR_CONFIGF		(MEMC_DDR_BASE + 0x0000)
#define MEMC_DDR_CONFIGA1		(MEMC_DDR_BASE + 0x0004)
#define MEMC_DDR_CONFIGA2		(MEMC_DDR_BASE + 0x0008)
#define MEMC_DDR_CONFIGC1		(MEMC_DDR_BASE + 0x000C)
#define MEMC_DDR_CONFIGC2		(MEMC_DDR_BASE + 0x0010)
#define MEMC_DDR_CONFIGR1		(MEMC_DDR_BASE + 0x0014)
#define MEMC_DDR_CONFIGR2		(MEMC_DDR_BASE + 0x0018)
#define MEMC_DDR_CONFIGR3		(MEMC_DDR_BASE + 0x001C)
#define MEMC_DDR_CONFIGT1		(MEMC_DDR_BASE + 0x0020)
#define MEMC_DDR_CONFIGT2		(MEMC_DDR_BASE + 0x0024)
#define MEMC_DDR_CONFIGT3		(MEMC_DDR_BASE + 0x0028)
#define MEMC_DDR_STATE8			(MEMC_DDR_BASE + 0x002C)
#define MEMC_DDR_CONFIGD		(MEMC_DDR_BASE + 0x0030)

#define MEMC_DDR_CONFIGZD		(MEMC_DDR_BASE + 0x0038)
#define MEMC_DDR_CONFIGZC		(MEMC_DDR_BASE + 0x003C)
#define MEMC_DDR_CONFIGZA		(MEMC_DDR_BASE + 0x0040)

/**************************
 * FUSE
 **************************/
#define	AFS_BASE			0xe00c0000

#if defined(CONFIG_ICX) || defined(CONFIG_ICD)
#define AFS_DRAM_TYPE		(AFS_BASE + 0x0008)
#endif /* CONFIG_ICX || CONFIG_ICD */
#define AFS_DATA1			(AFS_BASE + 0x0024)
#define AFS_DATA2			(AFS_BASE + 0x0028)
#define AFS_DATA3			(AFS_BASE + 0x002c)

/**************************
 * CHG
 **************************/
#define	CHG_BASE			(0xe0140000)
/* Boot Mode */
#define CHG_BOOT_MODE			(CHG_BASE + 0x0000)
#define CHG_P1_LAT			(CHG_BASE + 0x0004)

#define CHG_CTRL_SDINT			(CHG_BASE + 0x0104)
#define CHG_CTRL_AB0_BOOT		(CHG_BASE + 0x0108)
#define CHG_LCD_ENABLE			(CHG_BASE + 0x0110)

/* Pin Select */
#define CHG_PINSEL_G000			(CHG_BASE + 0x0200)
#define CHG_PINSEL_G032			(CHG_BASE + 0x0204)
#define CHG_PINSEL_G064			(CHG_BASE + 0x0208)
#define CHG_PINSEL_G096			(CHG_BASE + 0x020C)
#define CHG_PINSEL_G128			(CHG_BASE + 0x0210)

#define CHG_PINSEL_LCD			(CHG_BASE + 0x0280)
#if defined(CONFIG_ICX) || defined(CONFIG_ICD)
#define CHG_PINSEL_LCD3			(CHG_BASE + 0x0284)
#endif /* CONFIG_ICX || CONFIG_ICD */

#define CHG_PINSEL_UART			(CHG_BASE + 0x0288)
#define CHG_PINSEL_SD			(CHG_BASE + 0x0290)
#define CHG_PINSEL_AB			(CHG_BASE + 0x0294)
#define CHG_PINSEL_USI			(CHG_BASE + 0x0298)

/* Pin Pull Up/Down */
#define CHG_PULL0			(CHG_BASE + 0x0300)
#define CHG_PULL1			(CHG_BASE + 0x0304)
#define CHG_PULL2			(CHG_BASE + 0x0308)
#define CHG_PULL3			(CHG_BASE + 0x030C)
#define CHG_PULL4			(CHG_BASE + 0x0310)
#define CHG_PULL5			(CHG_BASE + 0x0314)
#define CHG_PULL6			(CHG_BASE + 0x0318)
#define CHG_PULL7			(CHG_BASE + 0x031C)
#define CHG_PULL8			(CHG_BASE + 0x0320)
#define CHG_PULL9			(CHG_BASE + 0x0324)
#define CHG_PULL10			(CHG_BASE + 0x0328)
#define CHG_PULL11			(CHG_BASE + 0x032C)
#define CHG_PULL12			(CHG_BASE + 0x0330)
#define CHG_PULL13			(CHG_BASE + 0x0334)
#define CHG_PULL14			(CHG_BASE + 0x0338)
#define CHG_PULL15			(CHG_BASE + 0x033C)
#define CHG_PULL16			(CHG_BASE + 0x0340)
#define CHG_PULL17			(CHG_BASE + 0x0344)
#define CHG_PULL18			(CHG_BASE + 0x0348)
#define CHG_PULL19			(CHG_BASE + 0x034C)
#define CHG_PULL20			(CHG_BASE + 0x0350)
#define CHG_PULL21			(CHG_BASE + 0x0354)
#define CHG_PULL22			(CHG_BASE + 0x0358)
#define CHG_PULL23			(CHG_BASE + 0x035C)
#define CHG_PULL24			(CHG_BASE + 0x0360)
#define CHG_PULL25			(CHG_BASE + 0x0364)

#define CHG_DRIVE0			(CHG_BASE + 0x0400)
#define CHG_DRIVE1			(CHG_BASE + 0x0404)
#define CHG_DRIVE2			(CHG_BASE + 0x0408)
#define CHG_DRIVE3			(CHG_BASE + 0x040C)
#define CHG_DRIVE4			(CHG_BASE + 0x0410)
#define CHG_DRIVE5			(CHG_BASE + 0x0414)

#define CHG_BUSHOLD			(CHG_BASE + 0x0500)

#define CHG_FLASHCLK_SEL		(CHG_BASE + 0x0510)

#define CHG_SDIO_CNT_SET		(CHG_BASE + 0x0520)


/**************************
 * AB0
 **************************/
#define	AB0_BASE			(0x2fff0000)
#define	AB0_FLASHCOMSET			(AB0_BASE + 0x000)
#define	AB0_FLASHCOMLATCH		(AB0_BASE + 0x004)

#define	AB0_FLASHCOMADD0		(AB0_BASE + 0x010)
#define	AB0_FLASHCOMDATA0		(AB0_BASE + 0x014)
#define	AB0_FLASHCOMADD1		(AB0_BASE + 0x018)
#define	AB0_FLASHCOMDATA1		(AB0_BASE + 0x01c)

#define	AB0_FLASHCLKCTRL		(AB0_BASE + 0x080)
#define	AB0_FLA_RCLK_DLY		(AB0_BASE + 0x084)

#define	AB0_WAIT_STATUS			(AB0_BASE + 0x090)

#define	AB0_CS0BASEADD			(AB0_BASE + 0x100)
#define	AB0_CS0BITCOMP			(AB0_BASE + 0x104)
#define	AB0_CS1BASEADD			(AB0_BASE + 0x110)
#define	AB0_CS1BITCOMP			(AB0_BASE + 0x114)
#define	AB0_CS2BASEADD			(AB0_BASE + 0x120)
#define	AB0_CS2BITCOMP			(AB0_BASE + 0x124)
#define	AB0_CS3BASEADD			(AB0_BASE + 0x130)
#define	AB0_CS3BITCOMP			(AB0_BASE + 0x134)
#define	AB0_CS4BASEADD			(AB0_BASE + 0x140)
#define	AB0_CS4BITCOMP			(AB0_BASE + 0x144)
#define	AB0_CS5BASEADD			(AB0_BASE + 0x150)
#define	AB0_CS5BITCOMP			(AB0_BASE + 0x154)

#define	AB0_CS0WAITCTRL			(AB0_BASE + 0x200)
#define	AB0_CS0WAITCTRL_W		(AB0_BASE + 0x204)
#define	AB0_CS0READCTRL			(AB0_BASE + 0x208)
#define	AB0_CS0WAIT_MASK		(AB0_BASE + 0x20c)
#define	AB0_CS0CONTROL			(AB0_BASE + 0x210)
#define	AB0_CS0FLASHRCR			(AB0_BASE + 0x214)
#define	AB0_CS0FLASHWCR			(AB0_BASE + 0x218)

#define	AB0_CS1WAITCTRL			(AB0_BASE + 0x220)
#define	AB0_CS1WAITCTRL_W		(AB0_BASE + 0x224)
#define	AB0_CS1READCTRL			(AB0_BASE + 0x228)
#define	AB0_CS1WAIT_MASK		(AB0_BASE + 0x22c)
#define	AB0_CS1CONTROL			(AB0_BASE + 0x230)
#define	AB0_CS1FLASHRCR			(AB0_BASE + 0x234)
#define	AB0_CS1FLASHWCR			(AB0_BASE + 0x238)

#define	AB0_CS2WAITCTRL			(AB0_BASE + 0x240)
#define	AB0_CS2WAITCTRL_W		(AB0_BASE + 0x244)
#define	AB0_CS2READCTRL			(AB0_BASE + 0x248)
#define	AB0_CS2WAIT_MASK		(AB0_BASE + 0x24c)
#define	AB0_CS2CONTROL			(AB0_BASE + 0x250)
#define	AB0_CS2FLASHRCR			(AB0_BASE + 0x254)
#define	AB0_CS2FLASHWCR			(AB0_BASE + 0x258)

#define	AB0_CS3WAITCTRL			(AB0_BASE + 0x260)
#define	AB0_CS3WAITCTRL_W		(AB0_BASE + 0x264)
#define	AB0_CS3READCTRL			(AB0_BASE + 0x268)
#define	AB0_CS3WAIT_MASK		(AB0_BASE + 0x26c)
#define	AB0_CS3CONTROL			(AB0_BASE + 0x270)
#define	AB0_CS3FLASHRCR			(AB0_BASE + 0x274)
#define	AB0_CS3FLASHWCR			(AB0_BASE + 0x278)

#define	AB0_CS4WAITCTRL			(AB0_BASE + 0x280)
#define	AB0_CS4WAITCTRL_W		(AB0_BASE + 0x284)
#define	AB0_CS4READCTRL			(AB0_BASE + 0x288)
#define	AB0_CS4WAIT_MASK		(AB0_BASE + 0x28c)
#define	AB0_CS4CONTROL			(AB0_BASE + 0x290)
#define	AB0_CS4FLASHRCR			(AB0_BASE + 0x294)
#define	AB0_CS4FLASHWCR			(AB0_BASE + 0x298)

#define	AB0_CS5WAITCTRL			(AB0_BASE + 0x2a0)
#define	AB0_CS5WAITCTRL_W		(AB0_BASE + 0x2a4)
#define	AB0_CS5READCTRL			(AB0_BASE + 0x2a8)
#define	AB0_CS5WAIT_MASK		(AB0_BASE + 0x2ac)
#define	AB0_CS5CONTROL			(AB0_BASE + 0x2b0)
#define	AB0_CS5FLASHRCR			(AB0_BASE + 0x2b4)
#define	AB0_CS5FLASHWCR			(AB0_BASE + 0x2b8)


/**************************
 * GIO
 **************************/
#define	GIO_BASE			(0xe0050000)
#define	GIO_000_BASE			(GIO_BASE + 0x0000)
#define	GIO_032_BASE			(GIO_BASE + 0x0080)
#define	GIO_064_BASE			(GIO_BASE + 0x0100)
#define	GIO_096_BASE			(GIO_BASE + 0x0180)
#define	GIO_128_BASE			(GIO_BASE + 0x0200)

/* offset address */
#define GIO_E1				0x0000
#define GIO_E0				0x0004
#define GIO_EM				0x0004
#define GIO_OL				0x0008
#define GIO_OH				0x000C
#define GIO_I				0x0010
#define GIO_IIA				0x0014
#define GIO_IEN				0x0018
#define GIO_IDS				0x001C
#define GIO_IIM				0x001C
#define GIO_RAW				0x0020
#define GIO_MST				0x0024
#define GIO_IIR				0x0028
#define GIO_GSW				0x003C
#define GIO_IDT0			0x0040
#define GIO_IDT1			0x0044
#define GIO_IDT2			0x0048
#define GIO_IDT3			0x004C
#define GIO_RAWBL			0x0050
#define GIO_RAWBH			0x0054
#define GIO_IRBL			0x0058
#define GIO_IRBH			0x005C

#define GIO_000_E1			(GIO_000_BASE + GIO_E1)
#define GIO_000_E0			(GIO_000_BASE + GIO_E0)
#define GIO_000_EM			(GIO_000_BASE + GIO_EM)
#define GIO_000_OL			(GIO_000_BASE + GIO_OL)
#define GIO_000_OH			(GIO_000_BASE + GIO_OH)
#define GIO_000_I			(GIO_000_BASE + GIO_I)
#define GIO_000_IIA			(GIO_000_BASE + GIO_IIA)
#define GIO_000_IEN			(GIO_000_BASE + GIO_IEN)
#define GIO_000_IDS			(GIO_000_BASE + GIO_IDS)
#define GIO_000_IIM			(GIO_000_BASE + GIO_IIM)
#define GIO_000_RAW			(GIO_000_BASE + GIO_RAW)
#define GIO_000_MST			(GIO_000_BASE + GIO_MST)
#define GIO_000_IIR			(GIO_000_BASE + GIO_IIR)
#define GIO_000_GSW			(GIO_000_BASE + GIO_GSW)
#define GIO_000_IDT0			(GIO_000_BASE + GIO_IDT0)
#define GIO_000_IDT1			(GIO_000_BASE + GIO_IDT1)
#define GIO_000_IDT2			(GIO_000_BASE + GIO_IDT2)
#define GIO_000_IDT3			(GIO_000_BASE + GIO_IDT3)
#define GIO_000_RAWBL			(GIO_000_BASE + GIO_RAWBL)
#define GIO_000_RAWBH			(GIO_000_BASE + GIO_RAWBH)
#define GIO_000_IRBL			(GIO_000_BASE + GIO_IRBL)
#define GIO_000_IRBH			(GIO_000_BASE + GIO_IRBH)
#define GIO_032_E1			(GIO_032_BASE + GIO_E1)
#define GIO_032_E0			(GIO_032_BASE + GIO_E0)
#define GIO_032_EM			(GIO_032_BASE + GIO_EM)
#define GIO_032_OL			(GIO_032_BASE + GIO_OL)
#define GIO_032_OH			(GIO_032_BASE + GIO_OH)
#define GIO_032_I			(GIO_032_BASE + GIO_I)
#define GIO_032_IIA			(GIO_032_BASE + GIO_IIA)
#define GIO_032_IEN			(GIO_032_BASE + GIO_IEN)
#define GIO_032_IDS			(GIO_032_BASE + GIO_IDS)
#define GIO_032_IIM			(GIO_032_BASE + GIO_IIM)
#define GIO_032_RAW			(GIO_032_BASE + GIO_RAW)
#define GIO_032_MST			(GIO_032_BASE + GIO_MST)
#define GIO_032_IIR			(GIO_032_BASE + GIO_IIR)
#define GIO_032_GSW			(GIO_032_BASE + GIO_GSW)
#define GIO_032_IDT0			(GIO_032_BASE + GIO_IDT0)
#define GIO_032_IDT1			(GIO_032_BASE + GIO_IDT1)
#define GIO_032_IDT2			(GIO_032_BASE + GIO_IDT2)
#define GIO_032_IDT3			(GIO_032_BASE + GIO_IDT3)
#define GIO_032_RAWBL			(GIO_032_BASE + GIO_RAWBL)
#define GIO_032_RAWBH			(GIO_032_BASE + GIO_RAWBH)
#define GIO_032_IRBL			(GIO_032_BASE + GIO_IRBL)
#define GIO_032_IRBH			(GIO_032_BASE + GIO_IRBH)

#define GIO_064_E1			(GIO_064_BASE + GIO_E1)
#define GIO_064_E0			(GIO_064_BASE + GIO_E0)
#define GIO_064_EM			(GIO_064_BASE + GIO_EM)
#define GIO_064_OL			(GIO_064_BASE + GIO_OL)
#define GIO_064_OH			(GIO_064_BASE + GIO_OH)
#define GIO_064_I			(GIO_064_BASE + GIO_I)
#define GIO_064_IIA			(GIO_064_BASE + GIO_IIA)
#define GIO_064_IEN			(GIO_064_BASE + GIO_IEN)
#define GIO_064_IDS			(GIO_064_BASE + GIO_IDS)
#define GIO_064_IIM			(GIO_064_BASE + GIO_IIM)
#define GIO_064_RAW			(GIO_064_BASE + GIO_RAW)
#define GIO_064_MST			(GIO_064_BASE + GIO_MST)
#define GIO_064_IIR			(GIO_064_BASE + GIO_IIR)
#define GIO_064_GSW			(GIO_064_BASE + GIO_GSW)
#define GIO_064_IDT0			(GIO_064_BASE + GIO_IDT0)
#define GIO_064_IDT1			(GIO_064_BASE + GIO_IDT1)
#define GIO_064_IDT2			(GIO_064_BASE + GIO_IDT2)
#define GIO_064_IDT3			(GIO_064_BASE + GIO_IDT3)
#define GIO_064_RAWBL			(GIO_064_BASE + GIO_RAWBL)
#define GIO_064_RAWBH			(GIO_064_BASE + GIO_RAWBH)
#define GIO_064_IRBL			(GIO_064_BASE + GIO_IRBL)
#define GIO_064_IRBH			(GIO_064_BASE + GIO_IRBH)

#define GIO_096_E1			(GIO_096_BASE + GIO_E1)
#define GIO_096_E0			(GIO_096_BASE + GIO_E0)
#define GIO_096_EM			(GIO_096_BASE + GIO_EM)
#define GIO_096_OL			(GIO_096_BASE + GIO_OL)
#define GIO_096_OH			(GIO_096_BASE + GIO_OH)
#define GIO_096_I			(GIO_096_BASE + GIO_I)
#define GIO_096_IIA			(GIO_096_BASE + GIO_IIA)
#define GIO_096_IEN			(GIO_096_BASE + GIO_IEN)
#define GIO_096_IDS			(GIO_096_BASE + GIO_IDS)
#define GIO_096_IIM			(GIO_096_BASE + GIO_IIM)
#define GIO_096_RAW			(GIO_096_BASE + GIO_RAW)
#define GIO_096_MST			(GIO_096_BASE + GIO_MST)
#define GIO_096_IIR			(GIO_096_BASE + GIO_IIR)
#define GIO_096_GSW			(GIO_096_BASE + GIO_GSW)
#define GIO_096_IDT0			(GIO_096_BASE + GIO_IDT0)
#define GIO_096_IDT1			(GIO_096_BASE + GIO_IDT1)
#define GIO_096_IDT2			(GIO_096_BASE + GIO_IDT2)
#define GIO_096_IDT3			(GIO_096_BASE + GIO_IDT3)
#define GIO_096_RAWBL			(GIO_096_BASE + GIO_RAWBL)
#define GIO_096_RAWBH			(GIO_096_BASE + GIO_RAWBH)
#define GIO_096_IRBL			(GIO_096_BASE + GIO_IRBL)
#define GIO_096_IRBH			(GIO_096_BASE + GIO_IRBH)

#define GIO_128_E1			(GIO_128_BASE + GIO_E1)
#define GIO_128_E0			(GIO_128_BASE + GIO_E0)
#define GIO_128_EM			(GIO_128_BASE + GIO_EM)
#define GIO_128_OL			(GIO_128_BASE + GIO_OL)
#define GIO_128_OH			(GIO_128_BASE + GIO_OH)
#define GIO_128_I			(GIO_128_BASE + GIO_I)
#define GIO_128_IIA			(GIO_128_BASE + GIO_IIA)
#define GIO_128_IEN			(GIO_128_BASE + GIO_IEN)
#define GIO_128_IDS			(GIO_128_BASE + GIO_IDS)
#define GIO_128_IIM			(GIO_128_BASE + GIO_IIM)
#define GIO_128_RAW			(GIO_128_BASE + GIO_RAW)
#define GIO_128_MST			(GIO_128_BASE + GIO_MST)
#define GIO_128_IIR			(GIO_128_BASE + GIO_IIR)
#define GIO_128_GSW			(GIO_128_BASE + GIO_GSW)
#define GIO_128_IDT0			(GIO_128_BASE + GIO_IDT0)
#define GIO_128_IDT1			(GIO_128_BASE + GIO_IDT1)
#define GIO_128_IDT2			(GIO_128_BASE + GIO_IDT2)
#define GIO_128_IDT3			(GIO_128_BASE + GIO_IDT3)
#define GIO_128_RAWBL			(GIO_128_BASE + GIO_RAWBL)
#define GIO_128_RAWBH			(GIO_128_BASE + GIO_RAWBH)
#define GIO_128_IRBL			(GIO_128_BASE + GIO_IRBL)
#define GIO_128_IRBH			(GIO_128_BASE + GIO_IRBH)

/**************************
 * INTA
 **************************/
#define INTA_BASE			0xe0020000
#define INTD_BASE			0xe00e0000

#define INTA_CPU_BASE			(INTA_BASE + 0x00000000)
#define INTA_DST_BASE			(INTA_BASE + 0x00008000)

#define GIC_CPU_CTRL			(INTA_CPU_BASE + 0x000)
#define GIC_CPU_PRIMASK			(INTA_CPU_BASE + 0x004)
#define GIC_CPU_BINPOINT		(INTA_CPU_BASE + 0x008)
#define GIC_CPU_INTACK			(INTA_CPU_BASE + 0x00c)
#define GIC_CPU_EOI			(INTA_CPU_BASE + 0x010)
#define GIC_CPU_RUNNINGPRI		(INTA_CPU_BASE + 0x014)
#define GIC_CPU_HIGHPRI			(INTA_CPU_BASE + 0x018)

#define GIC_DIST_CTRL			(INTA_DST_BASE + 0x000)
#define GIC_DIST_CTR			(INTA_DST_BASE + 0x004)
#define GIC_DIST_ENABLE_SET		(INTA_DST_BASE + 0x100)
#define GIC_DIST_ENABLE_CLEAR		(INTA_DST_BASE + 0x180)
#define GIC_DIST_PENDING_SET		(INTA_DST_BASE + 0x200)
#define GIC_DIST_PENDING_CLEAR		(INTA_DST_BASE + 0x280)
#define GIC_DIST_ACTIVE_BIT		(INTA_DST_BASE + 0x300)
#define GIC_DIST_PRI			(INTA_DST_BASE + 0x400)
#define GIC_DIST_TARGET			(INTA_DST_BASE + 0x800)
#define GIC_DIST_CONFIG			(INTA_DST_BASE + 0xc00)
#define GIC_DIST_SOFTINT		(INTA_DST_BASE + 0xf00)

#define INTD_IT_PINV_SET2		(INTD_BASE + 0x308)


#if defined(CONFIG_ICX) || defined(CONFIG_ICD)

/**************************
 * PMU
 **************************/
#define PMU_BASE				0xe0100000

#define	PMU_PC					(PMU_BASE + 0x0004)
#define	PMU_START				(PMU_BASE + 0x0008)
#define PMU_POWER_ON_PC			(PMU_BASE + 0x0030)
#define PMU_WDT_COUNT_EN		(PMU_BASE + 0x0060)
#define PMU_WDT_COUNT_LMT		(PMU_BASE + 0x0064)
#define PMU_INT_HANDLER_PC		(PMU_BASE + 0x0068)
#define PMU_INTENSET_A			(PMU_BASE + 0x0088)
#define PMU_INTFFCLR_A			(PMU_BASE + 0x0090)
#define PMU_INTENSET_M			(PMU_BASE + 0x009c)
#define PMU_INTFFCLR_M			(PMU_BASE + 0x00a4)


/**************************
 * PWM
 **************************/
#define PWM_BASE				0xe1130000

#define PWM_CH0_BASE			(PWM_BASE + 0x0000)
#define PWM_CH1_BASE			(PWM_BASE + 0x0100)

#define PWM_CTRL				0x0000
#define PWM_MODE				0x0004
#define PWM_DELAY0				0x0010
#define PWM_LEDGE0				0x0014
#define PWM_TEDGE0				0x0018
#define PWM_TOTAL0				0x001c
#define	PWM_LOOP0				0x0020

#define PWM_CH1_CTRL			(PWM_CH1_BASE + PWM_CTRL)
#define PWM_CH1_MODE			(PWM_CH1_BASE + PWM_MODE)
#define PWM_CH1_DELAY0			(PWM_CH1_BASE + PWM_DELAY0)
#define PWM_CH1_LEDGE0			(PWM_CH1_BASE + PWM_LEDGE0)
#define PWM_CH1_TEDGE0			(PWM_CH1_BASE + PWM_TEDGE0)
#define PWM_CH1_TOTAL0			(PWM_CH1_BASE + PWM_TOTAL0)
#define PWM_CH1_LOOP0			(PWM_CH1_BASE + PWM_LOOP0)

#define PWM_INTENSET			(PWM_BASE + 0x0408)


/**************************
 * LCD
 **************************/
#define	LCD_BASE				0xe0040000

#define LCD_CONTROL				(LCD_BASE + 0x000)
#define LCD_QOS					(LCD_BASE + 0x004)
#define LCD_DATAREQ				(LCD_BASE + 0x008)
#define LCD_LCDOUT				(LCD_BASE + 0x010)
#define LCD_BUSSEL				(LCD_BASE + 0x014)
#define LCD_STATUS				(LCD_BASE + 0x018)
#define LCD_BACKCOLOR			(LCD_BASE + 0x01c)
#define LCD_AREAADR_ODD			(LCD_BASE + 0x020)
#define LCD_AREAADR_EVEN		(LCD_BASE + 0x024)
#define LCD_HOFFSET				(LCD_BASE + 0x028)
#define LCD_IFORMAT				(LCD_BASE + 0x02c)
#define LCD_HTOTAL				(LCD_BASE + 0x040)
#define LCD_HAREA				(LCD_BASE + 0x044)
#define LCD_HEDGE1				(LCD_BASE + 0x048)
#define LCD_HEDGE2				(LCD_BASE + 0x04c)
#define LCD_VTOTAL				(LCD_BASE + 0x050)
#define LCD_VAREA				(LCD_BASE + 0x054)
#define LCD_VEDGE1				(LCD_BASE + 0x058)
#define LCD_VEDGE2				(LCD_BASE + 0x05c)
#define LCD_INTENCLR			(LCD_BASE + 0x06c)
#define LCD_INTFFCLR			(LCD_BASE + 0x070)


/**************************
 * IMC
 **************************/
#define	IMC_BASE				0xe1260000

#define IMC_CONTROL				(IMC_BASE + 0x000)
#define IMC_REFRESH				(IMC_BASE + 0x004)
#define IMC_WB_AREAADR_P		(IMC_BASE + 0x040)
#define IMC_WB_HOFFSET			(IMC_BASE + 0x044)
#define IMC_WB_FORMAT			(IMC_BASE + 0x048)
#define IMC_WB_SIZE				(IMC_BASE + 0x04c)
#define IMC_L1A_CONTROL			(IMC_BASE + 0x300)
#define IMC_L1A_FORMAT			(IMC_BASE + 0x304)
#define IMC_L1A_ALPHA			(IMC_BASE + 0x318)
#define IMC_L1A_OFFSET			(IMC_BASE + 0x330)
#define IMC_L1A_FRAMEADR_P		(IMC_BASE + 0x334)
#define IMC_L1A_SIZE			(IMC_BASE + 0x354)
#define IMC_BG_FORMAT			(IMC_BASE + 0x804)
#define IMC_BG_OFFSET			(IMC_BASE + 0x830)


/**************************
 * I2C
 **************************/
#define	IIC0_BASE				0xe0070000

#define IIC_IICACT0				(IIC0_BASE + 0x000)
#define IIC_IIC0				(IIC0_BASE + 0x004)
#define IIC_IICC0				(IIC0_BASE + 0x008)
#define IIC_SVA0				(IIC0_BASE + 0x00c)
#define IIC_IICCL0				(IIC0_BASE + 0x010)
#define IIC_IICX0				(IIC0_BASE + 0x014)
#define IIC_IICS0				(IIC0_BASE + 0x018)
#define IIC_IICSE0				(IIC0_BASE + 0x01c)
#define IIC_IICF0				(IIC0_BASE + 0x020)

#endif /* CONFIG_ICX || CONFIG_ICD */

/* SRAM */
#define	SRAM_HWINFO_BOOT		0xf001ffe0

/* UART */
#define UART0_BASE			0xe1020000
#define UART0_FCR			(UART0_BASE + 0x0c)
#ifdef CONFIG_ICX
#define UART3_BASE			0xe1050000
#define UART3_FCR			(UART3_BASE + 0x0c)
#endif /* CONFIG_ICX */

/* L2CC */
#define L2CC_BASE			0x1e00a000
#define L2CC_ADD_FILTER_START		(L2CC_BASE + 0xc00)
#define L2CC_ADD_FILTER_END		(L2CC_BASE + 0xc04)

/* SMSC EEPROM access */
#define	SMSC9118_BASE			0x20000000
#define HW_CFG	 			(SMSC9118_BASE + 0x74)
#define E2P_CMD 			(SMSC9118_BASE + 0xB0)
#define E2P_DATA			(SMSC9118_BASE + 0xB4)

#endif /* _REG_H */
