/* 2012-09-16: File added by Sony Corporation */
/*
 * icx_smu.h
 *
 * Copyright 2011 Sony Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#ifndef __ICX_SMU_H__
#define __ICX_SMU_H__

/**********************/
/*@ group of register */
/**********************/

/* auto clock control */
#define SMU_AHBCLKCTRL0_GROUP       (0 << 16)
#define SMU_AHBCLKCTRL1_GROUP       (1 << 16)
#define SMU_AHBCLKCTRL2_GROUP       (2 << 16)
#define SMU_AHBCLKCTRL3_GROUP       (3 << 16)
#define SMU_APBCLKCTRL0_GROUP       (4 << 16)
#define SMU_APBCLKCTRL1_GROUP       (5 << 16)
#define SMU_APBCLKCTRL2_GROUP       (6 << 16)
#define SMU_CLKCTRL_GROUP           (7 << 16)
#define SMU_AVECLKCTRL_GROUP		(8 << 16)


/***********************/
/*@ group & bit assign */
/***********************/

#define SMU_REG_SHIFT(x)			(((x) & 0xffff) << 16)

/* RESETREQ */
#define SMU_RST_USIA_S0_A			(SMU_REG_SHIFT(SMU_USIAS0_RSTCTRL) | 2)
#define SMU_RST_USIA_S0_S			(SMU_REG_SHIFT(SMU_USIAS0_RSTCTRL) | 1)
#define SMU_RST_USIA_S1_A			(SMU_REG_SHIFT(SMU_USIAS1_RSTCTRL) | 2)
#define SMU_RST_USIA_S1_S			(SMU_REG_SHIFT(SMU_USIAS1_RSTCTRL) | 1)
#define SMU_RST_USIB_S2_A			(SMU_REG_SHIFT(SMU_USIBS2_RSTCTRL) | 2)
#define SMU_RST_USIB_S2_S			(SMU_REG_SHIFT(SMU_USIBS2_RSTCTRL) | 1)
#define SMU_RST_USIB_S3_A			(SMU_REG_SHIFT(SMU_USIBS3_RSTCTRL) | 2)
#define SMU_RST_USIB_S3_S			(SMU_REG_SHIFT(SMU_USIBS3_RSTCTRL) | 1)
#define SMU_RST_PWM					(SMU_REG_SHIFT(SMU_PWM_RSTCTRL   ) | 1)
#define SMU_RST_LCD_A				(SMU_REG_SHIFT(SMU_LCD_RSTCTRL   ) | 2)
#define SMU_RST_LCD					(SMU_REG_SHIFT(SMU_LCD_RSTCTRL   ) | 1)
#define SMU_RST_IMC					(SMU_REG_SHIFT(SMU_IMC_RSTCTRL   ) | 1)
#define SMU_RST_IIC0				(SMU_REG_SHIFT(SMU_IIC0_RSTCTRL  ) | 1)

/* GCLKCTRL */
#define SMU_CLK_USIA_S0_H			(SMU_REG_SHIFT(SMU_USIAS0GCLKCTRL) | 4)
#define SMU_CLK_USIA_S0_S			(SMU_REG_SHIFT(SMU_USIAS0GCLKCTRL) | 2)
#define SMU_CLK_USIA_S0_P			(SMU_REG_SHIFT(SMU_USIAS0GCLKCTRL) | 1)
#define SMU_CLK_USIA_S1_H			(SMU_REG_SHIFT(SMU_USIAS1GCLKCTRL) | 4)
#define SMU_CLK_USIA_S1_S			(SMU_REG_SHIFT(SMU_USIAS1GCLKCTRL) | 2)
#define SMU_CLK_USIA_S1_P			(SMU_REG_SHIFT(SMU_USIAS1GCLKCTRL) | 1)
#define SMU_CLK_USIB_S2_H			(SMU_REG_SHIFT(SMU_USIBS2GCLKCTRL) | 4)
#define SMU_CLK_USIB_S2_S			(SMU_REG_SHIFT(SMU_USIBS2GCLKCTRL) | 2)
#define SMU_CLK_USIB_S2_P			(SMU_REG_SHIFT(SMU_USIBS2GCLKCTRL) | 1)
#define SMU_CLK_USIB_S3_H			(SMU_REG_SHIFT(SMU_USIBS3GCLKCTRL) | 4)
#define SMU_CLK_USIB_S3_S			(SMU_REG_SHIFT(SMU_USIBS3GCLKCTRL) | 2)
#define SMU_CLK_USIB_S3_P			(SMU_REG_SHIFT(SMU_USIBS3GCLKCTRL) | 1)
#define SMU_CLK_PWM_PWCLK1			(SMU_REG_SHIFT(SMU_PWMGCLKCTRL   ) | 4)
#define SMU_CLK_PWM_PWCLK0			(SMU_REG_SHIFT(SMU_PWMGCLKCTRL   ) | 2)
#define SMU_CLK_PWM_PCLK			(SMU_REG_SHIFT(SMU_PWMGCLKCTRL   ) | 1)
#define SMU_CLK_LCD_C				(SMU_REG_SHIFT(SMU_LCDGCLKCTRL   ) | 8)
#define SMU_CLK_LCD_L				(SMU_REG_SHIFT(SMU_LCDGCLKCTRL   ) | 4)
#define SMU_CLK_LCD_P				(SMU_REG_SHIFT(SMU_LCDGCLKCTRL   ) | 2)
#define SMU_CLK_LCD					(SMU_REG_SHIFT(SMU_LCDGCLKCTRL   ) | 1)
#define SMU_CLK_IMC					(SMU_REG_SHIFT(SMU_IMCGCLKCTRL   ) | 2)
#define SMU_CLK_IMC_P				(SMU_REG_SHIFT(SMU_IMCGCLKCTRL   ) | 1)
#define SMU_CLK_IIC0_S				(SMU_REG_SHIFT(SMU_IIC0GCLKCTRL  ) | 2)
#define SMU_CLK_IIC0				(SMU_REG_SHIFT(SMU_IIC0GCLKCTRL  ) | 1)
#define SMU_CLK_REF					(SMU_REG_SHIFT(SMU_REFGCLKCTRL   ) | 1)

/* Auto clock control */
#define SMU_CLKCTRL_IMC_PCLK		(SMU_AHBCLKCTRL1_GROUP |  5)
#define SMU_CLKCTRL_IMC				(SMU_AHBCLKCTRL1_GROUP |  4)
#define SMU_CLKCTRL_LCDC			(SMU_AHBCLKCTRL1_GROUP |  1)
#define SMU_CLKCTRL_LCD				(SMU_AHBCLKCTRL1_GROUP |  0)
#define SMU_CLKCTRL_LCDPCLK			(SMU_APBCLKCTRL1_GROUP |  0)
#define SMU_CLKCTRL_USIBS3PCLK		(SMU_APBCLKCTRL2_GROUP |  5)
#define SMU_CLKCTRL_USIBS2PCLK		(SMU_APBCLKCTRL2_GROUP |  4)
#define SMU_CLKCTRL_USIAS1PCLK		(SMU_APBCLKCTRL2_GROUP |  1)
#define SMU_CLKCTRL_USIAS0PCLK		(SMU_APBCLKCTRL2_GROUP |  0)
#define SMU_CLKCTRL_USIBS3			(SMU_AHBCLKCTRL3_GROUP |  5)
#define SMU_CLKCTRL_USIBS2			(SMU_AHBCLKCTRL3_GROUP |  4)
#define SMU_CLKCTRL_USIAS1			(SMU_AHBCLKCTRL3_GROUP |  1)
#define SMU_CLKCTRL_USIAS0			(SMU_AHBCLKCTRL3_GROUP |  0)


/*******************/
/*@ request values */
/*******************/

/* reset req */
#define SMU_RESETREQ_RESET          0
#define SMU_RESETREQ_UNRESET        1

/* gated clock */
#define SMU_GCLKCTRL_CLOSE          0
#define SMU_GCLKCTRL_OPEN           1

/* auto clock control */
#define SMU_AUTOCLKCTRL_DISABLE		0
#define SMU_AUTOCLKCTRL_ENABLE		1

/* PLL select */
#define SMU_PLLSEL_PLL3             0x00000000
#define SMU_PLLSEL_OSC0             0x00000200

/* DIV value */
#define SMU_DIV(x)					(x - 1)


/***************/
/*@ prototypes */
/***************/

int smu_reset_control(u_int, u_char);
int smu_clockgate_control(u_int, u_char);
int smu_autoclock_control(u_int, u_char);

#endif /* __ICX_SMU_H__ */
