/* 2009-04-20: File added and changed by Sony Corporation */
/*
 *  Copyright 2009 Sony Corporation.
 *
 *  This file is based on include/asm-arm/arch-mp200/mp200_board.h
 */
/*
 *  File Name       : linux/include/asm-arm/arch-mp200/mp200_board.h
 *  Function        : mp200_board
 *  Release Version : Ver 1.01
 *  Release Date    : 2006/02/22
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2006
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#ifndef __ASM_ARCH_PGPF_BOARD_H
#define __ASM_ARCH_PGPF_BOARD_H

#include <asm/arch/pgpf/gpio.h>
#include <asm/arch/pgpf/irqs.h>

/* BANK 0 -- ASYNC0 1/3 [NOR FLASH] */
#define MP200_BANK0_BASE	0x00000000

#define PGPF_ETHER_OFFSET	0x08000000
#define PGPF_ETHER_SIZE		64
#define PGPF_ETHER_BASE		(MP200_BANK0_BASE + PGPF_ETHER_OFFSET)

/* BANK 1 -- ASYNC0 2/3 */
#define MP200_BANK1_BASE	0x10000000

/* BANK 2 -- ASYNC0 3/3 */
#define MP200_BANK2_BASE	0x20000000

#if defined(CONFIG_PGPF_NAVU2)
#include <asm/arch/pgpf/navu2/target.h>
#endif

/* Kernel low-level debugging */
#define MP200_LL_UART_PORT	0
#define MP200_LL_UART_BAUD	115200
#define MP200_LL_UART_BASE	MP200_UART0_BASE

/* NBLArgs */
#define NBLARGS_STD_LEN		0x1000
#define NBLARGS_STD_ADDR	0xc1ffe000

/* PLL3 Clock */
#if defined(CONFIG_PLL3_238MHZ)
#define PGPF_PLL3_CLK (237568000)
#elif defined(CONFIG_PLL3_230MHZ)
#define PGPF_PLL3_CLK (229376000)
#endif /* CONFIG_PLL3_* */

/* PWM Divider Value */
#define PGPF_PWM_DIV (8)

/* Production Level */
#define PGPF_PRODUCTION_LEVEL_BB	0x1 /* 001b */
#define PGPF_PRODUCTION_LEVEL_LF	0x2 /* 010b */
#define PGPF_PRODUCTION_LEVEL_FF	0x3 /* 011b */
#define PGPF_PRODUCTION_LEVEL_FF2	0x4 /* 100b */
#define PGPF_PRODUCTION_LEVEL_RS	0x5 /* 101b */
#define PGPF_PRODUCTION_LEVEL_MP	0x6 /* 110b */

#endif				/* __ASM_ARCH_PGPF_BOARD_H */
