/* 2009-08-20: File added and changed by Sony Corporation */
/*
 *  File Name       : linux/include/asm-arm/arch-mp200/hardware.h
 *  Function        : hardware
 *  Release Version : Ver 1.04
 *  Release Date    : 2009/03/03
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2009
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#ifndef __ASM_ARM_ARCH_MP200_HARDWARE_H
#define __ASM_ARM_ARCH_MP200_HARDWARE_H

#include <asm/sizes.h>
#include <asm/arch/io.h>

#define VA_PEID			IO_ADDRESS(MP200_PEID_BASE)
#define VA_INTC			IO_ADDRESS(MP200_INTC_BASE)

/* ************************************************************************
 *   MP200 address map
 * ***********************************************************************/

/*
 *  MP200 memory map
 */

/* BANK 0/1/2 -- AB0 [NOR FLASH/External Device] */
#define MP200_BANK2_BASE	0x20000000
#define MP200_AB0_OFFSET	0x0fff0000
#define MP200_AB0_SIZE		SZ_64K

#define MP200_AB0_BASE		(MP200_BANK2_BASE+MP200_AB0_OFFSET)

/* BANK 3 -- DRAM(FIFO0) [SDRAM] */
#define MP200_BANK3_BASE	0x30000000
#define MP200_SDRAM_OFFSET	(0x00000000)
#define MP200_SDRAM_SIZE	SZ_64M

#define MP200_SDRAM_BASE	(MP200_BANK3_BASE+MP200_SDRAM_OFFSET)

/* BANK 4 -- APB0 [Peripherals] */
#define MP200_BANK4_BASE	0x40000000

#define MP200_ROTATOR_OFFSET	0x00080000
#define MP200_ROTATOR_SIZE	SZ_64K
#define MP200_DMAC_OFFSET	0x00090000
#define MP200_DMAC_SIZE		SZ_64K
#define MP200_IMAGEPROC_OFFSET	0x000a0000
#define MP200_IMAGEPROC_SIZE	SZ_64K
#define MP200_CAMERA_OFFSET	0x000b0000
#define MP200_CAMERA_SIZE	SZ_64K
#define MP200_PCM1_OFFSET	0x000d0000
#define MP200_PCM1_SIZE		SZ_64K
#define MP200_PWM_OFFSET	0x00100000
#define MP200_PWM_SIZE		SZ_64K
#define MP200_SP2_OFFSET	0x00130000
#define MP200_SP2_SIZE		SZ_64K
#define MP200_DTV_OFFSET	0x00150000
#define MP200_DTV_SIZE		SZ_64K
#define MP200_DBG_OFFSET	0x00190000
#define MP200_DBG_SIZE		SZ_64K
#define MP200_NTSC_OFFSET	0x00210000
#define MP200_NTSC_SIZE		SZ_64K
#define MP200_NAND_OFFSET	0x00220000
#define MP200_NAND_SIZE		SZ_64K
#define MP200_IPUDMA_OFFSET	0x00250000
#define MP200_IPUDMA_SIZE	SZ_64K
#define MP200_IMC_OFFSET	0x00260000
#define MP200_IMC_SIZE		SZ_64K
#define MP200_LCD_OFFSET	0x00270000
#define MP200_LCD_SIZE		SZ_64K


/* BANK 5 -- ASYNC1 [Peripherals] */
#define MP200_BANK5_BASE	0x50000000

#define MP200_UART0_OFFSET	0x00000000
#define MP200_UART0_SIZE	SZ_64K
#define MP200_UART1_OFFSET	0x00010000
#define MP200_UART1_SIZE	SZ_64K
#define MP200_UART2_OFFSET	0x00020000
#define MP200_UART2_SIZE	SZ_64K
#define MP200_IIC2_OFFSET	0x00030000
#define MP200_IIC2_SIZE		SZ_64K
#define MP200_IIC_OFFSET	0x00040000
#define MP200_IIC_SIZE		SZ_64K
#define MP200_SDIA_OFFSET	0x00050000
#define MP200_SDIA_SIZE		SZ_64K
#define MP200_SDIB_OFFSET	0x00060000
#define MP200_SDIB_SIZE		SZ_64K
#define MP200_SDIC_OFFSET	0x00090000
#define MP200_SDIC_SIZE		SZ_64K


/* BANK 6 -- AHB Slave */
#define MP200_BANK6_BASE	0x60000000

#define MP200_USB_OFFSET	0x00000000
#define MP200_USB_SIZE		SZ_64K
#define MP200_AVC_OFFSET	0x00020000
#define MP200_AVC_SIZE		SZ_64K
#define MP200_MSP_OFFSET	0x00030000
#define MP200_MSP_SIZE		SZ_64K
#define MP200_MMM_OFFSET	0x00040000
#define MP200_MMM_SIZE		SZ_64K


/* BANK 7 -- Reserved */
#define MP200_BANK7_BASE	0x70000000

/* BANK 8 -- Local */
#define MP200_BANK8_BASE	0x80000000

#define MP200_L220_OFFSET	0x00010000
#define MP200_L220_SIZE		SZ_64K

/* BANK 9 -- Reserved */
#define MP200_BANK9_BASE	0x90000000

/* BANK 10 -- SRAM */
#define MP200_BANK10_BASE	0xa0000000

#define MP200_SSRAM_OFFSET	0x00000000
#define MP200_SSRAM_SIZE	SZ_128K
#define MP200_SSRAM_BASE	(MP200_BANK10_BASE+MP200_SSRAM_OFFSET)

/* BANK 11 -- Reserved */
#define MP200_BANK11_BASE	0xb0000000

/* BANK 12 -- APB1 */
#define MP200_BANK12_BASE	0xc0000000

#define MP200_TIMER_OFFSET	0x00000000
#define MP200_TIMER_SIZE	SZ_64K
#define MP200_TIMER0_OFFSET	0x00000000
#define MP200_TIMER1_OFFSET	0x00000100
#define MP200_TIMER2_OFFSET	0x00000200
#define MP200_TIMER3_OFFSET	0x00000300
#define MP200_WDT0_OFFSET	0x00001000
#define MP200_WDT1_OFFSET	0x00001100
#define MP200_WDT2_OFFSET	0x00001200
#define MP200_WDT3_OFFSET	0x00001300
#define MP200_TG0_OFFSET	0x00002000
#define MP200_TG1_OFFSET	0x00002100
#define MP200_TG2_OFFSET	0x00002200
#define MP200_TG3_OFFSET	0x00002300
#define MP200_TG4_OFFSET	0x00002400
#define MP200_TG5_OFFSET	0x00002500
#define MP200_PCM0_OFFSET	0x00010000
#define MP200_PCM0_SIZE		SZ_64K
#define MP200_INTC_OFFSET	0x00020000
#define MP200_INTC_SIZE		SZ_64K
#define MP200_GPIO_OFFSET	0x00050000
#define MP200_GPIO_SIZE		SZ_64K
#define MP200_PDMA_OFFSET	0x00080000
#define MP200_PDMA_SIZE		SZ_64K
#define MP200_MEMC_OFFSET	0x000a0000
#define MP200_MEMC_SIZE		SZ_64K
#define MP200_DCV_OFFSET	0x000d0000
#define MP200_DCV_SIZE		SZ_64K
#define MP200_PMU_OFFSET	0x00100000
#define MP200_PMU_SIZE		SZ_64K
#define MP200_SMU_OFFSET	0x00110000
#define MP200_SMU_SIZE		SZ_64K
#define MP200_SP0_OFFSET	0x00120000
#define MP200_SP0_SIZE		SZ_64K
#define MP200_SP1_OFFSET	0x00130000
#define MP200_SP1_SIZE		SZ_64K
#define MP200_CHG_OFFSET	0x00140000
#define MP200_CHG_SIZE		SZ_64K
#define MP200_MWI_OFFSET	0x00160000
#define MP200_MWI_SIZE		SZ_64K


#define MP200_SMU_S2_OFFSET	0x0c000000
#define MP200_SMU_S2_SIZE	SZ_64K
#define MP200_INTC_S2_OFFSET	0x0c010000
#define MP200_INTC_S2_SIZE	SZ_64K

/* BANK 13 -- Reserved */
#define MP200_BANK13_BASE	0xd0000000

/* BANK 14 -- Reserved */
#define MP200_BANK14_BASE	0xe0000000

/* BANK 15 -- PE0 ROM */
#define MP200_BANK15_BASE	0xf0000000

#define MP200_BOOTROM_OFFSET	0x00000000
#define MP200_BOOTROM_SIZE	SZ_128K
#define MP200_BOOTROM_BASE	(MP200_BANK15_BASE+MP200_BOOTROM_OFFSET)

/*
 * Peripherals
 */
#define MP200_ROTATOR_BASE	(MP200_BANK4_BASE+MP200_ROTATOR_OFFSET)
#define MP200_DMAC_BASE		(MP200_BANK4_BASE+MP200_DMAC_OFFSET)
#define MP200_IMAGEPROC_BASE	(MP200_BANK4_BASE+MP200_IMAGEPROC_OFFSET)
#define MP200_CAMERA_BASE	(MP200_BANK4_BASE+MP200_CAMERA_OFFSET)
#define MP200_PCM1_BASE		(MP200_BANK4_BASE+MP200_PCM1_OFFSET)
#define MP200_PWM_BASE		(MP200_BANK4_BASE+MP200_PWM_OFFSET)
#define MP200_SP2_BASE		(MP200_BANK4_BASE+MP200_SP2_OFFSET)
#define MP200_DTV_BASE		(MP200_BANK4_BASE+MP200_DTV_OFFSET)
#define MP200_DBG_BASE		(MP200_BANK4_BASE+MP200_DBG_OFFSET)
#define MP200_NTSC_BASE		(MP200_BANK4_BASE+MP200_NTSC_OFFSET)
#define MP200_NAND_BASE		(MP200_BANK4_BASE+MP200_NAND_OFFSET)
#define MP200_IPUDMA_BASE	(MP200_BANK4_BASE+MP200_IPUDMA_OFFSET)
#define MP200_IMC_BASE		(MP200_BANK4_BASE+MP200_IMC_OFFSET)
#define MP200_LCD_BASE		(MP200_BANK4_BASE+MP200_LCD_OFFSET)

#define MP200_UART0_BASE	(MP200_BANK5_BASE+MP200_UART0_OFFSET)
#define MP200_UART1_BASE	(MP200_BANK5_BASE+MP200_UART1_OFFSET)
#define MP200_UART2_BASE	(MP200_BANK5_BASE+MP200_UART2_OFFSET)
#define MP200_IIC2_BASE		(MP200_BANK5_BASE+MP200_IIC2_OFFSET)
#define MP200_IIC_BASE		(MP200_BANK5_BASE+MP200_IIC_OFFSET)
#define MP200_SDIA_BASE		(MP200_BANK5_BASE+MP200_SDIA_OFFSET)
#define MP200_SDIB_BASE		(MP200_BANK5_BASE+MP200_SDIB_OFFSET)
#define MP200_SDIC_BASE		(MP200_BANK5_BASE+MP200_SDIC_OFFSET)

#define MP200_USB_BASE		(MP200_BANK6_BASE+MP200_USB_OFFSET)
#define MP200_AVC_BASE		(MP200_BANK6_BASE+MP200_AVC_OFFSET)
#define MP200_MSP_BASE		(MP200_BANK6_BASE+MP200_MSP_OFFSET)
#define MP200_MMM_BASE		(MP200_BANK6_BASE+MP200_MMM_OFFSET)

#define MP200_L220_BASE		(MP200_BANK8_BASE+MP200_L220_OFFSET)

#define MP200_TIMER_BASE	(MP200_BANK12_BASE+MP200_TIMER_OFFSET)
#define MP200_TIMER0_BASE	(MP200_BANK12_BASE+MP200_TIMER0_OFFSET)
#define MP200_TIMER1_BASE	(MP200_BANK12_BASE+MP200_TIMER1_OFFSET)
#define MP200_TIMER2_BASE	(MP200_BANK12_BASE+MP200_TIMER2_OFFSET)
#define MP200_TIMER3_BASE	(MP200_BANK12_BASE+MP200_TIMER3_OFFSET)
#define MP200_WDT0_BASE		(MP200_BANK12_BASE+MP200_WDT0_OFFSET)
#define MP200_WDT1_BASE		(MP200_BANK12_BASE+MP200_WDT1_OFFSET)
#define MP200_WDT2_BASE		(MP200_BANK12_BASE+MP200_WDT2_OFFSET)
#define MP200_WDT3_BASE		(MP200_BANK12_BASE+MP200_WDT3_OFFSET)
#define MP200_TG0_BASE		(MP200_BANK12_BASE+MP200_TG0_OFFSET)
#define MP200_TG1_BASE		(MP200_BANK12_BASE+MP200_TG1_OFFSET)
#define MP200_TG2_BASE		(MP200_BANK12_BASE+MP200_TG2_OFFSET)
#define MP200_TG3_BASE		(MP200_BANK12_BASE+MP200_TG3_OFFSET)
#define MP200_TG4_BASE		(MP200_BANK12_BASE+MP200_TG4_OFFSET)
#define MP200_TG5_BASE		(MP200_BANK12_BASE+MP200_TG5_OFFSET)
#define MP200_PCM0_BASE		(MP200_BANK12_BASE+MP200_PCM0_OFFSET)
#define MP200_INTC_BASE		(MP200_BANK12_BASE+MP200_INTC_OFFSET)
#define MP200_GPIO_BASE		(MP200_BANK12_BASE+MP200_GPIO_OFFSET)
#define MP200_PDMA_BASE		(MP200_BANK12_BASE+MP200_PDMA_OFFSET)
#define MP200_MEMC_BASE		(MP200_BANK12_BASE+MP200_MEMC_OFFSET)
#define MP200_DCV_BASE		(MP200_BANK12_BASE+MP200_DCV_OFFSET)
#define MP200_PMU_BASE		(MP200_BANK12_BASE+MP200_PMU_OFFSET)
#define MP200_SMU_BASE		(MP200_BANK12_BASE+MP200_SMU_OFFSET)
#define MP200_SP0_BASE		(MP200_BANK12_BASE+MP200_SP0_OFFSET)
#define MP200_SP1_BASE		(MP200_BANK12_BASE+MP200_SP1_OFFSET)
#define MP200_CHG_BASE		(MP200_BANK12_BASE+MP200_CHG_OFFSET)
#define MP200_MWI_BASE		(MP200_BANK12_BASE+MP200_MWI_OFFSET)

#define MP200_SMU_S2_BASE	(MP200_BANK12_BASE+MP200_SMU_S2_OFFSET)
#define MP200_INTC_S2_BASE	(MP200_BANK12_BASE+MP200_INTC_S2_OFFSET)

/*
 *  MP200 Interrupt Controller
 */
/* INTC internal offset for ACPU, CCPU, DSP. */
#define MP200_INTC_ACPU_OFFSET		0x00000000
#define MP200_INTC_ADSP_OFFSET		0x0000c000

#define MP200_INTC_ACPU_BASE	(MP200_INTC_BASE+MP200_INTC_ACPU_OFFSET)
#define MP200_INTC_ADSP_BASE	(MP200_INTC_BASE+MP200_INTC_ADSP_OFFSET)

/*
 * operational register offset
 */
/* interrupt enable */
#define	MP200_INTC_ITy_IEN0_OFFSET	0x00000000
#define	MP200_INTC_ITy_IEN1_OFFSET	0x00000004
#define	MP200_INTC_ITy_IEN2_OFFSET	0x00000100
/* interrupt enable monitor */
#define	MP200_INTC_ITy_IMN0_OFFSET	0x00000000
#define	MP200_INTC_ITy_IMN1_OFFSET	0x00000004
#define	MP200_INTC_ITy_IMN2_OFFSET	0x00000100
/* interrupt disable */
#define	MP200_INTC_ITy_IDS0_OFFSET	0x00000008
#define	MP200_INTC_ITy_IDS1_OFFSET	0x0000000c
#define	MP200_INTC_ITy_IDS2_OFFSET	0x00000104
/* interrupt raw status */
#define	MP200_INTC_ITy_RAW0_OFFSET	0x00000010
#define	MP200_INTC_ITy_RAW1_OFFSET	0x00000014
#define	MP200_INTC_ITy_RAW2_OFFSET	0x00000108
/* interrupt maskable status */
#define	MP200_INTC_ITy_MST0_OFFSET	0x00000018
#define	MP200_INTC_ITy_MST1_OFFSET	0x0000001c
#define	MP200_INTC_ITy_MST2_OFFSET	0x0000010c
/* interrupt cause clear */
#define	MP200_INTC_ITy_IIR_OFFSET	0x00000024

/* inter processor communication - set */
#define MP200_INTC_ITy_IPI0_SET_OFFSET  0x00000030
#define	MP200_INTC_ITy_IPI3_SET_OFFSET	0x0000003c
/* inter processor communication - monitor */
#define MP200_INTC_ITy_IPI0_MON_OFFSET  0x00000030
#define	MP200_INTC_ITy_IPI3_MON_OFFSET	0x0000003c
/* inter processor communication - clear */
#define MP200_INTC_IT0_IPIz_CLR_OFFSET  0x00000050
#define	MP200_INTC_IT3_IPIz_CLR_OFFSET	0x0000005c

/* FIQ interrupt enable */
#define	MP200_INTC_ITy_FIE_OFFSET	0x00000080
/* FIQ interrupt monitor */
#define	MP200_INTC_ITy_FIM_OFFSET	0x00000080
/* FIQ interrupt disable */
#define	MP200_INTC_ITy_FID_OFFSET	0x00000084
/* interrupt vector base */
#define	MP200_INTC_ID_VBS_OFFSET	0x00000090
/* interrupt output clear */
#define	MP200_INTC_ID_CLR_OFFSET	0x00000094

/* eg, unsigned long va = IO_ADDRESS (MP200_INTC_BASE) + MP200_INTC_IT0_xxx;*/
/*
 * register map for ACPU
 */
#define MP200_INTC_IT0_IEN0     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_IT0_IEN1     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_IT0_IEN2     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IEN2_OFFSET)
#define MP200_INTC_IT0_IMN0     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_IT0_IMN1     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_IT0_IMN2     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IMN2_OFFSET)
#define MP200_INTC_IT0_IDS0     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_IT0_IDS1     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_IT0_IDS2     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IDS2_OFFSET)
#define MP200_INTC_IT0_RAW0     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_IT0_RAW1     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_IT0_RAW2     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_RAW2_OFFSET)
#define MP200_INTC_IT0_MST0     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_IT0_MST1     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_IT0_MST2     (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_MST2_OFFSET)
#define MP200_INTC_IT0_IIR      (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_IT0_IPID_SET (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IPI3_SET_OFFSET)
#define MP200_INTC_IT0_IPID_MON (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_IPI3_MON_OFFSET)
#define MP200_INTC_IT0_IPID_CLR (MP200_INTC_ADSP_OFFSET+MP200_INTC_IT0_IPIz_CLR_OFFSET)
#define MP200_INTC_IT0_FIE      (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_FIE_OFFSET)
#define MP200_INTC_IT0_FIM      (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_FIM_OFFSET)
#define MP200_INTC_IT0_FID      (MP200_INTC_ACPU_OFFSET+MP200_INTC_ITy_FID_OFFSET)


/*
 * register map for ADSP
 */
#define MP200_INTC_ID_IEN0      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IEN0_OFFSET)
#define MP200_INTC_ID_IEN1      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IEN1_OFFSET)
#define MP200_INTC_ID_IEN2      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IEN2_OFFSET)
#define MP200_INTC_ID_IMN0      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IMN0_OFFSET)
#define MP200_INTC_ID_IMN1      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IMN1_OFFSET)
#define MP200_INTC_ID_IMN2      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IMN2_OFFSET)
#define MP200_INTC_ID_IDS0      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IDS0_OFFSET)
#define MP200_INTC_ID_IDS1      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IDS1_OFFSET)
#define MP200_INTC_ID_IDS2      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IDS2_OFFSET)
#define MP200_INTC_ID_RAW0      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_RAW0_OFFSET)
#define MP200_INTC_ID_RAW1      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_RAW1_OFFSET)
#define MP200_INTC_ID_RAW2      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_RAW2_OFFSET)
#define MP200_INTC_ID_MST0      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_MST0_OFFSET)
#define MP200_INTC_ID_MST1      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_MST1_OFFSET)
#define MP200_INTC_ID_MST2      (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_MST2_OFFSET)
#define MP200_INTC_ID_IIR       (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IIR_OFFSET)
#define MP200_INTC_ID_IPI0_SET  (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IPI0_SET_OFFSET)
#define MP200_INTC_ID_IPI0_MON  (MP200_INTC_ADSP_OFFSET+MP200_INTC_ITy_IPI0_MON_OFFSET)
#define MP200_INTC_ID_IPI0_CLR  (MP200_INTC_ACPU_OFFSET+MP200_INTC_IT3_IPIz_CLR_OFFSET)
#define MP200_INTC_ID_VBS       (MP200_INTC_ADSP_OFFSET+MP200_INTC_ID_VBS_OFFSET)
#define MP200_INTC_ID_CLR       (MP200_INTC_ADSP_OFFSET+MP200_INTC_ID_CLR_OFFSET)


/*
 *  These are useconds NOT ticks.
 *
 */
#define mSEC_1			1000
#define mSEC_5			(mSEC_1 * 5)
#define mSEC_10			(mSEC_1 * 10)
#define mSEC_25			(mSEC_1 * 25)
#define SEC_1			(mSEC_1 * 1000)

/*
 * serial base baud
 */
#ifdef CONFIG_PLL3_238MHZ
/* PLL3 238MHZ */
#define MP200_BASE_BAUD (237567000 / 4)
#else
/* PLL3 230MHZ */
#define MP200_BASE_BAUD (229376000 / 4)
#endif

/*
 * Include platform-specific definition
 */
#if defined(CONFIG_MACH_MP200)
#include <asm/arch/mp200_board.h>
#elif defined(CONFIG_MACH_GROVER)
#include <asm/arch/grover/board.h>
#elif defined(CONFIG_MACH_PGPF)
#include <asm/arch/pgpf/board.h>
#endif

/*
 * MAP DESC
 */
#define MP200_MAP_DESC(base, size)	\
	{ .virtual = IO_ADDRESS(base), .pfn = __phys_to_pfn(base), .length = size, .type = MT_DEVICE }

#endif				/* __ASM_ARM_ARCH_MP200_HARDWARE_H */
