/* 2009-08-20: File added by Sony Corporation */
/*
 * include/asm-arm/arch-omap24xx/venc.h
 *
 * Copyright (C) 2004-2005 Texas Instruments, Inc.
 * TV Standard configuration for Video Encoder in OMAP24XX
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 *
 */


/* TV Encoder initialization for PAL and NTSC */

/* Typical encoder values for different TV tests */
#define VENC_HFLTR_CTRL_EN			0x00000000
#define VENC_X_COLOR_VAL			0x00000000

#define VENC_LINE21_VAL				0x00000000
#define VENC_LN_SEL_VAL				0x00000015
#define VENC_HTRIGGER_VTRIGGER_VAL		0x00000000

#define VENC_TVDETGP_INT_START_STOP_X_VAL	0x00140001
#define VENC_TVDETGP_INT_START_STOP_Y_VAL	0x00010001
#define VENC_GEN_CTRL_VAL			0x00FF0000
#define VENC_GEN_CTRL_PAL_VAL			0x00F90000

/* DAC enable and in normal operation */
#ifdef CONFIG_ARCH_OMAP2420
#define VENC_DAC_ENABLE				0x00000002
#endif

#ifdef CONFIG_ARCH_OMAP2430
#define VENC_DAC_ENABLE				0x0000000A
#endif

#ifdef CONFIG_ARCH_OMAP3430
#define VENC_DAC_ENABLE				0x0000000D
#endif

/*Values that are same for NTSC, PAL-M AND PAL-60 */
#define F_CONTROL_GEN				0x00000000
#define SYNC_CONTROL_GEN			0x00001040
#define VENC_LLEN_GEN				0x00000359
#define VENC_FLENS_GEN                  	0x0000020C
#define VENC_C_PHASE_GEN                	0x00000000
#define VENC_CC_CARR_WSS_CARR_GEN       	0x000025ed
#define VENC_L21_WC_CTL_GEN             	0x00170000
#define VENC_SAVID_EAVID_GEN            	0x069300F4
#define VENC_FLEN_FAL_GEN             		0x0016020C
#define VENC_HS_EXT_START_STOP_X_GEN    	0x000F0359
#define VENC_VS_INT_START_X_GEN         	0x01A00000
#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN   0x020D01AC
#define VENC_VS_EXT_STOP_Y_GEN			0x00000006
#define VENC_FID_INT_START_X_FID_INT_START_Y_GEN  0x0001008A
#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN 0x01AC0106
#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN 0x01060006


/* Values that are same for PAL-BDGHI, PAL-N, PAL-NC */

#define VENC_LLEN_PAL				0x0000035F
#define VENC_FLENS_PAL				0x00000270

#define VENC_LLEN_PAL_M				0x00000359
#define VENC_FLENS_PAL_M			0x0000020C

#define VENC_C_PHASE_PAL		       	0x000000F0 /* BDGHI & N */
#define VENC_C_PHASE_PAL_NC		       	0x00000000

#define VENC_CC_CARR_WSS_CARR_PAL		0x000025ED

#define VENC_L21_WC_CTL_PAL			0x00000000

#define VENC_SAVID_EAVID_PAL			0x06A70108
#define VENC_FLEN_FAL_PAL			0x00170270
#define VENC_HS_EXT_START_STOP_X_PAL		0x000F035F
#define VENC_VS_INT_START_X_PAL			0x01A70000
#define VENC_VS_EXT_STOP_Y_PAL			0x00000005

#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL	0x027101AF

#define VENC_GAIN_U_PAL_BDGHI			0x00000130


#define VENC_GAIN_U_PAL_N			0x000000FD
#define VENC_GAIN_U_PAL_NC			0x00000130
#define VENC_GAIN_U_PAL_M			0x00000140
#define VENC_GAIN_U_PAL_60			0x00000140

#define VENC_GAIN_V_PAL_BDGHI			0x000001B0

#define VENC_GAIN_V_PAL_N			0x00000165
#define VENC_GAIN_V_PAL_NC			0x000001B0
#define VENC_GAIN_V_PAL_M			0x00000190
#define VENC_GAIN_V_PAL_60			0x00000190

#define VENC_GAIN_Y_PAL_BDGHI			0x000001B0
#define VENC_GAIN_Y_PAL_N			0x00000177
#define VENC_GAIN_Y_PAL_NC			0x000001B0
#define VENC_GAIN_Y_PAL_M			0x000001C0
#define VENC_GAIN_Y_PAL_60			0x000001C0

#define VENC_BLACK_LEVEL_PAL_BDGHI		0x00000067

#define VENC_BLANK_LEVEL_PAL_BDGHI		0x00000067
#define VENC_BLACK_LEVEL_PAL_NC			0x00000063
#define VENC_BLANK_LEVEL_PAL_NC			0x00000063

#define VENC_BLACK_LEVEL_PAL_N			0x00000060
#define VENC_BLANK_LEVEL_PAL_N			0x00000053

#define VENC_BLACK_LEVEL_PAL_M			0x00000069
#define VENC_BLANK_LEVEL_PAL_M			0x0000005C

#define VENC_BLACK_LEVEL_PAL_60			0x00000069
#define VENC_BLANK_LEVEL_PAL_60			0x0000005C

#define VENC_M_CONTROL_PAL			0x00000002
#define VENC_M_CONTROL_PAL_M			0x00000003
#define VENC_M_CONTROL_PAL_60			0x00000003

#define VENC_BSTAMP_WSS_DATA_PAL_BDGHI		0x00000043

#define VENC_BSTAMP_WSS_DATA_PAL_N		0x00000038
#define VENC_BSTAMP_WSS_DATA_PAL_M		0x0000003F
#define VENC_BSTAMP_WSS_DATA_PAL_NC		0x00000041
#define VENC_BSTAMP_WSS_DATA_PAL_60		0x0000003F

#define VENC_S_CARR_PAL_M			0x21E6EFE3
#define VENC_S_CARR_PAL_NC			0x21E6EFE3
#define VENC_S_CARR_PAL_BDGHI			0x2A098ACB
#define VENC_S_CARR_PAL_60			0x2A098ACB



#define VENC_LAL_PHASE_RESET_PAL		0x00040136 /* BDGHI & N */
#define VENC_LAL_PHASE_RESET_PAL_NC		0x00040135
#define VENC_LAL_PHASE_RESET_PAL_2		0x00040107 /* PAL-M & PAL-60 */

#define VENC_HS_INT_START_STOP_X_PAL		0x00920358 /* BDGHI & N */
#define VENC_HS_INT_START_STOP_X_NC		0x00880358
#define VENC_HS_INT_START_STOP_X_PAL_2		0x007e034e /* PAL-M & PAL-60 */

#define VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL	0x000601A7
#define VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_2	0x020901a0 /* PAL-M & PAL-60*/
#define VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_NC 0x026F01A7

#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL	0x01AF0036
#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_2	0x01ac0022 /* PAL-M & PAL-60 */
#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_NC 0x01AF002E

#define VENC_AVID_START_STOP_X_PAL		0x03530082 /* BDGHI & N */
#define VENC_AVID_START_STOP_X_PAL_NC		0x03530083
#define VENC_AVID_START_STOP_X_PAL_2		0x03530082 /* PAL-M & PAL-60 */

#define VENC_AVID_START_STOP_Y_PAL		0x0270002E
#define VENC_AVID_START_STOP_Y_PAL_2		0x0270002E /* PAL-M & PAL-60 */
#define VENC_AVID_START_STOP_Y_PAL_NC		0x026E002E

#define VENC_FID_INT_START_X_FID_INT_START_Y_PAL 0x0005008A

#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL 0x002E0138


#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_PAL 0x01380005

/* NTSC */
#define VENC_GAIN_U_NTSC_M			0x00000102
#define VENC_GAIN_U_NTSC_J			0x00000100
#define VENC_GAIN_U_NTSC_443			0x00000140

#define VENC_GAIN_V_NTSC_M			0x0000016C
#define VENC_GAIN_V_NTSC_J			0x0000016D
#define VENC_GAIN_V_NTSC_443			0x00000190

#define VENC_GAIN_Y_NTSC_M			0x0000012F
#define VENC_GAIN_Y_NTSC_J			0x00000196
#define VENC_GAIN_Y_NTSC_443			0x000001C0

#define VENC_BLACK_LEVEL_NTSC_443		0x00000069
#define VENC_BLANK_LEVEL_NTSC_443		0x0000005C

#define VENC_BLACK_LEVEL_NTSC_M			0x00000043
#define VENC_BLANK_LEVEL_NTSC_M			0x00000038

#define VENC_BLACK_LEVEL_NTSC_J			0x00000053
#define VENC_BLANK_LEVEL_NTSC_J			0x00000053

#define VENC_M_CONTROL_NTSC			0x00000001

#define VENC_BSTAMP_WSS_DATA_NTSC		0x00000038
#define VENC_BSTAMP_WSS_DATA_NTSC_443		0x0000003F

#define VENC_S_CARR_NTSC_443			0x2A098ACB
#define VENC_S_CARR_NTSC			0x21F07C1F

#define VENC_HTRIGGER_VTRIGGER_VAL		0x00000000

#define VENC_FLEN_FAL_NTSC			0x0001020C

#define VENC_LAL_PHASE_RESET_NTSC		0x00060107

#define VENC_HS_INT_START_STOP_X_NTSC		0x007E034E

#define VENC_HS_INT_START_STOP_X_443		0x007e034e

#define VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC	0x020901A0
#define VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC_443 0x020901a0

#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC	0x01AC0022
#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC_443 0x01ac0022

#define VENC_AVID_START_STOP_X_NTSC		0x032000A0
#define VENC_AVID_START_STOP_X_NTSC_443		0x03480079

#define VENC_AVID_START_STOP_Y_NTSC		0x02060026
#define VENC_AVID_START_STOP_Y_NTSC_443		0x02040024

#define VENC_TVDETGP_INT_START_STOP_X_GEN	0x00140001
#define VENC_TVDETGP_INT_START_STOP_Y_GEN	0x00010001


struct tv_standard_config{
	u32 venc_llen;
	u32 venc_flens;
	u32 venc_hfltr_ctrl;
	u32 venc_cc_carr_wss_carr;
	u32 venc_c_phase;
	u32 venc_gain_u;
	u32 venc_gain_v;
	u32 venc_gain_y;
	u32 venc_black_level;
	u32 venc_blank_level;
	u32 venc_x_color;
	u32 venc_m_control;
	u32 venc_bstamp_wss_data;
	u32 venc_s_carr;
	u32 venc_line21;
	u32 venc_ln_sel;
	u32 venc_l21_wc_ctl;
	u32 venc_htrigger_vtrigger;
	u32 venc_savid_eavid;
	u32 venc_flen_fal;
	u32 venc_lal_phase_reset;
	u32 venc_hs_int_start_stop_x;
	u32 venc_hs_ext_start_stop_x;
	u32 venc_vs_int_start_x;
	u32 venc_vs_int_stop_x_vs_int_start_y;
	u32 venc_vs_int_stop_y_vs_ext_start_x;
	u32 venc_vs_ext_stop_x_vs_ext_start_y;
	u32 venc_vs_ext_stop_y;
	u32 venc_avid_start_stop_x;
	u32 venc_avid_start_stop_y;
	u32 venc_fid_int_start_x_fid_int_start_y;
	u32 venc_fid_int_offset_y_fid_ext_start_x;
	u32 venc_fid_ext_start_y_fid_ext_offset_y;
	u32 venc_tvdetgp_int_start_stop_x;
	u32 venc_tvdetgp_int_start_stop_y;
	u32 venc_gen_ctrl;
	u32 venc_dac_tst;
};

#ifndef CONFIG_ARCH_OMAP3410
static struct tv_standard_config pal_bdghi_cfg = {
	/*VENC_LLEN_PAL,*/0x0000035F,
	/*VENC_FLENS_PAL,*/0x00000270,
	/*VENC_HFLTR_CTRL_EN,*/0x00000000,
	/*VENC_CC_CARR_WSS_CARR_PAL,*/0x2F7225ED,
	/*VENC_C_PHASE_PAL,*/0x00000000,
	VENC_GAIN_U_PAL_BDGHI,/*0x00000111,*/
	VENC_GAIN_V_PAL_BDGHI,/*0x00000181,*/
	VENC_GAIN_Y_PAL_BDGHI,/*0x00000140,*/
	/*VENC_BLACK_LEVEL_PAL_BDGHI,*/0x0000003B,
	/*VENC_BLANK_LEVEL_PAL_BDGHI,*/0x0000003B,
	/*VENC_X_COLOR_VAL,*/0x00000007,
	/*VENC_M_CONTROL_PAL,*/0x00000002,
	/*VENC_BSTAMP_WSS_DATA_PAL_BDGHI,*/0x0000003F,
	/*VENC_S_CARR_PAL_BDGHI,*/0x2A098ACB,
	/*VENC_LINE21_VAL,*/0x00000000,
	/*VENC_LN_SEL_VAL,*/0x01290015,
	/*VENC_L21_WC_CTL_PAL,*/0x0000F603,
	/*VENC_HTRIGGER_VTRIGGER_VAL,*/0x00000000,
	/*VENC_SAVID_EAVID_PAL,*/0x06A70108,
	/*VENC_FLEN_FAL_PAL,*/0x00180270,
	/*VENC_LAL_PHASE_RESET_PAL,*/0x00040135,
	/*VENC_HS_INT_START_STOP_X_PAL,*/0x00880358,
	/*VENC_HS_EXT_START_STOP_X_PAL,*/0x000F035F,
	/*VENC_VS_INT_START_X_PAL,*/0x01A70000,
	/*VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL,*/0x000001A7,
	/*VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL,*/0x01AF0000,
	/*VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL,*/0x000101AF,
	/*VENC_VS_EXT_STOP_Y_PAL,*/0x00000025,
	/*VENC_AVID_START_STOP_X_PAL,*/0x03530083,
	/*VENC_AVID_START_STOP_Y_PAL,*/0x026C002E,
	/*VENC_FID_INT_START_X_FID_INT_START_Y_PAL,*/0x0001008A,
	/*VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL,*/0x002E0138,
	/*VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_PAL,*/0x01380001,
	/*VENC_TVDETGP_INT_START_STOP_X_GEN,*/0x00140001,
	/*VENC_TVDETGP_INT_START_STOP_Y_GEN,*/0x00010001,
	/*VENC_GEN_CTRL_PAL_VAL,*/0x00FF0000,
	VENC_DAC_ENABLE
};

static struct tv_standard_config pal_n_cfg = {
	VENC_LLEN_PAL,
	VENC_FLENS_PAL,
	VENC_HFLTR_CTRL_EN,
	VENC_CC_CARR_WSS_CARR_PAL,
	VENC_C_PHASE_PAL,
	VENC_GAIN_U_PAL_N,
	VENC_GAIN_V_PAL_N,
	VENC_GAIN_Y_PAL_N,
	VENC_BLACK_LEVEL_PAL_N,
	VENC_BLANK_LEVEL_PAL_N,
	VENC_X_COLOR_VAL,
	VENC_M_CONTROL_PAL,
	VENC_BSTAMP_WSS_DATA_PAL_BDGHI,
	VENC_S_CARR_PAL_BDGHI,
	VENC_LINE21_VAL,
	VENC_LN_SEL_VAL,
	VENC_L21_WC_CTL_PAL,
	VENC_HTRIGGER_VTRIGGER_VAL,
	VENC_SAVID_EAVID_PAL,
	VENC_FLEN_FAL_PAL,
	VENC_LAL_PHASE_RESET_PAL,
	VENC_HS_INT_START_STOP_X_PAL,
	VENC_HS_EXT_START_STOP_X_PAL,
	VENC_VS_INT_START_X_PAL,
	VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL,
	VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL,
	VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL,
	VENC_VS_EXT_STOP_Y_PAL,
	VENC_AVID_START_STOP_X_PAL,
	VENC_AVID_START_STOP_Y_PAL,
	VENC_FID_INT_START_X_FID_INT_START_Y_PAL,
	VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL,
	VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_PAL,
	VENC_TVDETGP_INT_START_STOP_X_GEN,
	VENC_TVDETGP_INT_START_STOP_Y_GEN,
	VENC_GEN_CTRL_PAL_VAL,
	VENC_DAC_ENABLE
};

static struct tv_standard_config pal_nc_cfg = {
	VENC_LLEN_PAL,
	VENC_FLENS_PAL,
	VENC_HFLTR_CTRL_EN,
	VENC_CC_CARR_WSS_CARR_PAL,
	VENC_C_PHASE_PAL,
	VENC_GAIN_U_PAL_NC,
	VENC_GAIN_V_PAL_NC,
	VENC_GAIN_Y_PAL_NC,
	VENC_BLACK_LEVEL_PAL_NC,
	VENC_BLANK_LEVEL_PAL_NC,
	VENC_X_COLOR_VAL,
	VENC_M_CONTROL_PAL,
	VENC_BSTAMP_WSS_DATA_PAL_NC,
	VENC_S_CARR_PAL_NC,
	VENC_LINE21_VAL,
	VENC_LN_SEL_VAL,
	VENC_L21_WC_CTL_PAL,
	VENC_HTRIGGER_VTRIGGER_VAL,
	VENC_SAVID_EAVID_PAL,
	VENC_FLEN_FAL_PAL,
	VENC_LAL_PHASE_RESET_PAL_NC,
	VENC_HS_INT_START_STOP_X_NC,
	VENC_HS_EXT_START_STOP_X_PAL,
	VENC_VS_INT_START_X_PAL,
	VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_NC,
	VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_NC,
	VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL,
	VENC_VS_EXT_STOP_Y_PAL,
	VENC_AVID_START_STOP_X_PAL_NC,
	VENC_AVID_START_STOP_Y_PAL_NC,
	VENC_FID_INT_START_X_FID_INT_START_Y_PAL,
	VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL,
	VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_PAL,
	VENC_TVDETGP_INT_START_STOP_X_GEN,
	VENC_TVDETGP_INT_START_STOP_Y_GEN,
	VENC_GEN_CTRL_PAL_VAL,
	VENC_DAC_ENABLE
};

static struct tv_standard_config pal_m_cfg = {
	VENC_LLEN_PAL_M,
	VENC_FLENS_PAL_M,
	VENC_HFLTR_CTRL_EN,
	VENC_CC_CARR_WSS_CARR_GEN,
	VENC_C_PHASE_GEN,
	VENC_GAIN_U_PAL_M,
	VENC_GAIN_V_PAL_M,
	VENC_GAIN_Y_PAL_M,
	VENC_BLACK_LEVEL_PAL_M,
	VENC_BLANK_LEVEL_PAL_M,
	VENC_X_COLOR_VAL,
	VENC_M_CONTROL_PAL_M,
	VENC_BSTAMP_WSS_DATA_PAL_M,
	VENC_S_CARR_PAL_M,
	VENC_LINE21_VAL,
	VENC_LN_SEL_VAL,
	VENC_L21_WC_CTL_GEN,
	VENC_HTRIGGER_VTRIGGER_VAL,
	VENC_SAVID_EAVID_GEN,
	VENC_FLEN_FAL_GEN,
	VENC_LAL_PHASE_RESET_PAL_2,
	VENC_HS_INT_START_STOP_X_PAL_2,
	VENC_HS_EXT_START_STOP_X_GEN,
	VENC_VS_INT_START_X_GEN,
	VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_2,
	VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_2,
	VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
	VENC_VS_EXT_STOP_Y_GEN,
	VENC_AVID_START_STOP_X_PAL_2,
	VENC_AVID_START_STOP_Y_PAL_2,
	VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
	VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
	VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
	VENC_TVDETGP_INT_START_STOP_X_GEN,
	VENC_TVDETGP_INT_START_STOP_Y_GEN,
	VENC_GEN_CTRL_VAL,
	VENC_DAC_ENABLE
};

static struct tv_standard_config pal_60_cfg = {
	VENC_LLEN_GEN,
	VENC_FLENS_GEN,
	VENC_HFLTR_CTRL_EN,
	VENC_CC_CARR_WSS_CARR_GEN,
	VENC_C_PHASE_GEN,
	VENC_GAIN_U_PAL_60,
	VENC_GAIN_V_PAL_60,
	VENC_GAIN_Y_PAL_60,
	VENC_BLACK_LEVEL_PAL_60,
	VENC_BLANK_LEVEL_PAL_60,
	VENC_X_COLOR_VAL,
	VENC_M_CONTROL_PAL_60,
	VENC_BSTAMP_WSS_DATA_PAL_60,
	VENC_S_CARR_PAL_60,
	VENC_LINE21_VAL,
	VENC_LN_SEL_VAL,
	VENC_L21_WC_CTL_GEN,
	VENC_HTRIGGER_VTRIGGER_VAL,
	VENC_SAVID_EAVID_GEN,
	VENC_FLEN_FAL_GEN,
	VENC_LAL_PHASE_RESET_PAL_2,
	VENC_HS_INT_START_STOP_X_PAL_2,
	VENC_HS_EXT_START_STOP_X_GEN,
	VENC_VS_INT_START_X_GEN,
	VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_2,
	VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_2,
	VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
	VENC_VS_EXT_STOP_Y_GEN,
	VENC_AVID_START_STOP_X_PAL_2,
	VENC_AVID_START_STOP_Y_PAL_2,
	VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
	VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
	VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
	VENC_TVDETGP_INT_START_STOP_X_GEN,
	VENC_TVDETGP_INT_START_STOP_Y_GEN,
	VENC_GEN_CTRL_VAL,
	VENC_DAC_ENABLE
};

static struct tv_standard_config ntsc_m_cfg  = {
	/*VENC_LLEN_GEN,*/0x00000359,
	/*VENC_FLENS_GEN,*/0x0000020C,
	/*VENC_HFLTR_CTRL_EN,*/0x00000000,
	/*VENC_CC_CARR_WSS_CARR_GEN,*/0x043F2631,
	/*VENC_C_PHASE_GEN,*/0x00000000,
	/*VENC_GAIN_U_NTSC_M,*/0x00000102,
	/*VENC_GAIN_V_NTSC_M,*/0x0000016C,
	/*VENC_GAIN_Y_NTSC_M,*/0x0000012F,
	/*VENC_BLACK_LEVEL_NTSC_M,*/0x00000043,
	/*VENC_BLANK_LEVEL_NTSC_M,*/0x00000038,
	/*VENC_X_COLOR_VAL,*/0x00000007,
	/*VENC_M_CONTROL_NTSC,*/0x00000001,
	/*VENC_BSTAMP_WSS_DATA_NTSC,*/0x00000038,
	/*VENC_S_CARR_NTSC,*/0x21F07C1F,
	/*VENC_LINE21_VAL,*/0x00000000,
	/*VENC_LN_SEL_VAL,*/0x01310011,
	/*VENC_L21_WC_CTL_GEN,*/0x0000F003,
	/*VENC_HTRIGGER_VTRIGGER_VAL,*/0x00000000,
	/*VENC_SAVID_EAVID_GEN,*/0x069300F4,
	/*VENC_FLEN_FAL_GEN,*/0x0016020C,
	/*VENC_LAL_PHASE_RESET_NTSC,*/0x00060107,
	/*VENC_HS_INT_START_STOP_X_NTSC,*/0x008E0350,
	/*VENC_HS_EXT_START_STOP_X_GEN,*/0x000F0359,
	/*VENC_VS_INT_START_X_GEN,*/0x01A00000,
	/*VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC,*/0x020701A0,
	/*VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC,*/0x01AC0024,
	/*VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,*/0x020D01AC,
	/*VENC_VS_EXT_STOP_Y_GEN,*/0x00000006,
	/*VENC_AVID_START_STOP_X_NTSC,*/0x03480078,
	/*VENC_AVID_START_STOP_Y_NTSC,*/0x02060024,
	/*VENC_FID_INT_START_X_FID_INT_START_Y_GEN,*/0x0001008A,
	/*VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,*/0x01AC0106,
	/*VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,*/0x01060006,
	/*VENC_TVDETGP_INT_START_STOP_X_GEN,*/0x00140001,
	/*VENC_TVDETGP_INT_START_STOP_Y_GEN,*/0x00010001,
	/*VENC_GEN_CTRL_VAL,*/0x00F90000,
	VENC_DAC_ENABLE
};

static struct tv_standard_config ntsc_443_cfg = {
	VENC_LLEN_GEN,
	VENC_FLENS_GEN,
	VENC_HFLTR_CTRL_EN,
	VENC_CC_CARR_WSS_CARR_GEN,
	VENC_C_PHASE_GEN,
	VENC_GAIN_U_NTSC_443,
	VENC_GAIN_V_NTSC_443,
	VENC_GAIN_Y_NTSC_443,
	VENC_BLACK_LEVEL_NTSC_443,
	VENC_BLANK_LEVEL_NTSC_443,
	VENC_X_COLOR_VAL,
	VENC_M_CONTROL_NTSC,
	VENC_BSTAMP_WSS_DATA_NTSC_443,
	VENC_S_CARR_NTSC_443,
	VENC_LINE21_VAL,
	VENC_LN_SEL_VAL,
	VENC_L21_WC_CTL_GEN,
	VENC_HTRIGGER_VTRIGGER_VAL,
	VENC_SAVID_EAVID_GEN,
	VENC_FLEN_FAL_GEN,
	VENC_LAL_PHASE_RESET_NTSC,
	VENC_HS_INT_START_STOP_X_443,
	VENC_HS_EXT_START_STOP_X_GEN,
	VENC_VS_INT_START_X_GEN,
	VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC_443,
	VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC_443,
	VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
	VENC_VS_EXT_STOP_Y_GEN,
	VENC_AVID_START_STOP_X_NTSC_443,
	VENC_AVID_START_STOP_Y_NTSC_443,
	VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
	VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
	VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
	VENC_TVDETGP_INT_START_STOP_X_GEN,
	VENC_TVDETGP_INT_START_STOP_Y_GEN,
	VENC_GEN_CTRL_VAL,
	VENC_DAC_ENABLE
};

static struct tv_standard_config ntsc_j_cfg = {
	VENC_LLEN_GEN,
	VENC_FLENS_GEN,
	VENC_HFLTR_CTRL_EN,
	VENC_CC_CARR_WSS_CARR_GEN,
	VENC_C_PHASE_GEN,
	VENC_GAIN_U_NTSC_J,
	VENC_GAIN_V_NTSC_J,
	VENC_GAIN_Y_NTSC_J,
	VENC_BLACK_LEVEL_NTSC_J,
	VENC_BLANK_LEVEL_NTSC_J,
	VENC_X_COLOR_VAL,
	VENC_M_CONTROL_NTSC,
	VENC_BSTAMP_WSS_DATA_NTSC,
	VENC_S_CARR_NTSC,
	VENC_LINE21_VAL,
	VENC_LN_SEL_VAL,
	VENC_L21_WC_CTL_GEN,
	VENC_HTRIGGER_VTRIGGER_VAL,
	VENC_SAVID_EAVID_GEN,
	VENC_FLEN_FAL_GEN,
	VENC_LAL_PHASE_RESET_NTSC,
	VENC_HS_INT_START_STOP_X_NTSC,
	VENC_HS_EXT_START_STOP_X_GEN,
	VENC_VS_INT_START_X_GEN,
	VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC,
	VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC,
	VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
	VENC_VS_EXT_STOP_Y_GEN,
	VENC_AVID_START_STOP_X_NTSC,
	VENC_AVID_START_STOP_Y_NTSC,
	VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
	VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
	VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
	VENC_TVDETGP_INT_START_STOP_X_GEN,
	VENC_TVDETGP_INT_START_STOP_Y_GEN,
	VENC_GEN_CTRL_VAL,
	VENC_DAC_ENABLE
};
#endif
