/* 2009-08-20: File added and changed by Sony Corporation */
/*
 *  linux/arch/arm/mach-mp200/clock.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_MP200_CLOCK_H
#define __ARCH_ARM_MACH_MP200_CLOCK_H

#include <asm/arch/smu.h>

struct module;

struct clk {
	struct list_head  node;
	struct module    *owner;
	const char       *name;
	__u32             clk_bit;
	__u32             clkctrl_bit;
	__u32             div_reg;
};

/* DMA */
static struct clk clk_dma_tclk = {
	.name        = "dma_tclk",
	.clk_bit     = MP200_CLOCKGATE_DMA_TCLK,
	.div_reg     = SMU_DIVDMATCLK,
};
static struct clk clk_dma_pch3 = {
	.name        = "dma_pch3",
	.clk_bit     = MP200_CLOCKGATE_DMA_PCH3_CLK,
	.clkctrl_bit = MP200_CLKCTRL_DMAPCH3,
};
static struct clk clk_dma_pch2 = {
	.name        = "dma_pch2",
	.clk_bit     = MP200_CLOCKGATE_DMA_PCH2_CLK,
	.clkctrl_bit = MP200_CLKCTRL_DMAPCH2,
};
static struct clk clk_dma_pch0 = {
	.name        = "dma_pch0",
	.clk_bit     = MP200_CLOCKGATE_DMA_PCH0_CLK,
	.clkctrl_bit = MP200_CLKCTRL_DMAPCH0,
};
static struct clk clk_dma_pclk = {
	.name        = "dma_pclk",
	.clk_bit     = MP200_CLOCKGATE_DMA_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_DMAPCLK,
};

/* IMC */
static struct clk clk_imc_pclk = {
	.name        = "imc_pclk",
	.clk_bit     = MP200_CLOCKGATE_IMC_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_IMCPCLK,
};
static struct clk clk_imc = {
	.name        = "imc",
	.clk_bit     = MP200_CLOCKGATE_IMC_CLK,
	.clkctrl_bit = MP200_CLKCTRL_IMC,
};

/* IPU */
static struct clk clk_ipu_ahb = {
	.name        = "ipu_ahb",
	.clk_bit     = MP200_CLOCKGATE_IPUAHB_CLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUAHB,
};
static struct clk clk_ipu_dma_pclk = {
	.name        = "ipu_dma_pclk",
	.clk_bit     = MP200_CLOCKGATE_IPUDMA_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUDMA,
};
static struct clk clk_ipu_dma = {
	.name        = "ipu_dma",
	.clk_bit     = MP200_CLOCKGATE_IPUDMA_CLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUDMACLK,
};
static struct clk clk_rot_pclk = {
	.name        = "rot_pclk",
	.clk_bit     = MP200_CLOCKGATE_ROT_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUROTPCLK,
};
static struct clk clk_rot = {
	.name        = "rot",
	.clk_bit     = MP200_CLOCKGATE_ROT_CLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUROT,
};
static struct clk clk_img_pclk = {
	.name        = "ipu_img_pclk",
	.clk_bit     = MP200_CLOCKGATE_IMG_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUIMGPCLK,
};
static struct clk clk_img_2 = {
	.name        = "img_2",
	.clk_bit     = MP200_CLOCKGATE_IMG_2_CLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUIMG2,
};
static struct clk clk_img_1 = {
	.name        = "img_1",
	.clk_bit     = MP200_CLOCKGATE_IMG_1_CLK,
	.clkctrl_bit = MP200_CLKCTRL_IPUIMG1,
};

static struct clk clk_pdma_pclk = {
	.name        = "pdma_pclk",
	.clk_bit     = MP200_CLOCKGATE_PDMA_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_PDMAPCLK,
};
static struct clk clk_pdma_hclk = {
	.name        = "pdma_hclk",
	.clk_bit     = MP200_CLOCKGATE_PDMA_HCLK,
	.clkctrl_bit = MP200_CLKCTRL_PDMAHCK,
};
static struct clk clk_pdma_aclk = {
	.name        = "pdma_aclk",
	.clk_bit     = MP200_CLOCKGATE_PDMA_ACLK,
	.clkctrl_bit = MP200_CLKCTRL_PDMAACK,
};


/* DSP */
static struct clk clk_dsp_aclk = {
	.name        = "dsp_aclk",
	.clk_bit     = MP200_CLOCKGATE_DSP_ACLK,
};
static struct clk clk_dsp = {
	.name        = "dsp",
	.clk_bit     = MP200_CLOCKGATE_DSP_CLK,
	.clkctrl_bit = MP200_CLKCTRL_ADSP,
};

/* AVC */
static struct clk clk_avc_hsclk = {
	.name        = "avc_hsclk",
	.clk_bit     = MP200_CLOCKGATE_AVC_HSCLK,
	.clkctrl_bit = MP200_CLKCTRL_AVCHSCK,
};
static struct clk clk_avc_hmclk = {
	.name        = "avc_hmclk",
	.clk_bit     = MP200_CLOCKGATE_AVC_HMCLK,
	.clkctrl_bit = MP200_CLKCTRL_AVCHMCK,
};
static struct clk clk_avc_clkm = {
	.name        = "avc_clkm",
	.clk_bit     = MP200_CLOCKGATE_AVC_CLKM,
	.clkctrl_bit = MP200_CLKCTRL_AVCCKM,
};
static struct clk clk_avc_clke = {
	.name        = "avc_clke",
	.clk_bit     = MP200_CLOCKGATE_AVC_CLKE,
	.clkctrl_bit = MP200_CLKCTRL_AVCCKE,
};
static struct clk clk_avc_clkd = {
	.name        = "avc_clkd",
	.clk_bit     = MP200_CLOCKGATE_AVC_CLKD,
	.clkctrl_bit = MP200_CLKCTRL_AVCCKD,
};
static struct clk clk_avc_clkc = {
	.name        = "avc_clkc",
	.clk_bit     = MP200_CLOCKGATE_AVC_CLKC,
	.clkctrl_bit = MP200_CLKCTRL_AVCCKC,
};

/* DCV */
static struct clk clk_dcv_pclk = {
	.name        = "dcv_pclk",
	.clk_bit     = MP200_CLOCKGATE_DCV_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_DCVPCLK,
};
static struct clk clk_dcv = {
	.name        = "dcv",
	.clk_bit     = MP200_CLOCKGATE_DCV_CLK,
};

/* LCD */
static struct clk clk_lcd_cclk = {
	.name        = "lcd_cclk",
	.clk_bit     = MP200_CLOCKGATE_LCD_CCLK,
	.clkctrl_bit = MP200_CLKCTRL_LCDCCK,
};
static struct clk clk_lcd_lclk = {
	.name        = "lcd_lclk",
	.clk_bit     = MP200_CLOCKGATE_LCD_LCLK,
	.div_reg     = SMU_DIVLCDLCLK,
};
static struct clk clk_lcd_pclk = {
	.name        = "lcd_pclk",
	.clk_bit     = MP200_CLOCKGATE_LCD_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_LCDPCLK,
};
static struct clk clk_lcd = {
	.name        = "lcd",
	.clk_bit     = MP200_CLOCKGATE_LCD_CLK,
	.clkctrl_bit = MP200_CLKCTRL_LCD,
};


/* DTV */
static struct clk clk_dtv_pclk = {
	.name        = "dtv_pclk",
	.clk_bit     = MP200_CLOCKGATE_DTV_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_DTVPCLK,
};
static struct clk clk_dtv = {
	.name        = "dtv",
	.clk_bit     = MP200_CLOCKGATE_DTV_CLK,
	.clkctrl_bit = MP200_CLKCTRL_DTV,
};

/* NTS */
static struct clk clk_nts_pclk = {
	.name        = "nts",
	.clk_bit     = MP200_CLOCKGATE_NTS_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_NTSPCLK,
};
static struct clk clk_nts = {
	.name        = "nts",
	.clk_bit     = MP200_CLOCKGATE_NTS_CLK,
	.clkctrl_bit = MP200_CLKCTRL_NTS,
};

/* NAND */
static struct clk clk_nand_pclk = {
	.name        = "nand_pclk",
	.clk_bit     = MP200_CLOCKGATE_NAND_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_NANDPCLK,
};
static struct clk clk_nand_hclk = {
	.name        = "nand_hclk",
	.clk_bit     = MP200_CLOCKGATE_NAND_HCLK,
	.clkctrl_bit = MP200_CLKCTRL_NAND,
};


/* MMM */
static struct clk clk_mmm  = {
	.name        = "mmm",
	.clk_bit     = MP200_CLOCKGATE_MMM_CLK,
	.clkctrl_bit = MP200_CLKCTRL_MMM,
};
/* MSP */
static struct clk clk_msp_rtck = {
	.name        = "msp_rtck",
	.clk_bit     = MP200_CLOCKGATE_MSP_RTCK,
};
static struct clk clk_msp_sclk = {
	.name        = "msp_sclk",
	.clk_bit     = MP200_CLOCKGATE_MSP_SCLK,
};
static struct clk clk_msp_pclk = {
	.name        = "msp_pclk",
	.clk_bit     = MP200_CLOCKGATE_MSP_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_MSPPCLK,
};


/* PCM */
static struct clk clk_pcm1_sclk = {
	.name        = "pcm1_sclk",
	.clk_bit     = MP200_CLOCKGATE_PM1_SCLK,
	.div_reg     = SMU_DIVPM1SCLK,
};
static struct clk clk_pcm0_sclk = {
	.name        = "pcm0_sclk",
	.clk_bit     = MP200_CLOCKGATE_PM0_SCLK,
	.div_reg     = SMU_DIVPM0SCLK,
};
static struct clk clk_pcm_pclk = {
	.name        = "pcm",
	.clk_bit     = MP200_CLOCKGATE_PM0_PCLK,
};

static struct clk clk_pcm0_clk = {
	.name        = "pcm0_clk",
	.clk_bit     = MP200_CLOCKGATE_PM0_CLK,
	.clkctrl_bit = MP200_CLKCTRL_PM0PCLK,
};
static struct clk clk_pcm1_clk = {
	.name        = "pcm1_clk",
	.clk_bit     = MP200_CLOCKGATE_PM1_CLK,
	.clkctrl_bit = MP200_CLKCTRL_PM1PCLK,
};



/* USB */
static struct clk clk_usb = {
	.name        = "usb",
	.clk_bit     = MP200_CLOCKGATE_USB_CLK,
};

/* SDM */
static struct clk clk_sdia = {
	.name        = "sdia",
	.clk_bit     = MP200_CLOCKGATE_SDIA_CLK,
};
static struct clk clk_sdib = {
	.name        = "sdib",
	.clk_bit     = MP200_CLOCKGATE_SDIB_CLK,
};
static struct clk clk_sdic = {
	.name        = "sdic",
	.clk_bit     = MP200_CLOCKGATE_SDIC_CLK,
};

/* UART */
static struct clk clk_uart2 = {
	.name        = "uart2",
	.clk_bit     = MP200_CLOCKGATE_U72_SCLK,
	.div_reg     = SMU_DIVU72SCLK,
};
static struct clk clk_uart1 = {
	.name        = "uart1",
	.clk_bit     = MP200_CLOCKGATE_U71_SCLK,
	.div_reg     = SMU_DIVU71SCLK,
};
static struct clk clk_uart0 = {
	.name        = "uart0",
	.clk_bit     = MP200_CLOCKGATE_U70_SCLK,
	.div_reg     = SMU_DIVU70SCLK,
};
static struct clk clk_uart = {
	.name        = "uart",
	.clk_bit     = MP200_CLOCKGATE_U70_CLK,
};

/* I2C */
static struct clk clk_i2c_sclk = {
	.name        = "i2c_sclk",
	.clk_bit     = MP200_CLOCKGATE_IIC_SCLK,
	.div_reg     = SMU_DIVIICSCLK,
};
static struct clk clk_i2c = {
	.name        = "i2c",
	.clk_bit     = MP200_CLOCKGATE_IIC_CLK,
};
static struct clk clk_i2c2_sclk = {
	.name        = "i2c2_sclk",
	.clk_bit     = MP200_CLOCKGATE_IIC2_SCLK,
	.div_reg     = SMU_DIVIICSCLK,
};
static struct clk clk_i2c2 = {
	.name        = "i2c2",
	.clk_bit     = MP200_CLOCKGATE_IIC2_CLK,
};

/* EFS */
static struct clk clk_efs = {
	.name        = "efs",
	.clk_bit     = MP200_CLOCKGATE_EFS_PCLK,		/* <- no exist ClockStructure.xls */
};


/* PWM */
static struct clk clk_pwm_pwclk1 = {
	.name        = "pwm_pwclk1",
	.clk_bit     = MP200_CLOCKGATE_PWM_PWCLK1,
};
static struct clk clk_pwm_pwclk0 = {
	.name        = "pwm_pwclk0",
	.clk_bit     = MP200_CLOCKGATE_PWM_PWCLK0,
};
static struct clk clk_pwm_pclk = {
	.name        = "pwm_pclk",
	.clk_bit     = MP200_CLOCKGATE_PWM_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_PWMPCLK,
};

/* SPI */
static struct clk clk_spi2_sclk = {
	.name        = "spi2_sclk",
	.clk_bit     = MP200_CLOCKGATE_SP2_SCLK,
	.clkctrl_bit = MP200_CLKCTRL_SP2SCLK,
	.div_reg     = SMU_DIVSP2SCLK,
};
static struct clk clk_spi2_pclk = {
	.name        = "spi2_pclk",
	.clk_bit     = MP200_CLOCKGATE_SP2_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_SP2PCLK,
};
static struct clk clk_spi1_sclk = {
	.name        = "spi1_sclk",
	.clk_bit     = MP200_CLOCKGATE_SP1_SCLK,
	.clkctrl_bit = MP200_CLKCTRL_SP1SCLK,
	.div_reg     = SMU_DIVSP1SCLK,
};
static struct clk clk_spi1_pclk = {
	.name        = "spi1_pclk",
	.clk_bit     = MP200_CLOCKGATE_SP1_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_SP1PCLK,
};
static struct clk clk_spi0_sclk = {
	.name        = "spi0_sclk",
	.clk_bit     = MP200_CLOCKGATE_SP0_SCLK,
	.clkctrl_bit = MP200_CLKCTRL_SP0SCLK,
	.div_reg     = SMU_DIVSP0SCLK,
};
static struct clk clk_spi0_pclk = {
	.name        = "spi0_pclk",
	.clk_bit     = MP200_CLOCKGATE_SP0_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_SP0PCLK,
};

/* MWI(uWire) */
static struct clk clk_mwi_sclk = {
	.name        = "mwi_sclk",
	.clk_bit     = MP200_CLOCKGATE_MWI_SCLK,
	.div_reg     = SMU_DIVMWISCLK,
};
static struct clk clk_mwi_pclk = {
	.name        = "mwi_pclk",
	.clk_bit     = MP200_CLOCKGATE_MWI_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_MWIPCLK,
};

/* TIMER */
static struct clk clk_tim = {
	.name        = "tim",
	.clk_bit     = MP200_CLOCKGATE_ATIM_PCLK,
	.clkctrl_bit = MP200_CLKCTRL_TIMPCLK,
	.div_reg     = SMU_DIVTIMTIN,
};
static struct clk clk_tw3 = {
	.name        = "WDT3",
	.clk_bit     = MP200_CLOCKGATE_TW3_TIN,
	.div_reg     = SMU_TI3TIN_SEL,
};
static struct clk clk_tw2 = {
	.name        = "WDT2",
	.clk_bit     = MP200_CLOCKGATE_TW2_TIN,
	.div_reg     = SMU_TI2TIN_SEL,
};
static struct clk clk_tw1 = {
	.name        = "WDT1",
	.clk_bit     = MP200_CLOCKGATE_TW1_TIN,
	.div_reg     = SMU_TI1TIN_SEL,
};
static struct clk clk_tw0 = {
	.name        = "WDT0",
	.clk_bit     = MP200_CLOCKGATE_TW0_TIN,
	.div_reg     = SMU_TI0TIN_SEL,
};
static struct clk clk_tg5 = {
	.name        = "GPT5",
	.clk_bit     = MP200_CLOCKGATE_TG5_TIN,
	.div_reg     = SMU_TGNTIN_SEL,
};
static struct clk clk_tg4 = {
	.name        = "GPT4",
	.clk_bit     = MP200_CLOCKGATE_TG4_TIN,
	.div_reg     = SMU_TGNTIN_SEL,
};
static struct clk clk_tg3 = {
	.name        = "GPT3",
	.clk_bit     = MP200_CLOCKGATE_TG3_TIN,
	.div_reg     = SMU_TGNTIN_SEL,
};
static struct clk clk_tg2 = {
	.name        = "GPT2",
	.clk_bit     = MP200_CLOCKGATE_TG2_TIN,
	.div_reg     = SMU_TGNTIN_SEL,
};
static struct clk clk_tg1 = {
	.name        = "GPT1",
	.clk_bit     = MP200_CLOCKGATE_TG1_TIN,
	.div_reg     = SMU_TGNTIN_SEL,
};
static struct clk clk_tg0 = {
	.name        = "GPT0",
	.clk_bit     = MP200_CLOCKGATE_TG0_TIN,
	.div_reg     = SMU_TGNTIN_SEL,
};
static struct clk clk_timer3 = {
	.name        = "timer3",
	.clk_bit     = MP200_CLOCKGATE_TI3_TIN,
	.div_reg     = SMU_TI3TIN_SEL,
};
static struct clk clk_timer2 = {
	.name        = "timer2",
	.clk_bit     = MP200_CLOCKGATE_TI2_TIN,
	.div_reg     = SMU_TI2TIN_SEL,
};
static struct clk clk_timer1 = {
	.name        = "timer1",
	.clk_bit     = MP200_CLOCKGATE_TI1_TIN,
	.div_reg     = SMU_TI1TIN_SEL,
};
static struct clk clk_timer0 = {
	.name        = "timer0",
	.clk_bit     = MP200_CLOCKGATE_TI0_TIN,
	.div_reg     = SMU_TI0TIN_SEL,
};


#endif /* __ARCH_ARM_MACH_MP200_CLOCK_H */
