Device-Tree bindings for Xilinx Video Timing Controller(VTC)

Xilinx VTC is a general purpose video timing generator and detector.
The input side of this core automatically detects horizontal and
vertical synchronization, pulses, polarity, blanking timing and active pixels.
While on the output, it generates the horizontal and vertical blanking and
synchronization pulses used with a standard video system including support
for programmable pulse polarity.

The core is commonly used with Video in to AXI4-Stream core to detect the
format and timing of incoming video data or with AXI4-Stream to Video out core
to generate outgoing video timing for downstream sinks like a video monitor.

For details please refer to
https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_1/pg016_v_tc.pdf

Required properties:
 - compatible: value should be "xlnx,bridge-v-tc-6.1"
 - reg: base address and size of the VTC IP
 - xlnx,pixels-per-clock: Pixels per clock of the stream. Can be 1, 2 or 4.

Example:
	v_tc_0: v_tc@80030000 {
			compatible = "xlnx,bridge-v-tc-6.1";
			reg = <0x0 0x80030000 0x0 0x10000>;
			xlnx,pixels-per-clock = <2>;
	};
