Xilinx ZynqMP PHY binding

This binding describes a ZynqMP PHY device that is used to control ZynqMP
High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.

Required properties (controller (parent) node):
- compatible	: Can be "xlnx,zynqmp-psgtr-v1.1" or "xlnx,zynqmp-psgtr"
		  "xlnx,zynqmp-psgtr-v1.1" has the lpd address mapping removed

- reg           : Address and length of register sets for each device in
                  "reg-names"
- reg-names     : The names of the register addresses corresponding to the
		  registers filled in "reg":
			- serdes: SERDES block register set
			- siou: SIOU block register set
			- lpd: Low power domain peripherals reset control

Required nodes	:  A sub-node is required for each lane the controller
		   provides.

Required properties (port (child) nodes):
lane0:
- #phy-cells	: Should be 4
		  Cell after port phandle is device type from:
			- <PHY_TYPE_PCIE 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SATA 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_DP 1 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SGMII 0 LANE_NUM FREQUENCY>
lane1:
- #phy-cells	: Should be 4
		  Cell after port phandle is device type from:
			- <PHY_TYPE_PCIE 1 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SATA 1 LANE_NUM FREQUENCY>
			- <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_DP 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SGMII 1 LANE_NUM FREQUENCY>
lane2:
- #phy-cells	: Should be 4
		  Cell after port phandle is device type from:
			- <PHY_TYPE_PCIE 2 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SATA 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_DP 1 LANE_NUM FREQUENC>
			- <PHY_TYPE_SGMII 2 LANE_NUM FREQUENCY>
lane3:
- #phy-cells	: Should be 4
		  Cell after port phandle is device type from:
			- <PHY_TYPE_PCIE 3 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SATA 1 LANE_NUM FREQUENCY>
			- <PHY_TYPE_USB3 1 LANE_NUM FREQUENCY >
			- <PHY_TYPE_DP 0 LANE_NUM FREQUENCY>
			- <PHY_TYPE_SGMII 3 LANE_NUM FREQUENCY>

Note:	LANE_NUM : This determines which lane's reference clock is shared by controller.
	FREQUENCY: This the clock frequency at which controller wants to operate.


Example:
	serdes: zynqmp_phy@fd400000 {
		compatible = "xlnx,zynqmp-psgtr";
		status = "okay";
		reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>,
			<0x0 0xff5e0000 0x0 0x1000>;
		reg-names = "serdes", "siou", "lpd";

		lane0: lane@0 {
			#phy-cells = <4>;
		};
		lane1: lane@1 {
			#phy-cells = <4>;
		};
		lane2: lane@2 {
			#phy-cells = <4>;
		};
		lane3: lane@3 {
			#phy-cells = <4>;
		};
	};

Specifying phy control of devices
=================================

Device nodes should specify the configuration required in their "phys"
property, containing a phandle to the phy port node and a device type.

phys = <PHANDLE CONTROLLER_TYPE CONTROLLER_INSTANCE LANE_NUM LANE_FREQ>;

PHANDLE                 = &lane0 or &lane1 or &lane2 or &lane3
CONTROLLER_TYPE         = PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB
			  or PHY_TYPE_DP or PHY_TYPE_SGMII
CONTROLLER_INSTANCE     = Depends on controller type used, can be any of
				PHY_TYPE_PCIE : 0 or 1 or 2 or 3
				PHY_TYPE_SATA : 0 or 1
				PHY_TYPE_USB  : 0 or 1
				PHY_TYPE_DP   : 0 or 1
				PHY_TYPE_SGMII: 0 or 1 or 2 or 3
LANE_NUM                = Depends on which lane clock is used as ref clk, can be
			  0 or 1 or 2 or 3
LANE_FREQ               = Frequency that controller can operate, can be any of
			  19.2Mhz,20Mhz,24Mhz,26Mhz,27Mhz,28.4Mhz,40Mhz,52Mhz,
			  100Mhz,108Mhz,125Mhz,135Mhz,150Mhz

Example:

#include <dt-bindings/phy/phy.h>

	usb@fe200000 {
		...
		phys	  = <&lane2 PHY_TYPE_USB3 0 2 2600000>;
		...
	};

	ahci@fd0c0000 {
		...
		phys	  = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
		...
	};
