Xilinx ZynqMP DisplayPort subsystem
-----------------------------------

Required properties:

- compatible: Must be "xlnx,zynqmp-dpsub-1.7".

- reg: Physical base address and length of the registers set for the device.
- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register
  partitions.

- interrupts: Interrupt number.
- interrupts-parent: phandle for interrupt controller.

- clocks: phandles for axi, audio, non-live video, and live video clocks.
  axi clock is required. Audio clock is optional. If not present, audio will
  be disabled. One of non-live or live video clock should be present.
- clock-names: The identification strings are required. "aclk" for axi clock.
  "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock.
  "dp_live_video_in_clk" for live video clock (clock from programmable logic).

- phys: phandles for phy specifier. The number of lanes is configurable
  between 1 and 2. The number of phandles should be 1 or 2.
- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
  For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0"
  and "dp-phy1" are required where "dp-phy0" is the primary lane.

- power-domains: phandle for the corresponding power domain

- vid-layer, gfx-layer: Required to represent available layers

Required layer properties

- dmas: phandles for DMA channels as defined in
  Documentation/devicetree/bindings/dma/dma.txt.
- dma-names: The identifier strings are required. "gfx0" for graphics layer
  dma channel. "vid" followed by index (0 - 2) for video layer dma channels.

Optional child node

- The driver populates any child device node in this node. This can be used,
  for example, to populate the sound device from the DisplayPort subsystem
  driver.

Example:
	zynqmp-display-subsystem@fd4a0000 {
		compatible = "xlnx,zynqmp-dpsub-1.7";
		reg = <0x0 0xfd4a0000 0x0 0x1000>,
		      <0x0 0xfd4aa000 0x0 0x1000>,
		      <0x0 0xfd4ab000 0x0 0x1000>,
		      <0x0 0xfd4ac000 0x0 0x1000>;
		reg-names = "dp", "blend", "av_buf", "aud";
		interrupts = <0 119 4>;
		interrupt-parent = <&gic>;

		clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
		clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;

		phys = <&lane1>, <&lane0>;
		phy-names = "dp-phy0", "dp-phy1";

		power-domains = <&pd_dp>;

		vid-layer {
			dma-names = "vid0", "vid1", "vid2";
			dmas = <&xlnx_dpdma 0>,
			       <&xlnx_dpdma 1>,
			       <&xlnx_dpdma 2>;
		};

		gfx-layer {
			dma-names = "gfx0";
			dmas = <&xlnx_dpdma 3>;
		};

		dma-names = "vid0", "vid1", "vid2", "gfx0";
		dmas = <&xlnx_dpdma 0>,
		       <&xlnx_dpdma 1>,
		       <&xlnx_dpdma 2>,
		       <&xlnx_dpdma 3>;
	};
};
