Binding for Synopsys IntelliDDR Multi Protocol Memory Controller

Synopsys EDAC driver, it does reports the DDR ECC single bit errors
that are corrected and double bit ecc errors that are detected by the DDR
ECC controller.

The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration. The ECC controller corrects one bit error and detects
two bit errors.

Required properties:
 - compatible: One of:
	- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
	- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
 - reg: Should contain DDR controller registers location and length.

Required properties for "xlnx,zynqmp-ddrc-2.40a":
 - interrupt-parent: Should be core interrupt controller.
 - interrupts: Property with a value describing the interrupt number.

Example:
	memory-controller@f8006000 {
		compatible = "xlnx,zynq-ddrc-a05";
		reg = <0xf8006000 0x1000>;
	};

	mc: memory-controller@fd070000 {
		compatible = "xlnx,zynqmp-ddrc-2.40a";
		reg = <0x0 0xfd070000 0x0 0x30000>;
		interrupt-parent = <&gic>;
		interrupts = <0 112 4>;
	};
