Device Tree Bindings for the Arasan SDHCI Controller

  The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
  Only deviations are documented here.

  [1] Documentation/devicetree/bindings/mmc/mmc.txt
  [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
  [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
  [4] Documentation/devicetree/bindings/phy/phy-bindings.txt

Required Properties:
  - compatible: Compatibility string.  One of:
    - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
    - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
    - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
    - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
    - "xlnx,zynqmp-8.9a": Xilinx ZynqMP Arasan SDHCI 8.9a PHY
      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  - reg: From mmc bindings: Register location and length.
  - clocks: From clock bindings: Handles to clock inputs.
  - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  - interrupts: Interrupt specifier
  - interrupt-parent: Phandle for the interrupt controller that services
		      interrupts for this device.

Required Properties for "arasan,sdhci-5.1":
  - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  - phy-names:  MUST be "phy_arasan".

Required Properties for "xlnx,zynqmp-8.9a":
  - xlnx,mio_bank: The value will be 0/1/2 depending on MIO bank selection.
  - xlnx,device_id: Unique Id of the device, value will be 0/1.

Optional Properties:
  - broken-mmc-highspeed: Indicates to force
				the controller to use in standard speed.
  - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
    used to access core corecfg registers.  Offsets of registers in this
    syscon are determined based on the main compatible string for the device.
  - clock-output-names: If specified, this will be the name of the card clock
    which will be exposed by this device.  Required if #clock-cells is
    specified.
  - #clock-cells: If specified this should be the value <0>.  With this property
    in place we will export a clock representing the Card Clock.  This clock
    is expected to be consumed by our PHY.  You must also specify
  - xlnx,fails-without-test-cd: when present, the controller doesn't work when
    the CD line is not connected properly, and the line is not connected
    properly. Test mode can be used to force the controller to function.
 - pinctrl-0: pin control group to be used for this controller.
 - pinctrl-names: must contain a "default" entry.

Optional Properties for "xlnx,zynqmp-8.9a":
 - nvmem-cells: list of phandle to the nvmem data cells.
 - nvmem-cell-names: Names for the each nvmem-cells specified.
 - xlnx,itap-delay-sd-hsd: Input Tap Delay for SD HS.
 - xlnx,itap-delay-sdr25: Input Tap Delay for SDR25.
 - xlnx,itap-delay-sdr50: Input Tap Delay for SDR50.
 - xlnx,itap-delay-sdr104: Input Tap Delay for SDR104.
 - xlnx,itap-delay-sd-ddr50: Input Tap Delay for SD DDR50.
 - xlnx,itap-delay-mmc-hsd: Input Tap Delay for MMC HS.
 - xlnx,itap-delay-mmc-ddr52: Input Tap Delay for MMC DDR52.
 - xlnx,itap-delay-mmc-hs200: Input Tap Delay for MMC HS200.
 - xlnx,otap-delay-sd-hsd: Output Tap Delay for SD HS.
 - xlnx,otap-delay-sdr25: Output Tap Delay for SDR25.
 - xlnx,otap-delay-sdr50: Output Tap Delay for SDR50.
 - xlnx,otap-delay-sdr104: Output Tap Delay for SDR104.
 - xlnx,otap-delay-sd-ddr50: Output Tap Delay for DDR50.
 - xlnx,otap-delay-mmc-hsd: Output Tap Delay for MMC HS.
 - xlnx,otap-delay-mmc-ddr52: Output Tap Delay for MMC DDR52.
 - xlnx,otap-delay-mmc-hs200: Output Tap Delay for MMC HS200.

Example:
	sdhci@e0100000 {
		compatible = "arasan,sdhci-8.9a";
		reg = <0xe0100000 0x1000>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&clkc 21>, <&clkc 32>;
		interrupt-parent = <&gic>;
		interrupts = <0 24 4>;
	} ;

	sdhci@e2800000 {
		compatible = "arasan,sdhci-5.1";
		reg = <0xe2800000 0x1000>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&cru 8>, <&cru 18>;
		interrupt-parent = <&gic>;
		interrupts = <0 24 4>;
		phys = <&emmc_phy>;
		phy-names = "phy_arasan";
	} ;

	sdhci: sdhci@fe330000 {
		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
		reg = <0x0 0xfe330000 0x0 0x10000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
		clock-names = "clk_xin", "clk_ahb";
		arasan,soc-ctl-syscon = <&grf>;
		assigned-clocks = <&cru SCLK_EMMC>;
		assigned-clock-rates = <200000000>;
		clock-output-names = "emmc_cardclock";
		phys = <&emmc_phy>;
		phy-names = "phy_arasan";
		#clock-cells = <0>;
	};
