/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Modified during 2001 by
 * Advanced Communications Technologies (Australia) Pty. Ltd.
 * Howard Walker, Tuong Vu-Dinh
 *
 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
 * Added support for the 16M dram simm on the 8260ads boards
 *
 * (C) Copyright 2003 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <pci.h>
#include <asm/m8260_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf ppar psor pdir podr pdat */
#if 0
	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   1,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
#else
	/* PA31 */ { 0,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
	/* PA30 */ { 0,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
	/* PA29 */ { 0,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
	/* PA28 */ { 0,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
	/* PA27 */ { 0,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
	/* PA26 */ { 0,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
	/* PA25 */ { 0,   0,   0,   0,   0,   0 }, /* PA25 */
	/* PA24 */ { 0,   0,   0,   0,   0,   0 }, /* PA24 */
	/* PA23 */ { 0,   0,   0,   0,   0,   0 }, /* PA23 */
	/* PA22 */ { 0,   0,   0,   0,   0,   0 }, /* PA22 */
	/* PA21 */ { 0,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
	/* PA20 */ { 0,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
	/* PA19 */ { 0,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
	/* PA18 */ { 0,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
	/* PA17 */ { 0,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
	/* PA16 */ { 0,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
	/* PA15 */ { 0,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
	/* PA14 */ { 0,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
	/* PA13 */ { 0,   0,   0,   0,   0,   0 }, /* PA13 */
	/* PA12 */ { 0,   0,   0,   0,   0,   0 }, /* PA12 */
	/* PA11 */ { 0,   0,   0,   0,   0,   0 }, /* PA11 */
	/* PA10 */ { 0,   0,   0,   0,   0,   0 }, /* PA10 */
	/* PA9  */ { 0,   0,   0,   0,   0,   0 }, /* PA9 */
	/* PA8  */ { 0,   0,   0,   0,   0,   0 }, /* PA8 */
	/* PA7  */ { 0,   0,   0,   1,   0,   0 }, /* PA7 */
	/* PA6  */ { 0,   0,   0,   0,   0,   0 }, /* PA6 */
	/* PA5  */ { 0,   0,   0,   1,   0,   0 }, /* PA5 */
	/* PA4  */ { 0,   0,   0,   1,   0,   0 }, /* PA4 */
	/* PA3  */ { 0,   0,   0,   1,   0,   0 }, /* PA3 */
	/* PA2  */ { 0,   0,   0,   1,   0,   0 }, /* PA2 */
	/* PA1  */ { 0,   0,   0,   0,   0,   0 }, /* PA1 */
	/* PA0  */ { 0,   0,   0,   1,   0,   0 }  /* PA0 */
#endif
    },

    /* Port B configuration */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:MII RX_DV  */
	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:MII RX_ER  */
	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:MII TX_ER  */
	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:MII TX_EN  */
	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 USBCLK */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* PC20 USBOE */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII Rx Clock (CLK15) */
	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII Tx Clock (CLK16) */
	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DSR */
	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
	/* PC12 */ {   0,   1,   0,   0,   0,   0   }, /* SCC2 DSR */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* Port (open) */
	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* DM8161 MDC */
	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* DM8161 MDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*	      conf ppar psor pdir podr pdat */
#if 0
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TxD */
	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
	/* PD26 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
#else
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
#endif
    }
};


void reset_phy (void)
{
	vu_long *bcsr = (vu_long *)CFG_BCSR;

	/* reset the FEC port */
	bcsr[1] &= ~FETH1_RST;
	udelay(2);
	bcsr[1] |=  FETH1_RST;
	udelay(1000);
#ifdef CONFIG_MII
#if 1
	/*
	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
	 * Enable autonegotiation.
	 */
#if defined(CONFIG_ETHER_ON_FCC2)
	miiphy_write(0, 16, 0x610);
	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif
#if defined(CONFIG_ETHER_ON_FCC3)
	miiphy_write(3, 16, 0x610);
	miiphy_write(3, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif

#else
	/*
	 * Ethernet PHY is configured (by means of configuration pins)
	 * to work at 10Mb/s only. We reconfigure it using MII
	 * to advertise all capabilities, including 100Mb/s, and
	 * restart autonegotiation.
	 */
	miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
	miiphy_write(0, PHY_DCR,  0x0000); /* Do not bypass Rx/Tx (de)scrambler */
	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif
#endif /* CONFIG_MII */
}

typedef struct pci_ic_s {
	unsigned long pci_int_stat;
	unsigned long pci_int_mask;
} pci_ic_t;

int board_early_init_f (void)
{
	vu_long *bcsr = (vu_long *)CFG_BCSR;
	volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT;
	volatile memctl8260_t *memctl = (volatile memctl8260_t *)CFG_IMMR;

#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
	/* Early BCSR support */
	memctl->memc_or1 = CFG_OR1_PRELIM;
	memctl->memc_br1 = CFG_BR1_PRELIM;
#endif
#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM)
	/* Early PCI support */
	memctl->memc_or8 = CFG_OR8_PRELIM;
	memctl->memc_br8 = CFG_BR8_PRELIM;
#endif
	
	bcsr[1] = ~FETHIEN_1 & ~RS232EN_1;
#if defined (CONFIG_ETHER_ON_FCC3)
	bcsr[3] = ~FETHIEN_2;
#endif
	if ((bcsr[3] & BCSR_PCI_MODE) == 0)
	{
		volatile immap_t *immap = (immap_t *) CFG_IMMR;

		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
		immap->im_siu_conf.sc_siumcr =
			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
			| SIUMCR_LBPC01;
		pci_ic->pci_int_mask |= 0xfff00000;
	}

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)

long int initdram (int board_type)
{
	long int msize = 32;

	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	volatile uchar *ramaddr, c = 0xff;
	uint or;
	uint psdmr;
	uint psrt;

	int i;

	immap->im_siu_conf.sc_ppc_acr  = 0x00000002;
	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
	immap->im_siu_conf.sc_tescr1   = 0x00004000;

	or    = CFG_OR2;
	psdmr = CFG_PSDMR;
	psrt  = CFG_PSRT;

	memctl->memc_mptpr = CFG_MPTPR;
	memctl->memc_psrt = psrt;

	memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
	memctl->memc_or2 = or;

	ramaddr = (uchar *)(CFG_SDRAM_BASE + 8);
	udelay(100);

	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
	*ramaddr = c;
	udelay(100);

	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
	for (i = 0; i < 8; i++)
		*ramaddr = c;
	udelay(100);

	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
	*ramaddr = c;
	udelay(100);

	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
	*ramaddr = c;
	udelay(100);

	/* return total 60x bus SDRAM size */
	return (msize * 1024 * 1024);
}

int checkboard (void)
{
	puts ("Board: Motorola PQ2FADS Pilot version\n");
	return 0;
}


/* from here, there is PCI related section... */
#ifdef	CONFIG_PCI

#if defined(CFG_SIIMAGE_680A)
extern void setup_sii680a(struct pci_controller *, pci_dev_t, struct pci_config_table *);
#endif
#if defined(CFG_PROMISE_PDC2026X)
extern void pci_setup_pdc2026x(struct pci_controller *, pci_dev_t, struct pci_config_table *);
#endif

#define	sii680aSetup		9
#define	pdc2026xSetup		10

#define MPC8280FADS_PCI_IRQ_VECTOR(dev, int_pin)	\
	mpc8280fads_pci_irq[(PCI_DEV(dev) % 0x16)][((int_pin-1) % 4)]

static unsigned char mpc8280fads_pci_irq[][4] = {
	{ 64 ,65, 66, 67 },
	{ 67 ,64, 65, 66 },
	{ 66 ,67, 64, 65 },
};
static void mpc8280fads_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
	pci_dev_t bdf, found_bridge;
	unsigned char irq = 0;
	unsigned char int_pin, busid, sub_busno;
	unsigned short class;

	found_bridge = bdf = PCI_BDF(0,0,0);
	class = 0;

	if (dev == bdf )
		return;
	if (PCI_BUS(dev) == 0) {
		/* for BUS0 configuration */
		pci_hose_read_config_word(hose, bdf, PCI_CLASS_DEVICE, &class);
		if (class != PCI_CLASS_BRIDGE_PCI) {
			pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &int_pin);
			irq = MPC8280FADS_PCI_IRQ_VECTOR(dev, int_pin);
		}
	} else {	
		for (busid = hose->first_busno; busid < PCI_BUS(dev) ; busid++) {
			for (	bdf = PCI_BDF(busid,0,0); 
				bdf < PCI_BDF(busid,PCI_MAX_PCI_DEVICES-1, 0);
				bdf += PCI_BDF(0,1,0)) {
			
				pci_hose_read_config_word(hose, bdf, PCI_CLASS_DEVICE, &class);
				if (class == PCI_CLASS_BRIDGE_PCI) {
					pci_hose_read_config_byte(hose, bdf, PCI_SECONDARY_BUS, &sub_busno);
					if (sub_busno == PCI_BUS(dev) )
						found_bridge = bdf;
				}
			}
		}
		if ( found_bridge != 0) {
			pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &int_pin);
			int_pin += PCI_DEV(dev) % 4;
			irq = MPC8280FADS_PCI_IRQ_VECTOR(found_bridge, int_pin);
		}
	}
	if (irq != 0 )
		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, irq);
}


static struct pci_config_table mpc8280fads_config_table[] =  
{    
#if defined(CFG_SIIMAGE_680A)
  	{ PCI_VENDOR_ID_SIIMAGE, PCI_DEVICE_ID_SIIMAGE_680, 
	PCI_ANY_ID, 
	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  (void *)sii680aSetup, {0,0,0},      
    },
#endif
#if defined(CFG_PROMISE_PDC2026X)
  	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269,
	PCI_ANY_ID, 
	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  (void *)pdc2026xSetup, {0,0,0},      
    },
  	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268,
	PCI_ANY_ID, 
	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  (void *)pdc2026xSetup, {0,0,0},      
    },
#endif
    {
	0,0,
	0,
	0,0,0,
	0,{0,0,0}
    }
};

static void mpc8280fads_reloc_pointers(void)	/* why we can not relocated pointer to ram area ? */
{
	int i;
	for (i=0; mpc8280fads_config_table[i].config_device; i++)
	{
		switch((int)mpc8280fads_config_table[i].config_device) {

#if defined(CFG_SIIMAGE_680A)
		case sii680aSetup:	mpc8280fads_config_table[i].config_device = setup_sii680a;		break;
#endif
#if defined(CFG_PROMISE_PDC2026X)
		case pdc2026xSetup:	mpc8280fads_config_table[i].config_device = pci_setup_pdc2026x;		break;
#endif
		default: printf("Error: Unknown constant in pci.c:relocate_pointers()\n");
	}
    }
}

struct pci_controller hose;

extern void pci_mpc8250_init(struct pci_controller *);

void pci_init_board(void)
{
	mpc8280fads_reloc_pointers();
	hose.fixup_irq = mpc8280fads_pci_fixup_irq;
	hose.config_table = mpc8280fads_config_table;
	hose.first_busno = 0;
	hose.last_busno =0x04;
	pci_mpc8250_init(&hose);
}
#endif
