/*
 * (C) Copyright 2001
 * Stuart Hughes <stuarth@lineo.com>
 * This file is based on similar values for other boards found in other
 * U-Boot config files, and some that I found in the mpc8260ads manual.
 *
 * Note: my board is a PILOT rev.
 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
 *
 * (C) Copyright 2003 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
#define CONFIG_MPC8272ADS	1	/* ...on motorola ads board */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/* allow serial and ethaddr to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else */
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#ifdef CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */


#define CONFIG_NET_MULTI

#ifndef CONFIG_NET_MULTI
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
/*
 * - Rx-CLK is CLK11
 * - Tx-CLK is CLK10
 * - Select bus for bd/buffers (see 28-13)
 * - Full duplex
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#elif (defined(CONFIG_ETHER_ON_FCC) && CONFIG_ETHER_INDEX == 2)
/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - Select bus for bd/buffers (see 28-13)
 * - Full duplex
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif	/* CONFIG_ETHER_INDEX */

#else	/* CONFIG_NET_MULTI */
#define CONFIG_ETHER_LOOPBACK_TEST
#define	CONFIG_ETHER_ON_FCC1
#define	CONFIG_ETHER_ON_FCC2

# define CFG_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
# define CFG_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)

# define CFG_CMXFCR_MASK2       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)

# define CFG_CPMFCR_RAMTYPE     0
# define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif	/* CONFIG_NET_MULTI */






#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
/*
 * GPIO pins used for bit-banged MII communications
 */
/* 
0000 0000 0000 0000 0001	19	MDC
0000 0000 0000 0000 0000 8	18 MDIO

Original : MDIO = PC9, MDC = PC10
*/
#define	MD_PORT_VALUE(x)		( 1 << (31-x) )
#define	MDIO_PORT_NUM			18
#define	MDC_PORT_NUM			19


#define MDIO_PORT	2		/* Port C */

#define MDIO_ACTIVE	(iop->pdir |=  MD_PORT_VALUE(MDIO_PORT_NUM) )		
#define MDIO_TRISTATE	(iop->pdir &= ~(MD_PORT_VALUE(MDIO_PORT_NUM)) )
#define MDIO_READ	((iop->pdat & MD_PORT_VALUE(MDIO_PORT_NUM)) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  MD_PORT_VALUE(MDIO_PORT_NUM); \
			else	iop->pdat &= ~(MD_PORT_VALUE(MDIO_PORT_NUM))

#define MDC(bit)	if(bit) iop->pdat |=  MD_PORT_VALUE(MDC_PORT_NUM); \
			else	iop->pdat &= ~(MD_PORT_VALUE(MDC_PORT_NUM))

#define MIIDELAY	udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */




#undef CONFIG_SPD_EEPROM	/* PQ27eADS does not have SPD... */

#ifndef CONFIG_SDRAM_PBI
#define CONFIG_SDRAM_PBI        1 /* By default, use bank-based interleaving */
#endif

#define CONFIG_8260_CLKIN	100000000	/* in Hz */

#define CONFIG_BAUDRATE		115200

#define CFG_EXCLUDE		 CFG_CMD_BEDBUG | \
				 CFG_CMD_BMP	| \
				 CFG_CMD_BSP	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_DOC	| \
				 CFG_CMD_DTT	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_FAT    | \
				 CFG_CMD_FDC	| \
				 CFG_CMD_FDOS	| \
				 CFG_CMD_HWFLOW	| \
				 CFG_CMD_KGDB	| \
				 CFG_CMD_MMC	| \
				 CFG_CMD_NAND	| \
				 CFG_CMD_PCMCIA | \
				 CFG_CMD_SCSI	| \
				 CFG_CMD_SPI	| \
				 CFG_CMD_USB	| \
				 CFG_CMD_VFD

#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_CMD_SDRAM	| \
				 CFG_CMD_I2C	| \
				 CFG_EXCLUDE	) )

#define	CONFIG_EXTRA_ENV_SETTINGS			\
	"ethaddr=00:30:65:98:9E:03\0"			\
	"eth1addr=00:30:65:98:9E:04\0"			\
	"serverip=222.21.101.119\0"			\
	"ipaddr=222.21.101.111\0"				\
	"ide_reset_timeout=5\0"				\
	"ide_maxbus=1\0"				\
	"ide_cd_timeout=30\0"				\
	"firstboot="	\
	"protect off ff800000 ff83ffff; " 		\
	"erase ff800000 ff83ffff; " 			\
	"cp.b fff00000 ff800000 20; "			\
	"protect on ff800000 ff83ffff; " 		\
	"protect off fff40000 fff7ffff; "		\
	"erase fff40000 fff7ffff; "			\
	"setenv bootcmd run flashboot; "			\
	"setenv bootdelay 5; "				\
	"setenv flashbootcmd bootm ff900000; "	\
	"setenv flashbootargs setenv bootargs console=ttyS0,115200 root=/dev/ram rw; "	\
	"setenv hdbootcmd diskboot 800000 0:2; "	\
	"setenv hdbootargs setenv bootargs console=tty0 console=ttyS0,115200 root=/dev/hda4; "	\
	"setenv nfsbootcmd bootm ff900000; "	\
	"setenv nfsbootargs setenv bootargs console=ttyS0,115200 ip=dhcp root=/dev/nfs rw; "	\
	"setenv flashboot run flashbootargs flashbootcmd; "	\
	"setenv hdboot run hdbootargs hdbootcmd; "	\
	"setenv nfsboot run nfsbootargs nfsbootcmd; "	\
	"setenv firstboot; "				\
	"echo setting for firstboot was completed; "	\
	"echo pls set JP9 to memory side.; "		\
	"saveenv; "					\
	"reset\0"

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	0	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"run firstboot"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG	/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16			/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CFG_FLASH_BASE		0xff800000
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
#define CFG_FLASH_SIZE		8
#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define CFG_JFFS2_FIRST_SECTOR  1
#define CFG_JFFS2_LAST_SECTOR   27
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART

/* this is stuff came out of the Motorola docs */
#define CFG_DEFAULT_IMMR	0x0F010000
#define CFG_IMMR		0xF0000000
#define CFG_BCSR		0xe0000000
#define CFG_PCI_INT		0xF8200000	/* PCI interrupt controller */
#define CFG_SDRAM_BASE		0x00000000
#undef CFG_LSDRAM_BASE
#define CFG_EEPROM_CS_BASE	0xF8300000		/* EEPROM */
#define CFG_ATM_UNI_CS_BASE	0xF8100000		/* PM5350 ATM UNI */
/* PCI */
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_BOOTDELAY 1
#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_EEPRO100
#define CONFIG_RTL8139

#define CONFIG_RTY922_EXT		/* Enable IDE and more Extended Mode */
#define	CFG_SIIMAGE_680A
#define	CFG_PROMISE_PDC2026X

/* PCI Memory map (if different from default map */
#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
				 PICMR_PREFETCH_EN)

/*
 * These are the windows that allow the CPU to access PCI address space.
 * All three PCI master windows, which allow the CPU to access PCI
 * prefetch, non prefetch, and IO space (see below), must all fit within
 * these windows.
 */

/* PCIBR0 */
#define CFG_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
#define CFG_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
/* PCIBR1 */
#define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
#define CFG_PCIMSK1_MASK		PCIMSK_16MB		/* Size of window */

/*
 * Master window that allows the CPU to access PCI Memory (prefetch).
 * This window will be setup with the first set of Outbound ATU registers
 * in the bridge.
 */

#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)

/*
 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)

/*
 * Master window that allows the CPU to access PCI IO space.
 * This window will be setup with the third set of Outbound ATU registers
 * in the bridge.
 */

#define CFG_PCI_MSTR_IO_LOCAL       0xF4000000          /* Local base */
#define CFG_PCI_MSTR_IO_BUS         0x00000000	          /* PCI base   */
#define CFG_CPU_PCI_IO_START        CFG_PCI_MSTR_IO_LOCAL
#define CFG_PCI_MSTR_IO_SIZE        0x01000000          /* 16MB */
#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_16MB | POCMR_ENABLE | POCMR_PCI_IO)

#define	_IO_BASE			CFG_PCI_MSTR_IO_LOCAL

#define CFG_DBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* end of pci section */


/* ATAPI Support (experimental) */
#define CONFIG_ATAPI
#define CFG_IDE_MAXBUS          2                       /* max. 2 IDE busses    */
#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR       CFG_PCI_MSTR_IO_LOCAL	/* base address */
#define CFG_ATA_IDE0_OFFSET     0                   /* default ide0 offste */
#define CFG_ATA_IDE1_OFFSET     0                   /* default ide1 offset */
#define CFG_ATA_DATA_OFFSET     0                       /* data reg offset    */
#define CFG_ATA_REG_OFFSET      0                       /* reg offset */
#define CFG_ATA_ALT_OFFSET      0                   /* alternate register offset */

#define ATA_RESET_TIME          (ata_reset_time)

#undef	CONFIG_LBA48
#undef  CONFIG_IDE_PCMCIA                               /* no pcmcia interface required */
#undef  CONFIG_IDE_LED                                  /* no led for ide supported */

/* Partion suppport */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION




/* BCSR[1] */
#define RS232EN_1		0x02000002
#define RS232EN_2		0x01000001
#define FETHIEN_1		0x08000008
#define FETH1_RST		0x04000004
/* BCSR[3] */
#define USB_EN			0x80000000	/* Low = Enable USB, High = USB disable */
#define USB_HI_SPEED		0x40000000	/* Low = HighSpeed, High = LowSpeed */
#define USBVCCO			0x20000000	/* Low = VCCO OFF, High = VCCO apply */
#define FETHIEN_2		0x10000000
#define FETH2_RST		0x08000000
#define ATM16			0x04000000
#define ATM_SINGLE_PHY		0x02000000
#define BCSR_PCI_MODE		0x01000000

#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM	0x02	/* Software reboot	     */

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#else
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
#endif /* CONFIG_BZIP2 */

#ifndef CFG_RAMBOOT
#  define CFG_ENV_IS_IN_FLASH	1
#  define CFG_ENV_SECT_SIZE	0x40000
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
#else
#  define CFG_ENV_IS_IN_NVRAM	1
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
#  define CFG_ENV_SIZE		0x200
#endif /* CFG_RAMBOOT */


#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


 #define CFG_HID0_INIT		0

#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )

#define CFG_HID2		0
/*
#define CFG_HRCW_MASTER (   ( HRCW_BPS11 )						|\
			    ( HRCW_L2CPC01 | HRCW_DPPC11 | HRCW_ISB010 )		|\
			    ( HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )			|\
			    ( HRCW_CS10PC00 | HRCW_PCI_MODCK | HRCW_MODCK_H1010 )	\
			)
*/
#define CFG_HRCW_MASTER 0x0c72361a

/* 
	Attention! HRCW_CS10PC is MUST BE set to 00. HRCW_APPC is MUST BE set to 10. 
   	If it wrong, Bootloader does not run correctly... 
	Because CS6 and CS7 is used by Tool CS1 and CS2.
*/
			

/* no slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0

#define CFG_SYPCR		0xFFFFFFC3
#define CFG_BCR			0x100C0000 
#define CFG_SIUMCR            	0x0d200000

#define CFG_SCCR		SCCR_DFBRG01
#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
#define CFG_OR0_PRELIM		0xFF800876
#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
#define CFG_OR1_PRELIM		0xFFFF8010
#define CFG_BR3_PRELIM		(CFG_PCI_INT | 0x1801)			/* PCI interrupt controller */
#define CFG_OR3_PRELIM		0xFFFF8010
#define CFG_BR4_PRELIM		(CFG_EEPROM_CS_BASE | 0x00000801)	/* EEPROM */
#define CFG_OR4_PRELIM		0xFFFF8846
#define CFG_BR5_PRELIM		(CFG_ATM_UNI_CS_BASE | 0x00000801)	/* PM5350 ATM UNI */
#define CFG_OR5_PRELIM		0xFFFF8E36
#define CFG_RMR			RMR_CSRE
#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR		0

#undef CFG_LSDRAM_BASE		/* No local bus SDRAM on MPC8266ADS */
	
#define CFG_OR2			0xfc002CC0
/*#define CFG_PSDMR		0x834e24a3*/
#define	CFG_PSDMR		0x834f36a3
/* #define CFG_PSDMR		0x83feb3a3 */
/*
	maybe following settings also works...
	CL3 :			0x834eb4a3	(RFRC=7CLK, PRE2ACT=3, PRE2RW=2, LD2PRE=CL-1, CL=3)
	
*/
	/* LDOTOPRE is CL - 1 */


#define CFG_PSRT		0x13
#define CFG_MPTPR		0x2800	/* 0x1900 ??? */

#define CFG_RESET_ADDRESS	0xfff00110

#define	CONFIG_IDENT_STRING	"Rev.0.1-a7-pre7 for MPC8272ADS"

#endif /* __CONFIG_H */
