/*
 * include/asm-arm/arch-cxd4115/regs-cf.h
 *
 * CXD4115 CF registers
 *
 * Copyright 2007,2008,2009 Sony Corporation
 * 
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * 
 */
#ifndef __REGS_CF_H__
#define __REGS_CF_H__

#define CF_EXIO_DMA		0x00001000
#define CF_ATTRBASE      	0x00004000
#define CF_MEMBASE		0x00004800
#define CF_IOBASE	        0x00005000
#define CF_EXIO0_IOBASE		0x00010000
#define CF_EXIO1_IOBASE		0x00020000

/* registers */
#define CF_STAT             0x00
#define CF_IRQ_STAT         0x04
#define CF_IRQ_EN           0x08
#define CF_IRQ_CLR          0x0c
#define CF_MODE             0x10
#define CF_MON              0x14
#define CF_EXIO_MON         0x18
#define CF_DMA_POL          0x1c
#define CF_DMA_CNT          0x20
#define CF_TIMPAR1          0x24
#define CF_TIMPAR2          0x28
#define CF_TIMPAR3          0x2c
#define EXIO0_TIMPAR1       0x30
#define EXIO0_TIMPAR2       0x34
#define EXIO1_TIMPAR1       0x38
#define EXIO1_TIMPAR2       0x3c
#define DMA_TIMPAR1         0x40
#define DMA_TIMPAR2         0x44

/* Bit assign for CF registers */
#define CF_STAT_DM_FUL      0x01
//#define CF_STAT_DM_EMP      0x02
//#define CF_STAT_DM_CF_BUSY  0x04
#define CF_STAT_DM_CF0_INT   0x08
//#define CF_STAT_DM_RST_BSY  0x10
//#define CF_STAT_DM0_FUL     0x100
//#define CF_STAT_DM1_FUL     0x200
#define CF_STAT_DREQ0       0x400
//#define CF_STAT_DREQ1       0x800

#define CF_IRQ_STAT_INT_CF0_TIMOV   0x01
#define CF_IRQ_STAT_INT_CF0_IRQ     0x02
#define CF_IRQ_STAT_INT_IOIS16      0x04
#define CF_IRQ_STAT_INT_EXIO_IRQ    0x08

#define CF_IRQ_EN_INT_CF0_TIMOV_EN  0x01
#define CF_IRQ_EN_INT_CF0_IRQ_EN    0x02
#define CF_IRQ_EN_INT_IOIS16_EN     0x04
#define CF_IRQ_EN_INT_EXIO_IRQ_EN   0x08

#define CF_IRQ_CLR_INT_CF0_TIMOV_CLR    0x01
#define CF_IRQ_CLR_INT_CF0_IRQ_CLR      0x02
#define CF_IRQ_CLR_INT_IOIS16_CLR       0x04

#define CF_IRQ_MODE_CF0_MODE   0x01

/* IO access timing */
#define CF_TIMPAR1_VAL	0x15121413
#define CF_TIMPAR2_VAL  0x0c031202
#define CF_TIMPAR3_VAL  0x0006

#endif /* __REGS_CF_H__ */
