/*
 * include/asm-arm/arch-cxd4105/regs-dmac.h
 *
 * CXD4105 address map
 *
 * Copyright 2005,2006 Sony Corporation
 * 
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * 
 */
#ifndef __REGS_DMAC_H__
#define __REGS_DMAC_H__

#if 0 /* 16byte FIFO.  DO NOT USE */
#define CXD4105_DMAC1_BASE		(CXD4105_AHB_BASE+SZ_1M*4)
#define CXD4105_DMAC1_SIZE		(SZ_1M)
#endif

/* 32byte FIFO */
#define CXD4105_DMAC0_BASE		(CXD4105_AHB_BASE+SZ_1M*5)
#define CXD4105_DMAC0_SIZE		(SZ_1M)

/* global register */
#define DMACINTSTATUS   	(IO_ADDRESSP(CXD4105_DMAC0_BASE))
# define DMAC_VALIDBITMASK		0x000000ff /* 8ch */
#define DMACINTTCSTATUS   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x04)
#define DMACINTTCCLR   		(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x08)
#define DMACINTERRORSTATUS   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x0C)
#define DMACINTERRCLR   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x10)
#define DMACRAWINTTCSTATUS   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x14)
#define DMACRAWINTERRORSTATUS  	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x18)
#define DMACENBLDCHNS   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x1C)
#define DMACSOFTBREQ   		(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x20)
#define DMACSOFTSREQ   		(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x24)
#define DMACSOFTLBREQ   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x28)
#define DMACSOFTLSREQ   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x2C)
#define DMACCONFIGRATION   	(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x30)
#define DMACSYNC   		(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x34)
#define DMACSREQMASK   		(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x38)

/* channel registers */
#define DMA_BASE_(x)		(IO_ADDRESSP(CXD4105_DMAC0_BASE)+0x100+((x)<<5))
#define DMACCSRCADDR_(x)	(DMA_BASE_(x)+0x00)
#define DMACCDESTADDR_(x)	(DMA_BASE_(x)+0x04)
#define DMACCLLI_(x)		(DMA_BASE_(x)+0x08)
#define DMACCCONTROL_(x)	(DMA_BASE_(x)+0x0C)
# define DMAC_TC_ENABLE		0x80000000 /* TC intr enable */
#define DMACCCONFIGURATION_(x)	(DMA_BASE_(x)+0x10)
# define DMACCCONFIG_DESTDEV_SHIFT 6
# define DMACCCONFIG_SRCDEV_SHIFT  1
# define DMACCCONFIG_HALT	0x00040000
# define DMACCCONFIG_ACTIVE	0x00020000
# define DMACCCONFIG_ENABLE	0x00000001

#define DMA_MAX_CHANNELS	8
#define DMA_CH_TO_IRQ(x)	(IRQ_DMA0_0 + (x))
#define DMA_IRQ_TO_CH(x)	((x) - IRQ_DMA0_0)

#define DMA_REQID_MS0		0
#define DMA_REQID_MS1		1
#define DMA_REQID_MSIO		2
#define DMA_REQID_MXXTX		3
#define DMA_REQID_MXXRX		4
#define DMA_REQID_UART0TX	5
#define DMA_REQID_UART0RX	6
#define DMA_REQID_UART1TX	7
#define DMA_REQID_UART1RX	8
#define DMA_REQID_SSP0TX	10
#define DMA_REQID_SSP0RX	11
#define DMA_REQID_SSP1TX	12
#define DMA_REQID_SSP1RX	13
#define DMA_REQID_EXIO		15

#endif /* __REGS_DMAC_H__ */
