/*
 * arch/arm/mach-cxd4115/uart.S
 *
 * UART initialize for cxd4115
 *
 * Copyright 2008 Sony Corporation
 *
 */

#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/hardware.h>
#include <asm/arch/regs-clk.h>
#include <linux/amba/serial.h>

/* 
 * UARTx's ck_pclk_power_save register.
 * This should go asm/arch/regs-clk.h
 */
#define CXD4115_HSTCTRL_UART(x) (CXD4115_HSTCTRL_BASE + CLKBLK_UART_CLKBASE + 0x10*(x))


/* setting values */
	
#define __UART_TIMEOUT        0x1ff
/* UART clock 12MHz, baud 115200bps */
#define __UART_BAUD_F         0x21
#define __UART_BAUD_I          0x6

#define __UART_8N1_NO_FIFO    0x70

	.text				
ENTRY(uart0_init)
	@ Initialize UART (not uart0)
	@ Preserve r0 and r1

	ldr	r2, =CXD4115_HSTCTRL_UART(CONFIG_CXD4115_DEBUG_UART_NO)
	mov	r3, #0x01
	str	r3, [r2]			@ enable UART CLK
#if 0
	@ select GPIO
	ldr	r2, =CXD4105_GPIO(CXD4105_UART_GPIO) @ GPIOE1 base
	mov	r3, #0x01
	str	r3, [r2, #GPIOE_PORTSEL(0)]	@ GPIOE1_1 as UART0 TXD
#endif
	@ r2 :	 Base address
	ldr	r2, =CXD4115_UART(CONFIG_CXD4115_DEBUG_UART_NO)
	
	@ Interrupt
	mov	r3, #0
	str	r3, [r2, #0x38]
	
	@ 115200bps,8N1 (CLK=12MHz)
	mov	r3, #__UART_BAUD_F
	str	r3, [r2, #UART011_FBRD]

	mov	r3, #__UART_BAUD_I
	str	r3, [r2, #UART011_IBRD]
	
	mov	r3, #__UART_8N1_NO_FIFO
	str	r3, [r2, #UART011_LCRH]
	
	@ clear int
	mov	r3, #0
	str	r3, [r2, #0x04]
	
	@ TX enable
	mov	r3, #UART011_CR_TXE
	orr	r3, #UART011_CR_RXE    @ option
	orr	r3, #UART01x_CR_UARTEN
	str	r3, [r2, #UART011_CR]
	
	mov	pc, lr
