/*
 * include/asm-arm/arch-cxd4115/regs-emc.h
 *
 * EMC registers
 *
 * Copyright 2007,2008,2009 Sony Corporation
 * 
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * 
 */
#ifndef __CXD4115_REGS_EMC_H__
#define __CXD4115_REGS_EMC_H__

/* register offset */
#define EMC_STATUS		0x00
#  define EMC_SDRAM_BUSY		(1<<10)
#define EMC_TRANS_CTRL		0x04
#define EMC_CS_PHY_BIND		0x08
# define EMC_PHY_AM0			0x0
# define EMC_PHY_SB			0x1
# define EMC_PHY_SD			0x2
# define EMC_PHY_AM2			0x4
# define EMC_CS_MASK			0xf
# define EMC_CS_SHIFT(x)		((x) << 2)
#define EMC_IO_CNTRL		0x0c
#define EMC_PHY_SDR_CMD		0x20
# define EMC_SDR_SEQCMD_SREF		0x03
# define EMC_SDR_SEQCMD_DPD		0x0c
#define EMC_PHY_SDR_ADDR	0x24
#define EMC_PHY_SDR_DATA	0x28
#define EMC_PHY_SDR_PWS		0x2C
#define EMC_PHY_SDR_PWC		0x30
#define EMC_PHY_SDR_CFG		0x34
#define EMC_PHY_SDR_PRM1	0x38
#define EMC_PHY_SDR_PRM2	0x3c
#define EMC_PHY_SDR_PRM3	0x40
#define EMC_PHY_SDR_PRM4	0x44
#define EMC_PHY_AM0_CFG		0x50
# define EMC_PHY_AM_PG			0x10
# define EMC_PHY_AM_BL1			0x00
# define EMC_PHY_AM_BL2			0x04
# define EMC_PHY_AM_BL4			0x08
# define EMC_PHY_AM_BL8			0x0c
# define EMC_PHY_AM_DW8			0x00
# define EMC_PHY_AM_DW16		0x01
# define EMC_PHY_AM_DW32		0x02
#define EMC_PHY_AM0_PRM1	0x54
#define EMC_PHY_AM0_PRM2	0x58
#define EMC_PHY_AM0_PRM3	0x5c
#define EMC_PHY_AM0_PRM4	0x60
#define EMC_PHY_AM0_PRM5	0x64
#define EMC_PHY_AM2_CFG		0x70
#define EMC_PHY_AM2_PRM1	0x74
#define EMC_PHY_AM2_PRM2	0x78
#define EMC_PHY_AM2_PRM3	0x7c
#define EMC_PHY_AM2_PRM4	0x80
#define EMC_PHY_AM2_PRM5	0x84
#define EMC_PHY_SB_CFG		0x94
#define EMC_PHY_SB_PRM1		0x98
#define EMC_PHY_SB_PRM2		0x9c
#define EMC_PHY_SB_PRM3		0xa0
#define EMC_PHY_SB_PRM4		0xa4
#define EMC_C0_SINGLE_WR	0x100
#define EMC_CNT_MODE		0x160
#define EMC_BP_ON_MODE		0x164
# define EMC_BP_ON			0x00000001
#define EMC_BM_CTRL		0x200
#define EMC_BM_INTSTAT		0x204
#define EMC_BM_INTCLR		0x208
#define EMC_BM_STATUS		0x20c
#define EMC_BM_CMPADR		0x210
#define EMC_BM_CMPDAT		0x214
#define EMC_BM_MSKADR		0x218
#define EMC_BM_MSKDAT		0x21c
#define EMC_BM_CAPADR		0x220
#define EMC_BM_CAPDAT		0x224

#endif /* __CXD4115_REGS_EMC_H__ */
