/*
 * include/asm-arm/arch-cxd4115/pci.h
 *
 * PCI bridge definitions
 *
 * Copyright 2007,2008,2009 Sony Corporation
 * 
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * 
 */
#ifndef __ARCH_CXD4115_PCI_H
#define __ARCH_CXD4115_PCI_H

/*  AHB <--> PCI  Physical Address mapping
       AHB             PCI BUS
   -----------------------------
   0x10000000  <---  0x10000000
        :                 :       for PCI BusMaster (to DDR)
   0x1fffffff  <---  0x1fffffff
   -----------------------------
   0x60000000  <---  0x60000000
        :                 :       for PCI BusMaster (to SDR)
   0x6fffffff  <---  0x6fffffff
   -----------------------------
   0x50000000  --->  0x50000000   [Window2]
        :                 :       for CPU (Prefechable)
   0x5fffffff  --->  0x5fffffff
   -----------------------------
   0x78068000  --->  0x78068000   [Window1] 
        :                 :       for CPU (I/O and Config space)
   0x78077fff  --->  0x78077fff
   -----------------------------
   0xd0000000  --->  0xd0000000   [Window3]
        :                 :       for CPU (NonPrefechable)
   0xdfffffff  --->  0xdfffffff
   -----------------------------
*/

#define PCIAHB_WINDOW1_BASE     (0x10000000)
#define PCIAHB_WINDOW1_SIZE     (0x10000000)
#define PCIAHB_WINDOW2_BASE     (0x60000000)
#define PCIAHB_WINDOW2_SIZE     (0x10000000)

#define AHBPCI_WINDOW1_BASE     (0x78068000)
#define AHBPCI_WINDOW1_SIZE     (0x00010000)
#define AHBPCI_WINDOW2_BASE     (0x50000000)
#define AHBPCI_WINDOW2_SIZE     (0x10000000)
#define AHBPCI_WINDOW3_BASE     (0xD0000000)
#define AHBPCI_WINDOW3_SIZE     (0x10000000)

/* PCI window (MEM, NonPrefetch) */
#define CXD4115_PCIWINDOW_BASE    AHBPCI_WINDOW3_BASE
#define CXD4115_PCIWINDOW_SIZE    AHBPCI_WINDOW3_SIZE

/* PCI window (I/O, Config) */
#define CXD4115_PCIWINDOW_IOBASE  AHBPCI_WINDOW1_BASE
#define CXD4115_PCIWINDOW_IOSIZE  AHBPCI_WINDOW1_SIZE

#define PCI_IDSEL(x)		(11 + (x))
#define PCI_CXD4115_SLOT	0

#ifndef __ASSEMBLY__
extern int cxd4115_pci_intr_init(void);
#endif /* !__ASSEMBLY__ */
#endif /* __ARCH_CXD4115_PCI_H */
