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////////////////////////////////////////////////////////////////////////////////
//==============================================================================
// [mhal_mux.h]
// Date: 20090220
// Descriptions: Add a new mux layer for HW setting
//==============================================================================
#ifndef MHAL_MUX_H
#define MHAL_MUX_H

///////////////////////////////
//  Mux Hardware Option
///////////////////////////////
// Please set this #define after Mux tree is ready
#define MUX_TREE_HEIGHT 4

#define NUMBER_OF_ANALOG_PORT 3
#define NUMBER_OF_ANALOG_SYNC_PORT (4)
#define NUMBER_OF_CVBS_PORT 17
#define NUMBER_OF_DVI_PORT 4
#define NUMBER_OF_MVOP_PORT 2
#define NUMBER_OF_CVBS_OUT_PORT 2
#define NUMBER_OF_YPBPR_OUT_PORT 0
#define PIP_SUPPORTED (MAX_WINDOW_NUM > 1)
#define NUMBER_OF_SCALER_OP_PORT 1
#define NUMBER_OF_RY_PORT 3

#define HAL_DVI_IP_A    0 //alex_tung
#define HAL_DVI_IP_B    1
#define HAL_DVI_IP_C    2
#define HAL_DVI_IP_D    3

/*
    Input ports.
    It is interface between Hal and Driver level.
*/

typedef enum
{
    HAL_INPUTPORT_NONE = INPUT_PORT_NONE_PORT,

    HAL_INPUTPORT_ANALOG0 = INPUT_PORT_ANALOG0,
    HAL_INPUTPORT_ANALOG1,
    HAL_INPUTPORT_ANALOG2,

    HAL_INPUTPORT_ANALOG_SYNC0 = INPUT_PORT_ANALOG0_SYNC,
    HAL_INPUTPORT_ANALOG_SYNC1,
    HAL_INPUTPORT_ANALOG_SYNC2,
    HAL_INPUTPORT_ANALOG_SYNC3,

    HAL_INPUTPORT_YMUX_CVBS0 = INPUT_PORT_YMUX_CVBS0,
    HAL_INPUTPORT_YMUX_CVBS1,
    HAL_INPUTPORT_YMUX_CVBS2,
    HAL_INPUTPORT_YMUX_CVBS3,
    HAL_INPUTPORT_YMUX_CVBS4,
    HAL_INPUTPORT_YMUX_CVBS5,
    HAL_INPUTPORT_YMUX_CVBS6,
    HAL_INPUTPORT_YMUX_CVBS7,
    HAL_INPUTPORT_YMUX_G0,
    HAL_INPUTPORT_YMUX_G1,
    HAL_INPUTPORT_YMUX_G2,
    HAL_INPUTPORT_YMUX_R0,
    HAL_INPUTPORT_YMUX_R1,
    HAL_INPUTPORT_YMUX_R2,
    HAL_INPUTPORT_YMUX_B0,
    HAL_INPUTPORT_YMUX_B1,
    HAL_INPUTPORT_YMUX_B2,

    HAL_INPUTPORT_CMUX_CVBS0 = INPUT_PORT_CMUX_CVBS0,
    HAL_INPUTPORT_CMUX_CVBS1,
    HAL_INPUTPORT_CMUX_CVBS2,
    HAL_INPUTPORT_CMUX_CVBS3,
    HAL_INPUTPORT_CMUX_CVBS4,
    HAL_INPUTPORT_CMUX_CVBS5,
    HAL_INPUTPORT_CMUX_CVBS6,
    HAL_INPUTPORT_CMUX_CVBS7,
    HAL_INPUTPORT_CMUX_R0,
    HAL_INPUTPORT_CMUX_R1,
    HAL_INPUTPORT_CMUX_R2,
    HAL_INPUTPORT_CMUX_G0,
    HAL_INPUTPORT_CMUX_G1,
    HAL_INPUTPORT_CMUX_G2,
    HAL_INPUTPORT_CMUX_B0,
    HAL_INPUTPORT_CMUX_B1,
    HAL_INPUTPORT_CMUX_B2,

    HAL_INPUTPORT_DVI0 = INPUT_PORT_DVI0,
    HAL_INPUTPORT_DVI1,
    HAL_INPUTPORT_DVI2,
    HAL_INPUTPORT_DVI3,

    HAL_INPUTPORT_MVOP = INPUT_PORT_MVOP,
    HAL_INPUTPORT_MVOP2,

    HAL_INPUTPORT_SCALER_OP = INPUT_PORT_SCALER_OP,

    HAL_INPUTPORT_YMUX_RY0 = INPUT_PORT_YMUX_RY0,
    HAL_INPUTPORT_YMUX_RY1,
    HAL_INPUTPORT_YMUX_RY2,
} E_INPUT_PORT_TYPE;

// Output ports.


typedef enum
{
    HAL_OUTPUTPORT_NONE_PORT = OUTPUT_PORT_NONE_PORT,

    HAL_OUTPUTPORT_SCALER_MAIN_WINDOW = OUTPUT_PORT_SCALER_MAIN_WINDOW,
    HAL_OUTPUTPORT_SCALER2_MAIN_WINDOW = OUTPUT_PORT_SCALER2_MAIN_WINDOW,

    HAL_OUTPUTPORT_SCALER_SUB_WINDOW1 = OUTPUT_PORT_SCALER_SUB_WINDOW1,
    HAL_OUTPUTPORT_SCALER2_SUB_WINDOW = OUTPUT_PORT_SCALER2_SUB_WINDOW,

    HAL_OUTPUTPORT_CVBS1 = OUTPUT_PORT_CVBS1,
    HAL_OUTPUTPORT_CVBS2 ,

    HAL_OUTPUTPORT_YPBPR1 = OUTPUT_PORT_YPBPR1,

    HAL_OUTPUTPORT_DIP_WINDOW = OUTPUT_PORT_DWIN,


}E_OUTPUT_PORT_TYPE;

typedef enum
{
    SC_MAINWIN_IPMUX_ADC_A      = 0,            ///< ADC A
    SC_MAINWIN_IPMUX_HDMI_DVI   = 1,            ///< DVI
    SC_MAINWIN_IPMUX_VD         = 2,            ///< VD
    SC_MAINWIN_IPMUX_MVOP       = 3,            ///< MPEG/DC0
    SC_MAINWIN_IPMUX_SC_VOP     = 4,            ///< Scaler VOP output
    SC_MAINWIN_IPMUX_EXT_VD     = 5,            ///< External VD
    SC_MAINWIN_IPMUX_ADC_B      = 6,            ///< ADC B
    SC_MAINWIN_IPMUX_CAPTURE    = 7,            ///< Capture
    SC_MAINWIN_IPMUX_MVOP2      = 8,            ///< MPEG/DC1
    SC_MAINWIN_IPMUX_IP_SUB     = 9,            ///< IP SUB/VE
    SC_MAINWIN_IPMUX_NOUSE      = 10,           ///< no use now
    SC_MAINWIN_IPMUX_DC2        = 11,           ///< DC2
    SC_MAINWIN_IPMUX_IP_SUB2    = 12,           ///< IP SUB2/DIP
    SC_MAINWIN_IPMUX_MHL        = 13,           ///< MHL
    SC_MAINWIN_IPMUX_VD2        = 14,           ///< VD2
} SC_MAINWIN_IPMUX_TYPE;

typedef enum
{
    SC_SUBWIN_IPMUX_ADC_A      = 0,            ///< ADC A
    SC_SUBWIN_IPMUX_HDMI_DVI   = 1,            ///< DVI
    SC_SUBWIN_IPMUX_VD         = 2,            ///< VD
    SC_SUBWIN_IPMUX_MVOP       = 3,            ///< MPEG/DC0
    SC_SUBWIN_IPMUX_SC_VOP     = 4,            ///< Scaler VOP output
    SC_SUBWIN_IPMUX_EXT_VD     = 5,            ///< External VD
    SC_SUBWIN_IPMUX_ADC_B      = 6,            ///< ADC B
    SC_SUBWIN_IPMUX_MLINK      = 8,            ///< MLink
    SC_SUBWIN_IPMUX_CAPTURE    = 7,            ///< Capture
    SC_SUBWIN_IPMUX_MVOP2      = 8,            ///< MPEG/DC1
    SC_SUBWIN_IPMUX_IP_SUB     = 9,            ///< IP SUB/VE
    SC_SUBWIN_IPMUX_NOUSE      = 10,           ///< no use now
    SC_SUBWIN_IPMUX_DC2        = 11,           ///< DC2
    SC_SUBWIN_IPMUX_IP_SUB2    = 12,           ///< IP SUB2/DIP
    SC_SUBWIN_IPMUX_MHL        = 13,           ///< MHL
    SC_SUBWIN_IPMUX_VD2        = 14,           ///< VD2
    SC_SUBWIN_IPMUX_TESTPATTERN  = 15,    ///NO DATA
} SC_SUBWIN_IPMUX_TYPE;

typedef enum
{
    SC_CLK_ADC_A      = 0,            ///< ADC A
    SC_CLK_HDMI_DVI   = 1,            ///< DVI
    SC_CLK_HDMI_DVI_P0  = 1,            ///< DVI P0
    SC_CLK_VD         = 2,            ///< VD
    SC_CLK_DC0        = 3,            ///< MPEG/DC0
    SC_CLK_ADC_B      = 4,            ///< ADC_B

    SC_CLK_ODCLK      = 7,            ///< ODLCK
    SC_CLK_DC1        = 8,            ///< MPEG/DC1
    SC_CLK_ADC_C      = 9,            ///< ADC
    SC_CLK_ODCLK_B    = 10,           ///<ODCLK
    SC_CLK_HDMI_DVI_P2  = 11,           ///<DVI P2
    SC_CLK_HDMI_DVI_P3  = 12,           ///<DVI P3
    SC_CLK_HDMI_DVI_P1  = 13,           ///<DVI P1
    SC_CLK_MHL        = 13,           ///<MHL
} SC_IDCLK_TYPE;

typedef enum
{
    SC_OFFLINE_IPMUX_ADC_A      = 0,            ///< ADC A
    SC_OFFLINE_IPMUX_HDMI_DVI   = 1,            ///< DVI
    SC_OFFLINE_IPMUX_VD         = 2,            ///< VD
    SC_OFFLINE_IPMUX_MVOP       = 3,            ///< MPEG/DC0
    SC_OFFLINE_IPMUX_SC_VOP     = 4,            ///< Scaler VOP output
    SC_OFFLINE_IPMUX_EXT_VD     = 5,            ///< External VD
    SC_OFFLINE_IPMUX_ADC_B      = 6,            ///< ADC B
    SC_OFFLINE_IPMUX_CAPTURE    = 7,            ///< Capture
    SC_OFFLINE_IPMUX_MVOP2      = 8,            ///< MPEG/DC1
    SC_OFFLINE_IPMUX_IP_SUB     = 9,            ///< IP SUB/VE
    SC_OFFLINE_IPMUX_NOUSE      = 10,           ///< no use now
    SC_OFFLINE_IPMUX_DC2        = 11,           ///< DC2
    SC_OFFLINE_IPMUX_IP_SUB2    = 12,           ///< IP SUB2/DIP
    SC_OFFLINE_IPMUX_MHL        = 13,           ///< MHL
} SC_OFFLINE_IPMUX_TYPE;

typedef enum
{
    SC_DWIN_IPMUX_ADC_A      = 0,            ///< ADC A
    SC_DWIN_IPMUX_HDMI_DVI   = 1,            ///< DVI
    SC_DWIN_IPMUX_VD         = 2,            ///< VD
    SC_DWIN_IPMUX_MVOP       = 3,            ///< MPEG/DC0
    SC_DWIN_IPMUX_SC_VOP     = 4,            ///< Scaler VOP output
    SC_DWIN_IPMUX_EXT_VD     = 5,            ///< External VD
    SC_DWIN_IPMUX_ADC_B      = 6,            ///< ADC B
    SC_DWIN_IPMUX_MLINK      = 8,            ///< MLink
    SC_DWIN_IPMUX_CAPTURE    = 7,            ///< Capture
    SC_DWIN_IPMUX_MVOP2      = 8,            ///< MPEG/DC1
    SC_DWIN_IPMUX_IP_SUB     = 9,            ///< IP SUB/VE
    SC_DWIN_IPMUX_NOUSE      = 10,           ///< no use now
    SC_DWIN_IPMUX_DC2        = 11,           ///< DC2
    SC_DWIN_IPMUX_IP_SUB2    = 12,           ///< IP SUB2/DIP
    SC_DWIN_IPMUX_MHL        = 13,           ///< MHL
    SC_DWIN_IPMUX_VD2        = 14,           ///< VD2
} SC_DWIN_IPMUX_TYPE;

typedef enum
{
    SC2_MAINWIN_IPMUX_ADC_A      = 0,            ///< ADC A
    SC2_MAINWIN_IPMUX_HDMI_DVI   = 1,            ///< DVI
    SC2_MAINWIN_IPMUX_VD         = 2,            ///< VD
    SC2_MAINWIN_IPMUX_MVOP       = 3,            ///< MPEG/DC0

    SC2_MAINWIN_IPMUX_CAPTURE    = 7,            ///< Capture
    SC2_MAINWIN_IPMUX_MVOP2      = 8,            ///< MPEG/DC1

    SC2_MAINWIN_IPMUX_SPT4K_CH0  = 11,           ///< 4K spliter ch0

    SC2_MAINWIN_IPMUX_MHL        = 13,           ///< MHL
    SC2_MAINWIN_IPMUX_SPT4K_CH1  = 14,           ///< 4K spliter ch1
} SC2_MAINWIN_IPMUX_TYPE;

typedef enum
{
    SC2_CLK_ADC_A      = 0,            ///< ADC A
    SC2_CLK_HDMI_DVI   = 1,            ///< DVI
    SC2_CLK_HDMI_DVI_P0 = 1,            ///< DVI P0
    SC2_CLK_VD         = 2,            ///< VD
    SC2_CLK_DC0        = 3,            ///< MPEG/DC0
    SC2_CLK_ADC_B      = 4,            ///< ADC_B

    SC2_CLK_ODCLK      = 7,            ///< ODLCK
    SC2_CLK_DC1        = 8,            ///< MPEG/DC1
    SC2_CLK_ADC_C      = 9,            ///< ADC
    SC2_CLK_ODCLK_B    = 10,           ///<ODCLK
    SC2_CLK_HDMI_DVI_P2 = 11,           ///<DVI P2
    SC2_CLK_HDMI_DVI_P3 = 12,           ///<DVI P3
    SC2_CLK_HDMI_DVI_P1 = 13,           ///<DVI P1
    SC2_CLK_MHL        = 13,           ///<MHL
} SC2_IDCLK_TYPE;

typedef enum
{
    E_XC_INPUT_FSS_ADCA = 0,
    E_XC_INPUT_FSS_HDMI_P0,
    E_XC_INPUT_FSS_VD,
    E_XC_INPUT_FSS_MVOP0,
    E_XC_INPUT_FSS_HDMI_P1,
    E_XC_INPUT_FSS_MVOP1,
    E_XC_INPUT_FSS_ADC_OFFLINE,
    E_XC_INPUT_FSS_HDMI_P2,
    E_XC_INPUT_FSS_HDMI_P3,
    E_XC_INPUT_FSS_HDMI_420,
    E_XC_INPUT_FSS_MAX,
} EN_XC_INPUT_FSS_TYPE;

#define IsFSSSrcTypeHDMI(x) (((x)==E_XC_INPUT_FSS_HDMI_P0) || ((x)==E_XC_INPUT_FSS_HDMI_P1) || ((x)==E_XC_INPUT_FSS_HDMI_P2) || ((x)==E_XC_INPUT_FSS_HDMI_P3))
#define IsFSSSrcTypeMVOP(x) (((x)==E_XC_INPUT_FSS_MVOP0) || ((x)==E_XC_INPUT_FSS_MVOP1))
#define IsFSSDisableType(x) (FALSE)
#define Hal_SC_mux_set_adc_y_mux(args...)
#define Hal_SC_mux_set_adc_c_mux(args...)


void Hal_SC_mux_dispatch(void *pInstance, E_MUX_INPUTPORT src , E_MUX_OUTPUTPORT dest);
void Hal_SC_mux_set_dvi_mux(void *pInstance, MS_U8 PortId, E_OUTPUT_PORT_TYPE enDstPort);
void Hal_SC_set_sync_port_by_dataport(void *pInstance, E_MUX_INPUTPORT src_port );

void Hal_SC_mux_set_mainwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux);
MS_BOOL Hal_SC_mux_get_mainwin_ip_mux(void *pInstance, MS_U8 *pU8Data_Mux, MS_U8 *pU8Clk_Mux);
void Hal_SC_set_subwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux);
void Hal_SC_mux_set_dipwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux);
void Hal_SC_EnableCLK_for_DIP(void *pInstance, MS_BOOL bEnable);

void Hal_SC2_mux_set_mainwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux);
MS_BOOL Hal_SC2_mux_get_mainwin_ip_mux(void *pInstance, MS_U8 *pU8Data_Mux, MS_U8 *pU8Clk_Mux);
void Hal_SC_mux_SetScalerIndexInformationToADC(void *pInstance, MS_U8 u8ScalerIndex, MS_U16 u16InputSourceType);

MS_BOOL MHal_XC_IsFSSEnabled(void *pInstance, SCALER_WIN eWindow);
void MHal_XC_SetFSSEnable(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow);
EN_XC_INPUT_FSS_TYPE MHal_XC_GetFssSource(void *pInstance, SCALER_WIN eWindow);
void MHal_XC_SetFSSSource(void *pInstance, E_MUX_INPUTPORT enSrcPort, MS_BOOL bHDMI420);
EN_XC_INPUT_FSS_TYPE MHal_XC_GetFSSMuxPort(void *pInstance, E_INPUT_PORT_TYPE enSrcPort);
EN_XC_INPUT_FSS_TYPE MHal_XC_InputSrcToFssSrc(void *pInstance, INPUT_SOURCE_TYPE_t enInputSrcType);
INPUT_SOURCE_TYPE_t MHal_XC_FssSrcToInputSrc(void *pInstance, EN_XC_INPUT_FSS_TYPE enFssSrc);
void MHal_XC_SetDviMux(void *pInstance, MS_U8 PortId);
MS_U8 MHal_XC_GetDviMux(void);


#define MHal_XC_SetHfrMuxSel(args...)
#define MHal_XC_SetHfrIpClkEnable(args...)

#endif // MHAL_MUX_H
