/**  MediaTek Inc. (C) 2018. All rights reserved.**  Copyright Statement:**  This software/firmware and related
documentation ("MediaTek Software") are*  protected under relevant copyright laws. The information contained
herein is*  confidential and proprietary to MediaTek Inc. and/or its licensors. Without*  the prior written
permission of MediaTek inc. and/or its licensors, any*  reproduction, modification, use or disclosure of MediaTek
Software, and*  information contained herein, in whole or in part, shall be strictly*  prohibited.**  BY OPENING
THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES*  THAT THE SOFTWARE/FIRMWARE AND ITS
DOCUMENTATIONS ("MEDIATEK SOFTWARE")*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TORECEIVER*
ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL*  WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT
NOT LIMITED TO THE IMPLIED*  WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR*  NONINFRINGEMENT.
NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH*  RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY
BE USED BY,*  INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES*  TO LOOK ONLY TO SUCH
THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.*  RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE
RESPONSIBILITY TO*  OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK*  SOFTWARE. MEDIATEK
SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE*  RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM
TO A PARTICULAR*  STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S*  ENTIRE AND
CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE*  RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO
REVISE OR REPLACE THE*  MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE*  CHARGE PAID
BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.**  The following software/firmware and/or related
documentation ("MediaTek*  Software") have been modified by MediaTek Inc. All revisions are subject to*  any
receiver's applicable license agreements with MediaTek Inc.*/
#ifndef _PQ_CONTEXT_H_
#define _PQ_CONTEXT_H_

#ifdef __cplusplus
extern "C"
{
#endif

#if defined(_MDRV_PQ_C_)
#define INTERFACE
#else
#define INTERFACE extern
#endif

#include "apiXC.h"
#include "drvPQ.h"
#include "mdrv_xc_io.h"
#include "mdrv_xc_st.h"
//PQ define
//----------------------------------------------------------------
#define IsVBY1_16LANE(x)   (((x)== E_XC_PNL_LPLL_VBY1_10BIT_16LANE)||((x)== E_XC_PNL_LPLL_VBY1_8BIT_16LANE))
#define HVSP_XRULE_HSD        (0)
#define HVSP_XRULE_VSD        (1)
#define HVSP_XRULE_HSP        (2)
#define HVSP_XRULE_VSP        (3)

#define IS_HVSP_NONSTANDARD_RESOLUTION(HSize,Vsize)    (((HSize) > PQ_4K2K_MIN_H_SIZE) && ((Vsize) < PQ_4K2K_MIN_V_SIZE))

//----------------------------------------------------------------
//
//----------------------------------------------------------------
//PQ Debug Level
//----------------------------------------------------------------
#define PQ_DBG_OFF          (0x0000)
#define PQ_DBG_PQTAB        (0x0001) ///< Debug PQ Table
#define PQ_DBG_SRULE        (0x0002)///< Debug S RULE
#define PQ_DBG_CSCRULE      (0x0004)///< Debug CSC RULE
#define PQ_DBG_GRULE        (0x0008)///< Debug G RULE
#define PQ_DBG_BW           (0x0010)///< Debug BANDWIDTH
#define PQ_DBG_MADI         (0x0020)///< Debug MADI
#define PQ_DBG_INFO         (0x0040)///< Debug INFO
#define PQ_DBG_IOCTL        (0x0080)///< Debug MADI
#define PQ_DBG_P2P          (0x0100)///< Debug point to point
#define PQ_DBG_DELAYTIME    (0x0200)///< Debug delay time
#define PQ_DBG_ERROR        (0x0400)///< Debug Critical Error
#define PQ_DBG_HSY          (0x0800)///< Debug HSY Engine
#define PQ_DBG_HVSP         (0x1000)///< Debug for HVSP>
#define PQ_DBG_PQ_BIN       (0x2000)///< Debug PQ_Bin related
#define PQ_DBG_ALL          (0xFFFF)

#define PQMADi_DBG(x)   do { if( _u16PQDbgSwitch & PQ_DBG_MADI) x; } while(0);

#define PQ_INVALID_QMAP_INDEX    (0xFFFF)
#define PQ_4K2K_MIN_H_SIZE  (2096)
#define PQ_4K2K_MIN_V_SIZE  (1050)
#define PQ_IS_4K_INPUT(HSize,Vsize)  (((HSize) > PQ_4K2K_MIN_H_SIZE) && ((Vsize) >= PQ_4K2K_MIN_V_SIZE)) //Load 4k2k PQ mode if input is 4k2k or 4k1k.

INTERFACE stDS_PQ_REG DS_REG[DS_PQ_MAX_NUM];
INTERFACE MS_U16 DS_REG_CNT;

INTERFACE MS_U16 _u16PQDbgSwitch;
INTERFACE PQ_INPUT_SOURCE_TYPE _enInputSourceType[PQ_MAX_WINDOW];
INTERFACE MS_PQ_MuliMedia_Info _stMultiMedia_Info[PQ_MAX_WINDOW];
INTERFACE MS_U16 _gu16HVSPSramWriteCount;

#define HVSP_DISABLE_STAGE      (0)
#define HVSP_WRTIESRAM_STAGE    (1)
#define HVSP_BILINEAR           (0x0303)

#define PQ_LEVEL_PRINTF(_dbgSwitch_,_fmt, _args...)\
{\
    if( (_dbgSwitch_ & _u16PQDbgSwitch) != 0 )  \
    {\
        if (_dbgSwitch_ & PQ_DBG_ERROR)                \
        {\
            printf("[PQ] PQ_DBG_ERROR [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_P2P)\
        {\
            printf("[PQ] PQ_DBG_P2P [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_PQTAB)\
        {\
            printf("[PQ] PQ_DBG_PQTAB [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if (_dbgSwitch_ & PQ_DBG_SRULE)                \
        {\
            printf("[PQ] PQ_DBG_SRULE [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_CSCRULE)\
        {\
            printf("[PQ] PQ_DBG_CSCRULE [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_GRULE)\
        {\
            printf("[PQ] PQ_DBG_GRULE [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_BW)\
        {\
            printf("[PQ] PQ_DBG_BW [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_MADI)\
        {\
            printf("[PQ] PQ_DBG_MADI [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_INFO)\
        {\
            printf("[PQ] PQ_DBG_INFO [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_IOCTL)\
        {\
            printf("[PQ] PQ_DBG_IOCTL [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_DELAYTIME)\
        {\
            printf("[PQ] PQ_DBG_DELAYTIME [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_HSY)\
        {\
            printf("[PQ] PQ_DBG_HSY [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_HVSP)\
        {\
            printf("[PQ] PQ_DBG_HVSP [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else if(_dbgSwitch_ & PQ_DBG_PQ_BIN)\
        {\
            printf("[PQ] PQ_DBG_PQ_BIN [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
        else\
        {\
            printf("[PQ] XC_NOTDEFINE [%s,%d]: " _fmt, __FUNCTION__,__LINE__,##_args);  \
        }\
    }\
}

//----------------------------------------------------------------
//PQ Xrule Grule bypass
//----------------------------------------------------------------
INTERFACE MS_U16 _gu16PQDbgXRuleBypass;

#define PQ_DS_NO_BYPASS                 (0x0000)
#define PQ_MMDS_XRULE_BYPASS            (0x0001)
#define PQ_SPF_XRULE_BYPASS             (0x0002)
#define PQ_HVSP_XRULE_BYPASS            (0x0004)

typedef enum
{
    E_PQ_DS_BYPASS_TYPE_NONE = 0,
    E_PQ_MMDS_XRULE_BYPASS,
    E_PQ_SPF_XRULE_BYPASS,
    E_PQ_HVSP_XRULE_BYPASS,
}EN_PQ_DS_BYPASS_TYPE;

//----------------------------------------------------------------
//PQ Procfs Level
//----------------------------------------------------------------
typedef enum
{
    //[Assert]
    E_PQ_PROCFS_SEL_ASSERT_PANIC = 0,
    E_PQ_ASSERT_SEL_ASSERT_DUMPSTACK,

    E_PQ_PROCFS_SEL_MAX,
} EN_PQ_PROCFS_SEL;

//TRUE: Enable the memc fastplay play feature by procfs
INTERFACE MS_BOOL _u16PQProcfsFastPlayByMemc;

INTERFACE MS_U16 _u16PQAssertLevel;
#if defined(MSOS_TYPE_LINUX_KERNEL)
#define PQ_ASSERT(_bool_)\
{\
    if (_u16PQAssertLevel == E_PQ_ASSERT_SEL_ASSERT_DUMPSTACK)\
    {\
        dump_stack();\
    }\
    else if (_u16PQAssertLevel == E_PQ_PROCFS_SEL_ASSERT_PANIC)\
    {\
        MS_ASSERT(_bool_);\
    }\
    else\
    {\
        dump_stack();\
    }\
}
#else
#define PQ_ASSERT(_bool_)\
{\
    if (_u16PQAssertLevel == E_PQ_ASSERT_SEL_ASSERT_DUMPSTACK)\
    {\
        printf("[PQ] ASSERT [%s,%d]", __FUNCTION__, __LINE__);\
    }\
    else if (_u16PQAssertLevel == E_PQ_PROCFS_SEL_ASSERT_PANIC)\
    {\
        MS_ASSERT(_bool_);\
    }\
    else\
    {\
        printf("[PQ] ASSERT [%s,%d]", __FUNCTION__, __LINE__);\
    }\
}
#endif

//----------------------------------------------------------------
//Other
//----------------------------------------------------------------
#define PQ_NULL_POINTER(pPointer)\
{\
        if(pPointer == NULL)\
        {\
            PQ_LEVEL_PRINTF(PQ_DBG_ERROR,"[PQ] Null Pointer!!! \n");\
            return FALSE;\
        }\
}

#define PQ_FREQV_GATE_FOR_100I     (650) //Value is Freq*10.Freq V gate for 100i case. Freq V over 65hz frame lock would unlock.
#define PQ_PNL_INDEX_NULL (0)

#define ST_PQ_MADI_VR_INFO_VERSION (2)
typedef struct DLL_PACKED
{
    /// Structure version
    MS_U32  u32Version;
    /// Structure length
    MS_U32  u32Length;
    MS_U8* pu8BitsPerPixel;
    PQ_DEINTERLACE_MODE * peDeInterlaceMode;
    MS_U8* pu8FrameCount;
    MS_U8* pu8PQDelayCount;
    E_XC_FB_LEVEL* penFBLevel;
    MS_BOOL* pbOPWriteOffEnable;
    MS_U8 *pu8CmpBitsPerPixel;
} ST_PQ_MADI_VR_INFO;

#define ST_PQ_GET_IDX_AND_LOAD_TABLE_INFO_VERSION (1)
typedef struct DLL_PACKED
{
    /// Structure version
    MS_U32  u32Version;
    /// Structure length
    MS_U32  u32Length;
    PQ_WIN enWindow;
    MS_U16 u16IPIdx;
    PQ_ENGINE_TYPE enPQEngineType;
} ST_PQ_GET_IDX_AND_LOAD_TABLE_INFO;
#define ST_PQ_GET_MADI_VR_INFO_VERSION (3)
typedef struct DLL_PACKED
{
      /// Structure version
      MS_U32  u32Version;
      /// Structure length
      MS_U32  u32Length;
      PQ_WIN enWindow;
      MS_BOOL bMemFmt422;
      MS_U8 *pu8BitsPerPixel;
      PQ_DEINTERLACE_MODE *peDeInterlaceMode;
      MS_U8 *pu8FrameCount;
      MS_U8 *pu8CmpBitsPerPixel;
      MS_U16 u16IPIdx;
} ST_PQ_GET_MADI_VR_INFO;

typedef enum
{
    E_PQ_IP_MADI,
    E_PQ_IP_MADI_MOTION,
    E_PQ_IP_MADI_DFK,
    E_PQ_IP_MADI_SST,
    E_PQ_IP_MADI_FORCE,
    E_PQ_IP_SWDRIVER,
    E_PQ_IP_444TO422,
    E_PQ_IP_422TO444,
    E_PQ_IP_420CUP,
    E_PQ_IP_SRAM3,
    E_PQ_IP_SRAM4,
    E_PQ_IP_CSRAM3,
    E_PQ_IP_CSRAM4,
    E_PQ_IP_MEMFORMAT,
    E_PQ_IP_VD_SAMPLING_NO_COMM,
    E_PQ_IP_NUM,
} EN_PQ_IP;

typedef enum
{
    E_PQ_TABLE_IP_MADI_FORCE_YC_FULLMOTION,
    E_PQ_TABLE_IP_MADI_FORCE_YC_FULLSTILL,
    E_PQ_TABLE_IP_CSRAM3_C121,
    E_PQ_TABLE_IP_CSRAM3_C2121,
    E_PQ_TABLE_IP_CSRAM4_C121,
    E_PQ_TABLE_IP_CSRAM4_C2121,
    E_PQ_TABLE_IP_444TO422_ON,
    E_PQ_TABLE_IP_444TO422_OFF,
    E_PQ_TABLE_IP_422TO444_ON,
    E_PQ_TABLE_IP_422TO444_OFF,
    E_PQ_TABLE_IP_420CUP_ON,
    E_PQ_TABLE_IP_420CUP_OFF,
    E_PQ_TABLE_IP_NUM,
} EN_PQ_TABLE_IP;

typedef enum
{
    E_PQ_GRULE_IP_NR,
    E_PQ_GRULE_IP_OSD_BW,
    E_PQ_GRULE_IP_MPEG_NR,
    E_PQ_GRULE_IP_FILM_MODE,
    E_PQ_GRULE_IP_PTP,
    E_PQ_GRULE_IP_GAME_MODE,
    E_PQ_GRULE_IP_DS_PARAMETERS,
    E_PQ_GRULE_IP_HDR,
    E_PQ_GRULE_IP_DYNAMIC_CONTRAST,
    E_PQ_GRULE_IP_EDGE_ENHANCER,
    E_PQ_GRULE_IP_ABF,
    E_PQ_GRULE_IP_BWLE,
    E_PQ_GRULE_IP_NUM,
} EN_PQ_GRULE_IP;

typedef enum
{
    E_PQ_XRULE_IP_HSD,
    E_PQ_XRULE_IP_VSD,
    E_PQ_XRULE_IP_HSP,
    E_PQ_XRULE_IP_VSP,
    E_PQ_XRULE_IP_CSC,
    E_PQ_XRULE_IP_DB_NTSC,
    E_PQ_XRULE_IP_DB_PAL,
    E_PQ_XRULE_IP_MM_DS,
    E_PQ_XRULE_IP_SPF_DS,
    E_PQ_XRULE_IP_DLC_HISTOGRAM,
    E_PQ_XRULE_IP_DISABLE_UC,
    E_PQ_XRULE_IP_PQ_DS_LINEBUFFER,
    E_PQ_XRULE_IP_HVSP_DS,
    E_PQ_XRULE_IP_NUM,
} EN_PQ_XRULE_IP;


typedef struct DLL_PACKED
{
    EN_PQ_GRULE_TYPE enPQGruleType;
    EN_PQ_GRULE_IP enGruleIP;
    MS_U16 u16GRuleLevelIndex;
    PQ_WIN enSupportWindow;
    PQ_ENGINE_TYPE enEngineType;
    MS_BOOL bIsSkipDumpTalbe;
} ST_PQ_GRULE_TABLE;

typedef MS_BOOL (*PQ_GRULE_FUNCTION) (void* pInstance,PQ_WIN enWindow,ST_PQ_GRULE_TABLE *pstPQGruleTable);

typedef struct DLL_PACKED
{
    ST_PQ_GRULE_TABLE stPQGruleTable;
    PQ_GRULE_FUNCTION pfnPQ_GRULE_FUNCTION;
} ST_PQ_GRULE_INFO;

// PQ Function
typedef enum
{
    E_PQ_VR_INFO_RESOLUTION = 0,
    E_PQ_VR_INFO_COLOR_FORMAT,
    E_PQ_VR_INFO_SUB_SAMPLE,
    E_PQ_VR_INFO_SCANNING,
    E_PQ_VR_INFO_SOURCE_TYPE,
    E_PQ_VR_INFO_FRAME_RATE,
    E_PQ_VR_INFO_DIMENSION,
    E_PQ_VR_INFO_PRE_SCALING_HV,
    E_PQ_VR_INFO_POST_SCALING_HV,
    E_PQ_VR_INFO_FSC_HV,
    E_PQ_VR_INFO_WINDOW_ID,
    E_PQ_VR_INFO_TOTAL_WINDOW,
    E_PQ_VR_INFO_SRC_INDEX,
    E_PQ_VR_INFO_MADI_INDEX,
    E_PQ_VR_INFO_GRULE_DBG,
    E_PQ_VR_INFO_XRULE_DBG,
    E_PQ_VR_INFO_TMO_GRULE_DBG,
    E_PQ_VR_INFO_PQ_DELAY_TIME,
    E_PQ_VR_INFO_TYPE_NUMS,
}EN_PQ_VR_INFO_TYPE;

#define PQ_VR_DGB_GRULE_MAX (32)
#define PQ_VR_DGB_XRULE_MAX (16)
#define PQ_VR_DGB_TMO_XRULE_MAX (16)

#define ST_PQ_SET_VR_INFO_VERSION (1)
typedef struct DLL_PACKED
{
      /// Structure version
      MS_U32  u32Version;
      /// Structure length
      MS_U32  u32Length;
      EN_PQ_VR_INFO_TYPE enVRInfoType;
      PQ_WIN enWindow;
      void* pValue;
      MS_U16 u16RuleIndex;
} ST_PQ_SET_VR_INFO;

typedef enum
{
    E_PQ_HVSP_DS_1920_HDOWN_VDOWN,      // PQ_DS_HVSP_Settings_H1920_ScDown_V_ScDown_Main
    E_PQ_HVSP_DS_1920_HDOWN_V1X,        // PQ_DS_HVSP_Settings_H1920_ScDown_V_1X_Main
    E_PQ_HVSP_DS_1920_HDOWN_VUP,        // PQ_DS_HVSP_Settings_H1920_ScDown_V_ScUp_Main
    E_PQ_HVSP_DS_1920UP_HDOWN_VDOWN,    // PQ_DS_HVSP_Settings_H1920Up_ScDown_V_ScDown_Main
    E_PQ_HVSP_DS_1920UP_HDOWN_V1X,      // PQ_DS_HVSP_Settings_H1920Up_ScDown_V_1X_Main
    E_PQ_HVSP_DS_1920UP_HDOWN_VUP,      // PQ_DS_HVSP_Settings_H1920Up_ScDown_V_ScUp_Main
    E_PQ_HVSP_DS_1920_H1X_VDOWN,        // PQ_DS_HVSP_Settings_H1920_1X_V_ScDown_Main
    E_PQ_HVSP_DS_1920_H1X_V1X,          // PQ_DS_HVSP_Settings_H1920_1X_V_1X_Main
    E_PQ_HVSP_DS_1920_H1X_VUP,          // PQ_DS_HVSP_Settings_H1920_1X_V_ScUp_Main
    E_PQ_HVSP_DS_1920UP_H1X_VDOWN,      // PQ_DS_HVSP_Settings_H1920Up_1X_V_ScDown_Main
    E_PQ_HVSP_DS_1920UP_H1X_V1X,        // PQ_DS_HVSP_Settings_H1920Up_1X_V_1X_Main
    E_PQ_HVSP_DS_1920UP_H1X_VUP,        // PQ_DS_HVSP_Settings_H1920Up_1X_V_ScUp_Main
    E_PQ_HVSP_DS_1920_HUP_VDOWN,        // PQ_DS_HVSP_Settings_H1920_ScUp_V_ScDown_Main
    E_PQ_HVSP_DS_1920_HUP_V1X,          // PQ_DS_HVSP_Settings_H1920_ScUp_V_1X_Main
    E_PQ_HVSP_DS_1920_HUP_VUP,          // PQ_DS_HVSP_Settings_H1920_ScUp_V_ScUp_Main
    E_PQ_HVSP_DS_1920UP_HUP_VDOWN,      // PQ_DS_HVSP_Settings_H1920Up_ScUp_V_ScDown_Main
    E_PQ_HVSP_DS_1920UP_HUP_V1X,        // PQ_DS_HVSP_Settings_H1920Up_ScUp_V_1X_Main
    E_PQ_HVSP_DS_1920UP_HUP_VUP,        // PQ_DS_HVSP_Settings_H1920Up_ScUp_V_ScUp_Main
    E_PQ_HVSP_DS_NUM,
} EN_PQ_HVSP_DS_SETTING_IP;

MS_BOOL MDrv_PQ_GetIndexAndLoadTable(ST_PQ_GET_IDX_AND_LOAD_TABLE_INFO* pstPQGetIdxAndLoadTblInfo);
MS_BOOL MDrv_PQ_SetMADiVRInfo(ST_PQ_MADI_VR_INFO* pstPQMADiVRInfo);
MS_BOOL MDrv_PQ_GetBPPInfoFromMADiVR(ST_PQ_GET_MADI_VR_INFO* pstPQGetMADiVRInfo);
MS_BOOL MDrv_PQ_LoadControlPathTable(ST_PQ_GET_MADI_VR_INFO *pstPQGetMADiVRInfo);
MS_BOOL MDrv_PQ_SetSPFXruleSetting(ST_KDRV_XC_CFD_SPF_XRULE* pstXCCFDSPFXrule);
MS_BOOL MDrv_PQ_SetQMAPXruleData(void* pInstance, PQ_WIN enWindow, EN_PQ_QMAP_TYPE enQmapType);
MS_BOOL MDrv_PQ_IsFBLMadi(void* pInstance, PQ_WIN eWindow);


#define PQ_FILE_NAME_LENGTH 128
typedef struct
{
    MS_U32 u32MIPQBIN_Size;
    char MIPQBin_Path[PQ_FILE_NAME_LENGTH];
}PQ_MITEST_PRIVATE;

typedef struct
{
    MS_PHYADDR u32PQMITestBinAddr[MAX_PQ_BIN_NUM];
    MS_U32 u32TestBinSize[MAX_PQ_BIN_NUM];
}ST_PQ_MITESTBIN_PRIVATE;

typedef struct DLL_PACKED
{
    MS_U8 u8WRBankMappingNum;
    MS_U16 u16UCMFrameNum;
    MS_U16 u16UCMRWDiff;
    MS_BOOL bIsSupportZNR;
    EN_PQ_MFC_LEVEL enMfcLevel;
    PQ_INPUT_SOURCE_TYPE enSourceType;
    MS_BOOL bFRCEnabled;
}ST_PQ_GET_VIDEOTIME_INFO;

typedef struct DLL_PACKED
{
    PQ_WIN enWindow;
    MS_U8 u8FRCInteger;
    MS_U8 u8FRCDecimal;
    MS_U16 u16Input_vfreq;
    MS_U16 u16Output_vfreq;
    MS_BOOL bEnableGameMode;
}ST_PQ_GET_FRCRWDIFFCOUNT_INFO;

typedef struct DLL_PACKED
{
    MS_U16 u16LowerBound;
    MS_U16 u16HigherBound;
    MS_U8  u8GameModeCount;
    MS_U8  u8NormalModeCount;
}ST_PQ_FRCRWDIFFCOUNT_TBL;


MS_BOOL MDrv_PQ_SetBinInfo(MS_U32 PQBIN_Size, char *PQBin_Path, PQ_BIN_TYPE enPQBinType);
PQ_WIN MDrv_PQ_SCtoPQ_WinMapping(SCALER_WIN enWindow);
SCALER_WIN MDrv_PQ_PQtoSC_WinMapping(PQ_WIN enWindow);
MS_BOOL MDrv_PQ_SetProcfsLevel(EN_PQ_PROCFS_SEL enProcfs);
MS_BOOL MDrv_PQ_SetPQInfoToVR(ST_PQ_SET_VR_INFO stPQSetVRInfo);
MS_BOOL MDrv_PQ_LoadGameModeGrule(void* pInstance, PQ_WIN eWindow,MS_U16 u16GRuleLevelIndex);
MS_BOOL MDrv_PQ_SetFastPlaybyMemcDbg(MS_BOOL bEnable);
MS_U16 MDrv_PQ_GetTMOGRule_LevelIndex(void* pInstance, MS_U16 u16GRuleType, MS_U16 u16TMOGRuleLevelIndex);
#ifdef __cplusplus
}
#endif

#endif /* _DRVPQ_DATATYPES_H_ */
