//<MStar Software>
//******************************************************************************
// MStar Software
// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
// All software, firmware and related documentation herein ("MStar Software") are
// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
// law, including, but not limited to, copyright law and international treaties.
// Any use, modification, reproduction, retransmission, or republication of all
// or part of MStar Software is expressly prohibited, unless prior written
// permission has been granted by MStar.
//
// By accessing, browsing and/or using MStar Software, you acknowledge that you
// have read, understood, and agree, to be bound by below terms ("Terms") and to
// comply with all applicable laws and regulations:
//
// 1. MStar shall retain any and all right, ownership and interest to MStar
//    Software and any modification/derivatives thereof.
//    No right, ownership, or interest to MStar Software and any
//    modification/derivatives thereof is transferred to you under Terms.
//
// 2. You understand that MStar Software might include, incorporate or be
//    supplied together with third party`s software and the use of MStar
//    Software may require additional licenses from third parties.
//    Therefore, you hereby agree it is your sole responsibility to separately
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// 4. MStar Software is provided on an "AS IS" basis without warranties of any
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// 7. These terms shall be governed by and construed in accordance with the laws
//    of Taiwan, R.O.C., excluding its conflict of law rules.
//    Any and all dispute arising out hereof or related hereto shall be finally
//    settled by arbitration referred to the Chinese Arbitration Association,
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//    The arbitration award shall be final and binding to both parties.
//
//******************************************************************************
//<MStar Software>

#ifndef _REG_MIU_H_
#define _REG_MIU_H_

//-------------------------------------------------------------------------------------------------
//  Hardware Capability
//-------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
#define BITS_RANGE(range)                       (BIT(((1)?range)+1) - BIT((0)?range))
#define BITS_RANGE_VAL(x, range)                (((x) & BITS_RANGE(range)) >> ((0)?range))

#define MIU_REG_BASE                            (0x1200UL)
#define MIU1_REG_BASE                           (0x0600UL)
#define MIU2_REG_BASE                           (0x62000UL)
#define MIU_ARB_REG_BASE                        (0x61500UL)    //MIU0, Group 4~7
#define MIU1_ARB_REG_BASE                       (0x62200UL)    //MIU1, Group 4~7
#define MIU2_ARB_REG_BASE                       (0x62300UL)    //MIU2, Group 4~7
#define MIU_ARBB_REG_BASE                       (0x052000UL)
#define MIU1_ARBB_REG_BASE                      (0x052100UL)
#define MIU_DIG_REG_BASE                        (0x052B00UL)
#define MIU1_DIG_REG_BASE                       (0x052C00UL)
#define MIU_PROTECT_BASE                        (0x01A00UL)  //0x301A00UL
#define MIU1_PROTECT_BASE                       (0x01B00UL)  //0x301B00UL
#define MIU_BLOCK_ARBITER_GP1                   (0x10200UL)
#define MIU_BLOCK_ARBITER_GP2                   (0x10300UL)
#define MIU_BLOCK_ARBITER_GP3                   (0x10400UL)
#define MIU_BLOCK_ARBITER_GP4                   (0x10500UL)
#define MIU_BLOCK_ARBITER_GP5                   (0x10600UL)
#define MIU_BLOCK_ARBITER_GP6                   (0x10700UL)
#define MIU_BLOCK_ARBITER_GP7                   (0x10800UL)
#define MIU_BLOCK_ARBITER_GP8                   (0x10900UL)
#define MIU_DIG_E                               (0x52B00UL)

#define PM_REG_BASE                             (0x1E00UL)
#define MIU_ATOP_BASE                           (0x10D00UL)
#define MIU1_ATOP_BASE                          (0x61600UL)
#define MIU2_ATOP_BASE                          (0x62100UL)
#define CHIP_TOP_BASE                           (0x1E00UL)

#define PM_CHIP_REVISION                        (PM_REG_BASE + 0x03)    //0x001E03
//#define DDR_FREQ_SET_0                        (MIU_REG_BASE + 0x20)   //0x101220
//#define DDR_FREQ_SET_1                        (MIU_REG_BASE + 0x21)   //0x101221
//#define DDR_FREQ_DIV_1                        (MIU_REG_BASE + 0x25)   //0x101225
//#define DDR_FREQ_INPUT_DIV_2                  (MIU_REG_BASE + 0x26)   //0x101226
//#define DDR_FREQ_LOOP_DIV_2                   (MIU_REG_BASE + 0x27)   //0x101227
//#define DDR_CLK_SELECT                        (MIU_REG_BASE + 0x3e)   //0x10123E
//#define DDR_FREQ_STATUS                       (MIU_REG_BASE + 0x3f)   //0x10123F

//#define MIU_RQ_MASK_NUM                         (0x4)
#define MIU_RQ0L_MASK                           (MIU_REG_BASE + 0x46)
#define MIU_RQ0H_MASK                           (MIU_REG_BASE + 0x47)
#define MIU_RQ1L_MASK                           (MIU_REG_BASE + 0x66)
#define MIU_RQ1H_MASK                           (MIU_REG_BASE + 0x67)
#define MIU_RQ2L_MASK                           (MIU_REG_BASE + 0x86)
#define MIU_RQ2H_MASK                           (MIU_REG_BASE + 0x87)
//group number is set from group1, so need to minuse 1 to get the register base from group1
#define REG_MIU_RQX_MASK(x)                     (0x06UL + 0x100UL * ((x)-1))
#define REG_MIU_RQX_HPMASK(x)                   (0x08UL + 0x100UL * ((x)-1))

#define MIU_PROTECT_EN                          (MIU_PROTECT_BASE)
#define MIU_PROTECT_DDR_SIZE                    (MIU_REG_BASE + 0xD3)
#define MIU_PROTECT_DDR_BOUND                   (MIU_PROTECT_BASE+0xC6)
//#define MIU_PROTECT_DDR_SIZE_MASK             BITS_RANGE(11:8)
#define MIU_PROTECT_DDR_32MB                    (0x50)
#define MIU_PROTECT_DDR_64MB                    (0x60)
#define MIU_PROTECT_DDR_128MB                   (0x70)
#define MIU_PROTECT_DDR_256MB                   (0x80)
#define MIU_PROTECT_DDR_512MB                   (0x90)
#define MIU_PROTECT_DDR_1024MB                  (0xA0)
#define MIU_PROTECT_DDR_2048MB                  (0xB0)
#define MIU_PROTECT_DDR_4096MB                  (0xC0)
#define MIU_PROTECT_DDR_8192MB                  (0xD0)
#define MIU_PROTECT_DDR_32MB_BOUND              (0x1FFF)
#define MIU_PROTECT_DDR_64MB_BOUND              (0x3FFF)
#define MIU_PROTECT_DDR_128MB_BOUND             (0x7FFF)
#define MIU_PROTECT_DDR_256MB_BOUND             (0xFFFF)
#define MIU_PROTECT_DDR_384MB_BOUND             (0x17FFF)
#define MIU_PROTECT_DDR_512MB_BOUND             (0x1FFFF)
#define MIU_PROTECT_DDR_768MB_BOUND             (0x2FFFF)
#define MIU_PROTECT_DDR_1024MB_BOUND            (0x3FFFF)
#define MIU_PROTECT_DDR_1280MB_BOUND            (0x4FFFF)
#define MIU_PROTECT_DDR_1536MB_BOUND            (0x5FFFF)
#define MIU_PROTECT_DDR_1792MB_BOUND            (0x6FFFF)
#define MIU_PROTECT_DDR_2048MB_BOUND            (0x7FFFF)
#define MIU_PROTECT_DDR_2304MB_BOUND            (0x8FFFF)
#define MIU_PROTECT_DDR_2560MB_BOUND            (0x9FFFF)
#define MIU_PROTECT_DDR_2816MB_BOUND            (0xAFFFF)
#define MIU_PROTECT_DDR_3072MB_BOUND            (0xBFFFF)
#define MIU_PROTECT_DDR_3328MB_BOUND            (0xCFFFF)
#define MIU_PROTECT_DDR_3584MB_BOUND            (0xDFFFF)
#define MIU_PROTECT_DDR_3840MB_BOUND            (0xEFFFF)
#define MIU_PROTECT_DDR_4096MB_BOUND            (0xFFFFF)
#define MIU_PROTECT_32MB_ADDR                   (32*0x100000ULL)
#define MIU_PROTECT_64MB_ADDR                   (64*0x100000ULL)
#define MIU_PROTECT_128MB_ADDR                  (128*0x100000ULL)
#define MIU_PROTECT_256MB_ADDR                  (256*0x100000ULL)
#define MIU_PROTECT_512MB_ADDR                  (512*0x100000ULL)
#define MIU_PROTECT_1024MB_ADDR                 (1024*0x100000ULL)
#define MIU_PROTECT_2048MB_ADDR                 (2048*0x100000ULL)
#define MIU_PROTECT_4096MB_ADDR                 (4096*0x100000ULL)
#define MIU_PROTECT_8192MB_ADDR                 (8192*0x100000ULL)

#define MIU_PROTECT0_ID0                        (MIU_PROTECT_BASE+0xA0)
#define MIU_PROTECT0_GROUP1_ID0                 (MIU_PROTECT_BASE+0xB0)
#define MIU_PROTECT_GROUP_SEL                   (MIU_PROTECT_BASE+0x0C)
#define MIU_BW_REQUEST                          (MIU_REG_BASE+0x1A)
#define MIU_BW_REQUESTH                         (MIU_REG_BASE+0x2A)
#define MIU_BW_RESULT                           (MIU_REG_BASE+0x1C)
#define MIU_BW_STATUS                           (MIU_REG_BASE+0x52)
#define MIU_PROTECT0_ID_ENABLE                  (MIU_PROTECT_BASE+0x80)
#define MIU_PROTECT1_ID_ENABLE                  (MIU_PROTECT_BASE+0x82)
#define MIU_PROTECT2_ID_ENABLE                  (MIU_PROTECT_BASE+0x84)
#define MIU_PROTECT3_ID_ENABLE                  (MIU_PROTECT_BASE+0x86)
#define MIU_PROTECT4_ID_ENABLE                  (MIU_PROTECT_BASE+0x88)
#define MIU_PROTECT5_ID_ENABLE                  (MIU_PROTECT_BASE+0x8A)
#define MIU_PROTECT6_ID_ENABLE                  (MIU_PROTECT_BASE+0x8C)
#define MIU_PROTECT7_ID_ENABLE                  (MIU_PROTECT_BASE+0x8E)
#define MIU_PROTECT0_START                      (MIU_PROTECT_BASE+0x20)
#define MIU_PROTECT1_START                      (MIU_PROTECT_BASE+0x28)
#define MIU_PROTECT2_START                      (MIU_PROTECT_BASE+0x30)
#define MIU_PROTECT3_START                      (MIU_PROTECT_BASE+0x38)
#define MIU_PROTECT4_START                      (MIU_PROTECT_BASE+0x40)
#define MIU_PROTECT5_START                      (MIU_PROTECT_BASE+0x48)
#define MIU_PROTECT6_START                      (MIU_PROTECT_BASE+0x50)
#define MIU_PROTECT7_START                      (MIU_PROTECT_BASE+0x58)
#define REG_MIU_PROTECT_LOADDR                  (0x70 << 1)	//0xE0
#define REG_MIU_PROTECT_HIADDR                  (0x71 << 1)	//0xE2
#define REG_MIU_PROTECT_BLOCK                   (0x7E << 1)     //0xFC
#define REG_MIU_PROTECT_STATUS                  (0x7F << 1)	//0xFE

#define REG_MIU_DDR_STATUS                      (MIU_ARB_REG_BASE+0x66)
#define REG_MIU_CPU_HIGHWAY_TYPE                (MIU_ARB_REG_BASE+0x86)
#define REG_MIU_CPU_HIGHWAY_ENABLE              (MIU_ARBB_REG_BASE+0x60)
#define REG_MIU_CPU_SCOPE_0_START               (MIU_ARBB_REG_BASE+0x68)
#define REG_MIU_CPU_SCOPE_0_END                 (MIU_ARBB_REG_BASE+0x6A)
#define REG_MIU_CPU_SCOPE_0_START_H             (MIU_ARBB_REG_BASE+0x62)
#define REG_MIU_CPU_SCOPE_0_END_H               (MIU_ARBB_REG_BASE+0x63)
#define REG_MIU_CPU_SCOPE_1_START               (MIU_ARBB_REG_BASE+0x6C)
#define REG_MIU_CPU_SCOPE_1_END                 (MIU_ARBB_REG_BASE+0x6E)
#define REG_MIU_CPU_SCOPE_1_START_H             (MIU_ARBB_REG_BASE+0x64)
#define REG_MIU_CPU_SCOPE_1_END_H               (MIU_ARBB_REG_BASE+0x65)
#define REG_MIU_CPU_SCOPE_2_START               (MIU_ARBB_REG_BASE+0x70)
#define REG_MIU_CPU_SCOPE_2_END                 (MIU_ARBB_REG_BASE+0x72)
#define REG_MIU_CPU_SCOPE_2_START_H             (MIU_ARBB_REG_BASE+0x66)
#define REG_MIU_CPU_SCOPE_2_END_H               (MIU_ARBB_REG_BASE+0x67)

#define REG_MIU_SIZE_CONFIG                     (MIU_DIG_E+0x26)

// MIU selection registers
#define REG_MIU_SEL0                            (MIU_REG_BASE + 0xf0)  //0x12F0
#define REG_MIU_SEL1                            (MIU_REG_BASE + 0xf2)  //0x12F1
#define REG_MIU_SEL2                            (MIU_REG_BASE + 0xf4)  //0x12F2
#define REG_MIU_SEL3                            (MIU_REG_BASE + 0xf6)  //0x12F3
#define REG_MIU_SELX(x)                         (0xF0 + (x) * 2)

//MIU1
#define MIU1_BW_REQUEST                         (MIU1_REG_BASE + 0x1A)
#define MIU1_BW_REQUESTH                         (MIU1_REG_BASE+0x2A)
#define MIU1_BW_RESULT                          (MIU1_REG_BASE + 0x1C)
#define MIU1_REG_RESERVED_3F                    (MIU1_REG_BASE+0x7E)
#define MIU1_BW_STATUS                           (MIU1_REG_BASE+0x52)

#define MIU1_PROTECT_EN                          (MIU1_PROTECT_BASE)
#define MIU1_PROTECT_DDR_SIZE                    (MIU1_REG_BASE+0xD3)
#define MIU1_PROTECT_DDR_BOUND                   (MIU1_PROTECT_BASE+0xC6)
#define MIU1_PROTECT0_ID0                        (MIU1_PROTECT_BASE+0xA0)
#define MIU1_PROTECT0_GROUP1_ID0                 (MIU1_PROTECT_BASE+0xB0)
#define MIU1_PROTECT_GROUP_SEL                   (MIU1_PROTECT_BASE+0x0C)
#define MIU1_PROTECT0_ID_ENABLE                  (MIU1_PROTECT_BASE+0x80)
#define MIU1_PROTECT1_ID_ENABLE                  (MIU1_PROTECT_BASE+0x82)
#define MIU1_PROTECT2_ID_ENABLE                  (MIU1_PROTECT_BASE+0x84)
#define MIU1_PROTECT3_ID_ENABLE                  (MIU1_PROTECT_BASE+0x86)
#define MIU1_PROTECT4_ID_ENABLE                  (MIU1_PROTECT_BASE+0x88)
#define MIU1_PROTECT5_ID_ENABLE                  (MIU1_PROTECT_BASE+0x8A)
#define MIU1_PROTECT6_ID_ENABLE                  (MIU1_PROTECT_BASE+0x8C)
#define MIU1_PROTECT7_ID_ENABLE                  (MIU1_PROTECT_BASE+0x8E)
#define MIU1_PROTECT0_START                      (MIU1_PROTECT_BASE+0x20)
#define MIU1_PROTECT1_START                      (MIU1_PROTECT_BASE+0x28)
#define MIU1_PROTECT2_START                      (MIU1_PROTECT_BASE+0x30)
#define MIU1_PROTECT3_START                      (MIU1_PROTECT_BASE+0x38)
#define MIU1_PROTECT4_START                      (MIU1_PROTECT_BASE+0x40)
#define MIU1_PROTECT5_START                      (MIU1_PROTECT_BASE+0x48)
#define MIU1_PROTECT6_START                      (MIU1_PROTECT_BASE+0x50)
#define MIU1_PROTECT7_START                      (MIU1_PROTECT_BASE+0x58)

#define REG_MIU1_DDR_STATUS                      (MIU1_ARB_REG_BASE+0x66)

#define REG_MIU_I64_MODE                         (BIT7)
#define REG_MIU_INIT_DONE                        (BIT15)
#define REG_MIU_DDR4 (BIT3)

//Protection Status
#define REG_MIU_PROTECT_LOG_CLR                 (BIT0)
#define REG_MIU_PROTECT_IRQ_MASK                (BIT1)
#define REG_MIU_PROTECT_HIT_FALG                (BIT4)
#define REG_MIU_PROTECT_HIT_ID                  15:8
#define REG_MIU_PROTECT_HIT_NO                  3:0

// MIU Scramble
#define REG_MIU_SCRAMBLE_EN                     (MIU_REG_BASE + 0x06)

//MIU Bus Width
#define REG_MI64_FORCE                          (CHIP_TOP_BASE + 0x40)

#define REG_MIU_DRAM_BUS                        (MIU_DIG_REG_BASE + 0x21)
#define REG_MIU1_DRAM_BUS                       (MIU1_DIG_REG_BASE + 0x21)
#define REG_MIU_DRAM_CHANNEL                    (MIU_DIG_REG_BASE + 0x26)

//MIU Data Ratio
#define REG_MIU_DATA_RATIO                      (MIU_REG_BASE + 0x03)
#define REG_MIU1_DATA_RATIO                     (MIU1_REG_BASE + 0x03)

//MIU Dram Frequency
#define REG_MIU_DRAM_FREQ                       (MIU_ATOP_BASE + 0x32)
#define REG_MIU1_DRAM_FREQ                      (MIU1_ATOP_BASE + 0x32)

//MIU Bandwidth Monitor
#define MIU_BW_MONITOR_SEL                      (MIU_DIG_REG_BASE+0xE4)
#define MIU_BW_MONITOR_WRI_ID                   (MIU_DIG_REG_BASE+0xE5)
#define MIU_BW_MONITOR_WRI_EN                   (MIU_DIG_REG_BASE+0xE6)
#define MIU_BW_MONITOR_READ                     (MIU_DIG_REG_BASE+0xE7)
#define MIU_BW_MONITOR_MPLL_PERIOD              (MIU_DIG_REG_BASE+0x7E)
#define MIU_BW_MONITOR0                         (MIU_DIG_REG_BASE+0xE8)
#define MIU_BW_MONITOR1                         (MIU_DIG_REG_BASE+0xEA)
#define MIU_BW_MONITOR2                         (MIU_DIG_REG_BASE+0xEC)
#define MIU_BW_MONITOR3                         (MIU_DIG_REG_BASE+0xEE)
#define MIU_BW_MONITOR4                         (MIU_DIG_REG_BASE+0xF0)
#define MIU_BW_MONITOR5                         (MIU_DIG_REG_BASE+0xF2)
#define MIU_BW_MONITOR6                         (MIU_DIG_REG_BASE+0xF4)
#define MIU_BW_MONITOR7                         (MIU_DIG_REG_BASE+0xF6)

#define MIU1_BW_MONITOR_SEL                     (MIU1_DIG_REG_BASE+0xE4)
#define MIU1_BW_MONITOR_WRI_ID                  (MIU1_DIG_REG_BASE+0xE5)
#define MIU1_BW_MONITOR_WRI_EN                  (MIU1_DIG_REG_BASE+0xE6)
#define MIU1_BW_MONITOR_READ                    (MIU1_DIG_REG_BASE+0xE7)
#define MIU1_BW_MONITOR0                        (MIU1_DIG_REG_BASE+0xE8)
#define MIU1_BW_MONITOR1                        (MIU1_DIG_REG_BASE+0xEA)
#define MIU1_BW_MONITOR2                        (MIU1_DIG_REG_BASE+0xEC)
#define MIU1_BW_MONITOR3                        (MIU1_DIG_REG_BASE+0xEE)
#define MIU1_BW_MONITOR4                        (MIU1_DIG_REG_BASE+0xF0)
#define MIU1_BW_MONITOR5                        (MIU1_DIG_REG_BASE+0xF2)
#define MIU1_BW_MONITOR6                        (MIU1_DIG_REG_BASE+0xF4)
#define MIU1_BW_MONITOR7                        (MIU1_DIG_REG_BASE+0xF6)

//MIU UMA Mode
#define REG_MIU_ASYM_UMA_MODE                   (MIU_DIG_REG_BASE+0x26)
#define REG_MIU_UMA_MODE                        (MIU_DIG_REG_BASE+0x27)

//-------------------------------------------------------------------------------------------------
//MAU
//
//-------------------------------------------------------------------------------------------------
#define RIUBASE_MAU0                            0x1840UL
#define RIUBASE_MAU1                            0x1860UL


//-------------------------------------------------------------------------------------------------
//  MIU ATOP registers
//-------------------------------------------------------------------------------------------------
#define MIU_DDFSTEP                             (0x28)//0x110D28
#define MIU_SSC_EN                              (0x29)//0x110D29
#define MIU_DDFSPAN                             (0x2A)//0x110D2A
#define MIU_DDFSET                              (0x30)
//#define MIU_PLL_INPUT_DIV_2ND                 (0x34) // no this reg in Einstein
#define MIU_PLL_LOOP_DIV_2ND                    (0x34)
//xxx_div_first
#define MIU_PLLCTRL                             (0x36)
#define MIU_DDRPLL_DIV_FIRST                    (0x37)
#define MIU_DDR_PHASE_ERR_CHECK                 (0xF4)

//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------


#endif // _REG_MIU_H_

