// SPDX-License-Identifier: GPL-2.0+
/*------------------------------------------------------------------------------
 * MediaTek Inc. (C) 2018. All rights reserved.
 *
 * Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein is
 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
 * the prior written permission of MediaTek inc. and/or its licensors, any
 * reproduction, modification, use or disclosure of MediaTek Software, and
 * information contained herein, in whole or in part, shall be strictly
 * prohibited.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 *
 * The following software/firmware and/or related documentation ("MediaTek
 * Software") have been modified by MediaTek Inc. All revisions are subject to
 * any receiver's applicable license agreements with MediaTek Inc.
 *----------------------------------------------------------------------------*/

#ifndef _DT_BINDINGS_MT5896_GPIO_H
#define _DT_BINDINGS_MT5896_GPIO_H

#define PAD_DDCA_CK     1
#define PAD_DDCA_DA     2
#define PAD_IRIN        3
#define PAD_PWM_PM      4
#define PAD_CEC0        5
#define PAD_GPIO0_PM    6
#define PAD_GPIO1_PM    7
#define PAD_GPIO2_PM    8
#define PAD_USB_CTRL    9
#define PAD_GPIO5_PM    10
#define PAD_GPIO6_PM    11
#define PAD_GPIO7_PM    12
#define PAD_GPIO8_PM    13
#define PAD_GPIO9_PM    14
#define PAD_GPIO10_PM   15
#define PAD_GPIO11_PM   16
#define PAD_GPIO12_PM   17
#define PAD_GPIO13_PM   18
#define PAD_GPIO14_PM   19
#define PAD_GPIO15_PM   20
#define PAD_GPIO16_PM   21
#define PAD_GPIO17_PM   22
#define PAD_GPIO18_PM   23
#define PAD_GPIO19_PM   24
#define PAD_GPIO20_PM   25
#define PAD_GPIO21_PM   26
#define PAD_GPIO22_PM   27
#define PAD_GPIO23_PM   28
#define PAD_GPIO24_PM   29
#define PAD_GPIO25_PM   30
#define PAD_GPIO26_PM   31
#define PAD_GPIO27_PM   32
#define PAD_GPIO28_PM   33
#define PAD_DDCDA_CK    34
#define PAD_DDCDA_DA    35
#define PAD_DDCDB_CK    36
#define PAD_DDCDB_DA    37
#define PAD_DDCDC_CK    38
#define PAD_DDCDC_DA    39
#define PAD_DDCDD_CK    40
#define PAD_DDCDD_DA    41
#define PAD_SAR0        42
#define PAD_SAR1        43
#define PAD_SAR2        44
#define PAD_SAR3        45
#define PAD_SAR4        46
#define PAD_VPLUGIN     47
#define PAD_SAR6        48
#define PAD_SAR7        49
#define PAD_VID0        50
#define PAD_VID1        51
#define PAD_VID2        52
#define PAD_WOL_INT_OUT 53
#define PAD_DDCR_CK     54
#define PAD_DDCR_DA     55
#define PAD_DIM0        56
#define PAD_DIM1        57
#define PAD_DIM2        58
#define PAD_DIM3        59
#define PAD_GPIO0       60
#define PAD_GPIO1       61
#define PAD_GPIO8       62
#define PAD_GPIO9       63
#define PAD_GPIO10      64
#define PAD_GPIO11      65
#define PAD_GPIO12      66
#define PAD_GPIO13      67
#define PAD_GPIO14      68
#define PAD_GPIO15      69
#define PAD_GPIO16      70
#define PAD_GPIO17      71
#define PAD_GPIO18      72
#define PAD_I2S_IN_BCK  73
#define PAD_I2S_IN_DIN0 74
#define PAD_I2S_IN_DIN1 75
#define PAD_I2S_IN_DIN2 76
#define PAD_I2S_IN_WCK  77
#define PAD_I2S_OUT_BCK 78
#define PAD_I2S_OUT_MCK 79
#define PAD_I2S_OUT_SD0 80
#define PAD_I2S_OUT_SD1 81
#define PAD_I2S_OUT_SD2 82
#define PAD_I2S_OUT_WCK 83
#define PAD_LD_SPI_CK   84
#define PAD_LD_SPI_CS   85
#define PAD_LD_SPI_MISO 86
#define PAD_LD_SPI_MOSI 87
#define PAD_MIC_BCK     88
#define PAD_MIC_SD0     89
#define PAD_MIC_SD1     90
#define PAD_MIC_SD2     91
#define PAD_PCM2_CD_N   92
#define PAD_PCM2_CE_N   93
#define PAD_PCM2_IRQA_N 94
#define PAD_PCM2_RESET  95
#define PAD_PCM2_WAIT_N 96
#define PAD_PCM_A0      97
#define PAD_PCM_A1      98
#define PAD_PCM_A2      99
#define PAD_PCM_A3      100
#define PAD_PCM_A4      101
#define PAD_PCM_A5      102
#define PAD_PCM_A6      103
#define PAD_PCM_A7      104
#define PAD_PCM_A8      105
#define PAD_PCM_A9      106
#define PAD_PCM_A10     107
#define PAD_PCM_A11     108
#define PAD_PCM_A12     109
#define PAD_PCM_A13     110
#define PAD_PCM_A14     111
#define PAD_PCM_CD_N    112
#define PAD_PCM_CE_N    113
#define PAD_PCM_D0      114
#define PAD_PCM_D1      115
#define PAD_PCM_D2      116
#define PAD_PCM_D3      117
#define PAD_PCM_D4      118
#define PAD_PCM_D5      119
#define PAD_PCM_D6      120
#define PAD_PCM_D7      121
#define PAD_PCM_IORD_N  122
#define PAD_PCM_IOWR_N  123
#define PAD_PCM_IRQA_N  124
#define PAD_PCM_OE_N    125
#define PAD_PCM_REG_N   126
#define PAD_PCM_RESET   127
#define PAD_PCM_WAIT_N  128
#define PAD_PCM_WE_N    129
#define PAD_PWM0        130
#define PAD_PWM1        131
#define PAD_PWM2        132
#define PAD_SPDIF_IN    133
#define PAD_SPDIF_OUT   134
#define PAD_TCON0       135
#define PAD_TCON1       136
#define PAD_TCON2       137
#define PAD_TCON3       138
#define PAD_TCON4       139
#define PAD_TGPIO0      140
#define PAD_TGPIO1      141
#define PAD_TGPIO2      142
#define PAD_TGPIO3      143
#define PAD_TS0_CLK     144
#define PAD_TS0_D0      145
#define PAD_TS0_D1      146
#define PAD_TS0_D2      147
#define PAD_TS0_D3      148
#define PAD_TS0_D4      149
#define PAD_TS0_D5      150
#define PAD_TS0_D6      151
#define PAD_TS0_D7      152
#define PAD_TS0_SYNC    153
#define PAD_TS0_VLD     154
#define PAD_TS1_CLK     155
#define PAD_TS1_D0      156
#define PAD_TS1_D1      157
#define PAD_TS1_D2      158
#define PAD_TS1_D3      159
#define PAD_TS1_D4      160
#define PAD_TS1_D5      161
#define PAD_TS1_D6      162
#define PAD_TS1_D7      163
#define PAD_TS1_SYNC    164
#define PAD_TS1_VLD     165
#define PAD_TS2_CLK     166
#define PAD_TS2_D0      167
#define PAD_TS2_D1      168
#define PAD_TS2_D2      169
#define PAD_TS2_D3      170
#define PAD_TS2_D4      171
#define PAD_TS2_D5      172
#define PAD_TS2_D6      173
#define PAD_TS2_D7      174
#define PAD_TS2_SYNC    175
#define PAD_TS2_VLD     176
#define PAD_TS3_CLK     177
#define PAD_TS3_D0      178
#define PAD_TS3_SYNC    179
#define PAD_TS3_VLD     180
#define PAD_HDMIRX_ARCTX 181
#define PAD_TS3_D1      292
#define PAD_TS3_D2      293
#define PAD_TS3_D3      294
#define PAD_TS3_D4      295
#define PAD_TS3_D5      296
#define PAD_TS3_D6      297
#define PAD_TS3_D7      298
#define PAD_TCON5       299
#define PAD_TCON6       300
#define PAD_TCON7       301
#define PAD_TCON8       302
#define PAD_GPIO29_PM   303
#define PAD_GPIO30_PM   304
#define PAD_GPIO31_PM   305

/* analog gpio */
/*
#define PADA_RIN0P      182
#define PADA_RIN1P      183
#define PADA_GIN0P      184
#define PADA_GIN1P      185
#define PADA_GIN0M      186
#define PADA_GIN1M      187
#define PADA_BIN0P      188
#define PADA_BIN1P      189
#define PADA_HSYNC0     190
#define PADA_VSYNC0     191
*/

#endif /* _DT_BINDINGS_MT5896_GPIO_H */
