#define GOP2_BKA4E8 0x0149D000

//Page GOP2_BKA4E8
#define REG_0004_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x004)
    #define REG_0004_GOP2_BKA4E8_REG_GOP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_GOP2_BKA4E8_REG_GOP_AFBC_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0004_GOP2_BKA4E8_REG_MIRROR_V Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0004_GOP2_BKA4E8_REG_DATA_FMT Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0004_GOP2_BKA4E8_REG_UV_SWAP Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0004_GOP2_BKA4E8_REG_YC_SWAP Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0004_GOP2_BKA4E8_REG_AD_SWAP Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0004_GOP2_BKA4E8_REG_AFBC_YUV_TRANS Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0004_GOP2_BKA4E8_REG_422TO444_MD Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0004_GOP2_BKA4E8_REG_PIX_ALPHA_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0004_GOP2_BKA4E8_REG_ALPHA_INV Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x008)
    #define REG_0008_GOP2_BKA4E8_REG_DRAM_BASE_STR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x00C)
    #define REG_000C_GOP2_BKA4E8_REG_DRAM_BASE_STR_1 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0010_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x010)
    #define REG_0010_GOP2_BKA4E8_REG_PIC_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0014_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x014)
    #define REG_0014_GOP2_BKA4E8_REG_PIC_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0018_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x018)
    #define REG_0018_GOP2_BKA4E8_REG_PIC_X_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_001C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x01C)
    #define REG_001C_GOP2_BKA4E8_REG_PIC_Y_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0020_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x020)
    #define REG_0020_GOP2_BKA4E8_REG_DISP_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0024_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x024)
    #define REG_0024_GOP2_BKA4E8_REG_DISP_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0028_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x028)
    #define REG_0028_GOP2_BKA4E8_REG_DISP_HSTR Fld(13,0,AC_MSKW10)//[12:0]
#define REG_002C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x02C)
    #define REG_002C_GOP2_BKA4E8_REG_DISP_VSTR Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0030_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x030)
    #define REG_0030_GOP2_BKA4E8_REG_ALPHA_DEF0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0030_GOP2_BKA4E8_REG_ALPHA_DEF1 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0034_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x034)
    #define REG_0034_GOP2_BKA4E8_REG_ALPHA_DEF2 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0034_GOP2_BKA4E8_REG_ALPHA_DEF3 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0038_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x038)
    #define REG_0038_GOP2_BKA4E8_REG_SCROLL_H_LEN Fld(14,0,AC_MSKW10)//[13:0]
#define REG_003C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x03C)
    #define REG_003C_GOP2_BKA4E8_REG_SCROLL_H_STOP_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0040_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x040)
    #define REG_0040_GOP2_BKA4E8_REG_SCROLL_V_LEN Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0044_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x044)
    #define REG_0044_GOP2_BKA4E8_REG_SCROLL_V_STOP_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0048_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x048)
    #define REG_0048_GOP2_BKA4E8_REG_SCROLL_RATE Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0048_GOP2_BKA4E8_REG_SCROLL_H_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0048_GOP2_BKA4E8_REG_SCROLL_V_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0048_GOP2_BKA4E8_REG_SCROLL_H_STOP_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0048_GOP2_BKA4E8_REG_SCROLL_V_STOP_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0048_GOP2_BKA4E8_REG_RMA_REM_FLAG Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0048_GOP2_BKA4E8_REG_PRE_ALPHA_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0048_GOP2_BKA4E8_REG_RMA_ALPHA_INV Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0048_GOP2_BKA4E8_REG_RMA_DIV_ADD1 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0048_GOP2_BKA4E8_REG_RMA_REM_FLAG_CLR Fld(1,15,AC_MSKB1)//[15:15]
#define REG_004C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x04C)
    #define REG_004C_GOP2_BKA4E8_REG_TRANS_CLR_KEY_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x050)
    #define REG_0050_GOP2_BKA4E8_REG_TRANS_CLR_KEY_1 Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_0050_GOP2_BKA4E8_REG_TRANS_CLR_GRAY_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0050_GOP2_BKA4E8_REG_TRANS_CLR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0054_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x054)
    #define REG_0054_GOP2_BKA4E8_REG_TSTPAT_PARA_X Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0054_GOP2_BKA4E8_REG_TSTPAT_PARA_Y Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0054_GOP2_BKA4E8_REG_TSTPAT_PARA_X_DUP Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0054_GOP2_BKA4E8_REG_TSTPAT_PARA_Y_DUP Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0054_GOP2_BKA4E8_REG_TSTPAT_STG_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0054_GOP2_BKA4E8_REG_TSTPAT_TGEN_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0058_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x058)
    #define REG_0058_GOP2_BKA4E8_REG_HSP_RATIO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_005C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x05C)
    #define REG_005C_GOP2_BKA4E8_REG_HSP_RATIO_1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_005C_GOP2_BKA4E8_REG_HSP_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0060_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x060)
    #define REG_0060_GOP2_BKA4E8_REG_VSP_RATIO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x064)
    #define REG_0064_GOP2_BKA4E8_REG_VSP_RATIO_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0064_GOP2_BKA4E8_REG_VSP_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0068_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x068)
    #define REG_0068_GOP2_BKA4E8_REG_HSP_OUT_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_006C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x06C)
    #define REG_006C_GOP2_BKA4E8_REG_VSP_OUT_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0070_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x070)
    #define REG_0070_GOP2_BKA4E8_REG_HSP_INI_RATIO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x074)
    #define REG_0074_GOP2_BKA4E8_REG_HSP_INI_RATIO_1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_0074_GOP2_BKA4E8_REG_HSP_INI_RATIO_M1 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0078_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x078)
    #define REG_0078_GOP2_BKA4E8_REG_VSP_INI_RATIO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_007C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x07C)
    #define REG_007C_GOP2_BKA4E8_REG_VSP_INI_RATIO_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_007C_GOP2_BKA4E8_REG_VSP_INI_RATIO_M1 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0080_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x080)
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_RANGE3 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_RANGE2 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_RANGE1 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_Y_SUB16_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_COL3X3_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_COL3X3_DITHER_SEL Fld(2,5,AC_MSKB0)//[6:5]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_B_SUB16_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_R_SUB16_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_B_ADD_16_POST_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_R_ADD_16_POST_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_CR_ADD_128_POST_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_CB_ADD_128_POST_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0080_GOP2_BKA4E8_REG_MAIN_R2Y_Y_ADD_16_POST_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0084_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x084)
    #define REG_0084_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB11 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0088_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x088)
    #define REG_0088_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB12 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_008C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x08C)
    #define REG_008C_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB13 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0090_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x090)
    #define REG_0090_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB21 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0094_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x094)
    #define REG_0094_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB22 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0098_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x098)
    #define REG_0098_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB23 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_009C_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x09C)
    #define REG_009C_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB31 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A0_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0A0)
    #define REG_00A0_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB32 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A4_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0A4)
    #define REG_00A4_GOP2_BKA4E8_REG_MAIN_R2Y_SRGB33 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A8_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0A8)
    #define REG_00A8_GOP2_BKA4E8_REG_PSE_RST_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00A8_GOP2_BKA4E8_REG_PSE_RST_NUM Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_00A8_GOP2_BKA4E8_REG_FIX_R2Y_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_00A8_GOP2_BKA4E8_REG_FIX_R2Y_DITHER_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_00A8_GOP2_BKA4E8_REG_FIX_Y2R_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_00A8_GOP2_BKA4E8_REG_FIX_Y2R_DITHER_EN Fld(1,11,AC_MSKB1)//[11:11]
#define REG_00AC_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0AC)
    #define REG_00AC_GOP2_BKA4E8_REG_B_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B0_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0B0)
    #define REG_00B0_GOP2_BKA4E8_REG_G_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B4_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0B4)
    #define REG_00B4_GOP2_BKA4E8_REG_R_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B8_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0B8)
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_BYPASS Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_CR_LOAD_INI Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_42TO44_DITH_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_DITH_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_422TO444_MD Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_AYC_PLACE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00B8_GOP2_BKA4E8_REG_DOLBY_UV_SWAP_UNLINK Fld(1,7,AC_MSKB0)//[7:7]
#define REG_00BC_GOP2_BKA4E8 (GOP2_BKA4E8 + 0x0BC)
    #define REG_00BC_GOP2_BKA4E8_REG_AFBC_ERR_STATUS_CLR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00BC_GOP2_BKA4E8_REG_AFBC_ERR_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00BC_GOP2_BKA4E8_REG_AFBC_CORE_IDLE_N Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00BC_GOP2_BKA4E8_REG_DOLBY_XIU2AHB_ERR_STS Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00BC_GOP2_BKA4E8_REG_AFBC_ERR_DISPLAY_EN Fld(1,8,AC_MSKB1)//[8:8]

