////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (; MStar; Confidential; Information; ) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
//****************************************************
//   Quality Map CodeGen Version 4.0
// 1920
// M7332_TMO
// 1/3/2020  5:56:50 PM
// 17504
//****************************************************
#define Version_17504

#ifndef _M7332_TMO_MAIN_H_
#define _M7332_TMO_MAIN_H_

#define PQ_IP_TMO_NUM_Main 14
#define PQ_Source_RESERVED0
#define PQ_Source_BT709
#define PQ_Source_UNSPECIFIED
#define PQ_Source_RESERVED3
#define PQ_Source_GAMMA2P2
#define PQ_Source_GAMMA2P8
#define PQ_Source_BT601525_601625
#define PQ_Source_SMPTE240M
#define PQ_Source_LINEAR
#define PQ_Source_LOG0
#define PQ_Source_LOG1
#define PQ_Source_XVYCC
#define PQ_Source_BT1361
#define PQ_Source_SRGB_SYCC
#define PQ_Source_BT2020NCL
#define PQ_Source_BT2020CL
#define PQ_Source_SMPTE2084
#define PQ_Source_SMPTE428
#define PQ_Source_HLG
#define PQ_Source_BT1886
#define PQ_Source_DOLBYMETA
#define PQ_Source_ADOBERGB
#define PQ_Source_RGBbyPass

typedef enum
{
    #if PQ_QM_VR
    QM_RESERVED0_TMO_Main, //0
    #endif
    #if PQ_QM_VR
    QM_BT709_TMO_Main, //1
    #endif
    #if PQ_QM_VR
    QM_UNSPECIFIED_TMO_Main, //2
    #endif
    #if PQ_QM_VR
    QM_RESERVED3_TMO_Main, //3
    #endif
    #if PQ_QM_VR
    QM_GAMMA2P2_TMO_Main, //4
    #endif
    #if PQ_QM_VR
    QM_GAMMA2P8_TMO_Main, //5
    #endif
    #if PQ_QM_VR
    QM_BT601525_601625_TMO_Main, //6
    #endif
    #if PQ_QM_VR
    QM_SMPTE240M_TMO_Main, //7
    #endif
    #if PQ_QM_VR
    QM_LINEAR_TMO_Main, //8
    #endif
    #if PQ_QM_VR
    QM_LOG0_TMO_Main, //9
    #endif
    #if PQ_QM_VR
    QM_LOG1_TMO_Main, //10
    #endif
    #if PQ_QM_VR
    QM_XVYCC_TMO_Main, //11
    #endif
    #if PQ_QM_VR
    QM_BT1361_TMO_Main, //12
    #endif
    #if PQ_QM_VR
    QM_SRGB_SYCC_TMO_Main, //13
    #endif
    #if PQ_QM_VR
    QM_BT2020NCL_TMO_Main, //14
    #endif
    #if PQ_QM_VR
    QM_BT2020CL_TMO_Main, //15
    #endif
    #if PQ_QM_VR
    QM_SMPTE2084_TMO_Main, //16
    #endif
    #if PQ_QM_VR
    QM_SMPTE428_TMO_Main, //17
    #endif
    #if PQ_QM_VR
    QM_HLG_TMO_Main, //18
    #endif
    #if PQ_QM_VR
    QM_BT1886_TMO_Main, //19
    #endif
    #if PQ_QM_VR
    QM_DOLBYMETA_TMO_Main, //20
    #endif
    #if PQ_QM_VR
    QM_ADOBERGB_TMO_Main, //21
    #endif
    #if PQ_QM_VR
    QM_RGBbyPass_TMO_Main, //22
    #endif
    QM_TMO_INPUTTYPE_NUM_Main, // 23
} SC_TMO_QUALITY_MAP_INDEX_e_Main;

#define PQ_IP_TMO_SOURCE_SETTING_Main_ENABLE 1
#define PQ_IP_TMO_TARGET_SETTING_Main_ENABLE 1
#define PQ_IP_TMO_Option_Main_ENABLE 1
#define PQ_IP_NFXTest_SETTING_Main_ENABLE 1
#define PQ_IP_SWDR_SETTING_Main_ENABLE 1
#define PQ_IP_UCD_SETTING_Main_ENABLE 1
#define PQ_IP_DLC_SETTING_Main_ENABLE 1
#define PQ_IP_AVC_SETTING_Main_ENABLE 1
#define PQ_IP_CFD_Control_Point_EN_Main_ENABLE 1
#define PQ_IP_CFD_Control_Point_2_Main_ENABLE 1
#define PQ_IP_CFD_Control_Point_3_Main_ENABLE 1
#define PQ_IP_Pre_SDR_IP_Main_ENABLE 1
#define PQ_IP_HDR_IP_Main_ENABLE 1
#define PQ_IP_Post_SDR_IP_Main_ENABLE 1

typedef enum
{
#if PQ_IP_TMO_SOURCE_SETTING_Main_ENABLE
    PQ_IP_TMO_SOURCE_SETTING_Main,  //0
#endif

#if PQ_IP_TMO_TARGET_SETTING_Main_ENABLE
    PQ_IP_TMO_TARGET_SETTING_Main,  //1
#endif

#if PQ_IP_TMO_Option_Main_ENABLE
    PQ_IP_TMO_Option_Main,  //2
#endif

#if PQ_IP_NFXTest_SETTING_Main_ENABLE
    PQ_IP_NFXTest_SETTING_Main,  //3
#endif

#if PQ_IP_SWDR_SETTING_Main_ENABLE
    PQ_IP_SWDR_SETTING_Main,  //4
#endif

#if PQ_IP_UCD_SETTING_Main_ENABLE
    PQ_IP_UCD_SETTING_Main,  //5
#endif

#if PQ_IP_DLC_SETTING_Main_ENABLE
    PQ_IP_DLC_SETTING_Main,  //6
#endif

#if PQ_IP_AVC_SETTING_Main_ENABLE
    PQ_IP_AVC_SETTING_Main,  //7
#endif

#if PQ_IP_CFD_Control_Point_EN_Main_ENABLE
    PQ_IP_CFD_Control_Point_EN_Main,  //8
#endif

#if PQ_IP_CFD_Control_Point_2_Main_ENABLE
    PQ_IP_CFD_Control_Point_2_Main,  //9
#endif

#if PQ_IP_CFD_Control_Point_3_Main_ENABLE
    PQ_IP_CFD_Control_Point_3_Main,  //10
#endif

#if PQ_IP_Pre_SDR_IP_Main_ENABLE
    PQ_IP_Pre_SDR_IP_Main,  //11
#endif

#if PQ_IP_HDR_IP_Main_ENABLE
    PQ_IP_HDR_IP_Main,  //12
#endif

#if PQ_IP_Post_SDR_IP_Main_ENABLE
    PQ_IP_Post_SDR_IP_Main,  //13
#endif

 }   PQ_TMO_IPTYPE_Main;

typedef enum
{
PQ_IP_TMO_SOURCE_SETTING_COM_Main,  //0
PQ_IP_TMO_TARGET_SETTING_COM_Main,  //1
PQ_IP_TMO_Option_COM_Main,  //2
PQ_IP_NFXTest_SETTING_COM_Main,  //3
PQ_IP_SWDR_SETTING_COM_Main,  //4
PQ_IP_UCD_SETTING_COM_Main,  //5
PQ_IP_DLC_SETTING_COM_Main,  //6
PQ_IP_AVC_SETTING_COM_Main,  //7
PQ_IP_CFD_Control_Point_EN_COM_Main,  //8
PQ_IP_CFD_Control_Point_2_COM_Main,  //9
PQ_IP_CFD_Control_Point_3_COM_Main,  //10
PQ_IP_Pre_SDR_IP_COM_Main,  //11
PQ_IP_HDR_IP_COM_Main,  //12
PQ_IP_Post_SDR_IP_COM_Main,  //13
PQ_IP_TMO_COM_NUMS_Main,
} PQ_IP_TMO_COM_Group_Main;

typedef enum
{
PQ_IP_TMO_SOURCE_SETTING_OFF_Main,
PQ_IP_TMO_SOURCE_SETTING_RESERVED0_Main,
PQ_IP_TMO_SOURCE_SETTING_BT709_Main,
PQ_IP_TMO_SOURCE_SETTING_UNSPECIFIED_Main,
PQ_IP_TMO_SOURCE_SETTING_RESERVED3_Main,
PQ_IP_TMO_SOURCE_SETTING_GAMMA2P2_Main,
PQ_IP_TMO_SOURCE_SETTING_GAMMA2P8_Main,
PQ_IP_TMO_SOURCE_SETTING_BT601525_601625_Main,
PQ_IP_TMO_SOURCE_SETTING_SMPTE240M_Main,
PQ_IP_TMO_SOURCE_SETTING_LINEAR_Main,
PQ_IP_TMO_SOURCE_SETTING_LOG0_Main,
PQ_IP_TMO_SOURCE_SETTING_LOG1_Main,
PQ_IP_TMO_SOURCE_SETTING_XVYCC_Main,
PQ_IP_TMO_SOURCE_SETTING_BT1361_Main,
PQ_IP_TMO_SOURCE_SETTING_SRGB_SYCC_Main,
PQ_IP_TMO_SOURCE_SETTING_BT2020NCL_Main,
PQ_IP_TMO_SOURCE_SETTING_BT2020CL_Main,
PQ_IP_TMO_SOURCE_SETTING_SMPTE2084_Main,
PQ_IP_TMO_SOURCE_SETTING_SMPTE428_Main,
PQ_IP_TMO_SOURCE_SETTING_HLG_Main,
PQ_IP_TMO_SOURCE_SETTING_BT1886_Main,
PQ_IP_TMO_SOURCE_SETTING_DOLBYMETA_Main,
PQ_IP_TMO_SOURCE_SETTING_ADOBERGB_Main,
PQ_IP_TMO_SOURCE_SETTING_HDR_Main,
PQ_IP_TMO_SOURCE_SETTING_MTK_QA_INX_28_160nit_Main,
PQ_IP_TMO_SOURCE_SETTING_MTK_QA_AUO_32_Main,
PQ_IP_TMO_SOURCE_SETTING_NUMS_Main
} PQ_IP_TMO_SOURCE_SETTING_Group_Main;

typedef enum
{
PQ_IP_TMO_TARGET_SETTING_OFF_Main,
PQ_IP_TMO_TARGET_SETTING_RESERVED0_H_Main,
PQ_IP_TMO_TARGET_SETTING_BT709_H_Main,
PQ_IP_TMO_TARGET_SETTING_UNSPECIFIED_H_Main,
PQ_IP_TMO_TARGET_SETTING_RESERVED3_H_Main,
PQ_IP_TMO_TARGET_SETTING_GAMMA2P2_H_Main,
PQ_IP_TMO_TARGET_SETTING_GAMMA2P8_H_Main,
PQ_IP_TMO_TARGET_SETTING_BT601525_601625_H_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE240M_H_Main,
PQ_IP_TMO_TARGET_SETTING_LINEAR_H_Main,
PQ_IP_TMO_TARGET_SETTING_LOG0_H_Main,
PQ_IP_TMO_TARGET_SETTING_LOG1_H_Main,
PQ_IP_TMO_TARGET_SETTING_XVYCC_H_Main,
PQ_IP_TMO_TARGET_SETTING_BT1361_H_Main,
PQ_IP_TMO_TARGET_SETTING_SRGB_SYCC_H_Main,
PQ_IP_TMO_TARGET_SETTING_BT2020NCL_H_Main,
PQ_IP_TMO_TARGET_SETTING_BT2020CL_H_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE2084_H_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE428_H_Main,
PQ_IP_TMO_TARGET_SETTING_HLG_H_Main,
PQ_IP_TMO_TARGET_SETTING_BT1886_H_Main,
PQ_IP_TMO_TARGET_SETTING_DOLBYMETA_H_Main,
PQ_IP_TMO_TARGET_SETTING_ADOBERGB_H_Main,
PQ_IP_TMO_TARGET_SETTING_RESERVED0_M_Main,
PQ_IP_TMO_TARGET_SETTING_BT709_M_Main,
PQ_IP_TMO_TARGET_SETTING_UNSPECIFIED_M_Main,
PQ_IP_TMO_TARGET_SETTING_RESERVED3_M_Main,
PQ_IP_TMO_TARGET_SETTING_GAMMA2P2_M_Main,
PQ_IP_TMO_TARGET_SETTING_GAMMA2P8_M_Main,
PQ_IP_TMO_TARGET_SETTING_BT601525_601625_M_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE240M_M_Main,
PQ_IP_TMO_TARGET_SETTING_LINEAR_M_Main,
PQ_IP_TMO_TARGET_SETTING_LOG0_M_Main,
PQ_IP_TMO_TARGET_SETTING_LOG1_M_Main,
PQ_IP_TMO_TARGET_SETTING_XVYCC_M_Main,
PQ_IP_TMO_TARGET_SETTING_BT1361_M_Main,
PQ_IP_TMO_TARGET_SETTING_SRGB_SYCC_M_Main,
PQ_IP_TMO_TARGET_SETTING_BT2020NCL_M_Main,
PQ_IP_TMO_TARGET_SETTING_BT2020CL_M_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE2084_M_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE428_M_Main,
PQ_IP_TMO_TARGET_SETTING_HLG_M_Main,
PQ_IP_TMO_TARGET_SETTING_BT1886_M_Main,
PQ_IP_TMO_TARGET_SETTING_DOLBYMETA_M_Main,
PQ_IP_TMO_TARGET_SETTING_ADOBERGB_M_Main,
PQ_IP_TMO_TARGET_SETTING_RESERVED0_L_Main,
PQ_IP_TMO_TARGET_SETTING_BT709_L_Main,
PQ_IP_TMO_TARGET_SETTING_UNSPECIFIED_L_Main,
PQ_IP_TMO_TARGET_SETTING_RESERVED3_L_Main,
PQ_IP_TMO_TARGET_SETTING_GAMMA2P2_L_Main,
PQ_IP_TMO_TARGET_SETTING_GAMMA2P8_L_Main,
PQ_IP_TMO_TARGET_SETTING_BT601525_601625_L_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE240M_L_Main,
PQ_IP_TMO_TARGET_SETTING_LINEAR_L_Main,
PQ_IP_TMO_TARGET_SETTING_LOG0_L_Main,
PQ_IP_TMO_TARGET_SETTING_LOG1_L_Main,
PQ_IP_TMO_TARGET_SETTING_XVYCC_L_Main,
PQ_IP_TMO_TARGET_SETTING_BT1361_L_Main,
PQ_IP_TMO_TARGET_SETTING_SRGB_SYCC_L_Main,
PQ_IP_TMO_TARGET_SETTING_BT2020NCL_L_Main,
PQ_IP_TMO_TARGET_SETTING_BT2020CL_L_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE2084_L_Main,
PQ_IP_TMO_TARGET_SETTING_SMPTE428_L_Main,
PQ_IP_TMO_TARGET_SETTING_HLG_L_Main,
PQ_IP_TMO_TARGET_SETTING_BT1886_L_Main,
PQ_IP_TMO_TARGET_SETTING_DOLBYMETA_L_Main,
PQ_IP_TMO_TARGET_SETTING_ADOBERGB_L_Main,
PQ_IP_TMO_TARGET_SETTING_HDR_Main,
PQ_IP_TMO_TARGET_SETTING_MTK_QA_INX_28_160nit_Main,
PQ_IP_TMO_TARGET_SETTING_MTK_QA_AUO_32_Main,
PQ_IP_TMO_TARGET_SETTING_NUMS_Main
} PQ_IP_TMO_TARGET_SETTING_Group_Main;

typedef enum
{
PQ_IP_TMO_Option_OFF_Main,
PQ_IP_TMO_Option_RESERVED0_H_Main,
PQ_IP_TMO_Option_BT709_H_Main,
PQ_IP_TMO_Option_UNSPECIFIED_H_Main,
PQ_IP_TMO_Option_RESERVED3_H_Main,
PQ_IP_TMO_Option_GAMMA2P2_H_Main,
PQ_IP_TMO_Option_GAMMA2P8_H_Main,
PQ_IP_TMO_Option_BT601525_601625_H_Main,
PQ_IP_TMO_Option_SMPTE240M_H_Main,
PQ_IP_TMO_Option_LINEAR_H_Main,
PQ_IP_TMO_Option_LOG0_H_Main,
PQ_IP_TMO_Option_LOG1_H_Main,
PQ_IP_TMO_Option_XVYCC_H_Main,
PQ_IP_TMO_Option_BT1361_H_Main,
PQ_IP_TMO_Option_SRGB_SYCC_H_Main,
PQ_IP_TMO_Option_BT2020NCL_H_Main,
PQ_IP_TMO_Option_BT2020CL_H_Main,
PQ_IP_TMO_Option_SMPTE2084_H_Main,
PQ_IP_TMO_Option_SMPTE428_H_Main,
PQ_IP_TMO_Option_HLG_H_Main,
PQ_IP_TMO_Option_BT1886_H_Main,
PQ_IP_TMO_Option_DOLBYMETA_H_Main,
PQ_IP_TMO_Option_ADOBERGB_H_Main,
PQ_IP_TMO_Option_RESERVED0_M_Main,
PQ_IP_TMO_Option_BT709_M_Main,
PQ_IP_TMO_Option_UNSPECIFIED_M_Main,
PQ_IP_TMO_Option_RESERVED3_M_Main,
PQ_IP_TMO_Option_GAMMA2P2_M_Main,
PQ_IP_TMO_Option_GAMMA2P8_M_Main,
PQ_IP_TMO_Option_BT601525_601625_M_Main,
PQ_IP_TMO_Option_SMPTE240M_M_Main,
PQ_IP_TMO_Option_LINEAR_M_Main,
PQ_IP_TMO_Option_LOG0_M_Main,
PQ_IP_TMO_Option_LOG1_M_Main,
PQ_IP_TMO_Option_XVYCC_M_Main,
PQ_IP_TMO_Option_BT1361_M_Main,
PQ_IP_TMO_Option_SRGB_SYCC_M_Main,
PQ_IP_TMO_Option_BT2020NCL_M_Main,
PQ_IP_TMO_Option_BT2020CL_M_Main,
PQ_IP_TMO_Option_SMPTE2084_M_Main,
PQ_IP_TMO_Option_SMPTE428_M_Main,
PQ_IP_TMO_Option_HLG_M_Main,
PQ_IP_TMO_Option_BT1886_M_Main,
PQ_IP_TMO_Option_DOLBYMETA_M_Main,
PQ_IP_TMO_Option_ADOBERGB_M_Main,
PQ_IP_TMO_Option_RESERVED0_L_Main,
PQ_IP_TMO_Option_BT709_L_Main,
PQ_IP_TMO_Option_UNSPECIFIED_L_Main,
PQ_IP_TMO_Option_RESERVED3_L_Main,
PQ_IP_TMO_Option_GAMMA2P2_L_Main,
PQ_IP_TMO_Option_GAMMA2P8_L_Main,
PQ_IP_TMO_Option_BT601525_601625_L_Main,
PQ_IP_TMO_Option_SMPTE240M_L_Main,
PQ_IP_TMO_Option_LINEAR_L_Main,
PQ_IP_TMO_Option_LOG0_L_Main,
PQ_IP_TMO_Option_LOG1_L_Main,
PQ_IP_TMO_Option_XVYCC_L_Main,
PQ_IP_TMO_Option_BT1361_L_Main,
PQ_IP_TMO_Option_SRGB_SYCC_L_Main,
PQ_IP_TMO_Option_BT2020NCL_L_Main,
PQ_IP_TMO_Option_BT2020CL_L_Main,
PQ_IP_TMO_Option_SMPTE2084_L_Main,
PQ_IP_TMO_Option_SMPTE428_L_Main,
PQ_IP_TMO_Option_HLG_L_Main,
PQ_IP_TMO_Option_BT1886_L_Main,
PQ_IP_TMO_Option_DOLBYMETA_L_Main,
PQ_IP_TMO_Option_ADOBERGB_L_Main,
PQ_IP_TMO_Option_NUMS_Main
} PQ_IP_TMO_Option_Group_Main;

typedef enum
{
PQ_IP_NFXTest_SETTING_OFF_Main,
PQ_IP_NFXTest_SETTING_NFX_105_Main,
PQ_IP_NFXTest_SETTING_NFX_422_Main,
PQ_IP_NFXTest_SETTING_NFX_422_350_Main,
PQ_IP_NFXTest_SETTING_NFX_422_350_noDLC_Main,
PQ_IP_NFXTest_SETTING_NUMS_Main
} PQ_IP_NFXTest_SETTING_Group_Main;

typedef enum
{
PQ_IP_SWDR_SETTING_OFF_Main,
PQ_IP_SWDR_SETTING_RESERVED_H_Main,
PQ_IP_SWDR_SETTING_DR_H_Main,
PQ_IP_SWDR_SETTING_SWDR_H_Main,
PQ_IP_SWDR_SETTING_RESERVED_M_Main,
PQ_IP_SWDR_SETTING_DR_M_Main,
PQ_IP_SWDR_SETTING_SWDR_M_Main,
PQ_IP_SWDR_SETTING_RESERVED_L_Main,
PQ_IP_SWDR_SETTING_DR_L_Main,
PQ_IP_SWDR_SETTING_SWDR_L_Main,
PQ_IP_SWDR_SETTING_AIPQ_DR_M_Main,
PQ_IP_SWDR_SETTING_NUMS_Main
} PQ_IP_SWDR_SETTING_Group_Main;

typedef enum
{
PQ_IP_UCD_SETTING_OFF_Main,
PQ_IP_UCD_SETTING_LOW_Main,
PQ_IP_UCD_SETTING_MID_Main,
PQ_IP_UCD_SETTING_HIGH_Main,
PQ_IP_UCD_SETTING_NUMS_Main
} PQ_IP_UCD_SETTING_Group_Main;

typedef enum
{
PQ_IP_DLC_SETTING_Default_Main,
PQ_IP_DLC_SETTING_High_Main,
PQ_IP_DLC_SETTING_Mid_Main,
PQ_IP_DLC_SETTING_Low_Main,
PQ_IP_DLC_SETTING_High_HDR_Main,
PQ_IP_DLC_SETTING_Mid_HDR_Main,
PQ_IP_DLC_SETTING_Low_HDR_Main,
PQ_IP_DLC_SETTING_High_HLG_Main,
PQ_IP_DLC_SETTING_Mid_HLG_Main,
PQ_IP_DLC_SETTING_Low_HLG_Main,
PQ_IP_DLC_SETTING_HDR_Demo0912_Main,
PQ_IP_DLC_SETTING_Mid_Demo_Main,
PQ_IP_DLC_SETTING_NUMS_Main
} PQ_IP_DLC_SETTING_Group_Main;

typedef enum
{
PQ_IP_AVC_SETTING_OFF_Main,
PQ_IP_AVC_SETTING_LINEAR_Main,
PQ_IP_AVC_SETTING_NORMAL_Main,
PQ_IP_AVC_SETTING_HIGH_Main,
PQ_IP_AVC_SETTING_NUMS_Main
} PQ_IP_AVC_SETTING_Group_Main;

typedef enum
{
PQ_IP_CFD_Control_Point_EN_OFF_Main,
PQ_IP_CFD_Control_Point_EN_All_ON_Main,
PQ_IP_CFD_Control_Point_EN_Gamut_on_Main,
PQ_IP_CFD_Control_Point_EN_NUMS_Main
} PQ_IP_CFD_Control_Point_EN_Group_Main;

typedef enum
{
PQ_IP_CFD_Control_Point_2_OFF_Main,
PQ_IP_CFD_Control_Point_2_SDR_Main,
PQ_IP_CFD_Control_Point_2_HDR_Main,
PQ_IP_CFD_Control_Point_2_DOLBY_Main,
PQ_IP_CFD_Control_Point_2_NUMS_Main
} PQ_IP_CFD_Control_Point_2_Group_Main;

typedef enum
{
PQ_IP_CFD_Control_Point_3_OFF_Main,
PQ_IP_CFD_Control_Point_3_SDR_Main,
PQ_IP_CFD_Control_Point_3_HDR_Main,
PQ_IP_CFD_Control_Point_3_Panel_Out_Main,
PQ_IP_CFD_Control_Point_3_NUMS_Main
} PQ_IP_CFD_Control_Point_3_Group_Main;

typedef enum
{
PQ_IP_Pre_SDR_IP_OFF_Main,
PQ_IP_Pre_SDR_IP_default_Main,
PQ_IP_Pre_SDR_IP_Customer1_Main,
PQ_IP_Pre_SDR_IP_NUMS_Main
} PQ_IP_Pre_SDR_IP_Group_Main;

typedef enum
{
PQ_IP_HDR_IP_OFF_Main,
PQ_IP_HDR_IP_default_Main,
PQ_IP_HDR_IP_Customer1_Main,
PQ_IP_HDR_IP_NUMS_Main
} PQ_IP_HDR_IP_Group_Main;

typedef enum
{
PQ_IP_Post_SDR_IP_OFF_Main,
PQ_IP_Post_SDR_IP_default_Main,
PQ_IP_Post_SDR_IP_Customer1_Main,
PQ_IP_Post_SDR_IP_MI_3_Main,
PQ_IP_Post_SDR_IP_NUMS_Main
} PQ_IP_Post_SDR_IP_Group_Main;

extern U8 MST_SkipRule_IP_TMO_Main[PQ_IP_TMO_NUM_Main];
extern EN_IPTAB_INFO PQ_IPTAB_INFO_TMO_Main[];
extern U8 QMAP_1920_TMO_Main[QM_TMO_INPUTTYPE_NUM_Main][PQ_IP_TMO_NUM_Main];
extern U8 QMAP_1366_TMO_Main[QM_TMO_INPUTTYPE_NUM_Main][PQ_IP_TMO_NUM_Main];
extern U8 QMAP_4K2K_TMO_Main[QM_TMO_INPUTTYPE_NUM_Main][PQ_IP_TMO_NUM_Main];

#endif
