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///////////////////////////////////////////////////////////////////////////////////////////////////
///
/// @file   halPNL.h
/// @brief  Panel Driver Interface
/// @author MStar Semiconductor Inc.
///////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _HAL_PNL_H_
#define _HAL_PNL_H_

#ifdef __cplusplus
extern "C" {
#endif

#ifdef _HAL_PNL_C_
#define HAL_PNL_INTERFACE
#else
#define HAL_PNL_INTERFACE extern
#endif

#ifdef MSOS_TYPE_LINUX_KERNEL
#else
#define SUPPORT_XC_EXT_REG
#endif

//   Current platform is DAC out or not
#define IS_DAC_OUT      FALSE

// version0: Not support TV chip as HDMITx
// version1: Maserati + Raptor
// version2: Maxim + inside HDMITx
#define HW_DESIGN_HDMITX_VER        (2)

// XC register serpead define
#define XC_REGISTER_SPREAD 1
#define SUPPORT_FRC       0
#define REG_CHIP_REVISION           0x1ECEUL  //0x1ECFUL is high byte
#define XC_SUPPORT_AUTO_VSYNC   1
#define PNL_SUPPORT_DEVICE_NUM  2
#define MONACO_SC2
#define PNL_SUPPORT_2P_MODE                  (FALSE)
#define MOD_P_NUM 2
#define MFT_P_NUM 2

//#define PNL_SUPPORT_H_BRCK_PORCH_MODE

//Vsync front
#define PNL_NEED_VSYNC_FRONT (TRUE)
//-------------------------------------------------------------------------------------------------
//  Driver Capability
//-------------------------------------------------------------------------------------------------
#define  GAMMA_10BIT              BIT(0)            ///< gamma value range up to 10 BIt
#define  GAMMA_12BIT              BIT(1)            ///< gamma value range up to 12 BIT

#define  GAMMA_8BIT_MAPPING       BIT(0)            ///< mapping GAMMA value to 256 sampline entries
#define  GAMMA_10BIT_MAPPING      BIT(1)            ///< mapping GAMMA value to 1024 sampling entries
#define SUPPORT_SCALER_EXT_REG (1) //Support Extend reg
#define SUPPORT_XC_EXT_REG (1)
typedef struct
{
    MS_U8 eSupportGammaType;                        ///< refer to HAL_PNL_GAMMA_TYPE
    MS_U8 eSupportGammaMapMode;                       ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE
} PNL_HalInfo;

#define SUPPORT_OVERDRIVE                   1
#define GAMMA_TYPE                  (GAMMA_10BIT | GAMMA_12BIT)
#define GAMMA_MAPPING               (GAMMA_8BIT_MAPPING | GAMMA_10BIT_MAPPING)
#define SUPPORT_SYNC_FOR_DUAL_MODE			TRUE  //New feature after T7
#define ENABLE_Auto_ModCurrentCalibration   1
#define ENABLE_FORCE_FSM_TIMING_MODE (TRUE)
#define ENABLE_OD_AUTODOWNLOAD (FALSE)

// MIU Word (Bytes)
#define BYTE_PER_WORD           (32)

#define SUPPORT_TCON            TRUE

//#define for TCON.BIN
#define TCON20_VERSION              (2)
#define SKIP_TCON_SUBNUM            (34)
#define SKIP_TCON_MAIMHEADER        (32)
#define SKIP_TCON_SUBHEADER         (8)
#define SKIP_TCON20_SUBHEADER       (40)
#define SKIP_TCON20_PANETYPE        (2)

#define PCID_TABLE_SIZE_17X17           (289)
#define PCID_RGB_CHANNEL                (3)
#define PCID_PIXEL_OD_POLARITY_LUT_SIZE (8)
#define PCID_SKIP_HEADER                (21)
#define PCID_TABLE_COL_9                (9)
#define PCID_TABLE_COL_8                (8)
#define PCID_TABLE_ROW_9                (9)
#define PCID_TABLE_ROW_8                (8)

#define LINE_OD_HW_GAIN_SIZE_13X9        (117)
#define LINE_OD_HW_GAIN_COL_13           (13)
#define LINE_OD_HW_GAIN_ROW_9           (9)

#define MAX_DELAY_TIME                  (10)
#define TRIG_WRITE_SRAM                 (0x2000)
#define SELECT_ALL_CHANNEL_RGB          (0x000C)
#define SELECT_SRAM1                    (0x0000)
#define SELECT_SRAM2                    (0x0100)
#define SELECT_SRAM3                    (0x0200)
#define SELECT_SRAM4                    (0x0300)
#define W_RGB_MASK                      (0x230C)

#define RGB_3D_LUT_BF_XVYCC_DEGAMMA (TRUE)

#define PNL_4K_WIDTH    (3840)
#define PNL_4K_HEIGHT   (2160)
#define PNL_FHD_WIDTH    (1920)
#define PNL_FHD_HEIGHT   (1080)
#define PNL_1366X768_WIDTH    (1366)
#define PNL_1366X768_HEIGHT   (768)


#define EFUSE_MOD_ATOP_SUBBANK (0x5D) //the Efuse subbank of MOD_A RCON/BiasCon value
//#define MOD_TVFRC   //for sub bank register change
//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------


#define BK_REG_L( x, y )            ((x) | (((y) << 1)))
#define BK_REG_H( x, y )            (((x) | (((y) << 1))) + 1)

// NONPM
#define REG_RVD_BASE                0x100A00UL
#define REG_CHIPTOP_BASE            0x100B00UL  // 0x1E00 - 0x1EFF
#if XC_REGISTER_SPREAD
#define REG_SCALER_BASE             0x130000UL
#else
#define REG_SCALER_BASE             0x102F00UL
#endif
#define REG_HDGEN_BASE              0x103000UL
#define REG_LPLL_BASE               0x103100UL
#define REG_MOD_BASE                0x103200UL
#define REG_MOD_A_BASE              0x111E00UL
#define REG_CLKGEN1_BASE            0x103300UL
#define REG_UTMI1_BASE              0x103A00UL
#define REG_DISP_MISC_BASE          (0x152300UL)

#define REG_CLKGEN0_BASE            0x100B00UL
#define REG_CLKGEN1_BASE            0x103300UL

#define REG_MFT_BASE                0x123100UL

#define REG_CHIP_BASE               0x101E00UL

#define REG_SC2_BASE                0x103000UL

#define REG_SCEX_BASE               0x330000UL

/* TCON */
#define L_BK_TCON(x)                BK_REG_L(REG_HDGEN_BASE, x)
#define H_BK_TCON(x)                BK_REG_H(REG_HDGEN_BASE, x)

/* LPLL */
#define L_BK_LPLL(x)                BK_REG_L(REG_LPLL_BASE, x)
#define H_BK_LPLL(x)                BK_REG_H(REG_LPLL_BASE, x)

/* UTMI1 */
#define L_BK_UTMI1(x)               BK_REG_L(REG_UTMI1_BASE, x)
#define H_BK_UTMI1(x)               BK_REG_H(REG_UTMI1_BASE, x)

/* DISP MISC */
#define L_BK_DISP_MISC(x)           BK_REG_L(REG_DISP_MISC_BASE, x)
#define H_BK_DISP_MISC(x)           BK_REG_H(REG_DISP_MISC_BASE, x)

#define L_CLKGEN0(x)                BK_REG_L(REG_CLKGEN0_BASE, x)
#define H_CLKGEN0(x)                BK_REG_H(REG_CLKGEN0_BASE, x)
#define L_CLKGEN1(x)                BK_REG_L(REG_CLKGEN1_BASE, x)
#define H_CLKGEN1(x)                BK_REG_H(REG_CLKGEN1_BASE, x)
#define L_CLKGEN2(x)                BK_REG_L(REG_RVD_BASE, x)
#define H_CLKGEN2(x)                BK_REG_H(REG_RVD_BASE, x)

#define REG_CLKGEN0_52_L            (REG_CHIPTOP_BASE + 0xA4)
#define REG_CLKGEN0_53_L            (REG_CHIPTOP_BASE + 0xA6)
#define REG_CLKGEN0_57_L            (REG_CHIPTOP_BASE + 0xAE)
#define REG_CLKGEN0_58_L            (REG_CHIPTOP_BASE + 0xB0)
#define REG_CLKGEN0_5E_L            (REG_CHIPTOP_BASE + 0xBC)
#define REG_CLKGEN0_63_L            (REG_CHIPTOP_BASE + 0xC6)

#define REG_CLKGEN1_31_L            (REG_CLKGEN1_BASE + 0x62)
#define REG_RVD_09_L                (REG_RVD_BASE + 0x12)
#define REG_RVD_43_L                (REG_RVD_BASE + 0x86)
#define REG_RVD_44_L                (REG_RVD_BASE + 0x88)
#define REG_RVD_46_L                (REG_RVD_BASE + 0x8C)

#define REG_MFT_00_L                (REG_MFT_BASE + 0x00)
#define REG_MFT_01_L                (REG_MFT_BASE + 0x02)
#define REG_MFT_02_L                (REG_MFT_BASE + 0x04)
#define REG_MFT_03_L                (REG_MFT_BASE + 0x06)
#define REG_MFT_79_L                (REG_MFT_BASE + 0xF2)
#define REG_MFT_7E_L                (REG_MFT_BASE + 0xFC)

#define REG_CHIP_25_L               (REG_CHIP_BASE + 0x4A)
#define REG_CHIP_50_L               (REG_CHIP_BASE + 0xA0)

#define REG_SC2_00_L                (REG_SC2_BASE + 0x00)
#define REG_SC2_03_L                (REG_SC2_BASE + 0x06)

#define REG_SCEX_1601_L             (REG_SCEX_BASE + 0x1602)
#define REG_SCEX_1610_L             (REG_SCEX_BASE + 0x1620)

#define REG_SCEX_0301_L             (REG_SCEX_BASE + 0x0302)
#define REG_SCEX_0D52_L             (REG_SCEX_BASE + 0x0DA4)

#define XC_PAFRC_DITH_NOISEDITH_EN          (0x00)
#define XC_PAFRC_DITH_TAILCUT_DISABLE       (0x00)

#define LVDS_DUAL_OUTPUT          0
#define LVDS_DUAL_OUTPUT_SPECIAL  1// only for use with T8 board
#define LVDS_SINGLE_OUTPUT_A      2
#define LVDS_SINGLE_OUTPUT_B      3
#define LVDS_OUTPUT_User          4

// SCALER CLK select
#define REG_CKG_ODCLK                 REG_CLKGEN0_53_L
    #define CKG_ODCLK_GATED           BIT(0)
    #define CKG_ODCLK_INVERT          BIT(1)
    #define CKG_ODCLK_SEL_SOURCE      BIT(2)
    #define CKG_ODCLK_SEL_SYNTHETIC   (0 << 2)
    #define CKG_ODCLK_SEL_LPLL        (1 << 2)
    #define CKG_ODCLK_MASK            (BIT(3) | BIT(4))
    #define CKG_ODCLK_CLK_DIV_2       (0 << 3)
    #define CKG_ODCLK_XTAL            (1 << 3)
    #define CKG_ODCLK_CLK_DIV_4       (2 << 3)
    #define CKG_ODCLK_CLK_LPLL        (3 << 3)


#define REG_CKG_ODCLK_MFT             REG_CLKGEN0_53_L
    #define CKG_ODCLK_MFT_GATED         BIT(4)
    #define CKG_ODCLK_MFT_INVERT        BIT(5)
    #define CKG_ODCLK_MFT_SEL_SOURCE    BIT(6)
    #define CKG_ODCLK_MFT_SEL_SYNTHETIC   (0 << 6)
    #define CKG_ODCLK_MFT_SEL_LPLL        (1 << 6)
    #define CKG_ODCLK_MFT_MASK            (BIT(7) | BIT(8))
    #define CKG_ODCLK_MFT_CLK_DIV_2       (0 << 7)
    #define CKG_ODCLK_MFT_XTAL            (1 << 7)
    #define CKG_ODCLK_MFT_CLK_DIV_4       (2 << 7)
    #define CKG_ODCLK_MFT_CLK_LPLL        (3 << 7)


#define REG_CKG_TX_MOD              REG_CLKGEN0_58_L
    #define CKG_TX_MOD_GATED         BIT(0)
    #define CKG_TX_MOD_INVERT        BIT(1)
    #define CKG_TX_MOD_MASK          (BIT(3) | BIT(2))
    #define CKG_TX_1X_4XDIGITAL      (0 << 2)

#define PANEL_LPLL_INPUT_DIV_1st          0x00
#define PANEL_LPLL_INPUT_DIV_2nd          0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#define PANEL_LPLL_LOOP_DIV_1st           0x03 // 0:/1, 1:/2, 2:/4, 3:/8
#define PANEL_LPLL_LOOP_DIV_2nd           0x01 //
#define PANEL_LPLL_OUTPUT_DIV_1st         0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#define PANEL_LPLL_OUTPUT_DIV_2nd         0x00

#define LVDS_MPLL_CLOCK_MHZ     (864) // For crystal 24Mhz
#define LVDS_OSD_MPLL_CLOCK_MHZ (432)

#define LVDS_SPAN_FACTOR        131072

#define VOP_DE_HSTART_MASK      (0x3FFF) //BK_10_04
#define VOP_DE_HEND_MASK        (0x3FFF) //BK_10_05
#define VOP_DE_VSTART_MASK      (0x1FFF) //BK_10_06
#define VOP_DE_VEND_MASK        (0x1FFF) //BK_10_07

#define VOP_VTT_MASK            (0x1FFF) //BK_10_0D
#define VOP_HTT_MASK            (0x3FFF) //BK_10_0C

#define VOP_VSYNC_START_MASK      (0x17FF) //BK_10_02
#define VOP_VSYNC_END_MASK      (0x1FFF) //BK_10_03
#define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08
#define VOP_DISPLAY_HEND_MASK   (0x3FFF) //BK_10_09
#define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A
#define VOP_DISPLAY_VEND_MASK   (0x1FFF) //BK_10_0B

#define LPLL_CAL_PARAMETER     (16) //m7332 parameter is 16

#define SUPPORT_MOD_ADBANK_SEPARATE

#define SUPPORT_VBY1_HWTRAINING_MODE


//for auto set output config and clk according to pin mapping
#define CONFIG_FOR_VBY1_DATA 0x01
#define CONFIG_FOR_VBY1_DATA_BIT_NUM 2

#define VBY1_CLK_TBL_ROW 4

#define SUPPORT_PANEL_GAMMA
#define SUPPORT_PANEL_GAMMA_W_CHANNEL          (TRUE)
#define PANEL_GAMMA_1LUT_MAX_CHANNEL           (4) //RGBW
#define PANEL_GAMMA_2LUT_MAX_CHANNEL           (6) //RGBRGB

//PQ gamma ADL implemented in kernel ADL framework
//Only set to TRUE when kernel support it.
#define ENABLE_AUTODOWNLOAD_PQ_GAMMA (TRUE)

//Define OVERDRIVE
#define OVERDRIVE_WEIGHT                       (0x40)
#define OVERDRIVE_ACTIVE_THRESHOLD             (0x08)
#define OVERDRIVE_RGB_CHANNEL                  (3)
#define OVERDRIVE_RGBW_CHANNEL                 (4)
#define OVERDRIVE_MIU_BUS                      (256)
#define OVERDRIVE_PG_LENGTH                    (64)
#define OVERDRIVE_PG_ENTRY_PRE_REQ             (128)
#define OVERDRIVE_ENABLE_HSCALING              (TRUE)
#define OVERDRIVE_ENABLE_HSD_4X                (FALSE)
#define OVERDRIVE_ENABLE_VSCALING              (TRUE)
#define OVERDRIVE_VSCALING_PATCH               (TRUE)//only use at ((M7322,M7332,M7642) and (tconless) and (OVERDRIVE_ENABLE_VSCALING =TRUE))
#define OVERDRIVE_ENABLE_RGBW                  (TRUE) //If HW supprt OD RGBW
#define OVERDRIVE_RGB_444_MODE                 (12) //pix-bit
#define OVERDRIVE_RGB_565_MODE                 (16) //pix-bit
#define OVERDRIVE_RGB_666_MODE                 (18) //pix-bit
#define OVERDRIVE_COMPRESS_MODE                (12) //pix-bit
#define OVERDRIVE_RGB_555_MODE                 (15) //pix-bit
#define OVERDRIVE_RGB_888_MODE                 (24) //pix-bit
#define OVERDRIVE_MODE                         (OVERDRIVE_COMPRESS_MODE)
#define OVERDRIVE_PIXEL                        (8)
#define OVERDRIVE_PANEL_EPI                    (5)
#define OVERDRIVE_PANEL_CEDS                   (8)
#define OVERDRIVE_EXTRA_MEM_SIZE_FACTOR                    (14)//extra DRAM size to prevent page table over run
#define OVERDRIVE_ODW_6_BITMODE              (6)
#define OVERDRIVE_ODW_8_BITMODE              (8)
#define OVERDRIVE_ODW_10_BITMODE             (10)
#define OVERDRIVE_ODW_BITMODE            (OVERDRIVE_ODW_6_BITMODE)

#define ALIGN_8(x) (((x) + 0x7) & (~0x7))
//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------
typedef enum
{
    E_HALPNL_DEVICE0_XC_BANK_OFFSET    = 0,
    E_HALPNL_DEVICE1_XC_BANK_OFFSET    = 0x80
}PNL_HAL_DEVICE_XC_BANK_OFFSET;

typedef enum
{
    E_DRVPNL_ALLIN_MODE      = 1,
    E_DRVPNL_2X_MODE         = 2,
    E_DRVPNL_SEPARATE_MODE   = 3,
    E_DRVPNL_TYPE_NUM
}DRVPNL_OUT_SWING_TYPE;

typedef enum
{
    HAL_TI_10BIT_MODE = 0,
    HAL_TI_8BIT_MODE = 2,
    HAL_TI_6BIT_MODE = 3,
} PNL_HAL_TIMODES;

typedef enum
{
    E_HAL_PCID_LUT0 = 0,
    E_HAL_PCID_LUT1 = 1,
} PNL_HAL_PCID_LUT_TYPE;

typedef struct __attribute__((packed))
{
    MS_U32 u32SRAM_B1 : 8; //[7:0]
    MS_U32 u32SRAM_B2 : 8; //[15:8]
    MS_U32 u32SRAM_B3 : 8; //[23:16]
    MS_U32 u32SRAM_B4 : 8; //[31:24]
    //MS_U32 u32SRAM_B : 32;
    MS_U32 u32SRAM_G1 : 8; //[7:0]
    MS_U32 u32SRAM_G2 : 8; //[15:8]
    MS_U32 u32SRAM_G3 : 8; //[23:16]
    MS_U32 u32SRAM_G4 : 8; //[31:24]
    //MS_U32 u32SRAM_G : 32;
    MS_U32 u32SRAM_R1 : 8; //[7:0]
    MS_U32 u32SRAM_R2 : 8; //[15:8]
    MS_U32 u32SRAM_R3 : 8; //[23:16]
    MS_U32 u32SRAM_R4 : 8; //[31:24]
    //MS_U32 u32SRAM_R : 32;
    MS_U32 u32OD_B_WriteEn : 1;
    MS_U32 u32OD_G_WriteEn : 1;
    MS_U32 u32OD_R_WriteEn : 1;
    MS_U32 u32SecondOD_B_WriteEn : 1;
    MS_U32 u32SecondOD_G_WriteEn : 1;
    MS_U32 u32SecondOD_R_WriteEn : 1;
    MS_U32 u32Dummy0 : 2;
    MS_U32 u32Table_WriteAddr : 9;
    MS_U32 u32Dummy1 : 15;
    MS_U32 u32SRAM_W1 : 8; //[7:0]
    MS_U32 u32SRAM_W2 : 8; //[15:8]
    MS_U32 u32SRAM_W3 : 8; //[23:16]
    MS_U32 u32SRAM_W4 : 8; //[31:24]
    //MS_U32 u32SRAM_W : 32;
    MS_U32 u32OD_W_WriteEn : 1;
    MS_U32 u32SecondOD_W_WriteEn : 1;
    MS_U32 u32Dummy2 : 30; //[191:162]
    MS_U32 u32Dummy3 : 32; //[223:192]
    MS_U32 u32Dummy4 : 32; //[255:224]
}ST_PNL_OD_NEW_MODE_DRAM_FORMAT;

typedef enum
{
    E_PANEL_GAMMA_SUPPORT_RIU,
    E_PANEL_GAMMA_SUPPORT_ADL,
} E_PANEL_GAMMA_WRITE_TYPE;

typedef enum
{
    E_PANEL_MFT_MODE_BYPASS = 0,
    E_PANEL_MFT_MODE_2P_TO_1P = 1,
    E_PANEL_MFT_MODE_2DIVISION = 2,
    E_PANEL_MFT_MODE_4DIVISION = 3,
    E_PANEL_MFT_MODE_8DIVISION = 4,
    E_PANEL_MFT_MODE_1DIVISION = 5,
} EN_PANEL_MFT_MODE;

typedef enum
{
    E_PNL_TEST_NONE = 0,
    E_PNL_TEST_PASS,
    E_PNL_TEST_FAIL,
    E_PNL_TEST_NOT_SUPPORTED,
    E_PNL_TEST_MAX
} EN_PNL_TEST_STATUS;
//-------------------------------------------------------------------------------------------------
//  Function and Variable
//-------------------------------------------------------------------------------------------------
HAL_PNL_INTERFACE MS_VIRT g_ptr_PnlRiuBaseAddr;
HAL_PNL_INTERFACE MS_VIRT g_ptr_PMRiuBaseAddr;
#ifdef SUPPORT_XC_EXT_REG
HAL_PNL_INTERFACE MS_VIRT g_ptr_EXTRiuBaseAddr;
#endif

MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21);
void MHal_PNL_TCON_Init(void *pInstance);

void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping);

void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type);
void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21);
void MHal_Output_Channel_Order(void *pInstance, MS_U8 Type, MS_U16 u16OutputOrder0_3, MS_U16 u16OutputOrder4_7, MS_U16 u16OutputOrder8_11, MS_U16 u16OutputOrder12_13);
void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance);

void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping);
MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance);
MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping);
void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue);
void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue);
void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode);
#ifdef MONACO_SC2
void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode );
#endif
void Hal_PNL_Get12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode );
void MHal_PNL_GetGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U16 * pu16Tab );
//void _MDrv_PNL_Set_12BIT_Gamma(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab);
MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src);
void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz);
MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz);
MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz);

MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance);
void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode);
void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo);
void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_PHY u32OD_LSB_Addr, MS_PHY u32OD_LSB_limit, MS_U8 u8MIUSel);
void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable);
void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]);
#ifdef ROLLS_ROYCE
void MHal_PNL_OverDriver_Setting_TBL(void *pInstance, MS_U8* pu16ODTbl,MS_U32 u32ODTabSize,MS_U16 u16SepatateMode);
#else
void MHal_PNL_OverDriver_Setting_TBL(void *pInstance, MS_U16* pu16ODTbl,MS_U32 u32ODTabSize,MS_U16 u16SepatateMode);
#endif
void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam);
PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance);
void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type);
MS_U16 MHal_PNL_GetCurrentSwingLevel(void *pInstance);
MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level);
MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level);
void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select);
#define MHal_PNL_MOD_Control_Out_Swing_Channel(args...) FALSE
MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level);

void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData);
void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData);
void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask);
void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData);
void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type);
PNL_Result MHal_PNL_MOD_Calibration(void *pInstance);
PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn);
void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue);

void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank);
void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz);

void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank);
MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance);
MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance);


/// Set pair swap for user mode
#define MHal_FRC_MOD_PairSwap_UserMode(args...)

#define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC

void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz);

MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance);
MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance);

MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable);
MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance);
void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat);
MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable);
void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable);

void MHal_PNL_Set_T3D_Setting(void *pInstance);

void MHal_PNL_Set_Device_Bank_Offset(void *pInstance);
void MHal_PNL_Init(void *pInstance);
void MHal_PNL_Bringup(void *pInstance);
void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance);

MS_U16 MHal_PNL_GetPanelVStart(void);
MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance);
void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable);
MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance);
void MHal_PNL_TCON_Patch(void);
MS_BOOL MHal_PNL_PolInvert(void* pInstance, MS_U8 u8MotionThreshold, MS_U8 u8OsdThreshold, MS_U8 u8VideoThreshold);
void MHal_PNL_PowerDownLPLL(void *pInstance, MS_BOOL bEnable);
void MHal_PNL_TCON_GPIOPatch(void *pInstance);
void MHal_MOD_PrePowerOn(void *pInstance);
#define MHal_PNL_TCON_SCPatch(args...);
MS_BOOL MHal_PNL_VsyncShift(void);
void MHal_PNL_TCON_OD_VScaling_Patch(void *pInstance);
MS_BOOL MHal_PNL_DumpPCID_TBL(void *pInstance, MS_U8* pu8RTbl,MS_U8* pu8GTbl,MS_U8* pu8BTbl,PNL_HAL_PCID_LUT_TYPE eLutType);
void MHal_PNL_PCID_Init(void *pInstance,MS_U8* pu8Tbl,MS_BOOL bPixelOverdriveEn,MS_BOOL bXTREn);
void MHal_PNL_PCID_Enable(void *pInstance, MS_BOOL bEnable);
void MHal_PNL_SetMirrorMode(void *pInstance, ST_PNL_MIRRORINFO *pstPnlMirrorInfo);
void MHal_PNL_GetMirrorStatus(void *pInstance, ST_PNL_MIRRORINFO *pstPnlMirrorInfo);
MS_BOOL MHal_PNL_OverDriver_IsEnableRGBW(void *pInstance);
void MHal_PNL_OverDriver_EnableWChannel(void *pInstance,MS_BOOL bEnWChannel);
void MHal_PNL_PanelGamma_Enable(void *pInstance, MS_BOOL bEnable);
void MHal_PNL_SetPanelGammaByPass(void *pInstance, MS_BOOL bEnable);
MS_BOOL MHal_PNL_GetPanelGammaByPass(void *pInstance);
MS_BOOL MHal_PNL_PanelGamma_Set2LUTMode(void *pInstance, MS_PNL_PNLGAMMA_Config *pstPNLGammaConfig);
MS_BOOL MHal_PNL_SetPanelGammaTbl(void* pInstance,ST_PNL_PNLGAMMATBL *pstSetPNLGammaTbl);
MS_BOOL MHal_PNL_GetPanelGammaTbl_From_Bin(void* pInstance,ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl);
MS_BOOL MHal_PNL_GetPanelGammaTbl_From_Reg(void* pInstance,ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl);
MS_BOOL MHal_PNL_ADL_SetPQGammaTable(void *pInstance, DRVPNL_GAMMA_TYPE enGammaType, MS_U8* pu8GammaTab[3], DRVPNL_GAMMA_MAPPEING_MODE enGammaMapMode);
MS_BOOL MHal_PNL_STR_StoreSetting(void* pInstance);
MS_BOOL MHal_PNL_STR_RecoverSetting(void* pInstance);
void MHal_PNL_EnablePQGammaCLK(void *pInstance);
MS_BOOL MHal_PNL_DumpLineOD_TBL(void *pInstance, MS_U8* pu8EvenRTbl, MS_U8* pu8EvenGTbl, MS_U8* pu8EvenBTbl, MS_U8* pu8OddRTbl, MS_U8* pu8OddGTbl, MS_U8* pu8OddBTbl, MS_U8 u8LutSramSeg);
MS_BOOL MHal_PNL_DumpLineOD_Gain_TBL(void *pInstance, MS_U8* pu8ODGainTbl,MS_U16 u16GainTableSize);
PNL_Result MHal_PNL_GetMODSTATUS(void* pInstance,ST_PNL_MODSTATUS *pstGetMODSTATUS);
void MHal_PNL_Haps_Patch(void *pInstance);
void MHal_PNL_StoreSwingCfg(void* pInstance);
void MHal_PNL_RecoverSwingCfg(void* pInstance);
void MHal_PNL_StorePECfg(void* pInstance);
void MHal_PNL_RecoverPECfg(void* pInstance);
void MHal_PNL_StoreFreeSwapCfg(void* pInstance);
void MHal_PNL_RecoverFreeSwapCfg(void* pInstance);
MS_BOOL MHal_PNL_CheckOutputConfig(void *pInstance);
void MHal_PNL_AdjustDclk(void *pInstance,MS_U64* pu64InputDclk,PNL_TYPE ePnlType);
MS_BOOL Hal_PNL_TestAutodownload_PanelGamma(void* pInstance, EN_PNL_TEST_STATUS* penTestReport);
MS_BOOL Hal_PNL_TestAutodownload_OD(void* pInstance, EN_PNL_TEST_STATUS* penTestReport);
#ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
void SYMBOL_WEAK MHal_PNL_MdbIoctl_EchoCmd(MDBCMD_CMDLINE_PARAMETER *paraCmdLine);
void SYMBOL_WEAK MHal_PNL_MdbIoctl_Cat(MDBCMD_GETINFO_PARAMETER *paraGetInfo);
#endif
void MHal_PNL_EfuseMPLL(MS_BOOL bEnable);
#define MHal_PNL_Init_MIPI(args...) FALSE
#define MHal_PNL_MIPI_SetDsiPnlTiming(args...) FALSE
#define MHal_PNL_MIPI_DCS_ShortPacket(args...) FALSE
#define MHal_PNL_MIPI_DCS_LongPacket(args...) FALSE
#define MHal_PNL_MIPI_DCS_Read(args...) FALSE
#define MHal_PNL_MIPI_SetDsiMode(args...)
#define MHal_PNL_MIPI_SetDsiStart(args...)

#ifdef __cplusplus
}
#endif

#endif // _HAL_PNL_H_

