
U8 QMAP_1366_TMO_Main[QM_TMO_INPUTTYPE_NUM_Main][PQ_IP_TMO_NUM_Main]=
{
    #if PQ_QM_VR
    {//1366 RESERVED0, 0
    PQ_IP_TMO_SOURCE_SETTING_RESERVED0_Main, PQ_IP_TMO_TARGET_SETTING_RESERVED0_H_Main, PQ_IP_TMO_Option_RESERVED0_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_RESERVED_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_OFF_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 BT709, 1
    PQ_IP_TMO_SOURCE_SETTING_BT709_Main, PQ_IP_TMO_TARGET_SETTING_BT709_H_Main, PQ_IP_TMO_Option_BT709_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 UNSPECIFIED, 2
    PQ_IP_TMO_SOURCE_SETTING_UNSPECIFIED_Main, PQ_IP_TMO_TARGET_SETTING_UNSPECIFIED_H_Main, PQ_IP_TMO_Option_UNSPECIFIED_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_OFF_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 RESERVED3, 3
    PQ_IP_TMO_SOURCE_SETTING_RESERVED3_Main, PQ_IP_TMO_TARGET_SETTING_RESERVED3_H_Main, PQ_IP_TMO_Option_RESERVED3_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_RESERVED_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_OFF_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 GAMMA2P2, 4
    PQ_IP_TMO_SOURCE_SETTING_GAMMA2P2_Main, PQ_IP_TMO_TARGET_SETTING_GAMMA2P2_H_Main, PQ_IP_TMO_Option_GAMMA2P2_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 GAMMA2P8, 5
    PQ_IP_TMO_SOURCE_SETTING_GAMMA2P8_Main, PQ_IP_TMO_TARGET_SETTING_GAMMA2P8_H_Main, PQ_IP_TMO_Option_GAMMA2P8_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 BT601525_601625, 6
    PQ_IP_TMO_SOURCE_SETTING_BT601525_601625_Main, PQ_IP_TMO_TARGET_SETTING_BT601525_601625_H_Main, PQ_IP_TMO_Option_BT601525_601625_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 SMPTE240M, 7
    PQ_IP_TMO_SOURCE_SETTING_SMPTE240M_Main, PQ_IP_TMO_TARGET_SETTING_SMPTE240M_H_Main, PQ_IP_TMO_Option_SMPTE240M_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 LINEAR, 8
    PQ_IP_TMO_SOURCE_SETTING_LINEAR_Main, PQ_IP_TMO_TARGET_SETTING_LINEAR_H_Main, PQ_IP_TMO_Option_LINEAR_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 LOG0, 9
    PQ_IP_TMO_SOURCE_SETTING_LOG0_Main, PQ_IP_TMO_TARGET_SETTING_LOG0_H_Main, PQ_IP_TMO_Option_LOG0_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 LOG1, 10
    PQ_IP_TMO_SOURCE_SETTING_LOG1_Main, PQ_IP_TMO_TARGET_SETTING_LOG1_H_Main, PQ_IP_TMO_Option_LOG1_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 XVYCC, 11
    PQ_IP_TMO_SOURCE_SETTING_XVYCC_Main, PQ_IP_TMO_TARGET_SETTING_XVYCC_H_Main, PQ_IP_TMO_Option_XVYCC_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 BT1361, 12
    PQ_IP_TMO_SOURCE_SETTING_BT1361_Main, PQ_IP_TMO_TARGET_SETTING_BT1361_H_Main, PQ_IP_TMO_Option_BT1361_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 SRGB_SYCC, 13
    PQ_IP_TMO_SOURCE_SETTING_SRGB_SYCC_Main, PQ_IP_TMO_TARGET_SETTING_SRGB_SYCC_H_Main, PQ_IP_TMO_Option_SRGB_SYCC_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 BT2020NCL, 14
    PQ_IP_TMO_SOURCE_SETTING_BT2020NCL_Main, PQ_IP_TMO_TARGET_SETTING_BT2020NCL_H_Main, PQ_IP_TMO_Option_BT2020NCL_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 BT2020CL, 15
    PQ_IP_TMO_SOURCE_SETTING_BT2020CL_Main, PQ_IP_TMO_TARGET_SETTING_BT2020CL_H_Main, PQ_IP_TMO_Option_BT2020CL_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 SMPTE2084, 16
    PQ_IP_TMO_SOURCE_SETTING_MTK_QA_INX_28_160nit_Main, PQ_IP_TMO_TARGET_SETTING_MTK_QA_INX_28_160nit_Main, PQ_IP_TMO_Option_SMPTE2084_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 SMPTE428, 17
    PQ_IP_TMO_SOURCE_SETTING_SMPTE428_Main, PQ_IP_TMO_TARGET_SETTING_SMPTE428_H_Main, PQ_IP_TMO_Option_SMPTE428_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 HLG, 18
    PQ_IP_TMO_SOURCE_SETTING_HLG_Main, PQ_IP_TMO_TARGET_SETTING_HLG_H_Main, PQ_IP_TMO_Option_HLG_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_OFF_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 BT1886, 19
    PQ_IP_TMO_SOURCE_SETTING_BT1886_Main, PQ_IP_TMO_TARGET_SETTING_BT1886_H_Main, PQ_IP_TMO_Option_BT1886_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_DR_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 DOLBYMETA, 20
    PQ_IP_TMO_SOURCE_SETTING_DOLBYMETA_Main, PQ_IP_TMO_TARGET_SETTING_DOLBYMETA_H_Main, PQ_IP_TMO_Option_DOLBYMETA_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_RESERVED_L_Main, 
    PQ_IP_UCD_SETTING_OFF_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_DOLBY_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 ADOBERGB, 21
    PQ_IP_TMO_SOURCE_SETTING_ADOBERGB_Main, PQ_IP_TMO_TARGET_SETTING_ADOBERGB_H_Main, PQ_IP_TMO_Option_ADOBERGB_H_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_RESERVED_L_Main, 
    PQ_IP_UCD_SETTING_HIGH_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_SDR_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
    #if PQ_QM_VR
    {//1366 RGBbyPass, 22
    PQ_IP_TMO_SOURCE_SETTING_OFF_Main, PQ_IP_TMO_TARGET_SETTING_OFF_Main, PQ_IP_TMO_Option_OFF_Main, PQ_IP_NFXTest_SETTING_NFX_422_Main, PQ_IP_SWDR_SETTING_OFF_Main, 
    PQ_IP_UCD_SETTING_OFF_Main, PQ_IP_DLC_SETTING_Default_Main, PQ_IP_AVC_SETTING_OFF_Main, PQ_IP_CFD_Control_Point_EN_OFF_Main, PQ_IP_CFD_Control_Point_2_OFF_Main, 
    PQ_IP_CFD_Control_Point_3_Panel_Out_Main, PQ_IP_Pre_SDR_IP_default_Main, PQ_IP_HDR_IP_default_Main, PQ_IP_Post_SDR_IP_MI_3_Main, 
    },
    #endif
};

