#ifndef _MODV21_H
#define _MODV21_H

#define modv21 0x00485400

//Page MODV21_1
#define REG_0004_MODV21 (modv21 + 0x004)
    #define REG_0004_MODV21_REG_MFT_MODE Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0004_MODV21_REG_SRAM_EXT_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0004_MODV21_REG_DIV_PIX_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0004_MODV21_REG_8P_OE_IN_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0004_MODV21_REG_MULTI_READ_MD Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0004_MODV21_REG_STG_OE_SWAP Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0004_MODV21_REG_MFT_H_MIRROR Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_MODV21 (modv21 + 0x008)
    #define REG_0008_MODV21_REG_MOD_IN_8PLR_SWAP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0008_MODV21_REG_MOD_IN_4POE_MIRROR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0008_MODV21_REG_MFT_VB_MASK_LB_RD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0008_MODV21_REG_MFT_VB_MASK_LB_WR Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0008_MODV21_REG_MFT_KEEP_VB_DE_OUT Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0008_MODV21_REG_DE2TO1_ENABLE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_000C_MODV21 (modv21 + 0x00C)
    #define REG_000C_MODV21_REG_MFT_VLD_CNT_RST_BY_SYNC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_000C_MODV21_REG_MFT_VLD_CNT_RST_SYNC_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_000C_MODV21_REG_DE_RD_TRIG_SRC_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_000C_MODV21_REG_MFT_EXT_LB_RD_TRIG Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_000C_MODV21_REG_MFT_VLD_WRAP_FIX_HTT Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_000C_MODV21_REG_MFT_CTRL_TS_FIX_DISABLE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_000C_MODV21_REG_MFT_RD_TRIG_FIX_HTT_DISABLE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0014_MODV21 (modv21 + 0x014)
    #define REG_0014_MODV21_REG_HS_RP_DELAY_VALUE Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0014_MODV21_REG_HS_FP_DELAY_VALUE Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0018_MODV21 (modv21 + 0x018)
    #define REG_0018_MODV21_REG_DE_RD_DELAY_VALUE Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0018_MODV21_REG_H_SEG_FORCE Fld(8,8,AC_FULLB1)//[15:8]
#define REG_001C_MODV21 (modv21 + 0x01C)
    #define REG_001C_MODV21_REG_DBG_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_001C_MODV21_REG_DBG_STATUS Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0020_MODV21 (modv21 + 0x020)
    #define REG_0020_MODV21_REG_TRACE_CNT Fld(15,0,AC_MSKW10)//[14:0]
    #define REG_0020_MODV21_REG_TRACE_CNT_CLR Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0024_MODV21 (modv21 + 0x024)
    #define REG_0024_MODV21_REG_GATED_PATTERN Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0024_MODV21_REG_GATED_PATTERN_SW Fld(5,5,AC_MSKW10)//[9:5]
    #define REG_0024_MODV21_REG_GATED_SW_RELOAD Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0024_MODV21_REG_GATED_COND_VLD Fld(1,11,AC_MSKB1)//[11:11]
#define REG_0030_MODV21 (modv21 + 0x030)
    #define REG_0030_MODV21_REG_VS_RP_DELAY_VALUE Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0030_MODV21_REG_VS_FP_DELAY_VALUE Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0038_MODV21 (modv21 + 0x038)
    #define REG_0038_MODV21_REG_MFT_CTRL_REGEN_MODE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0038_MODV21_REG_MFT_READ_TRIG_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0038_MODV21_REG_MFT_VDE_NO_PIPE1H Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0038_MODV21_REG_MFT_VS_NO_PIPE1H Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0038_MODV21_REG_MFT_READ_TRIG_TUNE Fld(4,12,AC_MSKB1)//[15:12]
#define REG_003C_MODV21 (modv21 + 0x03C)
    #define REG_003C_MODV21_REG_MFT_READ_HDE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_MODV21 (modv21 + 0x040)
    #define REG_0040_MODV21_REG_HSIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0044_MODV21 (modv21 + 0x044)
    #define REG_0044_MODV21_REG_DIV_LEN Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0048_MODV21 (modv21 + 0x048)
    #define REG_0048_MODV21_REG_BASE0_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_004C_MODV21 (modv21 + 0x04C)
    #define REG_004C_MODV21_REG_BASE1_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0050_MODV21 (modv21 + 0x050)
    #define REG_0050_MODV21_REG_BASE2_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0054_MODV21 (modv21 + 0x054)
    #define REG_0054_MODV21_REG_BASE3_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0058_MODV21 (modv21 + 0x058)
    #define REG_0058_MODV21_REG_BASE4_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_005C_MODV21 (modv21 + 0x05C)
    #define REG_005C_MODV21_REG_BASE5_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0060_MODV21 (modv21 + 0x060)
    #define REG_0060_MODV21_REG_BASE6_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0064_MODV21 (modv21 + 0x064)
    #define REG_0064_MODV21_REG_BASE7_ADDR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0070_MODV21 (modv21 + 0x070)
    #define REG_0070_MODV21_REG_ACT_SFT_OFS Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0070_MODV21_REG_ACT_SFT_SW_MANUAL_MD Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0070_MODV21_REG_MD_4P Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0070_MODV21_REG_ACT_SFT_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0070_MODV21_REG_H_SEG_FORCE_MD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0070_MODV21_REG_ACT_SFT_PARA_VDB Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0070_MODV21_REG_ACT_SFT_PARA_UPD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0080_MODV21 (modv21 + 0x080)
    #define REG_0080_MODV21_REG_MFT8P_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0080_MODV21_REG_LB_SPMODE_PARA_UPD Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0080_MODV21_REG_LB_SPMODE_PARA_VDB Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0080_MODV21_REG_LB_RD_SPMODE_EN Fld(1,8,AC_MSKB1)//[8:8]
#define REG_0084_MODV21 (modv21 + 0x084)
    #define REG_0084_MODV21_REG_MFT8P_CH0_SWAP Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0084_MODV21_REG_ACT_SFT_DLY_USE_CH0 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0084_MODV21_REG_MFT8P_CH1_SWAP Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0084_MODV21_REG_ACT_SFT_DLY_USE_CH1 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0084_MODV21_REG_MFT8P_CH2_SWAP Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0084_MODV21_REG_ACT_SFT_DLY_USE_CH2 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0084_MODV21_REG_MFT8P_CH3_SWAP Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0084_MODV21_REG_ACT_SFT_DLY_USE_CH3 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0088_MODV21 (modv21 + 0x088)
    #define REG_0088_MODV21_REG_MFT8P_CH4_SWAP Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0088_MODV21_REG_ACT_SFT_DLY_USE_CH4 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0088_MODV21_REG_MFT8P_CH5_SWAP Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0088_MODV21_REG_ACT_SFT_DLY_USE_CH5 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0088_MODV21_REG_MFT8P_CH6_SWAP Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0088_MODV21_REG_ACT_SFT_DLY_USE_CH6 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0088_MODV21_REG_MFT8P_CH7_SWAP Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0088_MODV21_REG_ACT_SFT_DLY_USE_CH7 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C0_MODV21 (modv21 + 0x0C0)
    #define REG_00C0_MODV21_REG_2D2G_PIX_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00C0_MODV21_REG_2D2G_2LINE_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00C0_MODV21_REG_2D2G_2LINE_MODE_INI Fld(1,2,AC_MSKB0)//[2:2]
#define REG_00C4_MODV21 (modv21 + 0x0C4)
    #define REG_00C4_MODV21_REG_2D2G_PIX_SWAP00_MODE1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00C4_MODV21_REG_2D2G_PIX_SWAP01_MODE1 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00C4_MODV21_REG_2D2G_PIX_SWAP02_MODE1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00C4_MODV21_REG_2D2G_PIX_SWAP03_MODE1 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00C8_MODV21 (modv21 + 0x0C8)
    #define REG_00C8_MODV21_REG_2D2G_PIX_SWAP04_MODE1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00C8_MODV21_REG_2D2G_PIX_SWAP05_MODE1 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00C8_MODV21_REG_2D2G_PIX_SWAP06_MODE1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00C8_MODV21_REG_2D2G_PIX_SWAP07_MODE1 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00CC_MODV21 (modv21 + 0x0CC)
    #define REG_00CC_MODV21_REG_2D2G_PIX_SWAP08_MODE1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00CC_MODV21_REG_2D2G_PIX_SWAP09_MODE1 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00CC_MODV21_REG_2D2G_PIX_SWAP10_MODE1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00CC_MODV21_REG_2D2G_PIX_SWAP11_MODE1 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00D0_MODV21 (modv21 + 0x0D0)
    #define REG_00D0_MODV21_REG_2D2G_PIX_SWAP12_MODE1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00D0_MODV21_REG_2D2G_PIX_SWAP13_MODE1 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00D0_MODV21_REG_2D2G_PIX_SWAP14_MODE1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00D0_MODV21_REG_2D2G_PIX_SWAP15_MODE1 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00D4_MODV21 (modv21 + 0x0D4)
    #define REG_00D4_MODV21_REG_2D2G_PIX_SWAP16_MODE1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00D4_MODV21_REG_2D2G_PIX_SWAP17_MODE1 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00D4_MODV21_REG_2D2G_PIX_SWAP18_MODE1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00D4_MODV21_REG_2D2G_PIX_SWAP19_MODE1 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00D8_MODV21 (modv21 + 0x0D8)
    #define REG_00D8_MODV21_REG_2D2G_PIX_SWAP20_MODE1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00D8_MODV21_REG_2D2G_PIX_SWAP21_MODE1 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00D8_MODV21_REG_2D2G_PIX_SWAP22_MODE1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00D8_MODV21_REG_2D2G_PIX_SWAP23_MODE1 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00DC_MODV21 (modv21 + 0x0DC)
    #define REG_00DC_MODV21_REG_2D2G_PIX_SWAP00_MODE2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00DC_MODV21_REG_2D2G_PIX_SWAP01_MODE2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00DC_MODV21_REG_2D2G_PIX_SWAP02_MODE2 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00DC_MODV21_REG_2D2G_PIX_SWAP03_MODE2 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00E0_MODV21 (modv21 + 0x0E0)
    #define REG_00E0_MODV21_REG_2D2G_PIX_SWAP04_MODE2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00E0_MODV21_REG_2D2G_PIX_SWAP05_MODE2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00E0_MODV21_REG_2D2G_PIX_SWAP06_MODE2 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00E0_MODV21_REG_2D2G_PIX_SWAP07_MODE2 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00E4_MODV21 (modv21 + 0x0E4)
    #define REG_00E4_MODV21_REG_2D2G_PIX_SWAP08_MODE2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00E4_MODV21_REG_2D2G_PIX_SWAP09_MODE2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00E4_MODV21_REG_2D2G_PIX_SWAP10_MODE2 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00E4_MODV21_REG_2D2G_PIX_SWAP11_MODE2 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00E8_MODV21 (modv21 + 0x0E8)
    #define REG_00E8_MODV21_REG_2D2G_PIX_SWAP12_MODE2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00E8_MODV21_REG_2D2G_PIX_SWAP13_MODE2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00E8_MODV21_REG_2D2G_PIX_SWAP14_MODE2 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00E8_MODV21_REG_2D2G_PIX_SWAP15_MODE2 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00EC_MODV21 (modv21 + 0x0EC)
    #define REG_00EC_MODV21_REG_2D2G_PIX_SWAP16_MODE2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00EC_MODV21_REG_2D2G_PIX_SWAP17_MODE2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00EC_MODV21_REG_2D2G_PIX_SWAP18_MODE2 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00EC_MODV21_REG_2D2G_PIX_SWAP19_MODE2 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00F0_MODV21 (modv21 + 0x0F0)
    #define REG_00F0_MODV21_REG_2D2G_PIX_SWAP20_MODE2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00F0_MODV21_REG_2D2G_PIX_SWAP21_MODE2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_00F0_MODV21_REG_2D2G_PIX_SWAP22_MODE2 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00F0_MODV21_REG_2D2G_PIX_SWAP23_MODE2 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0100_MODV21 (modv21 + 0x100)
    #define REG_0100_MODV21_REG_GUARDBAND_MODE Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_0100_MODV21_REG_8P_GB_SHIFT_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0114_MODV21 (modv21 + 0x114)
    #define REG_0114_MODV21_REG_MFT_VS_INV Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0114_MODV21_REG_MFT_HS_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0114_MODV21_REG_MFT_DE_INV Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0114_MODV21_REG_MFT_VS_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0114_MODV21_REG_MFT_HS_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0114_MODV21_REG_MFT_DE_MASK Fld(1,5,AC_MSKB0)//[5:5]
#define REG_0118_MODV21 (modv21 + 0x118)
    #define REG_0118_MODV21_REG_MFT_DE_FILTER_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0118_MODV21_REG_MFT_DE_FILTER_ST Fld(15,0,AC_MSKW10)//[14:0]
#define REG_011C_MODV21 (modv21 + 0x11C)
    #define REG_011C_MODV21_REG_MFT_DE_FILTER_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0120_MODV21 (modv21 + 0x120)
    #define REG_0120_MODV21_REG_WOB_H_PARA_UPD Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0120_MODV21_REG_WOB_H_PARA_VDB Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0120_MODV21_REG_WOB_H_2CHIP_SLV Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0120_MODV21_REG_WOB_H_EDGE_REPEAT_MD Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0120_MODV21_REG_WOB_H_SHIFT_LR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0120_MODV21_REG_WOB_H_SHIFT_PIX Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0124_MODV21 (modv21 + 0x124)
    #define REG_0124_MODV21_REG_WOB_H_DE_WIDTH Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0128_MODV21 (modv21 + 0x128)
    #define REG_0128_MODV21_REG_WOB_H_SW_MD Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0128_MODV21_REG_WOB_H_SW_CONF_WR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0128_MODV21_REG_WOB_H_SHRINK_MD Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0128_MODV21_REG_WOB_H_SW_CONF_RD_VALUE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0128_MODV21_REG_WOB_H_SW_CONF_WR_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0128_MODV21_REG_WOB_H_SW_CONF_WR_VALUE Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0140_MODV21 (modv21 + 0x140)
    #define REG_0140_MODV21_REG_MOD_1PTO2P_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0140_MODV21_REG_MOD_2PTO4P_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0140_MODV21_REG_MOD_4PTO8P_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0140_MODV21_REG_MLX_METHOD Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0140_MODV21_REG_ENDIAN_MLX Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0140_MODV21_REG_ARGB_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0140_MODV21_REG_YUV_422_MODE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0144_MODV21 (modv21 + 0x144)
    #define REG_0144_MODV21_REG_SEL_R_CH0 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0144_MODV21_REG_SEL_G_CH0 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0144_MODV21_REG_SEL_B_CH0 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0144_MODV21_REG_SEL_R_CH1 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0144_MODV21_REG_SEL_G_CH1 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0144_MODV21_REG_SEL_B_CH1 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0148_MODV21 (modv21 + 0x148)
    #define REG_0148_MODV21_REG_SEL_R_CH2 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0148_MODV21_REG_SEL_G_CH2 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0148_MODV21_REG_SEL_B_CH2 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0148_MODV21_REG_SEL_R_CH3 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0148_MODV21_REG_SEL_G_CH3 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0148_MODV21_REG_SEL_B_CH3 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_014C_MODV21 (modv21 + 0x14C)
    #define REG_014C_MODV21_REG_SEL_R_CH4 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_014C_MODV21_REG_SEL_G_CH4 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_014C_MODV21_REG_SEL_B_CH4 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_014C_MODV21_REG_SEL_R_CH5 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_014C_MODV21_REG_SEL_G_CH5 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_014C_MODV21_REG_SEL_B_CH5 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0150_MODV21 (modv21 + 0x150)
    #define REG_0150_MODV21_REG_SEL_R_CH6 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0150_MODV21_REG_SEL_G_CH6 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0150_MODV21_REG_SEL_B_CH6 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0150_MODV21_REG_SEL_R_CH7 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0150_MODV21_REG_SEL_G_CH7 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0150_MODV21_REG_SEL_B_CH7 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0154_MODV21 (modv21 + 0x154)
    #define REG_0154_MODV21_REG_IN_CH0_SWAP Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0154_MODV21_REG_IN_CH1_SWAP Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0154_MODV21_REG_IN_CH2_SWAP Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0154_MODV21_REG_IN_CH3_SWAP Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0158_MODV21 (modv21 + 0x158)
    #define REG_0158_MODV21_REG_IN_CH4_SWAP Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0158_MODV21_REG_IN_CH5_SWAP Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0158_MODV21_REG_IN_CH6_SWAP Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0158_MODV21_REG_IN_CH7_SWAP Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0180_MODV21 (modv21 + 0x180)
    #define REG_0180_MODV21_REG_TEST_MODE Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0180_MODV21_REG_TEST_GRAY_R_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0180_MODV21_REG_TEST_GRAY_G_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0180_MODV21_REG_TEST_GRAY_B_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0180_MODV21_REG_TEST_H_INV Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0180_MODV21_REG_TEST_H_LINE_MODE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0180_MODV21_REG_TEST_V_INV Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0180_MODV21_REG_TEST_V_LINE_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0180_MODV21_REG_TEST_ENGINE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0184_MODV21 (modv21 + 0x184)
    #define REG_0184_MODV21_REG_TEST_H_LINE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_MODV21 (modv21 + 0x188)
    #define REG_0188_MODV21_REG_TEST_H_LINE_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_018C_MODV21 (modv21 + 0x18C)
    #define REG_018C_MODV21_REG_TEST_V_LINE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_MODV21 (modv21 + 0x190)
    #define REG_0190_MODV21_REG_TEST_V_LINE_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_MODV21 (modv21 + 0x194)
    #define REG_0194_MODV21_REG_TEST_COLOR_A Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0198_MODV21 (modv21 + 0x198)
    #define REG_0198_MODV21_REG_TEST_COLOR_R Fld(12,0,AC_MSKW10)//[11:0]
#define REG_019C_MODV21 (modv21 + 0x19C)
    #define REG_019C_MODV21_REG_TEST_COLOR_G Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01A0_MODV21 (modv21 + 0x1A0)
    #define REG_01A0_MODV21_REG_TEST_COLOR_B Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01A4_MODV21 (modv21 + 0x1A4)
    #define REG_01A4_MODV21_REG_TEST2_COLOR_A Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01A8_MODV21 (modv21 + 0x1A8)
    #define REG_01A8_MODV21_REG_TEST2_COLOR_R Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01AC_MODV21 (modv21 + 0x1AC)
    #define REG_01AC_MODV21_REG_TEST2_COLOR_G Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01B0_MODV21 (modv21 + 0x1B0)
    #define REG_01B0_MODV21_REG_TEST2_COLOR_B Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01B4_MODV21 (modv21 + 0x1B4)
    #define REG_01B4_MODV21_REG_TEST_COLOR_CHG_LEVEL Fld(15,0,AC_MSKW10)//[14:0]
    #define REG_01B4_MODV21_REG_TEST_COLOR_CHG_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01C0_MODV21 (modv21 + 0x1C0)
    #define REG_01C0_MODV21_REG_TGEN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C4_MODV21 (modv21 + 0x1C4)
    #define REG_01C4_MODV21_REG_TGEN_HSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_MODV21 (modv21 + 0x1C8)
    #define REG_01C8_MODV21_REG_TGEN_HDE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_MODV21 (modv21 + 0x1CC)
    #define REG_01CC_MODV21_REG_TGEN_HDE_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D0_MODV21 (modv21 + 0x1D0)
    #define REG_01D0_MODV21_REG_TGEN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_MODV21 (modv21 + 0x1D4)
    #define REG_01D4_MODV21_REG_TGEN_VSYNC_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D8_MODV21 (modv21 + 0x1D8)
    #define REG_01D8_MODV21_REG_TGEN_VDE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01DC_MODV21 (modv21 + 0x1DC)
    #define REG_01DC_MODV21_REG_TGEN_VDE_WIDTH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E0_MODV21 (modv21 + 0x1E0)
    #define REG_01E0_MODV21_REG_TGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01E0_MODV21_REG_TGEN_SET_READY Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01E0_MODV21_REG_TGEN_ENGINE Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01E0_MODV21_REG_TGEN_REPLACE_SEL Fld(5,4,AC_MSKW10)//[8:4]
    #define REG_01E0_MODV21_REG_TGEN_DB_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01E0_MODV21_REG_TGEN_VXDE_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01E0_MODV21_REG_TGEN_NO_CONT_HDE Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01E4_MODV21 (modv21 + 0x1E4)
    #define REG_01E4_MODV21_REG_MFT_RSTZ Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01E4_MODV21_REG_HS_WID_ADJ_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01E4_MODV21_REG_SSAPYB_H_BOW Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01E4_MODV21_REG_MEM_OFF_DLY_IN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01E4_MODV21_REG_MEM_OFF_DLY_ACK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E8_MODV21 (modv21 + 0x1E8)
    #define REG_01E8_MODV21_REG_MFT_DUMMY0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01EC_MODV21 (modv21 + 0x1EC)
    #define REG_01EC_MODV21_REG_MFT_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]

//Page MODV21_2
#define REG_01F0_MODV21 (modv21 + 0x1F0)
    #define REG_01F0_MODV21_REG_MFT_DUMMY2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_MODV21 (modv21 + 0x1F4)
    #define REG_01F4_MODV21_REG_MFT_DUMMY3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_MODV21 (modv21 + 0x1FC)
    #define REG_01FC_MODV21_REG_DEBUG_OUT_SEL Fld(3,0,AC_MSKB0)//[2:0]

#endif
