//<MStar Software>
//******************************************************************************
// MStar Software
// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
// All software, firmware and related documentation herein ("MStar Software") are
// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
// law, including, but not limited to, copyright law and international treaties.
// Any use, modification, reproduction, retransmission, or republication of all
// or part of MStar Software is expressly prohibited, unless prior written
// permission has been granted by MStar.
//
// By accessing, browsing and/or using MStar Software, you acknowledge that you
// have read, understood, and agree, to be bound by below terms ("Terms") and to
// comply with all applicable laws and regulations:
//
// 1. MStar shall retain any and all right, ownership and interest to MStar
//    Software and any modification/derivatives thereof.
//    No right, ownership, or interest to MStar Software and any
//    modification/derivatives thereof is transferred to you under Terms.
//
// 2. You understand that MStar Software might include, incorporate or be
//    supplied together with third party`s software and the use of MStar
//    Software may require additional licenses from third parties.
//    Therefore, you hereby agree it is your sole responsibility to separately
//    obtain any and all third party right and license necessary for your use of
//    such third party`s software.
//
// 3. MStar Software and any modification/derivatives thereof shall be deemed as
//    MStar`s confidential information and you agree to keep MStar`s
//    confidential information in strictest confidence and not disclose to any
//    third party.
//
// 4. MStar Software is provided on an "AS IS" basis without warranties of any
//    kind. Any warranties are hereby expressly disclaimed by MStar, including
//    without limitation, any warranties of merchantability, non-infringement of
//    intellectual property rights, fitness for a particular purpose, error free
//    and in conformity with any international standard.  You agree to waive any
//    claim against MStar for any loss, damage, cost or expense that you may
//    incur related to your use of MStar Software.
//    In no event shall MStar be liable for any direct, indirect, incidental or
//    consequential damages, including without limitation, lost of profit or
//    revenues, lost or damage of data, and unauthorized system use.
//    You agree that this Section 4 shall still apply without being affected
//    even if MStar Software has been modified by MStar in accordance with your
//    request or instruction for your use, except otherwise agreed by both
//    parties in writing.
//
// 5. If requested, MStar may from time to time provide technical supports or
//    services in relation with MStar Software to you for your use of
//    MStar Software in conjunction with your or your customer`s product
//    ("Services").
//    You understand and agree that, except otherwise agreed by both parties in
//    writing, Services are provided on an "AS IS" basis and the warranty
//    disclaimer set forth in Section 4 above shall apply.
//
// 6. Nothing contained herein shall be construed as by implication, estoppels
//    or otherwise:
//    (a) conferring any license or right to use MStar name, trademark, service
//        mark, symbol or any other identification;
//    (b) obligating MStar or any of its affiliates to furnish any person,
//        including without limitation, you and your customers, any assistance
//        of any kind whatsoever, or any information; or
//    (c) conferring any license or right under any intellectual property right.
//
// 7. These terms shall be governed by and construed in accordance with the laws
//    of Taiwan, R.O.C., excluding its conflict of law rules.
//    Any and all dispute arising out hereof or related hereto shall be finally
//    settled by arbitration referred to the Chinese Arbitration Association,
//    Taipei in accordance with the ROC Arbitration Law and the Arbitration
//    Rules of the Association by three (3) arbitrators appointed in accordance
//    with the said Rules.
//    The place of arbitration shall be in Taipei, Taiwan and the language shall
//    be English.
//    The arbitration award shall be final and binding to both parties.
//
//******************************************************************************
//<MStar Software>
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// ("MStar Confidential Information") by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////////////////////////
///
/// @file   drvPNL.h
/// @brief  Panel Driver Interface
/// @author MStar Semiconductor Inc.
///////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _DRV_PNL_H_
#define _DRV_PNL_H_

#ifdef _DRVPNL_C_
#define DRV_PNL_INTERFACE
#else
#define DRV_PNL_INTERFACE extern
#endif

#include "ULog.h"
#include "utopia_dapi.h"
//-------------------------------------------------------------------------------------------------
//  Driver Capability
//-------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
#define PNL_LIB_VERSION         "000.000.000.000"

//clock hz define, the unit is 0.1hz
#define DCLK_1MHZ_X10            0010000000
#define DCLK_25MHZ_X10           0250000000
#define DCLK_50MHZ_X10           0500000000
#define DCLK_75MHZ_X10           0750000000
#define DCLK_100MHZ_X10          1000000000
#define DCLK_150MHZ_X10          1500000000

#define KERNEL_DRIVER_PATCH 1
#ifdef CONFIG_MS_DEBUG_XC_LOG
#ifndef PNL_LOG_DBG
#define PNL_LOG_DBG
#endif
#endif
// OS related
//#define PNL_LOG_DBG     1
#define KERNEL_DRIVER_PNL_STR_PATCH 0

// Debug related
#ifdef PNL_LOG_DBG
#if (defined CONFIG_MLOG)
#define PNL_DBG(_dbgSwitch_, _fmt, _args...)      \
    { \
        if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) \
        {\
            ULOGD("PNL_DBG","[%s,%5d] ",__FUNCTION__,__LINE__);\
            ULOGD("PNL_DBG","PNL:"_fmt, ##_args); \
        }\
    }
#else
#define PNL_DBG(_dbgSwitch_, _fmt, _args...)      \
    { \
        if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) \
        {\
            printf("PNL_DBG:"_fmt, ##_args); \
        }\
    }
#endif
#else
#define PNL_DBG(_dbgSwitch_, _fmt, _args...)      { }
#endif

#define PNL_ASSERT(_cnd, _fmt, _args...)                                                                            \
                                    if (!(_cnd)) {                                                                  \
                                        MS_DEBUG_MSG(printf("PNL ASSERT: %s %d:"_fmt, __FILE__, __LINE__, ##_args));              \
                                        /* while(1); */                                                             \
                                    }

#define POLINVERT_MOTION_THRESHOLD   5   // 5%
#define POLINVERT_OSD_THRESHOLD      90  // 90%
#define POLINVERT_VIDEO_THRESHOLD    90  // 90%
#define POLINVERT_FULL_THRESHOLD     100 // 100%

#define PANEL_VSYNC_START_DEFUALT    (2)
#define PANEL_DE_PORCH_PROTECT_LENGTH    (2)
#define PANEL_FRONT_PORCH_PROTECT_LENGTH (20)

// for Utopia 2.0 to Utopia 1.0 compatibility.
DRV_PNL_INTERFACE void* pu32PNLInst_private;
DRV_PNL_INTERFACE void* g_pPNLResource[E_PNL_POOL_ID_NUM];

// Deafine Panel gamma ADL entry size
#define PNLGAMMA_ADL_CMD_LENGTH     (32) //byte
#define PNLGAMMA_ADL_CMD_ENTRY      (512)
#define PNLGAMMA_ADL_CMD_192_ENTRY  (192) //RGB
#define PNLGAMMA_ADL_CMD_256_ENTRY  (256) //RGBW
#define PNLGAMMA_ADL_CMD_384_ENTRY  (384) //RGBRGB

#define PANEL_GAMMA_MAINHEADER_LEN  (32)
#define PANEL_GAMMA_CHANNEL_OFFSET  (64*32)    //Each channel of R/G/B/W has 64 entry separately, each entry contains 32bytes command
#define PANEL_GAMMA_TBL_OFFSET      (0x2000)   //Each table contains R/G/B/W 4 channels, accouts for 64*32*4 = 0x2000 bytes
#define PANEL_GAMMA_ENTRY           (1024)     //Panel gamma curve has 1024 entries

//LINE OD
#define LINE_OD_TABLE_SIZE_19X19        (361)
#define LINE_OD_TABLE_SIZE_17X17        (289)
#define LINE_OD_TABLE_COL_10            (10)
#define LINE_OD_TABLE_COL_9             (9)
#define LINE_OD_TABLE_ROW_10            (10)
#define LINE_OD_TABLE_ROW_9             (9)
#define LINE_OD_GAIN_TABLE_SIZE_4X4        (16)
#define LINE_OD_GAIN_TABLE_SIZE_13X9        (117)
#define LINE_OD_GAIN_TABLE_ROW_4           (4)
#define LINE_OD_GAIN_TABLE_COL_4           (4)
#define LINE_OD_GAIN_TABLE_COL_13           (13)
#define LINE_OD_GAIN_TABLE_ROW_9           (9)
#define LINE_OD_REG_NUM_1X1           (1)
#define LINE_OD_REG_NUM_4X4           (16)
#define LINE_OD_REG_NUM_2X8           (16)
//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------
typedef enum
{
    E_PNL_FAIL = 0,
    E_PNL_OK = 1,
    E_PNL_GET_BASEADDR_FAIL,            ///< get base address failed when initialize panel driver
    E_PNL_OBTAIN_MUTEX_FAIL,            ///< obtain mutex timeout when calling this function
} PNL_Result;

typedef enum
{
    E_DRVPNL_GAMMA_10BIT         = 1,
    E_DRVPNL_GAMMA_12BIT         = 2,
} DRVPNL_GAMMA_TYPE;

typedef enum
{
    E_DRVPNL_GAMMA_8BIT_MAPPING  = 1,      ///< mapping 1024 to 256 gamma entries
    E_DRVPNL_GAMMA_10BIT_MAPPING = 2,         ///< mapping 1024 to 1024 gamma entries
} DRVPNL_GAMMA_MAPPEING_MODE;

/// Define Panel MISC control index
/// please enum use BIT0 = 0x01, BIT1 = 0x02, BIT2 = 0x04, BIT3 = 0x08, BIT4 = 0x10,
typedef enum
{
    E_DRVPNL_MISC_MFC_ENABLE = 0x0001,

    E_DRVPNL_MISC_MFC_MCP    = 0x0010,
    E_DRVPNL_MISC_MFC_ABChannel = 0x0020,
    E_DRVPNL_MISC_MFC_ACChannel = 0x0040,
    E_DRVPNL_MISC_MFC_ENABLE_60HZ = 0x0080,
    E_DRVPNL_MISC_MFC_ENABLE_240HZ = 0x0100,
    E_DRVPNL_MISC_4K2K_ENABLE_60HZ = 0x0200,
    E_DRVPNL_MISC_SKIP_T3D_CONTROL = 0x0400,
} DRVPNL_MISC;

typedef enum
{
    E_PNL_OVERDRIVER_SEPARATE_R_ENABLE = 0x08,
    E_PNL_OVERDRIVER_SEPARATE_G_ENABLE = 0x04,
    E_PNL_OVERDRIVER_SEPARATE_B_ENABLE = 0x02,
    E_PNL_OVERDRIVER_SEPARATE_W_ENABLE = 0x01,
} EN_PNL_OVERDRIVER_SEPARATE;

typedef enum
{
    E_PNL_MIPI_DSI_COMMAND_MODE,
    E_PNL_MIPI_DSI_SYNC_PULSE_VIDEO_MODE,
    E_PNL_MIPI_DSI_SYNC_EVENT_VIDEO_MODE,
    E_PNL_MIPI_DSI_BURST_VIDEO_MODE,
    E_PNL_MIPI_DSI_MODE_MAX,
}EN_PNL_MIPI_DSI_MODE;


typedef enum
{
    E_PNL_MIPI_DCS_CMD_UNKNWON,
    E_PNL_MIPI_DCS_CMD_DELAY,
    E_PNL_MIPI_DCS_CMD_SHORT_PACKET,
    E_PNL_MIPI_DCS_CMD_SHORT_PACKET_MULTI,
    E_PNL_MIPI_DCS_CMD_LONG_PACKET,
    E_PNL_MIPI_DCS_CMD_READ,
    E_PNL_MIPI_DCS_CMD_MAX,
}EN_PNL_MIPI_DCS_CMD_TYPE;

typedef struct
{
    MS_U8 u8SupportGammaType;    ///< refer to APIPNL_GAMMA_TYPE
    MS_U8 u8SupportGammaMapLv;   ///< refero to APIPNL_GAMMA_MAPPEING_MODE
} ST_PNL_DRV_INFO;

typedef struct
{
    MS_BOOL bPanel_Initialized;     ///< panel initialized or not
    MS_BOOL bPanel_Enabled;         ///< panel enabled or not, if enabled, you can see OSD/Video
} PNL_DrvStatus;

typedef enum
{
    E_PNL_TYPE_TTL,                      // 0
    E_PNL_TYPE_LVDS,                     // 1
    E_PNL_TYPE_RSDS,                     // 2
    E_PNL_TYPE_MINILVDS,                 // 3 <--  E_XC_PNL_LPLL_MINILVDS_6P_2L,
    E_PNL_TYPE_ANALOG_MINILVDS,          // 4
    E_PNL_TYPE_DIGITAL_MINILVDS,         // 5
    E_PNL_TYPE_MFC,                      // 6
    E_PNL_TYPE_DAC_I,                    // 7
    E_PNL_TYPE_DAC_P,                    // 8
    E_PNL_TYPE_PDPLVDS,                  // 9 ///< For PDP(Vsync use Manually MODE)

    E_PNL_TYPE_EXT,                      // 10
    E_PNL_LPLL_EPI34_8P = E_PNL_TYPE_EXT,// 10
    E_PNL_LPLL_EPI28_8P,                 // 11
    E_PNL_LPLL_EPI34_6P,                 // 12
    E_PNL_LPLL_EPI28_6P,                 // 13

//  E_PNL_LPLL_MINILVDS_6P_2L,                   ///< replace this with E_PNL_TYPE_MINILVDS
    E_PNL_LPLL_MINILVDS_5P_2L,           // 14
    E_PNL_LPLL_MINILVDS_4P_2L,           // 15
    E_PNL_LPLL_MINILVDS_3P_2L,           // 16
    E_PNL_LPLL_MINILVDS_6P_1L,           // 17
    E_PNL_LPLL_MINILVDS_5P_1L,           // 18
    E_PNL_LPLL_MINILVDS_4P_1L,           // 19
    E_PNL_LPLL_MINILVDS_3P_1L,           // 20

    E_PNL_TYPE_HS_LVDS,                  // 21
    E_PNL_TYPE_HF_LVDS,                  // 22

    E_PNL_TYPE_TTL_TCON,                 // 23
    E_PNL_LPLL_MINILVDS_2CH_3P_8BIT,     // 24 // 2 channel, 3 pari, 8 bits
    E_PNL_LPLL_MINILVDS_2CH_4P_8BIT,     // 25 // 2 channel, 4 pari, 8 bits
    E_PNL_LPLL_MINILVDS_2CH_5P_8BIT,    // 26 //2 channel, 5 pari, 8 bits
    E_PNL_LPLL_MINILVDS_2CH_6P_8BIT,    // 27 //2 channel, 6 pari, 8 bits

    E_PNL_LPLL_MINILVDS_1CH_3P_8BIT,    // 28 //1 channel, 3 pair, 8 bits
    E_PNL_LPLL_MINILVDS_1CH_4P_8BIT,    // 29 //1 channel, 4 pair, 8 bits
    E_PNL_LPLL_MINILVDS_1CH_5P_8BIT,    // 30 //1 channel, 5 pair, 8 bits
    E_PNL_LPLL_MINILVDS_1CH_6P_8BIT,    // 31 //1 channel, 6 pair, 8 bits

    E_PNL_LPLL_MINILVDS_2CH_3P_6BIT,    // 32 //2 channel, 3 pari, 6 bits
    E_PNL_LPLL_MINILVDS_2CH_4P_6BIT,    // 33 //2 channel, 4 pari, 6 bits
    E_PNL_LPLL_MINILVDS_2CH_5P_6BIT,    // 34 //2 channel, 5 pari, 6 bits
    E_PNL_LPLL_MINILVDS_2CH_6P_6BIT,    // 35 //2 channel, 6 pari, 6 bits

    E_PNL_LPLL_MINILVDS_1CH_3P_6BIT,    // 36 //1 channel, 3 pair, 6 bits
    E_PNL_LPLL_MINILVDS_1CH_4P_6BIT,    // 37 //1 channel, 4 pair, 6 bits
    E_PNL_LPLL_MINILVDS_1CH_5P_6BIT,    // 38 //1 channel, 5 pair, 6 bits
    E_PNL_LPLL_MINILVDS_1CH_6P_6BIT,    // 39 //1 channel, 6 pair, 6 bits

    E_PNL_LPLL_HDMI_BYPASS_MODE,        //40  // HDMI Bypass Mode

    E_PNL_LPLL_EPI34_2P,                         /// 41
    E_PNL_LPLL_EPI34_4P,                         /// 42
    E_PNL_LPLL_EPI28_2P,                         /// 43
    E_PNL_LPLL_EPI28_4P,                         /// 44

    E_PNL_LPLL_VBY1_10BIT_4LANE,    ///45
    E_PNL_LPLL_VBY1_10BIT_2LANE,    ///46
    E_PNL_LPLL_VBY1_10BIT_1LANE,    ///47
    E_PNL_LPLL_VBY1_8BIT_4LANE,     ///48
    E_PNL_LPLL_VBY1_8BIT_2LANE,     ///49
    E_PNL_LPLL_VBY1_8BIT_1LANE,     ///50

    E_PNL_LPLL_VBY1_10BIT_8LANE,     ///51
    E_PNL_LPLL_VBY1_8BIT_8LANE,     ///52

    E_PNL_LPLL_EPI28_12P,           /// 53

    E_PNL_LPLL_HS_LVDS_BYPASS_MODE, ///54
    E_PNL_LPLL_VBY1_10BIT_4LANE_BYPASS_MODE, ///55
    E_PNL_LPLL_VBY1_8BIT_4LANE_BYPASS_MODE, ///56
    E_PNL_LPLL_EPI24_12P,           ///57
    E_PNL_LPLL_VBY1_10BIT_16LANE,   ///58
    E_PNL_LPLL_VBY1_8BIT_16LANE,    ///59
    E_PNL_LPLL_USI_T_8BIT_12P,      ///60
    E_PNL_LPLL_USI_T_10BIT_12P,     ///61
    E_PNL_LPLL_ISP_8BIT_12P,        ///62
    E_PNL_LPLL_ISP_8BIT_6P_D,       ///63
    E_PNL_LPLL_ISP_8BIT_8P,         ///64
    E_PNL_LPLL_ISP_10BIT_12P,       ///65
    E_PNL_LPLL_ISP_10BIT_6P_D,      ///66
    E_PNL_LPLL_ISP_10BIT_8P,        ///67
    E_PNL_LPLL_EPI24_16P,           ///68
    E_PNL_LPLL_EPI28_16P,           ///69
    E_PNL_LPLL_EPI28_6P_EPI3G,      ///70
    E_PNL_LPLL_EPI28_8P_EPI3G,      ///71
    E_PNL_LPLL_CMPI24_10BIT_12P,    ///72
    E_PNL_LPLL_CMPI27_8BIT_12P,     ///73
    E_PNL_LPLL_CMPI27_8BIT_8P,      ///74
    E_PNL_LPLL_CMPI24_10BIT_8P,     ///75

    E_PNL_LPLL_USII_8BIT_12X1_4K,    ///76
    E_PNL_LPLL_USII_8BIT_6X1_D_4K,   ///77
    E_PNL_LPLL_USII_8BIT_8X1_4K,     ///78
    E_PNL_LPLL_USII_8BIT_6X1_4K,     ///79
    E_PNL_LPLL_USII_8BIT_6X2_4K,     ///80
    E_PNL_LPLL_USII_10BIT_12X1_4K,   ///81
    E_PNL_LPLL_USII_10BIT_8X1_4K,    ///82

    E_PNL_LPLL_EPI24_8P,              ///83
    E_PNL_LPLL_USI_T_8BIT_8P,         ///84
    E_PNL_LPLL_USI_T_10BIT_8P,        ///85
    E_PNL_LPLL_MINILVDS_4CH_6P_8BIT, ///86
    E_PNL_LPLL_EPI28_12P_EPI3G,      ///87
    E_PNL_LPLL_EPI28_16P_EPI3G,      ///88

    E_PNL_LPLL_MIPI_DSI_RGB888_4lane,  ///89
    E_PNL_LPLL_MIPI_DSI_RGB565_4lane,  ///90
    E_PNL_LPLL_MIPI_DSI_RGB666_4lane,  ///91
    E_PNL_LPLL_MIPI_DSI_RGB888_3lane,  ///92
    E_PNL_LPLL_MIPI_DSI_RGB565_3lane,  ///93
    E_PNL_LPLL_MIPI_DSI_RGB666_3lane,  ///94
    E_PNL_LPLL_MIPI_DSI_RGB888_2lane,  ///95
    E_PNL_LPLL_MIPI_DSI_RGB565_2lane,  ///96
    E_PNL_LPLL_MIPI_DSI_RGB666_2lane,  ///97
    E_PNL_LPLL_MIPI_DSI_RGB888_1lane,  ///98
    E_PNL_LPLL_MIPI_DSI_RGB565_1lane,  ///99
    E_PNL_LPLL_MIPI_DSI_RGB666_1lane,  ///100

    E_PNL_LPLL_NUM, ///101
} PNL_TYPE;

typedef enum
{
    E_PNL_LPLL_VIDEO = 0,
    E_PNL_LPLL_OSD,

}PNL_LPLL_TYPE_SEL;

typedef enum
{
    E_PNL_MODE_SINGLE = 0,          ///< single channel
    E_PNL_MODE_DUAL = 1,            ///< dual channel

    E_PNL_MODE_QUAD = 2,            ///< quad channel
    E_PNL_MODE_QUAD_LR = 3,            ///< quad channel

} PNL_MODE;

typedef enum
{
    E_PNL_OUTPUT_NO_OUTPUT = 0,     ///< even called g_IPanel.Enable(TRUE), still no physical output
    E_PNL_OUTPUT_CLK_ONLY,          ///< after called g_IPanel.Enable(TRUE), will output clock only
    E_PNL_OUTPUT_DATA_ONLY,         ///< after called g_IPanel.Enable(TRUE), will output data only
    E_PNL_OUTPUT_CLK_DATA,          ///< after called g_IPanel.Enable(TRUE), will output clock and data
    E_PNL_OUTPUT_MAX,          ///< after called g_IPanel.Enable(TRUE), will output clock and data
} PNL_OUTPUT_MODE;

typedef struct
{
    // Output timing info
    MS_U16  u16VTotal;            ///< Output vertical total
    MS_U16  u16DEVStart;          ///< Output DE vertical start
    MS_U16  u16DEVEnd;            ///< Output DE Vertical end
    MS_U16  u16VSyncStart;        ///< Output VSync start
    MS_U16  u16VSyncEnd;          ///< Output VSync end
    MS_U16  u16HTotal;            ///< Output horizontal total
    MS_U16  u16DEHStart;          ///< Output DE horizontal start
    MS_U16  u16DEHEnd;            ///< Output DE horizontal end
    MS_U16  u16HSyncWidth;        ///< Output HSync width
    MS_BOOL bIsPanelManualVysncMode; ///< enable manuel V sync control
    MS_BOOL bInterlaceOutput;     ///< enable Scaler Interlace output
} PNL_TimingInfo;

// MIPI DPHY timing control
typedef struct DLL_PACKED
{
    //DSI_PHY_TIMCON 0
    MS_U8   u8T_HS_Trail;       // for register DA_HS_TRAIL
    MS_U8   u8T_HS_Zero;        // for register DA_HS_ZERO
    MS_U8   u8T_HS_Prepare;     // for register DA_HS_PREP
    MS_U8   u8T_LPX;            // for register LPX
    //DSI_PHY_TIMCON 1
    MS_U8   u8T_HS_Exit;        // for register DA_HS_EXIT
    MS_U8   u8T_TA_Get;         // for register TA_GET
    MS_U8   u8T_TA_Sure;        // for register TA_SURE
    MS_U8   u8T_TA_Go;          // for register TA_GO
    //DSI_PHY_TIMCON 2
    MS_U8   u8T_CLK_Trail;      // for register CLK_HS_TRAIL
    MS_U8   u8T_CLK_Zero;       // for register CLK_HS_ZERO
    MS_U8   u8T_HS_Sync;        // for regsiter DA_HS_SYNC
    MS_U8   u8Cycle_Cont_Det;   // for regsiter CONT_DET
    //DSI_PHY_TIMCON 3
    MS_U8   u8T_HS_Exit_Clk;    // for register CLK_HS_EXIT
    MS_U8   u8T_CLK_Post;       // for register CLK_HS_POST
    MS_U8   u8T_CLK_Prepare;    // for register CLK_HS_PREP
}ST_PNL_MIPI_DPHY_TIMING;

// MIPI DCS command
typedef struct DLL_PACKED
{
    EN_PNL_MIPI_DCS_CMD_TYPE  enPnlMipiDcsCmd;
    MS_U16  u16Size;
    MS_U8*  pu8Data;
} ST_PNL_MIPI_DCS_CMD;

typedef struct __attribute__((packed))
{
    const char *pPanelName;                ///<  PanelName
#if !defined (__aarch64__)
    MS_U32 u32AlignmentDummy0;
#endif
    // Output timing
    MS_U16 u16HStart;               ///< DE H start
    MS_U16 u16VStart;               ///< DE V start
    MS_U16 u16Width;                ///< DE H width
    MS_U16 u16Height;               ///< DE V height
    MS_U16 u16HTotal;               ///< H total
    MS_U16 u16VTotal;               ///< V total

    MS_U16 u16DefaultVFreq;         ///< Panel output Vfreq., used in free run

    // Later need to refine to use Min/Max SET for PDP panel, but for LCD, it maybe no need to check the Min/Max SET
    //MS_U16 u16DefaultHTotal, u16DefaultVTotal;
    //MS_U16 u16MinHTotal, u16DefaultHTotal, u16MaxHTotal;
    //MS_U16 u16MinVTotal, u16DefaultVTotal, u16MaxVTotal;
    //MS_U32 u32MinDCLK, u32MaxDCLK;
    MS_U32 u32MinSET, u32MaxSET;

    // output type
    PNL_TYPE eLPLL_Type;            ///< 0: LVDS type, 1: RSDS type
    PNL_TYPE eLPLL_Type_Ext;        ///< 0: Ext LVDS type, 1: RSDS type
    PNL_MODE eLPLL_Mode;            ///< 0: single mode, 1: dual mode

    // sync
    MS_U8  u8HSyncWidth;            ///< H sync width
    MS_U16 u16VSyncStart;           ///< V sync start = Vtotal - backporch - VSyncWidth
    MS_U8  u8VSyncWidth;            ///< V sync width
    MS_BOOL bManuelVSyncCtrl;       ///< enable manuel V sync control

    // output control
    MS_U16 u16OCTRL;                ///< Output control such as Swap port, etc.
    MS_U16 u16OSTRL;                ///< Output control sync as Invert sync/DE, etc.
    MS_U16 u16ODRV;                 ///< Driving current
    MS_U16 u16DITHCTRL;             ///< Dither control

    // MOD
    MS_U16 u16MOD_CTRL0;            ///< MOD_REG(0x40), PANEL_DCLK_DELAY:8, PANEL_SWAP_LVDS_CH:6, PANEL_SWAP_LVDS_POL:5, PANEL_LVDS_TI_MODE:2,
    MS_U16 u16MOD_CTRL9;            ///< MOD_REG(0x49), PANEL_SWAP_EVEN_ML:14, PANEL_SWAP_EVEN_RB:13, PANEL_SWAP_ODD_ML:12, PANEL_SWAP_ODD_RB:11, [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit
    MS_U16 u16MOD_CTRLA;            ///< MOD_REG(0x4A), PANEL_INV_HSYNC:12, PANEL_INV_DCLK:4, PANEL_INV_VSYNC:3, PANEL_INV_DE:2, PANEL_DUAL_PORT:1, PANEL_SWAP_PORT:0,
    MS_U8  u8MOD_CTRLB;             ///< MOD_REG(0x4B), [1:0]ti_bitmode=00(10bit)

    // Other
    MS_U16 u16LVDSTxSwapValue;      ///< swap PN setting
    MS_U8  u8PanelNoiseDith;        ///<  PAFRC mixed with noise dither disable
    MS_U32 u32PNL_MISC;
    MS_U16 u16OutputCFG0_7;
    MS_U16 u16OutputCFG8_15;
    MS_U16 u16OutputCFG16_21;

    // panel on/off timing
    MS_U16 u16PanelOnTiming1;                 ///<  time between panel & data while turn on power
    MS_U16 u16PanelOnTiming2;                 ///<  time between data & back light while turn on power
    MS_U16 u16PanelOffTiming1;                 ///<  time between back light & data while turn off power
    MS_U16 u16PanelOffTiming2;                 ///<  time between data & panel while turn off power

    MS_U8 u16PanelDimmingCtl;                  ///<  Initial Dimming Value
    MS_U8 u16PanelMaxPWMVal;                 ///<  Max Dimming Value
    MS_U8 u16PanelMinPWMVal;                  ///<  Min Dimming Value

                                                                                        ///<  not support Manuel VSync Start/End now
                                                                                        ///<  VOP_02[10:0] VSync start = Vtt - VBackPorch - VSyncWidth
                                                                                        ///<  VOP_03[10:0] VSync end = Vtt - VBackPorch
    MS_U8 u16PanelHSyncBackPorch;    ///<  PANEL_HSYNC_BACK_PORCH, no register setting, provide value for query only
    MS_U8 u16PanelVBackPorch;              ///<  define PANEL_VSYNC_BACK_PORCH
    MS_U16 u16PanelAspectRatio;           ///<  Panel Aspect Ratio, provide information to upper layer application for aspect ratio setting.

    MS_U16 u16PanelOutTimingMode;        ///<Define which panel output timing change mode is used to change VFreq for same panel

    MS_U16 u16Ext_LpllType;              ///< Ext LPLL type is used by OSDC

    MS_U8  u8OutputOrderType;
    MS_U16 u16OutputOrder0_3;
    MS_U16 u16OutputOrder4_7;
    MS_U16 u16OutputOrder8_11;
    MS_U16 u16OutputOrder12_13;

    MS_BOOL bVideo_HW_Training_En;       ///< Enable Video HW training mode
    MS_BOOL bOSD_HW_Training_En;         ///< Enable OSD HW training mode

    //HDMI2.1 VRR
    MS_BOOL bVRR_en;                     // variable refresh rate
    MS_U16 u16VRRMaxRate;                // vrr max frame rate
    MS_U16 u16VRRMinRate;                // vrr min frame rate
    MS_BOOL bCinemaVRR_en;
    MS_U16 u16M_delta;                   // change vtt every time by m_delta

    MS_U16 u16MaxVTotal;                 // Panel max VTT
    MS_U16 u16MinVTotal;                 // Panel min VTT

    //MIPI DPHY timing
    MS_BOOL bDphyTimingRdy;     // DPHY timing Ready in panel ini
    MS_U8   u8T_HS_Trail;       // for register DA_HS_TRAIL
    MS_U8   u8T_HS_Zero;        // for register DA_HS_ZERO
    MS_U8   u8T_HS_Prepare;     // for register DA_HS_PREP
    MS_U8   u8T_LPX;            // for register LPX
    MS_U8   u8T_HS_Exit;        // for register DA_HS_EXIT
    MS_U8   u8T_TA_Get;         // for register TA_GET
    MS_U8   u8T_TA_Sure;        // for register TA_SURE
    MS_U8   u8T_TA_Go;          // for register TA_GO
    MS_U8   u8T_CLK_Trail;      // for register CLK_HS_TRAIL
    MS_U8   u8T_CLK_Zero;       // for register CLK_HS_ZERO
    MS_U8   u8T_HS_Sync;        // for regsiter DA_HS_SYNC
    MS_U8   u8Cycle_Cont_Det;   // for regsiter CONT_DET
    MS_U8   u8T_HS_Exit_Clk;    // for register CLK_HS_EXIT
    MS_U8   u8T_CLK_Post;       // for register CLK_HS_POST
    MS_U8   u8T_CLK_Prepare;    // for register CLK_HS_PREP
} PNL_InitData;



//HW LVDS Reserved Bit to L/R flag Info
typedef struct
{
    MS_U32 u32pair; // pair 0: BIT0, pair 1: BIT1, pair 2: BIT2, pair 3: BIT3, pair 4: BIT4, etc ...
    MS_U16 u16channel; // channel A: BIT0, channel B: BIT1,
    MS_BOOL bEnable;
} PNL_DrvHW_LVDSResInfo;

typedef struct
{
    MS_U16 u16ExpectSwingLevel;
    MS_U8 u8ModCaliPairSel;
    MS_U8 u8ModCaliTarget;
    MS_S8 s8ModCaliOffset;
    MS_BOOL bPVDD_2V5;
}PNL_ModCali_InitData;

typedef struct
{
    MS_U16 u16ControlSwingch0;
    MS_U16 u16ControlSwingch1;
    MS_U16 u16ControlSwingch2;
    MS_U16 u16ControlSwingch3;
    MS_U16 u16ControlSwingch4;
    MS_U16 u16ControlSwingch5;
    MS_U16 u16ControlSwingch6;
    MS_U16 u16ControlSwingch7;
    MS_U16 u16ControlSwingch8;
    MS_U16 u16ControlSwingch9;
    MS_U16 u16ControlSwingch10;
    MS_U16 u16ControlSwingch11;
    MS_U16 u16ControlSwingch12;
    MS_U16 u16ControlSwingch13;
}ST_PNL_SWING_Config;

typedef struct
{
    MS_U16 u16ControlPEch0;
    MS_U16 u16ControlPEch1;
    MS_U16 u16ControlPEch2;
    MS_U16 u16ControlPEch3;
    MS_U16 u16ControlPEch4;
    MS_U16 u16ControlPEch5;
    MS_U16 u16ControlPEch6;
    MS_U16 u16ControlPEch7;
    MS_U16 u16ControlPEch8;
    MS_U16 u16ControlPEch9;
    MS_U16 u16ControlPEch10;
    MS_U16 u16ControlPEch11;
    MS_U16 u16ControlPEch12;
    MS_U16 u16ControlPEch13;
    MS_U16 u16ControlPEch14;
    MS_U16 u16ControlPEch15;
}ST_PNL_PE_Config;

typedef struct
{
    MS_U16 u16OutputOrder0_3;
    MS_U16 u16OutputOrder4_7;
    MS_U16 u16OutputOrder8_11;
    MS_U16 u16OutputOrder12_15;
}ST_PNL_SWAP_Config;

typedef enum
{
/*
__________________________________________________________________________________________________________________________________________
|Vby1 Output Format|D0|D1|D2|D3|D4|D5|D6|D7|D8|D9|D10|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|D24|D25|D26|D27|D28|D29|D30|D31|
|------------------|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ARGB 1           |R0|R1|R2|R3|R4|R5|R6|R7|G0|G1|G2 |G3 |G4 |G5 |G6 |G7 |B0 |B1 |B2 |B3 |B4 |B5 |B6 |B7 |A1 |A0 |A2 |A3 |A4 |A5 |A6 |A7 |
|------------------|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ARGB 2           |R2|R3|R4|R5|R6|R7|A6|A7|G2|G3|G4 |G5 |G6 |G7 |A4 |A5 |B2 |B3 |B4 |B5 |B6 |B7 |A2 |A3 |A0 |A1 |B0 |B1 |G0 |G1 |R0 |R1 |
------------------------------------------------------------------------------------------------------------------------------------------
*/
    E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB1,
    E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB2,
} E_PNL_OSDC_OUTPUT_FORMAT;

typedef enum
{
    E_PNL_TCON_PANELINFO_PANELLINKTYPE = 0,
    E_PNL_TCON_PANELINFO_PANELLINKEXTTYPE,
    E_PNL_TCON_PANELINFO_FIXEDVABCKPORCH,
    E_PNL_TCON_PANELINFO_FIXEDHBACKPORCH,

    E_PNL_TCON_PANELINFO_VSYNC_START = 11,
    E_PNL_TCON_PANELINFO_VSYNC_END,
    E_PNL_TCON_PANELINFO_VDESTART,
    E_PNL_TCON_PANELINFO_VDEND,
    E_PNL_TCON_PANELINFO_PANELMAXVTOTAL,
    E_PNL_TCON_PANELINFO_PANELVTOTAL,
    E_PNL_TCON_PANELINFO_MINVTOTAL,
    E_PNL_TCON_PANELINFO_VDEHEADDUMMY,
    E_PNL_TCON_PANELINFO_VDETAILDUMMY,

    E_PNL_TCON_PANELINFO_HSYNC_START = 31,
    E_PNL_TCON_PANELINFO_HSYNC_END,
    E_PNL_TCON_PANELINFO_HDESTART,
    E_PNL_TCON_PANELINFO_HDEEND,
    E_PNL_TCON_PANELINFO_PANELMAXHTOTAL,
    E_PNL_TCON_PANELINFO_PANELHTOTAL,
    E_PNL_TCON_PANELINFO_PANELMINHTOTAL,
    E_PNL_TCON_PANELINFO_HDEHEADDUMMY,
    E_PNL_TCON_PANELINFO_HDETAILDUMMY,

    E_PNL_TCON_PANELINFO_PANELMAXDCLK = 51,
    E_PNL_TCON_PANELINFO_PANELDCLK,
    E_PNL_TCON_PANELINFO_PANELMINDCLK,
    E_PNL_TCON_PANELINFO_PANELMAXSET,
    E_PNL_TCON_PANELINFO_MINSET,
    E_PNL_TCON_PANELINFO_OUTTIMINGMODE,
    E_PNL_TCON_PANELINFO_TOTALPAIR,
    E_PNL_TCON_PANELINFO_PAIREVEN,
    E_PNL_TCON_PANELINFO_PAIRODD,
    E_PNL_TCON_PANELINFO_DUALPORT,

    E_PNL_TCON_PANELINFO_PANELHSYNCWIDTH = 71,
    E_PNL_TCON_PANELINFO_PANELHSYNCBACKPORCH,
    E_PNL_TCON_PANELINFO_PANELVSYNCWIDTH,
    E_PNL_TCON_PANELINFO_PANELVBACKPORCH,

    E_PNL_TCON_PANELINFO_SSC_ENABLE = 80,
    E_PNL_TCON_PANELINFO_SSC_FMODULATION,
    E_PNL_TCON_PANELINFO_SSC_PERCENTAGE,
    E_PNL_TCON_PANELINFO_SSC_BIN_CTRL,
} E_PNL_TCON_PANELINFO;

typedef struct
{
    MS_U32 u32PanelLinkType;
    MS_U32 u32PanelLinkExtType;
    MS_U32 u32FixedVBackPorch;
    MS_U32 u32FixedHBackPorch;
    MS_U32 u32VsyncStart;
    MS_U32 u32VsyncEnd;
    MS_U32 u32VDEStart;
    MS_U32 u32VDEEnd;
    MS_U32 u32PanelMaxVTotal;
    MS_U32 u32PanelVTotal;
    MS_U32 u32PanelMinVTotal;
    MS_U32 u32VDEHeadDummy;
    MS_U32 u32VDETailDummy;
    MS_U32 u32HsyncStart;
    MS_U32 u32HsyncEnd;
    MS_U32 u32HDEStart;
    MS_U32 u32HDEEnd;
    MS_U32 u32PanelMaxHTotal;
    MS_U32 u32PanelHTotal;
    MS_U32 u32PanelMinHTotal;
    MS_U32 u32HDEHeadDummy;
    MS_U32 u32HDETailDummy;
    MS_U32 u32PanelMaxDCLK;
    MS_U32 u32PanelDCLK;
    MS_U32 u32PanelMinDCLK;
    MS_U32 u32PanelMaxSET;
    MS_U32 u32PanelMinSET;
    MS_U32 u32OutTimingMode;
    MS_U32 u32HTotalPair;
    MS_U32 u32VTotalPair_Even;
    MS_U32 u32VTotalPair_Odd;
    MS_U32 u32DaulPort;
    MS_U32 u32PanelHsyncWidth;
    MS_U32 u32PanelHsyncBackPorch;
    MS_U32 u32PanelVsyncWidth;
    MS_U32 u32PanelVsyncBackPorch;
    MS_U32 u32SSCEnable;
    MS_U32 u32SSC_Fmodulation;
    MS_U32 u32SSC_Percentage;
    MS_U32 u32SSC_TconBinCtrl;
}ST_PNL_TCON_PANELINFO;

typedef enum
{
    E_PNL_INTERFACE_MINILVDS_TYPE = 0,
    E_PNL_INTERFACE_EPI_TYPE,
    E_PNL_INTERFACE_ISP_TYPE,
    E_PNL_INTERFACE_CEDS_TYPE,
    E_PNL_INTERFACE_USIT_TYPE,
    E_PNL_INTERFACE_CMPI_TYPE,
    E_PNL_INTERFACE_VBY1_TYPE,
    E_PNL_INTERFACE_CHPI_TYPE,
    E_PNL_INTERFACE_CSPI_TYPE,
    E_PNL_INTERFACE_MAX_TYPE,
} EN_PNL_INTERFACE_TYPE;

typedef struct
{
    MS_BOOL bUsingTCON;
#if !defined(CONFIG_MBOOT)
    MS_U8 u8SubTableType;
    MS_U16 u16RegCount;
    MS_U8 u8RegType;
    MS_U16 u16RegListOffset;
#endif
    ST_PNL_TCON_PANELINFO stPanelInfo;
    EN_PNL_INTERFACE_TYPE enPanelInterface;
}ST_PNL_TCON_Config;

// TCon register type
typedef enum
{
    EN_TCON20_REGISTERTYPE_6_BYTES = 0,       // 32-bit address, 4+1+1, address+mask+value
    EN_TCON20_REGISTERTYPE_4_BYTES,       // 16-bit address, 2+1+1, address+mask+value
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_9_BYTES,      // 32-bit address, 4+1+1+1+1+1, address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_7_BYTES,      // 16-bit address, 2+1+1+1+1+1, address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_WITHSUB_15_BYTES, // 32-bit address, 4+1+1+4+1+1+1+1+1, subAddress+subMask+subValue+address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_WITHSUB_11_BYTES, // 16-bit address, 2+1+1+2+1+1+1+1+1, subAddress+subMask+subValue+address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERGAMMA_4_BYTES, // Register type 6: P-Gamma (Power Gamma) 4-byte register format (16-bit address size and 16-bit value size)
    EN_TCON20_REGISTERTYPE_3_BYTES, // Register type 7: TCON 3-byte register format (12-bit address size)
    EN_TCON20_REGISTERTYPE_PANEL_1_BYTES, // Register type 8: 1-byte only data.
    EN_TCON20_REGISTERTYPE_PANEL_6_BYTES, //Register tyep 9: 2+4, panelinfo ID+value
    EN_TCON20_REGISTERTYPE_POWERSEQUENCE_14BYTES, // Register type A : 3+1+1+3+2+2+1+1 subbankaddress + mask+subbank+adress+mask+value+delaytime+prioriry
    EN_TCON20_REGISTERTYPE_PANEL_6_BYTES_NEWSSC, //Register tyep 9: 2+4, panelinfo ID+value, for new SSC calculation
    EN_TCON_REGISTERTYPE_END,
} E_PNL_TCON20_REGISTERTYPE;

typedef struct __attribute__((packed))
{
    MS_U16 u16Version;               //[15:8]: major, [7:0]: minor version
    MS_U8 u8LineOD_en;               //[0]: line od enable
    MS_U8 u8SeparateFlag;            //[0]: channel separate flag [1]: table separate flag (unused)
    MS_U32 u32YearMonthDayMinute;    //[31:25]: reserved, [24:20]: year, [19:16]: month, [15:11]: day, [10:0]: minute
    MS_U8 u8TableMatrix;             //0: 19x19, 1: 17x17
    MS_U8 u8RegionNumber;            //(Version>1 0: 1x1, 1: 2x8, 2:4X4) (Version<=1 16: 4x4 or 2x8, 1: 1x1)
    MS_U8 u8GainMatrix;            //0: 4x4, 1: 13x9
    MS_U8 u8GainRegion;            //0: 1x1
    MS_U8 u8Reserved;
} ST_PNL_LINE_OD_SUB_HEADER, *pST_PNL_LINE_OD_SUB_HEADER;

typedef struct __attribute__((packed))
{
    MS_U8 u8GammaType;
    MS_U8 u8Table2DNumber;
    MS_U8 u8Table3DNumber;
    MS_U8 u8TableFormat;
    MS_U16 u16PreTableOrignalSize;
    MS_U16 u16PreTableAlignedSize;
    MS_U32 u32Table2DStartAddress;
    MS_U32 u32Table3DStartAddress;
    MS_U8 u8BINVersion_Minor2;
    MS_U8 u8BINVersion_Minor1;
    MS_U8 u8BINVersion_Major;
    MS_U8 u8PanelSize;
    MS_U16 u16Minute : 11;
    MS_U8 u8Day : 5;
    MS_U8 u8Month : 4;
    MS_U8 u8Year : 5;
    MS_U8 u8Reserved0 : 7;
    MS_BOOL bGamma2LutEnable : 1;
    MS_U8 u8Gamma2LutMode : 2;
    MS_U32 u32Reserved1 : 29;
    MS_U32 u32Reserved2;
}MS_PNL_PNLGAMMA_Config;

#define IsTCONType_EPI(x) ( (((x) >= E_PNL_LPLL_EPI34_8P) && ((x) <= E_PNL_LPLL_EPI28_6P)) || (((x) >= E_PNL_LPLL_EPI34_2P) && ((x) <= E_PNL_LPLL_EPI28_4P)) || \
                                                 ((x) == E_PNL_LPLL_EPI28_12P) || ((x) == E_PNL_LPLL_EPI24_12P) || (((x) >= E_PNL_LPLL_EPI24_16P) && ((x) <= E_PNL_LPLL_EPI28_8P_EPI3G)) || \
                                                 ((x) == E_PNL_LPLL_EPI24_8P) || ((x) == E_PNL_LPLL_EPI28_12P_EPI3G) || ((x) == E_PNL_LPLL_EPI28_16P_EPI3G))
#define IsTCONType_ISP(x) ( ( (x) >= E_PNL_LPLL_ISP_8BIT_12P) && ( (x) <= E_PNL_LPLL_ISP_10BIT_8P) )
#define IsTCONType_USIT(x) ( ( (x) == E_PNL_LPLL_USI_T_8BIT_12P ) || ( (x) == E_PNL_LPLL_USI_T_10BIT_12P) || ( (x) == E_PNL_LPLL_USI_T_8BIT_8P) || ( (x) == E_PNL_LPLL_USI_T_10BIT_8P) )
#define IsTCONType_USII(x) (( (x) >= E_PNL_LPLL_USII_8BIT_12X1_4K) && ((x) <= E_PNL_LPLL_USII_10BIT_8X1_4K))
#define IsTCONType_CMPI(x) (( (x) >= E_PNL_LPLL_CMPI24_10BIT_12P) && ((x) <= E_PNL_LPLL_CMPI24_10BIT_8P))
#define IsTCONType_MiniLVDS(x) ( ((x) >= E_PNL_LPLL_MINILVDS_5P_2L && (x) <= E_PNL_LPLL_MINILVDS_3P_1L ) || ((x) >= E_PNL_LPLL_MINILVDS_2CH_3P_8BIT && (x) <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT) )
#define IsVBY1(x)      ( (((x)>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&((x)<= E_PNL_LPLL_VBY1_8BIT_8LANE)) || ((x)== E_PNL_LPLL_VBY1_10BIT_16LANE)||((x)== E_PNL_LPLL_VBY1_8BIT_16LANE) )

#define IsTCON(x)      ( IsTCONType_EPI(x) || IsTCONType_ISP(x) || IsTCONType_USIT(x) || IsTCONType_USII(x) || IsTCONType_CMPI(x) || IsTCONType_MiniLVDS(x) )
#define IsTCONTYPE(x)  ( ((x) != E_PNL_INTERFACE_VBY1_TYPE))
#define IsTCONBIN(x)   (((IsTCON(x)) && (stTCONPanelConfig.bUsingTCON)))
#define IsTCONLESS(x)   ((IsTCONBIN(x) && IsTCONTYPE(stTCONPanelConfig.enPanelInterface)))
#define IsMIPI(x)   ( ( (x) >= E_PNL_LPLL_MIPI_DSI_RGB888_4lane) && ( (x) <= E_PNL_LPLL_MIPI_DSI_RGB666_1lane) )
//-------------------------------------------------------------------------------------------------
//  Function and Variable
//-------------------------------------------------------------------------------------------------
DRV_PNL_INTERFACE MS_U16 _u16PnlDbgSwitch;

// must have functions
DRV_PNL_INTERFACE const MS_U8 * MDrv_PNL_GetLibVer(void);                  ///< Get version (without Mutex protect)
DRV_PNL_INTERFACE ST_PNL_DRV_INFO MDrv_PNL_GetInfo(void *pInstance);              ///< Get supported gamma type from driver (without Mutex protect)

// initial functions
PNL_Result MDrv_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam);
PNL_Result MDrv_PNL_Init(void *pInstance);       ///< initialize panel driver
PNL_Result MDrv_PNL_IOMapBaseInit(void *pInstance);
PNL_Result MDrv_PNL_Close(void *pInstance);                                                            ///< close panel driver and release resources

//DRV_PNL_INTERFACE void MDrv_PNL_TCONMAP_DumpTable(MS_U8 *pTCONTable, MS_U8 u8Tcontype);
//DRV_PNL_INTERFACE void MDrv_PNL_TCONMAP_Power_Sequence(MS_U8 *pTCONTable, MS_BOOL bEnable);
void MDrv_PNL_TCON_DumpSCRegTab(void *pInstance, MS_U8* pu8TconTab,MS_U16 u16RegisterCount);
void MDrv_PNL_TCON_DumpMODRegTab(void *pInstance, MS_U8* pu8TconTab,MS_U16 u16RegisterCount);
void MDrv_PNL_TCON_DumpGENRegTab(void *pInstance, MS_U8* pu8TconTab,MS_U16 u16RegisterCount);
void MDrv_PNL_TCON_DumpOverDriveRegTab(void *pInstance, MS_U8* pu8TconTab);
void MDrv_PNL_TCON_DumpPowerSequenceRegTab(void *pInstance, MS_U8* pu8TconTab,MS_U16 u16RegisterCount);
void MDrv_PNL_TCON_DumpPanelInfo(void *pInstance,MS_U8* pTCONTable,MS_U32 u32RegisterlistSize);
void MDrv_PNL_TCON_ReSet_PanelConig(void *pInstance);


DRV_PNL_INTERFACE void MDrv_PNL_TCON_Count_Reset(void *pInstance, MS_BOOL bEnable);
DRV_PNL_INTERFACE void MDrv_PNL_TCON_Init(void *pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_GetDataFromRegister(void *pInstance, PNL_TimingInfo *PNLTiming);

// control & setting functions
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_En(void *pInstance, MS_BOOL bPanelOn);                            ///< bPanelOn = TRUE to show up OSD & video

#define MDrv_PNL_MOD_Calibration  MHal_PNL_MOD_Calibration
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_MOD_Calibration(void *pInstance);

DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetGammaTbl(void *pInstance, DRVPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3], DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); ///< set gamma table
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_GetGammaTbl(void *pInstance, DRVPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3],DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); ///< get gamma table
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_GetGammaTblEx(void *pInstance, ST_PNL_GAMMATBL *pstGetGammaTbl); ///< get gamma table
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16Offset, MS_U16 u16GammaValue);
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable);
DRV_PNL_INTERFACE void MDrv_PNL_MFC(void *pInstance, MS_BOOL bIsMFC);
DRV_PNL_INTERFACE void MDrv_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue);
DRV_PNL_INTERFACE void MDrv_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type);
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetPanelType(void *pInstance, PNL_InitData *pstPanelInitData);

DRV_PNL_INTERFACE void MDrv_PNL_SetSSC_Rdeviation(void *pInstance, MS_U16 u16Rdeviation);
DRV_PNL_INTERFACE void MDrv_PNL_SetSSC_Fmodulation(void *pInstance, MS_U16 u16Fmodulation);
DRV_PNL_INTERFACE void MDrv_PNL_SetSSC_En(void *pInstance, MS_BOOL bEnable);

DRV_PNL_INTERFACE void MDrv_PNL_SetOSDSSC_Rdeviation(void *pInstance, MS_U16 u16Rdeviation);
DRV_PNL_INTERFACE void MDrv_PNL_SetOSDSSC_Fmodulation(void *pInstance, MS_U16 u16Fmodulation);
DRV_PNL_INTERFACE void MDrv_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable);

DRV_PNL_INTERFACE void MDrv_Mod_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData);
DRV_PNL_INTERFACE void MDrv_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type);
DRV_PNL_INTERFACE MS_U16 MDrv_PNL_GetCurrentSwingLevel(void *pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Update_Ini_Para(void *pInstance, ST_PNL_INI_PARA *pstPnlPara);
DRV_PNL_INTERFACE MS_BOOL  MDrv_PNL_Control_Out_Swing_Channel(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_SkipTimingChange_GetCaps(void *pInstance);
DRV_PNL_INTERFACE void  MDrv_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode);

DRV_PNL_INTERFACE void MDrv_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo);
DRV_PNL_INTERFACE void MDrv_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_LSB_Addr, MS_U8 u8ODTbl[1056]);
#ifdef ROLLS_ROYCE
DRV_PNL_INTERFACE void MDrv_PNL_OverDriver_Setting(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_LSB_Addr, MS_U8* pu8ODTbl, MS_U32 u32ODTabSize,MS_U16 u16SepatateMode);
#else
DRV_PNL_INTERFACE void MDrv_PNL_OverDriver_Setting(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_LSB_Addr, MS_U16* pu16ODTbl, MS_U32 u32ODTabSize,MS_U16 u16SepatateMode);
#endif
DRV_PNL_INTERFACE void MDrv_PNL_OverDriver_Enable(void *pInstance, EN_PNL_OVERDRIVE_MODE enOverdriveMode);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_OverDriver_IsEnableRGBW(void *pInstance);
DRV_PNL_INTERFACE MS_U32 MDrv_PNL_CalculateLPLLSETbyDClk(void *pInstance, MS_U64 ldHz, MS_BOOL bHighAccurate);

#define MDrv_MOD_PVDD_Power_Setting  MHal_MOD_PVDD_Power_Setting
DRV_PNL_INTERFACE void MDrv_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5);

#define MDrv_PNL_MISC_Control  MHal_PNL_MISC_Control
DRV_PNL_INTERFACE void MDrv_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC);

DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Is_SupportFRC(void *pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Is_SupportTCON(void *pInstance);
DRV_PNL_INTERFACE void MDrv_FRC_MOD_ForcePairSwap(void *pInstance, MS_U32 u32Polarity);
MS_U16 MDrv_PNL_Get_DEVstart(void *pInstance);
MS_U16 MDrv_PNL_Get_DEHstart(void *pInstance);
MS_U16 MDrv_PNL_GetDefaultVfreq(void *pInstance, MS_U16 u16Vfreq);
MS_BOOL MDrv_PNL_isYUVOutput(void *pInstance);
MS_BOOL MDrv_PNL_GetDACOut(void *pInstance);

void MDrv_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz);

MS_BOOL MDrv_PNL_EnableInternalTermination(void *pInstance, MS_BOOL bEnable);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_VBY1_Handshake(void *pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_VBY1_OC_Handshake(void *pInstance);
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable);
DRV_PNL_INTERFACE void MDrv_PNL_GetOutputInterlaceTiming(void *pInstance, MS_BOOL* bIsInterlaceOutput);
DRV_PNL_INTERFACE void MDrv_PNL_SetOSDCOutputType(void *pInstance, MS_U16 eLPLL_Type, MS_U8 eOC_OutputFormat);
DRV_PNL_INTERFACE MS_U32 MDrv_PNL_Get_Semaphore(void *pInstance,E_PNL_POOL_ID eID);
DRV_PNL_INTERFACE MS_U32 MDrv_PNL_Release_Semaphore(void *pInstance,E_PNL_POOL_ID eID);
DRV_PNL_INTERFACE MS_U32 MDrv_PNL_GetDeviceNum(void);
DRV_PNL_INTERFACE MS_U16 MDrv_PNL_GetPanelVStart(void);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Check_VBY1_Handshake_Status(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select);
DRV_PNL_INTERFACE void MDrv_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable);
DRV_PNL_INTERFACE const char* MDrv_PNL_GetName(void);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_PowerDownLPLL(void *pInstance,MS_BOOL bEnable);
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetPanelGammaBIN(void *pInstance,MS_U8* u8GammaTbl,MS_U32 u32Size,MS_U8 u8Index);
DRV_PNL_INTERFACE void MDrv_PNL_Set_SSC_EnableHighAccurate(void *pInstance, MS_BOOL bEnable);
MS_BOOL MDrv_PNL_TCON_DumpPCIDRegTab(void *pInstance, MS_U8* pu8TconTab);
MS_BOOL MDrv_PNL_TCON_DumpLineODLutTab(void *pInstance, MS_U8* pu8TconTab);
MS_BOOL MDrv_PNL_TCON_DumpLineODRegTab(void *pInstance, MS_U8* pu8TconTab, MS_U16 u16RegisterCount);
MS_BOOL MDrv_PNL_TCON_DumpRegTab(void *pInstance, MS_U8* pu8TconTab, MS_U16 u16RegisterCount);

DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_SetPolInvertThreshold(void *pInstance, MS_U8 u8OsdThreshold, MS_U8 u8VideoThreshold, MS_U8 u8MotionThreshold);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_PolInvert(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_SetMirrorMode(void *pInstance, ST_PNL_MIRRORINFO *pstPnlMirrorInfo);
DRV_PNL_INTERFACE void MDrv_PNL_GetMirrorStatus(void *pInstance, ST_PNL_MIRRORINFO *pstPnlMirrorInfo);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_GetPanelGammaTbl(void* pInstance,ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_SetPanelGammaTbl(void* pInstance,ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_STR_StoreSetting(void* pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_STR_RecoverSetting(void* pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_StorePECfg(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_RecoverPECfg(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_StoreSwingCfg(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_RecoverSwingCfg(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_StoreFreeSwapCfg(void *pInstance);
DRV_PNL_INTERFACE void MDrv_PNL_RecoverFreeSwapCfg(void *pInstance);
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetVRRInfo(void *pInstance, ST_PNL_VRR_INFO *pstVrrInfo);
DRV_PNL_INTERFACE PNL_Result MDrv_PNL_GetMODSTATUS(void* pInstance,ST_PNL_MODSTATUS *pstGetMODRSTATUS);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_CheckOutputConfig(void* pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_NeedVsyncFront(void);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_VsyncShift(void);
#ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
//-------------------------------------------------------------------------------------------------
/// For Procfs Debug Message
//-------------------------------------------------------------------------------------------------
DRV_PNL_INTERFACE void MDrv_PNLMdbIoctl_EchoCmd(MDBCMD_CMDLINE_PARAMETER *paraCmdLine);
DRV_PNL_INTERFACE void MDrv_PNLMdbIoctl_Cat(MDBCMD_GETINFO_PARAMETER *paraGetInfo);
#endif
DRV_PNL_INTERFACE void MDrv_PNL_EfuseMPLL(MS_BOOL bEnable);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_MIPI_UpdateDsiPnlTiming(void *pInstance);
DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_MIPI_DumpDcsBin(void *pInstance, MS_U8* pu8TMipiDcsTab);
#endif // _DRV_PNL_H_

