/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_REG00_PM_H
#define _DT_BINDINGS_CLK_MT5896_REG00_PM_H

#define ckgen00_pm(Offset) Offset

#define reg_ckg_cm4 ckgen00_pm(0x0000)
#define reg_ckg_cm4_s 0
#define reg_ckg_cm4_e 3
#define reg_ckg_cm4_core ckgen00_pm(0x0004)
#define reg_ckg_cm4_core_s 0
#define reg_ckg_cm4_core_e 3
#define reg_ckg_cm4_dfs ckgen00_pm(0x0008)
#define reg_ckg_cm4_dfs_s 0
#define reg_ckg_cm4_dfs_e 3
#define reg_ckg_cm4_systick ckgen00_pm(0x000C)
#define reg_ckg_cm4_systick_s 0
#define reg_ckg_cm4_systick_e 2
#define reg_ckg_cm4_tck ckgen00_pm(0x0010)
#define reg_ckg_cm4_tck_s 0
#define reg_ckg_cm4_tck_e 2
#define reg_ckg_cm4_tsvalueb ckgen00_pm(0x0014)
#define reg_ckg_cm4_tsvalueb_s 0
#define reg_ckg_cm4_tsvalueb_e 2
#define reg_ckg_codec_i2s_mck ckgen00_pm(0x0018)
#define reg_ckg_codec_i2s_mck_s 0
#define reg_ckg_codec_i2s_mck_e 3
#define reg_ckg_codec_i2s_rx_bck ckgen00_pm(0x001C)
#define reg_ckg_codec_i2s_rx_bck_s 0
#define reg_ckg_codec_i2s_rx_bck_e 4
#define reg_ckg_codec_i2s_rx_ms_bck_p ckgen00_pm(0x0020)
#define reg_ckg_codec_i2s_rx_ms_bck_p_s 0
#define reg_ckg_codec_i2s_rx_ms_bck_p_e 4
#define reg_ckg_dig_mic ckgen00_pm(0x0024)
#define reg_ckg_dig_mic_s 0
#define reg_ckg_dig_mic_e 3
#define reg_ckg_i2s_rx_bck_dg ckgen00_pm(0x0028)
#define reg_ckg_i2s_rx_bck_dg_s 0
#define reg_ckg_i2s_rx_bck_dg_e 4
#define reg_ckg_nf_synth_ref ckgen00_pm(0x002C)
#define reg_ckg_nf_synth_ref_s 0
#define reg_ckg_nf_synth_ref_e 4
#define reg_ckg_paganini_imi ckgen00_pm(0x0030)
#define reg_ckg_paganini_imi_s 0
#define reg_ckg_paganini_imi_e 3
#define reg_ckg_paganini_imi_dfs ckgen00_pm(0x0034)
#define reg_ckg_paganini_imi_dfs_s 0
#define reg_ckg_paganini_imi_dfs_e 3
#define reg_ckg_pll2pagadiv ckgen00_pm(0x0038)
#define reg_ckg_pll2pagadiv_s 0
#define reg_ckg_pll2pagadiv_e 2
#define reg_ckg_src_a1_256fsi ckgen00_pm(0x003C)
#define reg_ckg_src_a1_256fsi_s 0
#define reg_ckg_src_a1_256fsi_e 3
#define reg_ckg_paga_pll_sel ckgen00_pm(0x0040)
#define reg_ckg_paga_pll_sel_s 0
#define reg_ckg_paga_pll_sel_e 4
#define reg_ckg_vrec_mac ckgen00_pm(0x0044)
#define reg_ckg_vrec_mac_s 0
#define reg_ckg_vrec_mac_e 4
#define reg_ckg_xtal_24m_paganini ckgen00_pm(0x0048)
#define reg_ckg_xtal_24m_paganini_s 0
#define reg_ckg_xtal_24m_paganini_e 1
#define reg_ckg_paganini_imi_div2 ckgen00_pm(0x004C)
#define reg_ckg_paganini_imi_div2_s 0
#define reg_ckg_paganini_imi_div2_e 2
#define reg_ckg_smi_pm ckgen00_pm(0x0058)
#define reg_ckg_smi_pm_s 0
#define reg_ckg_smi_pm_e 1
#define reg_ckg_smi_pm_usb_pcie ckgen00_pm(0x0058)
#define reg_ckg_smi_pm_usb_pcie_s 8
#define reg_ckg_smi_pm_usb_pcie_e 9
#define reg_ckg_smi_div2_pm ckgen00_pm(0x005C)
#define reg_ckg_smi_div2_pm_s 0
#define reg_ckg_smi_div2_pm_e 1
#define reg_ckg_cec ckgen00_pm(0x0070)
#define reg_ckg_cec_s 0
#define reg_ckg_cec_e 3
#define reg_ckg_cec1 ckgen00_pm(0x0074)
#define reg_ckg_cec1_s 0
#define reg_ckg_cec1_e 3
#define reg_ckg_cec2 ckgen00_pm(0x0078)
#define reg_ckg_cec2_s 0
#define reg_ckg_cec2_e 3
#define reg_ckg_cec3 ckgen00_pm(0x007C)
#define reg_ckg_cec3_s 0
#define reg_ckg_cec3_e 3
#define reg_ckg_ddc ckgen00_pm(0x0080)
#define reg_ckg_ddc_s 0
#define reg_ckg_ddc_e 4
#define reg_ckg_dvi_raw0 ckgen00_pm(0x0084)
#define reg_ckg_dvi_raw0_s 0
#define reg_ckg_dvi_raw0_e 2
#define reg_ckg_dvi_raw1 ckgen00_pm(0x0088)
#define reg_ckg_dvi_raw1_s 0
#define reg_ckg_dvi_raw1_e 2
#define reg_ckg_dvi_raw2 ckgen00_pm(0x008C)
#define reg_ckg_dvi_raw2_s 0
#define reg_ckg_dvi_raw2_e 2
#define reg_ckg_dvi_raw3 ckgen00_pm(0x0090)
#define reg_ckg_dvi_raw3_s 0
#define reg_ckg_dvi_raw3_e 2
#define reg_ckg_hotplug ckgen00_pm(0x0094)
#define reg_ckg_hotplug_s 0
#define reg_ckg_hotplug_e 3
#define reg_ckg_scdc_p0 ckgen00_pm(0x0098)
#define reg_ckg_scdc_p0_s 0
#define reg_ckg_scdc_p0_e 1
#define reg_ckg_scdc_p1 ckgen00_pm(0x009C)
#define reg_ckg_scdc_p1_s 0
#define reg_ckg_scdc_p1_e 1
#define reg_ckg_scdc_p2 ckgen00_pm(0x00A0)
#define reg_ckg_scdc_p2_s 0
#define reg_ckg_scdc_p2_e 1
#define reg_ckg_scdc_p3 ckgen00_pm(0x00A4)
#define reg_ckg_scdc_p3_s 0
#define reg_ckg_scdc_p3_e 1
#define reg_ckg_sd ckgen00_pm(0x00C8)
#define reg_ckg_sd_s 0
#define reg_ckg_sd_e 4
#define reg_ckg_gmac_rx ckgen00_pm(0x00D4)
#define reg_ckg_gmac_rx_s 0
#define reg_ckg_gmac_rx_e 3
#define reg_ckg_gmac_tx ckgen00_pm(0x00D8)
#define reg_ckg_gmac_tx_s 0
#define reg_ckg_gmac_tx_e 3
#define reg_ckg_mcu_bus_pm ckgen00_pm(0x00E8)
#define reg_ckg_mcu_bus_pm_s 0
#define reg_ckg_mcu_bus_pm_e 4
#define reg_ckg_mcu_pm ckgen00_pm(0x00EC)
#define reg_ckg_mcu_pm_s 0
#define reg_ckg_mcu_pm_e 4
#define reg_ckg_mcu_pm_paganini ckgen00_pm(0x00EC)
#define reg_ckg_mcu_pm_paganini_s 8
#define reg_ckg_mcu_pm_paganini_e 9
#define reg_ckg_mcu_pm_pm_usb_pcie ckgen00_pm(0x00EC)
#define reg_ckg_mcu_pm_pm_usb_pcie_s 10
#define reg_ckg_mcu_pm_pm_usb_pcie_e 11
#define reg_ckg_miic0_pm ckgen00_pm(0x00F0)
#define reg_ckg_miic0_pm_s 0
#define reg_ckg_miic0_pm_e 3
#define reg_ckg_miic1_pm ckgen00_pm(0x00F4)
#define reg_ckg_miic1_pm_s 0
#define reg_ckg_miic1_pm_e 3
#define reg_ckg_spi_pm ckgen00_pm(0x00F8)
#define reg_ckg_spi_pm_s 0
#define reg_ckg_spi_pm_e 4
#define reg_ckg_uart0_pm ckgen00_pm(0x00FC)
#define reg_ckg_uart0_pm_s 0
#define reg_ckg_uart0_pm_e 3
#define reg_ckg_uart0_pm_synth ckgen00_pm(0x0100)
#define reg_ckg_uart0_pm_synth_s 0
#define reg_ckg_uart0_pm_synth_e 3
#define reg_ckg_uart1_pm ckgen00_pm(0x0104)
#define reg_ckg_uart1_pm_s 0
#define reg_ckg_uart1_pm_e 3
#define reg_ckg_uart1_pm_synth ckgen00_pm(0x0108)
#define reg_ckg_uart1_pm_synth_s 0
#define reg_ckg_uart1_pm_synth_e 3
#define reg_ckg_fuart0_pm ckgen00_pm(0x010C)
#define reg_ckg_fuart0_pm_s 0
#define reg_ckg_fuart0_pm_e 3
#define reg_ckg_fuart0_pm_synth ckgen00_pm(0x0110)
#define reg_ckg_fuart0_pm_synth_s 0
#define reg_ckg_fuart0_pm_synth_e 3
#define reg_ckg_xiu2sram ckgen00_pm(0x0114)
#define reg_ckg_xiu2sram_s 0
#define reg_ckg_xiu2sram_e 2
#define reg_ckg_ir ckgen00_pm(0x0148)
#define reg_ckg_ir_s 0
#define reg_ckg_ir_e 4
#define reg_ckg_kref ckgen00_pm(0x0158)
#define reg_ckg_kref_s 0
#define reg_ckg_kref_e 3
#define reg_ckg_rtc2 ckgen00_pm(0x015C)
#define reg_ckg_rtc2_s 0
#define reg_ckg_rtc2_e 1
#define reg_ckg_rtc ckgen00_pm(0x0160)
#define reg_ckg_rtc_s 0
#define reg_ckg_rtc_e 4
#define reg_ckg_sar ckgen00_pm(0x0164)
#define reg_ckg_sar_s 0
#define reg_ckg_sar_e 4
#define reg_ckg_pm_sleep ckgen00_pm(0x0168)
#define reg_ckg_pm_sleep_s 0
#define reg_ckg_pm_sleep_e 4
#define reg_ckg_pwm_pm ckgen00_pm(0x0184)
#define reg_ckg_pwm_pm_s 0
#define reg_ckg_pwm_pm_e 2
#define reg_ckg_pm_ssusb_dma_ctl ckgen00_pm(0x0190)
#define reg_ckg_pm_ssusb_dma_ctl_s 0
#define reg_ckg_pm_ssusb_dma_ctl_e 1
#define reg_ckg_pm_ssusb_frmcnt_ctl ckgen00_pm(0x0194)
#define reg_ckg_pm_ssusb_frmcnt_ctl_s 0
#define reg_ckg_pm_ssusb_frmcnt_ctl_e 2
#define reg_ckg_pm_ssusb_pclk_ctl ckgen00_pm(0x0198)
#define reg_ckg_pm_ssusb_pclk_ctl_s 0
#define reg_ckg_pm_ssusb_pclk_ctl_e 2
#define reg_ckg_pm_ssusb_scl_ctl ckgen00_pm(0x019C)
#define reg_ckg_pm_ssusb_scl_ctl_s 0
#define reg_ckg_pm_ssusb_scl_ctl_e 2
#define reg_ckg_pm_ssusb_sdin_ctl ckgen00_pm(0x01A0)
#define reg_ckg_pm_ssusb_sdin_ctl_s 0
#define reg_ckg_pm_ssusb_sdin_ctl_e 2
#define reg_ckg_pm_ssusb_sys_ctl ckgen00_pm(0x01A4)
#define reg_ckg_pm_ssusb_sys_ctl_s 0
#define reg_ckg_pm_ssusb_sys_ctl_e 1
#define reg_ckg_pm_ssusb_utmi_ctl ckgen00_pm(0x01A8)
#define reg_ckg_pm_ssusb_utmi_ctl_s 0
#define reg_ckg_pm_ssusb_utmi_ctl_e 2
#define reg_ckg_pm_ssusb_xhci_ctl ckgen00_pm(0x01AC)
#define reg_ckg_pm_ssusb_xhci_ctl_s 0
#define reg_ckg_pm_ssusb_xhci_ctl_e 1
#define reg_ckg_pm_pextp ckgen00_pm(0x01B0)
#define reg_ckg_pm_pextp_s 0
#define reg_ckg_pm_pextp_e 3
#define reg_pm_test_enable ckgen00_pm(0x01C0)
#define reg_pm_test_enable_s 0
#define reg_pm_test_enable_e 0
#define reg_pm_test_div_sel ckgen00_pm(0x01C0)
#define reg_pm_test_div_sel_s 4
#define reg_pm_test_div_sel_e 6
#define reg_pm_test_src_sel ckgen00_pm(0x01C0)
#define reg_pm_test_src_sel_s 8
#define reg_pm_test_src_sel_e 15
#define reg_pm_usb_pcie_test_enable ckgen00_pm(0x01C4)
#define reg_pm_usb_pcie_test_enable_s 0
#define reg_pm_usb_pcie_test_enable_e 0
#define reg_pm_usb_pcie_test_div_sel ckgen00_pm(0x01C4)
#define reg_pm_usb_pcie_test_div_sel_s 4
#define reg_pm_usb_pcie_test_div_sel_e 6
#define reg_pm_usb_pcie_test_src_sel ckgen00_pm(0x01C4)
#define reg_pm_usb_pcie_test_src_sel_s 8
#define reg_pm_usb_pcie_test_src_sel_e 15
#define reg_pm_eth_test_enable ckgen00_pm(0x01C8)
#define reg_pm_eth_test_enable_s 0
#define reg_pm_eth_test_enable_e 0
#define reg_pm_eth_test_div_sel ckgen00_pm(0x01C8)
#define reg_pm_eth_test_div_sel_s 4
#define reg_pm_eth_test_div_sel_e 6
#define reg_pm_eth_test_src_sel ckgen00_pm(0x01C8)
#define reg_pm_eth_test_src_sel_s 8
#define reg_pm_eth_test_src_sel_e 15
#define reg_pm_ephy_test_enable ckgen00_pm(0x01CC)
#define reg_pm_ephy_test_enable_s 0
#define reg_pm_ephy_test_enable_e 0
#define reg_pm_ephy_test_div_sel ckgen00_pm(0x01CC)
#define reg_pm_ephy_test_div_sel_s 4
#define reg_pm_ephy_test_div_sel_e 6
#define reg_pm_ephy_test_src_sel ckgen00_pm(0x01CC)
#define reg_pm_ephy_test_src_sel_s 8
#define reg_pm_ephy_test_src_sel_e 15
#define reg_paganini_test_enable ckgen00_pm(0x01D0)
#define reg_paganini_test_enable_s 0
#define reg_paganini_test_enable_e 0
#define reg_paganini_test_div_sel ckgen00_pm(0x01D0)
#define reg_paganini_test_div_sel_s 4
#define reg_paganini_test_div_sel_e 6
#define reg_paganini_test_src_sel ckgen00_pm(0x01D0)
#define reg_paganini_test_src_sel_s 8
#define reg_paganini_test_src_sel_e 15
#define reg_ckgen00_pm_dummy0 ckgen00_pm(0x01F8)
#define reg_ckgen00_pm_dummy0_s 0
#define reg_ckgen00_pm_dummy0_e 15
#define reg_ckgen00_pm_dummy1 ckgen00_pm(0x01FC)
#define reg_ckgen00_pm_dummy1_s 0
#define reg_ckgen00_pm_dummy1_e 15

#endif
