/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_REG01_H
#define _DT_BINDINGS_CLK_MT5896_REG01_H

#define ckgen01(x)     (x+0x2000)

#define reg_ckg_adc2miu ckgen01(0x0000)
#define reg_ckg_adc2miu_s 0
#define reg_ckg_adc2miu_e 3
#define reg_ckg_adc2miusc ckgen01(0x0008)
#define reg_ckg_adc2miusc_s 0
#define reg_ckg_adc2miusc_e 3
#define reg_ckg_adc2sc ckgen01(0x0010)
#define reg_ckg_adc2sc_s 0
#define reg_ckg_adc2sc_e 3
#define reg_ckg_adc ckgen01(0x0018)
#define reg_ckg_adc_s 0
#define reg_ckg_adc_e 2
#define reg_ckg_adcpll200 ckgen01(0x0020)
#define reg_ckg_adcpll200_s 0
#define reg_ckg_adcpll200_e 1
#define reg_ckg_adcpll400 ckgen01(0x0028)
#define reg_ckg_adcpll400_s 0
#define reg_ckg_adcpll400_e 1
#define reg_ckg_adcpllb_mpll_216m ckgen01(0x0030)
#define reg_ckg_adcpllb_mpll_216m_s 0
#define reg_ckg_adcpllb_mpll_216m_e 1
#define reg_ckg_b_adc ckgen01(0x0038)
#define reg_ckg_b_adc_s 0
#define reg_ckg_b_adc_e 3
#define reg_ckg_b_int ckgen01(0x0040)
#define reg_ckg_b_int_s 0
#define reg_ckg_b_int_e 3
#define reg_ckg_clk_tstbus_div ckgen01(0x0048)
#define reg_ckg_clk_tstbus_div_s 0
#define reg_ckg_clk_tstbus_div_e 1
#define reg_ckg_clkd_adc_p ckgen01(0x0058)
#define reg_ckg_clkd_adc_p_s 0
#define reg_ckg_clkd_adc_p_e 3
#define reg_ckg_clkd_atop ckgen01(0x0060)
#define reg_ckg_clkd_atop_s 0
#define reg_ckg_clkd_atop_e 3
#define reg_ckg_clkd_atop_internal ckgen01(0x0068)
#define reg_ckg_clkd_atop_internal_s 0
#define reg_ckg_clkd_atop_internal_e 3
#define reg_ckg_clkpll ckgen01(0x0070)
#define reg_ckg_clkpll_s 0
#define reg_ckg_clkpll_e 1
#define reg_ckg_cvbs_dac_a_digital0 ckgen01(0x0078)
#define reg_ckg_cvbs_dac_a_digital0_s 0
#define reg_ckg_cvbs_dac_a_digital0_e 2
#define reg_ckg_cvbs_dac_a_digital0_mux ckgen01(0x0080)
#define reg_ckg_cvbs_dac_a_digital0_mux_s 0
#define reg_ckg_cvbs_dac_a_digital0_mux_e 2
#define reg_ckg_cvbs_dac_a_digital1 ckgen01(0x0088)
#define reg_ckg_cvbs_dac_a_digital1_s 0
#define reg_ckg_cvbs_dac_a_digital1_e 2
#define reg_ckg_dig_108 ckgen01(0x0090)
#define reg_ckg_dig_108_s 0
#define reg_ckg_dig_108_e 1
#define reg_ckg_dig_216 ckgen01(0x0098)
#define reg_ckg_dig_216_s 0
#define reg_ckg_dig_216_e 1
#define reg_ckg_fblank ckgen01(0x00A0)
#define reg_ckg_fblank_s 0
#define reg_ckg_fblank_e 2
#define reg_ckg_fsc_vd ckgen01(0x00A8)
#define reg_ckg_fsc_vd_s 0
#define reg_ckg_fsc_vd_e 1
#define reg_ckg_fscx2_fb2atop ckgen01(0x00B0)
#define reg_ckg_fscx2_fb2atop_s 0
#define reg_ckg_fscx2_fb2atop_e 2
#define reg_ckg_g_adc ckgen01(0x00B8)
#define reg_ckg_g_adc_s 0
#define reg_ckg_g_adc_e 3
#define reg_ckg_g_int ckgen01(0x00C0)
#define reg_ckg_g_int_s 0
#define reg_ckg_g_int_e 3
#define reg_ckg_iclamp_rgb ckgen01(0x00C8)
#define reg_ckg_iclamp_rgb_s 0
#define reg_ckg_iclamp_rgb_e 3
#define reg_ckg_isog ckgen01(0x00D0)
#define reg_ckg_isog_s 0
#define reg_ckg_isog_e 1
#define reg_ckg_nco_clk ckgen01(0x00E0)
#define reg_ckg_nco_clk_s 0
#define reg_ckg_nco_clk_e 1
#define reg_ckg_r_adc ckgen01(0x00F0)
#define reg_ckg_r_adc_s 0
#define reg_ckg_r_adc_e 3
#define reg_ckg_r_int ckgen01(0x00F8)
#define reg_ckg_r_int_s 0
#define reg_ckg_r_int_e 3
#define reg_ckg_vd_iclamp ckgen01(0x0108)
#define reg_ckg_vd_iclamp_s 0
#define reg_ckg_vd_iclamp_e 1
#define reg_ckg_vd_adcpll ckgen01(0x0110)
#define reg_ckg_vd_adcpll_s 0
#define reg_ckg_vd_adcpll_e 2
#define reg_ckg_vd_nco_clk ckgen01(0x0118)
#define reg_ckg_vd_nco_clk_s 0
#define reg_ckg_vd_nco_clk_e 1
#define reg_ckg_vdpll400 ckgen01(0x0120)
#define reg_ckg_vdpll400_s 0
#define reg_ckg_vdpll400_e 1
#define reg_ckg_xtal12_4interrupt ckgen01(0x0128)
#define reg_ckg_xtal12_4interrupt_s 0
#define reg_ckg_xtal12_4interrupt_e 1
#define reg_ckg_xtal12_4plugdet ckgen01(0x0130)
#define reg_ckg_xtal12_4plugdet_s 0
#define reg_ckg_xtal12_4plugdet_e 1
#define reg_ckg_xtal12 ckgen01(0x0138)
#define reg_ckg_xtal12_s 0
#define reg_ckg_xtal12_e 1
#define reg_ckg_xtal24 ckgen01(0x0140)
#define reg_ckg_xtal24_s 0
#define reg_ckg_xtal24_e 1
#define reg_ckg_y_adc ckgen01(0x0148)
#define reg_ckg_y_adc_s 0
#define reg_ckg_y_adc_e 2
#define reg_ckg_y_int ckgen01(0x0150)
#define reg_ckg_y_int_s 0
#define reg_ckg_y_int_e 2
#define reg_ckg_yuv_adc ckgen01(0x0158)
#define reg_ckg_yuv_adc_s 0
#define reg_ckg_yuv_adc_e 2
#define reg_ckg_adcplb_mpll_mheg5 ckgen01(0x0160)
#define reg_ckg_adcplb_mpll_mheg5_s 8
#define reg_ckg_adcplb_mpll_mheg5_e 9
#define reg_ckg_frc_fclk ckgen01(0x01E8)
#define reg_ckg_frc_fclk_s 0
#define reg_ckg_frc_fclk_e 3
#define reg_ckg_frc_fclk_frcmi ckgen01(0x01E8)
#define reg_ckg_frc_fclk_frcmi_s 4
#define reg_ckg_frc_fclk_frcmi_e 6
#define reg_ckg_frc_fclk_frciopmrv55 ckgen01(0x01E8)
#define reg_ckg_frc_fclk_frciopmrv55_s 8
#define reg_ckg_frc_fclk_frciopmrv55_e 9
#define reg_ckg_frc_fclk_frcmehalo ckgen01(0x01E8)
#define reg_ckg_frc_fclk_frcmehalo_s 10
#define reg_ckg_frc_fclk_frcmehalo_e 11
#define reg_ckg_frc_fclk_frcmemlb ckgen01(0x01E8)
#define reg_ckg_frc_fclk_frcmemlb_s 12
#define reg_ckg_frc_fclk_frcmemlb_e 13
#define reg_ckg_dap ckgen01(0x01EC)
#define reg_ckg_dap_s 0
#define reg_ckg_dap_e 1
#define reg_ckg_frc_fclk_2x ckgen01(0x01F0)
#define reg_ckg_frc_fclk_2x_s 0
#define reg_ckg_frc_fclk_2x_e 3
#define reg_ckg_frc_fclk_2x_frciopmrv55 ckgen01(0x01F0)
#define reg_ckg_frc_fclk_2x_frciopmrv55_s 8
#define reg_ckg_frc_fclk_2x_frciopmrv55_e 10
#define reg_ckg_frc_fclk_2x_frcmehalo ckgen01(0x01F4)
#define reg_ckg_frc_fclk_2x_frcmehalo_s 0
#define reg_ckg_frc_fclk_2x_frcmehalo_e 2
#define reg_ckg_frc_fclk_2xplus ckgen01(0x01F8)
#define reg_ckg_frc_fclk_2xplus_s 0
#define reg_ckg_frc_fclk_2xplus_e 3
#define reg_ckg_frc_fclk_2xplus_scmw ckgen01(0x01F8)
#define reg_ckg_frc_fclk_2xplus_scmw_s 12
#define reg_ckg_frc_fclk_2xplus_scmw_e 13
#define reg_ckg_frc_fclk_2xplus_scip ckgen01(0x01F8)
#define reg_ckg_frc_fclk_2xplus_scip_s 14
#define reg_ckg_frc_fclk_2xplus_scip_e 15
#define reg_ckg_rv55frc_rv55frc ckgen01(0x0200)
#define reg_ckg_rv55frc_rv55frc_s 0
#define reg_ckg_rv55frc_rv55frc_e 4
#define reg_ckg_rv55frc ckgen01(0x0208)
#define reg_ckg_rv55frc_s 0
#define reg_ckg_rv55frc_e 2
#define reg_ckg_rv55frc_frciopmrv55 ckgen01(0x0208)
#define reg_ckg_rv55frc_frciopmrv55_s 8
#define reg_ckg_rv55frc_frciopmrv55_e 9
#define reg_ckg_rv55frc_jtag_tck_frciopmrv55 ckgen01(0x0210)
#define reg_ckg_rv55frc_jtag_tck_frciopmrv55_s 0
#define reg_ckg_rv55frc_jtag_tck_frciopmrv55_e 1
#define reg_ckg_rv55frc_jtag_tck_rv55frc ckgen01(0x0210)
#define reg_ckg_rv55frc_jtag_tck_rv55frc_s 8
#define reg_ckg_rv55frc_jtag_tck_rv55frc_e 9
#define reg_ckg_rv55pqu_rv55pqu ckgen01(0x0218)
#define reg_ckg_rv55pqu_rv55pqu_s 0
#define reg_ckg_rv55pqu_rv55pqu_e 4
#define reg_ckg_rv55pqu ckgen01(0x0220)
#define reg_ckg_rv55pqu_s 0
#define reg_ckg_rv55pqu_e 2
#define reg_ckg_rv55pqu_frciopmrv55 ckgen01(0x0220)
#define reg_ckg_rv55pqu_frciopmrv55_s 8
#define reg_ckg_rv55pqu_frciopmrv55_e 9
#define reg_ckg_rv55pqu_jtag_tck_frciopmrv55 ckgen01(0x0228)
#define reg_ckg_rv55pqu_jtag_tck_frciopmrv55_s 0
#define reg_ckg_rv55pqu_jtag_tck_frciopmrv55_e 1
#define reg_ckg_rv55pqu_jtag_tck_rv55pqu ckgen01(0x0228)
#define reg_ckg_rv55pqu_jtag_tck_rv55pqu_s 8
#define reg_ckg_rv55pqu_jtag_tck_rv55pqu_e 9
#define reg_ckg_xcsrspll_syn ckgen01(0x0230)
#define reg_ckg_xcsrspll_syn_s 0
#define reg_ckg_xcsrspll_syn_e 3
#define reg_ckg_dap_frciopmrv55 ckgen01(0x0238)
#define reg_ckg_dap_frciopmrv55_s 0
#define reg_ckg_dap_frciopmrv55_e 1
#define reg_ckg_dap_rv55frc ckgen01(0x0238)
#define reg_ckg_dap_rv55frc_s 8
#define reg_ckg_dap_rv55frc_e 9
#define reg_ckg_dap_rv55pqu ckgen01(0x0238)
#define reg_ckg_dap_rv55pqu_s 10
#define reg_ckg_dap_rv55pqu_e 11
#define reg_ckg_rv55dap_jtag_tck_frciopmrv55 ckgen01(0x0240)
#define reg_ckg_rv55dap_jtag_tck_frciopmrv55_s 0
#define reg_ckg_rv55dap_jtag_tck_frciopmrv55_e 1
#define reg_ckg_xtal_24m_frcmemlb ckgen01(0x0248)
#define reg_ckg_xtal_24m_frcmemlb_s 0
#define reg_ckg_xtal_24m_frcmemlb_e 1
#define reg_ckg_xtal_24m_frcmi ckgen01(0x0250)
#define reg_ckg_xtal_24m_frcmi_s 0
#define reg_ckg_xtal_24m_frcmi_e 1
#define reg_ckg_xtal_12m_frciopmrv55 ckgen01(0x0258)
#define reg_ckg_xtal_12m_frciopmrv55_s 0
#define reg_ckg_xtal_12m_frciopmrv55_e 1
#define reg_ckg_xtal_24m_frciopmrv55 ckgen01(0x0260)
#define reg_ckg_xtal_24m_frciopmrv55_s 0
#define reg_ckg_xtal_24m_frciopmrv55_e 1
#define reg_ckg_xtal_24m_frcmehalo ckgen01(0x0268)
#define reg_ckg_xtal_24m_frcmehalo_s 0
#define reg_ckg_xtal_24m_frcmehalo_e 1
#define reg_ckg_xtal_12m_rv55frc ckgen01(0x0270)
#define reg_ckg_xtal_12m_rv55frc_s 0
#define reg_ckg_xtal_12m_rv55frc_e 1
#define reg_ckg_xtal_24m_rv55frc ckgen01(0x0278)
#define reg_ckg_xtal_24m_rv55frc_s 0
#define reg_ckg_xtal_24m_rv55frc_e 1
#define reg_ckg_xtal_12m_rv55pqu ckgen01(0x0280)
#define reg_ckg_xtal_12m_rv55pqu_s 0
#define reg_ckg_xtal_12m_rv55pqu_e 1
#define reg_ckg_xtal_24m_rv55pqu ckgen01(0x0288)
#define reg_ckg_xtal_24m_rv55pqu_s 0
#define reg_ckg_xtal_24m_rv55pqu_e 1
#define reg_ckg_ge ckgen01(0x02A0)
#define reg_ckg_ge_s 0
#define reg_ckg_ge_e 4
#define reg_ckg_hdmi_r2 ckgen01(0x02B0)
#define reg_ckg_hdmi_r2_s 0
#define reg_ckg_hdmi_r2_e 3
#define reg_ckg_hdmirx_timestamp ckgen01(0x02B8)
#define reg_ckg_hdmirx_timestamp_s 0
#define reg_ckg_hdmirx_timestamp_e 1
#define reg_ckg_128fs_fb_s0 ckgen01(0x02C0)
#define reg_ckg_128fs_fb_s0_s 0
#define reg_ckg_128fs_fb_s0_e 3
#define reg_ckg_128fs_fb_s1 ckgen01(0x02C8)
#define reg_ckg_128fs_fb_s1_s 0
#define reg_ckg_128fs_fb_s1_e 3
#define reg_ckg_128fs_s0 ckgen01(0x02D0)
#define reg_ckg_128fs_s0_s 0
#define reg_ckg_128fs_s0_e 3
#define reg_ckg_128fs_s1 ckgen01(0x02D8)
#define reg_ckg_128fs_s1_s 0
#define reg_ckg_128fs_s1_e 3
#define reg_ckg_216 ckgen01(0x02E0)
#define reg_ckg_216_s 0
#define reg_ckg_216_e 3
#define reg_ckg_256fs_s0 ckgen01(0x02E8)
#define reg_ckg_256fs_s0_s 0
#define reg_ckg_256fs_s0_e 2
#define reg_ckg_256fs_s1 ckgen01(0x02F0)
#define reg_ckg_256fs_s1_s 0
#define reg_ckg_256fs_s1_e 2
#define reg_ckg_432 ckgen01(0x02F8)
#define reg_ckg_432_s 0
#define reg_ckg_432_e 2
#define reg_ckg_864 ckgen01(0x0300)
#define reg_ckg_864_s 0
#define reg_ckg_864_e 2
#define reg_ckg_clk_det_inner_misc_0 ckgen01(0x0308)
#define reg_ckg_clk_det_inner_misc_0_s 0
#define reg_ckg_clk_det_inner_misc_0_e 4
#define reg_ckg_clk_det_inner_misc_0_0 ckgen01(0x0310)
#define reg_ckg_clk_det_inner_misc_0_0_s 0
#define reg_ckg_clk_det_inner_misc_0_0_e 4
#define reg_ckg_clk_det_inner_misc_1 ckgen01(0x0318)
#define reg_ckg_clk_det_inner_misc_1_s 0
#define reg_ckg_clk_det_inner_misc_1_e 3
#define reg_ckg_clk_det_inner_misc_1_0 ckgen01(0x0320)
#define reg_ckg_clk_det_inner_misc_1_0_s 0
#define reg_ckg_clk_det_inner_misc_1_0_e 4
#define reg_ckg_cts_synth_s0 ckgen01(0x0328)
#define reg_ckg_cts_synth_s0_s 0
#define reg_ckg_cts_synth_s0_e 3
#define reg_ckg_cts_synth_s0_0 ckgen01(0x0330)
#define reg_ckg_cts_synth_s0_0_s 0
#define reg_ckg_cts_synth_s0_0_e 4
#define reg_ckg_cts_synth_s1 ckgen01(0x0338)
#define reg_ckg_cts_synth_s1_s 0
#define reg_ckg_cts_synth_s1_e 3
#define reg_ckg_cts_synth_s1_0 ckgen01(0x0340)
#define reg_ckg_cts_synth_s1_0_s 0
#define reg_ckg_cts_synth_s1_0_e 4
#define reg_ckg_dsc_engine ckgen01(0x0348)
#define reg_ckg_dsc_engine_s 0
#define reg_ckg_dsc_engine_e 3
#define reg_ckg_dvi2miu_rd_s0 ckgen01(0x0350)
#define reg_ckg_dvi2miu_rd_s0_s 0
#define reg_ckg_dvi2miu_rd_s0_e 3
#define reg_ckg_dvi2miu_rd_s1 ckgen01(0x0358)
#define reg_ckg_dvi2miu_rd_s1_s 0
#define reg_ckg_dvi2miu_rd_s1_e 3
#define reg_ckg_dvi2miu_wr_s0 ckgen01(0x0360)
#define reg_ckg_dvi2miu_wr_s0_s 0
#define reg_ckg_dvi2miu_wr_s0_e 3
#define reg_ckg_dvi2miu_wr_s0_0 ckgen01(0x0368)
#define reg_ckg_dvi2miu_wr_s0_0_s 0
#define reg_ckg_dvi2miu_wr_s0_0_e 4
#define reg_ckg_dvi2miu_wr_s0_1 ckgen01(0x0370)
#define reg_ckg_dvi2miu_wr_s0_1_s 0
#define reg_ckg_dvi2miu_wr_s0_1_e 3
#define reg_ckg_dvi2miu_wr_s1 ckgen01(0x0398)
#define reg_ckg_dvi2miu_wr_s1_s 0
#define reg_ckg_dvi2miu_wr_s1_e 3
#define reg_ckg_dvi2miu_wr_s1_0 ckgen01(0x03A0)
#define reg_ckg_dvi2miu_wr_s1_0_s 0
#define reg_ckg_dvi2miu_wr_s1_0_e 4
#define reg_ckg_dvi2miu_wr_s1_1 ckgen01(0x03A8)
#define reg_ckg_dvi2miu_wr_s1_1_s 0
#define reg_ckg_dvi2miu_wr_s1_1_e 3
#define reg_ckg_earc_audio ckgen01(0x03D0)
#define reg_ckg_earc_audio_s 0
#define reg_ckg_earc_audio_e 2
#define reg_ckg_earc_cm ckgen01(0x03D8)
#define reg_ckg_earc_cm_s 0
#define reg_ckg_earc_cm_e 2
#define reg_ckg_earc_debounce ckgen01(0x03E0)
#define reg_ckg_earc_debounce_s 0
#define reg_ckg_earc_debounce_e 1
#define reg_ckg_earc_dm_prbs ckgen01(0x03E8)
#define reg_ckg_earc_dm_prbs_s 0
#define reg_ckg_earc_dm_prbs_e 2
#define reg_ckg_link_dscd ckgen01(0x03F0)
#define reg_ckg_link_dscd_s 0
#define reg_ckg_link_dscd_e 4
#define reg_ckg_p0_clk_det_dec_misc_0 ckgen01(0x03F8)
#define reg_ckg_p0_clk_det_dec_misc_0_s 0
#define reg_ckg_p0_clk_det_dec_misc_0_e 3
#define reg_ckg_p0_clk_det_dec_misc_0_0 ckgen01(0x0400)
#define reg_ckg_p0_clk_det_dec_misc_0_0_s 0
#define reg_ckg_p0_clk_det_dec_misc_0_0_e 3
#define reg_ckg_p0_clk_det_dec_misc_1 ckgen01(0x0408)
#define reg_ckg_p0_clk_det_dec_misc_1_s 0
#define reg_ckg_p0_clk_det_dec_misc_1_e 3
#define reg_ckg_p0_clk_det_dec_misc_1_0 ckgen01(0x0410)
#define reg_ckg_p0_clk_det_dec_misc_1_0_s 0
#define reg_ckg_p0_clk_det_dec_misc_1_0_e 3
#define reg_ckg_p0_clk_det_dep_misc_0 ckgen01(0x0418)
#define reg_ckg_p0_clk_det_dep_misc_0_s 0
#define reg_ckg_p0_clk_det_dep_misc_0_e 3
#define reg_ckg_p0_clk_det_dep_misc_0_0 ckgen01(0x0420)
#define reg_ckg_p0_clk_det_dep_misc_0_0_s 0
#define reg_ckg_p0_clk_det_dep_misc_0_0_e 3
#define reg_ckg_p0_clk_det_dep_misc_1 ckgen01(0x0428)
#define reg_ckg_p0_clk_det_dep_misc_1_s 0
#define reg_ckg_p0_clk_det_dep_misc_1_e 3
#define reg_ckg_p0_clk_det_dep_misc_1_0 ckgen01(0x0430)
#define reg_ckg_p0_clk_det_dep_misc_1_0_s 0
#define reg_ckg_p0_clk_det_dep_misc_1_0_e 3
#define reg_ckg_p0_link ckgen01(0x0438)
#define reg_ckg_p0_link_s 0
#define reg_ckg_p0_link_e 3
#define reg_ckg_p0_pix_1p ckgen01(0x0440)
#define reg_ckg_p0_pix_1p_s 0
#define reg_ckg_p0_pix_1p_e 3
#define reg_ckg_p0_pix_8p ckgen01(0x0448)
#define reg_ckg_p0_pix_8p_s 0
#define reg_ckg_p0_pix_8p_e 4
#define reg_ckg_p0_pix_dc_mux ckgen01(0x0450)
#define reg_ckg_p0_pix_dc_mux_s 0
#define reg_ckg_p0_pix_dc_mux_e 4
#define reg_ckg_p0_pix_rcv_mux ckgen01(0x0458)
#define reg_ckg_p0_pix_rcv_mux_s 0
#define reg_ckg_p0_pix_rcv_mux_e 4
#define reg_ckg_p0_pix_rep_1p ckgen01(0x0460)
#define reg_ckg_p0_pix_rep_1p_s 0
#define reg_ckg_p0_pix_rep_1p_e 3
#define reg_ckg_p0_pix_tmdspll ckgen01(0x0468)
#define reg_ckg_p0_pix_tmdspll_s 0
#define reg_ckg_p0_pix_tmdspll_e 3
#define reg_ckg_p0_pix_xc_mux ckgen01(0x0478)
#define reg_ckg_p0_pix_xc_mux_s 0
#define reg_ckg_p0_pix_xc_mux_e 3
#define reg_ckg_p0_timing_det_dec ckgen01(0x0480)
#define reg_ckg_p0_timing_det_dec_s 0
#define reg_ckg_p0_timing_det_dec_e 4
#define reg_ckg_p0_timing_det_dep ckgen01(0x0488)
#define reg_ckg_p0_timing_det_dep_s 0
#define reg_ckg_p0_timing_det_dep_e 4
#define reg_ckg_p0_timing_det_dtop ckgen01(0x0490)
#define reg_ckg_p0_timing_det_dtop_s 0
#define reg_ckg_p0_timing_det_dtop_e 3
#define reg_ckg_p0_tmds_frl_8p ckgen01(0x0498)
#define reg_ckg_p0_tmds_frl_8p_s 0
#define reg_ckg_p0_tmds_frl_8p_e 3
#define reg_ckg_p0_tmds_hdcp_1p ckgen01(0x04A0)
#define reg_ckg_p0_tmds_hdcp_1p_s 0
#define reg_ckg_p0_tmds_hdcp_1p_e 3
#define reg_ckg_p0_tmds_hdcp_4p ckgen01(0x04A8)
#define reg_ckg_p0_tmds_hdcp_4p_s 0
#define reg_ckg_p0_tmds_hdcp_4p_e 3
#define reg_ckg_p0_tmds_hdcp_8p ckgen01(0x04B0)
#define reg_ckg_p0_tmds_hdcp_8p_s 0
#define reg_ckg_p0_tmds_hdcp_8p_e 3
#define reg_ckg_p0_tmds_hdcp_mux ckgen01(0x04B8)
#define reg_ckg_p0_tmds_hdcp_mux_s 0
#define reg_ckg_p0_tmds_hdcp_mux_e 3
#define reg_ckg_p0_tmds_hdmi_1p ckgen01(0x04C0)
#define reg_ckg_p0_tmds_hdmi_1p_s 0
#define reg_ckg_p0_tmds_hdmi_1p_e 3
#define reg_ckg_p0_tmds_hdmi_8p ckgen01(0x04C8)
#define reg_ckg_p0_tmds_hdmi_8p_s 0
#define reg_ckg_p0_tmds_hdmi_8p_e 3
#define reg_ckg_p0_tmds_hdmi_mux ckgen01(0x04D0)
#define reg_ckg_p0_tmds_hdmi_mux_s 0
#define reg_ckg_p0_tmds_hdmi_mux_e 3
#define reg_ckg_p1_clk_det_dec_misc_0 ckgen01(0x04D8)
#define reg_ckg_p1_clk_det_dec_misc_0_s 0
#define reg_ckg_p1_clk_det_dec_misc_0_e 3
#define reg_ckg_p1_clk_det_dec_misc_0_0 ckgen01(0x04E0)
#define reg_ckg_p1_clk_det_dec_misc_0_0_s 0
#define reg_ckg_p1_clk_det_dec_misc_0_0_e 3
#define reg_ckg_p1_clk_det_dec_misc_1 ckgen01(0x04E8)
#define reg_ckg_p1_clk_det_dec_misc_1_s 0
#define reg_ckg_p1_clk_det_dec_misc_1_e 3
#define reg_ckg_p1_clk_det_dec_misc_1_0 ckgen01(0x04F0)
#define reg_ckg_p1_clk_det_dec_misc_1_0_s 0
#define reg_ckg_p1_clk_det_dec_misc_1_0_e 3
#define reg_ckg_p1_clk_det_dep_misc_0 ckgen01(0x04F8)
#define reg_ckg_p1_clk_det_dep_misc_0_s 0
#define reg_ckg_p1_clk_det_dep_misc_0_e 3
#define reg_ckg_p1_clk_det_dep_misc_0_0 ckgen01(0x0500)
#define reg_ckg_p1_clk_det_dep_misc_0_0_s 0
#define reg_ckg_p1_clk_det_dep_misc_0_0_e 3
#define reg_ckg_p1_clk_det_dep_misc_1 ckgen01(0x0508)
#define reg_ckg_p1_clk_det_dep_misc_1_s 0
#define reg_ckg_p1_clk_det_dep_misc_1_e 3
#define reg_ckg_p1_clk_det_dep_misc_1_0 ckgen01(0x0510)
#define reg_ckg_p1_clk_det_dep_misc_1_0_s 0
#define reg_ckg_p1_clk_det_dep_misc_1_0_e 3
#define reg_ckg_p1_link ckgen01(0x0518)
#define reg_ckg_p1_link_s 0
#define reg_ckg_p1_link_e 3
#define reg_ckg_p1_pix_1p ckgen01(0x0520)
#define reg_ckg_p1_pix_1p_s 0
#define reg_ckg_p1_pix_1p_e 3
#define reg_ckg_p1_pix_8p ckgen01(0x0528)
#define reg_ckg_p1_pix_8p_s 0
#define reg_ckg_p1_pix_8p_e 4
#define reg_ckg_p1_pix_dc_mux ckgen01(0x0530)
#define reg_ckg_p1_pix_dc_mux_s 0
#define reg_ckg_p1_pix_dc_mux_e 4
#define reg_ckg_p1_pix_rcv_mux ckgen01(0x0538)
#define reg_ckg_p1_pix_rcv_mux_s 0
#define reg_ckg_p1_pix_rcv_mux_e 4
#define reg_ckg_p1_pix_rep_1p ckgen01(0x0540)
#define reg_ckg_p1_pix_rep_1p_s 0
#define reg_ckg_p1_pix_rep_1p_e 3
#define reg_ckg_p1_pix_tmdspll ckgen01(0x0548)
#define reg_ckg_p1_pix_tmdspll_s 0
#define reg_ckg_p1_pix_tmdspll_e 3
#define reg_ckg_p1_pix_xc_mux ckgen01(0x0558)
#define reg_ckg_p1_pix_xc_mux_s 0
#define reg_ckg_p1_pix_xc_mux_e 3
#define reg_ckg_p1_timing_det_dec ckgen01(0x0560)
#define reg_ckg_p1_timing_det_dec_s 0
#define reg_ckg_p1_timing_det_dec_e 4
#define reg_ckg_p1_timing_det_dep ckgen01(0x0568)
#define reg_ckg_p1_timing_det_dep_s 0
#define reg_ckg_p1_timing_det_dep_e 4
#define reg_ckg_p1_timing_det_dtop ckgen01(0x0570)
#define reg_ckg_p1_timing_det_dtop_s 0
#define reg_ckg_p1_timing_det_dtop_e 3
#define reg_ckg_p1_tmds_frl_8p ckgen01(0x0578)
#define reg_ckg_p1_tmds_frl_8p_s 0
#define reg_ckg_p1_tmds_frl_8p_e 3
#define reg_ckg_p1_tmds_hdcp_1p ckgen01(0x0580)
#define reg_ckg_p1_tmds_hdcp_1p_s 0
#define reg_ckg_p1_tmds_hdcp_1p_e 3
#define reg_ckg_p1_tmds_hdcp_4p ckgen01(0x0588)
#define reg_ckg_p1_tmds_hdcp_4p_s 0
#define reg_ckg_p1_tmds_hdcp_4p_e 3
#define reg_ckg_p1_tmds_hdcp_8p ckgen01(0x0590)
#define reg_ckg_p1_tmds_hdcp_8p_s 0
#define reg_ckg_p1_tmds_hdcp_8p_e 3
#define reg_ckg_p1_tmds_hdcp_mux ckgen01(0x0598)
#define reg_ckg_p1_tmds_hdcp_mux_s 0
#define reg_ckg_p1_tmds_hdcp_mux_e 3
#define reg_ckg_p1_tmds_hdmi_1p ckgen01(0x05A0)
#define reg_ckg_p1_tmds_hdmi_1p_s 0
#define reg_ckg_p1_tmds_hdmi_1p_e 3
#define reg_ckg_p1_tmds_hdmi_8p ckgen01(0x05A8)
#define reg_ckg_p1_tmds_hdmi_8p_s 0
#define reg_ckg_p1_tmds_hdmi_8p_e 3
#define reg_ckg_p1_tmds_hdmi_mux ckgen01(0x05B0)
#define reg_ckg_p1_tmds_hdmi_mux_s 0
#define reg_ckg_p1_tmds_hdmi_mux_e 3
#define reg_ckg_p2_clk_det_dec_misc_0 ckgen01(0x05B8)
#define reg_ckg_p2_clk_det_dec_misc_0_s 0
#define reg_ckg_p2_clk_det_dec_misc_0_e 3
#define reg_ckg_p2_clk_det_dec_misc_0_0 ckgen01(0x05C0)
#define reg_ckg_p2_clk_det_dec_misc_0_0_s 0
#define reg_ckg_p2_clk_det_dec_misc_0_0_e 3
#define reg_ckg_p2_clk_det_dec_misc_1 ckgen01(0x05C8)
#define reg_ckg_p2_clk_det_dec_misc_1_s 0
#define reg_ckg_p2_clk_det_dec_misc_1_e 3
#define reg_ckg_p2_clk_det_dec_misc_1_0 ckgen01(0x05D0)
#define reg_ckg_p2_clk_det_dec_misc_1_0_s 0
#define reg_ckg_p2_clk_det_dec_misc_1_0_e 3
#define reg_ckg_p2_clk_det_dep_misc_0 ckgen01(0x05D8)
#define reg_ckg_p2_clk_det_dep_misc_0_s 0
#define reg_ckg_p2_clk_det_dep_misc_0_e 3
#define reg_ckg_p2_clk_det_dep_misc_0_0 ckgen01(0x05E0)
#define reg_ckg_p2_clk_det_dep_misc_0_0_s 0
#define reg_ckg_p2_clk_det_dep_misc_0_0_e 3
#define reg_ckg_p2_clk_det_dep_misc_1 ckgen01(0x05E8)
#define reg_ckg_p2_clk_det_dep_misc_1_s 0
#define reg_ckg_p2_clk_det_dep_misc_1_e 3
#define reg_ckg_p2_clk_det_dep_misc_1_0 ckgen01(0x05F0)
#define reg_ckg_p2_clk_det_dep_misc_1_0_s 0
#define reg_ckg_p2_clk_det_dep_misc_1_0_e 3
#define reg_ckg_p2_link ckgen01(0x05F8)
#define reg_ckg_p2_link_s 0
#define reg_ckg_p2_link_e 3
#define reg_ckg_p2_pix_1p ckgen01(0x0600)
#define reg_ckg_p2_pix_1p_s 0
#define reg_ckg_p2_pix_1p_e 3
#define reg_ckg_p2_pix_8p ckgen01(0x0608)
#define reg_ckg_p2_pix_8p_s 0
#define reg_ckg_p2_pix_8p_e 4
#define reg_ckg_p2_pix_dc_mux ckgen01(0x0610)
#define reg_ckg_p2_pix_dc_mux_s 0
#define reg_ckg_p2_pix_dc_mux_e 4
#define reg_ckg_p2_pix_rcv_mux ckgen01(0x0618)
#define reg_ckg_p2_pix_rcv_mux_s 0
#define reg_ckg_p2_pix_rcv_mux_e 4
#define reg_ckg_p2_pix_rep_1p ckgen01(0x0620)
#define reg_ckg_p2_pix_rep_1p_s 0
#define reg_ckg_p2_pix_rep_1p_e 3
#define reg_ckg_p2_pix_tmdspll ckgen01(0x0628)
#define reg_ckg_p2_pix_tmdspll_s 0
#define reg_ckg_p2_pix_tmdspll_e 3
#define reg_ckg_p2_pix_xc_mux ckgen01(0x0638)
#define reg_ckg_p2_pix_xc_mux_s 0
#define reg_ckg_p2_pix_xc_mux_e 3
#define reg_ckg_p2_timing_det_dec ckgen01(0x0640)
#define reg_ckg_p2_timing_det_dec_s 0
#define reg_ckg_p2_timing_det_dec_e 4
#define reg_ckg_p2_timing_det_dep ckgen01(0x0648)
#define reg_ckg_p2_timing_det_dep_s 0
#define reg_ckg_p2_timing_det_dep_e 4
#define reg_ckg_p2_timing_det_dtop ckgen01(0x0650)
#define reg_ckg_p2_timing_det_dtop_s 0
#define reg_ckg_p2_timing_det_dtop_e 3
#define reg_ckg_p2_tmds_frl_8p ckgen01(0x0658)
#define reg_ckg_p2_tmds_frl_8p_s 0
#define reg_ckg_p2_tmds_frl_8p_e 3
#define reg_ckg_p2_tmds_hdcp_1p ckgen01(0x0660)
#define reg_ckg_p2_tmds_hdcp_1p_s 0
#define reg_ckg_p2_tmds_hdcp_1p_e 3
#define reg_ckg_p2_tmds_hdcp_4p ckgen01(0x0668)
#define reg_ckg_p2_tmds_hdcp_4p_s 0
#define reg_ckg_p2_tmds_hdcp_4p_e 3
#define reg_ckg_p2_tmds_hdcp_8p ckgen01(0x0670)
#define reg_ckg_p2_tmds_hdcp_8p_s 0
#define reg_ckg_p2_tmds_hdcp_8p_e 3
#define reg_ckg_p2_tmds_hdcp_mux ckgen01(0x0678)
#define reg_ckg_p2_tmds_hdcp_mux_s 0
#define reg_ckg_p2_tmds_hdcp_mux_e 3
#define reg_ckg_p2_tmds_hdmi_1p ckgen01(0x0680)
#define reg_ckg_p2_tmds_hdmi_1p_s 0
#define reg_ckg_p2_tmds_hdmi_1p_e 3
#define reg_ckg_p2_tmds_hdmi_8p ckgen01(0x0688)
#define reg_ckg_p2_tmds_hdmi_8p_s 0
#define reg_ckg_p2_tmds_hdmi_8p_e 3
#define reg_ckg_p2_tmds_hdmi_mux ckgen01(0x0690)
#define reg_ckg_p2_tmds_hdmi_mux_s 0
#define reg_ckg_p2_tmds_hdmi_mux_e 3
#define reg_ckg_p3_clk_det_dec_misc_0 ckgen01(0x0698)
#define reg_ckg_p3_clk_det_dec_misc_0_s 0
#define reg_ckg_p3_clk_det_dec_misc_0_e 3
#define reg_ckg_p3_clk_det_dec_misc_0_0 ckgen01(0x06A0)
#define reg_ckg_p3_clk_det_dec_misc_0_0_s 0
#define reg_ckg_p3_clk_det_dec_misc_0_0_e 3
#define reg_ckg_p3_clk_det_dec_misc_1 ckgen01(0x06A8)
#define reg_ckg_p3_clk_det_dec_misc_1_s 0
#define reg_ckg_p3_clk_det_dec_misc_1_e 3
#define reg_ckg_p3_clk_det_dec_misc_1_0 ckgen01(0x06B0)
#define reg_ckg_p3_clk_det_dec_misc_1_0_s 0
#define reg_ckg_p3_clk_det_dec_misc_1_0_e 3
#define reg_ckg_p3_clk_det_dep_misc_0 ckgen01(0x06B8)
#define reg_ckg_p3_clk_det_dep_misc_0_s 0
#define reg_ckg_p3_clk_det_dep_misc_0_e 3
#define reg_ckg_p3_clk_det_dep_misc_0_0 ckgen01(0x06C0)
#define reg_ckg_p3_clk_det_dep_misc_0_0_s 0
#define reg_ckg_p3_clk_det_dep_misc_0_0_e 3
#define reg_ckg_p3_clk_det_dep_misc_1 ckgen01(0x06C8)
#define reg_ckg_p3_clk_det_dep_misc_1_s 0
#define reg_ckg_p3_clk_det_dep_misc_1_e 3
#define reg_ckg_p3_clk_det_dep_misc_1_0 ckgen01(0x06D0)
#define reg_ckg_p3_clk_det_dep_misc_1_0_s 0
#define reg_ckg_p3_clk_det_dep_misc_1_0_e 3
#define reg_ckg_p3_link ckgen01(0x06D8)
#define reg_ckg_p3_link_s 0
#define reg_ckg_p3_link_e 3
#define reg_ckg_p3_pix_1p ckgen01(0x06E0)
#define reg_ckg_p3_pix_1p_s 0
#define reg_ckg_p3_pix_1p_e 3
#define reg_ckg_p3_pix_8p ckgen01(0x06E8)
#define reg_ckg_p3_pix_8p_s 0
#define reg_ckg_p3_pix_8p_e 4
#define reg_ckg_p3_pix_dc_mux ckgen01(0x06F0)
#define reg_ckg_p3_pix_dc_mux_s 0
#define reg_ckg_p3_pix_dc_mux_e 4
#define reg_ckg_p3_pix_rcv_mux ckgen01(0x06F8)
#define reg_ckg_p3_pix_rcv_mux_s 0
#define reg_ckg_p3_pix_rcv_mux_e 4
#define reg_ckg_p3_pix_rep_1p ckgen01(0x0700)
#define reg_ckg_p3_pix_rep_1p_s 0
#define reg_ckg_p3_pix_rep_1p_e 3
#define reg_ckg_p3_pix_tmdspll ckgen01(0x0708)
#define reg_ckg_p3_pix_tmdspll_s 0
#define reg_ckg_p3_pix_tmdspll_e 3
#define reg_ckg_p3_pix_xc_mux ckgen01(0x0718)
#define reg_ckg_p3_pix_xc_mux_s 0
#define reg_ckg_p3_pix_xc_mux_e 3
#define reg_ckg_p3_timing_det_dec ckgen01(0x0720)
#define reg_ckg_p3_timing_det_dec_s 0
#define reg_ckg_p3_timing_det_dec_e 4
#define reg_ckg_p3_timing_det_dep ckgen01(0x0728)
#define reg_ckg_p3_timing_det_dep_s 0
#define reg_ckg_p3_timing_det_dep_e 4
#define reg_ckg_p3_timing_det_dtop ckgen01(0x0730)
#define reg_ckg_p3_timing_det_dtop_s 0
#define reg_ckg_p3_timing_det_dtop_e 3
#define reg_ckg_p3_tmds_frl_8p ckgen01(0x0738)
#define reg_ckg_p3_tmds_frl_8p_s 0
#define reg_ckg_p3_tmds_frl_8p_e 3
#define reg_ckg_p3_tmds_hdcp_1p ckgen01(0x0740)
#define reg_ckg_p3_tmds_hdcp_1p_s 0
#define reg_ckg_p3_tmds_hdcp_1p_e 3
#define reg_ckg_p3_tmds_hdcp_4p ckgen01(0x0748)
#define reg_ckg_p3_tmds_hdcp_4p_s 0
#define reg_ckg_p3_tmds_hdcp_4p_e 3
#define reg_ckg_p3_tmds_hdcp_8p ckgen01(0x0750)
#define reg_ckg_p3_tmds_hdcp_8p_s 0
#define reg_ckg_p3_tmds_hdcp_8p_e 3
#define reg_ckg_p3_tmds_hdcp_mux ckgen01(0x0758)
#define reg_ckg_p3_tmds_hdcp_mux_s 0
#define reg_ckg_p3_tmds_hdcp_mux_e 3
#define reg_ckg_p3_tmds_hdmi_1p ckgen01(0x0760)
#define reg_ckg_p3_tmds_hdmi_1p_s 0
#define reg_ckg_p3_tmds_hdmi_1p_e 3
#define reg_ckg_p3_tmds_hdmi_8p ckgen01(0x0768)
#define reg_ckg_p3_tmds_hdmi_8p_s 0
#define reg_ckg_p3_tmds_hdmi_8p_e 3
#define reg_ckg_p3_tmds_hdmi_mux ckgen01(0x0770)
#define reg_ckg_p3_tmds_hdmi_mux_s 0
#define reg_ckg_p3_tmds_hdmi_mux_e 3
#define reg_ckg_pix_tmdspll_dscd ckgen01(0x0778)
#define reg_ckg_pix_tmdspll_dscd_s 0
#define reg_ckg_pix_tmdspll_dscd_e 4
#define reg_ckg_pix_xc_s0 ckgen01(0x0780)
#define reg_ckg_pix_xc_s0_s 0
#define reg_ckg_pix_xc_s0_e 4
#define reg_ckg_pix_xc_s1 ckgen01(0x0788)
#define reg_ckg_pix_xc_s1_s 0
#define reg_ckg_pix_xc_s1_e 4
#define reg_ckg_r2_hdmi ckgen01(0x0790)
#define reg_ckg_r2_hdmi_s 0
#define reg_ckg_r2_hdmi_e 1
#define reg_ckg_timing_det_dtop ckgen01(0x0798)
#define reg_ckg_timing_det_dtop_s 0
#define reg_ckg_timing_det_dtop_e 4
#define reg_ckg_tmds_audio_s0 ckgen01(0x07A0)
#define reg_ckg_tmds_audio_s0_s 0
#define reg_ckg_tmds_audio_s0_e 3
#define reg_ckg_tmds_audio_s0_0 ckgen01(0x07A8)
#define reg_ckg_tmds_audio_s0_0_s 0
#define reg_ckg_tmds_audio_s0_0_e 4
#define reg_ckg_tmds_audio_s1 ckgen01(0x07B0)
#define reg_ckg_tmds_audio_s1_s 0
#define reg_ckg_tmds_audio_s1_e 3
#define reg_ckg_tmds_audio_s1_0 ckgen01(0x07B8)
#define reg_ckg_tmds_audio_s1_0_s 0
#define reg_ckg_tmds_audio_s1_0_e 4
#define reg_ckg_tmds_dscd ckgen01(0x07C0)
#define reg_ckg_tmds_dscd_s 0
#define reg_ckg_tmds_dscd_e 4
#define reg_ckg_xtal_24 ckgen01(0x07C8)
#define reg_ckg_xtal_24_s 0
#define reg_ckg_xtal_24_e 1
#define reg_ckg_xtal_hdmi_12 ckgen01(0x07D0)
#define reg_ckg_xtal_hdmi_12_s 0
#define reg_ckg_xtal_hdmi_12_e 2
#define reg_ckg_p0_tmdspll_test_dig ckgen01(0x07D8)
#define reg_ckg_p0_tmdspll_test_dig_s 0
#define reg_ckg_p0_tmdspll_test_dig_e 3
#define reg_ckg_p1_tmdspll_test_dig ckgen01(0x07E0)
#define reg_ckg_p1_tmdspll_test_dig_s 0
#define reg_ckg_p1_tmdspll_test_dig_e 3
#define reg_ckg_p2_tmdspll_test_dig ckgen01(0x07E8)
#define reg_ckg_p2_tmdspll_test_dig_s 0
#define reg_ckg_p2_tmdspll_test_dig_e 3
#define reg_ckg_p3_tmdspll_test_dig ckgen01(0x07F0)
#define reg_ckg_p3_tmdspll_test_dig_s 0
#define reg_ckg_p3_tmdspll_test_dig_e 3
#define reg_ckg_128fs_fb_s0_ff ckgen01(0x07F8)
#define reg_ckg_128fs_fb_s0_ff_s 0
#define reg_ckg_128fs_fb_s0_ff_e 3
#define reg_ckg_128fs_fb_s1_ff ckgen01(0x0800)
#define reg_ckg_128fs_fb_s1_ff_s 0
#define reg_ckg_128fs_fb_s1_ff_e 3
#define reg_ckg_det_rclk ckgen01(0x08E0)
#define reg_ckg_det_rclk_s 0
#define reg_ckg_det_rclk_e 2
#define reg_ckg_det_wclk ckgen01(0x08E8)
#define reg_ckg_det_wclk_s 0
#define reg_ckg_det_wclk_e 5
#define reg_ckg_lpll_odclk ckgen01(0x08F0)
#define reg_ckg_lpll_odclk_s 0
#define reg_ckg_lpll_odclk_e 5
#define reg_ckg_lpll_odclk_nodiv ckgen01(0x08F8)
#define reg_ckg_lpll_odclk_nodiv_s 0
#define reg_ckg_lpll_odclk_nodiv_e 1
#define reg_ckg_lpll_syn_432 ckgen01(0x0900)
#define reg_ckg_lpll_syn_432_s 0
#define reg_ckg_lpll_syn_432_e 2
#define reg_ckg_lpll_syn_864 ckgen01(0x0908)
#define reg_ckg_lpll_syn_864_s 0
#define reg_ckg_lpll_syn_864_e 1
#define reg_ckg_mod_a_odclk ckgen01(0x0910)
#define reg_ckg_mod_a_odclk_s 0
#define reg_ckg_mod_a_odclk_e 5
#define reg_ckg_mod_d_odclk ckgen01(0x0918)
#define reg_ckg_mod_d_odclk_s 0
#define reg_ckg_mod_d_odclk_e 5
#define reg_ckg_mod_o_sr_wclk ckgen01(0x091C)
#define reg_ckg_mod_o_sr_wclk_s 0
#define reg_ckg_mod_o_sr_wclk_e 4
#define reg_ckg_mod_v1_sr_wclk ckgen01(0x0920)
#define reg_ckg_mod_v1_sr_wclk_s 0
#define reg_ckg_mod_v1_sr_wclk_e 4
#define reg_ckg_mod_v2_sr_wclk ckgen01(0x0924)
#define reg_ckg_mod_v2_sr_wclk_s 0
#define reg_ckg_mod_v2_sr_wclk_e 4
#define reg_ckg_o_mod_sr_rclk ckgen01(0x0928)
#define reg_ckg_o_mod_sr_rclk_s 0
#define reg_ckg_o_mod_sr_rclk_e 2
#define reg_ckg_o_odclk ckgen01(0x0930)
#define reg_ckg_o_odclk_s 0
#define reg_ckg_o_odclk_e 5
#define reg_ckg_o_odclk_stg1 ckgen01(0x0938)
#define reg_ckg_o_odclk_stg1_s 0
#define reg_ckg_o_odclk_stg1_e 5
#define reg_ckg_o_odclk_stg2 ckgen01(0x0940)
#define reg_ckg_o_odclk_stg2_s 0
#define reg_ckg_o_odclk_stg2_e 5
#define reg_ckg_o_odclk_stg3 ckgen01(0x0948)
#define reg_ckg_o_odclk_stg3_s 0
#define reg_ckg_o_odclk_stg3_e 5
#define reg_ckg_o_odclk_stg4 ckgen01(0x0950)
#define reg_ckg_o_odclk_stg4_s 0
#define reg_ckg_o_odclk_stg4_e 5
#define reg_ckg_o_odclk_stg5 ckgen01(0x0958)
#define reg_ckg_o_odclk_stg5_s 0
#define reg_ckg_o_odclk_stg5_e 5
#define reg_ckg_o_odclk_stg6 ckgen01(0x0960)
#define reg_ckg_o_odclk_stg6_s 0
#define reg_ckg_o_odclk_stg6_e 5
#define reg_ckg_pwm ckgen01(0x0968)
#define reg_ckg_pwm_s 0
#define reg_ckg_pwm_e 6
#define reg_ckg_v1_mod_sr_rclk ckgen01(0x0970)
#define reg_ckg_v1_mod_sr_rclk_s 0
#define reg_ckg_v1_mod_sr_rclk_e 2
#define reg_ckg_v1_odclk ckgen01(0x0978)
#define reg_ckg_v1_odclk_s 0
#define reg_ckg_v1_odclk_e 5
#define reg_ckg_v1_odclk_stg1 ckgen01(0x0980)
#define reg_ckg_v1_odclk_stg1_s 0
#define reg_ckg_v1_odclk_stg1_e 5
#define reg_ckg_v1_odclk_stg2 ckgen01(0x0988)
#define reg_ckg_v1_odclk_stg2_s 0
#define reg_ckg_v1_odclk_stg2_e 5
#define reg_ckg_v1_odclk_stg3 ckgen01(0x0990)
#define reg_ckg_v1_odclk_stg3_s 0
#define reg_ckg_v1_odclk_stg3_e 5
#define reg_ckg_v1_odclk_stg4 ckgen01(0x0998)
#define reg_ckg_v1_odclk_stg4_s 0
#define reg_ckg_v1_odclk_stg4_e 5
#define reg_ckg_v1_odclk_stg5 ckgen01(0x09A0)
#define reg_ckg_v1_odclk_stg5_s 0
#define reg_ckg_v1_odclk_stg5_e 5
#define reg_ckg_v1_odclk_stg6 ckgen01(0x09A8)
#define reg_ckg_v1_odclk_stg6_s 0
#define reg_ckg_v1_odclk_stg6_e 5
#define reg_ckg_v1_odclk_stg7 ckgen01(0x09B0)
#define reg_ckg_v1_odclk_stg7_s 0
#define reg_ckg_v1_odclk_stg7_e 5
#define reg_ckg_v1_odclk_stg8 ckgen01(0x09B8)
#define reg_ckg_v1_odclk_stg8_s 0
#define reg_ckg_v1_odclk_stg8_e 5
#define reg_ckg_v2_mod_sr_rclk ckgen01(0x09C0)
#define reg_ckg_v2_mod_sr_rclk_s 0
#define reg_ckg_v2_mod_sr_rclk_e 2
#define reg_ckg_v2_odclk ckgen01(0x09C8)
#define reg_ckg_v2_odclk_s 0
#define reg_ckg_v2_odclk_e 5
#define reg_ckg_v2_odclk_stg1 ckgen01(0x09D0)
#define reg_ckg_v2_odclk_stg1_s 0
#define reg_ckg_v2_odclk_stg1_e 5
#define reg_ckg_v2_odclk_stg2 ckgen01(0x09D8)
#define reg_ckg_v2_odclk_stg2_s 0
#define reg_ckg_v2_odclk_stg2_e 5
#define reg_ckg_v2_odclk_stg3 ckgen01(0x09E0)
#define reg_ckg_v2_odclk_stg3_s 0
#define reg_ckg_v2_odclk_stg3_e 5
#define reg_ckg_v2_odclk_stg4 ckgen01(0x09E8)
#define reg_ckg_v2_odclk_stg4_s 0
#define reg_ckg_v2_odclk_stg4_e 5
#define reg_ckg_v2_odclk_stg5 ckgen01(0x09F0)
#define reg_ckg_v2_odclk_stg5_s 0
#define reg_ckg_v2_odclk_stg5_e 5
#define reg_ckg_v2_odclk_stg6 ckgen01(0x09F8)
#define reg_ckg_v2_odclk_stg6_s 0
#define reg_ckg_v2_odclk_stg6_e 5
#define reg_ckg_v2_odclk_stg7 ckgen01(0x0A00)
#define reg_ckg_v2_odclk_stg7_s 0
#define reg_ckg_v2_odclk_stg7_e 5
#define reg_ckg_o_mod_sr_rclk_finial ckgen01(0x0A08)
#define reg_ckg_o_mod_sr_rclk_finial_s 0
#define reg_ckg_o_mod_sr_rclk_finial_e 2
#define reg_ckg_o_mod_sr_rclk_pre0 ckgen01(0x0A10)
#define reg_ckg_o_mod_sr_rclk_pre0_s 0
#define reg_ckg_o_mod_sr_rclk_pre0_e 2
#define reg_ckg_o_mod_sr_rclk_pre1 ckgen01(0x0A18)
#define reg_ckg_o_mod_sr_rclk_pre1_s 0
#define reg_ckg_o_mod_sr_rclk_pre1_e 2
#define reg_ckg_v1_mod_sr_rclk_finial ckgen01(0x0A20)
#define reg_ckg_v1_mod_sr_rclk_finial_s 0
#define reg_ckg_v1_mod_sr_rclk_finial_e 2
#define reg_ckg_v1_mod_sr_rclk_pre0 ckgen01(0x0A28)
#define reg_ckg_v1_mod_sr_rclk_pre0_s 0
#define reg_ckg_v1_mod_sr_rclk_pre0_e 2
#define reg_ckg_v1_mod_sr_rclk_pre1 ckgen01(0x0A30)
#define reg_ckg_v1_mod_sr_rclk_pre1_s 0
#define reg_ckg_v1_mod_sr_rclk_pre1_e 2
#define reg_ckg_v2_mod_sr_rclk_finial ckgen01(0x0A38)
#define reg_ckg_v2_mod_sr_rclk_finial_s 0
#define reg_ckg_v2_mod_sr_rclk_finial_e 2
#define reg_ckg_v2_mod_sr_rclk_pre0 ckgen01(0x0A40)
#define reg_ckg_v2_mod_sr_rclk_pre0_s 0
#define reg_ckg_v2_mod_sr_rclk_pre0_e 2
#define reg_ckg_v2_mod_sr_rclk_pre1 ckgen01(0x0A48)
#define reg_ckg_v2_mod_sr_rclk_pre1_s 0
#define reg_ckg_v2_mod_sr_rclk_pre1_e 2
#define reg_ckg_idclk_mod ckgen01(0x0A50)
#define reg_ckg_idclk_mod_s 0
#define reg_ckg_idclk_mod_e 2
#define reg_ckg_v1_odclk_stg9 ckgen01(0x0A58)
#define reg_ckg_v1_odclk_stg9_s 0
#define reg_ckg_v1_odclk_stg9_e 5
#define reg_ckg_xtal_12m_mod ckgen01(0x0A60)
#define reg_ckg_xtal_12m_mod_s 0
#define reg_ckg_xtal_12m_mod_e 1
#define reg_ckg_xtal_24m_mod ckgen01(0x0A68)
#define reg_ckg_xtal_24m_mod_s 0
#define reg_ckg_xtal_24m_mod_e 1
#define reg_ckg_xc_od_delta_scip ckgen01(0x0A7C)
#define reg_ckg_xc_od_delta_scip_s 0
#define reg_ckg_xc_od_delta_scip_e 1
#define reg_ckg_xc_od_delta_scscl ckgen01(0x0A80)
#define reg_ckg_xc_od_delta_scscl_s 0
#define reg_ckg_xc_od_delta_scscl_e 1
#define reg_ckg_xc_od_scscl ckgen01(0x0A80)
#define reg_ckg_xc_od_scscl_s 8
#define reg_ckg_xc_od_scscl_e 9
#define reg_ckg_v1_odclk_scscl ckgen01(0x0A84)
#define reg_ckg_v1_odclk_scscl_s 0
#define reg_ckg_v1_odclk_scscl_e 5
#define reg_ckg_v2_odclk_scscl ckgen01(0x0A84)
#define reg_ckg_v2_odclk_scscl_s 8
#define reg_ckg_v2_odclk_scscl_e 13
#define reg_v1_v2_o_odclk_from_mod ckgen01(0x0A88)
#define reg_v1_v2_o_odclk_from_mod_s 0
#define reg_v1_v2_o_odclk_from_mod_e 0
#define reg_ckg_v1_odclk_scip ckgen01(0x0A8C)
#define reg_ckg_v1_odclk_scip_s 0
#define reg_ckg_v1_odclk_scip_e 5
#define reg_ckg_v2_odclk_scip ckgen01(0x0A8C)
#define reg_ckg_v2_odclk_scip_s 8
#define reg_ckg_v2_odclk_scip_e 13
#define reg_ckg_v1_odclk_sctcon ckgen01(0x0A90)
#define reg_ckg_v1_odclk_sctcon_s 0
#define reg_ckg_v1_odclk_sctcon_e 5
#define reg_ckg_v1_odclk_scmw ckgen01(0x0A94)
#define reg_ckg_v1_odclk_scmw_s 0
#define reg_ckg_v1_odclk_scmw_e 5
#define reg_ckg_v2_odclk_sctcon ckgen01(0x0A98)
#define reg_ckg_v2_odclk_sctcon_s 0
#define reg_ckg_v2_odclk_sctcon_e 5
#define reg_ckg_o_odclk_sctcon ckgen01(0x0A9C)
#define reg_ckg_o_odclk_sctcon_s 0
#define reg_ckg_o_odclk_sctcon_e 5
#define reg_ckg_xc_dc0 ckgen01(0x0AA0)
#define reg_ckg_xc_dc0_s 0
#define reg_ckg_xc_dc0_e 4
#define reg_ckg_xc_sub1_dc0 ckgen01(0x0AA4)
#define reg_ckg_xc_sub1_dc0_s 0
#define reg_ckg_xc_sub1_dc0_e 4
#define reg_ckg_xc_sub_dc0 ckgen01(0x0AA8)
#define reg_ckg_xc_sub_dc0_s 0
#define reg_ckg_xc_sub_dc0_e 4
#define reg_ckg_xc_vein_scip ckgen01(0x0AAC)
#define reg_ckg_xc_vein_scip_s 0
#define reg_ckg_xc_vein_scip_e 3
#define reg_ckg_xc_b2r ckgen01(0x0AB0)
#define reg_ckg_xc_b2r_s 0
#define reg_ckg_xc_b2r_e 2
#define reg_ckg_xc_od_meta_sctcon ckgen01(0x0AB4)
#define reg_ckg_xc_od_meta_sctcon_s 0
#define reg_ckg_xc_od_meta_sctcon_e 1
#define reg_ckg_xc_b2r_sub ckgen01(0x0AB8)
#define reg_ckg_xc_b2r_sub_s 0
#define reg_ckg_xc_b2r_sub_e 2
#define reg_ckg_xc_od_delta_meta_sctcon ckgen01(0x0ABC)
#define reg_ckg_xc_od_delta_meta_sctcon_s 0
#define reg_ckg_xc_od_delta_meta_sctcon_e 1
#define reg_ckg_xc_ed ckgen01(0x0AC0)
#define reg_ckg_xc_ed_s 0
#define reg_ckg_xc_ed_e 3
#define reg_ckg_xc_od_osd_meta_sctcon ckgen01(0x0AC4)
#define reg_ckg_xc_od_osd_meta_sctcon_s 0
#define reg_ckg_xc_od_osd_meta_sctcon_e 1
#define reg_ckg_xc_fd ckgen01(0x0AC8)
#define reg_ckg_xc_fd_s 0
#define reg_ckg_xc_fd_e 3
#define reg_ckg_xc_fd_scip ckgen01(0x0AC8)
#define reg_ckg_xc_fd_scip_s 8
#define reg_ckg_xc_fd_scip_e 9
#define reg_ckg_xc_fd_scscl ckgen01(0x0AC8)
#define reg_ckg_xc_fd_scscl_s 12
#define reg_ckg_xc_fd_scscl_e 13
#define reg_ckg_v1_meta_odclk_sctcon ckgen01(0x0ACC)
#define reg_ckg_v1_meta_odclk_sctcon_s 0
#define reg_ckg_v1_meta_odclk_sctcon_e 5
#define reg_ckg_xc_fn ckgen01(0x0AD0)
#define reg_ckg_xc_fn_s 0
#define reg_ckg_xc_fn_e 3
#define reg_ckg_v2_meta_odclk_sctcon ckgen01(0x0AD4)
#define reg_ckg_v2_meta_odclk_sctcon_s 0
#define reg_ckg_v2_meta_odclk_sctcon_e 5
#define reg_ckg_xc_fs ckgen01(0x0AD8)
#define reg_ckg_xc_fs_s 0
#define reg_ckg_xc_fs_e 3
#define reg_ckg_xc_fs_scip ckgen01(0x0AD8)
#define reg_ckg_xc_fs_scip_s 8
#define reg_ckg_xc_fs_scip_e 9
#define reg_ckg_o_meta_odclk_sctcon ckgen01(0x0ADC)
#define reg_ckg_o_meta_odclk_sctcon_s 0
#define reg_ckg_o_meta_odclk_sctcon_e 5
#define reg_ckg_xc_od ckgen01(0x0AE0)
#define reg_ckg_xc_od_s 0
#define reg_ckg_xc_od_e 2
#define reg_ckg_xc_od_scip ckgen01(0x0AE0)
#define reg_ckg_xc_od_scip_s 8
#define reg_ckg_xc_od_scip_e 9
#define reg_ckg_xc_slow ckgen01(0x0AE8)
#define reg_ckg_xc_slow_s 0
#define reg_ckg_xc_slow_e 2
#define reg_ckg_xc_srs ckgen01(0x0AF0)
#define reg_ckg_xc_srs_s 0
#define reg_ckg_xc_srs_e 2
#define reg_ckg_xc_fs_scace ckgen01(0x0AF8)
#define reg_ckg_xc_fs_scace_s 0
#define reg_ckg_xc_fs_scace_e 1
#define reg_ckg_xtal_12m_scace ckgen01(0x0B00)
#define reg_ckg_xtal_12m_scace_s 0
#define reg_ckg_xtal_12m_scace_e 1
#define reg_ckg_xtal_24m_scace ckgen01(0x0B08)
#define reg_ckg_xtal_24m_scace_s 0
#define reg_ckg_xtal_24m_scace_e 1
#define reg_ckg_xc_dc0_scip ckgen01(0x0B10)
#define reg_ckg_xc_dc0_scip_s 0
#define reg_ckg_xc_dc0_scip_e 1
#define reg_ckg_xc_dbg2miu_scip ckgen01(0x0B18)
#define reg_ckg_xc_dbg2miu_scip_s 0
#define reg_ckg_xc_dbg2miu_scip_e 3
#define reg_ckg_xc_ed0_scip ckgen01(0x0B20)
#define reg_ckg_xc_ed0_scip_s 0
#define reg_ckg_xc_ed0_scip_e 1
#define reg_ckg_xc_ed1_scip ckgen01(0x0B28)
#define reg_ckg_xc_ed1_scip_s 0
#define reg_ckg_xc_ed1_scip_e 1
#define reg_ckg_xc_fn_scip ckgen01(0x0B30)
#define reg_ckg_xc_fn_scip_s 0
#define reg_ckg_xc_fn_scip_e 1
#define reg_ckg_xc_id0_scip ckgen01(0x0B38)
#define reg_ckg_xc_id0_scip_s 0
#define reg_ckg_xc_id0_scip_e 4
#define reg_ckg_xc_id1_scip ckgen01(0x0B40)
#define reg_ckg_xc_id1_scip_s 0
#define reg_ckg_xc_id1_scip_e 4
#define reg_ckg_xtal_24m_scip ckgen01(0x0B48)
#define reg_ckg_xtal_24m_scip_s 0
#define reg_ckg_xtal_24m_scip_e 1
#define reg_ckg_xtal_12m_scip ckgen01(0x0B50)
#define reg_ckg_xtal_12m_scip_s 0
#define reg_ckg_xtal_12m_scip_e 1
#define reg_ckg_xtal_ip1_scip ckgen01(0x0B58)
#define reg_ckg_xtal_ip1_scip_s 0
#define reg_ckg_xtal_ip1_scip_e 3
#define reg_ckg_xc_fd_scmw ckgen01(0x0B60)
#define reg_ckg_xc_fd_scmw_s 0
#define reg_ckg_xc_fd_scmw_e 1
#define reg_ckg_xc_fn_scmw ckgen01(0x0B68)
#define reg_ckg_xc_fn_scmw_s 0
#define reg_ckg_xc_fn_scmw_e 1
#define reg_ckg_xc_fs_scmw ckgen01(0x0B70)
#define reg_ckg_xc_fs_scmw_s 0
#define reg_ckg_xc_fs_scmw_e 1
#define reg_ckg_xc_od_scmw ckgen01(0x0B78)
#define reg_ckg_xc_od_scmw_s 0
#define reg_ckg_xc_od_scmw_e 1
#define reg_ckg_xtal_24m_scmw ckgen01(0x0B80)
#define reg_ckg_xtal_24m_scmw_s 0
#define reg_ckg_xtal_24m_scmw_e 1
#define reg_ckg_xc_fn_scnr ckgen01(0x0B88)
#define reg_ckg_xc_fn_scnr_s 0
#define reg_ckg_xc_fn_scnr_e 1
#define reg_ckg_xtal_24m_scnr ckgen01(0x0B98)
#define reg_ckg_xtal_24m_scnr_s 0
#define reg_ckg_xtal_24m_scnr_e 1
#define reg_ckg_xc_fn_scpq ckgen01(0x0BA0)
#define reg_ckg_xc_fn_scpq_s 0
#define reg_ckg_xc_fn_scpq_e 1
#define reg_ckg_xtal_24m_scpq ckgen01(0x0BA8)
#define reg_ckg_xtal_24m_scpq_s 0
#define reg_ckg_xtal_24m_scpq_e 1
#define reg_ckg_xc_fn_scscl ckgen01(0x0BB0)
#define reg_ckg_xc_fn_scscl_s 0
#define reg_ckg_xc_fn_scscl_e 1
#define reg_ckg_xc_fs_scscl ckgen01(0x0BB8)
#define reg_ckg_xc_fs_scscl_s 0
#define reg_ckg_xc_fs_scscl_e 1
#define reg_ckg_xtal_12m_scscl ckgen01(0x0BC0)
#define reg_ckg_xtal_12m_scscl_s 0
#define reg_ckg_xtal_12m_scscl_e 1
#define reg_ckg_xtal_24m_scscl ckgen01(0x0BC8)
#define reg_ckg_xtal_24m_scscl_s 0
#define reg_ckg_xtal_24m_scscl_e 1
#define reg_ckg_xc_fs_scsr ckgen01(0x0BD0)
#define reg_ckg_xc_fs_scsr_s 0
#define reg_ckg_xc_fs_scsr_e 1
#define reg_ckg_xc_sr_alai_scsr ckgen01(0x0BD8)
#define reg_ckg_xc_sr_alai_scsr_s 0
#define reg_ckg_xc_sr_alai_scsr_e 2
#define reg_ckg_xc_sr_sram_share_scsr ckgen01(0x0BE0)
#define reg_ckg_xc_sr_sram_share_scsr_s 0
#define reg_ckg_xc_sr_sram_share_scsr_e 3
#define reg_ckg_xc_srs_scsr ckgen01(0x0BE8)
#define reg_ckg_xc_srs_scsr_s 0
#define reg_ckg_xc_srs_scsr_e 1
#define reg_ckg_xtal_12m_scsr ckgen01(0x0BF0)
#define reg_ckg_xtal_12m_scsr_s 0
#define reg_ckg_xtal_12m_scsr_e 1
#define reg_ckg_xtal_24m_scsr ckgen01(0x0BF8)
#define reg_ckg_xtal_24m_scsr_s 0
#define reg_ckg_xtal_24m_scsr_e 1
#define reg_ckg_xc_fd_sctcon ckgen01(0x0C00)
#define reg_ckg_xc_fd_sctcon_s 0
#define reg_ckg_xc_fd_sctcon_e 1
#define reg_ckg_xc_fn_sctcon ckgen01(0x0C08)
#define reg_ckg_xc_fn_sctcon_s 0
#define reg_ckg_xc_fn_sctcon_e 1
#define reg_ckg_xc_od_sctcon ckgen01(0x0C10)
#define reg_ckg_xc_od_sctcon_s 0
#define reg_ckg_xc_od_sctcon_e 1
#define reg_ckg_xtal_12m_sctcon ckgen01(0x0C18)
#define reg_ckg_xtal_12m_sctcon_s 0
#define reg_ckg_xtal_12m_sctcon_e 1
#define reg_ckg_xtal_24m_sctcon ckgen01(0x0C20)
#define reg_ckg_xtal_24m_sctcon_s 0
#define reg_ckg_xtal_24m_sctcon_e 1
#define reg_ckg_xc_fn_scdv ckgen01(0x0C28)
#define reg_ckg_xc_fn_scdv_s 0
#define reg_ckg_xc_fn_scdv_e 1
#define reg_ckg_xtal_12m_scdv ckgen01(0x0C30)
#define reg_ckg_xtal_12m_scdv_s 0
#define reg_ckg_xtal_12m_scdv_e 1
#define reg_ckg_xtal_24m_scdv ckgen01(0x0C38)
#define reg_ckg_xtal_24m_scdv_s 0
#define reg_ckg_xtal_24m_scdv_e 1
#define reg_ckg_xcpll_syn ckgen01(0x0C40)
#define reg_ckg_xcpll_syn_s 0
#define reg_ckg_xcpll_syn_e 3
#define reg_ckg_delta_b2p2_sram ckgen01(0x0C48)
#define reg_ckg_delta_b2p2_sram_s 0
#define reg_ckg_delta_b2p2_sram_e 2
#define reg_ckg_gucd_18_lut2_sram ckgen01(0x0C50)
#define reg_ckg_gucd_18_lut2_sram_s 0
#define reg_ckg_gucd_18_lut2_sram_e 2
#define reg_ckg_gucd_256_lut2_sram ckgen01(0x0C58)
#define reg_ckg_gucd_256_lut2_sram_s 0
#define reg_ckg_gucd_256_lut2_sram_e 2
#define reg_ckg_hsy_8p3_sram ckgen01(0x0C60)
#define reg_ckg_hsy_8p3_sram_s 0
#define reg_ckg_hsy_8p3_sram_e 2
#define reg_ckg_hsy_8p_sram ckgen01(0x0C68)
#define reg_ckg_hsy_8p_sram_s 0
#define reg_ckg_hsy_8p_sram_e 2
#define reg_ckg_dip1_hvsp_sram ckgen01(0x0C6C)
#define reg_ckg_dip1_hvsp_sram_s 0
#define reg_ckg_dip1_hvsp_sram_e 2
#define reg_ckg_lce_ace_sram ckgen01(0x0C70)
#define reg_ckg_lce_ace_sram_s 0
#define reg_ckg_lce_ace_sram_e 2
#define reg_ckg_dip1_xvycc_sram ckgen01(0x0C74)
#define reg_ckg_dip1_xvycc_sram_s 0
#define reg_ckg_dip1_xvycc_sram_e 2
#define reg_ckg_pq_gamma_sram ckgen01(0x0C78)
#define reg_ckg_pq_gamma_sram_s 0
#define reg_ckg_pq_gamma_sram_e 2
#define reg_ckg_rgb_3dlut_sram ckgen01(0x0C80)
#define reg_ckg_rgb_3dlut_sram_s 0
#define reg_ckg_rgb_3dlut_sram_e 2
#define reg_ckg_vip_ace_sram ckgen01(0x0C88)
#define reg_ckg_vip_ace_sram_s 0
#define reg_ckg_vip_ace_sram_e 2
#define reg_ckg_xvycc_sram ckgen01(0x0C90)
#define reg_ckg_xvycc_sram_s 0
#define reg_ckg_xvycc_sram_e 2
#define reg_ckg_dv_hw5_sram ckgen01(0x0C98)
#define reg_ckg_dv_hw5_sram_s 0
#define reg_ckg_dv_hw5_sram_e 2
#define reg_ckg_dc0_sram ckgen01(0x0CA0)
#define reg_ckg_dc0_sram_s 0
#define reg_ckg_dc0_sram_e 2
#define reg_ckg_ucd_st_sram ckgen01(0x0CA8)
#define reg_ckg_ucd_st_sram_s 0
#define reg_ckg_ucd_st_sram_e 2
#define reg_ckg_xc_adc_scip ckgen01(0x0CB0)
#define reg_ckg_xc_adc_scip_s 0
#define reg_ckg_xc_adc_scip_e 3
#define reg_ckg_xc_sub_dc0_scip ckgen01(0x0CB8)
#define reg_ckg_xc_sub_dc0_scip_s 0
#define reg_ckg_xc_sub_dc0_scip_e 1
#define reg_ckg_xc_sub1_dc0_scip ckgen01(0x0CBC)
#define reg_ckg_xc_sub1_dc0_scip_s 0
#define reg_ckg_xc_sub1_dc0_scip_e 1
#define reg_ckg_xc_disp_mfdec_scip ckgen01(0x0CC0)
#define reg_ckg_xc_disp_mfdec_scip_s 0
#define reg_ckg_xc_disp_mfdec_scip_e 1
#define reg_ckg_xc_hd2miu_m_scip ckgen01(0x0CC8)
#define reg_ckg_xc_hd2miu_m_scip_s 0
#define reg_ckg_xc_hd2miu_m_scip_e 2
#define reg_ckg_xc_hd2miu_s_scip ckgen01(0x0CD0)
#define reg_ckg_xc_hd2miu_s_scip_s 0
#define reg_ckg_xc_hd2miu_s_scip_e 2
#define reg_ckg_xc_hdmi0_scip ckgen01(0x0CD8)
#define reg_ckg_xc_hdmi0_scip_s 0
#define reg_ckg_xc_hdmi0_scip_e 3
#define reg_ckg_xc_hdmi1_scip ckgen01(0x0CE0)
#define reg_ckg_xc_hdmi1_scip_s 0
#define reg_ckg_xc_hdmi1_scip_e 3
#define reg_ckg_xc_hdmi2_scip ckgen01(0x0CE8)
#define reg_ckg_xc_hdmi2_scip_s 0
#define reg_ckg_xc_hdmi2_scip_e 3
#define reg_ckg_xc_hdmi3_scip ckgen01(0x0CF0)
#define reg_ckg_xc_hdmi3_scip_s 0
#define reg_ckg_xc_hdmi3_scip_e 3
#define reg_ckg_xc_ip2_src_scip ckgen01(0x0CF8)
#define reg_ckg_xc_ip2_src_scip_s 0
#define reg_ckg_xc_ip2_src_scip_e 3
#define reg_ckg_xc_slow_scip ckgen01(0x0D00)
#define reg_ckg_xc_slow_scip_s 0
#define reg_ckg_xc_slow_scip_e 1
#define reg_ckg_xc_tgen_win_scip ckgen01(0x0D08)
#define reg_ckg_xc_tgen_win_scip_s 0
#define reg_ckg_xc_tgen_win_scip_e 3
#define reg_ckg_xc_ucd_stat_scip ckgen01(0x0D10)
#define reg_ckg_xc_ucd_stat_scip_s 0
#define reg_ckg_xc_ucd_stat_scip_e 3
#define reg_ckg_xc_vd_scip ckgen01(0x0D18)
#define reg_ckg_xc_vd_scip_s 0
#define reg_ckg_xc_vd_scip_e 1
#define reg_ckg_xc_ve_scip ckgen01(0x0D20)
#define reg_ckg_xc_ve_scip_s 0
#define reg_ckg_xc_ve_scip_e 3
#define reg_ckg_xc_vedac ckgen01(0x0D28)
#define reg_ckg_xc_vedac_s 0
#define reg_ckg_xc_vedac_e 1
#define reg_ckg_dbk_hw_sram ckgen01(0x0D30)
#define reg_ckg_dbk_hw_sram_s 0
#define reg_ckg_dbk_hw_sram_e 2
#define reg_ckg_scnr_hdr_sram ckgen01(0x0D38)
#define reg_ckg_scnr_hdr_sram_s 0
#define reg_ckg_scnr_hdr_sram_e 2
#define reg_ckg_spf_hdbk_sram ckgen01(0x0D40)
#define reg_ckg_spf_hdbk_sram_s 0
#define reg_ckg_spf_hdbk_sram_e 2
#define reg_ckg_vdbk_sram ckgen01(0x0D48)
#define reg_ckg_vdbk_sram_s 0
#define reg_ckg_vdbk_sram_e 2
#define reg_ckg_delta_b2p_sram ckgen01(0x0D50)
#define reg_ckg_delta_b2p_sram_s 0
#define reg_ckg_delta_b2p_sram_e 2
#define reg_ckg_gucd_18_sram ckgen01(0x0D58)
#define reg_ckg_gucd_18_sram_s 0
#define reg_ckg_gucd_18_sram_e 2
#define reg_ckg_gucd_256_sram ckgen01(0x0D60)
#define reg_ckg_gucd_256_sram_s 0
#define reg_ckg_gucd_256_sram_e 2
#define reg_ckg_hsy_sp3_sram ckgen01(0x0D68)
#define reg_ckg_hsy_sp3_sram_s 0
#define reg_ckg_hsy_sp3_sram_e 2
#define reg_ckg_hsy_sp_sram ckgen01(0x0D70)
#define reg_ckg_hsy_sp_sram_s 0
#define reg_ckg_hsy_sp_sram_e 2
#define reg_ckg_hvsp_stp1_sram ckgen01(0x0D78)
#define reg_ckg_hvsp_stp1_sram_s 0
#define reg_ckg_hvsp_stp1_sram_e 2
#define reg_ckg_hvsp_stp2_sram ckgen01(0x0D80)
#define reg_ckg_hvsp_stp2_sram_s 0
#define reg_ckg_hvsp_stp2_sram_e 2
#define reg_ckg_lce_scl_sram ckgen01(0x0D88)
#define reg_ckg_lce_scl_sram_s 0
#define reg_ckg_lce_scl_sram_e 2
#define reg_ckg_vip_pq_sram ckgen01(0x0D90)
#define reg_ckg_vip_pq_sram_s 0
#define reg_ckg_vip_pq_sram_e 2
#define reg_ckg_aisr_sram ckgen01(0x0D98)
#define reg_ckg_aisr_sram_s 0
#define reg_ckg_aisr_sram_e 3
#define reg_ckg_aisr_hvsp_sram ckgen01(0x0D9C)
#define reg_ckg_aisr_hvsp_sram_s 0
#define reg_ckg_aisr_hvsp_sram_e 3
#define reg_ckg_xc_aisr_scsr ckgen01(0x0DA0)
#define reg_ckg_xc_aisr_scsr_s 0
#define reg_ckg_xc_aisr_scsr_e 2
#define reg_ckg_xc_fn_scsr ckgen01(0x0DA8)
#define reg_ckg_xc_fn_scsr_s 0
#define reg_ckg_xc_fn_scsr_e 1
#define reg_ckg_demura_sram ckgen01(0x0DB0)
#define reg_ckg_demura_sram_s 0
#define reg_ckg_demura_sram_e 2
#define reg_ckg_gop0_sram ckgen01(0x0DB8)
#define reg_ckg_gop0_sram_s 0
#define reg_ckg_gop0_sram_e 2
#define reg_ckg_gop1_sram ckgen01(0x0DC0)
#define reg_ckg_gop1_sram_s 0
#define reg_ckg_gop1_sram_e 2
#define reg_ckg_gop2_sram ckgen01(0x0DC8)
#define reg_ckg_gop2_sram_s 0
#define reg_ckg_gop2_sram_e 2
#define reg_ckg_gop3_sram ckgen01(0x0DD0)
#define reg_ckg_gop3_sram_s 0
#define reg_ckg_gop3_sram_e 2
#define reg_ckg_ld_edge2d_sram ckgen01(0x0DD8)
#define reg_ckg_ld_edge2d_sram_s 0
#define reg_ckg_ld_edge2d_sram_e 2
#define reg_ckg_ldcomp_sram ckgen01(0x0DE0)
#define reg_ckg_ldcomp_sram_s 0
#define reg_ckg_ldcomp_sram_e 2
#define reg_ckg_ldm_ga_sram ckgen01(0x0DE8)
#define reg_ckg_ldm_ga_sram_s 0
#define reg_ckg_ldm_ga_sram_e 2
#define reg_ckg_ldmcg_sram ckgen01(0x0DF0)
#define reg_ckg_ldmcg_sram_s 0
#define reg_ckg_ldmcg_sram_e 2
#define reg_ckg_lpq_pa_sram ckgen01(0x0DF8)
#define reg_ckg_lpq_pa_sram_s 0
#define reg_ckg_lpq_pa_sram_e 2
#define reg_ckg_osd_dv_hw5_sram ckgen01(0x0E00)
#define reg_ckg_osd_dv_hw5_sram_s 0
#define reg_ckg_osd_dv_hw5_sram_e 2
#define reg_ckg_padj_sram ckgen01(0x0E08)
#define reg_ckg_padj_sram_s 0
#define reg_ckg_padj_sram_e 2
#define reg_ckg_panel_ga_sram ckgen01(0x0E10)
#define reg_ckg_panel_ga_sram_s 0
#define reg_ckg_panel_ga_sram_e 2
#define reg_ckg_sidclk_hd0_scip ckgen01(0x0E14)
#define reg_ckg_sidclk_hd0_scip_s 0
#define reg_ckg_sidclk_hd0_scip_e 1
#define reg_ckg_sidclk_hd1_scip ckgen01(0x0E18)
#define reg_ckg_sidclk_hd1_scip_s 0
#define reg_ckg_sidclk_hd1_scip_e 1
#define reg_ckg_sidclk_hd2_scip ckgen01(0x0E1C)
#define reg_ckg_sidclk_hd2_scip_s 0
#define reg_ckg_sidclk_hd2_scip_e 1
#define reg_ckg_sidclk_hd3_scip ckgen01(0x0E20)
#define reg_ckg_sidclk_hd3_scip_s 0
#define reg_ckg_sidclk_hd3_scip_e 1
#define reg_ckg_xc_dip0_scip ckgen01(0x0E24)
#define reg_ckg_xc_dip0_scip_s 0
#define reg_ckg_xc_dip0_scip_e 4
#define reg_ckg_xc_dip1_scip ckgen01(0x0E28)
#define reg_ckg_xc_dip1_scip_s 0
#define reg_ckg_xc_dip1_scip_e 4
#define reg_ckg_xc_dip2_scip ckgen01(0x0E2C)
#define reg_ckg_xc_dip2_scip_s 0
#define reg_ckg_xc_dip2_scip_e 4
#define reg_ckg_xc_afbc_sctcon ckgen01(0x0E30)
#define reg_ckg_xc_afbc_sctcon_s 0
#define reg_ckg_xc_afbc_sctcon_e 1
#define reg_ckg_xc_gop0_dst_sctcon ckgen01(0x0E34)
#define reg_ckg_xc_gop0_dst_sctcon_s 0
#define reg_ckg_xc_gop0_dst_sctcon_e 2
#define reg_ckg_xc_gop_scl_sctcon ckgen01(0x0E38)
#define reg_ckg_xc_gop_scl_sctcon_s 0
#define reg_ckg_xc_gop_scl_sctcon_e 2
#define reg_ckg_xc_gop_sctcon ckgen01(0x0E3C)
#define reg_ckg_xc_gop_sctcon_s 0
#define reg_ckg_xc_gop_sctcon_e 1
#define reg_ckg_xc_gopc_dst_sctcon ckgen01(0x0E40)
#define reg_ckg_xc_gopc_dst_sctcon_s 0
#define reg_ckg_xc_gopc_dst_sctcon_e 2
#define reg_ckg_xc_gopg_dst_sctcon ckgen01(0x0E44)
#define reg_ckg_xc_gopg_dst_sctcon_s 0
#define reg_ckg_xc_gopg_dst_sctcon_e 2
#define reg_ckg_xc_od_delta_sctcon ckgen01(0x0E48)
#define reg_ckg_xc_od_delta_sctcon_s 0
#define reg_ckg_xc_od_delta_sctcon_e 1
#define reg_ckg_xc_od_div2_sctcon ckgen01(0x0E4C)
#define reg_ckg_xc_od_div2_sctcon_s 0
#define reg_ckg_xc_od_div2_sctcon_e 1
#define reg_ckg_xc_od_div4_sctcon ckgen01(0x0E50)
#define reg_ckg_xc_od_div4_sctcon_s 0
#define reg_ckg_xc_od_div4_sctcon_e 1
#define reg_flow_ctrl_rate_xc_ed ckgen01(0x0E54)
#define reg_flow_ctrl_rate_xc_ed_s 0
#define reg_flow_ctrl_rate_xc_ed_e 5
#define reg_flow_ctrl_rate_xc_fn ckgen01(0x0E58)
#define reg_flow_ctrl_rate_xc_fn_s 0
#define reg_flow_ctrl_rate_xc_fn_e 5
#define reg_flow_ctrl_rate_xc_fs ckgen01(0x0E5C)
#define reg_flow_ctrl_rate_xc_fs_s 0
#define reg_flow_ctrl_rate_xc_fs_e 5
#define reg_flow_ctrl_rate_xc_fd ckgen01(0x0E60)
#define reg_flow_ctrl_rate_xc_fd_s 0
#define reg_flow_ctrl_rate_xc_fd_e 5
#define reg_ckg_xc_od_osd_sctcon ckgen01(0x0E68)
#define reg_ckg_xc_od_osd_sctcon_s 0
#define reg_ckg_xc_od_osd_sctcon_e 1
#define reg_ckg_xc_fs_sctcon ckgen01(0x0E70)
#define reg_ckg_xc_fs_sctcon_s 0
#define reg_ckg_xc_fs_sctcon_e 1
#define reg_ckg_xc_sc2fpll_scip ckgen01(0x0E78)
#define reg_ckg_xc_sc2fpll_scip_s 0
#define reg_ckg_xc_sc2fpll_scip_e 4
#define reg_ckg_mcu_mail0 ckgen01(0x0EE0)
#define reg_ckg_mcu_mail0_s 0
#define reg_ckg_mcu_mail0_e 2
#define reg_ckg_mcu_mail1 ckgen01(0x0EE8)
#define reg_ckg_mcu_mail1_s 0
#define reg_ckg_mcu_mail1_e 2
#define reg_ckg_vd2x ckgen01(0x0EF0)
#define reg_ckg_vd2x_s 0
#define reg_ckg_vd2x_e 3
#define reg_ckg_vd2x_mheg5 ckgen01(0x0EF0)
#define reg_ckg_vd2x_mheg5_s 8
#define reg_ckg_vd2x_mheg5_e 9
#define reg_ckg_vd_32fsc ckgen01(0x0EF8)
#define reg_ckg_vd_32fsc_s 0
#define reg_ckg_vd_32fsc_e 2
#define reg_ckg_vd_32fsc_mheg5 ckgen01(0x0EF8)
#define reg_ckg_vd_32fsc_mheg5_s 8
#define reg_ckg_vd_32fsc_mheg5_e 9
#define reg_ckg_vd ckgen01(0x0F00)
#define reg_ckg_vd_s 0
#define reg_ckg_vd_e 3
#define reg_ckg_vd_mheg5 ckgen01(0x0F00)
#define reg_ckg_vd_mheg5_s 8
#define reg_ckg_vd_mheg5_e 9
#define reg_ckg_cmbai ckgen01(0x0F08)
#define reg_ckg_cmbai_s 0
#define reg_ckg_cmbai_e 1
#define reg_ckg_cmbao ckgen01(0x0F10)
#define reg_ckg_cmbao_s 0
#define reg_ckg_cmbao_e 1
#define reg_ckg_cmbbi ckgen01(0x0F18)
#define reg_ckg_cmbbi_s 0
#define reg_ckg_cmbbi_e 1
#define reg_ckg_cmbbo ckgen01(0x0F20)
#define reg_ckg_cmbbo_s 0
#define reg_ckg_cmbbo_e 1
#define reg_ckg_ve ckgen01(0x0F40)
#define reg_ckg_ve_s 0
#define reg_ckg_ve_e 3
#define reg_ckg_vedac ckgen01(0x0F48)
#define reg_ckg_vedac_s 0
#define reg_ckg_vedac_e 4
#define reg_ckg_venc ckgen01(0x0F50)
#define reg_ckg_venc_s 0
#define reg_ckg_venc_e 3
#define reg_ckg_venc_mheg5 ckgen01(0x0F50)
#define reg_ckg_venc_mheg5_s 8
#define reg_ckg_venc_mheg5_e 9
#define reg_ckg_smi_fcie_sel ckgen01(0x0F68)
#define reg_ckg_smi_fcie_sel_s 0
#define reg_ckg_smi_fcie_sel_e 3
#define reg_ckg_ecc ckgen01(0x0F70)
#define reg_ckg_ecc_s 0
#define reg_ckg_ecc_e 4
#define reg_ckg_ecc_tsp ckgen01(0x0F70)
#define reg_ckg_ecc_tsp_s 8
#define reg_ckg_ecc_tsp_e 9
#define reg_ckg_fcie ckgen01(0x0F78)
#define reg_ckg_fcie_s 0
#define reg_ckg_fcie_e 4
#define reg_ckg_fcie_tsp ckgen01(0x0F78)
#define reg_ckg_fcie_tsp_s 8
#define reg_ckg_fcie_tsp_e 11
#define reg_ckg_fcie_syn ckgen01(0x0F80)
#define reg_ckg_fcie_syn_s 0
#define reg_ckg_fcie_syn_e 1
#define reg_ckg_gmac_ahb ckgen01(0x0F90)
#define reg_ckg_gmac_ahb_s 0
#define reg_ckg_gmac_ahb_e 3
#define reg_ckg_gmac_ahb_mheg5 ckgen01(0x0F90)
#define reg_ckg_gmac_ahb_mheg5_s 8
#define reg_ckg_gmac_ahb_mheg5_e 9
#define reg_ckg_gmac_rx_mheg5 ckgen01(0x0F98)
#define reg_ckg_gmac_rx_mheg5_s 8
#define reg_ckg_gmac_rx_mheg5_e 9
#define reg_ckg_gmac_tx_mheg5 ckgen01(0x0FA0)
#define reg_ckg_gmac_tx_mheg5_s 8
#define reg_ckg_gmac_tx_mheg5_e 9
#define reg_ckg_pextp_pl_pclk_tsp ckgen01(0x0FB4)
#define reg_ckg_pextp_pl_pclk_tsp_s 0
#define reg_ckg_pextp_pl_pclk_tsp_e 2
#define reg_ckg_xtal_12m_pcie_phy ckgen01(0x0FB8)
#define reg_ckg_xtal_12m_pcie_phy_s 0
#define reg_ckg_xtal_12m_pcie_phy_e 1
#define reg_ckg_pextp_tl ckgen01(0x0FC0)
#define reg_ckg_pextp_tl_s 0
#define reg_ckg_pextp_tl_e 3
#define reg_ckg_pextp_tl_tsp ckgen01(0x0FC0)
#define reg_ckg_pextp_tl_tsp_s 8
#define reg_ckg_pextp_tl_tsp_e 9
#define reg_ckg_ssusb_usb20_phy_clk_tsp ckgen01(0x0FC4)
#define reg_ckg_ssusb_usb20_phy_clk_tsp_s 0
#define reg_ckg_ssusb_usb20_phy_clk_tsp_e 2
#define reg_ckg_ssusb_usb20_phy_clk_1p_tsp ckgen01(0x0FC8)
#define reg_ckg_ssusb_usb20_phy_clk_1p_tsp_s 0
#define reg_ckg_ssusb_usb20_phy_clk_1p_tsp_e 2
#define reg_ckg_ssusb_usb20_phy_clk_2p_tsp ckgen01(0x0FCC)
#define reg_ckg_ssusb_usb20_phy_clk_2p_tsp_s 0
#define reg_ckg_ssusb_usb20_phy_clk_2p_tsp_e 2
#define reg_ckg_ssusb_frmcnt_tsp ckgen01(0x0FD0)
#define reg_ckg_ssusb_frmcnt_tsp_s 0
#define reg_ckg_ssusb_frmcnt_tsp_e 2
#define reg_ckg_ssusb_pclk_tsp ckgen01(0x0FD4)
#define reg_ckg_ssusb_pclk_tsp_s 0
#define reg_ckg_ssusb_pclk_tsp_e 2
#define reg_ckg_ssusb_pclk_1p_tsp ckgen01(0x0FD8)
#define reg_ckg_ssusb_pclk_1p_tsp_s 0
#define reg_ckg_ssusb_pclk_1p_tsp_e 2
#define reg_ckg_xtal_12m_usb_phy ckgen01(0x0FE0)
#define reg_ckg_xtal_12m_usb_phy_s 0
#define reg_ckg_xtal_12m_usb_phy_e 1
#define reg_ckg_ssusb_sys_tsp ckgen01(0x0FE8)
#define reg_ckg_ssusb_sys_tsp_s 0
#define reg_ckg_ssusb_sys_tsp_e 1
#define reg_ckg_ssusb_xhci_tsp ckgen01(0x0FEC)
#define reg_ckg_ssusb_xhci_tsp_s 0
#define reg_ckg_ssusb_xhci_tsp_e 1
#define reg_ckg_usbphy240_tsp ckgen01(0x0FF0)
#define reg_ckg_usbphy240_tsp_s 0
#define reg_ckg_usbphy240_tsp_e 2
#define reg_ckg_usbphy240_mux_tsp ckgen01(0x0FF4)
#define reg_ckg_usbphy240_mux_tsp_s 0
#define reg_ckg_usbphy240_mux_tsp_e 2
#define reg_ckg_usbphy30_tsp ckgen01(0x0FF8)
#define reg_ckg_usbphy30_tsp_s 0
#define reg_ckg_usbphy30_tsp_e 2
#define reg_ckg_smi_uhc_sel ckgen01(0x0FFC)
#define reg_ckg_smi_uhc_sel_s 0
#define reg_ckg_smi_uhc_sel_e 3
#define reg_ckg_ufs ckgen01(0x1000)
#define reg_ckg_ufs_s 0
#define reg_ckg_ufs_e 3
#define reg_ckg_ufs_tsp ckgen01(0x1000)
#define reg_ckg_ufs_tsp_s 8
#define reg_ckg_ufs_tsp_e 9
#define reg_ckg_ufs_aes ckgen01(0x1008)
#define reg_ckg_ufs_aes_s 0
#define reg_ckg_ufs_aes_e 3
#define reg_ckg_ufs_aes_tsp ckgen01(0x1008)
#define reg_ckg_ufs_aes_tsp_s 8
#define reg_ckg_ufs_aes_tsp_e 9
#define reg_ckg_ufs_mp_sap_cfg_tsp ckgen01(0x100C)
#define reg_ckg_ufs_mp_sap_cfg_tsp_s 0
#define reg_ckg_ufs_mp_sap_cfg_tsp_e 1
#define reg_ckg_ufs_rx_symbol_tsp ckgen01(0x1010)
#define reg_ckg_ufs_rx_symbol_tsp_s 0
#define reg_ckg_ufs_rx_symbol_tsp_e 2
#define reg_ckg_ufs_tx_symbol_tsp ckgen01(0x1014)
#define reg_ckg_ufs_tx_symbol_tsp_s 0
#define reg_ckg_ufs_tx_symbol_tsp_e 2
#define reg_ckg_ufs_unipro_cg_syn ckgen01(0x1018)
#define reg_ckg_ufs_unipro_cg_syn_s 0
#define reg_ckg_ufs_unipro_cg_syn_e 3
#define reg_ckg_ufs_unipro_cg_syn_tsp ckgen01(0x1018)
#define reg_ckg_ufs_unipro_cg_syn_tsp_s 8
#define reg_ckg_ufs_unipro_cg_syn_tsp_e 9
#define reg_ckg_smi_aesdma_sel ckgen01(0x1020)
#define reg_ckg_smi_aesdma_sel_s 0
#define reg_ckg_smi_aesdma_sel_e 3
#define reg_ckg_smi_tsp_sel ckgen01(0x1028)
#define reg_ckg_smi_tsp_sel_s 0
#define reg_ckg_smi_tsp_sel_e 3
#define reg_ckg_mcu_nonpm ckgen01(0x1040)
#define reg_ckg_mcu_nonpm_s 0
#define reg_ckg_mcu_nonpm_e 4
#define reg_ckg_mcu_nonpm_demod0 ckgen01(0x1040)
#define reg_ckg_mcu_nonpm_demod0_s 8
#define reg_ckg_mcu_nonpm_demod0_e 9
#define reg_ckg_mcu_nonpm_frciopmrv55 ckgen01(0x1040)
#define reg_ckg_mcu_nonpm_frciopmrv55_s 10
#define reg_ckg_mcu_nonpm_frciopmrv55_e 11
#define reg_ckg_mcu_nonpm_frcmehalo ckgen01(0x1040)
#define reg_ckg_mcu_nonpm_frcmehalo_s 12
#define reg_ckg_mcu_nonpm_frcmehalo_e 13
#define reg_ckg_mcu_nonpm_pcie_phy ckgen01(0x1040)
#define reg_ckg_mcu_nonpm_pcie_phy_s 14
#define reg_ckg_mcu_nonpm_pcie_phy_e 15
#define reg_ckg_mcu_nonpm_scace ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scace_s 0
#define reg_ckg_mcu_nonpm_scace_e 1
#define reg_ckg_mcu_nonpm_scdv ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scdv_s 2
#define reg_ckg_mcu_nonpm_scdv_e 3
#define reg_ckg_mcu_nonpm_scip ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scip_s 4
#define reg_ckg_mcu_nonpm_scip_e 5
#define reg_ckg_mcu_nonpm_scmw ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scmw_s 6
#define reg_ckg_mcu_nonpm_scmw_e 7
#define reg_ckg_mcu_nonpm_scnr ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scnr_s 8
#define reg_ckg_mcu_nonpm_scnr_e 9
#define reg_ckg_mcu_nonpm_scpq ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scpq_s 10
#define reg_ckg_mcu_nonpm_scpq_e 11
#define reg_ckg_mcu_nonpm_scscl ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scscl_s 12
#define reg_ckg_mcu_nonpm_scscl_e 13
#define reg_ckg_mcu_nonpm_scsr ckgen01(0x1048)
#define reg_ckg_mcu_nonpm_scsr_s 14
#define reg_ckg_mcu_nonpm_scsr_e 15
#define reg_ckg_mcu_nonpm_sctcon ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_sctcon_s 0
#define reg_ckg_mcu_nonpm_sctcon_e 1
#define reg_ckg_mcu_nonpm_ufs_phy ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_ufs_phy_s 2
#define reg_ckg_mcu_nonpm_ufs_phy_e 3
#define reg_ckg_mcu_nonpm_usb_phy ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_usb_phy_s 4
#define reg_ckg_mcu_nonpm_usb_phy_e 5
#define reg_ckg_xiu_vdec_soc ckgen01(0x1050)
#define reg_ckg_xiu_vdec_soc_s 6
#define reg_ckg_xiu_vdec_soc_e 7
#define reg_ckg_mcu_nonpm_aia ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_aia_s 8
#define reg_ckg_mcu_nonpm_aia_e 9
#define reg_ckg_mcu_nonpm_mheg5 ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_mheg5_s 10
#define reg_ckg_mcu_nonpm_mheg5_e 11
#define reg_ckg_mcu_nonpm_gpu_die ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_gpu_die_s 12
#define reg_ckg_mcu_nonpm_gpu_die_e 13
#define reg_ckg_mcu_nonpm_gpu_nodie ckgen01(0x1050)
#define reg_ckg_mcu_nonpm_gpu_nodie_s 14
#define reg_ckg_mcu_nonpm_gpu_nodie_e 15
#define reg_ckg_mcu_nonpm_hdmirx ckgen01(0x1058)
#define reg_ckg_mcu_nonpm_hdmirx_s 0
#define reg_ckg_mcu_nonpm_hdmirx_e 1
#define reg_ckg_mcu_nonpm_ip_wrap ckgen01(0x1058)
#define reg_ckg_mcu_nonpm_ip_wrap_s 2
#define reg_ckg_mcu_nonpm_ip_wrap_e 3
#define reg_ckg_mcu_nonpm_viva ckgen01(0x1058)
#define reg_ckg_mcu_nonpm_viva_s 4
#define reg_ckg_mcu_nonpm_viva_e 5
#define reg_ckg_mcu_nonpm_tsp ckgen01(0x1058)
#define reg_ckg_mcu_nonpm_tsp_s 6
#define reg_ckg_mcu_nonpm_tsp_e 7
#define reg_ckg_pextp_ahb_apb_tsp ckgen01(0x1058)
#define reg_ckg_pextp_ahb_apb_tsp_s 8
#define reg_ckg_pextp_ahb_apb_tsp_e 9
#define reg_ckg_mcu_au ckgen01(0x10E0)
#define reg_ckg_mcu_au_s 0
#define reg_ckg_mcu_au_e 4
#define reg_ckg_mcu_au_audio_r2 ckgen01(0x10E0)
#define reg_ckg_mcu_au_audio_r2_s 8
#define reg_ckg_mcu_au_audio_r2_e 9
#define reg_ckg_viva_au_mcu ckgen01(0x10E0)
#define reg_ckg_viva_au_mcu_s 10
#define reg_ckg_viva_au_mcu_e 12
#define reg_ckg_mcu_au_rv55audio ckgen01(0x10E0)
#define reg_ckg_mcu_au_rv55audio_s 14
#define reg_ckg_mcu_au_rv55audio_e 15
#define reg_ckg_mcu_codec ckgen01(0x10F8)
#define reg_ckg_mcu_codec_s 0
#define reg_ckg_mcu_codec_e 4
#define reg_ckg_mcu_dmd ckgen01(0x1110)
#define reg_ckg_mcu_dmd_s 0
#define reg_ckg_mcu_dmd_e 4
#define reg_ckg_mcu_dmd_demod0 ckgen01(0x1110)
#define reg_ckg_mcu_dmd_demod0_s 8
#define reg_ckg_mcu_dmd_demod0_e 9
#define reg_ckg_mcu_frc ckgen01(0x1128)
#define reg_ckg_mcu_frc_s 0
#define reg_ckg_mcu_frc_e 4
#define reg_ckg_mcu_frc_frciopmrv55 ckgen01(0x1128)
#define reg_ckg_mcu_frc_frciopmrv55_s 8
#define reg_ckg_mcu_frc_frciopmrv55_e 9
#define reg_ckg_mcu_frc_rv55frc ckgen01(0x1128)
#define reg_ckg_mcu_frc_rv55frc_s 10
#define reg_ckg_mcu_frc_rv55frc_e 11
#define reg_ckg_mcu_frc_rv55pqu ckgen01(0x1128)
#define reg_ckg_mcu_frc_rv55pqu_s 12
#define reg_ckg_mcu_frc_rv55pqu_e 13
#define reg_ckg_mcu_hdmi ckgen01(0x1140)
#define reg_ckg_mcu_hdmi_s 0
#define reg_ckg_mcu_hdmi_e 4
#define reg_ckg_mcu_hdmi_hdmirx ckgen01(0x1140)
#define reg_ckg_mcu_hdmi_hdmirx_s 10
#define reg_ckg_mcu_hdmi_hdmirx_e 12
#define reg_ckg_mcu_sc ckgen01(0x1170)
#define reg_ckg_mcu_sc_s 0
#define reg_ckg_mcu_sc_e 4
#define reg_ckg_mcu_xc_scace ckgen01(0x1170)
#define reg_ckg_mcu_xc_scace_s 10
#define reg_ckg_mcu_xc_scace_e 11
#define reg_ckg_mcu_xc_scdv ckgen01(0x1170)
#define reg_ckg_mcu_xc_scdv_s 12
#define reg_ckg_mcu_xc_scdv_e 13
#define reg_ckg_mcu_xc_scip ckgen01(0x1170)
#define reg_ckg_mcu_xc_scip_s 14
#define reg_ckg_mcu_xc_scip_e 15
#define reg_ckg_mcu_xc_scmw ckgen01(0x1178)
#define reg_ckg_mcu_xc_scmw_s 0
#define reg_ckg_mcu_xc_scmw_e 1
#define reg_ckg_mcu_xc_scnr ckgen01(0x1178)
#define reg_ckg_mcu_xc_scnr_s 2
#define reg_ckg_mcu_xc_scnr_e 3
#define reg_ckg_mcu_xc_scpq ckgen01(0x1178)
#define reg_ckg_mcu_xc_scpq_s 4
#define reg_ckg_mcu_xc_scpq_e 5
#define reg_ckg_mcu_xc_scscl ckgen01(0x1178)
#define reg_ckg_mcu_xc_scscl_s 6
#define reg_ckg_mcu_xc_scscl_e 7
#define reg_ckg_mcu_xc_scsr ckgen01(0x1178)
#define reg_ckg_mcu_xc_scsr_s 8
#define reg_ckg_mcu_xc_scsr_e 9
#define reg_ckg_mcu_xc_sctcon ckgen01(0x1178)
#define reg_ckg_mcu_xc_sctcon_s 10
#define reg_ckg_mcu_xc_sctcon_e 11
#define reg_ckg_mcu_vd ckgen01(0x11A0)
#define reg_ckg_mcu_vd_s 0
#define reg_ckg_mcu_vd_e 4
#define reg_ckg_mcu_vd_mheg5 ckgen01(0x11A0)
#define reg_ckg_mcu_vd_mheg5_s 10
#define reg_ckg_mcu_vd_mheg5_e 11
#define reg_ckg_mcu_bus ckgen01(0x11B8)
#define reg_ckg_mcu_bus_s 0
#define reg_ckg_mcu_bus_e 4
#define reg_ckg_mcu_bus_frciopmrv55 ckgen01(0x11B8)
#define reg_ckg_mcu_bus_frciopmrv55_s 8
#define reg_ckg_mcu_bus_frciopmrv55_e 9
#define reg_ckg_mcu_bus_scscl ckgen01(0x11B8)
#define reg_ckg_mcu_bus_scscl_s 10
#define reg_ckg_mcu_bus_scscl_e 11
#define reg_ckg_au_mcu_bus ckgen01(0x11B8)
#define reg_ckg_au_mcu_bus_s 12
#define reg_ckg_au_mcu_bus_e 14
#define reg_ckg_mcu_bus_demod0 ckgen01(0x11C0)
#define reg_ckg_mcu_bus_demod0_s 0
#define reg_ckg_mcu_bus_demod0_e 1
#define reg_ckg_mcu_bus_hdmirx ckgen01(0x11C0)
#define reg_ckg_mcu_bus_hdmirx_s 2
#define reg_ckg_mcu_bus_hdmirx_e 3
#define reg_ckg_mcu_bus_mheg5 ckgen01(0x11C0)
#define reg_ckg_mcu_bus_mheg5_s 4
#define reg_ckg_mcu_bus_mheg5_e 5
#define reg_ckg_mcu_bus_rv55frc ckgen01(0x11C0)
#define reg_ckg_mcu_bus_rv55frc_s 6
#define reg_ckg_mcu_bus_rv55frc_e 7
#define reg_ckg_mcu_bus_rv55pqu ckgen01(0x11C0)
#define reg_ckg_mcu_bus_rv55pqu_s 8
#define reg_ckg_mcu_bus_rv55pqu_e 9
#define reg_ckg_miic0 ckgen01(0x11F0)
#define reg_ckg_miic0_s 0
#define reg_ckg_miic0_e 3
#define reg_ckg_miic0_mheg5 ckgen01(0x11F0)
#define reg_ckg_miic0_mheg5_s 8
#define reg_ckg_miic0_mheg5_e 9
#define reg_ckg_miic1 ckgen01(0x11F8)
#define reg_ckg_miic1_s 0
#define reg_ckg_miic1_e 3
#define reg_ckg_miic1_mheg5 ckgen01(0x11F8)
#define reg_ckg_miic1_mheg5_s 8
#define reg_ckg_miic1_mheg5_e 9
#define reg_ckg_miic2 ckgen01(0x1200)
#define reg_ckg_miic2_s 0
#define reg_ckg_miic2_e 3
#define reg_ckg_miic2_mheg5 ckgen01(0x1200)
#define reg_ckg_miic2_mheg5_s 8
#define reg_ckg_miic2_mheg5_e 9
#define reg_ckg_miic3 ckgen01(0x1208)
#define reg_ckg_miic3_s 0
#define reg_ckg_miic3_e 3
#define reg_ckg_miic3_mheg5 ckgen01(0x1208)
#define reg_ckg_miic3_mheg5_s 8
#define reg_ckg_miic3_mheg5_e 9
#define reg_ckg_mspi_cilink ckgen01(0x1230)
#define reg_ckg_mspi_cilink_s 0
#define reg_ckg_mspi_cilink_e 2
#define reg_ckg_mspi_cilink_mheg5 ckgen01(0x1230)
#define reg_ckg_mspi_cilink_mheg5_s 8
#define reg_ckg_mspi_cilink_mheg5_e 9
#define reg_ckg_mspi_cilink_div ckgen01(0x1238)
#define reg_ckg_mspi_cilink_div_s 0
#define reg_ckg_mspi_cilink_div_e 4
#define reg_ckg_mspi0 ckgen01(0x1240)
#define reg_ckg_mspi0_s 0
#define reg_ckg_mspi0_e 2
#define reg_ckg_mspi0_mheg5 ckgen01(0x1240)
#define reg_ckg_mspi0_mheg5_s 8
#define reg_ckg_mspi0_mheg5_e 9
#define reg_ckg_mspi0_div ckgen01(0x1248)
#define reg_ckg_mspi0_div_s 0
#define reg_ckg_mspi0_div_e 4
#define reg_ckg_mspi1 ckgen01(0x1250)
#define reg_ckg_mspi1_s 0
#define reg_ckg_mspi1_e 2
#define reg_ckg_mspi1_mheg5 ckgen01(0x1250)
#define reg_ckg_mspi1_mheg5_s 8
#define reg_ckg_mspi1_mheg5_e 9
#define reg_ckg_mspi1_div ckgen01(0x1258)
#define reg_ckg_mspi1_div_s 0
#define reg_ckg_mspi1_div_e 4
#define reg_ckg_mspi2 ckgen01(0x1260)
#define reg_ckg_mspi2_s 0
#define reg_ckg_mspi2_e 2
#define reg_ckg_mspi2_mheg5 ckgen01(0x1260)
#define reg_ckg_mspi2_mheg5_s 8
#define reg_ckg_mspi2_mheg5_e 9
#define reg_ckg_mspi2_div ckgen01(0x1268)
#define reg_ckg_mspi2_div_s 0
#define reg_ckg_mspi2_div_e 4
#define reg_ckg_mspi3 ckgen01(0x1270)
#define reg_ckg_mspi3_s 0
#define reg_ckg_mspi3_e 2
#define reg_ckg_mspi3_mheg5 ckgen01(0x1270)
#define reg_ckg_mspi3_mheg5_s 8
#define reg_ckg_mspi3_mheg5_e 9
#define reg_ckg_mspi3_div ckgen01(0x1278)
#define reg_ckg_mspi3_div_s 0
#define reg_ckg_mspi3_div_e 4
#define reg_ckg_mspi4 ckgen01(0x1280)
#define reg_ckg_mspi4_s 0
#define reg_ckg_mspi4_e 2
#define reg_ckg_mspi4_mheg5 ckgen01(0x1280)
#define reg_ckg_mspi4_mheg5_s 8
#define reg_ckg_mspi4_mheg5_e 9
#define reg_ckg_mspi4_div ckgen01(0x1288)
#define reg_ckg_mspi4_div_s 0
#define reg_ckg_mspi4_div_e 4
#define reg_ckg_mspi5 ckgen01(0x1290)
#define reg_ckg_mspi5_s 0
#define reg_ckg_mspi5_e 2
#define reg_ckg_mspi5_mheg5 ckgen01(0x1290)
#define reg_ckg_mspi5_mheg5_s 8
#define reg_ckg_mspi5_mheg5_e 9
#define reg_ckg_mspi5_div ckgen01(0x1298)
#define reg_ckg_mspi5_div_s 0
#define reg_ckg_mspi5_div_e 4
#define reg_ckg_mspi6 ckgen01(0x12A0)
#define reg_ckg_mspi6_s 0
#define reg_ckg_mspi6_e 2
#define reg_ckg_mspi6_mheg5 ckgen01(0x12A0)
#define reg_ckg_mspi6_mheg5_s 8
#define reg_ckg_mspi6_mheg5_e 9
#define reg_ckg_mspi6_div ckgen01(0x12A8)
#define reg_ckg_mspi6_div_s 0
#define reg_ckg_mspi6_div_e 4
#define reg_ckg_mspi7 ckgen01(0x12B0)
#define reg_ckg_mspi7_s 0
#define reg_ckg_mspi7_e 2
#define reg_ckg_mspi7_mheg5 ckgen01(0x12B0)
#define reg_ckg_mspi7_mheg5_s 8
#define reg_ckg_mspi7_mheg5_e 9
#define reg_ckg_mspi7_div ckgen01(0x12B8)
#define reg_ckg_mspi7_div_s 0
#define reg_ckg_mspi7_div_e 4
#define reg_ckg_frc_mspi0 ckgen01(0x12C0)
#define reg_ckg_frc_mspi0_s 0
#define reg_ckg_frc_mspi0_e 2
#define reg_ckg_frc_mspi0_frciopmrv55 ckgen01(0x12C8)
#define reg_ckg_frc_mspi0_frciopmrv55_s 0
#define reg_ckg_frc_mspi0_frciopmrv55_e 1
#define reg_ckg_frc_mspi0_div ckgen01(0x12D0)
#define reg_ckg_frc_mspi0_div_s 0
#define reg_ckg_frc_mspi0_div_e 4
#define reg_ckg_spi ckgen01(0x12E8)
#define reg_ckg_spi_s 0
#define reg_ckg_spi_e 4
#define reg_ckg_spi_mheg5 ckgen01(0x12E8)
#define reg_ckg_spi_mheg5_s 8
#define reg_ckg_spi_mheg5_e 9
#define reg_ckg_uart0 ckgen01(0x1368)
#define reg_ckg_uart0_s 0
#define reg_ckg_uart0_e 3
#define reg_ckg_uart0_mheg5 ckgen01(0x1368)
#define reg_ckg_uart0_mheg5_s 8
#define reg_ckg_uart0_mheg5_e 9
#define reg_ckg_uart0_synth ckgen01(0x1370)
#define reg_ckg_uart0_synth_s 0
#define reg_ckg_uart0_synth_e 3
#define reg_ckg_uart1 ckgen01(0x1378)
#define reg_ckg_uart1_s 0
#define reg_ckg_uart1_e 3
#define reg_ckg_uart1_mheg5 ckgen01(0x1378)
#define reg_ckg_uart1_mheg5_s 8
#define reg_ckg_uart1_mheg5_e 9
#define reg_ckg_uart1_synth ckgen01(0x1380)
#define reg_ckg_uart1_synth_s 0
#define reg_ckg_uart1_synth_e 3
#define reg_ckg_uart2 ckgen01(0x1388)
#define reg_ckg_uart2_s 0
#define reg_ckg_uart2_e 3
#define reg_ckg_uart2_mheg5 ckgen01(0x1388)
#define reg_ckg_uart2_mheg5_s 8
#define reg_ckg_uart2_mheg5_e 9
#define reg_ckg_uart2_synth ckgen01(0x1390)
#define reg_ckg_uart2_synth_s 0
#define reg_ckg_uart2_synth_e 3
#define reg_ckg_frc_uart0 ckgen01(0x1398)
#define reg_ckg_frc_uart0_s 0
#define reg_ckg_frc_uart0_e 3
#define reg_ckg_frc_uart0_frciopmrv55 ckgen01(0x1398)
#define reg_ckg_frc_uart0_frciopmrv55_s 8
#define reg_ckg_frc_uart0_frciopmrv55_e 9
#define reg_ckg_frc_uart0_synth ckgen01(0x13A0)
#define reg_ckg_frc_uart0_synth_s 0
#define reg_ckg_frc_uart0_synth_e 3
#define reg_ckg_frc_uart1 ckgen01(0x13A8)
#define reg_ckg_frc_uart1_s 0
#define reg_ckg_frc_uart1_e 3
#define reg_ckg_frc_uart1_frciopmrv55 ckgen01(0x13A8)
#define reg_ckg_frc_uart1_frciopmrv55_s 8
#define reg_ckg_frc_uart1_frciopmrv55_e 9
#define reg_ckg_frc_uart1_synth ckgen01(0x13B0)
#define reg_ckg_frc_uart1_synth_s 0
#define reg_ckg_frc_uart1_synth_e 3
#define reg_ckg_fuart0 ckgen01(0x13B8)
#define reg_ckg_fuart0_s 0
#define reg_ckg_fuart0_e 3
#define reg_ckg_fuart0_mheg5 ckgen01(0x13B8)
#define reg_ckg_fuart0_mheg5_s 8
#define reg_ckg_fuart0_mheg5_e 9
#define reg_ckg_fuart0_synth ckgen01(0x13C0)
#define reg_ckg_fuart0_synth_s 0
#define reg_ckg_fuart0_synth_e 3
#define reg_ckg_au_uart0 ckgen01(0x13C8)
#define reg_ckg_au_uart0_s 0
#define reg_ckg_au_uart0_e 3
#define reg_ckg_au_uart0_viva ckgen01(0x13C8)
#define reg_ckg_au_uart0_viva_s 8
#define reg_ckg_au_uart0_viva_e 9
#define reg_ckg_au_uart0_synth ckgen01(0x13D0)
#define reg_ckg_au_uart0_synth_s 0
#define reg_ckg_au_uart0_synth_e 3
#define reg_ckg_frc_fuart0 ckgen01(0x13D8)
#define reg_ckg_frc_fuart0_s 0
#define reg_ckg_frc_fuart0_e 3
#define reg_ckg_frc_fuart0_frciopmrv55 ckgen01(0x13D8)
#define reg_ckg_frc_fuart0_frciopmrv55_s 8
#define reg_ckg_frc_fuart0_frciopmrv55_e 9
#define reg_ckg_frc_fuart0_synth ckgen01(0x13E0)
#define reg_ckg_frc_fuart0_synth_s 0
#define reg_ckg_frc_fuart0_synth_e 3
#define reg_sw_en_clkd_adc2adc_top_data ckgen01(0x14A8)
#define reg_sw_en_clkd_adc2adc_top_data_s 0
#define reg_sw_en_clkd_adc2adc_top_data_e 0
#define reg_sw_en_clkd_adc2gemiu2adc_top_data ckgen01(0x14AC)
#define reg_sw_en_clkd_adc2gemiu2adc_top_data_s 0
#define reg_sw_en_clkd_adc2gemiu2adc_top_data_e 0
#define reg_sw_en_clkd_adc2sc2adc_top_data ckgen01(0x14B0)
#define reg_sw_en_clkd_adc2sc2adc_top_data_s 0
#define reg_sw_en_clkd_adc2sc2adc_top_data_e 0
#define reg_sw_en_clkd_fblank2adc_top_data ckgen01(0x14B4)
#define reg_sw_en_clkd_fblank2adc_top_data_s 0
#define reg_sw_en_clkd_fblank2adc_top_data_e 0
#define reg_sw_en_clkd_vd2adc_top_data ckgen01(0x14B8)
#define reg_sw_en_clkd_vd2adc_top_data_s 0
#define reg_sw_en_clkd_vd2adc_top_data_e 0
#define reg_sw_en_clkfscx2_vd2adc_top_data ckgen01(0x14BC)
#define reg_sw_en_clkfscx2_vd2adc_top_data_s 0
#define reg_sw_en_clkfscx2_vd2adc_top_data_e 0
#define reg_sw_en_adc2adc ckgen01(0x14C0)
#define reg_sw_en_adc2adc_s 0
#define reg_sw_en_adc2adc_e 0
#define reg_sw_en_adc2miu2adc ckgen01(0x14C4)
#define reg_sw_en_adc2miu2adc_s 0
#define reg_sw_en_adc2miu2adc_e 0
#define reg_sw_en_adc2miusc2adc ckgen01(0x14C8)
#define reg_sw_en_adc2miusc2adc_s 0
#define reg_sw_en_adc2miusc2adc_e 0
#define reg_sw_en_adc2sc2adc ckgen01(0x14CC)
#define reg_sw_en_adc2sc2adc_s 0
#define reg_sw_en_adc2sc2adc_e 0
#define reg_sw_en_adcpll2002adc ckgen01(0x14D0)
#define reg_sw_en_adcpll2002adc_s 0
#define reg_sw_en_adcpll2002adc_e 0
#define reg_sw_en_adcpll4002adc ckgen01(0x14D4)
#define reg_sw_en_adcpll4002adc_s 0
#define reg_sw_en_adcpll4002adc_e 0
#define reg_sw_en_b_adc2adc ckgen01(0x14D8)
#define reg_sw_en_b_adc2adc_s 0
#define reg_sw_en_b_adc2adc_e 0
#define reg_sw_en_b_int2adc ckgen01(0x14DC)
#define reg_sw_en_b_int2adc_s 0
#define reg_sw_en_b_int2adc_e 0
#define reg_sw_en_clkpll2adc ckgen01(0x14E0)
#define reg_sw_en_clkpll2adc_s 0
#define reg_sw_en_clkpll2adc_e 0
#define reg_sw_en_cvbs_dac_a_digital0_mux2adc ckgen01(0x14E4)
#define reg_sw_en_cvbs_dac_a_digital0_mux2adc_s 0
#define reg_sw_en_cvbs_dac_a_digital0_mux2adc_e 0
#define reg_sw_en_cvbs_dac_a_digital02adc ckgen01(0x14E8)
#define reg_sw_en_cvbs_dac_a_digital02adc_s 0
#define reg_sw_en_cvbs_dac_a_digital02adc_e 0
#define reg_sw_en_cvbs_dac_a_digital12adc ckgen01(0x14EC)
#define reg_sw_en_cvbs_dac_a_digital12adc_s 0
#define reg_sw_en_cvbs_dac_a_digital12adc_e 0
#define reg_sw_en_dig_2162adc ckgen01(0x14F0)
#define reg_sw_en_dig_2162adc_s 0
#define reg_sw_en_dig_2162adc_e 0
#define reg_sw_en_fblank2adc ckgen01(0x14F4)
#define reg_sw_en_fblank2adc_s 0
#define reg_sw_en_fblank2adc_e 0
#define reg_sw_en_fsc_vd2adc ckgen01(0x14F8)
#define reg_sw_en_fsc_vd2adc_s 0
#define reg_sw_en_fsc_vd2adc_e 0
#define reg_sw_en_g_adc2adc ckgen01(0x1500)
#define reg_sw_en_g_adc2adc_s 0
#define reg_sw_en_g_adc2adc_e 0
#define reg_sw_en_g_int2adc ckgen01(0x1504)
#define reg_sw_en_g_int2adc_s 0
#define reg_sw_en_g_int2adc_e 0
#define reg_sw_en_isog2adc ckgen01(0x1508)
#define reg_sw_en_isog2adc_s 0
#define reg_sw_en_isog2adc_e 0
#define reg_sw_en_nco_clk2adc ckgen01(0x1510)
#define reg_sw_en_nco_clk2adc_s 0
#define reg_sw_en_nco_clk2adc_e 0
#define reg_sw_en_r_adc2adc ckgen01(0x1518)
#define reg_sw_en_r_adc2adc_s 0
#define reg_sw_en_r_adc2adc_e 0
#define reg_sw_en_r_int2adc ckgen01(0x151C)
#define reg_sw_en_r_int2adc_s 0
#define reg_sw_en_r_int2adc_e 0
#define reg_sw_en_vd_iclamp2adc ckgen01(0x1520)
#define reg_sw_en_vd_iclamp2adc_s 0
#define reg_sw_en_vd_iclamp2adc_e 0
#define reg_sw_en_vd_iclamp2video_atop ckgen01(0x1524)
#define reg_sw_en_vd_iclamp2video_atop_s 0
#define reg_sw_en_vd_iclamp2video_atop_e 0
#define reg_sw_en_vd_nco_clk2adc ckgen01(0x1528)
#define reg_sw_en_vd_nco_clk2adc_s 0
#define reg_sw_en_vd_nco_clk2adc_e 0
#define reg_sw_en_vd2adc ckgen01(0x152C)
#define reg_sw_en_vd2adc_s 0
#define reg_sw_en_vd2adc_e 0
#define reg_sw_en_vdpll4002adc ckgen01(0x1530)
#define reg_sw_en_vdpll4002adc_s 0
#define reg_sw_en_vdpll4002adc_e 0
#define reg_sw_en_xtal12_4interrupt2adc ckgen01(0x1534)
#define reg_sw_en_xtal12_4interrupt2adc_s 0
#define reg_sw_en_xtal12_4interrupt2adc_e 0
#define reg_sw_en_xtal12_4plugdet2adc ckgen01(0x1538)
#define reg_sw_en_xtal12_4plugdet2adc_s 0
#define reg_sw_en_xtal12_4plugdet2adc_e 0
#define reg_sw_en_xtal122adc ckgen01(0x153C)
#define reg_sw_en_xtal122adc_s 0
#define reg_sw_en_xtal122adc_e 0
#define reg_sw_en_xtal242adc ckgen01(0x1540)
#define reg_sw_en_xtal242adc_s 0
#define reg_sw_en_xtal242adc_e 0
#define reg_sw_en_y_adc2adc ckgen01(0x1544)
#define reg_sw_en_y_adc2adc_s 0
#define reg_sw_en_y_adc2adc_e 0
#define reg_sw_en_y_int2adc ckgen01(0x1548)
#define reg_sw_en_y_int2adc_s 0
#define reg_sw_en_y_int2adc_e 0
#define reg_sw_en_yuv_adc2adc ckgen01(0x154C)
#define reg_sw_en_yuv_adc2adc_s 0
#define reg_sw_en_yuv_adc2adc_e 0
#define reg_sw_en_adcplb_mpll2adc ckgen01(0x1550)
#define reg_sw_en_adcplb_mpll2adc_s 0
#define reg_sw_en_adcplb_mpll2adc_e 0
#define reg_sw_en_disp_mfdec2gpu_nodie ckgen01(0x1564)
#define reg_sw_en_disp_mfdec2gpu_nodie_s 0
#define reg_sw_en_disp_mfdec2gpu_nodie_e 0
#define reg_sw_en_disp_mfdec2scnr ckgen01(0x1564)
#define reg_sw_en_disp_mfdec2scnr_s 1
#define reg_sw_en_disp_mfdec2scnr_e 1
#define reg_sw_en_dap2frciopm ckgen01(0x1570)
#define reg_sw_en_dap2frciopm_s 0
#define reg_sw_en_dap2frciopm_e 0
#define reg_sw_en_dap2frciopmrv55 ckgen01(0x1570)
#define reg_sw_en_dap2frciopmrv55_s 1
#define reg_sw_en_dap2frciopmrv55_e 1
#define reg_sw_en_dap2rv55audio ckgen01(0x1570)
#define reg_sw_en_dap2rv55audio_s 2
#define reg_sw_en_dap2rv55audio_e 2
#define reg_sw_en_dap2rv55frc ckgen01(0x1570)
#define reg_sw_en_dap2rv55frc_s 3
#define reg_sw_en_dap2rv55frc_e 3
#define reg_sw_en_dap2rv55pqu ckgen01(0x1570)
#define reg_sw_en_dap2rv55pqu_s 4
#define reg_sw_en_dap2rv55pqu_e 4
#define reg_sw_en_dap_tck2rv55audio ckgen01(0x1574)
#define reg_sw_en_dap_tck2rv55audio_s 0
#define reg_sw_en_dap_tck2rv55audio_e 0
#define reg_sw_en_frc_fclk_2x2deflicker ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2deflicker_s 0
#define reg_sw_en_frc_fclk_2x2deflicker_e 0
#define reg_sw_en_frc_fclk_2x2fdclk_2x ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2fdclk_2x_s 1
#define reg_sw_en_frc_fclk_2x2fdclk_2x_e 1
#define reg_sw_en_frc_fclk_2x2frciopm ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2frciopm_s 2
#define reg_sw_en_frc_fclk_2x2frciopm_e 2
#define reg_sw_en_frc_fclk_2x2frciopmrv55 ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2frciopmrv55_s 3
#define reg_sw_en_frc_fclk_2x2frciopmrv55_e 3
#define reg_sw_en_frc_fclk_2x2mi_ph3 ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2mi_ph3_s 4
#define reg_sw_en_frc_fclk_2x2mi_ph3_e 4
#define reg_sw_en_frc_fclk_2x2mi_ph4 ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2mi_ph4_s 5
#define reg_sw_en_frc_fclk_2x2mi_ph4_e 5
#define reg_sw_en_frc_fclk_2x2out_stage ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2out_stage_s 6
#define reg_sw_en_frc_fclk_2x2out_stage_e 6
#define reg_sw_en_frc_fclk_2x2snr ckgen01(0x1578)
#define reg_sw_en_frc_fclk_2x2snr_s 8
#define reg_sw_en_frc_fclk_2x2snr_e 8
#define reg_sw_en_frc_fclk_2xplus2frciopmrv55 ckgen01(0x157C)
#define reg_sw_en_frc_fclk_2xplus2frciopmrv55_s 0
#define reg_sw_en_frc_fclk_2xplus2frciopmrv55_e 0
#define reg_sw_en_frc_fclk_2xplus2scip ckgen01(0x157C)
#define reg_sw_en_frc_fclk_2xplus2scip_s 1
#define reg_sw_en_frc_fclk_2xplus2scip_e 1
#define reg_sw_en_frc_fclk_2xplus2scmw ckgen01(0x157C)
#define reg_sw_en_frc_fclk_2xplus2scmw_s 2
#define reg_sw_en_frc_fclk_2xplus2scmw_e 2
#define reg_sw_en_frc_fclk2fdclk ckgen01(0x1580)
#define reg_sw_en_frc_fclk2fdclk_s 0
#define reg_sw_en_frc_fclk2fdclk_e 0
#define reg_sw_en_frc_fclk2frciopm ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frciopm_s 1
#define reg_sw_en_frc_fclk2frciopm_e 1
#define reg_sw_en_frc_fclk2frciopmrv55 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frciopmrv55_s 2
#define reg_sw_en_frc_fclk2frciopmrv55_e 2
#define reg_sw_en_frc_fclk2frcmemlb_clk_all ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_all_s 3
#define reg_sw_en_frc_fclk2frcmemlb_clk_all_e 3
#define reg_sw_en_frc_fclk2frcmemlb_clk_mlb_sram ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_mlb_sram_s 4
#define reg_sw_en_frc_fclk2frcmemlb_clk_mlb_sram_e 4
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_0 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_0_s 5
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_0_e 5
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_1 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_1_s 6
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_1_e 6
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_2 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_2_s 7
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_2_e 7
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_3 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_3_s 8
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_3_e 8
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_4 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_4_s 9
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_4_e 9
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_5 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_5_s 10
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_5_e 10
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_6 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_6_s 11
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_6_e 11
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_7 ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_7_s 12
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_7_e 12
#define reg_sw_en_frc_fclk2frcmemlb_gmv ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmemlb_gmv_s 13
#define reg_sw_en_frc_fclk2frcmemlb_gmv_e 13
#define reg_sw_en_frc_fclk2frcmi_clk_all ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmi_clk_all_s 14
#define reg_sw_en_frc_fclk2frcmi_clk_all_e 14
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_l ckgen01(0x1580)
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_l_s 15
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_l_e 15
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_r ckgen01(0x1584)
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_r_s 0
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_r_e 0
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_sram_l ckgen01(0x1584)
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_sram_l_s 1
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_sram_l_e 1
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_sram_r ckgen01(0x1584)
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_sram_r_s 2
#define reg_sw_en_frc_fclk2frcmi_clk_mlb_mi_sram_r_e 2
#define reg_sw_en_frc_fclk2me ckgen01(0x1584)
#define reg_sw_en_frc_fclk2me_s 3
#define reg_sw_en_frc_fclk2me_e 3
#define reg_sw_en_frc_fclk2me_4x4 ckgen01(0x1584)
#define reg_sw_en_frc_fclk2me_4x4_s 4
#define reg_sw_en_frc_fclk2me_4x4_e 4
#define reg_sw_en_frc_fclk2me_ph1 ckgen01(0x1584)
#define reg_sw_en_frc_fclk2me_ph1_s 5
#define reg_sw_en_frc_fclk2me_ph1_e 5
#define reg_sw_en_frc_fclk2me_ph2 ckgen01(0x1584)
#define reg_sw_en_frc_fclk2me_ph2_s 6
#define reg_sw_en_frc_fclk2me_ph2_e 6
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_8 ckgen01(0x1584)
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_8_s 7
#define reg_sw_en_frc_fclk2frcmemlb_clk_sad_8_e 7
#define reg_sw_en_rv55frc_jtag_tck2rv55frc ckgen01(0x158C)
#define reg_sw_en_rv55frc_jtag_tck2rv55frc_s 0
#define reg_sw_en_rv55frc_jtag_tck2rv55frc_e 0
#define reg_sw_en_rv55pqu_jtag_tck2rv55pqu ckgen01(0x1590)
#define reg_sw_en_rv55pqu_jtag_tck2rv55pqu_s 0
#define reg_sw_en_rv55pqu_jtag_tck2rv55pqu_e 0
#define reg_sw_en_rv_tck2rv55frc ckgen01(0x1594)
#define reg_sw_en_rv_tck2rv55frc_s 0
#define reg_sw_en_rv_tck2rv55frc_e 0
#define reg_sw_en_rv_tck2rv55pqu ckgen01(0x1594)
#define reg_sw_en_rv_tck2rv55pqu_s 1
#define reg_sw_en_rv_tck2rv55pqu_e 1
#define reg_sw_en_rv55dap_jtag_tck2frciopm ckgen01(0x159C)
#define reg_sw_en_rv55dap_jtag_tck2frciopm_s 0
#define reg_sw_en_rv55dap_jtag_tck2frciopm_e 0
#define reg_sw_en_rv55dap_jtag_tck2frciopmrv55 ckgen01(0x159C)
#define reg_sw_en_rv55dap_jtag_tck2frciopmrv55_s 1
#define reg_sw_en_rv55dap_jtag_tck2frciopmrv55_e 1
#define reg_sw_en_rv55frc2rv55frc ckgen01(0x15A4)
#define reg_sw_en_rv55frc2rv55frc_s 0
#define reg_sw_en_rv55frc2rv55frc_e 0
#define reg_sw_en_rv55pqu2rv55pqu ckgen01(0x15A8)
#define reg_sw_en_rv55pqu2rv55pqu_s 0
#define reg_sw_en_rv55pqu2rv55pqu_e 0
#define reg_sw_en_xcsrspll_syn2xcsrspll_dmacro ckgen01(0x15AC)
#define reg_sw_en_xcsrspll_syn2xcsrspll_dmacro_s 0
#define reg_sw_en_xcsrspll_syn2xcsrspll_dmacro_e 0
#define reg_sw_en_xtal_12m2frciopm ckgen01(0x15B4)
#define reg_sw_en_xtal_12m2frciopm_s 0
#define reg_sw_en_xtal_12m2frciopm_e 0
#define reg_sw_en_xtal_12m2frciopmrv55 ckgen01(0x15B4)
#define reg_sw_en_xtal_12m2frciopmrv55_s 1
#define reg_sw_en_xtal_12m2frciopmrv55_e 1
#define reg_sw_en_xtal_12m2rv55audio ckgen01(0x15B4)
#define reg_sw_en_xtal_12m2rv55audio_s 2
#define reg_sw_en_xtal_12m2rv55audio_e 2
#define reg_sw_en_xtal_12m2rv55frc ckgen01(0x15B4)
#define reg_sw_en_xtal_12m2rv55frc_s 3
#define reg_sw_en_xtal_12m2rv55frc_e 3
#define reg_sw_en_xtal_12m2rv55pqu ckgen01(0x15B4)
#define reg_sw_en_xtal_12m2rv55pqu_s 4
#define reg_sw_en_xtal_12m2rv55pqu_e 4
#define reg_sw_en_xtal_24m2frciopm ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2frciopm_s 0
#define reg_sw_en_xtal_24m2frciopm_e 0
#define reg_sw_en_xtal_24m2frciopmrv55 ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2frciopmrv55_s 1
#define reg_sw_en_xtal_24m2frciopmrv55_e 1
#define reg_sw_en_xtal_24m2frcmehalo ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2frcmehalo_s 2
#define reg_sw_en_xtal_24m2frcmehalo_e 2
#define reg_sw_en_xtal_24m2frcmemlb ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2frcmemlb_s 3
#define reg_sw_en_xtal_24m2frcmemlb_e 3
#define reg_sw_en_xtal_24m2frcmi ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2frcmi_s 4
#define reg_sw_en_xtal_24m2frcmi_e 4
#define reg_sw_en_xtal_24m2rv55audio ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2rv55audio_s 5
#define reg_sw_en_xtal_24m2rv55audio_e 5
#define reg_sw_en_xtal_24m2rv55frc ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2rv55frc_s 6
#define reg_sw_en_xtal_24m2rv55frc_e 6
#define reg_sw_en_xtal_24m2rv55pqu ckgen01(0x15C0)
#define reg_sw_en_xtal_24m2rv55pqu_s 7
#define reg_sw_en_xtal_24m2rv55pqu_e 7
#define reg_sw_en_ge_fifo_r2ge ckgen01(0x15CC)
#define reg_sw_en_ge_fifo_r2ge_s 0
#define reg_sw_en_ge_fifo_r2ge_e 0
#define reg_sw_en_ge_fifo_w2ge ckgen01(0x15D0)
#define reg_sw_en_ge_fifo_w2ge_s 0
#define reg_sw_en_ge_fifo_w2ge_e 0
#define reg_sw_en_ge_psram2ge ckgen01(0x15D4)
#define reg_sw_en_ge_psram2ge_s 0
#define reg_sw_en_ge_psram2ge_e 0
#define reg_sw_en_ge2ge ckgen01(0x15D8)
#define reg_sw_en_ge2ge_s 0
#define reg_sw_en_ge2ge_e 0
#define reg_sw_en_clk_128fs_fb_s02mac ckgen01(0x15E4)
#define reg_sw_en_clk_128fs_fb_s02mac_s 0
#define reg_sw_en_clk_128fs_fb_s02mac_e 0
#define reg_sw_en_clk_128fs_fb_s12mac ckgen01(0x15E8)
#define reg_sw_en_clk_128fs_fb_s12mac_s 0
#define reg_sw_en_clk_128fs_fb_s12mac_e 0
#define reg_sw_en_clk_128fs_s02mac ckgen01(0x15EC)
#define reg_sw_en_clk_128fs_s02mac_s 0
#define reg_sw_en_clk_128fs_s02mac_e 0
#define reg_sw_en_clk_128fs_s12mac ckgen01(0x15F0)
#define reg_sw_en_clk_128fs_s12mac_s 0
#define reg_sw_en_clk_128fs_s12mac_e 0
#define reg_sw_en_clk_2162mac ckgen01(0x15F4)
#define reg_sw_en_clk_2162mac_s 0
#define reg_sw_en_clk_2162mac_e 0
#define reg_sw_en_clk_cts_synth_s02mac ckgen01(0x15F8)
#define reg_sw_en_clk_cts_synth_s02mac_s 0
#define reg_sw_en_clk_cts_synth_s02mac_e 0
#define reg_sw_en_clk_cts_synth_s12mac ckgen01(0x15FC)
#define reg_sw_en_clk_cts_synth_s12mac_s 0
#define reg_sw_en_clk_cts_synth_s12mac_e 0
#define reg_sw_en_clk_det_inner_misc_02mac ckgen01(0x1600)
#define reg_sw_en_clk_det_inner_misc_02mac_s 0
#define reg_sw_en_clk_det_inner_misc_02mac_e 0
#define reg_sw_en_clk_det_inner_misc_12mac ckgen01(0x1604)
#define reg_sw_en_clk_det_inner_misc_12mac_s 0
#define reg_sw_en_clk_det_inner_misc_12mac_e 0
#define reg_sw_en_clk_dsc_engine2dsc ckgen01(0x1608)
#define reg_sw_en_clk_dsc_engine2dsc_s 0
#define reg_sw_en_clk_dsc_engine2dsc_e 0
#define reg_sw_en_clk_dvi2miu_rd_s02mac ckgen01(0x160C)
#define reg_sw_en_clk_dvi2miu_rd_s02mac_s 0
#define reg_sw_en_clk_dvi2miu_rd_s02mac_e 0
#define reg_sw_en_clk_dvi2miu_rd_s12mac ckgen01(0x1610)
#define reg_sw_en_clk_dvi2miu_rd_s12mac_s 0
#define reg_sw_en_clk_dvi2miu_rd_s12mac_e 0
#define reg_sw_en_clk_dvi2miu_wr_s02mac ckgen01(0x1614)
#define reg_sw_en_clk_dvi2miu_wr_s02mac_s 0
#define reg_sw_en_clk_dvi2miu_wr_s02mac_e 0
#define reg_sw_en_clk_dvi2miu_wr_s12mac ckgen01(0x1618)
#define reg_sw_en_clk_dvi2miu_wr_s12mac_s 0
#define reg_sw_en_clk_dvi2miu_wr_s12mac_e 0
#define reg_sw_en_clk_link_dscd2mac ckgen01(0x161C)
#define reg_sw_en_clk_link_dscd2mac_s 0
#define reg_sw_en_clk_link_dscd2mac_e 0
#define reg_sw_en_clk_mpll_4322mac ckgen01(0x1620)
#define reg_sw_en_clk_mpll_4322mac_s 0
#define reg_sw_en_clk_mpll_4322mac_e 0
#define reg_sw_en_clk_mpll_8642phy ckgen01(0x1624)
#define reg_sw_en_clk_mpll_8642phy_s 0
#define reg_sw_en_clk_mpll_8642phy_e 0
#define reg_sw_en_clk_pix_tmdspll_dscd2mac ckgen01(0x1628)
#define reg_sw_en_clk_pix_tmdspll_dscd2mac_s 0
#define reg_sw_en_clk_pix_tmdspll_dscd2mac_e 0
#define reg_sw_en_clk_pix_xc_s02mac ckgen01(0x162C)
#define reg_sw_en_clk_pix_xc_s02mac_s 0
#define reg_sw_en_clk_pix_xc_s02mac_e 0
#define reg_sw_en_clk_pix_xc_s12mac ckgen01(0x1630)
#define reg_sw_en_clk_pix_xc_s12mac_s 0
#define reg_sw_en_clk_pix_xc_s12mac_e 0
#define reg_sw_en_clk_r2_hdmi2mac ckgen01(0x1634)
#define reg_sw_en_clk_r2_hdmi2mac_s 0
#define reg_sw_en_clk_r2_hdmi2mac_e 0
#define reg_sw_en_clk_timing_det_dtop2mac ckgen01(0x1638)
#define reg_sw_en_clk_timing_det_dtop2mac_s 0
#define reg_sw_en_clk_timing_det_dtop2mac_e 0
#define reg_sw_en_clk_tmds_audio_s02mac ckgen01(0x163C)
#define reg_sw_en_clk_tmds_audio_s02mac_s 0
#define reg_sw_en_clk_tmds_audio_s02mac_e 0
#define reg_sw_en_clk_tmds_audio_s12mac ckgen01(0x1640)
#define reg_sw_en_clk_tmds_audio_s12mac_s 0
#define reg_sw_en_clk_tmds_audio_s12mac_e 0
#define reg_sw_en_clk_tmds_dscd2mac ckgen01(0x1644)
#define reg_sw_en_clk_tmds_dscd2mac_s 0
#define reg_sw_en_clk_tmds_dscd2mac_e 0
#define reg_sw_en_clk_xtal_242mac ckgen01(0x1648)
#define reg_sw_en_clk_xtal_242mac_s 0
#define reg_sw_en_clk_xtal_242mac_e 0
#define reg_sw_en_clk_xtal_hdmi_122mac ckgen01(0x164C)
#define reg_sw_en_clk_xtal_hdmi_122mac_s 0
#define reg_sw_en_clk_xtal_hdmi_122mac_e 0
#define reg_sw_en_earc_audio2earc ckgen01(0x1650)
#define reg_sw_en_earc_audio2earc_s 0
#define reg_sw_en_earc_audio2earc_e 0
#define reg_sw_en_earc_cm2earc ckgen01(0x1654)
#define reg_sw_en_earc_cm2earc_s 0
#define reg_sw_en_earc_cm2earc_e 0
#define reg_sw_en_earc_debounce2earc ckgen01(0x1658)
#define reg_sw_en_earc_debounce2earc_s 0
#define reg_sw_en_earc_debounce2earc_e 0
#define reg_sw_en_earc_dm_prbs2earc ckgen01(0x165C)
#define reg_sw_en_earc_dm_prbs2earc_s 0
#define reg_sw_en_earc_dm_prbs2earc_e 0
#define reg_sw_en_p0_clk_det_dec_misc_02mac ckgen01(0x1664)
#define reg_sw_en_p0_clk_det_dec_misc_02mac_s 0
#define reg_sw_en_p0_clk_det_dec_misc_02mac_e 0
#define reg_sw_en_p0_clk_det_dec_misc_12mac ckgen01(0x1668)
#define reg_sw_en_p0_clk_det_dec_misc_12mac_s 0
#define reg_sw_en_p0_clk_det_dec_misc_12mac_e 0
#define reg_sw_en_p0_clk_det_dep_misc_02mac ckgen01(0x166C)
#define reg_sw_en_p0_clk_det_dep_misc_02mac_s 0
#define reg_sw_en_p0_clk_det_dep_misc_02mac_e 0
#define reg_sw_en_p0_clk_det_dep_misc_12mac ckgen01(0x1670)
#define reg_sw_en_p0_clk_det_dep_misc_12mac_s 0
#define reg_sw_en_p0_clk_det_dep_misc_12mac_e 0
#define reg_sw_en_p0_clk_link2mac ckgen01(0x1674)
#define reg_sw_en_p0_clk_link2mac_s 0
#define reg_sw_en_p0_clk_link2mac_e 0
#define reg_sw_en_p0_clk_pix_1p2mac ckgen01(0x1678)
#define reg_sw_en_p0_clk_pix_1p2mac_s 0
#define reg_sw_en_p0_clk_pix_1p2mac_e 0
#define reg_sw_en_p0_clk_pix_8p2mac ckgen01(0x167C)
#define reg_sw_en_p0_clk_pix_8p2mac_s 0
#define reg_sw_en_p0_clk_pix_8p2mac_e 0
#define reg_sw_en_p0_clk_pix_dc_mux2mac ckgen01(0x1680)
#define reg_sw_en_p0_clk_pix_dc_mux2mac_s 0
#define reg_sw_en_p0_clk_pix_dc_mux2mac_e 0
#define reg_sw_en_p0_clk_pix_rcv_mux2mac ckgen01(0x1684)
#define reg_sw_en_p0_clk_pix_rcv_mux2mac_s 0
#define reg_sw_en_p0_clk_pix_rcv_mux2mac_e 0
#define reg_sw_en_p0_clk_pix_rep_1p2mac ckgen01(0x1688)
#define reg_sw_en_p0_clk_pix_rep_1p2mac_s 0
#define reg_sw_en_p0_clk_pix_rep_1p2mac_e 0
#define reg_sw_en_p0_clk_pix_tmdspll2mac ckgen01(0x168C)
#define reg_sw_en_p0_clk_pix_tmdspll2mac_s 0
#define reg_sw_en_p0_clk_pix_tmdspll2mac_e 0
#define reg_sw_en_p0_clk_pix_xc_mux2mac ckgen01(0x1690)
#define reg_sw_en_p0_clk_pix_xc_mux2mac_s 0
#define reg_sw_en_p0_clk_pix_xc_mux2mac_e 0
#define reg_sw_en_p0_clk_timing_det_dec2mac ckgen01(0x1694)
#define reg_sw_en_p0_clk_timing_det_dec2mac_s 0
#define reg_sw_en_p0_clk_timing_det_dec2mac_e 0
#define reg_sw_en_p0_clk_timing_det_dep2mac ckgen01(0x1698)
#define reg_sw_en_p0_clk_timing_det_dep2mac_s 0
#define reg_sw_en_p0_clk_timing_det_dep2mac_e 0
#define reg_sw_en_p0_clk_tmds_frl_8p2mac ckgen01(0x169C)
#define reg_sw_en_p0_clk_tmds_frl_8p2mac_s 0
#define reg_sw_en_p0_clk_tmds_frl_8p2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdcp_1p2mac ckgen01(0x16A0)
#define reg_sw_en_p0_clk_tmds_hdcp_1p2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdcp_1p2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdcp_4p2mac ckgen01(0x16A4)
#define reg_sw_en_p0_clk_tmds_hdcp_4p2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdcp_4p2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdcp_8p2mac ckgen01(0x16A8)
#define reg_sw_en_p0_clk_tmds_hdcp_8p2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdcp_8p2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdcp_mux2mac ckgen01(0x16AC)
#define reg_sw_en_p0_clk_tmds_hdcp_mux2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdcp_mux2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdmi_1p2mac ckgen01(0x16B0)
#define reg_sw_en_p0_clk_tmds_hdmi_1p2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdmi_1p2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdmi_8p2mac ckgen01(0x16B4)
#define reg_sw_en_p0_clk_tmds_hdmi_8p2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdmi_8p2mac_e 0
#define reg_sw_en_p0_clk_tmds_hdmi_mux2mac ckgen01(0x16B8)
#define reg_sw_en_p0_clk_tmds_hdmi_mux2mac_s 0
#define reg_sw_en_p0_clk_tmds_hdmi_mux2mac_e 0
#define reg_sw_en_p1_clk_det_dec_misc_02mac ckgen01(0x16BC)
#define reg_sw_en_p1_clk_det_dec_misc_02mac_s 0
#define reg_sw_en_p1_clk_det_dec_misc_02mac_e 0
#define reg_sw_en_p1_clk_det_dec_misc_12mac ckgen01(0x16C0)
#define reg_sw_en_p1_clk_det_dec_misc_12mac_s 0
#define reg_sw_en_p1_clk_det_dec_misc_12mac_e 0
#define reg_sw_en_p1_clk_det_dep_misc_02mac ckgen01(0x16C4)
#define reg_sw_en_p1_clk_det_dep_misc_02mac_s 0
#define reg_sw_en_p1_clk_det_dep_misc_02mac_e 0
#define reg_sw_en_p1_clk_det_dep_misc_12mac ckgen01(0x16C8)
#define reg_sw_en_p1_clk_det_dep_misc_12mac_s 0
#define reg_sw_en_p1_clk_det_dep_misc_12mac_e 0
#define reg_sw_en_p1_clk_link2mac ckgen01(0x16CC)
#define reg_sw_en_p1_clk_link2mac_s 0
#define reg_sw_en_p1_clk_link2mac_e 0
#define reg_sw_en_p1_clk_pix_1p2mac ckgen01(0x16D0)
#define reg_sw_en_p1_clk_pix_1p2mac_s 0
#define reg_sw_en_p1_clk_pix_1p2mac_e 0
#define reg_sw_en_p1_clk_pix_8p2mac ckgen01(0x16D4)
#define reg_sw_en_p1_clk_pix_8p2mac_s 0
#define reg_sw_en_p1_clk_pix_8p2mac_e 0
#define reg_sw_en_p1_clk_pix_dc_mux2mac ckgen01(0x16D8)
#define reg_sw_en_p1_clk_pix_dc_mux2mac_s 0
#define reg_sw_en_p1_clk_pix_dc_mux2mac_e 0
#define reg_sw_en_p1_clk_pix_rcv_mux2mac ckgen01(0x16DC)
#define reg_sw_en_p1_clk_pix_rcv_mux2mac_s 0
#define reg_sw_en_p1_clk_pix_rcv_mux2mac_e 0
#define reg_sw_en_p1_clk_pix_rep_1p2mac ckgen01(0x16E0)
#define reg_sw_en_p1_clk_pix_rep_1p2mac_s 0
#define reg_sw_en_p1_clk_pix_rep_1p2mac_e 0
#define reg_sw_en_p1_clk_pix_tmdspll2mac ckgen01(0x16E4)
#define reg_sw_en_p1_clk_pix_tmdspll2mac_s 0
#define reg_sw_en_p1_clk_pix_tmdspll2mac_e 0
#define reg_sw_en_p1_clk_pix_xc_mux2mac ckgen01(0x16E8)
#define reg_sw_en_p1_clk_pix_xc_mux2mac_s 0
#define reg_sw_en_p1_clk_pix_xc_mux2mac_e 0
#define reg_sw_en_p1_clk_timing_det_dec2mac ckgen01(0x16EC)
#define reg_sw_en_p1_clk_timing_det_dec2mac_s 0
#define reg_sw_en_p1_clk_timing_det_dec2mac_e 0
#define reg_sw_en_p1_clk_timing_det_dep2mac ckgen01(0x16F0)
#define reg_sw_en_p1_clk_timing_det_dep2mac_s 0
#define reg_sw_en_p1_clk_timing_det_dep2mac_e 0
#define reg_sw_en_p1_clk_tmds_frl_8p2mac ckgen01(0x16F4)
#define reg_sw_en_p1_clk_tmds_frl_8p2mac_s 0
#define reg_sw_en_p1_clk_tmds_frl_8p2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdcp_1p2mac ckgen01(0x16F8)
#define reg_sw_en_p1_clk_tmds_hdcp_1p2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdcp_1p2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdcp_4p2mac ckgen01(0x16FC)
#define reg_sw_en_p1_clk_tmds_hdcp_4p2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdcp_4p2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdcp_8p2mac ckgen01(0x1700)
#define reg_sw_en_p1_clk_tmds_hdcp_8p2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdcp_8p2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdcp_mux2mac ckgen01(0x1704)
#define reg_sw_en_p1_clk_tmds_hdcp_mux2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdcp_mux2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdmi_1p2mac ckgen01(0x1708)
#define reg_sw_en_p1_clk_tmds_hdmi_1p2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdmi_1p2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdmi_8p2mac ckgen01(0x170C)
#define reg_sw_en_p1_clk_tmds_hdmi_8p2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdmi_8p2mac_e 0
#define reg_sw_en_p1_clk_tmds_hdmi_mux2mac ckgen01(0x1710)
#define reg_sw_en_p1_clk_tmds_hdmi_mux2mac_s 0
#define reg_sw_en_p1_clk_tmds_hdmi_mux2mac_e 0
#define reg_sw_en_p2_clk_det_dec_misc_02mac ckgen01(0x1714)
#define reg_sw_en_p2_clk_det_dec_misc_02mac_s 0
#define reg_sw_en_p2_clk_det_dec_misc_02mac_e 0
#define reg_sw_en_p2_clk_det_dec_misc_12mac ckgen01(0x1718)
#define reg_sw_en_p2_clk_det_dec_misc_12mac_s 0
#define reg_sw_en_p2_clk_det_dec_misc_12mac_e 0
#define reg_sw_en_p2_clk_det_dep_misc_02mac ckgen01(0x171C)
#define reg_sw_en_p2_clk_det_dep_misc_02mac_s 0
#define reg_sw_en_p2_clk_det_dep_misc_02mac_e 0
#define reg_sw_en_p2_clk_det_dep_misc_12mac ckgen01(0x1720)
#define reg_sw_en_p2_clk_det_dep_misc_12mac_s 0
#define reg_sw_en_p2_clk_det_dep_misc_12mac_e 0
#define reg_sw_en_p2_clk_link2mac ckgen01(0x1724)
#define reg_sw_en_p2_clk_link2mac_s 0
#define reg_sw_en_p2_clk_link2mac_e 0
#define reg_sw_en_p2_clk_pix_1p2mac ckgen01(0x1728)
#define reg_sw_en_p2_clk_pix_1p2mac_s 0
#define reg_sw_en_p2_clk_pix_1p2mac_e 0
#define reg_sw_en_p2_clk_pix_8p2mac ckgen01(0x172C)
#define reg_sw_en_p2_clk_pix_8p2mac_s 0
#define reg_sw_en_p2_clk_pix_8p2mac_e 0
#define reg_sw_en_p2_clk_pix_dc_mux2mac ckgen01(0x1730)
#define reg_sw_en_p2_clk_pix_dc_mux2mac_s 0
#define reg_sw_en_p2_clk_pix_dc_mux2mac_e 0
#define reg_sw_en_p2_clk_pix_rcv_mux2mac ckgen01(0x1734)
#define reg_sw_en_p2_clk_pix_rcv_mux2mac_s 0
#define reg_sw_en_p2_clk_pix_rcv_mux2mac_e 0
#define reg_sw_en_p2_clk_pix_rep_1p2mac ckgen01(0x1738)
#define reg_sw_en_p2_clk_pix_rep_1p2mac_s 0
#define reg_sw_en_p2_clk_pix_rep_1p2mac_e 0
#define reg_sw_en_p2_clk_pix_tmdspll2mac ckgen01(0x173C)
#define reg_sw_en_p2_clk_pix_tmdspll2mac_s 0
#define reg_sw_en_p2_clk_pix_tmdspll2mac_e 0
#define reg_sw_en_p2_clk_pix_xc_mux2mac ckgen01(0x1740)
#define reg_sw_en_p2_clk_pix_xc_mux2mac_s 0
#define reg_sw_en_p2_clk_pix_xc_mux2mac_e 0
#define reg_sw_en_p2_clk_timing_det_dec2mac ckgen01(0x1744)
#define reg_sw_en_p2_clk_timing_det_dec2mac_s 0
#define reg_sw_en_p2_clk_timing_det_dec2mac_e 0
#define reg_sw_en_p2_clk_timing_det_dep2mac ckgen01(0x1748)
#define reg_sw_en_p2_clk_timing_det_dep2mac_s 0
#define reg_sw_en_p2_clk_timing_det_dep2mac_e 0
#define reg_sw_en_p2_clk_tmds_frl_8p2mac ckgen01(0x174C)
#define reg_sw_en_p2_clk_tmds_frl_8p2mac_s 0
#define reg_sw_en_p2_clk_tmds_frl_8p2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdcp_1p2mac ckgen01(0x1750)
#define reg_sw_en_p2_clk_tmds_hdcp_1p2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdcp_1p2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdcp_4p2mac ckgen01(0x1754)
#define reg_sw_en_p2_clk_tmds_hdcp_4p2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdcp_4p2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdcp_8p2mac ckgen01(0x1758)
#define reg_sw_en_p2_clk_tmds_hdcp_8p2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdcp_8p2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdcp_mux2mac ckgen01(0x175C)
#define reg_sw_en_p2_clk_tmds_hdcp_mux2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdcp_mux2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdmi_1p2mac ckgen01(0x1760)
#define reg_sw_en_p2_clk_tmds_hdmi_1p2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdmi_1p2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdmi_8p2mac ckgen01(0x1764)
#define reg_sw_en_p2_clk_tmds_hdmi_8p2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdmi_8p2mac_e 0
#define reg_sw_en_p2_clk_tmds_hdmi_mux2mac ckgen01(0x1768)
#define reg_sw_en_p2_clk_tmds_hdmi_mux2mac_s 0
#define reg_sw_en_p2_clk_tmds_hdmi_mux2mac_e 0
#define reg_sw_en_p3_clk_det_dec_misc_02mac ckgen01(0x176C)
#define reg_sw_en_p3_clk_det_dec_misc_02mac_s 0
#define reg_sw_en_p3_clk_det_dec_misc_02mac_e 0
#define reg_sw_en_p3_clk_det_dec_misc_12mac ckgen01(0x1770)
#define reg_sw_en_p3_clk_det_dec_misc_12mac_s 0
#define reg_sw_en_p3_clk_det_dec_misc_12mac_e 0
#define reg_sw_en_p3_clk_det_dep_misc_02mac ckgen01(0x1774)
#define reg_sw_en_p3_clk_det_dep_misc_02mac_s 0
#define reg_sw_en_p3_clk_det_dep_misc_02mac_e 0
#define reg_sw_en_p3_clk_det_dep_misc_12mac ckgen01(0x1778)
#define reg_sw_en_p3_clk_det_dep_misc_12mac_s 0
#define reg_sw_en_p3_clk_det_dep_misc_12mac_e 0
#define reg_sw_en_p3_clk_link2mac ckgen01(0x177C)
#define reg_sw_en_p3_clk_link2mac_s 0
#define reg_sw_en_p3_clk_link2mac_e 0
#define reg_sw_en_p3_clk_pix_1p2mac ckgen01(0x1780)
#define reg_sw_en_p3_clk_pix_1p2mac_s 0
#define reg_sw_en_p3_clk_pix_1p2mac_e 0
#define reg_sw_en_p3_clk_pix_8p2mac ckgen01(0x1784)
#define reg_sw_en_p3_clk_pix_8p2mac_s 0
#define reg_sw_en_p3_clk_pix_8p2mac_e 0
#define reg_sw_en_p3_clk_pix_dc_mux2mac ckgen01(0x1788)
#define reg_sw_en_p3_clk_pix_dc_mux2mac_s 0
#define reg_sw_en_p3_clk_pix_dc_mux2mac_e 0
#define reg_sw_en_p3_clk_pix_rcv_mux2mac ckgen01(0x178C)
#define reg_sw_en_p3_clk_pix_rcv_mux2mac_s 0
#define reg_sw_en_p3_clk_pix_rcv_mux2mac_e 0
#define reg_sw_en_p3_clk_pix_rep_1p2mac ckgen01(0x1790)
#define reg_sw_en_p3_clk_pix_rep_1p2mac_s 0
#define reg_sw_en_p3_clk_pix_rep_1p2mac_e 0
#define reg_sw_en_p3_clk_pix_tmdspll2mac ckgen01(0x1794)
#define reg_sw_en_p3_clk_pix_tmdspll2mac_s 0
#define reg_sw_en_p3_clk_pix_tmdspll2mac_e 0
#define reg_sw_en_p3_clk_pix_xc_mux2mac ckgen01(0x1798)
#define reg_sw_en_p3_clk_pix_xc_mux2mac_s 0
#define reg_sw_en_p3_clk_pix_xc_mux2mac_e 0
#define reg_sw_en_p3_clk_timing_det_dec2mac ckgen01(0x179C)
#define reg_sw_en_p3_clk_timing_det_dec2mac_s 0
#define reg_sw_en_p3_clk_timing_det_dec2mac_e 0
#define reg_sw_en_p3_clk_timing_det_dep2mac ckgen01(0x17A0)
#define reg_sw_en_p3_clk_timing_det_dep2mac_s 0
#define reg_sw_en_p3_clk_timing_det_dep2mac_e 0
#define reg_sw_en_p3_clk_tmds_frl_8p2mac ckgen01(0x17A4)
#define reg_sw_en_p3_clk_tmds_frl_8p2mac_s 0
#define reg_sw_en_p3_clk_tmds_frl_8p2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdcp_1p2mac ckgen01(0x17A8)
#define reg_sw_en_p3_clk_tmds_hdcp_1p2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdcp_1p2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdcp_4p2mac ckgen01(0x17AC)
#define reg_sw_en_p3_clk_tmds_hdcp_4p2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdcp_4p2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdcp_8p2mac ckgen01(0x17B0)
#define reg_sw_en_p3_clk_tmds_hdcp_8p2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdcp_8p2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdcp_mux2mac ckgen01(0x17B4)
#define reg_sw_en_p3_clk_tmds_hdcp_mux2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdcp_mux2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdmi_1p2mac ckgen01(0x17B8)
#define reg_sw_en_p3_clk_tmds_hdmi_1p2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdmi_1p2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdmi_8p2mac ckgen01(0x17BC)
#define reg_sw_en_p3_clk_tmds_hdmi_8p2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdmi_8p2mac_e 0
#define reg_sw_en_p3_clk_tmds_hdmi_mux2mac ckgen01(0x17C0)
#define reg_sw_en_p3_clk_tmds_hdmi_mux2mac_s 0
#define reg_sw_en_p3_clk_tmds_hdmi_mux2mac_e 0
#define reg_sw_en_xc_afbc2sctcon ckgen01(0x17C8)
#define reg_sw_en_xc_afbc2sctcon_s 0
#define reg_sw_en_xc_afbc2sctcon_e 0
#define reg_sw_en_xc_gop0_dst2sctcon ckgen01(0x17CC)
#define reg_sw_en_xc_gop0_dst2sctcon_s 0
#define reg_sw_en_xc_gop0_dst2sctcon_e 0
#define reg_sw_en_xc_gop_scl2sctcon ckgen01(0x17D0)
#define reg_sw_en_xc_gop_scl2sctcon_s 0
#define reg_sw_en_xc_gop_scl2sctcon_e 0
#define reg_sw_en_xc_gop2sctcon ckgen01(0x17D4)
#define reg_sw_en_xc_gop2sctcon_s 0
#define reg_sw_en_xc_gop2sctcon_e 0
#define reg_sw_en_xc_gopc_dst2sctcon ckgen01(0x17D8)
#define reg_sw_en_xc_gopc_dst2sctcon_s 0
#define reg_sw_en_xc_gopc_dst2sctcon_e 0
#define reg_sw_en_xc_gopg_dst2sctcon ckgen01(0x17DC)
#define reg_sw_en_xc_gopg_dst2sctcon_s 0
#define reg_sw_en_xc_gopg_dst2sctcon_e 0
#define reg_sw_en_xc_od_delta2sctcon ckgen01(0x17E0)
#define reg_sw_en_xc_od_delta2sctcon_s 0
#define reg_sw_en_xc_od_delta2sctcon_e 0
#define reg_sw_en_xc_od_delta2scip ckgen01(0x17E0)
#define reg_sw_en_xc_od_delta2scip_s 8
#define reg_sw_en_xc_od_delta2scip_e 8
#define reg_sw_en_xc_od_delta2scscl ckgen01(0x17E0)
#define reg_sw_en_xc_od_delta2scscl_s 1
#define reg_sw_en_xc_od_delta2scscl_e 1
#define reg_sw_en_xc_od_div22sctcon ckgen01(0x17E4)
#define reg_sw_en_xc_od_div22sctcon_s 0
#define reg_sw_en_xc_od_div22sctcon_e 0
#define reg_sw_en_xc_od_div42sctcon ckgen01(0x17E8)
#define reg_sw_en_xc_od_div42sctcon_s 0
#define reg_sw_en_xc_od_div42sctcon_e 0
#define reg_sw_en_lpll_syn_864_pipe2fpll ckgen01(0x17F0)
#define reg_sw_en_lpll_syn_864_pipe2fpll_s 0
#define reg_sw_en_lpll_syn_864_pipe2fpll_e 0
#define reg_sw_en_det_rclk2det ckgen01(0x17F4)
#define reg_sw_en_det_rclk2det_s 0
#define reg_sw_en_det_rclk2det_e 0
#define reg_sw_en_det_wclk2det ckgen01(0x17F8)
#define reg_sw_en_det_wclk2det_s 0
#define reg_sw_en_det_wclk2det_e 0
#define reg_sw_en_idclk2fpll ckgen01(0x17FC)
#define reg_sw_en_idclk2fpll_s 0
#define reg_sw_en_idclk2fpll_e 0
#define reg_sw_en_lpll_odclk_nodiv2fpll ckgen01(0x1800)
#define reg_sw_en_lpll_odclk_nodiv2fpll_s 0
#define reg_sw_en_lpll_odclk_nodiv2fpll_e 0
#define reg_sw_en_lpll_odclk_nodiv2ttl ckgen01(0x1800)
#define reg_sw_en_lpll_odclk_nodiv2ttl_s 1
#define reg_sw_en_lpll_odclk_nodiv2ttl_e 1
#define reg_sw_en_lpll_odclk2fpll ckgen01(0x1804)
#define reg_sw_en_lpll_odclk2fpll_s 0
#define reg_sw_en_lpll_odclk2fpll_e 0
#define reg_sw_en_lpll_syn_4322fpll ckgen01(0x1808)
#define reg_sw_en_lpll_syn_4322fpll_s 0
#define reg_sw_en_lpll_syn_4322fpll_e 0
#define reg_sw_en_lpll_syn_8642fpll ckgen01(0x180C)
#define reg_sw_en_lpll_syn_8642fpll_s 0
#define reg_sw_en_lpll_syn_8642fpll_e 0
#define reg_sw_en_mod_a_odclk2mod_a ckgen01(0x1810)
#define reg_sw_en_mod_a_odclk2mod_a_s 0
#define reg_sw_en_mod_a_odclk2mod_a_e 0
#define reg_sw_en_mod_d_odclk2mod_d ckgen01(0x1814)
#define reg_sw_en_mod_d_odclk2mod_d_s 0
#define reg_sw_en_mod_d_odclk2mod_d_e 0
#define reg_sw_en_mod_d_odclk2lvds ckgen01(0x1814)
#define reg_sw_en_mod_d_odclk2lvds_s 1
#define reg_sw_en_mod_d_odclk2lvds_e 1
#define reg_sw_en_mod_d_odclk2ttl ckgen01(0x1814)
#define reg_sw_en_mod_d_odclk2ttl_s 2
#define reg_sw_en_mod_d_odclk2ttl_e 2
#define reg_sw_en_mod_o_sr_wclk2o ckgen01(0x1818)
#define reg_sw_en_mod_o_sr_wclk2o_s 0
#define reg_sw_en_mod_o_sr_wclk2o_e 0
#define reg_sw_en_mod_o_sr_wclk2vby1_o ckgen01(0x1818)
#define reg_sw_en_mod_o_sr_wclk2vby1_o_s 1
#define reg_sw_en_mod_o_sr_wclk2vby1_o_e 1
#define reg_sw_en_mod_v1_sr_wclk2v1 ckgen01(0x181C)
#define reg_sw_en_mod_v1_sr_wclk2v1_s 0
#define reg_sw_en_mod_v1_sr_wclk2v1_e 0
#define reg_sw_en_mod_v1_sr_wclk2vby1_v1 ckgen01(0x181C)
#define reg_sw_en_mod_v1_sr_wclk2vby1_v1_s 1
#define reg_sw_en_mod_v1_sr_wclk2vby1_v1_e 1
#define reg_sw_en_mod_v2_sr_wclk2v2 ckgen01(0x1820)
#define reg_sw_en_mod_v2_sr_wclk2v2_s 0
#define reg_sw_en_mod_v2_sr_wclk2v2_e 0
#define reg_sw_en_mod_v2_sr_wclk2vby1_v2 ckgen01(0x1820)
#define reg_sw_en_mod_v2_sr_wclk2vby1_v2_s 1
#define reg_sw_en_mod_v2_sr_wclk2vby1_v2_e 1
#define reg_sw_en_o_mod_sr_rclk2o ckgen01(0x1824)
#define reg_sw_en_o_mod_sr_rclk2o_s 0
#define reg_sw_en_o_mod_sr_rclk2o_e 0
#define reg_sw_en_o_odclk_stg12o ckgen01(0x1828)
#define reg_sw_en_o_odclk_stg12o_s 0
#define reg_sw_en_o_odclk_stg12o_e 0
#define reg_sw_en_o_odclk_stg22o ckgen01(0x182C)
#define reg_sw_en_o_odclk_stg22o_s 0
#define reg_sw_en_o_odclk_stg22o_e 0
#define reg_sw_en_o_odclk_stg32o ckgen01(0x1830)
#define reg_sw_en_o_odclk_stg32o_s 0
#define reg_sw_en_o_odclk_stg32o_e 0
#define reg_sw_en_o_odclk_stg42o ckgen01(0x1834)
#define reg_sw_en_o_odclk_stg42o_s 0
#define reg_sw_en_o_odclk_stg42o_e 0
#define reg_sw_en_o_odclk_stg52o ckgen01(0x1838)
#define reg_sw_en_o_odclk_stg52o_s 0
#define reg_sw_en_o_odclk_stg52o_e 0
#define reg_sw_en_o_odclk_stg62o ckgen01(0x183C)
#define reg_sw_en_o_odclk_stg62o_s 0
#define reg_sw_en_o_odclk_stg62o_e 0
#define reg_sw_en_o_odclk2o ckgen01(0x1840)
#define reg_sw_en_o_odclk2o_s 0
#define reg_sw_en_o_odclk2o_e 0
#define reg_sw_en_pwm2pwm ckgen01(0x1844)
#define reg_sw_en_pwm2pwm_s 0
#define reg_sw_en_pwm2pwm_e 0
#define reg_sw_en_v1_mod_sr_rclk2v1 ckgen01(0x1848)
#define reg_sw_en_v1_mod_sr_rclk2v1_s 0
#define reg_sw_en_v1_mod_sr_rclk2v1_e 0
#define reg_sw_en_v1_odclk_stg12v1 ckgen01(0x184C)
#define reg_sw_en_v1_odclk_stg12v1_s 0
#define reg_sw_en_v1_odclk_stg12v1_e 0
#define reg_sw_en_v1_odclk_stg22v1 ckgen01(0x1850)
#define reg_sw_en_v1_odclk_stg22v1_s 0
#define reg_sw_en_v1_odclk_stg22v1_e 0
#define reg_sw_en_v1_odclk_stg32v1 ckgen01(0x1854)
#define reg_sw_en_v1_odclk_stg32v1_s 0
#define reg_sw_en_v1_odclk_stg32v1_e 0
#define reg_sw_en_v1_odclk_stg42v1 ckgen01(0x1858)
#define reg_sw_en_v1_odclk_stg42v1_s 0
#define reg_sw_en_v1_odclk_stg42v1_e 0
#define reg_sw_en_v1_odclk_stg52v1 ckgen01(0x185C)
#define reg_sw_en_v1_odclk_stg52v1_s 0
#define reg_sw_en_v1_odclk_stg52v1_e 0
#define reg_sw_en_v1_odclk_stg62v1 ckgen01(0x1860)
#define reg_sw_en_v1_odclk_stg62v1_s 0
#define reg_sw_en_v1_odclk_stg62v1_e 0
#define reg_sw_en_v1_odclk_stg72v1 ckgen01(0x1864)
#define reg_sw_en_v1_odclk_stg72v1_s 0
#define reg_sw_en_v1_odclk_stg72v1_e 0
#define reg_sw_en_v1_odclk_stg82v1 ckgen01(0x1868)
#define reg_sw_en_v1_odclk_stg82v1_s 0
#define reg_sw_en_v1_odclk_stg82v1_e 0
#define reg_sw_en_v1_odclk2v1 ckgen01(0x186C)
#define reg_sw_en_v1_odclk2v1_s 0
#define reg_sw_en_v1_odclk2v1_e 0
#define reg_sw_en_v2_mod_sr_rclk2v2 ckgen01(0x1870)
#define reg_sw_en_v2_mod_sr_rclk2v2_s 0
#define reg_sw_en_v2_mod_sr_rclk2v2_e 0
#define reg_sw_en_v2_odclk_stg12v2 ckgen01(0x1874)
#define reg_sw_en_v2_odclk_stg12v2_s 0
#define reg_sw_en_v2_odclk_stg12v2_e 0
#define reg_sw_en_v2_odclk_stg22v2 ckgen01(0x1878)
#define reg_sw_en_v2_odclk_stg22v2_s 0
#define reg_sw_en_v2_odclk_stg22v2_e 0
#define reg_sw_en_v2_odclk_stg32v2 ckgen01(0x187C)
#define reg_sw_en_v2_odclk_stg32v2_s 0
#define reg_sw_en_v2_odclk_stg32v2_e 0
#define reg_sw_en_v2_odclk_stg42v2 ckgen01(0x1880)
#define reg_sw_en_v2_odclk_stg42v2_s 0
#define reg_sw_en_v2_odclk_stg42v2_e 0
#define reg_sw_en_v2_odclk_stg52v2 ckgen01(0x1884)
#define reg_sw_en_v2_odclk_stg52v2_s 0
#define reg_sw_en_v2_odclk_stg52v2_e 0
#define reg_sw_en_v2_odclk_stg62v2 ckgen01(0x1888)
#define reg_sw_en_v2_odclk_stg62v2_s 0
#define reg_sw_en_v2_odclk_stg62v2_e 0
#define reg_sw_en_v2_odclk_stg72v2 ckgen01(0x188C)
#define reg_sw_en_v2_odclk_stg72v2_s 0
#define reg_sw_en_v2_odclk_stg72v2_e 0
#define reg_sw_en_v2_odclk2v2 ckgen01(0x1890)
#define reg_sw_en_v2_odclk2v2_s 0
#define reg_sw_en_v2_odclk2v2_e 0
#define reg_sw_en_xtal_12m2mod_a ckgen01(0x1894)
#define reg_sw_en_xtal_12m2mod_a_s 0
#define reg_sw_en_xtal_12m2mod_a_e 0
#define reg_sw_en_xtal_12m2pwm ckgen01(0x1894)
#define reg_sw_en_xtal_12m2pwm_s 1
#define reg_sw_en_xtal_12m2pwm_e 1
#define reg_sw_en_xtal_24m2fpll ckgen01(0x1898)
#define reg_sw_en_xtal_24m2fpll_s 0
#define reg_sw_en_xtal_24m2fpll_e 0
#define reg_sw_en_o_mod_sr_rclk_finial2o ckgen01(0x189C)
#define reg_sw_en_o_mod_sr_rclk_finial2o_s 0
#define reg_sw_en_o_mod_sr_rclk_finial2o_e 0
#define reg_sw_en_o_mod_sr_rclk_pre02o ckgen01(0x18A0)
#define reg_sw_en_o_mod_sr_rclk_pre02o_s 0
#define reg_sw_en_o_mod_sr_rclk_pre02o_e 0
#define reg_sw_en_o_mod_sr_rclk_pre12o ckgen01(0x18A4)
#define reg_sw_en_o_mod_sr_rclk_pre12o_s 0
#define reg_sw_en_o_mod_sr_rclk_pre12o_e 0
#define reg_sw_en_v1_mod_sr_rclk_finial2v1 ckgen01(0x18A8)
#define reg_sw_en_v1_mod_sr_rclk_finial2v1_s 0
#define reg_sw_en_v1_mod_sr_rclk_finial2v1_e 0
#define reg_sw_en_v1_mod_sr_rclk_pre02v1 ckgen01(0x18AC)
#define reg_sw_en_v1_mod_sr_rclk_pre02v1_s 0
#define reg_sw_en_v1_mod_sr_rclk_pre02v1_e 0
#define reg_sw_en_v1_mod_sr_rclk_pre12v1 ckgen01(0x18B0)
#define reg_sw_en_v1_mod_sr_rclk_pre12v1_s 0
#define reg_sw_en_v1_mod_sr_rclk_pre12v1_e 0
#define reg_sw_en_v2_mod_sr_rclk_finial2v2 ckgen01(0x18B4)
#define reg_sw_en_v2_mod_sr_rclk_finial2v2_s 0
#define reg_sw_en_v2_mod_sr_rclk_finial2v2_e 0
#define reg_sw_en_v2_mod_sr_rclk_pre02v2 ckgen01(0x18B8)
#define reg_sw_en_v2_mod_sr_rclk_pre02v2_s 0
#define reg_sw_en_v2_mod_sr_rclk_pre02v2_e 0
#define reg_sw_en_v2_mod_sr_rclk_pre12v2 ckgen01(0x18BC)
#define reg_sw_en_v2_mod_sr_rclk_pre12v2_s 0
#define reg_sw_en_v2_mod_sr_rclk_pre12v2_e 0
#define reg_sw_en_v1_odclk_stg92v1 ckgen01(0x18C0)
#define reg_sw_en_v1_odclk_stg92v1_s 0
#define reg_sw_en_v1_odclk_stg92v1_e 0
#define reg_sw_en_aisr_hvsp_sram2scsr ckgen01(0x18C8)
#define reg_sw_en_aisr_hvsp_sram2scsr_s 0
#define reg_sw_en_aisr_hvsp_sram2scsr_e 0
#define reg_sw_en_xc_fs2sctcon ckgen01(0x18CC)
#define reg_sw_en_xc_fs2sctcon_s 0
#define reg_sw_en_xc_fs2sctcon_e 0
#define reg_sw_en_xc_od_osd2sctcon ckgen01(0x18D0)
#define reg_sw_en_xc_od_osd2sctcon_s 0
#define reg_sw_en_xc_od_osd2sctcon_e 0
#define reg_sw_en_aisr_sram2scsr ckgen01(0x18D4)
#define reg_sw_en_aisr_sram2scsr_s 0
#define reg_sw_en_aisr_sram2scsr_e 0
#define reg_sw_en_aisr_sram_ph_12scsr ckgen01(0x18D4)
#define reg_sw_en_aisr_sram_ph_12scsr_s 1
#define reg_sw_en_aisr_sram_ph_12scsr_e 1
#define reg_sw_en_dc0_sram2scip ckgen01(0x18D8)
#define reg_sw_en_dc0_sram2scip_s 0
#define reg_sw_en_dc0_sram2scip_e 0
#define reg_sw_en_dbk_hw_sram2scpq ckgen01(0x18DC)
#define reg_sw_en_dbk_hw_sram2scpq_s 0
#define reg_sw_en_dbk_hw_sram2scpq_e 0
#define reg_sw_en_delta_b2p_sram2scscl ckgen01(0x18E0)
#define reg_sw_en_delta_b2p_sram2scscl_s 0
#define reg_sw_en_delta_b2p_sram2scscl_e 0
#define reg_sw_en_delta_b2p2_sram2scace ckgen01(0x18E4)
#define reg_sw_en_delta_b2p2_sram2scace_s 0
#define reg_sw_en_delta_b2p2_sram2scace_e 0
#define reg_sw_en_demura_sram2sctcon ckgen01(0x18E8)
#define reg_sw_en_demura_sram2sctcon_s 0
#define reg_sw_en_demura_sram2sctcon_e 0
#define reg_sw_en_dv_hw5_sram2scdv ckgen01(0x18EC)
#define reg_sw_en_dv_hw5_sram2scdv_s 0
#define reg_sw_en_dv_hw5_sram2scdv_e 0
#define reg_sw_en_gop0_sram2sctcon ckgen01(0x18F0)
#define reg_sw_en_gop0_sram2sctcon_s 0
#define reg_sw_en_gop0_sram2sctcon_e 0
#define reg_sw_en_gop1_sram2sctcon ckgen01(0x18F4)
#define reg_sw_en_gop1_sram2sctcon_s 0
#define reg_sw_en_gop1_sram2sctcon_e 0
#define reg_sw_en_gop2_sram2sctcon ckgen01(0x18F8)
#define reg_sw_en_gop2_sram2sctcon_s 0
#define reg_sw_en_gop2_sram2sctcon_e 0
#define reg_sw_en_gop3_sram2sctcon ckgen01(0x18FC)
#define reg_sw_en_gop3_sram2sctcon_s 0
#define reg_sw_en_gop3_sram2sctcon_e 0
#define reg_sw_en_gucd_18_lut2_sram2scace ckgen01(0x1900)
#define reg_sw_en_gucd_18_lut2_sram2scace_s 0
#define reg_sw_en_gucd_18_lut2_sram2scace_e 0
#define reg_sw_en_gucd_18_sram2scscl ckgen01(0x1904)
#define reg_sw_en_gucd_18_sram2scscl_s 0
#define reg_sw_en_gucd_18_sram2scscl_e 0
#define reg_sw_en_gucd_256_lut2_sram2scace ckgen01(0x1908)
#define reg_sw_en_gucd_256_lut2_sram2scace_s 0
#define reg_sw_en_gucd_256_lut2_sram2scace_e 0
#define reg_sw_en_gucd_256_sram2scscl ckgen01(0x190C)
#define reg_sw_en_gucd_256_sram2scscl_s 0
#define reg_sw_en_gucd_256_sram2scscl_e 0
#define reg_sw_en_hsy_8p_sram2scmw ckgen01(0x1910)
#define reg_sw_en_hsy_8p_sram2scmw_s 0
#define reg_sw_en_hsy_8p_sram2scmw_e 0
#define reg_sw_en_hsy_8p_sram2scace ckgen01(0x1910)
#define reg_sw_en_hsy_8p_sram2scace_s 1
#define reg_sw_en_hsy_8p_sram2scace_e 1
#define reg_sw_en_hsy_8p3_sram2scmw ckgen01(0x1914)
#define reg_sw_en_hsy_8p3_sram2scmw_s 0
#define reg_sw_en_hsy_8p3_sram2scmw_e 0
#define reg_sw_en_hsy_8p3_sram2scace ckgen01(0x1914)
#define reg_sw_en_hsy_8p3_sram2scace_s 1
#define reg_sw_en_hsy_8p3_sram2scace_e 1
#define reg_sw_en_hsy_sp_sram2scscl ckgen01(0x1918)
#define reg_sw_en_hsy_sp_sram2scscl_s 0
#define reg_sw_en_hsy_sp_sram2scscl_e 0
#define reg_sw_en_hsy_sp3_sram2scscl ckgen01(0x191C)
#define reg_sw_en_hsy_sp3_sram2scscl_s 0
#define reg_sw_en_hsy_sp3_sram2scscl_e 0
#define reg_sw_en_hvsp_stp1_sram2scscl ckgen01(0x1920)
#define reg_sw_en_hvsp_stp1_sram2scscl_s 0
#define reg_sw_en_hvsp_stp1_sram2scscl_e 0
#define reg_sw_en_hvsp_stp2_sram2scscl ckgen01(0x1924)
#define reg_sw_en_hvsp_stp2_sram2scscl_s 0
#define reg_sw_en_hvsp_stp2_sram2scscl_e 0
#define reg_sw_en_lce_ace_sram2scace ckgen01(0x1928)
#define reg_sw_en_lce_ace_sram2scace_s 0
#define reg_sw_en_lce_ace_sram2scace_e 0
#define reg_sw_en_lce_scl_sram2scscl ckgen01(0x192C)
#define reg_sw_en_lce_scl_sram2scscl_s 0
#define reg_sw_en_lce_scl_sram2scscl_e 0
#define reg_sw_en_ld_edge2d_sram2sctcon ckgen01(0x1930)
#define reg_sw_en_ld_edge2d_sram2sctcon_s 0
#define reg_sw_en_ld_edge2d_sram2sctcon_e 0
#define reg_sw_en_ldcomp_sram2sctcon ckgen01(0x1934)
#define reg_sw_en_ldcomp_sram2sctcon_s 0
#define reg_sw_en_ldcomp_sram2sctcon_e 0
#define reg_sw_en_ldm_ga_sram2sctcon ckgen01(0x1938)
#define reg_sw_en_ldm_ga_sram2sctcon_s 0
#define reg_sw_en_ldm_ga_sram2sctcon_e 0
#define reg_sw_en_ldmcg_sram2sctcon ckgen01(0x193C)
#define reg_sw_en_ldmcg_sram2sctcon_s 0
#define reg_sw_en_ldmcg_sram2sctcon_e 0
#define reg_sw_en_lpq_pa_sram2sctcon ckgen01(0x1940)
#define reg_sw_en_lpq_pa_sram2sctcon_s 0
#define reg_sw_en_lpq_pa_sram2sctcon_e 0
#define reg_sw_en_osd_dv_hw5_sram2sctcon ckgen01(0x1944)
#define reg_sw_en_osd_dv_hw5_sram2sctcon_s 0
#define reg_sw_en_osd_dv_hw5_sram2sctcon_e 0
#define reg_sw_en_padj_sram2sctcon ckgen01(0x1948)
#define reg_sw_en_padj_sram2sctcon_s 0
#define reg_sw_en_padj_sram2sctcon_e 0
#define reg_sw_en_panel_ga_sram2sctcon ckgen01(0x194C)
#define reg_sw_en_panel_ga_sram2sctcon_s 0
#define reg_sw_en_panel_ga_sram2sctcon_e 0
#define reg_sw_en_pq_gamma_sram2scmw ckgen01(0x1950)
#define reg_sw_en_pq_gamma_sram2scmw_s 0
#define reg_sw_en_pq_gamma_sram2scmw_e 0
#define reg_sw_en_rgb_3dlut_sram2scmw ckgen01(0x1954)
#define reg_sw_en_rgb_3dlut_sram2scmw_s 0
#define reg_sw_en_rgb_3dlut_sram2scmw_e 0
#define reg_sw_en_scnr_hdr_sram2scpq ckgen01(0x1958)
#define reg_sw_en_scnr_hdr_sram2scpq_s 0
#define reg_sw_en_scnr_hdr_sram2scpq_e 0
#define reg_sw_en_spf_hdbk_sram2scpq ckgen01(0x195C)
#define reg_sw_en_spf_hdbk_sram2scpq_s 0
#define reg_sw_en_spf_hdbk_sram2scpq_e 0
#define reg_sw_en_ucd_st_sram2scip ckgen01(0x1960)
#define reg_sw_en_ucd_st_sram2scip_s 0
#define reg_sw_en_ucd_st_sram2scip_e 0
#define reg_sw_en_vdbk_sram2scpq ckgen01(0x1964)
#define reg_sw_en_vdbk_sram2scpq_s 0
#define reg_sw_en_vdbk_sram2scpq_e 0
#define reg_sw_en_vip_ace_sram2scace ckgen01(0x1968)
#define reg_sw_en_vip_ace_sram2scace_s 0
#define reg_sw_en_vip_ace_sram2scace_e 0
#define reg_sw_en_vip_pq_sram2scscl ckgen01(0x196C)
#define reg_sw_en_vip_pq_sram2scscl_s 0
#define reg_sw_en_vip_pq_sram2scscl_e 0
#define reg_sw_en_xc_adc2scip ckgen01(0x1970)
#define reg_sw_en_xc_adc2scip_s 0
#define reg_sw_en_xc_adc2scip_e 0
#define reg_sw_en_xc_aisr2scsr ckgen01(0x1974)
#define reg_sw_en_xc_aisr2scsr_s 0
#define reg_sw_en_xc_aisr2scsr_e 0
#define reg_sw_en_xc_sub_dc02scip ckgen01(0x1978)
#define reg_sw_en_xc_sub_dc02scip_s 0
#define reg_sw_en_xc_sub_dc02scip_e 0
#define reg_sw_en_xc_dc02scip ckgen01(0x197C)
#define reg_sw_en_xc_dc02scip_s 0
#define reg_sw_en_xc_dc02scip_e 0
#define reg_sw_en_xc_dbg2miu2scip ckgen01(0x1980)
#define reg_sw_en_xc_dbg2miu2scip_s 0
#define reg_sw_en_xc_dbg2miu2scip_e 0
#define reg_sw_en_xc_disp_mfdec2scip ckgen01(0x1984)
#define reg_sw_en_xc_disp_mfdec2scip_s 0
#define reg_sw_en_xc_disp_mfdec2scip_e 0
#define reg_sw_en_xc_ed02scip ckgen01(0x1988)
#define reg_sw_en_xc_ed02scip_s 0
#define reg_sw_en_xc_ed02scip_e 0
#define reg_sw_en_xc_ed12scip ckgen01(0x198C)
#define reg_sw_en_xc_ed12scip_s 0
#define reg_sw_en_xc_ed12scip_e 0
#define reg_sw_en_xc_fd2scmw ckgen01(0x1990)
#define reg_sw_en_xc_fd2scmw_s 0
#define reg_sw_en_xc_fd2scmw_e 0
#define reg_sw_en_xc_fd2sctcon ckgen01(0x1990)
#define reg_sw_en_xc_fd2sctcon_s 1
#define reg_sw_en_xc_fd2sctcon_e 1
#define reg_sw_en_xc_fd2scip ckgen01(0x1990)
#define reg_sw_en_xc_fd2scip_s 2
#define reg_sw_en_xc_fd2scip_e 2
#define reg_sw_en_xc_fd2scscl ckgen01(0x1990)
#define reg_sw_en_xc_fd2scscl_s 3
#define reg_sw_en_xc_fd2scscl_e 3
#define reg_sw_en_xc_fd_abf2sctcon ckgen01(0x1990)
#define reg_sw_en_xc_fd_abf2sctcon_s 4
#define reg_sw_en_xc_fd_abf2sctcon_e 4
#define reg_sw_en_xc_fd_gop02sctcon ckgen01(0x1990)
#define reg_sw_en_xc_fd_gop02sctcon_s 5
#define reg_sw_en_xc_fd_gop02sctcon_e 5
#define reg_sw_en_xc_fd_dv2sctcon ckgen01(0x1990)
#define reg_sw_en_xc_fd_dv2sctcon_s 6
#define reg_sw_en_xc_fd_dv2sctcon_e 6
#define reg_sw_en_xc_fn2scdv ckgen01(0x1994)
#define reg_sw_en_xc_fn2scdv_s 0
#define reg_sw_en_xc_fn2scdv_e 0
#define reg_sw_en_xc_fn2scip ckgen01(0x1994)
#define reg_sw_en_xc_fn2scip_s 1
#define reg_sw_en_xc_fn2scip_e 1
#define reg_sw_en_xc_fn2scm ckgen01(0x1994)
#define reg_sw_en_xc_fn2scm_s 2
#define reg_sw_en_xc_fn2scm_e 2
#define reg_sw_en_xc_fn2scmo ckgen01(0x1994)
#define reg_sw_en_xc_fn2scmo_s 3
#define reg_sw_en_xc_fn2scmo_e 3
#define reg_sw_en_xc_fn2scmw ckgen01(0x1994)
#define reg_sw_en_xc_fn2scmw_s 4
#define reg_sw_en_xc_fn2scmw_e 4
#define reg_sw_en_xc_fn2scnr ckgen01(0x1994)
#define reg_sw_en_xc_fn2scnr_s 5
#define reg_sw_en_xc_fn2scnr_e 5
#define reg_sw_en_xc_fn2scpq_dolby ckgen01(0x1994)
#define reg_sw_en_xc_fn2scpq_dolby_s 6
#define reg_sw_en_xc_fn2scpq_dolby_e 6
#define reg_sw_en_xc_fn2scpq_spf ckgen01(0x1994)
#define reg_sw_en_xc_fn2scpq_spf_s 7
#define reg_sw_en_xc_fn2scpq_spf_e 7
#define reg_sw_en_xc_fn2scscl ckgen01(0x1994)
#define reg_sw_en_xc_fn2scscl_s 8
#define reg_sw_en_xc_fn2scscl_e 8
#define reg_sw_en_xc_fn2scsr ckgen01(0x1994)
#define reg_sw_en_xc_fn2scsr_s 9
#define reg_sw_en_xc_fn2scsr_e 9
#define reg_sw_en_xc_fn2sctcon ckgen01(0x1994)
#define reg_sw_en_xc_fn2sctcon_s 10
#define reg_sw_en_xc_fn2sctcon_e 10
#define reg_sw_en_xc_fn_22scdv ckgen01(0x1994)
#define reg_sw_en_xc_fn_22scdv_s 11
#define reg_sw_en_xc_fn_22scdv_e 11
#define reg_sw_en_xc_fs2scace_hsy ckgen01(0x1998)
#define reg_sw_en_xc_fs2scace_hsy_s 0
#define reg_sw_en_xc_fs2scace_hsy_e 0
#define reg_sw_en_xc_fs2scace_vip ckgen01(0x1998)
#define reg_sw_en_xc_fs2scace_vip_s 1
#define reg_sw_en_xc_fs2scace_vip_e 1
#define reg_sw_en_xc_fs2scace_vop2 ckgen01(0x1998)
#define reg_sw_en_xc_fs2scace_vop2_s 2
#define reg_sw_en_xc_fs2scace_vop2_e 2
#define reg_sw_en_xc_fs2scmw ckgen01(0x1998)
#define reg_sw_en_xc_fs2scmw_s 3
#define reg_sw_en_xc_fs2scmw_e 3
#define reg_sw_en_xc_fs2scscl ckgen01(0x1998)
#define reg_sw_en_xc_fs2scscl_s 4
#define reg_sw_en_xc_fs2scscl_e 4
#define reg_sw_en_xc_fs2scsr ckgen01(0x1998)
#define reg_sw_en_xc_fs2scsr_s 5
#define reg_sw_en_xc_fs2scsr_e 5
#define reg_sw_en_xc_fs2scip ckgen01(0x1998)
#define reg_sw_en_xc_fs2scip_s 6
#define reg_sw_en_xc_fs2scip_e 6
#define reg_sw_en_xc_hd2miu_m2scip ckgen01(0x199C)
#define reg_sw_en_xc_hd2miu_m2scip_s 0
#define reg_sw_en_xc_hd2miu_m2scip_e 0
#define reg_sw_en_xc_hd2miu_s2scip ckgen01(0x19A0)
#define reg_sw_en_xc_hd2miu_s2scip_s 0
#define reg_sw_en_xc_hd2miu_s2scip_e 0
#define reg_sw_en_xc_hdmi02scip ckgen01(0x19A4)
#define reg_sw_en_xc_hdmi02scip_s 0
#define reg_sw_en_xc_hdmi02scip_e 0
#define reg_sw_en_xc_hdmi12scip ckgen01(0x19A8)
#define reg_sw_en_xc_hdmi12scip_s 0
#define reg_sw_en_xc_hdmi12scip_e 0
#define reg_sw_en_xc_hdmi22scip ckgen01(0x19AC)
#define reg_sw_en_xc_hdmi22scip_s 0
#define reg_sw_en_xc_hdmi22scip_e 0
#define reg_sw_en_xc_hdmi32scip ckgen01(0x19B0)
#define reg_sw_en_xc_hdmi32scip_s 0
#define reg_sw_en_xc_hdmi32scip_e 0
#define reg_sw_en_xc_id02scip ckgen01(0x19B4)
#define reg_sw_en_xc_id02scip_s 0
#define reg_sw_en_xc_id02scip_e 0
#define reg_sw_en_xc_id12scip ckgen01(0x19B8)
#define reg_sw_en_xc_id12scip_s 0
#define reg_sw_en_xc_id12scip_e 0
#define reg_sw_en_xc_ip2_src2scip ckgen01(0x19BC)
#define reg_sw_en_xc_ip2_src2scip_s 0
#define reg_sw_en_xc_ip2_src2scip_e 0
#define reg_sw_en_xc_mfdec2scip ckgen01(0x19C0)
#define reg_sw_en_xc_mfdec2scip_s 0
#define reg_sw_en_xc_mfdec2scip_e 0
#define reg_sw_en_xc_od2scmw ckgen01(0x19C4)
#define reg_sw_en_xc_od2scmw_s 0
#define reg_sw_en_xc_od2scmw_e 0
#define reg_sw_en_xc_od2sctcon ckgen01(0x19C4)
#define reg_sw_en_xc_od2sctcon_s 1
#define reg_sw_en_xc_od2sctcon_e 1
#define reg_sw_en_xc_od2scip ckgen01(0x19C4)
#define reg_sw_en_xc_od2scip_s 2
#define reg_sw_en_xc_od2scip_e 2
#define reg_sw_en_xc_od2scscl ckgen01(0x19C4)
#define reg_sw_en_xc_od2scscl_s 3
#define reg_sw_en_xc_od2scscl_e 3
#define reg_sw_en_xc_od_edge2sctcon ckgen01(0x19C4)
#define reg_sw_en_xc_od_edge2sctcon_s 4
#define reg_sw_en_xc_od_edge2sctcon_e 4
#define reg_sw_en_xc_slow2scip ckgen01(0x19C8)
#define reg_sw_en_xc_slow2scip_s 0
#define reg_sw_en_xc_slow2scip_e 0
#define reg_sw_en_xc_sr_alai2scsr ckgen01(0x19CC)
#define reg_sw_en_xc_sr_alai2scsr_s 0
#define reg_sw_en_xc_sr_alai2scsr_e 0
#define reg_sw_en_xc_sr_sram_share2scsr ckgen01(0x19D0)
#define reg_sw_en_xc_sr_sram_share2scsr_s 0
#define reg_sw_en_xc_sr_sram_share2scsr_e 0
#define reg_sw_en_xc_srs2scsr ckgen01(0x19D4)
#define reg_sw_en_xc_srs2scsr_s 0
#define reg_sw_en_xc_srs2scsr_e 0
#define reg_sw_en_xc_tgen_win2scip ckgen01(0x19D8)
#define reg_sw_en_xc_tgen_win2scip_s 0
#define reg_sw_en_xc_tgen_win2scip_e 0
#define reg_sw_en_xc_ucd_stat2scip ckgen01(0x19DC)
#define reg_sw_en_xc_ucd_stat2scip_s 0
#define reg_sw_en_xc_ucd_stat2scip_e 0
#define reg_sw_en_xc_vd2scip ckgen01(0x19E0)
#define reg_sw_en_xc_vd2scip_s 0
#define reg_sw_en_xc_vd2scip_e 0
#define reg_sw_en_xc_ve2scip ckgen01(0x19E4)
#define reg_sw_en_xc_ve2scip_s 0
#define reg_sw_en_xc_ve2scip_e 0
#define reg_sw_en_xcpll_syn2xcpll_dmacro ckgen01(0x19E8)
#define reg_sw_en_xcpll_syn2xcpll_dmacro_s 0
#define reg_sw_en_xcpll_syn2xcpll_dmacro_e 0
#define reg_sw_en_xtal_12m2scace ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2scace_s 0
#define reg_sw_en_xtal_12m2scace_e 0
#define reg_sw_en_xtal_12m2scdv ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2scdv_s 1
#define reg_sw_en_xtal_12m2scdv_e 1
#define reg_sw_en_xtal_12m2scnr ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2scnr_s 2
#define reg_sw_en_xtal_12m2scnr_e 2
#define reg_sw_en_xtal_12m2scscl ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2scscl_s 3
#define reg_sw_en_xtal_12m2scscl_e 3
#define reg_sw_en_xtal_12m2scsr ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2scsr_s 4
#define reg_sw_en_xtal_12m2scsr_e 4
#define reg_sw_en_xtal_12m2sctcon ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2sctcon_s 5
#define reg_sw_en_xtal_12m2sctcon_e 5
#define reg_sw_en_xtal_12m2scip ckgen01(0x19EC)
#define reg_sw_en_xtal_12m2scip_s 6
#define reg_sw_en_xtal_12m2scip_e 6
#define reg_sw_en_xtal_24m2scace ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scace_s 0
#define reg_sw_en_xtal_24m2scace_e 0
#define reg_sw_en_xtal_24m2scdv ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scdv_s 1
#define reg_sw_en_xtal_24m2scdv_e 1
#define reg_sw_en_xtal_24m2scip ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scip_s 2
#define reg_sw_en_xtal_24m2scip_e 2
#define reg_sw_en_xtal_24m2scmw ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scmw_s 3
#define reg_sw_en_xtal_24m2scmw_e 3
#define reg_sw_en_xtal_24m2scnr ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scnr_s 4
#define reg_sw_en_xtal_24m2scnr_e 4
#define reg_sw_en_xtal_24m2scpq ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scpq_s 5
#define reg_sw_en_xtal_24m2scpq_e 5
#define reg_sw_en_xtal_24m2scscl ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scscl_s 6
#define reg_sw_en_xtal_24m2scscl_e 6
#define reg_sw_en_xtal_24m2scsr ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2scsr_s 7
#define reg_sw_en_xtal_24m2scsr_e 7
#define reg_sw_en_xtal_24m2sctcon ckgen01(0x19F0)
#define reg_sw_en_xtal_24m2sctcon_s 8
#define reg_sw_en_xtal_24m2sctcon_e 8
#define reg_sw_en_xtal_ip12scip ckgen01(0x19F4)
#define reg_sw_en_xtal_ip12scip_s 0
#define reg_sw_en_xtal_ip12scip_e 0
#define reg_sw_en_xc_sub1_dc02scip ckgen01(0x19F8)
#define reg_sw_en_xc_sub1_dc02scip_s 0
#define reg_sw_en_xc_sub1_dc02scip_e 0
#define reg_sw_en_xvycc_sram2scmw ckgen01(0x19FC)
#define reg_sw_en_xvycc_sram2scmw_s 0
#define reg_sw_en_xvycc_sram2scmw_e 0
#define reg_sw_en_sidclk_hd02scip ckgen01(0x1A00)
#define reg_sw_en_sidclk_hd02scip_s 0
#define reg_sw_en_sidclk_hd02scip_e 0
#define reg_sw_en_sidclk_hd12scip ckgen01(0x1A04)
#define reg_sw_en_sidclk_hd12scip_s 0
#define reg_sw_en_sidclk_hd12scip_e 0
#define reg_sw_en_sidclk_hd22scip ckgen01(0x1A08)
#define reg_sw_en_sidclk_hd22scip_s 0
#define reg_sw_en_sidclk_hd22scip_e 0
#define reg_sw_en_sidclk_hd32scip ckgen01(0x1A0C)
#define reg_sw_en_sidclk_hd32scip_s 0
#define reg_sw_en_sidclk_hd32scip_e 0
#define reg_sw_en_xc_dip02scip ckgen01(0x1A10)
#define reg_sw_en_xc_dip02scip_s 0
#define reg_sw_en_xc_dip02scip_e 0
#define reg_sw_en_xc_dip12scip ckgen01(0x1A14)
#define reg_sw_en_xc_dip12scip_s 0
#define reg_sw_en_xc_dip12scip_e 0
#define reg_sw_en_xc_dip22scip ckgen01(0x1A18)
#define reg_sw_en_xc_dip22scip_s 0
#define reg_sw_en_xc_dip22scip_e 0
#define reg_sw_en_xc_vedac2scip ckgen01(0x1A1C)
#define reg_sw_en_xc_vedac2scip_s 0
#define reg_sw_en_xc_vedac2scip_e 0
#define reg_sw_en_xc_vein2scip ckgen01(0x1A20)
#define reg_sw_en_xc_vein2scip_s 0
#define reg_sw_en_xc_vein2scip_e 0
#define reg_sw_en_dip1_hvsp_sram2scmw ckgen01(0x1A24)
#define reg_sw_en_dip1_hvsp_sram2scmw_s 0
#define reg_sw_en_dip1_hvsp_sram2scmw_e 0
#define reg_sw_en_dip1_xvycc_sram2scmw ckgen01(0x1A28)
#define reg_sw_en_dip1_xvycc_sram2scmw_s 0
#define reg_sw_en_dip1_xvycc_sram2scmw_e 0
#define reg_sw_en_cmbai2vd ckgen01(0x1A2C)
#define reg_sw_en_cmbai2vd_s 0
#define reg_sw_en_cmbai2vd_e 0
#define reg_sw_en_cmbao2vd ckgen01(0x1A30)
#define reg_sw_en_cmbao2vd_s 0
#define reg_sw_en_cmbao2vd_e 0
#define reg_sw_en_cmbbi2vd ckgen01(0x1A34)
#define reg_sw_en_cmbbi2vd_s 0
#define reg_sw_en_cmbbi2vd_e 0
#define reg_sw_en_cmbbo2vd ckgen01(0x1A38)
#define reg_sw_en_cmbbo2vd_s 0
#define reg_sw_en_cmbbo2vd_e 0
#define reg_sw_en_mcu_mail02vd ckgen01(0x1A3C)
#define reg_sw_en_mcu_mail02vd_s 0
#define reg_sw_en_mcu_mail02vd_e 0
#define reg_sw_en_mcu_mail12vd ckgen01(0x1A40)
#define reg_sw_en_mcu_mail12vd_s 0
#define reg_sw_en_mcu_mail12vd_e 0
#define reg_sw_en_vd_32fsc2vd ckgen01(0x1A44)
#define reg_sw_en_vd_32fsc2vd_s 0
#define reg_sw_en_vd_32fsc2vd_e 0
#define reg_sw_en_vd2mheg5_adc ckgen01(0x1A48)
#define reg_sw_en_vd2mheg5_adc_s 0
#define reg_sw_en_vd2mheg5_adc_e 0
#define reg_sw_en_vd2vd ckgen01(0x1A48)
#define reg_sw_en_vd2vd_s 1
#define reg_sw_en_vd2vd_e 1
#define reg_sw_en_vd2x2mheg5_adc ckgen01(0x1A4C)
#define reg_sw_en_vd2x2mheg5_adc_s 0
#define reg_sw_en_vd2x2mheg5_adc_e 0
#define reg_sw_en_vd2x2vd ckgen01(0x1A4C)
#define reg_sw_en_vd2x2vd_s 1
#define reg_sw_en_vd2x2vd_e 1
#define reg_sw_en_xc_od_meta2sctcon ckgen01(0x1A50)
#define reg_sw_en_xc_od_meta2sctcon_s 0
#define reg_sw_en_xc_od_meta2sctcon_e 0
#define reg_sw_en_xc_od_delta_meta2sctcon ckgen01(0x1A54)
#define reg_sw_en_xc_od_delta_meta2sctcon_s 0
#define reg_sw_en_xc_od_delta_meta2sctcon_e 0
#define reg_sw_en_venc2venc ckgen01(0x1A58)
#define reg_sw_en_venc2venc_s 0
#define reg_sw_en_venc2venc_e 0
#define reg_sw_en_xc_od_osd_meta2sctcon ckgen01(0x1A5C)
#define reg_sw_en_xc_od_osd_meta2sctcon_s 0
#define reg_sw_en_xc_od_osd_meta2sctcon_e 0
#define reg_sw_en_clk_ip_1x_n2flash_dmacro ckgen01(0x1A60)
#define reg_sw_en_clk_ip_1x_n2flash_dmacro_s 0
#define reg_sw_en_clk_ip_1x_n2flash_dmacro_e 0
#define reg_sw_en_clk_ip_1x2flash_dmacro ckgen01(0x1A64)
#define reg_sw_en_clk_ip_1x2flash_dmacro_s 0
#define reg_sw_en_clk_ip_1x2flash_dmacro_e 0
#define reg_sw_en_clk_m_2x_n2flash_dmacro ckgen01(0x1A68)
#define reg_sw_en_clk_m_2x_n2flash_dmacro_s 0
#define reg_sw_en_clk_m_2x_n2flash_dmacro_e 0
#define reg_sw_en_clk_m_2x2flash_dmacro ckgen01(0x1A6C)
#define reg_sw_en_clk_m_2x2flash_dmacro_s 0
#define reg_sw_en_clk_m_2x2flash_dmacro_e 0
#define reg_sw_en_clk_m_4x_mid2flash_dmacro ckgen01(0x1A70)
#define reg_sw_en_clk_m_4x_mid2flash_dmacro_s 0
#define reg_sw_en_clk_m_4x_mid2flash_dmacro_e 0
#define reg_sw_en_clk_m_4x2flash_dmacro ckgen01(0x1A74)
#define reg_sw_en_clk_m_4x2flash_dmacro_s 0
#define reg_sw_en_clk_m_4x2flash_dmacro_e 0
#define reg_sw_en_fb_mclk2flash_dmacro ckgen01(0x1A78)
#define reg_sw_en_fb_mclk2flash_dmacro_s 0
#define reg_sw_en_fb_mclk2flash_dmacro_e 0
#define reg_sw_en_mpll2flash_dmacro ckgen01(0x1A7C)
#define reg_sw_en_mpll2flash_dmacro_s 0
#define reg_sw_en_mpll2flash_dmacro_e 0
#define reg_sw_en_osp2flash_dmacro ckgen01(0x1A80)
#define reg_sw_en_osp2flash_dmacro_s 0
#define reg_sw_en_osp2flash_dmacro_e 0
#define reg_sw_en_ecc2fcie ckgen01(0x1A84)
#define reg_sw_en_ecc2fcie_s 0
#define reg_sw_en_ecc2fcie_e 0
#define reg_sw_en_fcie_n2fcie ckgen01(0x1A88)
#define reg_sw_en_fcie_n2fcie_s 0
#define reg_sw_en_fcie_n2fcie_e 0
#define reg_sw_en_fcie2fcie ckgen01(0x1A8C)
#define reg_sw_en_fcie2fcie_s 0
#define reg_sw_en_fcie2fcie_e 0
#define reg_sw_en_fcie2sd_sdr_macro ckgen01(0x1A8C)
#define reg_sw_en_fcie2sd_sdr_macro_s 1
#define reg_sw_en_fcie2sd_sdr_macro_e 1
#define reg_sw_en_pad_sd2sd_sdr_macro ckgen01(0x1A90)
#define reg_sw_en_pad_sd2sd_sdr_macro_s 0
#define reg_sw_en_pad_sd2sd_sdr_macro_e 0
#define reg_sw_en_emmc_dqs_skew2emmc_dqs_skew ckgen01(0x1A94)
#define reg_sw_en_emmc_dqs_skew2emmc_dqs_skew_s 0
#define reg_sw_en_emmc_dqs_skew2emmc_dqs_skew_e 0
#define reg_sw_en_emmc_dqs_skew2sd_dqs_skew ckgen01(0x1A94)
#define reg_sw_en_emmc_dqs_skew2sd_dqs_skew_s 1
#define reg_sw_en_emmc_dqs_skew2sd_dqs_skew_e 1
#define reg_sw_en_emmc_dqs_dly_n2skew_latch ckgen01(0x1A98)
#define reg_sw_en_emmc_dqs_dly_n2skew_latch_s 0
#define reg_sw_en_emmc_dqs_dly_n2skew_latch_e 0
#define reg_sw_en_emmc_dqs_dly_n2dqs ckgen01(0x1A98)
#define reg_sw_en_emmc_dqs_dly_n2dqs_s 1
#define reg_sw_en_emmc_dqs_dly_n2dqs_e 1
#define reg_sw_en_emmc_dqs_dly_2nd_n2skew_latch_cmd ckgen01(0x1A9C)
#define reg_sw_en_emmc_dqs_dly_2nd_n2skew_latch_cmd_s 0
#define reg_sw_en_emmc_dqs_dly_2nd_n2skew_latch_cmd_e 0
#define reg_sw_en_gmac_ahb2gmac ckgen01(0x1AAC)
#define reg_sw_en_gmac_ahb2gmac_s 0
#define reg_sw_en_gmac_ahb2gmac_e 0
#define reg_sw_en_gmac_ref2gmac ckgen01(0x1AB0)
#define reg_sw_en_gmac_ref2gmac_s 0
#define reg_sw_en_gmac_ref2gmac_e 0
#define reg_sw_en_gmac_rx2gmac ckgen01(0x1AB4)
#define reg_sw_en_gmac_rx2gmac_s 0
#define reg_sw_en_gmac_rx2gmac_e 0
#define reg_sw_en_gmac_tx2gmac ckgen01(0x1AB8)
#define reg_sw_en_gmac_tx2gmac_s 0
#define reg_sw_en_gmac_tx2gmac_e 0
#define reg_sw_en_au_uart0_synth2mcu_ckctrl_top ckgen01(0x1ACC)
#define reg_sw_en_au_uart0_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_au_uart0_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_au_uart02au_uart0 ckgen01(0x1AD0)
#define reg_sw_en_au_uart02au_uart0_s 0
#define reg_sw_en_au_uart02au_uart0_e 0
#define reg_sw_en_frc_fuart0_synth2mcu_ckctrl_top ckgen01(0x1AD4)
#define reg_sw_en_frc_fuart0_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_frc_fuart0_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_frc_fuart02frciopm ckgen01(0x1AD8)
#define reg_sw_en_frc_fuart02frciopm_s 0
#define reg_sw_en_frc_fuart02frciopm_e 0
#define reg_sw_en_frc_fuart02frciopmrv55 ckgen01(0x1AD8)
#define reg_sw_en_frc_fuart02frciopmrv55_s 1
#define reg_sw_en_frc_fuart02frciopmrv55_e 1
#define reg_sw_en_frc_mspi0_div2mcu_ckctrl_top ckgen01(0x1ADC)
#define reg_sw_en_frc_mspi0_div2mcu_ckctrl_top_s 0
#define reg_sw_en_frc_mspi0_div2mcu_ckctrl_top_e 0
#define reg_sw_en_frc_mspi02frciopm ckgen01(0x1AE0)
#define reg_sw_en_frc_mspi02frciopm_s 0
#define reg_sw_en_frc_mspi02frciopm_e 0
#define reg_sw_en_frc_mspi02frciopmrv55 ckgen01(0x1AE0)
#define reg_sw_en_frc_mspi02frciopmrv55_s 1
#define reg_sw_en_frc_mspi02frciopmrv55_e 1
#define reg_sw_en_frc_uart0_synth2mcu_ckctrl_top ckgen01(0x1AE4)
#define reg_sw_en_frc_uart0_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_frc_uart0_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_frc_uart02frciopm ckgen01(0x1AE8)
#define reg_sw_en_frc_uart02frciopm_s 0
#define reg_sw_en_frc_uart02frciopm_e 0
#define reg_sw_en_frc_uart02frciopmrv55 ckgen01(0x1AE8)
#define reg_sw_en_frc_uart02frciopmrv55_s 1
#define reg_sw_en_frc_uart02frciopmrv55_e 1
#define reg_sw_en_frc_uart1_synth2mcu_ckctrl_top ckgen01(0x1AEC)
#define reg_sw_en_frc_uart1_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_frc_uart1_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_frc_uart12frciopm ckgen01(0x1AF0)
#define reg_sw_en_frc_uart12frciopm_s 0
#define reg_sw_en_frc_uart12frciopm_e 0
#define reg_sw_en_frc_uart12frciopmrv55 ckgen01(0x1AF0)
#define reg_sw_en_frc_uart12frciopmrv55_s 1
#define reg_sw_en_frc_uart12frciopmrv55_e 1
#define reg_sw_en_fuart0_synth2mcu_ckctrl_top ckgen01(0x1AF4)
#define reg_sw_en_fuart0_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_fuart0_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_fuart02mcu_fuart0 ckgen01(0x1AF8)
#define reg_sw_en_fuart02mcu_fuart0_s 0
#define reg_sw_en_fuart02mcu_fuart0_e 0
#define reg_sw_en_uart0_synth2mcu_ckctrl_top ckgen01(0x1AFC)
#define reg_sw_en_uart0_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_uart0_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_uart02mcu_uart0 ckgen01(0x1B00)
#define reg_sw_en_uart02mcu_uart0_s 0
#define reg_sw_en_uart02mcu_uart0_e 0
#define reg_sw_en_uart1_synth2mcu_ckctrl_top ckgen01(0x1B04)
#define reg_sw_en_uart1_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_uart1_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_uart12mcu_uart1 ckgen01(0x1B08)
#define reg_sw_en_uart12mcu_uart1_s 0
#define reg_sw_en_uart12mcu_uart1_e 0
#define reg_sw_en_uart2_synth2mcu_ckctrl_top ckgen01(0x1B0C)
#define reg_sw_en_uart2_synth2mcu_ckctrl_top_s 0
#define reg_sw_en_uart2_synth2mcu_ckctrl_top_e 0
#define reg_sw_en_uart22mcu_uart2 ckgen01(0x1B10)
#define reg_sw_en_uart22mcu_uart2_s 0
#define reg_sw_en_uart22mcu_uart2_e 0
#define reg_sw_en_mcu_au2audio_r2 ckgen01(0x1B44)
#define reg_sw_en_mcu_au2audio_r2_s 0
#define reg_sw_en_mcu_au2audio_r2_e 0
#define reg_sw_en_mcu_au2rv55audio ckgen01(0x1B44)
#define reg_sw_en_mcu_au2rv55audio_s 1
#define reg_sw_en_mcu_au2rv55audio_e 1
#define reg_sw_en_mcu_bus2frciopm ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2frciopm_s 0
#define reg_sw_en_mcu_bus2frciopm_e 0
#define reg_sw_en_mcu_bus2frciopmrv55 ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2frciopmrv55_s 1
#define reg_sw_en_mcu_bus2frciopmrv55_e 1
#define reg_sw_en_mcu_bus2mac ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2mac_s 2
#define reg_sw_en_mcu_bus2mac_e 2
#define reg_sw_en_mcu_bus2scscl ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2scscl_s 3
#define reg_sw_en_mcu_bus2scscl_e 3
#define reg_sw_en_au_mcu_bus2au_mcu ckgen01(0x1B4C)
#define reg_sw_en_au_mcu_bus2au_mcu_s 4
#define reg_sw_en_au_mcu_bus2au_mcu_e 4
#define reg_sw_en_mcu_bus2demod0 ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2demod0_s 5
#define reg_sw_en_mcu_bus2demod0_e 5
#define reg_sw_en_mcu_bus2mcu_m2mcu ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2mcu_m2mcu_s 6
#define reg_sw_en_mcu_bus2mcu_m2mcu_e 6
#define reg_sw_en_mcu_bus2rv55frc ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2rv55frc_s 7
#define reg_sw_en_mcu_bus2rv55frc_e 7
#define reg_sw_en_mcu_bus2rv55pqu ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2rv55pqu_s 8
#define reg_sw_en_mcu_bus2rv55pqu_e 8
#define reg_sw_en_mcu_bus2mcu_nonpm_riu_bridge ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2mcu_nonpm_riu_bridge_s 9
#define reg_sw_en_mcu_bus2mcu_nonpm_riu_bridge_e 9
#define reg_sw_en_mcu_bus2mcu_codec_riu_bridge ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2mcu_codec_riu_bridge_s 10
#define reg_sw_en_mcu_bus2mcu_codec_riu_bridge_e 10
#define reg_sw_en_mcu_bus2mcusys_xiu_bridge ckgen01(0x1B4C)
#define reg_sw_en_mcu_bus2mcusys_xiu_bridge_s 11
#define reg_sw_en_mcu_bus2mcusys_xiu_bridge_e 11
#define reg_sw_en_mcu_codec2mcu_codec_riu_bridge ckgen01(0x1B54)
#define reg_sw_en_mcu_codec2mcu_codec_riu_bridge_s 0
#define reg_sw_en_mcu_codec2mcu_codec_riu_bridge_e 0
#define reg_sw_en_mcu_codec2secure_top_codec ckgen01(0x1B54)
#define reg_sw_en_mcu_codec2secure_top_codec_s 2
#define reg_sw_en_mcu_codec2secure_top_codec_e 2
#define reg_sw_en_mcu_dmd2demod0 ckgen01(0x1B5C)
#define reg_sw_en_mcu_dmd2demod0_s 0
#define reg_sw_en_mcu_dmd2demod0_e 0
#define reg_sw_en_mcu_frc2frciopm ckgen01(0x1B64)
#define reg_sw_en_mcu_frc2frciopm_s 0
#define reg_sw_en_mcu_frc2frciopm_e 0
#define reg_sw_en_mcu_frc2frciopmrv55 ckgen01(0x1B64)
#define reg_sw_en_mcu_frc2frciopmrv55_s 1
#define reg_sw_en_mcu_frc2frciopmrv55_e 1
#define reg_sw_en_mcu_frc2rv55frc ckgen01(0x1B64)
#define reg_sw_en_mcu_frc2rv55frc_s 2
#define reg_sw_en_mcu_frc2rv55frc_e 2
#define reg_sw_en_mcu_frc2rv55pqu ckgen01(0x1B64)
#define reg_sw_en_mcu_frc2rv55pqu_s 3
#define reg_sw_en_mcu_frc2rv55pqu_e 3
#define reg_sw_en_mcu_hdmi2mac ckgen01(0x1B6C)
#define reg_sw_en_mcu_hdmi2mac_s 1
#define reg_sw_en_mcu_hdmi2mac_e 1
#define reg_sw_en_mcu_nonpm2chip_reg ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2chip_reg_s 0
#define reg_sw_en_mcu_nonpm2chip_reg_e 0
#define reg_sw_en_mcu_nonpm2cmdq ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2cmdq_s 1
#define reg_sw_en_mcu_nonpm2cmdq_e 1
#define reg_sw_en_mcu_nonpm2demod0 ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2demod0_s 2
#define reg_sw_en_mcu_nonpm2demod0_e 2
#define reg_sw_en_mcu_nonpm2dscrmb ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2dscrmb_s 3
#define reg_sw_en_mcu_nonpm2dscrmb_e 3
#define reg_sw_en_mcu_nonpm2fcie ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2fcie_s 4
#define reg_sw_en_mcu_nonpm2fcie_e 4
#define reg_sw_en_mcu_nonpm2pad_top ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2pad_top_s 5
#define reg_sw_en_mcu_nonpm2pad_top_e 5
#define reg_sw_en_mcu_nonpm2frciopmrv55 ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2frciopmrv55_s 6
#define reg_sw_en_mcu_nonpm2frciopmrv55_e 6
#define reg_sw_en_mcu_nonpm2frcmehalo ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2frcmehalo_s 7
#define reg_sw_en_mcu_nonpm2frcmehalo_e 7
#define reg_sw_en_mcu_nonpm2ge ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2ge_s 8
#define reg_sw_en_mcu_nonpm2ge_e 8
#define reg_sw_en_mcu_nonpm2gmac ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2gmac_s 9
#define reg_sw_en_mcu_nonpm2gmac_e 9
#define reg_sw_en_mcu_nonpm2gpd ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2gpd_s 10
#define reg_sw_en_mcu_nonpm2gpd_e 10
#define reg_sw_en_mcu_nonpm2gpu_die ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2gpu_die_s 11
#define reg_sw_en_mcu_nonpm2gpu_die_e 11
#define reg_sw_en_mcu_nonpm2gpu_nodie ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2gpu_nodie_s 12
#define reg_sw_en_mcu_nonpm2gpu_nodie_e 12
#define reg_sw_en_mcu_nonpm2intr_ctrl_top_wp ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2intr_ctrl_top_wp_s 13
#define reg_sw_en_mcu_nonpm2intr_ctrl_top_wp_e 13
#define reg_sw_en_mcu_nonpm2mac ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2mac_s 14
#define reg_sw_en_mcu_nonpm2mac_e 14
#define reg_sw_en_mcu_nonpm2mcu_bdma ckgen01(0x1B74)
#define reg_sw_en_mcu_nonpm2mcu_bdma_s 15
#define reg_sw_en_mcu_nonpm2mcu_bdma_e 15
#define reg_sw_en_mcu_nonpm2mcu_demura ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_demura_s 0
#define reg_sw_en_mcu_nonpm2mcu_demura_e 0
#define reg_sw_en_mcu_nonpm2mcu_fuart ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_fuart_s 1
#define reg_sw_en_mcu_nonpm2mcu_fuart_e 1
#define reg_sw_en_mcu_nonpm2mcu_mailbox0 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mailbox0_s 2
#define reg_sw_en_mcu_nonpm2mcu_mailbox0_e 2
#define reg_sw_en_mcu_nonpm2mcu_mailbox1 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mailbox1_s 3
#define reg_sw_en_mcu_nonpm2mcu_mailbox1_e 3
#define reg_sw_en_mcu_nonpm2mcu_mailbox2 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mailbox2_s 4
#define reg_sw_en_mcu_nonpm2mcu_mailbox2_e 4
#define reg_sw_en_mcu_nonpm2mcu_mailbox3 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mailbox3_s 5
#define reg_sw_en_mcu_nonpm2mcu_mailbox3_e 5
#define reg_sw_en_mcu_nonpm2mcu_mailbox4 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mailbox4_s 6
#define reg_sw_en_mcu_nonpm2mcu_mailbox4_e 6
#define reg_sw_en_mcu_nonpm2mcu_mailbox5 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mailbox5_s 7
#define reg_sw_en_mcu_nonpm2mcu_mailbox5_e 7
#define reg_sw_en_mcu_nonpm2mcu_mcuif ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mcuif_s 8
#define reg_sw_en_mcu_nonpm2mcu_mcuif_e 8
#define reg_sw_en_mcu_nonpm2mcu_miic0 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_miic0_s 9
#define reg_sw_en_mcu_nonpm2mcu_miic0_e 9
#define reg_sw_en_mcu_nonpm2mcu_miic1 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_miic1_s 10
#define reg_sw_en_mcu_nonpm2mcu_miic1_e 10
#define reg_sw_en_mcu_nonpm2mcu_miic2 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_miic2_s 11
#define reg_sw_en_mcu_nonpm2mcu_miic2_e 11
#define reg_sw_en_mcu_nonpm2mcu_miic3 ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_miic3_s 12
#define reg_sw_en_mcu_nonpm2mcu_miic3_e 12
#define reg_sw_en_mcu_nonpm2mcu_mspi_all ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_mspi_all_s 13
#define reg_sw_en_mcu_nonpm2mcu_mspi_all_e 13
#define reg_sw_en_mcu_nonpm2mcu_fmly_rom ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_fmly_rom_s 14
#define reg_sw_en_mcu_nonpm2mcu_fmly_rom_e 14
#define reg_sw_en_mcu_nonpm2mcu_nonpm_riu_bridge ckgen01(0x1B78)
#define reg_sw_en_mcu_nonpm2mcu_nonpm_riu_bridge_s 15
#define reg_sw_en_mcu_nonpm2mcu_nonpm_riu_bridge_e 15
#define reg_sw_en_mcu_nonpm2mcu_uart0 ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2mcu_uart0_s 1
#define reg_sw_en_mcu_nonpm2mcu_uart0_e 1
#define reg_sw_en_mcu_nonpm2mcu_uart1 ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2mcu_uart1_s 2
#define reg_sw_en_mcu_nonpm2mcu_uart1_e 2
#define reg_sw_en_mcu_nonpm2mcu_uart2 ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2mcu_uart2_s 3
#define reg_sw_en_mcu_nonpm2mcu_uart2_e 3
#define reg_sw_en_mcu_nonpm2mcu_xd2miu ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2mcu_xd2miu_s 4
#define reg_sw_en_mcu_nonpm2mcu_xd2miu_e 4
#define reg_sw_en_mcu_nonpm2mcusys_xiu_bridge ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2mcusys_xiu_bridge_s 5
#define reg_sw_en_mcu_nonpm2mcusys_xiu_bridge_e 5
#define reg_sw_en_mcu_nonpm2mheg5_smi ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2mheg5_smi_s 6
#define reg_sw_en_mcu_nonpm2mheg5_smi_e 6
#define reg_sw_en_mcu_nonpm2pextp ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2pextp_s 7
#define reg_sw_en_mcu_nonpm2pextp_e 7
#define reg_sw_en_mcu_nonpm2pextp_phy_top ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2pextp_phy_top_s 8
#define reg_sw_en_mcu_nonpm2pextp_phy_top_e 8
#define reg_sw_en_mcu_nonpm2prearb2pm_riu_top ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2prearb2pm_riu_top_s 9
#define reg_sw_en_mcu_nonpm2prearb2pm_riu_top_e 9
#define reg_sw_en_mcu_nonpm2rv55frc ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2rv55frc_s 10
#define reg_sw_en_mcu_nonpm2rv55frc_e 10
#define reg_sw_en_mcu_nonpm2rv55pqu ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2rv55pqu_s 11
#define reg_sw_en_mcu_nonpm2rv55pqu_e 11
#define reg_sw_en_mcu_nonpm2scace ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2scace_s 12
#define reg_sw_en_mcu_nonpm2scace_e 12
#define reg_sw_en_mcu_nonpm2scdv ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2scdv_s 13
#define reg_sw_en_mcu_nonpm2scdv_e 13
#define reg_sw_en_mcu_nonpm2scip ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2scip_s 14
#define reg_sw_en_mcu_nonpm2scip_e 14
#define reg_sw_en_mcu_nonpm2scmw ckgen01(0x1B7C)
#define reg_sw_en_mcu_nonpm2scmw_s 15
#define reg_sw_en_mcu_nonpm2scmw_e 15
#define reg_sw_en_mcu_nonpm2scnr ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2scnr_s 0
#define reg_sw_en_mcu_nonpm2scnr_e 0
#define reg_sw_en_mcu_nonpm2scpq ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2scpq_s 1
#define reg_sw_en_mcu_nonpm2scpq_e 1
#define reg_sw_en_mcu_nonpm2scscl ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2scscl_s 2
#define reg_sw_en_mcu_nonpm2scscl_e 2
#define reg_sw_en_mcu_nonpm2scsr ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2scsr_s 3
#define reg_sw_en_mcu_nonpm2scsr_e 3
#define reg_sw_en_mcu_nonpm2sctcon ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2sctcon_s 4
#define reg_sw_en_mcu_nonpm2sctcon_e 4
#define reg_sw_en_mcu_nonpm2smart0 ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2smart0_s 5
#define reg_sw_en_mcu_nonpm2smart0_e 5
#define reg_sw_en_mcu_nonpm2smart1 ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2smart1_s 6
#define reg_sw_en_mcu_nonpm2smart1_e 6
#define reg_sw_en_mcu_nonpm2ssusb ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2ssusb_s 7
#define reg_sw_en_mcu_nonpm2ssusb_e 7
#define reg_sw_en_mcu_nonpm2ssusb_dig_phy_top ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2ssusb_dig_phy_top_s 8
#define reg_sw_en_mcu_nonpm2ssusb_dig_phy_top_e 8
#define reg_sw_en_mcu_nonpm2ssusb_dig_phy_top_p1 ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2ssusb_dig_phy_top_p1_s 9
#define reg_sw_en_mcu_nonpm2ssusb_dig_phy_top_p1_e 9
#define reg_sw_en_mcu_nonpm2ssusb_u2_phy_top ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2ssusb_u2_phy_top_s 10
#define reg_sw_en_mcu_nonpm2ssusb_u2_phy_top_e 10
#define reg_sw_en_mcu_nonpm2tsp ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2tsp_s 11
#define reg_sw_en_mcu_nonpm2tsp_e 11
#define reg_sw_en_mcu_nonpm2tsp_smi ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2tsp_smi_s 12
#define reg_sw_en_mcu_nonpm2tsp_smi_e 12
#define reg_sw_en_mcu_nonpm2ufs ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2ufs_s 13
#define reg_sw_en_mcu_nonpm2ufs_e 13
#define reg_sw_en_mcu_nonpm2ufs_phy ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2ufs_phy_s 14
#define reg_sw_en_mcu_nonpm2ufs_phy_e 14
#define reg_sw_en_mcu_nonpm2usb20 ckgen01(0x1B80)
#define reg_sw_en_mcu_nonpm2usb20_s 15
#define reg_sw_en_mcu_nonpm2usb20_e 15
#define reg_sw_en_mcu_nonpm2vd ckgen01(0x1B84)
#define reg_sw_en_mcu_nonpm2vd_s 0
#define reg_sw_en_mcu_nonpm2vd_e 0
#define reg_sw_en_mcu_nonpm2venc ckgen01(0x1B84)
#define reg_sw_en_mcu_nonpm2venc_s 1
#define reg_sw_en_mcu_nonpm2venc_e 1
#define reg_sw_en_xiu2gce_biu ckgen01(0x1B84)
#define reg_sw_en_xiu2gce_biu_s 2
#define reg_sw_en_xiu2gce_biu_e 2
#define reg_sw_en_mcu_nonpm2xiu2apb ckgen01(0x1B84)
#define reg_sw_en_mcu_nonpm2xiu2apb_s 3
#define reg_sw_en_mcu_nonpm2xiu2apb_e 3
#define reg_sw_en_mcu_nonpm2ip_wrap ckgen01(0x1B84)
#define reg_sw_en_mcu_nonpm2ip_wrap_s 4
#define reg_sw_en_mcu_nonpm2ip_wrap_e 4
#define reg_sw_en_mcu_nonpm2viva_smi ckgen01(0x1B84)
#define reg_sw_en_mcu_nonpm2viva_smi_s 5
#define reg_sw_en_mcu_nonpm2viva_smi_e 5
#define reg_sw_en_mcu_nonpm2viva_vbdma ckgen01(0x1B84)
#define reg_sw_en_mcu_nonpm2viva_vbdma_s 6
#define reg_sw_en_mcu_nonpm2viva_vbdma_e 6
#define reg_sw_en_mcu_vd2mcu_m2mcu ckgen01(0x1BAC)
#define reg_sw_en_mcu_vd2mcu_m2mcu_s 0
#define reg_sw_en_mcu_vd2mcu_m2mcu_e 0
#define reg_sw_en_mcu_vd2mcu_mcuif ckgen01(0x1BAC)
#define reg_sw_en_mcu_vd2mcu_mcuif_s 1
#define reg_sw_en_mcu_vd2mcu_mcuif_e 1
#define reg_sw_en_mcu_vd2vd ckgen01(0x1BAC)
#define reg_sw_en_mcu_vd2vd_s 4
#define reg_sw_en_mcu_vd2vd_e 4
#define reg_sw_en_mcu_sc2rv55frc ckgen01(0x1BB4)
#define reg_sw_en_mcu_sc2rv55frc_s 0
#define reg_sw_en_mcu_sc2rv55frc_e 0
#define reg_sw_en_mcu_sc2rv55pqu ckgen01(0x1BB4)
#define reg_sw_en_mcu_sc2rv55pqu_s 1
#define reg_sw_en_mcu_sc2rv55pqu_e 1
#define reg_sw_en_mcu_xc2scace ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scace_s 2
#define reg_sw_en_mcu_xc2scace_e 2
#define reg_sw_en_mcu_xc2scdv ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scdv_s 3
#define reg_sw_en_mcu_xc2scdv_e 3
#define reg_sw_en_mcu_xc2scip ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scip_s 4
#define reg_sw_en_mcu_xc2scip_e 4
#define reg_sw_en_mcu_xc2scmw ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scmw_s 5
#define reg_sw_en_mcu_xc2scmw_e 5
#define reg_sw_en_mcu_xc2scnr ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scnr_s 6
#define reg_sw_en_mcu_xc2scnr_e 6
#define reg_sw_en_mcu_xc2scpq ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scpq_s 7
#define reg_sw_en_mcu_xc2scpq_e 7
#define reg_sw_en_mcu_xc2scscl ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scscl_s 8
#define reg_sw_en_mcu_xc2scscl_e 8
#define reg_sw_en_mcu_xc2scsr ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2scsr_s 9
#define reg_sw_en_mcu_xc2scsr_e 9
#define reg_sw_en_mcu_xc2sctcon ckgen01(0x1BB4)
#define reg_sw_en_mcu_xc2sctcon_s 10
#define reg_sw_en_mcu_xc2sctcon_e 10
#define reg_sw_en_miic02mcu_miic0 ckgen01(0x1BC4)
#define reg_sw_en_miic02mcu_miic0_s 0
#define reg_sw_en_miic02mcu_miic0_e 0
#define reg_sw_en_miic12mcu_miic1 ckgen01(0x1BC8)
#define reg_sw_en_miic12mcu_miic1_s 0
#define reg_sw_en_miic12mcu_miic1_e 0
#define reg_sw_en_miic22mcu_miic2 ckgen01(0x1BCC)
#define reg_sw_en_miic22mcu_miic2_s 0
#define reg_sw_en_miic22mcu_miic2_e 0
#define reg_sw_en_miic32mcu_miic3 ckgen01(0x1BD0)
#define reg_sw_en_miic32mcu_miic3_s 0
#define reg_sw_en_miic32mcu_miic3_e 0
#define reg_sw_en_mspi12mcu_mspi1 ckgen01(0x1BE4)
#define reg_sw_en_mspi12mcu_mspi1_s 0
#define reg_sw_en_mspi12mcu_mspi1_e 0
#define reg_sw_en_mspi22mcu_mspi2 ckgen01(0x1BE8)
#define reg_sw_en_mspi22mcu_mspi2_s 0
#define reg_sw_en_mspi22mcu_mspi2_e 0
#define reg_sw_en_mspi32mcu_mspi3 ckgen01(0x1BEC)
#define reg_sw_en_mspi32mcu_mspi3_s 0
#define reg_sw_en_mspi32mcu_mspi3_e 0
#define reg_sw_en_mspi42mcu_mspi4 ckgen01(0x1BF0)
#define reg_sw_en_mspi42mcu_mspi4_s 0
#define reg_sw_en_mspi42mcu_mspi4_e 0
#define reg_sw_en_mspi52mcu_mspi5 ckgen01(0x1BF4)
#define reg_sw_en_mspi52mcu_mspi5_s 0
#define reg_sw_en_mspi52mcu_mspi5_e 0
#define reg_sw_en_mspi62mcu_mspi6 ckgen01(0x1BF8)
#define reg_sw_en_mspi62mcu_mspi6_s 0
#define reg_sw_en_mspi62mcu_mspi6_e 0
#define reg_sw_en_mspi72mcu_mspi7 ckgen01(0x1BFC)
#define reg_sw_en_mspi72mcu_mspi7_s 0
#define reg_sw_en_mspi72mcu_mspi7_e 0
#define reg_sw_en_mspi_cilink_div2mcu_ckctrl_top ckgen01(0x1C00)
#define reg_sw_en_mspi_cilink_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi_cilink_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi_cilink2mcu_mspi_cilink ckgen01(0x1C04)
#define reg_sw_en_mspi_cilink2mcu_mspi_cilink_s 0
#define reg_sw_en_mspi_cilink2mcu_mspi_cilink_e 0
#define reg_sw_en_mspi0_div2mcu_ckctrl_top ckgen01(0x1C08)
#define reg_sw_en_mspi0_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi0_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi1_div2mcu_ckctrl_top ckgen01(0x1C0C)
#define reg_sw_en_mspi1_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi1_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi2_div2mcu_ckctrl_top ckgen01(0x1C10)
#define reg_sw_en_mspi2_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi2_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi02mcu_mspi0 ckgen01(0x1C14)
#define reg_sw_en_mspi02mcu_mspi0_s 0
#define reg_sw_en_mspi02mcu_mspi0_e 0
#define reg_sw_en_mspi3_div2mcu_ckctrl_top ckgen01(0x1C18)
#define reg_sw_en_mspi3_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi3_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi4_div2mcu_ckctrl_top ckgen01(0x1C1C)
#define reg_sw_en_mspi4_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi4_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi5_div2mcu_ckctrl_top ckgen01(0x1C20)
#define reg_sw_en_mspi5_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi5_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi6_div2mcu_ckctrl_top ckgen01(0x1C24)
#define reg_sw_en_mspi6_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi6_div2mcu_ckctrl_top_e 0
#define reg_sw_en_mspi7_div2mcu_ckctrl_top ckgen01(0x1C28)
#define reg_sw_en_mspi7_div2mcu_ckctrl_top_s 0
#define reg_sw_en_mspi7_div2mcu_ckctrl_top_e 0
#define reg_sw_en_spi2mcu_spi ckgen01(0x1C34)
#define reg_sw_en_spi2mcu_spi_s 0
#define reg_sw_en_spi2mcu_spi_e 0
#define reg_sw_en_spi2mcusys_xiu_bridge ckgen01(0x1C34)
#define reg_sw_en_spi2mcusys_xiu_bridge_s 1
#define reg_sw_en_spi2mcusys_xiu_bridge_e 1
#define reg_sw_en_xtal_12m2pextp_phy_top ckgen01(0x1C54)
#define reg_sw_en_xtal_12m2pextp_phy_top_s 0
#define reg_sw_en_xtal_12m2pextp_phy_top_e 0
#define reg_sw_en_pextp_ahb_apb2pextp ckgen01(0x1C58)
#define reg_sw_en_pextp_ahb_apb2pextp_s 0
#define reg_sw_en_pextp_ahb_apb2pextp_e 0
#define reg_sw_en_pextp_pl_pclk2pextp ckgen01(0x1C60)
#define reg_sw_en_pextp_pl_pclk2pextp_s 0
#define reg_sw_en_pextp_pl_pclk2pextp_e 0
#define reg_sw_en_pextp_tl2pextp ckgen01(0x1C64)
#define reg_sw_en_pextp_tl2pextp_s 0
#define reg_sw_en_pextp_tl2pextp_e 0
#define reg_sw_en_ufs_aes2ufs ckgen01(0x1C78)
#define reg_sw_en_ufs_aes2ufs_s 0
#define reg_sw_en_ufs_aes2ufs_e 0
#define reg_sw_en_ufs_ahb2ufs ckgen01(0x1C7C)
#define reg_sw_en_ufs_ahb2ufs_s 0
#define reg_sw_en_ufs_ahb2ufs_e 0
#define reg_sw_en_ufs_mp_sap_cfg2ufs ckgen01(0x1C84)
#define reg_sw_en_ufs_mp_sap_cfg2ufs_s 0
#define reg_sw_en_ufs_mp_sap_cfg2ufs_e 0
#define reg_sw_en_ufs_rx_symbol2ufs ckgen01(0x1C88)
#define reg_sw_en_ufs_rx_symbol2ufs_s 0
#define reg_sw_en_ufs_rx_symbol2ufs_e 0
#define reg_sw_en_ufs_tx_symbol2ufs ckgen01(0x1C8C)
#define reg_sw_en_ufs_tx_symbol2ufs_s 0
#define reg_sw_en_ufs_tx_symbol2ufs_e 0
#define reg_sw_en_ufs_unipro_cg_syn2ufs ckgen01(0x1C90)
#define reg_sw_en_ufs_unipro_cg_syn2ufs_s 0
#define reg_sw_en_ufs_unipro_cg_syn2ufs_e 0
#define reg_sw_en_ufs2ufs ckgen01(0x1C94)
#define reg_sw_en_ufs2ufs_s 0
#define reg_sw_en_ufs2ufs_e 0
#define reg_sw_en_ufs_phy_scan_150m2ufs_phy ckgen01(0x1C98)
#define reg_sw_en_ufs_phy_scan_150m2ufs_phy_s 0
#define reg_sw_en_ufs_phy_scan_150m2ufs_phy_e 0
#define reg_sw_en_ufs_phy_scan_300m2ufs_phy ckgen01(0x1C9C)
#define reg_sw_en_ufs_phy_scan_300m2ufs_phy_s 0
#define reg_sw_en_ufs_phy_scan_300m2ufs_phy_e 0
#define reg_sw_en_ufs_phy_scan_600m2ufs_phy ckgen01(0x1CA0)
#define reg_sw_en_ufs_phy_scan_600m2ufs_phy_s 0
#define reg_sw_en_ufs_phy_scan_600m2ufs_phy_e 0
#define reg_sw_en_ufs_phy_scan_26m2ufs_phy ckgen01(0x1CA4)
#define reg_sw_en_ufs_phy_scan_26m2ufs_phy_s 0
#define reg_sw_en_ufs_phy_scan_26m2ufs_phy_e 0
#define reg_sw_en_xtal_12m2ssusb_dig_phy_top ckgen01(0x1CB4)
#define reg_sw_en_xtal_12m2ssusb_dig_phy_top_s 0
#define reg_sw_en_xtal_12m2ssusb_dig_phy_top_e 0
#define reg_sw_en_xtal_12m2ssusb_dig_phy_top_p1 ckgen01(0x1CB8)
#define reg_sw_en_xtal_12m2ssusb_dig_phy_top_p1_s 0
#define reg_sw_en_xtal_12m2ssusb_dig_phy_top_p1_e 0
#define reg_sw_en_xtal_12m2ssusb_u2_phy_top ckgen01(0x1CBC)
#define reg_sw_en_xtal_12m2ssusb_u2_phy_top_s 0
#define reg_sw_en_xtal_12m2ssusb_u2_phy_top_e 0
#define reg_sw_en_ssusb_frmcnt2ssusb ckgen01(0x1CC0)
#define reg_sw_en_ssusb_frmcnt2ssusb_s 0
#define reg_sw_en_ssusb_frmcnt2ssusb_e 0
#define reg_sw_en_ssusb_pclk_1p2ssusb ckgen01(0x1CC4)
#define reg_sw_en_ssusb_pclk_1p2ssusb_s 0
#define reg_sw_en_ssusb_pclk_1p2ssusb_e 0
#define reg_sw_en_ssusb_pclk2ssusb ckgen01(0x1CC8)
#define reg_sw_en_ssusb_pclk2ssusb_s 0
#define reg_sw_en_ssusb_pclk2ssusb_e 0
#define reg_sw_en_ssusb_scl2ssusb ckgen01(0x1CCC)
#define reg_sw_en_ssusb_scl2ssusb_s 0
#define reg_sw_en_ssusb_scl2ssusb_e 0
#define reg_sw_en_ssusb_sdin2ssusb ckgen01(0x1CD0)
#define reg_sw_en_ssusb_sdin2ssusb_s 0
#define reg_sw_en_ssusb_sdin2ssusb_e 0
#define reg_sw_en_ssusb_sys2ssusb ckgen01(0x1CD4)
#define reg_sw_en_ssusb_sys2ssusb_s 0
#define reg_sw_en_ssusb_sys2ssusb_e 0
#define reg_sw_en_ssusb_usb20_phy_clk_1p2ssusb ckgen01(0x1CD8)
#define reg_sw_en_ssusb_usb20_phy_clk_1p2ssusb_s 0
#define reg_sw_en_ssusb_usb20_phy_clk_1p2ssusb_e 0
#define reg_sw_en_ssusb_usb20_phy_clk_2p2ssusb ckgen01(0x1CDC)
#define reg_sw_en_ssusb_usb20_phy_clk_2p2ssusb_s 0
#define reg_sw_en_ssusb_usb20_phy_clk_2p2ssusb_e 0
#define reg_sw_en_ssusb_usb20_phy_clk2ssusb ckgen01(0x1CE0)
#define reg_sw_en_ssusb_usb20_phy_clk2ssusb_s 0
#define reg_sw_en_ssusb_usb20_phy_clk2ssusb_e 0
#define reg_sw_en_ssusb_xhci2ssusb ckgen01(0x1CE4)
#define reg_sw_en_ssusb_xhci2ssusb_s 0
#define reg_sw_en_ssusb_xhci2ssusb_e 0
#define reg_sw_en_usbphy240_mux2usb20_shbg ckgen01(0x1CE8)
#define reg_sw_en_usbphy240_mux2usb20_shbg_s 0
#define reg_sw_en_usbphy240_mux2usb20_shbg_e 0
#define reg_sw_en_usbphy2402usb20_shbg ckgen01(0x1CEC)
#define reg_sw_en_usbphy2402usb20_shbg_s 0
#define reg_sw_en_usbphy2402usb20_shbg_e 0
#define reg_sw_en_usbphy302usb20_shbg ckgen01(0x1CF0)
#define reg_sw_en_usbphy302usb20_shbg_s 0
#define reg_sw_en_usbphy302usb20_shbg_e 0
#define reg_sw_en_p0_clk_tmdspll_test_dig2mac ckgen01(0x1D14)
#define reg_sw_en_p0_clk_tmdspll_test_dig2mac_s 0
#define reg_sw_en_p0_clk_tmdspll_test_dig2mac_e 0
#define reg_sw_en_p1_clk_tmdspll_test_dig2mac ckgen01(0x1D18)
#define reg_sw_en_p1_clk_tmdspll_test_dig2mac_s 0
#define reg_sw_en_p1_clk_tmdspll_test_dig2mac_e 0
#define reg_sw_en_p2_clk_tmdspll_test_dig2mac ckgen01(0x1D1C)
#define reg_sw_en_p2_clk_tmdspll_test_dig2mac_s 0
#define reg_sw_en_p2_clk_tmdspll_test_dig2mac_e 0
#define reg_sw_en_p3_clk_tmdspll_test_dig2mac ckgen01(0x1D20)
#define reg_sw_en_p3_clk_tmdspll_test_dig2mac_s 0
#define reg_sw_en_p3_clk_tmdspll_test_dig2mac_e 0
#define reg_sw_en_clk_128fs_fb_s0_ff2mac ckgen01(0x1D24)
#define reg_sw_en_clk_128fs_fb_s0_ff2mac_s 0
#define reg_sw_en_clk_128fs_fb_s0_ff2mac_e 0
#define reg_sw_en_clk_128fs_fb_s1_ff2mac ckgen01(0x1D28)
#define reg_sw_en_clk_128fs_fb_s1_ff2mac_s 0
#define reg_sw_en_clk_128fs_fb_s1_ff2mac_e 0
#define reg_sw_en_xtal_24m2mheg5_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2mheg5_mbist_s 0
#define reg_sw_en_xtal_24m2mheg5_mbist_e 0
#define reg_sw_en_xtal_24m2tsp_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2tsp_mbist_s 1
#define reg_sw_en_xtal_24m2tsp_mbist_e 1
#define reg_sw_en_xtal_24m2demod0_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2demod0_mbist_s 2
#define reg_sw_en_xtal_24m2demod0_mbist_e 2
#define reg_sw_en_xtal_24m2demod1_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2demod1_mbist_s 3
#define reg_sw_en_xtal_24m2demod1_mbist_e 3
#define reg_sw_en_gce_f26m2vdec_soc_mbist ckgen01(0x1D80)
#define reg_sw_en_gce_f26m2vdec_soc_mbist_s 4
#define reg_sw_en_gce_f26m2vdec_soc_mbist_e 4
#define reg_sw_en_xtal_24m2vdec_core0_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2vdec_core0_mbist_s 5
#define reg_sw_en_xtal_24m2vdec_core0_mbist_e 5
#define reg_sw_en_xtal_24m2vdec_core1_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2vdec_core1_mbist_s 6
#define reg_sw_en_xtal_24m2vdec_core1_mbist_e 6
#define reg_sw_en_xtal_24m2vdec_core2_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2vdec_core2_mbist_s 7
#define reg_sw_en_xtal_24m2vdec_core2_mbist_e 7
#define reg_sw_en_xtal_24m2aia_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2aia_mbist_s 8
#define reg_sw_en_xtal_24m2aia_mbist_e 8
#define reg_sw_en_xtal_24m2dramc0_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2dramc0_mbist_s 9
#define reg_sw_en_xtal_24m2dramc0_mbist_e 9
#define reg_sw_en_xtal_24m2dramc1_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2dramc1_mbist_s 10
#define reg_sw_en_xtal_24m2dramc1_mbist_e 10
#define reg_sw_en_xtal_24m2dramc2_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2dramc2_mbist_s 11
#define reg_sw_en_xtal_24m2dramc2_mbist_e 11
#define reg_sw_en_xtal_24m2gpu_die_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2gpu_die_mbist_s 12
#define reg_sw_en_xtal_24m2gpu_die_mbist_e 12
#define reg_sw_en_xtal_24m2gpu_nodie_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2gpu_nodie_mbist_s 13
#define reg_sw_en_xtal_24m2gpu_nodie_mbist_e 13
#define reg_sw_en_clk_xtal_242hdmirx_mbist ckgen01(0x1D80)
#define reg_sw_en_clk_xtal_242hdmirx_mbist_s 14
#define reg_sw_en_clk_xtal_242hdmirx_mbist_e 14
#define reg_sw_en_xtal_24m2ip_wrap_mbist ckgen01(0x1D80)
#define reg_sw_en_xtal_24m2ip_wrap_mbist_s 15
#define reg_sw_en_xtal_24m2ip_wrap_mbist_e 15
#define reg_sw_en_xtal_24m2mcusys_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2mcusys_mbist_s 0
#define reg_sw_en_xtal_24m2mcusys_mbist_e 0
#define reg_sw_en_xtal_24m2mod_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2mod_mbist_s 1
#define reg_sw_en_xtal_24m2mod_mbist_e 1
#define reg_sw_en_viva_xtal_24m2vivaldi9_mbist ckgen01(0x1D84)
#define reg_sw_en_viva_xtal_24m2vivaldi9_mbist_s 2
#define reg_sw_en_viva_xtal_24m2vivaldi9_mbist_e 2
#define reg_sw_en_xtal_24m2audio_r2_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2audio_r2_mbist_s 3
#define reg_sw_en_xtal_24m2audio_r2_mbist_e 3
#define reg_sw_en_xtal_24m2rv55audio_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2rv55audio_mbist_s 4
#define reg_sw_en_xtal_24m2rv55audio_mbist_e 4
#define reg_sw_en_xtal_24m2frciopmrv55_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2frciopmrv55_mbist_s 5
#define reg_sw_en_xtal_24m2frciopmrv55_mbist_e 5
#define reg_sw_en_xtal_24m2rv55frc_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2rv55frc_mbist_s 6
#define reg_sw_en_xtal_24m2rv55frc_mbist_e 6
#define reg_sw_en_xtal_24m2rv55pqu_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2rv55pqu_mbist_s 7
#define reg_sw_en_xtal_24m2rv55pqu_mbist_e 7
#define reg_sw_en_xtal_24m2frcmehalo_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2frcmehalo_mbist_s 8
#define reg_sw_en_xtal_24m2frcmehalo_mbist_e 8
#define reg_sw_en_xtal_24m2frcmemlb_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2frcmemlb_mbist_s 9
#define reg_sw_en_xtal_24m2frcmemlb_mbist_e 9
#define reg_sw_en_xtal_24m2frcmi_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2frcmi_mbist_s 10
#define reg_sw_en_xtal_24m2frcmi_mbist_e 10
#define reg_sw_en_xtal_24m2scace_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2scace_mbist_s 11
#define reg_sw_en_xtal_24m2scace_mbist_e 11
#define reg_sw_en_xtal_24m2scdv_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2scdv_mbist_s 12
#define reg_sw_en_xtal_24m2scdv_mbist_e 12
#define reg_sw_en_xtal_24m2scip_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2scip_mbist_s 13
#define reg_sw_en_xtal_24m2scip_mbist_e 13
#define reg_sw_en_xtal_24m2scmw_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2scmw_mbist_s 14
#define reg_sw_en_xtal_24m2scmw_mbist_e 14
#define reg_sw_en_xtal_24m2scnr_mbist ckgen01(0x1D84)
#define reg_sw_en_xtal_24m2scnr_mbist_s 15
#define reg_sw_en_xtal_24m2scnr_mbist_e 15
#define reg_sw_en_xtal_24m2scpq_mbist ckgen01(0x1D88)
#define reg_sw_en_xtal_24m2scpq_mbist_s 0
#define reg_sw_en_xtal_24m2scpq_mbist_e 0
#define reg_sw_en_xtal_24m2scscl_mbist ckgen01(0x1D88)
#define reg_sw_en_xtal_24m2scscl_mbist_s 1
#define reg_sw_en_xtal_24m2scscl_mbist_e 1
#define reg_sw_en_xtal_24m2scsr_mbist ckgen01(0x1D88)
#define reg_sw_en_xtal_24m2scsr_mbist_s 2
#define reg_sw_en_xtal_24m2scsr_mbist_e 2
#define reg_sw_en_xtal_24m2sctcon_mbist ckgen01(0x1D88)
#define reg_sw_en_xtal_24m2sctcon_mbist_s 3
#define reg_sw_en_xtal_24m2sctcon_mbist_e 3
#define reg_adcpll_test_enable ckgen01(0x1DC0)
#define reg_adcpll_test_enable_s 0
#define reg_adcpll_test_enable_e 0
#define reg_adcpll_test_div_sel ckgen01(0x1DC0)
#define reg_adcpll_test_div_sel_s 4
#define reg_adcpll_test_div_sel_e 6
#define reg_adcpll_test_src_sel ckgen01(0x1DC0)
#define reg_adcpll_test_src_sel_s 8
#define reg_adcpll_test_src_sel_e 15
#define reg_aia_top_test_enable ckgen01(0x1DC4)
#define reg_aia_top_test_enable_s 0
#define reg_aia_top_test_enable_e 0
#define reg_aia_top_test_div_sel ckgen01(0x1DC4)
#define reg_aia_top_test_div_sel_s 4
#define reg_aia_top_test_div_sel_e 6
#define reg_aia_top_test_src_sel ckgen01(0x1DC4)
#define reg_aia_top_test_src_sel_s 8
#define reg_aia_top_test_src_sel_e 15
#define reg_demod0_test_enable ckgen01(0x1DC8)
#define reg_demod0_test_enable_s 0
#define reg_demod0_test_enable_e 0
#define reg_demod0_test_div_sel ckgen01(0x1DC8)
#define reg_demod0_test_div_sel_s 4
#define reg_demod0_test_div_sel_e 6
#define reg_demod0_test_src_sel ckgen01(0x1DC8)
#define reg_demod0_test_src_sel_s 8
#define reg_demod0_test_src_sel_e 15
#define reg_demod1_test_enable ckgen01(0x1DCC)
#define reg_demod1_test_enable_s 0
#define reg_demod1_test_enable_e 0
#define reg_demod1_test_div_sel ckgen01(0x1DCC)
#define reg_demod1_test_div_sel_s 4
#define reg_demod1_test_div_sel_e 6
#define reg_demod1_test_src_sel ckgen01(0x1DCC)
#define reg_demod1_test_src_sel_s 8
#define reg_demod1_test_src_sel_e 15
#define reg_vdec_soc_test_enable ckgen01(0x1DD0)
#define reg_vdec_soc_test_enable_s 0
#define reg_vdec_soc_test_enable_e 0
#define reg_vdec_soc_test_div_sel ckgen01(0x1DD0)
#define reg_vdec_soc_test_div_sel_s 4
#define reg_vdec_soc_test_div_sel_e 6
#define reg_vdec_soc_test_src_sel ckgen01(0x1DD0)
#define reg_vdec_soc_test_src_sel_s 8
#define reg_vdec_soc_test_src_sel_e 15
#define reg_vdec_core0_test_enable ckgen01(0x1DD4)
#define reg_vdec_core0_test_enable_s 0
#define reg_vdec_core0_test_enable_e 0
#define reg_vdec_core0_test_div_sel ckgen01(0x1DD4)
#define reg_vdec_core0_test_div_sel_s 4
#define reg_vdec_core0_test_div_sel_e 6
#define reg_vdec_core0_test_src_sel ckgen01(0x1DD4)
#define reg_vdec_core0_test_src_sel_s 8
#define reg_vdec_core0_test_src_sel_e 15
#define reg_vdec_core1_test_enable ckgen01(0x1DD8)
#define reg_vdec_core1_test_enable_s 0
#define reg_vdec_core1_test_enable_e 0
#define reg_vdec_core1_test_div_sel ckgen01(0x1DD8)
#define reg_vdec_core1_test_div_sel_s 4
#define reg_vdec_core1_test_div_sel_e 6
#define reg_vdec_core1_test_src_sel ckgen01(0x1DD8)
#define reg_vdec_core1_test_src_sel_s 8
#define reg_vdec_core1_test_src_sel_e 15
#define reg_vdec_core2_test_enable ckgen01(0x1DDC)
#define reg_vdec_core2_test_enable_s 0
#define reg_vdec_core2_test_enable_e 0
#define reg_vdec_core2_test_div_sel ckgen01(0x1DDC)
#define reg_vdec_core2_test_div_sel_s 4
#define reg_vdec_core2_test_div_sel_e 6
#define reg_vdec_core2_test_src_sel ckgen01(0x1DDC)
#define reg_vdec_core2_test_src_sel_s 8
#define reg_vdec_core2_test_src_sel_e 15
#define reg_dramc0_test_enable ckgen01(0x1DE0)
#define reg_dramc0_test_enable_s 0
#define reg_dramc0_test_enable_e 0
#define reg_dramc0_test_div_sel ckgen01(0x1DE0)
#define reg_dramc0_test_div_sel_s 4
#define reg_dramc0_test_div_sel_e 6
#define reg_dramc0_test_src_sel ckgen01(0x1DE0)
#define reg_dramc0_test_src_sel_s 8
#define reg_dramc0_test_src_sel_e 15
#define reg_dramc1_test_enable ckgen01(0x1DE4)
#define reg_dramc1_test_enable_s 0
#define reg_dramc1_test_enable_e 0
#define reg_dramc1_test_div_sel ckgen01(0x1DE4)
#define reg_dramc1_test_div_sel_s 4
#define reg_dramc1_test_div_sel_e 6
#define reg_dramc1_test_src_sel ckgen01(0x1DE4)
#define reg_dramc1_test_src_sel_s 8
#define reg_dramc1_test_src_sel_e 15
#define reg_dramc2_test_enable ckgen01(0x1DE8)
#define reg_dramc2_test_enable_s 0
#define reg_dramc2_test_enable_e 0
#define reg_dramc2_test_div_sel ckgen01(0x1DE8)
#define reg_dramc2_test_div_sel_s 4
#define reg_dramc2_test_div_sel_e 6
#define reg_dramc2_test_src_sel ckgen01(0x1DE8)
#define reg_dramc2_test_src_sel_s 8
#define reg_dramc2_test_src_sel_e 15
#define reg_top_test_enable ckgen01(0x1DEC)
#define reg_top_test_enable_s 0
#define reg_top_test_enable_e 0
#define reg_top_test_div_sel ckgen01(0x1DEC)
#define reg_top_test_div_sel_s 4
#define reg_top_test_div_sel_e 6
#define reg_top_test_src_sel ckgen01(0x1DEC)
#define reg_top_test_src_sel_s 8
#define reg_top_test_src_sel_e 15
#define reg_mheg5_test_enable ckgen01(0x1DF0)
#define reg_mheg5_test_enable_s 0
#define reg_mheg5_test_enable_e 0
#define reg_mheg5_test_div_sel ckgen01(0x1DF0)
#define reg_mheg5_test_div_sel_s 4
#define reg_mheg5_test_div_sel_e 6
#define reg_mheg5_test_src_sel ckgen01(0x1DF0)
#define reg_mheg5_test_src_sel_s 8
#define reg_mheg5_test_src_sel_e 15
#define reg_gpu_die_test_enable ckgen01(0x1DF4)
#define reg_gpu_die_test_enable_s 0
#define reg_gpu_die_test_enable_e 0
#define reg_gpu_die_test_div_sel ckgen01(0x1DF4)
#define reg_gpu_die_test_div_sel_s 4
#define reg_gpu_die_test_div_sel_e 6
#define reg_gpu_die_test_src_sel ckgen01(0x1DF4)
#define reg_gpu_die_test_src_sel_s 8
#define reg_gpu_die_test_src_sel_e 15
#define reg_gpu_nodie_test_enable ckgen01(0x1DF8)
#define reg_gpu_nodie_test_enable_s 0
#define reg_gpu_nodie_test_enable_e 0
#define reg_gpu_nodie_test_div_sel ckgen01(0x1DF8)
#define reg_gpu_nodie_test_div_sel_s 4
#define reg_gpu_nodie_test_div_sel_e 6
#define reg_gpu_nodie_test_src_sel ckgen01(0x1DF8)
#define reg_gpu_nodie_test_src_sel_s 8
#define reg_gpu_nodie_test_src_sel_e 15
#define reg_gpu_shader_test_enable ckgen01(0x1DFC)
#define reg_gpu_shader_test_enable_s 0
#define reg_gpu_shader_test_enable_e 0
#define reg_gpu_shader_test_div_sel ckgen01(0x1DFC)
#define reg_gpu_shader_test_div_sel_s 4
#define reg_gpu_shader_test_div_sel_e 6
#define reg_gpu_shader_test_src_sel ckgen01(0x1DFC)
#define reg_gpu_shader_test_src_sel_s 8
#define reg_gpu_shader_test_src_sel_e 15
#define reg_hdmirx_test_enable ckgen01(0x1E00)
#define reg_hdmirx_test_enable_s 0
#define reg_hdmirx_test_enable_e 0
#define reg_hdmirx_test_div_sel ckgen01(0x1E00)
#define reg_hdmirx_test_div_sel_s 4
#define reg_hdmirx_test_div_sel_e 6
#define reg_hdmirx_test_src_sel ckgen01(0x1E00)
#define reg_hdmirx_test_src_sel_s 8
#define reg_hdmirx_test_src_sel_e 15
#define reg_ip_wrap_test_enable ckgen01(0x1E04)
#define reg_ip_wrap_test_enable_s 0
#define reg_ip_wrap_test_enable_e 0
#define reg_ip_wrap_test_div_sel ckgen01(0x1E04)
#define reg_ip_wrap_test_div_sel_s 4
#define reg_ip_wrap_test_div_sel_e 6
#define reg_ip_wrap_test_src_sel ckgen01(0x1E04)
#define reg_ip_wrap_test_src_sel_s 8
#define reg_ip_wrap_test_src_sel_e 15
#define reg_mcusys_test_enable ckgen01(0x1E08)
#define reg_mcusys_test_enable_s 0
#define reg_mcusys_test_enable_e 0
#define reg_mcusys_test_div_sel ckgen01(0x1E08)
#define reg_mcusys_test_div_sel_s 4
#define reg_mcusys_test_div_sel_e 6
#define reg_mcusys_test_src_sel ckgen01(0x1E08)
#define reg_mcusys_test_src_sel_s 8
#define reg_mcusys_test_src_sel_e 15
#define reg_mod_test_enable ckgen01(0x1E0C)
#define reg_mod_test_enable_s 0
#define reg_mod_test_enable_e 0
#define reg_mod_test_div_sel ckgen01(0x1E0C)
#define reg_mod_test_div_sel_s 4
#define reg_mod_test_div_sel_e 6
#define reg_mod_test_src_sel ckgen01(0x1E0C)
#define reg_mod_test_src_sel_s 8
#define reg_mod_test_src_sel_e 15
#define reg_mod_dot_test_enable ckgen01(0x1E10)
#define reg_mod_dot_test_enable_s 0
#define reg_mod_dot_test_enable_e 0
#define reg_mod_dot_test_div_sel ckgen01(0x1E10)
#define reg_mod_dot_test_div_sel_s 4
#define reg_mod_dot_test_div_sel_e 6
#define reg_mod_dot_test_src_sel ckgen01(0x1E10)
#define reg_mod_dot_test_src_sel_s 8
#define reg_mod_dot_test_src_sel_e 15
#define reg_lpll_test_enable ckgen01(0x1E14)
#define reg_lpll_test_enable_s 0
#define reg_lpll_test_enable_e 0
#define reg_lpll_test_div_sel ckgen01(0x1E14)
#define reg_lpll_test_div_sel_s 4
#define reg_lpll_test_div_sel_e 6
#define reg_lpll_test_src_sel ckgen01(0x1E14)
#define reg_lpll_test_src_sel_s 8
#define reg_lpll_test_src_sel_e 15
#define reg_vivaldi9_test_enable ckgen01(0x1E18)
#define reg_vivaldi9_test_enable_s 0
#define reg_vivaldi9_test_enable_e 0
#define reg_vivaldi9_test_div_sel ckgen01(0x1E18)
#define reg_vivaldi9_test_div_sel_s 4
#define reg_vivaldi9_test_div_sel_e 6
#define reg_vivaldi9_test_src_sel ckgen01(0x1E18)
#define reg_vivaldi9_test_src_sel_s 7
#define reg_vivaldi9_test_src_sel_e 15
#define reg_audio_r2_test_enable ckgen01(0x1E1C)
#define reg_audio_r2_test_enable_s 0
#define reg_audio_r2_test_enable_e 0
#define reg_audio_r2_test_div_sel ckgen01(0x1E1C)
#define reg_audio_r2_test_div_sel_s 4
#define reg_audio_r2_test_div_sel_e 6
#define reg_audio_r2_test_src_sel ckgen01(0x1E1C)
#define reg_audio_r2_test_src_sel_s 8
#define reg_audio_r2_test_src_sel_e 15
#define reg_rv55audio_test_enable ckgen01(0x1E20)
#define reg_rv55audio_test_enable_s 0
#define reg_rv55audio_test_enable_e 0
#define reg_rv55audio_test_div_sel ckgen01(0x1E20)
#define reg_rv55audio_test_div_sel_s 4
#define reg_rv55audio_test_div_sel_e 6
#define reg_rv55audio_test_src_sel ckgen01(0x1E20)
#define reg_rv55audio_test_src_sel_s 8
#define reg_rv55audio_test_src_sel_e 15
#define reg_tsp_test_enable ckgen01(0x1E24)
#define reg_tsp_test_enable_s 0
#define reg_tsp_test_enable_e 0
#define reg_tsp_test_div_sel ckgen01(0x1E24)
#define reg_tsp_test_div_sel_s 4
#define reg_tsp_test_div_sel_e 6
#define reg_tsp_test_src_sel ckgen01(0x1E24)
#define reg_tsp_test_src_sel_s 8
#define reg_tsp_test_src_sel_e 15
#define reg_frciopmrv55_test_enable ckgen01(0x1E28)
#define reg_frciopmrv55_test_enable_s 0
#define reg_frciopmrv55_test_enable_e 0
#define reg_frciopmrv55_test_div_sel ckgen01(0x1E28)
#define reg_frciopmrv55_test_div_sel_s 4
#define reg_frciopmrv55_test_div_sel_e 6
#define reg_frciopmrv55_test_src_sel ckgen01(0x1E28)
#define reg_frciopmrv55_test_src_sel_s 8
#define reg_frciopmrv55_test_src_sel_e 15
#define reg_rv55frc_test_enable ckgen01(0x1E2C)
#define reg_rv55frc_test_enable_s 0
#define reg_rv55frc_test_enable_e 0
#define reg_rv55frc_test_div_sel ckgen01(0x1E2C)
#define reg_rv55frc_test_div_sel_s 4
#define reg_rv55frc_test_div_sel_e 6
#define reg_rv55frc_test_src_sel ckgen01(0x1E2C)
#define reg_rv55frc_test_src_sel_s 8
#define reg_rv55frc_test_src_sel_e 15
#define reg_rv55pqu_test_enable ckgen01(0x1E30)
#define reg_rv55pqu_test_enable_s 0
#define reg_rv55pqu_test_enable_e 0
#define reg_rv55pqu_test_div_sel ckgen01(0x1E30)
#define reg_rv55pqu_test_div_sel_s 4
#define reg_rv55pqu_test_div_sel_e 6
#define reg_rv55pqu_test_src_sel ckgen01(0x1E30)
#define reg_rv55pqu_test_src_sel_s 8
#define reg_rv55pqu_test_src_sel_e 15
#define reg_frcmehalo_test_enable ckgen01(0x1E34)
#define reg_frcmehalo_test_enable_s 0
#define reg_frcmehalo_test_enable_e 0
#define reg_frcmehalo_test_div_sel ckgen01(0x1E34)
#define reg_frcmehalo_test_div_sel_s 4
#define reg_frcmehalo_test_div_sel_e 6
#define reg_frcmehalo_test_src_sel ckgen01(0x1E34)
#define reg_frcmehalo_test_src_sel_s 8
#define reg_frcmehalo_test_src_sel_e 15
#define reg_frcmemlb_test_enable ckgen01(0x1E38)
#define reg_frcmemlb_test_enable_s 0
#define reg_frcmemlb_test_enable_e 0
#define reg_frcmemlb_test_div_sel ckgen01(0x1E38)
#define reg_frcmemlb_test_div_sel_s 4
#define reg_frcmemlb_test_div_sel_e 6
#define reg_frcmemlb_test_src_sel ckgen01(0x1E38)
#define reg_frcmemlb_test_src_sel_s 8
#define reg_frcmemlb_test_src_sel_e 15
#define reg_frcmi_test_enable ckgen01(0x1E3C)
#define reg_frcmi_test_enable_s 0
#define reg_frcmi_test_enable_e 0
#define reg_frcmi_test_div_sel ckgen01(0x1E3C)
#define reg_frcmi_test_div_sel_s 4
#define reg_frcmi_test_div_sel_e 6
#define reg_frcmi_test_src_sel ckgen01(0x1E3C)
#define reg_frcmi_test_src_sel_s 8
#define reg_frcmi_test_src_sel_e 15
#define reg_scace_test_enable ckgen01(0x1E40)
#define reg_scace_test_enable_s 0
#define reg_scace_test_enable_e 0
#define reg_scace_test_div_sel ckgen01(0x1E40)
#define reg_scace_test_div_sel_s 4
#define reg_scace_test_div_sel_e 6
#define reg_scace_test_src_sel ckgen01(0x1E40)
#define reg_scace_test_src_sel_s 8
#define reg_scace_test_src_sel_e 15
#define reg_scdv_test_enable ckgen01(0x1E44)
#define reg_scdv_test_enable_s 0
#define reg_scdv_test_enable_e 0
#define reg_scdv_test_div_sel ckgen01(0x1E44)
#define reg_scdv_test_div_sel_s 4
#define reg_scdv_test_div_sel_e 6
#define reg_scdv_test_src_sel ckgen01(0x1E44)
#define reg_scdv_test_src_sel_s 8
#define reg_scdv_test_src_sel_e 15
#define reg_scip_test_enable ckgen01(0x1E48)
#define reg_scip_test_enable_s 0
#define reg_scip_test_enable_e 0
#define reg_scip_test_div_sel ckgen01(0x1E48)
#define reg_scip_test_div_sel_s 4
#define reg_scip_test_div_sel_e 6
#define reg_scip_test_src_sel ckgen01(0x1E48)
#define reg_scip_test_src_sel_s 8
#define reg_scip_test_src_sel_e 15
#define reg_scmw_test_enable ckgen01(0x1E4C)
#define reg_scmw_test_enable_s 0
#define reg_scmw_test_enable_e 0
#define reg_scmw_test_div_sel ckgen01(0x1E4C)
#define reg_scmw_test_div_sel_s 4
#define reg_scmw_test_div_sel_e 6
#define reg_scmw_test_src_sel ckgen01(0x1E4C)
#define reg_scmw_test_src_sel_s 8
#define reg_scmw_test_src_sel_e 15
#define reg_scnr_test_enable ckgen01(0x1E50)
#define reg_scnr_test_enable_s 0
#define reg_scnr_test_enable_e 0
#define reg_scnr_test_div_sel ckgen01(0x1E50)
#define reg_scnr_test_div_sel_s 4
#define reg_scnr_test_div_sel_e 6
#define reg_scnr_test_src_sel ckgen01(0x1E50)
#define reg_scnr_test_src_sel_s 8
#define reg_scnr_test_src_sel_e 15
#define reg_scpq_test_enable ckgen01(0x1E54)
#define reg_scpq_test_enable_s 0
#define reg_scpq_test_enable_e 0
#define reg_scpq_test_div_sel ckgen01(0x1E54)
#define reg_scpq_test_div_sel_s 4
#define reg_scpq_test_div_sel_e 6
#define reg_scpq_test_src_sel ckgen01(0x1E54)
#define reg_scpq_test_src_sel_s 8
#define reg_scpq_test_src_sel_e 15
#define reg_scscl_test_enable ckgen01(0x1E58)
#define reg_scscl_test_enable_s 0
#define reg_scscl_test_enable_e 0
#define reg_scscl_test_div_sel ckgen01(0x1E58)
#define reg_scscl_test_div_sel_s 4
#define reg_scscl_test_div_sel_e 6
#define reg_scscl_test_src_sel ckgen01(0x1E58)
#define reg_scscl_test_src_sel_s 8
#define reg_scscl_test_src_sel_e 15
#define reg_scsr_test_enable ckgen01(0x1E5C)
#define reg_scsr_test_enable_s 0
#define reg_scsr_test_enable_e 0
#define reg_scsr_test_div_sel ckgen01(0x1E5C)
#define reg_scsr_test_div_sel_s 4
#define reg_scsr_test_div_sel_e 6
#define reg_scsr_test_src_sel ckgen01(0x1E5C)
#define reg_scsr_test_src_sel_s 8
#define reg_scsr_test_src_sel_e 15
#define reg_sctcon_test_enable ckgen01(0x1E60)
#define reg_sctcon_test_enable_s 0
#define reg_sctcon_test_enable_e 0
#define reg_sctcon_test_div_sel ckgen01(0x1E60)
#define reg_sctcon_test_div_sel_s 4
#define reg_sctcon_test_div_sel_e 6
#define reg_sctcon_test_src_sel ckgen01(0x1E60)
#define reg_sctcon_test_src_sel_s 8
#define reg_sctcon_test_src_sel_e 15
#define reg_hdmirx_dphy_test_enable ckgen01(0x1E64)
#define reg_hdmirx_dphy_test_enable_s 0
#define reg_hdmirx_dphy_test_enable_e 0
#define reg_hdmirx_dphy_test_div_sel ckgen01(0x1E64)
#define reg_hdmirx_dphy_test_div_sel_s 4
#define reg_hdmirx_dphy_test_div_sel_e 6
#define reg_hdmirx_dphy_test_src_sel ckgen01(0x1E64)
#define reg_hdmirx_dphy_test_src_sel_s 8
#define reg_hdmirx_dphy_test_src_sel_e 15
#define reg_hdmirx_aphy_test_enable ckgen01(0x1E68)
#define reg_hdmirx_aphy_test_enable_s 0
#define reg_hdmirx_aphy_test_enable_e 0
#define reg_hdmirx_aphy_test_div_sel ckgen01(0x1E68)
#define reg_hdmirx_aphy_test_div_sel_s 4
#define reg_hdmirx_aphy_test_div_sel_e 6
#define reg_hdmirx_aphy_test_src_sel ckgen01(0x1E68)
#define reg_hdmirx_aphy_test_src_sel_s 8
#define reg_hdmirx_aphy_test_src_sel_e 15
#define reg_ausdm_test_enable ckgen01(0x1E6C)
#define reg_ausdm_test_enable_s 0
#define reg_ausdm_test_enable_e 0
#define reg_ausdm_test_div_sel ckgen01(0x1E6C)
#define reg_ausdm_test_div_sel_s 4
#define reg_ausdm_test_div_sel_e 6
#define reg_ausdm_test_src_sel ckgen01(0x1E6C)
#define reg_ausdm_test_src_sel_s 8
#define reg_ausdm_test_src_sel_e 15
#define reg_aur2pll_test_enable ckgen01(0x1E70)
#define reg_aur2pll_test_enable_s 0
#define reg_aur2pll_test_enable_e 0
#define reg_aur2pll_test_div_sel ckgen01(0x1E70)
#define reg_aur2pll_test_div_sel_s 4
#define reg_aur2pll_test_div_sel_e 6
#define reg_aur2pll_test_src_sel ckgen01(0x1E70)
#define reg_aur2pll_test_src_sel_s 8
#define reg_aur2pll_test_src_sel_e 15
#define reg_aupll_test_enable ckgen01(0x1E74)
#define reg_aupll_test_enable_s 0
#define reg_aupll_test_enable_e 0
#define reg_aupll_test_div_sel ckgen01(0x1E74)
#define reg_aupll_test_div_sel_s 4
#define reg_aupll_test_div_sel_e 6
#define reg_aupll_test_src_sel ckgen01(0x1E74)
#define reg_aupll_test_src_sel_s 8
#define reg_aupll_test_src_sel_e 15
#define reg_mcusys_die_test_enable ckgen01(0x1E78)
#define reg_mcusys_die_test_enable_s 0
#define reg_mcusys_die_test_enable_e 0
#define reg_mcusys_die_test_div_sel ckgen01(0x1E78)
#define reg_mcusys_die_test_div_sel_s 4
#define reg_mcusys_die_test_div_sel_e 6
#define reg_mcusys_die_test_src_sel ckgen01(0x1E78)
#define reg_mcusys_die_test_src_sel_s 8
#define reg_mcusys_die_test_src_sel_e 15
#define reg_dmd_ana_misc_test_enable ckgen01(0x1E7C)
#define reg_dmd_ana_misc_test_enable_s 0
#define reg_dmd_ana_misc_test_enable_e 0
#define reg_dmd_ana_misc_test_div_sel ckgen01(0x1E7C)
#define reg_dmd_ana_misc_test_div_sel_s 4
#define reg_dmd_ana_misc_test_div_sel_e 6
#define reg_dmd_ana_misc_test_src_sel ckgen01(0x1E7C)
#define reg_dmd_ana_misc_test_src_sel_s 8
#define reg_dmd_ana_misc_test_src_sel_e 15
#define reg_armpll_test_enable ckgen01(0x1E80)
#define reg_armpll_test_enable_s 0
#define reg_armpll_test_enable_e 0
#define reg_armpll_test_div_sel ckgen01(0x1E80)
#define reg_armpll_test_div_sel_s 4
#define reg_armpll_test_div_sel_e 6
#define reg_armpll_test_src_sel ckgen01(0x1E80)
#define reg_armpll_test_src_sel_s 8
#define reg_armpll_test_src_sel_e 15
#define reg_arm2pll_test_enable ckgen01(0x1E84)
#define reg_arm2pll_test_enable_s 0
#define reg_arm2pll_test_enable_e 0
#define reg_arm2pll_test_div_sel ckgen01(0x1E84)
#define reg_arm2pll_test_div_sel_s 4
#define reg_arm2pll_test_div_sel_e 6
#define reg_arm2pll_test_src_sel ckgen01(0x1E84)
#define reg_arm2pll_test_src_sel_s 8
#define reg_arm2pll_test_src_sel_e 15
#define reg_armpll_gpu_test_enable ckgen01(0x1E88)
#define reg_armpll_gpu_test_enable_s 0
#define reg_armpll_gpu_test_enable_e 0
#define reg_armpll_gpu_test_div_sel ckgen01(0x1E88)
#define reg_armpll_gpu_test_div_sel_s 4
#define reg_armpll_gpu_test_div_sel_e 6
#define reg_armpll_gpu_test_src_sel ckgen01(0x1E88)
#define reg_armpll_gpu_test_src_sel_s 8
#define reg_armpll_gpu_test_src_sel_e 15
#define reg_armpll_apu_test_enable ckgen01(0x1E8C)
#define reg_armpll_apu_test_enable_s 0
#define reg_armpll_apu_test_enable_e 0
#define reg_armpll_apu_test_div_sel ckgen01(0x1E8C)
#define reg_armpll_apu_test_div_sel_s 4
#define reg_armpll_apu_test_div_sel_e 6
#define reg_armpll_apu_test_src_sel ckgen01(0x1E8C)
#define reg_armpll_apu_test_src_sel_s 8
#define reg_armpll_apu_test_src_sel_e 15
#define reg_earc_dmacro_test_enable ckgen01(0x1E90)
#define reg_earc_dmacro_test_enable_s 0
#define reg_earc_dmacro_test_enable_e 0
#define reg_earc_dmacro_test_div_sel ckgen01(0x1E90)
#define reg_earc_dmacro_test_div_sel_s 4
#define reg_earc_dmacro_test_div_sel_e 6
#define reg_earc_dmacro_test_src_sel ckgen01(0x1E90)
#define reg_earc_dmacro_test_src_sel_s 8
#define reg_earc_dmacro_test_src_sel_e 15
#define reg_usb_phy_test_enable ckgen01(0x1E94)
#define reg_usb_phy_test_enable_s 0
#define reg_usb_phy_test_enable_e 0
#define reg_usb_phy_test_div_sel ckgen01(0x1E94)
#define reg_usb_phy_test_div_sel_s 4
#define reg_usb_phy_test_div_sel_e 6
#define reg_usb_phy_test_src_sel ckgen01(0x1E94)
#define reg_usb_phy_test_src_sel_s 8
#define reg_usb_phy_test_src_sel_e 15
#define reg_pcie_phy_test_enable ckgen01(0x1E98)
#define reg_pcie_phy_test_enable_s 0
#define reg_pcie_phy_test_enable_e 0
#define reg_pcie_phy_test_div_sel ckgen01(0x1E98)
#define reg_pcie_phy_test_div_sel_s 4
#define reg_pcie_phy_test_div_sel_e 6
#define reg_pcie_phy_test_src_sel ckgen01(0x1E98)
#define reg_pcie_phy_test_src_sel_s 8
#define reg_pcie_phy_test_src_sel_e 15
#define reg_ufs_phy_test_enable ckgen01(0x1E9C)
#define reg_ufs_phy_test_enable_s 0
#define reg_ufs_phy_test_enable_e 0
#define reg_ufs_phy_test_div_sel ckgen01(0x1E9C)
#define reg_ufs_phy_test_div_sel_s 4
#define reg_ufs_phy_test_div_sel_e 6
#define reg_ufs_phy_test_src_sel ckgen01(0x1E9C)
#define reg_ufs_phy_test_src_sel_s 8
#define reg_ufs_phy_test_src_sel_e 15
#define reg_flash_dmacro_test_enable ckgen01(0x1EA0)
#define reg_flash_dmacro_test_enable_s 0
#define reg_flash_dmacro_test_enable_e 0
#define reg_flash_dmacro_test_div_sel ckgen01(0x1EA0)
#define reg_flash_dmacro_test_div_sel_s 4
#define reg_flash_dmacro_test_div_sel_e 6
#define reg_flash_dmacro_test_src_sel ckgen01(0x1EA0)
#define reg_flash_dmacro_test_src_sel_s 8
#define reg_flash_dmacro_test_src_sel_e 15
#define reg_flash_32bif_test_enable ckgen01(0x1EA4)
#define reg_flash_32bif_test_enable_s 0
#define reg_flash_32bif_test_enable_e 0
#define reg_flash_32bif_test_div_sel ckgen01(0x1EA4)
#define reg_flash_32bif_test_div_sel_s 4
#define reg_flash_32bif_test_div_sel_e 6
#define reg_flash_32bif_test_src_sel ckgen01(0x1EA4)
#define reg_flash_32bif_test_src_sel_s 8
#define reg_flash_32bif_test_src_sel_e 15
#define reg_flash_8bit_test_enable ckgen01(0x1EA8)
#define reg_flash_8bit_test_enable_s 0
#define reg_flash_8bit_test_enable_e 0
#define reg_flash_8bit_test_div_sel ckgen01(0x1EA8)
#define reg_flash_8bit_test_div_sel_s 4
#define reg_flash_8bit_test_div_sel_e 6
#define reg_flash_8bit_test_src_sel ckgen01(0x1EA8)
#define reg_flash_8bit_test_src_sel_s 8
#define reg_flash_8bit_test_src_sel_e 15
#define reg_sd_sdr_macro_test_enable ckgen01(0x1EAC)
#define reg_sd_sdr_macro_test_enable_s 0
#define reg_sd_sdr_macro_test_enable_e 0
#define reg_sd_sdr_macro_test_div_sel ckgen01(0x1EAC)
#define reg_sd_sdr_macro_test_div_sel_s 4
#define reg_sd_sdr_macro_test_div_sel_e 6
#define reg_sd_sdr_macro_test_src_sel ckgen01(0x1EAC)
#define reg_sd_sdr_macro_test_src_sel_s 8
#define reg_sd_sdr_macro_test_src_sel_e 15
#define reg_vdecpll_dmacro_test_enable ckgen01(0x1EB0)
#define reg_vdecpll_dmacro_test_enable_s 0
#define reg_vdecpll_dmacro_test_enable_e 0
#define reg_vdecpll_dmacro_test_div_sel ckgen01(0x1EB0)
#define reg_vdecpll_dmacro_test_div_sel_s 4
#define reg_vdecpll_dmacro_test_div_sel_e 6
#define reg_vdecpll_dmacro_test_src_sel ckgen01(0x1EB0)
#define reg_vdecpll_dmacro_test_src_sel_s 8
#define reg_vdecpll_dmacro_test_src_sel_e 15
#define reg_sys0pll_dmacro_test_enable ckgen01(0x1EB4)
#define reg_sys0pll_dmacro_test_enable_s 0
#define reg_sys0pll_dmacro_test_enable_e 0
#define reg_sys0pll_dmacro_test_div_sel ckgen01(0x1EB4)
#define reg_sys0pll_dmacro_test_div_sel_s 4
#define reg_sys0pll_dmacro_test_div_sel_e 6
#define reg_sys0pll_dmacro_test_src_sel ckgen01(0x1EB4)
#define reg_sys0pll_dmacro_test_src_sel_s 8
#define reg_sys0pll_dmacro_test_src_sel_e 15
#define reg_sys1pll_dmacro_test_enable ckgen01(0x1EB8)
#define reg_sys1pll_dmacro_test_enable_s 0
#define reg_sys1pll_dmacro_test_enable_e 0
#define reg_sys1pll_dmacro_test_div_sel ckgen01(0x1EB8)
#define reg_sys1pll_dmacro_test_div_sel_s 4
#define reg_sys1pll_dmacro_test_div_sel_e 6
#define reg_sys1pll_dmacro_test_src_sel ckgen01(0x1EB8)
#define reg_sys1pll_dmacro_test_src_sel_s 8
#define reg_sys1pll_dmacro_test_src_sel_e 15
#define reg_sys2pll_dmacro_test_enable ckgen01(0x1EBC)
#define reg_sys2pll_dmacro_test_enable_s 0
#define reg_sys2pll_dmacro_test_enable_e 0
#define reg_sys2pll_dmacro_test_div_sel ckgen01(0x1EBC)
#define reg_sys2pll_dmacro_test_div_sel_s 4
#define reg_sys2pll_dmacro_test_div_sel_e 6
#define reg_sys2pll_dmacro_test_src_sel ckgen01(0x1EBC)
#define reg_sys2pll_dmacro_test_src_sel_s 8
#define reg_sys2pll_dmacro_test_src_sel_e 15
#define reg_rv55frcpll_dmacro_test_enable ckgen01(0x1EC0)
#define reg_rv55frcpll_dmacro_test_enable_s 0
#define reg_rv55frcpll_dmacro_test_enable_e 0
#define reg_rv55frcpll_dmacro_test_div_sel ckgen01(0x1EC0)
#define reg_rv55frcpll_dmacro_test_div_sel_s 4
#define reg_rv55frcpll_dmacro_test_div_sel_e 6
#define reg_rv55frcpll_dmacro_test_src_sel ckgen01(0x1EC0)
#define reg_rv55frcpll_dmacro_test_src_sel_s 8
#define reg_rv55frcpll_dmacro_test_src_sel_e 15
#define reg_xcpll_dmacro_test_enable ckgen01(0x1EC4)
#define reg_xcpll_dmacro_test_enable_s 0
#define reg_xcpll_dmacro_test_enable_e 0
#define reg_xcpll_dmacro_test_div_sel ckgen01(0x1EC4)
#define reg_xcpll_dmacro_test_div_sel_s 4
#define reg_xcpll_dmacro_test_div_sel_e 6
#define reg_xcpll_dmacro_test_src_sel ckgen01(0x1EC4)
#define reg_xcpll_dmacro_test_src_sel_s 8
#define reg_xcpll_dmacro_test_src_sel_e 15
#define reg_xcsrspll_dmacro_test_enable ckgen01(0x1EC8)
#define reg_xcsrspll_dmacro_test_enable_s 0
#define reg_xcsrspll_dmacro_test_enable_e 0
#define reg_xcsrspll_dmacro_test_div_sel ckgen01(0x1EC8)
#define reg_xcsrspll_dmacro_test_div_sel_s 4
#define reg_xcsrspll_dmacro_test_div_sel_e 6
#define reg_xcsrspll_dmacro_test_src_sel ckgen01(0x1EC8)
#define reg_xcsrspll_dmacro_test_src_sel_s 8
#define reg_xcsrspll_dmacro_test_src_sel_e 15
#define reg_sys3pll_dmacro_test_enable ckgen01(0x1ECC)
#define reg_sys3pll_dmacro_test_enable_s 0
#define reg_sys3pll_dmacro_test_enable_e 0
#define reg_sys3pll_dmacro_test_div_sel ckgen01(0x1ECC)
#define reg_sys3pll_dmacro_test_div_sel_s 4
#define reg_sys3pll_dmacro_test_div_sel_e 6
#define reg_sys3pll_dmacro_test_src_sel ckgen01(0x1ECC)
#define reg_sys3pll_dmacro_test_src_sel_s 8
#define reg_sys3pll_dmacro_test_src_sel_e 15
#define reg_gpubrdgpll_dmacro_test_enable ckgen01(0x1ED0)
#define reg_gpubrdgpll_dmacro_test_enable_s 0
#define reg_gpubrdgpll_dmacro_test_enable_e 0
#define reg_gpubrdgpll_dmacro_test_div_sel ckgen01(0x1ED0)
#define reg_gpubrdgpll_dmacro_test_div_sel_s 4
#define reg_gpubrdgpll_dmacro_test_div_sel_e 6
#define reg_gpubrdgpll_dmacro_test_src_sel ckgen01(0x1ED0)
#define reg_gpubrdgpll_dmacro_test_src_sel_s 8
#define reg_gpubrdgpll_dmacro_test_src_sel_e 15
#define reg_apubuspll_dmacro_test_enable ckgen01(0x1ED4)
#define reg_apubuspll_dmacro_test_enable_s 0
#define reg_apubuspll_dmacro_test_enable_e 0
#define reg_apubuspll_dmacro_test_div_sel ckgen01(0x1ED4)
#define reg_apubuspll_dmacro_test_div_sel_s 4
#define reg_apubuspll_dmacro_test_div_sel_e 6
#define reg_apubuspll_dmacro_test_src_sel ckgen01(0x1ED4)
#define reg_apubuspll_dmacro_test_src_sel_s 8
#define reg_apubuspll_dmacro_test_src_sel_e 15
#define reg_sw_en_calc2test_clk_calculate ckgen01(0x1F88)
#define reg_sw_en_calc2test_clk_calculate_s 0
#define reg_sw_en_calc2test_clk_calculate_e 0
#define reg_sw_en_riu_dmd2riu_dft_demod1 ckgen01(0x1F90)
#define reg_sw_en_riu_dmd2riu_dft_demod1_s 0
#define reg_sw_en_riu_dmd2riu_dft_demod1_e 0
#define reg_sw_en_riu_au2riu_dft_au_audio_r2 ckgen01(0x1F94)
#define reg_sw_en_riu_au2riu_dft_au_audio_r2_s 0
#define reg_sw_en_riu_au2riu_dft_au_audio_r2_e 0
#define reg_sw_en_riu_au2riu_dft_au_rv55audio ckgen01(0x1F94)
#define reg_sw_en_riu_au2riu_dft_au_rv55audio_s 1
#define reg_sw_en_riu_au2riu_dft_au_rv55audio_e 1
#define reg_sw_en_riu_hdmi2riu_dft_hdmi_hdmirx_dphy ckgen01(0x1F98)
#define reg_sw_en_riu_hdmi2riu_dft_hdmi_hdmirx_dphy_s 0
#define reg_sw_en_riu_hdmi2riu_dft_hdmi_hdmirx_dphy_e 0
#define reg_sw_en_riu_hdmi2riu_dft_hdmi_hdmirx_aphy ckgen01(0x1F98)
#define reg_sw_en_riu_hdmi2riu_dft_hdmi_hdmirx_aphy_s 1
#define reg_sw_en_riu_hdmi2riu_dft_hdmi_hdmirx_aphy_e 1
#define reg_sw_en_riu_xc2riu_dft_xc_scace ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scace_s 0
#define reg_sw_en_riu_xc2riu_dft_xc_scace_e 0
#define reg_sw_en_riu_xc2riu_dft_xc_scdv ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scdv_s 1
#define reg_sw_en_riu_xc2riu_dft_xc_scdv_e 1
#define reg_sw_en_riu_xc2riu_dft_xc_scip ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scip_s 2
#define reg_sw_en_riu_xc2riu_dft_xc_scip_e 2
#define reg_sw_en_riu_xc2riu_dft_xc_scmw ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scmw_s 3
#define reg_sw_en_riu_xc2riu_dft_xc_scmw_e 3
#define reg_sw_en_riu_xc2riu_dft_xc_scnr ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scnr_s 4
#define reg_sw_en_riu_xc2riu_dft_xc_scnr_e 4
#define reg_sw_en_riu_xc2riu_dft_xc_scpq ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scpq_s 5
#define reg_sw_en_riu_xc2riu_dft_xc_scpq_e 5
#define reg_sw_en_riu_xc2riu_dft_xc_scsr ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_scsr_s 6
#define reg_sw_en_riu_xc2riu_dft_xc_scsr_e 6
#define reg_sw_en_riu_xc2riu_dft_xc_sctcon ckgen01(0x1FA8)
#define reg_sw_en_riu_xc2riu_dft_xc_sctcon_s 7
#define reg_sw_en_riu_xc2riu_dft_xc_sctcon_e 7
#define reg_sw_en_riu_frc2riu_dft_frc_rv55frc ckgen01(0x1FB4)
#define reg_sw_en_riu_frc2riu_dft_frc_rv55frc_s 0
#define reg_sw_en_riu_frc2riu_dft_frc_rv55frc_e 0
#define reg_sw_en_riu_frc2riu_dft_frc_rv55pqu ckgen01(0x1FB4)
#define reg_sw_en_riu_frc2riu_dft_frc_rv55pqu_s 1
#define reg_sw_en_riu_frc2riu_dft_frc_rv55pqu_e 1
#define reg_sw_en_riu_frc2riu_dft_frc_frcmehalo ckgen01(0x1FB4)
#define reg_sw_en_riu_frc2riu_dft_frc_frcmehalo_s 2
#define reg_sw_en_riu_frc2riu_dft_frc_frcmehalo_e 2
#define reg_sw_en_riu_frc2riu_dft_frc_frcmemlb ckgen01(0x1FB4)
#define reg_sw_en_riu_frc2riu_dft_frc_frcmemlb_s 3
#define reg_sw_en_riu_frc2riu_dft_frc_frcmemlb_e 3
#define reg_sw_en_riu_frc2riu_dft_frc_frcmi ckgen01(0x1FB4)
#define reg_sw_en_riu_frc2riu_dft_frc_frcmi_s 4
#define reg_sw_en_riu_frc2riu_dft_frc_frcmi_e 4
#define reg_sw_en_riu_nonpm2riu_dft_adc ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_adc_s 0
#define reg_sw_en_riu_nonpm2riu_dft_adc_e 0
#define reg_sw_en_riu_nonpm2riu_dft_aia ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_aia_s 1
#define reg_sw_en_riu_nonpm2riu_dft_aia_e 1
#define reg_sw_en_riu_nonpm2riu_dft_demod0 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_demod0_s 2
#define reg_sw_en_riu_nonpm2riu_dft_demod0_e 2
#define reg_sw_en_riu_nonpm2riu_dft_demod1 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_demod1_s 3
#define reg_sw_en_riu_nonpm2riu_dft_demod1_e 3
#define reg_sw_en_riu_nonpm2riu_dft_vdec_soc ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_vdec_soc_s 4
#define reg_sw_en_riu_nonpm2riu_dft_vdec_soc_e 4
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core0 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core0_s 5
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core0_e 5
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core1 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core1_s 6
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core1_e 6
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core2 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core2_s 7
#define reg_sw_en_riu_nonpm2riu_dft_vdec_core2_e 7
#define reg_sw_en_riu_nonpm2riu_dft_dramc0 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_dramc0_s 8
#define reg_sw_en_riu_nonpm2riu_dft_dramc0_e 8
#define reg_sw_en_riu_nonpm2riu_dft_dramc1 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_dramc1_s 9
#define reg_sw_en_riu_nonpm2riu_dft_dramc1_e 9
#define reg_sw_en_riu_nonpm2riu_dft_dramc2 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_dramc2_s 10
#define reg_sw_en_riu_nonpm2riu_dft_dramc2_e 10
#define reg_sw_en_riu_nonpm2riu_dft_mheg5 ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_mheg5_s 11
#define reg_sw_en_riu_nonpm2riu_dft_mheg5_e 11
#define reg_sw_en_riu_nonpm2riu_dft_gpu_nodie ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_gpu_nodie_s 12
#define reg_sw_en_riu_nonpm2riu_dft_gpu_nodie_e 12
#define reg_sw_en_riu_nonpm2riu_dft_hdmirx ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_hdmirx_s 13
#define reg_sw_en_riu_nonpm2riu_dft_hdmirx_e 13
#define reg_sw_en_riu_nonpm2riu_dft_ip_wrap ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_ip_wrap_s 14
#define reg_sw_en_riu_nonpm2riu_dft_ip_wrap_e 14
#define reg_sw_en_riu_nonpm2riu_dft_mcusys ckgen01(0x1FC0)
#define reg_sw_en_riu_nonpm2riu_dft_mcusys_s 15
#define reg_sw_en_riu_nonpm2riu_dft_mcusys_e 15
#define reg_sw_en_riu_nonpm2riu_dft_mod ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_mod_s 0
#define reg_sw_en_riu_nonpm2riu_dft_mod_e 0
#define reg_sw_en_viva_riu2riu_dft_vivaldi9 ckgen01(0x1FC4)
#define reg_sw_en_viva_riu2riu_dft_vivaldi9_s 1
#define reg_sw_en_viva_riu2riu_dft_vivaldi9_e 1
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_audio_r2 ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_audio_r2_s 2
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_audio_r2_e 2
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55audio ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55audio_s 3
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55audio_e 3
#define reg_sw_en_riu_nonpm2riu_dft_tsp ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_tsp_s 4
#define reg_sw_en_riu_nonpm2riu_dft_tsp_e 4
#define reg_sw_en_riu_nonpm2riu_dft_frciopmrv55 ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_frciopmrv55_s 5
#define reg_sw_en_riu_nonpm2riu_dft_frciopmrv55_e 5
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55frc ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55frc_s 6
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55frc_e 6
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55pqu ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55pqu_s 7
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_rv55pqu_e 7
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmehalo ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmehalo_s 8
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmehalo_e 8
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmemlb ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmemlb_s 9
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmemlb_e 9
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmi ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmi_s 10
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_frcmi_e 10
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scace ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scace_s 11
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scace_e 11
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scdv ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scdv_s 12
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scdv_e 12
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scip ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scip_s 13
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scip_e 13
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scmw ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scmw_s 14
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scmw_e 14
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scnr ckgen01(0x1FC4)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scnr_s 15
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scnr_e 15
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scpq ckgen01(0x1FC8)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scpq_s 0
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scpq_e 0
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scscl ckgen01(0x1FC8)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scscl_s 1
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scscl_e 1
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scsr ckgen01(0x1FC8)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scsr_s 2
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_scsr_e 2
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_sctcon ckgen01(0x1FC8)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_sctcon_s 3
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_sctcon_e 3
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_hdmirx_dphy ckgen01(0x1FC8)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_hdmirx_dphy_s 4
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_hdmirx_dphy_e 4
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_hdmirx_aphy ckgen01(0x1FC8)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_hdmirx_aphy_s 5
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_hdmirx_aphy_e 5
#define reg_ckg_occ_src_for_test_div ckgen01(0x1FE8)
#define reg_ckg_occ_src_for_test_div_s 0
#define reg_ckg_occ_src_for_test_div_e 1
#define reg_sw_en_occ_src_for_test_div2test_ctrl_wp ckgen01(0x1FEC)
#define reg_sw_en_occ_src_for_test_div2test_ctrl_wp_s 0
#define reg_sw_en_occ_src_for_test_div2test_ctrl_wp_e 0
#define reg_ckgen01_dummy0 ckgen01(0x1FF0)
#define reg_ckgen01_dummy0_s 0
#define reg_ckgen01_dummy0_e 15
#define reg_ckgen01_dummy1 ckgen01(0x1FF4)
#define reg_ckgen01_dummy1_s 0
#define reg_ckgen01_dummy1_e 15
#define reg_ckgen01_dummy2 ckgen01(0x1FF8)
#define reg_ckgen01_dummy2_s 0
#define reg_ckgen01_dummy2_e 15
#define reg_ckgen01_dummy3 ckgen01(0x1FFC)
#define reg_ckgen01_dummy3_s 0
#define reg_ckgen01_dummy3_e 15

#endif
