/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#define AU_VIVA_XTAL_12M_INT_CK	1
#define AU_VIVA_XTAL_24M_INT_CK	2
#define AU_MCU_NONPM_INT_CK	3
#define AU_AU_UART0_INT_CK	5
#define AU_VIVA_SMI_INT_CK	6
#define AU_VIVA_RIU_INT_CK	9
#define AU_VIVA_RIU_BRG_R2_INT_CK	10
#define AU_VIVA_RIU_R2_INT_CK	11
#define AU_VIVA_AU_RIU_INT_CK	12
#define AU_VIVA_AU_MCU_INT_CK	13
#define AU_AU_MCU_BUS_INT_CK	14
#define AU_VIVA_R2_WB_MUX_INT_CK	15
#define AU_VIVA_R2_WB_INT_CK	16
#define AU_VIVA_SYNTH_CODEC_INT_CK	17
#define AU_VIVA_SYNTH_2ND_ORDER_INT_CK	18
#define AU_VIVA_AUPLL_IN_INT_CK	19
#define AU_VIVA_DSP_INT_CK	20
#define AU_VIVA_SIF_ADC_R2B_FIFO_IN_INT_CK	21
#define AU_VIVA_SIF_ADC_R2B_INT_CK	22
#define AU_VIVA_SIF_ADC_CIC_INT_CK	23
#define AU_VIVA_FM_DEMODULATOR_INT_CK	24
#define AU_VIVA_SIF_SYNTH_INT_CK	25
#define AU_VIVA_SIF_CORDIC_INT_CK	26
#define AU_VIVA_PARSER_INT_CK	27
#define AU_VIVA_GPA_480FSO_INT_CK	28
#define AU_VIVA_GPA_240FSO_INT_CK	29
#define AU_VIVA_GPA_256FSO_INT_CK	30
#define AU_VIVA_ADC_512FS_INT_CK	31
#define AU_VIVA_DAC_512FS_INT_CK	32
#define AU_VIVA_AB_MAC_INT_CK	33
#define AU_VIVA_AB3_MAC_INT_CK	34
#define AU_VIVA_SH_INT_CK	35
#define AU_VIVA_CODEC_SH_INT_CK	36
#define AU_PCM_I2S_256FS_MUX_INT_CK	37
#define AU_CH_M1_256FSI_MUX1_INT_CK	39
#define AU_CH_M1_256FSI_MUX0_INT_CK	40
#define AU_CH_M1_256FSI_MUX_INT_CK	41
#define AU_VIVA_CH_M1_256FSI_INT_CK	42
#define AU_CH_M2_256FSI_MUX1_INT_CK	44
#define AU_CH_M2_256FSI_MUX0_INT_CK	45
#define AU_CH_M2_256FSI_MUX_INT_CK	46
#define AU_VIVA_CH_M2_256FSI_INT_CK	47
#define AU_CH_M3_256FSI_MUX1_INT_CK	49
#define AU_CH_M3_256FSI_MUX0_INT_CK	50
#define AU_CH_M3_256FSI_MUX_INT_CK	51
#define AU_VIVA_CH_M3_256FSI_INT_CK	52
#define AU_CH_M4_256FSI_MUX1_INT_CK	54
#define AU_CH_M4_256FSI_MUX0_INT_CK	55
#define AU_CH_M4_256FSI_MUX_INT_CK	56
#define AU_VIVA_CH_M4_256FSI_INT_CK	57
#define AU_CH_M5_256FSI_MUX1_INT_CK	59
#define AU_CH_M5_256FSI_MUX0_INT_CK	60
#define AU_CH_M5_256FSI_MUX_INT_CK	61
#define AU_VIVA_CH_M5_256FSI_INT_CK	62
#define AU_CH_M6_256FSI_MUX1_INT_CK	64
#define AU_CH_M6_256FSI_MUX0_INT_CK	65
#define AU_CH_M6_256FSI_MUX_INT_CK	66
#define AU_VIVA_CH_M6_256FSI_INT_CK	67
#define AU_CH_M7_256FSI_MUX1_INT_CK	69
#define AU_CH_M7_256FSI_MUX0_INT_CK	70
#define AU_CH_M7_256FSI_MUX_INT_CK	71
#define AU_VIVA_CH_M7_256FSI_INT_CK	72
#define AU_CH_M8_256FSI_MUX1_INT_CK	74
#define AU_CH_M8_256FSI_MUX0_INT_CK	75
#define AU_CH_M8_256FSI_MUX_INT_CK	76
#define AU_VIVA_CH_M8_256FSI_INT_CK	77
#define AU_CH_M9_256FSI_MUX1_INT_CK	79
#define AU_CH_M9_256FSI_MUX0_INT_CK	80
#define AU_CH_M9_256FSI_MUX_INT_CK	81
#define AU_VIVA_CH_M9_256FSI_INT_CK	82
#define AU_CH_M10_256FSI_MUX1_INT_CK	84
#define AU_CH_M10_256FSI_MUX0_INT_CK	85
#define AU_CH_M10_256FSI_MUX_INT_CK	86
#define AU_VIVA_CH_M10_256FSI_INT_CK	87
#define AU_CH_M11_256FSI_MUX1_INT_CK	89
#define AU_CH_M11_256FSI_MUX0_INT_CK	90
#define AU_CH_M11_256FSI_MUX_INT_CK	91
#define AU_VIVA_CH_M11_256FSI_INT_CK	92
#define AU_CH_M12_256FSI_MUX1_INT_CK	94
#define AU_CH_M12_256FSI_MUX0_INT_CK	95
#define AU_CH_M12_256FSI_MUX_INT_CK	96
#define AU_VIVA_CH_M12_256FSI_INT_CK	97
#define AU_CH_M13_256FSI_MUX1_INT_CK	99
#define AU_CH_M13_256FSI_MUX0_INT_CK	100
#define AU_CH_M13_256FSI_MUX_INT_CK	101
#define AU_VIVA_CH_M13_256FSI_INT_CK	102
#define AU_CH_M14_256FSI_MUX1_INT_CK	104
#define AU_CH_M14_256FSI_MUX0_INT_CK	105
#define AU_CH_M14_256FSI_MUX_INT_CK	106
#define AU_VIVA_CH_M14_256FSI_INT_CK	107
#define AU_CH_M15_256FSI_MUX1_INT_CK	109
#define AU_CH_M15_256FSI_MUX0_INT_CK	110
#define AU_CH_M15_256FSI_MUX_INT_CK	111
#define AU_VIVA_CH_M15_256FSI_INT_CK	112
#define AU_CH_M16_256FSI_MUX1_INT_CK	114
#define AU_CH_M16_256FSI_MUX0_INT_CK	115
#define AU_CH_M16_256FSI_MUX_INT_CK	116
#define AU_VIVA_CH_M16_256FSI_INT_CK	117
#define AU_CH5_256FSI_MUX2_INT_CK	119
#define AU_CH5_256FSI_MUX1_INT_CK	120
#define AU_CH5_256FSI_MUX0_INT_CK	121
#define AU_CH5_256FSI_MUX_INT_CK	122
#define AU_VIVA_CH5_256FSI_INT_CK	123
#define AU_CH6_256FSI_MUX2_INT_CK	124
#define AU_CH6_256FSI_MUX1_INT_CK	125
#define AU_CH6_256FSI_MUX0_INT_CK	126
#define AU_CH6_256FSI_MUX_INT_CK	127
#define AU_VIVA_CH6_256FSI_INT_CK	128
#define AU_CH7_256FSI_MUX2_INT_CK	129
#define AU_CH7_256FSI_MUX1_INT_CK	130
#define AU_CH7_256FSI_MUX0_INT_CK	131
#define AU_CH7_256FSI_MUX_INT_CK	132
#define AU_VIVA_CH7_256FSI_INT_CK	133
#define AU_CH8_256FSI_MUX2_INT_CK	134
#define AU_CH8_256FSI_MUX1_INT_CK	135
#define AU_CH8_256FSI_MUX0_INT_CK	136
#define AU_CH8_256FSI_MUX_INT_CK	137
#define AU_VIVA_CH8_256FSI_INT_CK	138
#define AU_CH9_256FSI_MUX2_INT_CK	139
#define AU_CH9_256FSI_MUX1_INT_CK	140
#define AU_CH9_256FSI_MUX0_INT_CK	141
#define AU_CH9_256FSI_MUX_INT_CK	142
#define AU_VIVA_CH9_256FSI_INT_CK	143
#define AU_CH10_256FSI_MUX2_INT_CK	144
#define AU_CH10_256FSI_MUX1_INT_CK	145
#define AU_CH10_256FSI_MUX0_INT_CK	146
#define AU_CH10_256FSI_MUX_INT_CK	147
#define AU_VIVA_CH10_256FSI_INT_CK	148
#define AU_VIVA_DVB1_SYNTH_REF_INT_CK	150
#define AU_DECODER1_SYNTH_HDMI_CTSN_256FS_DIV_MUX_INT_CK	151
#define AU_DECODER1_SYNTH_HDMI_CTSN_128FS_DIV_MUX_INT_CK	152
#define AU_DECODER1_SYNTH_HDMI2_CTSN_256FS_DIV_MUX_INT_CK	153
#define AU_DECODER1_SYNTH_HDMI2_CTSN_128FS_DIV_MUX_INT_CK	154
#define AU_DECODER1_SYNTH_SPDIF_CDR_256FS_DIV_MUX_INT_CK	155
#define AU_DECODER1_SYNTH_SPDIF_CDR_128FS_DIV_MUX_INT_CK	156
#define AU_DECODER1_256FS_MUX0_INT_CK	157
#define AU_DECODER1_256FS_MUX1_INT_CK	158
#define AU_DECODER1_256FS_MUX_INT_CK	159
#define AU_VIVA_DVB1_TIMING_GEN_256FS_INT_CK	160
#define AU_DECODER1_128FS_MUX0_INT_CK	161
#define AU_DECODER1_128FS_MUX1_INT_CK	162
#define AU_DECODER1_128FS_MUX_INT_CK	163
#define AU_VIVA_DVB2_SYNTH_REF_INT_CK	165
#define AU_DECODER2_SYNTH_HDMI_CTSN_256FS_DIV_MUX_INT_CK	166
#define AU_DECODER2_SYNTH_HDMI_CTSN_128FS_DIV_MUX_INT_CK	167
#define AU_DECODER2_SYNTH_HDMI2_CTSN_256FS_DIV_MUX_INT_CK	168
#define AU_DECODER2_SYNTH_HDMI2_CTSN_128FS_DIV_MUX_INT_CK	169
#define AU_DECODER2_SYNTH_SPDIF_CDR_256FS_DIV_MUX_INT_CK	170
#define AU_DECODER2_SYNTH_SPDIF_CDR_128FS_DIV_MUX_INT_CK	171
#define AU_DECODER2_256FS_MUX0_INT_CK	172
#define AU_DECODER2_256FS_MUX1_INT_CK	173
#define AU_DECODER2_256FS_MUX_INT_CK	174
#define AU_VIVA_DVB2_TIMING_GEN_256FS_INT_CK	175
#define AU_DECODER2_128FS_MUX0_INT_CK	176
#define AU_DECODER2_128FS_MUX1_INT_CK	177
#define AU_DECODER2_128FS_MUX_INT_CK	178
#define AU_VIVA_DVB3_SYNTH_REF_INT_CK	179
#define AU_DECODER3_SYNTH_HDMI_CTSN_256FS_DIV_MUX_INT_CK	180
#define AU_DECODER3_SYNTH_HDMI_CTSN_128FS_DIV_MUX_INT_CK	181
#define AU_DECODER3_SYNTH_HDMI2_CTSN_256FS_DIV_MUX_INT_CK	182
#define AU_DECODER3_SYNTH_HDMI2_CTSN_128FS_DIV_MUX_INT_CK	183
#define AU_DECODER3_SYNTH_SPDIF_CDR_256FS_DIV_MUX_INT_CK	184
#define AU_DECODER3_SYNTH_SPDIF_CDR_128FS_DIV_MUX_INT_CK	185
#define AU_DECODER3_256FS_MUX0_INT_CK	186
#define AU_DECODER3_256FS_MUX1_INT_CK	187
#define AU_DECODER3_256FS_MUX_INT_CK	188
#define AU_VIVA_DVB3_TIMING_GEN_256FS_INT_CK	189
#define AU_DECODER3_128FS_MUX0_INT_CK	190
#define AU_DECODER3_128FS_MUX1_INT_CK	191
#define AU_DECODER3_128FS_MUX_INT_CK	192
#define AU_VIVA_DVB4_SYNTH_REF_INT_CK	193
#define AU_DECODER4_SYNTH_HDMI_CTSN_256FS_DIV_MUX_INT_CK	194
#define AU_DECODER4_SYNTH_HDMI_CTSN_128FS_DIV_MUX_INT_CK	195
#define AU_DECODER4_SYNTH_HDMI2_CTSN_256FS_DIV_MUX_INT_CK	196
#define AU_DECODER4_SYNTH_HDMI2_CTSN_128FS_DIV_MUX_INT_CK	197
#define AU_DECODER4_SYNTH_SPDIF_CDR_256FS_DIV_MUX_INT_CK	198
#define AU_DECODER4_SYNTH_SPDIF_CDR_128FS_DIV_MUX_INT_CK	199
#define AU_DECODER4_256FS_MUX0_INT_CK	200
#define AU_DECODER4_256FS_MUX1_INT_CK	201
#define AU_DECODER4_256FS_MUX_INT_CK	202
#define AU_VIVA_DVB4_TIMING_GEN_256FS_INT_CK	203
#define AU_DECODER4_128FS_MUX0_INT_CK	204
#define AU_DECODER4_128FS_MUX1_INT_CK	205
#define AU_DECODER4_128FS_MUX_INT_CK	206
#define AU_VIVA_DVB5_TIMING_GEN_256FS_INT_CK	207
#define AU_VIVA_DVB6_TIMING_GEN_256FS_INT_CK	208
#define AU_VIVA_AUDMA_V2_R1_SYNTH_REF_INT_CK	209
#define AU_VIVA_AUDMA_V2_R1_256FS_MUX_INT_CK	210
#define AU_VIVA_AUDMA_V2_R1_256FS_INT_CK	211
#define AU_VIVA_AUDMA_V2_R2_SYNTH_REF_INT_CK	212
#define AU_VIVA_AUDMA_V2_R2_256FS_INT_CK	213
#define AU_VIVA_SPDIF_RX_128FS_INT_CK	214
#define AU_VIVA_SPDIF_RX_DG_INT_CK	215
#define AU_VIVA_SPDIF_RX_SYNTH_REF_INT_CK	216
#define AU_VIVA_HDMI_RX_SYNTH_REF_INT_CK	217
#define AU_HDMI_RX_S2P_256FS_MUX_INT_CK	218
#define AU_VIVA_HDMI_RX_S2P_256FS_INT_CK	219
#define AU_HDMI_RX_S2P_128FS_MUX_INT_CK	220
#define AU_VIVA_HDMI_RX_S2P_128FS_INT_CK	221
#define AU_VIVA_HDMI_RX_V2A_TIME_STAMP_INT_CK	222
#define AU_VIVA_HDMI_RX_MPLL_432_INT_CK	223
#define AU_VIVA_HDMI_RX2_SYNTH_REF_INT_CK	224
#define AU_HDMI_RX2_S2P_256FS_MUX_INT_CK	225
#define AU_VIVA_HDMI_RX2_S2P_256FS_INT_CK	226
#define AU_HDMI_RX2_S2P_128FS_MUX_INT_CK	227
#define AU_VIVA_HDMI_RX2_S2P_128FS_INT_CK	228
#define AU_VIVA_HDMI_RX2_V2A_TIME_STAMP_INT_CK	229
#define AU_VIVA_HDMI_RX2_MPLL_432_INT_CK	230
#define AU_VIVA_BCLK_I2S_DECODER_INT_CK	231
#define AU_VIVA_MCLK_I2S_DECODER_INT_CK	232
#define AU_VIVA_I2S_BCLK_DG_INT_CK	233
#define AU_VIVA_I2S_SYNTH_REF_INT_CK	234
#define AU_VIVA_BCLK_I2S_DECODER2_INT_CK	235
#define AU_VIVA_MCLK_I2S_DECODER2_INT_CK	236
#define AU_VIVA_I2S_BCLK_DG2_INT_CK	237
#define AU_VIVA_BI2S_SYNTH_REF2_INT_CK	238
#define AU_HDMI_TX_TO_I2S_TX_256FS_MUX_INT_CK	239
#define AU_HDMI_TX_TO_I2S_TX_128FS_MUX_INT_CK	240
#define AU_HDMI_TX_TO_I2S_TX_64FS_MUX_INT_CK	241
#define AU_HDMI_TX_TO_I2S_TX_32FS_MUX_INT_CK	242
#define AU_HDMI_RX_TO_I2S_TX_256FS_MUX_INT_CK	243
#define AU_HDMI_RX_TO_I2S_TX_128FS_MUX_INT_CK	244
#define AU_HDMI_RX_TO_I2S_TX_64FS_MUX_INT_CK	245
#define AU_HDMI_RX_TO_I2S_TX_32FS_MUX_INT_CK	246
#define AU_VIVA_I2S_TX_FIFO_256FS_INT_CK	247
#define AU_VIVA_I2S_MCLK_SYNTH_REF_INT_CK	248
#define AU_VIVA_MCLK_I2S_ENCODER_INT_CK	249
#define AU_I2S_BCLK_SYNTH_REF_MUX_INT_CK	250
#define AU_VIVA_I2S_BCLK_SYNTH_REF_INT_CK	251
#define AU_BCLK_I2S_ENCODER_128FS_SSC_MUX_INT_CK	252
#define AU_BCLK_I2S_ENCODER_64FS_SSC_MUX_INT_CK	253
#define AU_BCLK_I2S_ENCODER_32FS_SSC_MUX_INT_CK	254
#define AU_BCLK_I2S_ENCODER_MUX_INT_CK	255
#define AU_BCLK_I2S_ENCODER_INT_CK	256
#define AU_BCLK_I2S_ENCODER_TO_PAD_INT_CK	257
#define AU_VIVA_I2S_TX_2_FIFO_256FS_INT_CK	258
#define AU_VIVA_MCLK_I2S_ENCODER2_INT_CK	259
#define AU_I2S_2_BCLK_SYNTH_REF_MUX_INT_CK	260
#define AU_VIVA_I2S_2_BCLK_SYNTH_REF_INT_CK	261
#define AU_BCLK_I2S_ENCODER2_128FS_SSC_MUX_INT_CK	262
#define AU_BCLK_I2S_ENCODER2_64FS_SSC_MUX_INT_CK	263
#define AU_BCLK_I2S_ENCODER2_32FS_SSC_MUX_INT_CK	264
#define AU_BCLK_I2S_ENCODER2_MUX_INT_CK	265
#define AU_BCLK_I2S_ENCODER2_INT_CK	266
#define AU_BCLK_I2S_ENCODER2_TO_PAD_INT_CK	267
#define AU_VIVA_I2S_TRX_SYNTH_REF_INT_CK	268
#define AU_VIVA_I2S_TRX_BCLK_TIMING_GEN_INT_CK	269
#define AU_VIVA_PCM_CLK_216_INT_CK	270
#define AU_VIVA_PCM_CLK_AUPLL_INT_CK	271
#define AU_SPDIF_TX_GPA_SYNTH_256FS_MUX_INT_CK	272
#define AU_SPDIF_TX_256FS_MUX_INT_CK	273
#define AU_VIVA_SPDIF_TX_256FS_INT_CK	274
#define AU_SPDIF_TX_GPA_128FS_MUX_INT_CK	275
#define AU_SPDIF_TX_128FS_MUX_INT_CK	276
#define AU_VIVA_SPDIF_TX_128FS_INT_CK	277
#define AU_VIVA_SPDIF_TX_SYNTH_REF_INT_CK	278
#define AU_SPDIF_TX2_GPA_SYNTH_256FS_MUX_INT_CK	279
#define AU_SPDIF_TX2_256FS_MUX_INT_CK	280
#define AU_VIVA_SPDIF_TX2_256FS_INT_CK	281
#define AU_SPDIF_TX2_GPA_128FS_MUX_INT_CK	282
#define AU_SPDIF_TX2_128FS_MUX_INT_CK	283
#define AU_VIVA_SPDIF_TX2_128FS_INT_CK	284
#define AU_VIVA_NPCM_SYNTH_REF_INT_CK	285
#define AU_VIVA_NPCM2_SYNTH_REF_INT_CK	286
#define AU_VIVA_NPCM3_SYNTH_REF_INT_CK	287
#define AU_VIVA_NPCM4_SYNTH_REF_INT_CK	288
#define AU_VIVA_NPCM4_256FS_TIMING_GEN_INT_CK	289
#define AU_VIVA_NPCM5_SYNTH_REF_INT_CK	290
#define AU_VIVA_NPCM5_256FS_TIMING_GEN_INT_CK	291
#define AU_HDMI_TX_256FS_MUX1_INT_CK	292
#define AU_HDMI_TX_256FS_MUX0_INT_CK	293
#define AU_HDMI_TX_256FS_MUX_INT_CK	294
#define AU_VIVA_HDMI_TX_256FS_INT_CK	295
#define AU_VIVA_HDMI_TX_128FS_INT_CK	296
#define AU_SPDIF_EXTEARC_256FS_MUX_INT_CK	297
#define AU_SPDIF_EXTEARC_128FS_MUX_INT_CK	298
#define AU_SPDIF_EXTEARC_MUX0_INT_CK	299
#define AU_SPDIF_EXTEARC_MUX_INT_CK	300
#define AU_VIVA_SPDIF_EXTEARC_INT_CK	301
#define AU_VIVA_EARC_TX_SYNTH_REF_INT_CK	302
#define AU_VIVA_EARC_TX_GPA_SYNTH_REF_INT_CK	303
#define AU_VIVA_EARC_TX_SYNTH_IIR_REF_INT_CK	304
#define AU_EARC_TX_GPA_256FS_MUX_INT_CK	305
#define AU_EARC_TX_PLL_256FS_REF_MUX_INT_CK	306
#define AU_EARC_TX_PLL_256FS_REF_INT_CK	307
#define AU_VIVA_EARC_TX_PLL_INT_CK	308
#define AU_VIVA_EARC_TX_64XCHXFS_INT_CK	309
#define AU_VIVA_EARC_TX_32XCHXFS_INT_CK	310
#define AU_VIVA_EARC_TX_32XFS_INT_CK	311
#define AU_EARC_TX_SOURCE_256FS_MUX_INT_CK	312
#define AU_VIVA_EARC_TX_SOURCE_256FS_INT_CK	313
#define AU_VIVA_SIN_GEN_INT_CK	314
#define AU_VIVA_TEST_BUS_INT_CK	315
#define AU_VIVA_SRC_MAC_BSPLINE_INT_CK	316
#define AU_VIVA_I2S_TDM_6X16TX32B_BCLK_INT_CK	317
#define AU_VIVA_I2S_TDM_6X16TX32B_FIFO_INT_CK	318
#define AU_INVERSE_OF_VIVA_I2S_TDM_6X16TX32B_BCLK_INT_CK	319
#define AU_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_INT_CK	320
#define AU_VIVA_I2S_TDM_1X16TX32B_BCLK_INT_CK	321
#define AU_VIVA_I2S_TDM_1X16TX32B_FIFO_INT_CK	322
#define AU_INVERSE_OF_VIVA_I2S_TDM_1X16TX32B_BCLK_INT_CK	323
#define AU_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_INT_CK	324
#define AU_R2_INT_CK	325
#define AU_RV_INT_CK	326
#define AU_RV_TCK_INT_CK	327
#define AU_DAP_INT_CK	328
#define AU_DAP_TCK_INT_CK	329
#define AU_NR	330
