#ifndef _LPLL_H
#define _LPLL_H

#define lpll 0x00486000

//Page LPLL_1
#define REG_0004_LPLL (lpll + 0x004)
    #define REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0008_LPLL (lpll + 0x008)
    #define REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_000C_LPLL (lpll + 0x00C)
    #define REG_000C_LPLL_REG_LPLL1_ICP_ICTRL Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL Fld(3,2,AC_MSKB0)//[4:2]
    #define REG_000C_LPLL_REG_LPLL1_PD Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_000C_LPLL_REG_LPLL1_2CHIP_SYN_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_000C_LPLL_REG_LPLL1_EN_DDR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_000C_LPLL_REG_LPLL1_ENFRUNZ Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_000C_LPLL_REG_LPLL1_EN_SKEW_DIVIDER Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_000C_LPLL_REG_LPLL1_TEST_EN_FIFO Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_000C_LPLL_REG_LPLL1_LOCK Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_000C_LPLL_REG_LPLL1_HIGH_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0010_LPLL (lpll + 0x010)
    #define REG_0010_LPLL_REG_LPLL1_SKEW_CLK1_PHASE_SEL Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0010_LPLL_REG_LPLL1_SKEW_CLK2_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0010_LPLL_REG_LPLL1_SDIV3P5_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0010_LPLL_REG_PRD_STABLE_THRESEL Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0014_LPLL (lpll + 0x014)
    #define REG_0014_LPLL_REG_PRD_STABLE_THRESH Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0014_LPLL_REG_PRD_LOCK_THRESH Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0014_LPLL_REG_PHASE_LOCK_THRESH Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0018_LPLL (lpll + 0x018)
    #define REG_0018_LPLL_REG_LIMIT_D5D6D7_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_LPLL (lpll + 0x01C)
    #define REG_001C_LPLL_REG_LIMIT_D5D6D7_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0020_LPLL (lpll + 0x020)
    #define REG_0020_LPLL_REG_LIMIT_D5D6D7_RK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_LPLL (lpll + 0x024)
    #define REG_0024_LPLL_REG_LIMIT_D5D6D7_RK_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0028_LPLL (lpll + 0x028)
    #define REG_0028_LPLL_REG_LIMIT_LPLL_OFFSET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_LPLL (lpll + 0x02C)
    #define REG_002C_LPLL_REG_I_GAIN_PRD Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_002C_LPLL_REG_P_GAIN_PRD Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_002C_LPLL_REG_I_GAIN_PHASE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_002C_LPLL_REG_P_GAIN_PHASE Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0030_LPLL (lpll + 0x030)
    #define REG_0030_LPLL_REG_FPLL_MODE Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0030_LPLL_REG_FRAME_LPLL_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0030_LPLL_REG_I_GAIN_PRD_ZERO Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0030_LPLL_REG_P_GAIN_PRD_ZERO Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0030_LPLL_REG_I_GAIN_PHASE_ZERO Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0030_LPLL_REG_P_GAIN_PHASE_ZERO Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0030_LPLL_REG_IVS_FRAME_DIV Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0030_LPLL_REG_OVS_FRAME_DIV Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0034_LPLL (lpll + 0x034)
    #define REG_0034_LPLL_REG_FORCE_PRD_STABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0034_LPLL_REG_FORCE_PRD_LOCK_DONE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0034_LPLL_REG_FORCE_PHASE_REDUCE_DONE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0034_LPLL_REG_FORCE_PHASE_CLOSE_DONE Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0034_LPLL_REG_EN_2_LIMIT Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0034_LPLL_REG_NO_SIGNAL_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0034_LPLL_REG_NON_STABLE_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0034_LPLL_REG_SSC_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0034_LPLL_REG_SYNTH_CLK_DIV2_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0038_LPLL (lpll + 0x038)
    #define REG_0038_LPLL_REG_EXT_IVS_FRAME_DIV Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0038_LPLL_REG_EXT_OVS_FRAME_DIV Fld(4,4,AC_MSKB0)//[7:4]
#define REG_003C_LPLL (lpll + 0x03C)
    #define REG_003C_LPLL_REG_PLL_SET_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_LPLL (lpll + 0x040)
    #define REG_0040_LPLL_REG_PLL_SET_1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0044_LPLL (lpll + 0x044)
    #define REG_0044_LPLL_REG_PHASE_DIF Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_LPLL (lpll + 0x048)
    #define REG_0048_LPLL_REG_PHASE_UP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_004C_LPLL (lpll + 0x04C)
    #define REG_004C_LPLL_REG_PRD_DIF Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_LPLL (lpll + 0x050)
    #define REG_0050_LPLL_REG_PRD_UP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0054_LPLL (lpll + 0x054)
    #define REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0054_LPLL_REG_LPLL1_INPUT_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0058_LPLL (lpll + 0x058)
    #define REG_0058_LPLL_REG_LPLL_TESTD_A Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0058_LPLL_REG_LPLL_TESTD Fld(8,8,AC_FULLB1)//[15:8]
#define REG_005C_LPLL (lpll + 0x05C)
    #define REG_005C_LPLL_REG_LPLL_STEP Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_LPLL (lpll + 0x060)
    #define REG_0060_LPLL_REG_LPLL_SPAN Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0064_LPLL (lpll + 0x064)
    #define REG_0064_LPLL_REG_IDCLK_DIV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_LPLL (lpll + 0x068)
    #define REG_0068_LPLL_REG_IDCLK_DIV_1 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_006C_LPLL (lpll + 0x06C)
    #define REG_006C_LPLL_REG_ODCLK_DIV_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_LPLL (lpll + 0x070)
    #define REG_0070_LPLL_REG_ODCLK_DIV_1 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0074_LPLL (lpll + 0x074)
    #define REG_0074_LPLL_REG_DEC_V_LIMIT Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_0074_LPLL_REG_FIX_DEC_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0078_LPLL (lpll + 0x078)
    #define REG_0078_LPLL_REG_INC_V_LIMIT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_007C_LPLL (lpll + 0x07C)
    #define REG_007C_LPLL_REG_PHASE_CLOSE_THRESH Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_007C_LPLL_REG_REDUCE_DONE_THRESH Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0080_LPLL (lpll + 0x080)
    #define REG_0080_LPLL_REG_HIS_CNT_LOW_THRESH Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0080_LPLL_REG_HIS_CNT_HIGH_THRESH Fld(3,4,AC_MSKB0)//[6:4]
#define REG_0084_LPLL (lpll + 0x084)
    #define REG_0084_LPLL_REG_IVS_PRD_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_LPLL (lpll + 0x088)
    #define REG_0088_LPLL_REG_IVS_PRD_VALUE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_008C_LPLL (lpll + 0x08C)
    #define REG_008C_LPLL_REG_OVS_PRD_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_LPLL (lpll + 0x090)
    #define REG_0090_LPLL_REG_OVS_PRD_VALUE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0098_LPLL (lpll + 0x098)
    #define REG_0098_LPLL_REG_FIX_V_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_0098_LPLL_REG_FIX_V_DEC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_009C_LPLL (lpll + 0x09C)
    #define REG_009C_LPLL_REG_FIX_H_TOTAL Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A0_LPLL (lpll + 0x0A0)
    #define REG_00A0_LPLL_REG_PLL_SET_USING_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_LPLL (lpll + 0x0A4)
    #define REG_00A4_LPLL_REG_PLL_SET_USING_1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_00A8_LPLL (lpll + 0x0A8)
    #define REG_00A8_LPLL_REG_CS_STATE Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_00A8_LPLL_REG_OVS_PRD_STABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00A8_LPLL_REG_IVS_PRD_STABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00A8_LPLL_REG_PRD_LOCK_DONE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00A8_LPLL_REG_PHASE_REDUCE_DONE Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00A8_LPLL_REG_PHASE_LOCK_DONE Fld(1,8,AC_MSKB1)//[8:8]
#define REG_00AC_LPLL (lpll + 0x0AC)
    #define REG_00AC_LPLL_REG_LPLL_SYN_CLK_SEL Fld(1,1,AC_MSKB0)//[1:1]
#define REG_00B0_LPLL (lpll + 0x0B0)
    #define REG_00B0_LPLL_REG_LPLL_LOOP_GAIN Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_00B0_LPLL_REG_LPLL_LOOP_DIV Fld(8,0,AC_FULLB0)//[7:0]
#define REG_00B8_LPLL (lpll + 0x0B8)
    #define REG_00B8_LPLL_REG_LPLL1_FIFO_DIV Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00B8_LPLL_REG_LPLL1_EN_SCALAR Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00B8_LPLL_REG_LPLL1_VCO_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00B8_LPLL_REG_LPLL1_EN_FIFO Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00B8_LPLL_REG_LPLL1_EN_VBY1_DIFF Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_00B8_LPLL_REG_LPLL1_EN_SKEW_CLK Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_00B8_LPLL_REG_LPLL1_EN_MINI Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00BC_LPLL (lpll + 0x0BC)
    #define REG_00BC_LPLL_REG_PD_MPLL_TEST_CLKD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00BC_LPLL_REG_PD_LPLL_SCALAR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00BC_LPLL_REG_PD_LPLL_FIFO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00BC_LPLL_REG_PD_LPLL_SYN432 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00BC_LPLL_REG_PD_LPLL_MASTER_TEST_CLK Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00BC_LPLL_REG_PD_LPLL_SLAVE_TEST_CLK Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00BC_LPLL_REG_PD_LPLL_OSD_TEST_CLK Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00BC_LPLL_REG_LPLL1_MASTER_SLAVE_DIV_FIRST Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00BC_LPLL_REG_LPLL1_MASTER_SLAVE_DIV5_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_00BC_LPLL_REG_LPLL1_MASTER_SLAVE_EN Fld(1,11,AC_MSKB1)//[11:11]
#define REG_00C0_LPLL (lpll + 0x0C0)
    #define REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_LPLL (lpll + 0x0C4)
    #define REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C8_LPLL (lpll + 0x0C8)
    #define REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_LPLL (lpll + 0x0CC)
    #define REG_00CC_LPLL_REG_LPLL2_ICP_ICTRL Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL Fld(3,2,AC_MSKB0)//[4:2]
    #define REG_00CC_LPLL_REG_LPLL2_PD Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00CC_LPLL_REG_LPLL2_PORST Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00CC_LPLL_REG_LPLL2_DIV14_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00CC_LPLL_REG_LPLL2_ENFRUNZ Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_00CC_LPLL_REG_LPLL2_LOCK Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00CC_LPLL_REG_LPLL2_HIGH_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00D0_LPLL (lpll + 0x0D0)
    #define REG_00D0_LPLL_REG_LPLL1_FINE_PHSEL1 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00D0_LPLL_REG_LPLL1_FINE_PHSEL2 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00D4_LPLL (lpll + 0x0D4)
    #define REG_00D4_LPLL_REG_LPLL_2CHIP_CLKOUT_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00D4_LPLL_REG_LPLL_2CHIP_FBIN_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00D4_LPLL_REG_LPLL_2CHIP_REFIN_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00D4_LPLL_REG_LPLL1_EN_2CHIP_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00D4_LPLL_REG_LPLL1_EN_CLKREF_FROM_OTHER_CHIP Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00D4_LPLL_REG_LPLL1_PD_PHDAC Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00D4_LPLL_REG_LPLL1_SKEW_DIV Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00D8_LPLL (lpll + 0x0D8)
    #define REG_00D8_LPLL_REG_LPLL1_TEST_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_LPLL (lpll + 0x0DC)
    #define REG_00DC_LPLL_REG_LPLL1_TEST_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_LPLL (lpll + 0x0E0)
    #define REG_00E0_LPLL_REG_LPLL1_NCO_RETIME_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00E0_LPLL_REG_LPLL1_SKEW1_DELAY1T Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00E0_LPLL_REG_LPLL1_SKEW2_DELAY1T Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00E0_LPLL_REG_LPLL1_SKEW3_DELAY1T Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00E0_LPLL_REG_LPLL1_SKEW4_DELAY1T Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN Fld(1,9,AC_MSKB1)//[9:9]
#define REG_00E4_LPLL (lpll + 0x0E4)
    #define REG_00E4_LPLL_REG_LPLL2_TEST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_LPLL (lpll + 0x0E8)
    #define REG_00E8_LPLL_REG_LPLL1_CLKIN_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00E8_LPLL_REG_LPLL1_RX_CLKFB_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00E8_LPLL_REG_LPLL_2CHIP_SCALAR_FB_DIV Fld(4,4,AC_MSKB0)//[7:4]
#define REG_00EC_LPLL (lpll + 0x0EC)
    #define REG_00EC_LPLL_REG_FORCE_DISABLE_FPLL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00EC_LPLL_REG_AUTO_DISABLE_FPLL_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00EC_LPLL_REG_LPLL_DUMMY0 Fld(14,2,AC_MSKW10)//[15:2]
#define REG_00F0_LPLL (lpll + 0x0F0)
    #define REG_00F0_LPLL_REG_LPLL_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_LPLL (lpll + 0x0F4)
    #define REG_00F4_LPLL_REG_IVS_OVS_PHASE_DIF_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_LPLL (lpll + 0x0F8)
    #define REG_00F8_LPLL_REG_IVS_OVS_PHASE_DIF_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_00FC_LPLL (lpll + 0x0FC)
    #define REG_00FC_LPLL_REG_IVS_OVS_PHASE_UP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0100_LPLL (lpll + 0x100)
    #define REG_0100_LPLL_REG_LPLLO_EN_DDR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0100_LPLL_REG_LPLLO_EN_FIFO Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0100_LPLL_REG_LPLLO_EN_MINI Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0100_LPLL_REG_LPLLO_EN_SCALAR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0100_LPLL_REG_LPLLO_SCALAR2FIFO_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0100_LPLL_REG_LPLLO_SDIV3P5_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0100_LPLL_REG_LPLLO_SKEW_EN_FIXCLK Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0100_LPLL_REG_LPLLO_SKEW_EN_SKEWCLK Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0100_LPLL_REG_LPLLO_TEST_EN_SDIV Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0100_LPLL_REG_LPLLO_TEST_FIFO_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0100_LPLL_REG_LPLLO_PD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0100_LPLL_REG_LPLLO_SEL_SKEW1_DELAY1T Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0100_LPLL_REG_LPLLO_SEL_SKEW2_DELAY1T Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0104_LPLL (lpll + 0x104)
    #define REG_0104_LPLL_REG_LPLLO_ICTRL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0104_LPLL_REG_LPLLO_LOCK Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0104_LPLL_REG_LPLLO_HIGH_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0108_LPLL (lpll + 0x108)
    #define REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0108_LPLL_REG_LPLLO_FIFO_DIV Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0108_LPLL_REG_LPLLO_SKEW_DIV Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0108_LPLL_REG_LPLLO_SKEW1_FINE Fld(4,12,AC_MSKB1)//[15:12]
#define REG_010C_LPLL (lpll + 0x10C)
    #define REG_010C_LPLL_REG_LPLLO_SKEW2_FINE Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_010C_LPLL_REG_LPLLO_SKEW1_COARSE Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_010C_LPLL_REG_LPLLO_SKEW2_COARSE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_010C_LPLL_REG_LPLLO_SCALAR2FIFO_DIV2 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_010C_LPLL_REG_LPLLO_EN_VBY1_HS Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0110_LPLL (lpll + 0x110)
    #define REG_0110_LPLL_REG_LPLLO_TEST_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0114_LPLL (lpll + 0x114)
    #define REG_0114_LPLL_REG_LPLLO_TEST_1 Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0114_LPLL_REG_LPLLO_TEST_1_V2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0130_LPLL (lpll + 0x130)
    #define REG_0130_LPLL_REG_TGEN2PLL_VTT_FINAL Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_0130_LPLL_REG_TGEN2PLL_VTT_UPDATE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0134_LPLL (lpll + 0x134)
    #define REG_0134_LPLL_REG_TGEN2PLL_VTT_TARGET Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0138_LPLL (lpll + 0x138)
    #define REG_0138_LPLL_REG_TGEN2PLL_VTT_RPT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_013C_LPLL (lpll + 0x13C)
    #define REG_013C_LPLL_REG_VTT2SET_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0140_LPLL (lpll + 0x140)
    #define REG_0140_LPLL_REG_PLL_SET_AGE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0144_LPLL (lpll + 0x144)
    #define REG_0144_LPLL_REG_PLL_SET_AGE_1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0148_LPLL (lpll + 0x148)
    #define REG_0148_LPLL_REG_AGE_LOCK_CNT_NUM_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_014C_LPLL (lpll + 0x14C)
    #define REG_014C_LPLL_REG_AGE_LOCK_CNT_NUM_1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_014C_LPLL_REG_AGE_VCNT_FREEZE_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_014C_LPLL_REG_AGE_LOCK_CLK_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_014C_LPLL_REG_AGE_LOCK_MODE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0150_LPLL (lpll + 0x150)
    #define REG_0150_LPLL_REG_AGE_OVS_DELAY_SW_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0154_LPLL (lpll + 0x154)
    #define REG_0154_LPLL_REG_AGE_OVS_DELAY_SW_VALUE_1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_0154_LPLL_REG_AGE_OVS_DELAY_SW_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0158_LPLL (lpll + 0x158)
    #define REG_0158_LPLL_REG_AGE_OVS_DELAY_HW_VALUE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_015C_LPLL (lpll + 0x15C)
    #define REG_015C_LPLL_REG_AGE_OVS_DELAY_HW_VALUE_1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_015C_LPLL_REG_LPLL_INTR_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_015C_LPLL_REG_LPLL_INTR Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0160_LPLL (lpll + 0x160)
    #define REG_0160_LPLL_REG_CLKEN_BITMAP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0164_LPLL (lpll + 0x164)
    #define REG_0164_LPLL_REG_DUMMY_ANA Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0168_LPLL (lpll + 0x168)
    #define REG_0168_LPLL_REG_SYN864_SW_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0168_LPLL_REG_SYNTH_SSC_SPAN_SUB_DIV Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0168_LPLL_REG_SYNTH_SSC_SPAN_SUB_DIV_RX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_017C_LPLL (lpll + 0x17C)
    #define REG_017C_LPLL_REG_OVS_PRD_MAXMIN_CLR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_017C_LPLL_REG_OVS_PRD_MAXMIN_SEL Fld(2,1,AC_MSKB0)//[2:1]
#define REG_0180_LPLL (lpll + 0x180)
    #define REG_0180_LPLL_REG_LPLL1_VBYONE_DIV Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0180_LPLL_REG_LPLL1_PD_PHDAC_EXT Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0180_LPLL_REG_LPLL1_EN_VBYONE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_LPLL (lpll + 0x184)
    #define REG_0184_LPLL_REG_LPLL1_SKEW_CLK3_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0184_LPLL_REG_LPLL1_FINE_PHSEL3 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0188_LPLL (lpll + 0x188)
    #define REG_0188_LPLL_REG_LPLL1_SKEW_CLK4_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0188_LPLL_REG_LPLL1_FINE_PHSEL4 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_018C_LPLL (lpll + 0x18C)
    #define REG_018C_LPLL_REG_LPLL1_SKEW_CLK5_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_018C_LPLL_REG_LPLL1_FINE_PHSEL5 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0190_LPLL (lpll + 0x190)
    #define REG_0190_LPLL_REG_LPLL1_SKEW_CLK6_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0190_LPLL_REG_LPLL1_FINE_PHSEL6 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0194_LPLL (lpll + 0x194)
    #define REG_0194_LPLL_REG_LPLL1_SKEW_CLK7_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0194_LPLL_REG_LPLL1_FINE_PHSEL7 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0198_LPLL (lpll + 0x198)
    #define REG_0198_LPLL_REG_LPLL1_SKEW_CLK8_PHASE_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0198_LPLL_REG_LPLL1_FINE_PHSEL8 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_019C_LPLL (lpll + 0x19C)
    #define REG_019C_LPLL_REG_LPLL1_COARSE_PHSEL1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_019C_LPLL_REG_LPLL1_COARSE_PHSEL2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_019C_LPLL_REG_LPLL1_COARSE_PHSEL3 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_019C_LPLL_REG_LPLL1_COARSE_PHSEL4 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01A0_LPLL (lpll + 0x1A0)
    #define REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01A0_LPLL_REG_EN_CLKREF_FROM_OTHER_CHIP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01A0_LPLL_REG_EN_2CHIP_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01A0_LPLL_REG_EN_VBY1_DIFF_LPLL Fld(1,3,AC_MSKB0)//[3:3]

//Page LPLL_2
#define REG_01A8_LPLL (lpll + 0x1A8)
    #define REG_01A8_LPLL_REG_PD_VCO_864M_DIV5 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01AC_LPLL (lpll + 0x1AC)
    #define REG_01AC_LPLL_REG_PD_VCO_864M_DIV3P5 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01AC_LPLL_REG_PD_VCO_864M_DIV3 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01AC_LPLL_REG_PD_VCO_864M_DIV2P5 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01AC_LPLL_REG_PD_VCO_864M_DIV2 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01AC_LPLL_REG_PD_VCO_864M Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_01AC_LPLL_REG_PD_DVB_864M_DIV10 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_01AC_LPLL_REG_PD_DVB_864M_DIV7 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01AC_LPLL_REG_PD_DVB_864M_DIV5 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01AC_LPLL_REG_PD_DVB_864M_DIV3P5 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01AC_LPLL_REG_PD_DVB_864M_DIV3 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01AC_LPLL_REG_PD_DVB_864M_DIV2 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_01AC_LPLL_REG_PD_DIGCLK Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_01AC_LPLL_REG_PD_CLK_DVI Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01AC_LPLL_REG_PD_CLK_CVBS Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01AC_LPLL_REG_EN_MPLL_SW_LPLL_CLK Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01AC_LPLL_REG_EN_MPLL_AMUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01B0_LPLL (lpll + 0x1B0)
    #define REG_01B0_LPLL_REG_MPLL_ICP_ICTRL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01B0_LPLL_REG_MPLL_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01B0_LPLL_REG_MPLL_CLK_ADC_VCO_DIV2_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_01B0_LPLL_REG_MPLL_IN_SELECT Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_01B0_LPLL_REG_MPLL_LOCK Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01B0_LPLL_REG_MPLL_HIGH_FLAG Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01B0_LPLL_REG_MPLL_TEST_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01B0_LPLL_REG_MPLL_CLK_ADC_VCO_DIV2_PD3 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01B0_LPLL_REG_MPLL_FRUN_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_01B0_LPLL_REG_MPLL_VCO_DIV2_DISABLE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_01B0_LPLL_REG_MPLL_CLK_ADC_VCO_DIV2_PD2 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01B0_LPLL_REG_MPLL_XTAL_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01B0_LPLL_REG_MPLL_RST_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01B0_LPLL_REG_MPLL_DISC_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01B4_LPLL (lpll + 0x1B4)
    #define REG_01B4_LPLL_REG_MPLL_INPUT_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01B4_LPLL_REG_MPLL_OUTPUT_DIV_FIRST Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01B4_LPLL_REG_MPLL_LOOP_DIV_FIRST Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01B4_LPLL_REG_MPLL_LOOP_DIV_SECOND Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01B8_LPLL (lpll + 0x1B8)
    #define REG_01B8_LPLL_REG_MPLL_TEST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01BC_LPLL (lpll + 0x1BC)
    #define REG_01BC_LPLL_REG_MPLL_OUTPUT_DIV Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01BC_LPLL_REG_MPLL_OV_CP_SW Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01BC_LPLL_REG_MPLL_PRDT_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_01BC_LPLL_REG_MPLL_CP_SW Fld(2,5,AC_MSKB0)//[6:5]
    #define REG_01BC_LPLL_REG_MPLL_DIS_SW Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01BC_LPLL_REG_MPLL_DIGCLK_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01BC_LPLL_REG_MPLL_OCC Fld(1,9,AC_MSKB1)//[9:9]
#define REG_01C0_LPLL (lpll + 0x1C0)
    #define REG_01C0_LPLL_REG_EN_CLK_DIV Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01C0_LPLL_REG_VTT_PLL_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01C0_LPLL_REG_PRD_LOCK_THRESH_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01C0_LPLL_REG_EN_PLL_FSYNC_RESET Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_01C0_LPLL_REG_CLR_FSYNC_RESET_2T_FLAG Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01C0_LPLL_REG_FSYNC_RESET_2T_FLAG Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01C0_LPLL_REG_FSYNC_RESET_THRESH Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01C4_LPLL (lpll + 0x1C4)
    #define REG_01C4_LPLL_REG_LPLL1_TEST_V2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_LPLL (lpll + 0x1C8)
    #define REG_01C8_LPLL_REG_IDCLK_DIV_PRD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_LPLL (lpll + 0x1CC)
    #define REG_01CC_LPLL_REG_IDCLK_DIV_PRD_1 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01D0_LPLL (lpll + 0x1D0)
    #define REG_01D0_LPLL_REG_ODCLK_DIV_PRD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_LPLL (lpll + 0x1D4)
    #define REG_01D4_LPLL_REG_ODCLK_DIV_PRD_1 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01D8_LPLL (lpll + 0x1D8)
    #define REG_01D8_LPLL_REG_OVS_SPREAD_REM Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01DC_LPLL (lpll + 0x1DC)
    #define REG_01DC_LPLL_REG_SPREAD_REM Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01E0_LPLL (lpll + 0x1E0)
    #define REG_01E0_LPLL_REG_OVS_PH_HALF_ORG_DIS Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01E0_LPLL_REG_V_OFFSET_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01E0_LPLL_REG_IVS_THRESH_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01E0_LPLL_REG_LOC_VTT_FIX_CAL_EN Fld(1,11,AC_MSKB1)//[11:11]
#define REG_01E4_LPLL (lpll + 0x1E4)
    #define REG_01E4_LPLL_REG_OVS_SPREADER_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01E4_LPLL_REG_OVS_SPREAD_NUM Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01E8_LPLL (lpll + 0x1E8)
    #define REG_01E8_LPLL_REG_SPREAD_NUM Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01EC_LPLL (lpll + 0x1EC)
    #define REG_01EC_LPLL_REG_SELF_DET_TH Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F0_LPLL (lpll + 0x1F0)
    #define REG_01F0_LPLL_REG_IVS_PRD_RPT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_LPLL (lpll + 0x1F4)
    #define REG_01F4_LPLL_REG_IVS_PRD_RPT_1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_01F4_LPLL_REG_IVS_PRD_RPT_RESET_AUTO Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01F4_LPLL_REG_VS_PRD_RPT_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01F4_LPLL_REG_IVS_PRD_IDCLK_RPT_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01F4_LPLL_REG_FPLL_GAT_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01F8_LPLL (lpll + 0x1F8)
    #define REG_01F8_LPLL_REG_SPREADER_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01F8_LPLL_REG_F_RPT_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01F8_LPLL_REG_PHASE_LOCK_THRESH_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01F8_LPLL_REG_F_RPT_CNT Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01FC_LPLL (lpll + 0x1FC)
    #define REG_01FC_LPLL_REG_EXT_SYNTH_CLK_SRC_EN_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01FC_LPLL_REG_TGEN_SRC_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01FC_LPLL_REG_FIX_POSI_LD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01FC_LPLL_REG_SW_TRIG_CLR_FIX_VTT Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01FC_LPLL_REG_SW_TRIG_DB_LOAD Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01FC_LPLL_REG_DB_EN Fld(1,0,AC_MSKB0)//[0:0]

#endif
