/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_MHEG5_H
#define _DT_BINDINGS_CLK_MT5896_MHEG5_H

#define CLK_MHEG5_XTAL_24M_INT_CK	1
#define CLK_MHEG5_XTAL_12M_INT_CK	2
#define CLK_MHEG5_SMI_INT_CK	3
#define CLK_MHEG5_MCU_BUS_INT_CK	4
#define CLK_MHEG5_MCU_NONPM_INT_CK	5
#define CLK_MHEG5_RIU_NONPM_INT_CK	6
#define CLK_MHEG5_MCU_VD_INT_CK	7
#define CLK_MHEG5_RIU_VD_INT_CK	8
#define CLK_MHEG5_SPI_INT_CK	9
#define CLK_MHEG5_MIIC0_INT_CK	10
#define CLK_MHEG5_MIIC1_INT_CK	11
#define CLK_MHEG5_MIIC2_INT_CK	12
#define CLK_MHEG5_MIIC3_INT_CK	13
#define CLK_MHEG5_MSPI0_INT_CK	14
#define CLK_MHEG5_MSPI1_INT_CK	15
#define CLK_MHEG5_MSPI2_INT_CK	16
#define CLK_MHEG5_MSPI3_INT_CK	17
#define CLK_MHEG5_MSPI4_INT_CK	18
#define CLK_MHEG5_MSPI5_INT_CK	19
#define CLK_MHEG5_MSPI6_INT_CK	20
#define CLK_MHEG5_MSPI7_INT_CK	21
#define CLK_MHEG5_MSPI_CILINK_INT_CK	22
#define CLK_MHEG5_UART0_INT_CK	23
#define CLK_MHEG5_UART1_INT_CK	24
#define CLK_MHEG5_UART2_INT_CK	25
#define CLK_MHEG5_FUART0_INT_CK	26
#define CLK_MHEG5_GE_INT_CK	27
#define CLK_MHEG5_GE_PSRAM_INT_CK	28
#define CLK_MHEG5_GE_FIFO_R_INT_CK	29
#define CLK_MHEG5_GE_FIFO_W_INT_CK	30
#define CLK_MHEG5_ADCPLB_MPLL_INT_CK	31
#define CLK_MHEG5_GPD_INT_CK	32
#define CLK_MHEG5_VENC_INT_CK	33
#define CLK_MHEG5_GMAC_AHB_INT_CK	34
#define CLK_MHEG5_GMAC_TX_INT_CK	35
#define CLK_MHEG5_GMAC_RX_INT_CK	36
#define CLK_MHEG5_SMART_INT_CK	37
#define CLK_MHEG5_SMART_SYNTH_432_INT_CK	38
#define CLK_MHEG5_SMART_SYNTH_27_INT_CK	39
#define CLK_MHEG5_SMART2_INT_CK	40
#define CLK_MHEG5_SMART2_SYNTH_432_INT_CK	41
#define CLK_MHEG5_SMART2_SYNTH_27_INT_CK	42
#define CLK_MHEG5_VD_INT_CK	43
#define CLK_MHEG5_VD2X_INT_CK	44
#define CLK_MHEG5_VD_32FSC_INT_CK	45
#define CLK_MHEG5_CMBAI_INT_CK	46
#define CLK_MHEG5_CMBBI_INT_CK	47
#define CLK_MHEG5_CMBAO_INT_CK	48
#define CLK_MHEG5_CMBBO_INT_CK	49
#define CLK_MHEG5_MCU_MAIL0_INT_CK	50
#define CLK_MHEG5_MCU_MAIL1_INT_CK	51
#define CLK_MHEG5_NR	52

#endif
