
#ifndef _DET_H
#define _DET_H

#include "hwreg_common.h"

#define det 0x00485C00

//Page DET
#define REG_0004_DET (det + 0x004)
    #define REG_0004_DET_REG_DETECT_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_DET_REG_DET_CNT_ALL_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0004_DET_REG_V1_LOCK_INTR_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0004_DET_REG_V1_LOCK_INV Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0004_DET_REG_V2_LOCK_INTR_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0004_DET_REG_V2_LOCK_INV Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0004_DET_REG_O_LOCK_INTR_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0004_DET_REG_O_LOCK_INV Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_DET (det + 0x008)
    #define REG_0008_DET_REG_DET_INTR_MASK_15_00 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_DET (det + 0x00C)
    #define REG_000C_DET_REG_DET_INTR_MASK_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0010_DET (det + 0x010)
    #define REG_0010_DET_REG_DET_INTR_MASK_47_32 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_DET (det + 0x014)
    #define REG_0014_DET_REG_DET_INTR_MASK_63_48 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0018_DET (det + 0x018)
    #define REG_0018_DET_REG_DET_INTR_BITMAP_15_00 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_DET (det + 0x01C)
    #define REG_001C_DET_REG_DET_INTR_BITMAP_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_DET (det + 0x020)
    #define REG_0020_DET_REG_DET_INTR_BITMAP_47_32 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_DET (det + 0x024)
    #define REG_0024_DET_REG_DET_INTR_BITMAP_63_48 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_DET (det + 0x028)
    #define REG_0028_DET_REG_SAMETK_CHK_BITMAP Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0040_DET (det + 0x040)
    #define REG_0040_DET_REG_V1_MOD_IN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_DET (det + 0x044)
    #define REG_0044_DET_REG_V1_MOD_IN_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_DET (det + 0x048)
    #define REG_0048_DET_REG_V1_MOD_IN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_004C_DET (det + 0x04C)
    #define REG_004C_DET_REG_V1_MOD_IN_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_DET (det + 0x050)
    #define REG_0050_DET_REG_V1_MOD_IN_VTT_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0050_DET_REG_V1_MOD_IN_VTT_CHG_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0050_DET_REG_V1_MOD_IN_VDE_CHG_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0050_DET_REG_V1_MOD_IN_VDE_CHG_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0050_DET_REG_V1_MOD_IN_HTT_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0050_DET_REG_V1_MOD_IN_HTT_CHG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0050_DET_REG_V1_MOD_IN_HDE_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0050_DET_REG_V1_MOD_IN_HDE_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0054_DET (det + 0x054)
    #define REG_0054_DET_REG_V1_MOD_IN_HDE_ST_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0054_DET_REG_V1_MOD_IN_HDE_ST_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0060_DET (det + 0x060)
    #define REG_0060_DET_REG_V1_VBY1_IN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_DET (det + 0x064)
    #define REG_0064_DET_REG_V1_VBY1_IN_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_DET (det + 0x068)
    #define REG_0068_DET_REG_V1_VBY1_IN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_006C_DET (det + 0x06C)
    #define REG_006C_DET_REG_V1_VBY1_IN_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_DET (det + 0x070)
    #define REG_0070_DET_REG_V1_VBY1_IN_VTT_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0070_DET_REG_V1_VBY1_IN_VTT_CHG_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0070_DET_REG_V1_VBY1_IN_VDE_CHG_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0070_DET_REG_V1_VBY1_IN_VDE_CHG_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0070_DET_REG_V1_VBY1_IN_HTT_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0070_DET_REG_V1_VBY1_IN_HTT_CHG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0070_DET_REG_V1_VBY1_IN_HDE_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0070_DET_REG_V1_VBY1_IN_HDE_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0074_DET (det + 0x074)
    #define REG_0074_DET_REG_V1_VBY1_IN_HDE_ST_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0074_DET_REG_V1_VBY1_IN_HDE_ST_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0080_DET (det + 0x080)
    #define REG_0080_DET_REG_V2_MOD_IN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0084_DET (det + 0x084)
    #define REG_0084_DET_REG_V2_MOD_IN_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_DET (det + 0x088)
    #define REG_0088_DET_REG_V2_MOD_IN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_008C_DET (det + 0x08C)
    #define REG_008C_DET_REG_V2_MOD_IN_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_DET (det + 0x090)
    #define REG_0090_DET_REG_V2_MOD_IN_VTT_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0090_DET_REG_V2_MOD_IN_VTT_CHG_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0090_DET_REG_V2_MOD_IN_VDE_CHG_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0090_DET_REG_V2_MOD_IN_VDE_CHG_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0090_DET_REG_V2_MOD_IN_HTT_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0090_DET_REG_V2_MOD_IN_HTT_CHG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0090_DET_REG_V2_MOD_IN_HDE_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0090_DET_REG_V2_MOD_IN_HDE_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0094_DET (det + 0x094)
    #define REG_0094_DET_REG_V2_MOD_IN_HDE_ST_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0094_DET_REG_V2_MOD_IN_HDE_ST_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00A0_DET (det + 0x0A0)
    #define REG_00A0_DET_REG_V2_VBY1_IN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_DET (det + 0x0A4)
    #define REG_00A4_DET_REG_V2_VBY1_IN_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A8_DET (det + 0x0A8)
    #define REG_00A8_DET_REG_V2_VBY1_IN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00AC_DET (det + 0x0AC)
    #define REG_00AC_DET_REG_V2_VBY1_IN_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B0_DET (det + 0x0B0)
    #define REG_00B0_DET_REG_V2_VBY1_IN_VTT_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_00B0_DET_REG_V2_VBY1_IN_VTT_CHG_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_00B0_DET_REG_V2_VBY1_IN_VDE_CHG_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00B0_DET_REG_V2_VBY1_IN_VDE_CHG_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_00B0_DET_REG_V2_VBY1_IN_HTT_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00B0_DET_REG_V2_VBY1_IN_HTT_CHG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_00B0_DET_REG_V2_VBY1_IN_HDE_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00B0_DET_REG_V2_VBY1_IN_HDE_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00B4_DET (det + 0x0B4)
    #define REG_00B4_DET_REG_V2_VBY1_IN_HDE_ST_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00B4_DET_REG_V2_VBY1_IN_HDE_ST_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00C0_DET (det + 0x0C0)
    #define REG_00C0_DET_REG_O_MOD_IN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_DET (det + 0x0C4)
    #define REG_00C4_DET_REG_O_MOD_IN_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_DET (det + 0x0C8)
    #define REG_00C8_DET_REG_O_MOD_IN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_DET (det + 0x0CC)
    #define REG_00CC_DET_REG_O_MOD_IN_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_DET (det + 0x0D0)
    #define REG_00D0_DET_REG_O_MOD_IN_VTT_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_00D0_DET_REG_O_MOD_IN_VTT_CHG_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_00D0_DET_REG_O_MOD_IN_VDE_CHG_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00D0_DET_REG_O_MOD_IN_VDE_CHG_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_00D0_DET_REG_O_MOD_IN_HTT_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00D0_DET_REG_O_MOD_IN_HTT_CHG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_00D0_DET_REG_O_MOD_IN_HDE_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00D0_DET_REG_O_MOD_IN_HDE_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00D4_DET (det + 0x0D4)
    #define REG_00D4_DET_REG_O_MOD_IN_HDE_ST_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00D4_DET_REG_O_MOD_IN_HDE_ST_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00E0_DET (det + 0x0E0)
    #define REG_00E0_DET_REG_O_VBY1_IN_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_DET (det + 0x0E4)
    #define REG_00E4_DET_REG_O_VBY1_IN_VDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_DET (det + 0x0E8)
    #define REG_00E8_DET_REG_O_VBY1_IN_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_DET (det + 0x0EC)
    #define REG_00EC_DET_REG_O_VBY1_IN_HDE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_DET (det + 0x0F0)
    #define REG_00F0_DET_REG_O_VBY1_IN_VTT_CHG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_00F0_DET_REG_O_VBY1_IN_VTT_CHG_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_00F0_DET_REG_O_VBY1_IN_VDE_CHG_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00F0_DET_REG_O_VBY1_IN_VDE_CHG_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_00F0_DET_REG_O_VBY1_IN_HTT_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00F0_DET_REG_O_VBY1_IN_HTT_CHG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_00F0_DET_REG_O_VBY1_IN_HDE_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00F0_DET_REG_O_VBY1_IN_HDE_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00F4_DET (det + 0x0F4)
    #define REG_00F4_DET_REG_O_VBY1_IN_HDE_ST_CHG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00F4_DET_REG_O_VBY1_IN_HDE_ST_CHG_CNT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0120_DET (det + 0x120)
    #define REG_0120_DET_REG_DET_FREQ_DBG_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0120_DET_REG_DET_FREQ_STATUS_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0120_DET_REG_FREQ_COMP_ONEHOT Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0120_DET_REG_FREQ_COMP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0124_DET (det + 0x124)
    #define REG_0124_DET_REG_RSIDE_INC_CNT_REF Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0128_DET (det + 0x128)
    #define REG_0128_DET_REG_WSIDE_INC_CNT_REF Fld(16,0,AC_FULLW10)//[15:0]
#define REG_012C_DET (det + 0x12C)
    #define REG_012C_DET_REG_DET_FREQ_DBG_STATUS Fld(16,0,AC_FULLW10)//[15:0]

#endif
