/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_SCTCON_H
#define _DT_BINDINGS_CLK_MT5896_SCTCON_H

#define CLK_SCTCON_XTAL_12M_INT_CK	1
#define CLK_SCTCON_XTAL_24M_INT_CK	2
#define CLK_SCTCON_MCU_NONPM_INT_CK	3
#define CLK_SCTCON_RIU_NONPM_INT_CK	4
#define CLK_SCTCON_SMI_INT_CK	5
#define CLK_SCTCON_MCU_XC_INT_CK	6
#define CLK_SCTCON_RIU_XC_INT_CK	7
#define CLK_SCTCON_O_ODCLK_INT_CK	10
#define CLK_SCTCON_XC_FD_INT_CK	11
#define CLK_SCTCON_XC_FD_ABF_INT_CK	12
#define CLK_SCTCON_XC_FD_GOP0_INT_CK	13
#define CLK_SCTCON_XC_FD_DV_INT_CK	14
#define CLK_SCTCON_XC_FN_INT_CK	15
#define CLK_SCTCON_XC_FS_INT_CK	16
#define CLK_SCTCON_XC_OD_INT_CK	17
#define CLK_SCTCON_XC_OD_EDGE_INT_CK	18
#define CLK_SCTCON_XC_OD_META_INT_CK	19
#define CLK_SCTCON_XC_OD_DELTA_META_INT_CK	20
#define CLK_SCTCON_XC_OD_OSD_META_INT_CK	21
#define CLK_SCTCON_XC_OD_DIV2_INT_CK	22
#define CLK_SCTCON_XC_OD_DIV4_INT_CK	23
#define CLK_SCTCON_XC_OD_DELTA_INT_CK	24
#define CLK_SCTCON_XC_OD_OSD_INT_CK	25
#define CLK_SCTCON_XC_GOP_INT_CK	26
#define CLK_SCTCON_XC_AFBC_INT_CK	27
#define CLK_SCTCON_XC_GOP0_DST_INT_CK	28
#define CLK_SCTCON_XC_GOPC_DST_INT_CK	29
#define CLK_SCTCON_XC_GOPG_DST_INT_CK	30
#define CLK_SCTCON_XC_GOP_SCL_INT_CK	31
#define CLK_SCTCON_PANEL_GA_SRAM_INT_CK	32
#define CLK_SCTCON_PADJ_SRAM_INT_CK	33
#define CLK_SCTCON_DEMURA_SRAM_INT_CK	34
#define CLK_SCTCON_GOP0_SRAM_INT_CK	35
#define CLK_SCTCON_GOP1_SRAM_INT_CK	36
#define CLK_SCTCON_GOP2_SRAM_INT_CK	37
#define CLK_SCTCON_GOP3_SRAM_INT_CK	38
#define CLK_SCTCON_LDMCG_SRAM_INT_CK	39
#define CLK_SCTCON_LDCOMP_SRAM_INT_CK	40
#define CLK_SCTCON_LPQ_PA_SRAM_INT_CK	41
#define CLK_SCTCON_LDM_GA_SRAM_INT_CK	42
#define CLK_SCTCON_LD_EDGE2D_SRAM_INT_CK	43
#define CLK_SCTCON_OSD_DV_HW5_SRAM_INT_CK	44
#define CLK_SCTCON_NR	45

#endif
