/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#define ts_sample(x)     (x + 0x241C00)

#define reg_ts0_clk_sample ts_sample(0x0000)
#define reg_ts0_clk_sample_s 0
#define reg_ts0_clk_sample_e 7
#define reg_ts1_clk_sample ts_sample(0x0000)
#define reg_ts1_clk_sample_s 8
#define reg_ts1_clk_sample_e 15
#define reg_ts2_clk_sample ts_sample(0x0004)
#define reg_ts2_clk_sample_s 0
#define reg_ts2_clk_sample_e 7
#define reg_ts3_clk_sample ts_sample(0x0004)
#define reg_ts3_clk_sample_s 8
#define reg_ts3_clk_sample_e 15
#define reg_ts4_clk_sample ts_sample(0x0008)
#define reg_ts4_clk_sample_s 0
#define reg_ts4_clk_sample_e 7
#define reg_ts5_clk_sample ts_sample(0x0008)
#define reg_ts5_clk_sample_s 8
#define reg_ts5_clk_sample_e 15
#define reg_tso_out_clk_sample ts_sample(0x000C)
#define reg_tso_out_clk_sample_s 0
#define reg_tso_out_clk_sample_e 7
#define reg_tso_s2p_out_clk_sample ts_sample(0x0010)
#define reg_tso_s2p_out_clk_sample_s 0
#define reg_tso_s2p_out_clk_sample_e 7
#define reg_tso_s2p1_out_clk_sample ts_sample(0x0010)
#define reg_tso_s2p1_out_clk_sample_s 8
#define reg_tso_s2p1_out_clk_sample_e 15
#define reg_tso2_out_clk_sample ts_sample(0x0014)
#define reg_tso2_out_clk_sample_s 0
#define reg_tso2_out_clk_sample_e 7
#define reg_tso2_s2p_out_clk_sample ts_sample(0x0018)
#define reg_tso2_s2p_out_clk_sample_s 0
#define reg_tso2_s2p_out_clk_sample_e 7
#define reg_tso2_s2p1_out_clk_sample ts_sample(0x0018)
#define reg_tso2_s2p1_out_clk_sample_s 8
#define reg_tso2_s2p1_out_clk_sample_e 15
#define reg_stc0syn_rst ts_sample(0x0040)
#define reg_stc0syn_rst_s 0
#define reg_stc0syn_rst_e 0
#define reg_stc0_cw_sel ts_sample(0x0040)
#define reg_stc0_cw_sel_s 1
#define reg_stc0_cw_sel_e 1
#define reg_update_stc0_cw ts_sample(0x0040)
#define reg_update_stc0_cw_s 2
#define reg_update_stc0_cw_e 2
#define reg_update_dc0_freerun_cw ts_sample(0x0040)
#define reg_update_dc0_freerun_cw_s 3
#define reg_update_dc0_freerun_cw_e 3
#define reg_update_dc0_sync_cw ts_sample(0x0040)
#define reg_update_dc0_sync_cw_s 4
#define reg_update_dc0_sync_cw_e 4
#define reg_stc0_ref_div2_en ts_sample(0x0040)
#define reg_stc0_ref_div2_en_s 5
#define reg_stc0_ref_div2_en_e 5
#define reg_stc0_ntp_en ts_sample(0x0040)
#define reg_stc0_ntp_en_s 6
#define reg_stc0_ntp_en_e 6
#define reg_stc0syn_cw_0 ts_sample(0x0044)
#define reg_stc0syn_cw_0_s 0
#define reg_stc0syn_cw_0_e 15
#define reg_stc0syn_cw_1 ts_sample(0x0048)
#define reg_stc0syn_cw_1_s 0
#define reg_stc0syn_cw_1_e 15
#define reg_dc0_freerun_cw_0 ts_sample(0x004C)
#define reg_dc0_freerun_cw_0_s 0
#define reg_dc0_freerun_cw_0_e 15
#define reg_dc0_freerun_cw_1 ts_sample(0x0050)
#define reg_dc0_freerun_cw_1_s 0
#define reg_dc0_freerun_cw_1_e 15
#define reg_dc0_num ts_sample(0x0054)
#define reg_dc0_num_s 0
#define reg_dc0_num_e 15
#define reg_dc0_den ts_sample(0x0058)
#define reg_dc0_den_s 0
#define reg_dc0_den_e 15
#define reg_stc1syn_rst ts_sample(0x0060)
#define reg_stc1syn_rst_s 0
#define reg_stc1syn_rst_e 0
#define reg_stc1_cw_sel ts_sample(0x0060)
#define reg_stc1_cw_sel_s 1
#define reg_stc1_cw_sel_e 1
#define reg_update_stc1_cw ts_sample(0x0060)
#define reg_update_stc1_cw_s 2
#define reg_update_stc1_cw_e 2
#define reg_update_dc1_freerun_cw ts_sample(0x0060)
#define reg_update_dc1_freerun_cw_s 3
#define reg_update_dc1_freerun_cw_e 3
#define reg_update_dc1_sync_cw ts_sample(0x0060)
#define reg_update_dc1_sync_cw_s 4
#define reg_update_dc1_sync_cw_e 4
#define reg_stc1_ref_div2_en ts_sample(0x0060)
#define reg_stc1_ref_div2_en_s 5
#define reg_stc1_ref_div2_en_e 5
#define reg_stc1_ntp_en ts_sample(0x0060)
#define reg_stc1_ntp_en_s 6
#define reg_stc1_ntp_en_e 6
#define reg_stc1syn_cw_0 ts_sample(0x0064)
#define reg_stc1syn_cw_0_s 0
#define reg_stc1syn_cw_0_e 15
#define reg_stc1syn_cw_1 ts_sample(0x0068)
#define reg_stc1syn_cw_1_s 0
#define reg_stc1syn_cw_1_e 15
#define reg_dc1_freerun_cw_0 ts_sample(0x006C)
#define reg_dc1_freerun_cw_0_s 0
#define reg_dc1_freerun_cw_0_e 15
#define reg_dc1_freerun_cw_1 ts_sample(0x0070)
#define reg_dc1_freerun_cw_1_s 0
#define reg_dc1_freerun_cw_1_e 15
#define reg_dc1_num ts_sample(0x0074)
#define reg_dc1_num_s 0
#define reg_dc1_num_e 15
#define reg_dc1_den ts_sample(0x0078)
#define reg_dc1_den_s 0
#define reg_dc1_den_e 15
#define reg_stc2syn_rst ts_sample(0x0080)
#define reg_stc2syn_rst_s 0
#define reg_stc2syn_rst_e 0
#define reg_stc2_cw_sel ts_sample(0x0080)
#define reg_stc2_cw_sel_s 1
#define reg_stc2_cw_sel_e 1
#define reg_update_stc2_cw ts_sample(0x0080)
#define reg_update_stc2_cw_s 2
#define reg_update_stc2_cw_e 2
#define reg_update_dc2_freerun_cw ts_sample(0x0080)
#define reg_update_dc2_freerun_cw_s 3
#define reg_update_dc2_freerun_cw_e 3
#define reg_update_dc2_sync_cw ts_sample(0x0080)
#define reg_update_dc2_sync_cw_s 4
#define reg_update_dc2_sync_cw_e 4
#define reg_stc2_ref_div2_en ts_sample(0x0080)
#define reg_stc2_ref_div2_en_s 5
#define reg_stc2_ref_div2_en_e 5
#define reg_stc2_ntp_en ts_sample(0x0080)
#define reg_stc2_ntp_en_s 6
#define reg_stc2_ntp_en_e 6
#define reg_stc2syn_cw_0 ts_sample(0x0084)
#define reg_stc2syn_cw_0_s 0
#define reg_stc2syn_cw_0_e 15
#define reg_stc2syn_cw_1 ts_sample(0x0088)
#define reg_stc2syn_cw_1_s 0
#define reg_stc2syn_cw_1_e 15
#define reg_dc2_freerun_cw_0 ts_sample(0x008C)
#define reg_dc2_freerun_cw_0_s 0
#define reg_dc2_freerun_cw_0_e 15
#define reg_dc2_freerun_cw_1 ts_sample(0x0090)
#define reg_dc2_freerun_cw_1_s 0
#define reg_dc2_freerun_cw_1_e 15
#define reg_dc2_num ts_sample(0x0094)
#define reg_dc2_num_s 0
#define reg_dc2_num_e 15
#define reg_dc2_den ts_sample(0x0098)
#define reg_dc2_den_s 0
#define reg_dc2_den_e 15
#define reg_stc3syn_rst ts_sample(0x00A0)
#define reg_stc3syn_rst_s 0
#define reg_stc3syn_rst_e 0
#define reg_stc3_cw_sel ts_sample(0x00A0)
#define reg_stc3_cw_sel_s 1
#define reg_stc3_cw_sel_e 1
#define reg_update_stc3_cw ts_sample(0x00A0)
#define reg_update_stc3_cw_s 2
#define reg_update_stc3_cw_e 2
#define reg_update_dc3_freerun_cw ts_sample(0x00A0)
#define reg_update_dc3_freerun_cw_s 3
#define reg_update_dc3_freerun_cw_e 3
#define reg_update_dc3_sync_cw ts_sample(0x00A0)
#define reg_update_dc3_sync_cw_s 4
#define reg_update_dc3_sync_cw_e 4
#define reg_stc3_ref_div2_en ts_sample(0x00A0)
#define reg_stc3_ref_div2_en_s 5
#define reg_stc3_ref_div2_en_e 5
#define reg_stc3_ntp_en ts_sample(0x00A0)
#define reg_stc3_ntp_en_s 6
#define reg_stc3_ntp_en_e 6
#define reg_stc3syn_cw_0 ts_sample(0x00A4)
#define reg_stc3syn_cw_0_s 0
#define reg_stc3syn_cw_0_e 15
#define reg_stc3syn_cw_1 ts_sample(0x00A8)
#define reg_stc3syn_cw_1_s 0
#define reg_stc3syn_cw_1_e 15
#define reg_dc3_freerun_cw_0 ts_sample(0x00AC)
#define reg_dc3_freerun_cw_0_s 0
#define reg_dc3_freerun_cw_0_e 15
#define reg_dc3_freerun_cw_1 ts_sample(0x00B0)
#define reg_dc3_freerun_cw_1_s 0
#define reg_dc3_freerun_cw_1_e 15
#define reg_dc3_num ts_sample(0x00B4)
#define reg_dc3_num_s 0
#define reg_dc3_num_e 15
#define reg_dc3_den ts_sample(0x00B8)
#define reg_dc3_den_s 0
#define reg_dc3_den_e 15
#define reg_ckg_tso2_mmt ts_sample(0x00C0)
#define reg_ckg_tso2_mmt_s 0
#define reg_ckg_tso2_mmt_e 7
#define reg_ckg_tso2_ch1 ts_sample(0x00C0)
#define reg_ckg_tso2_ch1_s 8
#define reg_ckg_tso2_ch1_e 15
#define reg_ckg_tso2_ch2 ts_sample(0x00C4)
#define reg_ckg_tso2_ch2_s 0
#define reg_ckg_tso2_ch2_e 7
#define reg_ckg_tso2_ch3 ts_sample(0x00C4)
#define reg_ckg_tso2_ch3_s 8
#define reg_ckg_tso2_ch3_e 15
#define reg_ckg_tso2_ch4 ts_sample(0x00C8)
#define reg_ckg_tso2_ch4_s 0
#define reg_ckg_tso2_ch4_e 7
#define reg_ckg_tso2_ch5 ts_sample(0x00C8)
#define reg_ckg_tso2_ch5_s 8
#define reg_ckg_tso2_ch5_e 15
#define reg_ckg_tso2_ch6 ts_sample(0x00CC)
#define reg_ckg_tso2_ch6_s 0
#define reg_ckg_tso2_ch6_e 7
#define reg_ckg_tso2_s2p ts_sample(0x00D0)
#define reg_ckg_tso2_s2p_s 0
#define reg_ckg_tso2_s2p_e 7
#define reg_ckg_tso2_s2p1 ts_sample(0x00D0)
#define reg_ckg_tso2_s2p1_s 8
#define reg_ckg_tso2_s2p1_e 15
#define reg_ckg_ts_tlv0 ts_sample(0x00D4)
#define reg_ckg_ts_tlv0_s 0
#define reg_ckg_ts_tlv0_e 7
#define reg_ckg_ts_tlv1 ts_sample(0x00D4)
#define reg_ckg_ts_tlv1_s 8
#define reg_ckg_ts_tlv1_e 15
#define reg_ckg_ts_tlv2 ts_sample(0x00D8)
#define reg_ckg_ts_tlv2_s 0
#define reg_ckg_ts_tlv2_e 7
#define reg_ckg_ts0 ts_sample(0x0138)
#define reg_ckg_ts0_s 0
#define reg_ckg_ts0_e 7
#define reg_ckg_ts1 ts_sample(0x0138)
#define reg_ckg_ts1_s 8
#define reg_ckg_ts1_e 15
#define reg_ckg_ts2 ts_sample(0x013C)
#define reg_ckg_ts2_s 0
#define reg_ckg_ts2_e 7
#define reg_ckg_tso_s2p ts_sample(0x013C)
#define reg_ckg_tso_s2p_s 8
#define reg_ckg_tso_s2p_e 15
#define reg_ckg_tso_s2p1 ts_sample(0x0140)
#define reg_ckg_tso_s2p1_s 0
#define reg_ckg_tso_s2p1_e 7
#define reg_ckg_tsfi ts_sample(0x0140)
#define reg_ckg_tsfi_s 8
#define reg_ckg_tsfi_e 15
#define reg_ckg_ts_alp0 ts_sample(0x0144)
#define reg_ckg_ts_alp0_s 0
#define reg_ckg_ts_alp0_e 7
#define reg_ckg_ts_alp1 ts_sample(0x0144)
#define reg_ckg_ts_alp1_s 8
#define reg_ckg_ts_alp1_e 15
#define reg_ckg_ts_alp2 ts_sample(0x0148)
#define reg_ckg_ts_alp2_s 0
#define reg_ckg_ts_alp2_e 7
#define reg_ckg_ts_alp_fi ts_sample(0x0148)
#define reg_ckg_ts_alp_fi_s 8
#define reg_ckg_ts_alp_fi_e 15
#define reg_ckg_tso_mmt ts_sample(0x014C)
#define reg_ckg_tso_mmt_s 0
#define reg_ckg_tso_mmt_e 7
#define reg_ckg_tso_ch1 ts_sample(0x014C)
#define reg_ckg_tso_ch1_s 8
#define reg_ckg_tso_ch1_e 15
#define reg_ckg_tso_ch2 ts_sample(0x0150)
#define reg_ckg_tso_ch2_s 0
#define reg_ckg_tso_ch2_e 7
#define reg_ckg_tso_ch3 ts_sample(0x0150)
#define reg_ckg_tso_ch3_s 8
#define reg_ckg_tso_ch3_e 15
#define reg_ckg_tso_ch4 ts_sample(0x0154)
#define reg_ckg_tso_ch4_s 0
#define reg_ckg_tso_ch4_e 7
#define reg_ckg_tso_ch5 ts_sample(0x0154)
#define reg_ckg_tso_ch5_s 8
#define reg_ckg_tso_ch5_e 15
#define reg_ckg_tso_ch6 ts_sample(0x0158)
#define reg_ckg_tso_ch6_s 0
#define reg_ckg_tso_ch6_e 7
#define reg_ckg_ts_tx_c1 ts_sample(0x0164)
#define reg_ckg_ts_tx_c1_s 0
#define reg_ckg_ts_tx_c1_e 5
#define reg_clk_ts_tx_c1_ext_div8 ts_sample(0x0164)
#define reg_clk_ts_tx_c1_ext_div8_s 6
#define reg_clk_ts_tx_c1_ext_div8_e 7
#define reg_ckg_ts_tx_c2 ts_sample(0x0164)
#define reg_ckg_ts_tx_c2_s 8
#define reg_ckg_ts_tx_c2_e 13
#define reg_clk_ts_tx_c2_ext_div8 ts_sample(0x0164)
#define reg_clk_ts_tx_c2_ext_div8_s 14
#define reg_clk_ts_tx_c2_ext_div8_e 15
#define reg_ckg_2b_rx_int ts_sample(0x0168)
#define reg_ckg_2b_rx_int_s 8
#define reg_ckg_2b_rx_int_e 11
#define reg_ckg_2b_tx ts_sample(0x0168)
#define reg_ckg_2b_tx_s 12
#define reg_ckg_2b_tx_e 15
#define reg_ckg_cilink_if ts_sample(0x016C)
#define reg_ckg_cilink_if_s 0
#define reg_ckg_cilink_if_e 3
#define reg_clk_2b_tx_ext_inv ts_sample(0x0170)
#define reg_clk_2b_tx_ext_inv_s 0
#define reg_clk_2b_tx_ext_inv_e 0
#define reg_ckg_tso_out ts_sample(0x0178)
#define reg_ckg_tso_out_s 0
#define reg_ckg_tso_out_e 7
#define reg_ckg_p_tso_src_sel ts_sample(0x0178)
#define reg_ckg_p_tso_src_sel_s 8
#define reg_ckg_p_tso_src_sel_e 15
#define reg_clk_tso_out_divnum ts_sample(0x017C)
#define reg_clk_tso_out_divnum_s 0
#define reg_clk_tso_out_divnum_e 7
#define reg_clk_tso_out_ph_tun_num ts_sample(0x017C)
#define reg_clk_tso_out_ph_tun_num_s 8
#define reg_clk_tso_out_ph_tun_num_e 15
#define reg_clk_tso_out_div_sel ts_sample(0x0180)
#define reg_clk_tso_out_div_sel_s 0
#define reg_clk_tso_out_div_sel_e 1
#define reg_clk_tso_out_ph_tun_en ts_sample(0x0180)
#define reg_clk_tso_out_ph_tun_en_s 2
#define reg_clk_tso_out_ph_tun_en_e 2
#define reg_clk_tso_out_div_mn_load ts_sample(0x0184)
#define reg_clk_tso_out_div_mn_load_s 15
#define reg_clk_tso_out_div_mn_load_e 15
#define reg_clk_tso_out_div_mn_n ts_sample(0x0184)
#define reg_clk_tso_out_div_mn_n_s 0
#define reg_clk_tso_out_div_mn_n_e 12
#define reg_clk_tso_out_div_mn_m ts_sample(0x0188)
#define reg_clk_tso_out_div_mn_m_s 0
#define reg_clk_tso_out_div_mn_m_e 7
#define reg_clk_tso_topad_inv ts_sample(0x018C)
#define reg_clk_tso_topad_inv_s 0
#define reg_clk_tso_topad_inv_e 0
#define reg_ckg_ts_sample ts_sample(0x018C)
#define reg_ckg_ts_sample_s 8
#define reg_ckg_ts_sample_e 15
#define reg_ckg_tso_trace ts_sample(0x0190)
#define reg_ckg_tso_trace_s 0
#define reg_ckg_tso_trace_e 7
#define reg_ckg_tso_trace_in ts_sample(0x0190)
#define reg_ckg_tso_trace_in_s 8
#define reg_ckg_tso_trace_in_e 15
#define reg_ckg_tso2_out ts_sample(0x0194)
#define reg_ckg_tso2_out_s 0
#define reg_ckg_tso2_out_e 7
#define reg_ckg_p_tso2_src_sel ts_sample(0x0194)
#define reg_ckg_p_tso2_src_sel_s 8
#define reg_ckg_p_tso2_src_sel_e 15
#define reg_clk_tso2_out_divnum ts_sample(0x0198)
#define reg_clk_tso2_out_divnum_s 0
#define reg_clk_tso2_out_divnum_e 7
#define reg_clk_tso2_out_ph_tun_num ts_sample(0x0198)
#define reg_clk_tso2_out_ph_tun_num_s 8
#define reg_clk_tso2_out_ph_tun_num_e 15
#define reg_clk_tso2_out_div_sel ts_sample(0x019C)
#define reg_clk_tso2_out_div_sel_s 0
#define reg_clk_tso2_out_div_sel_e 1
#define reg_clk_tso2_out_ph_tun_en ts_sample(0x019C)
#define reg_clk_tso2_out_ph_tun_en_s 2
#define reg_clk_tso2_out_ph_tun_en_e 2
#define reg_clk_tso2_out_div_mn_load ts_sample(0x01A0)
#define reg_clk_tso2_out_div_mn_load_s 15
#define reg_clk_tso2_out_div_mn_load_e 15
#define reg_clk_tso2_out_div_mn_n ts_sample(0x01A0)
#define reg_clk_tso2_out_div_mn_n_s 0
#define reg_clk_tso2_out_div_mn_n_e 12
#define reg_clk_tso2_out_div_mn_m ts_sample(0x01A4)
#define reg_clk_tso2_out_div_mn_m_s 0
#define reg_clk_tso2_out_div_mn_m_e 7
#define reg_clk_tso2_topad_inv ts_sample(0x01A8)
#define reg_clk_tso2_topad_inv_s 0
#define reg_clk_tso2_topad_inv_e 0
#define reg_ckg_tso2_trace ts_sample(0x01AC)
#define reg_ckg_tso2_trace_s 0
#define reg_ckg_tso2_trace_e 7
#define reg_ckg_tso2_trace_in ts_sample(0x01AC)
#define reg_ckg_tso2_trace_in_s 8
#define reg_ckg_tso2_trace_in_e 15
#define reg_clk_gating_ip_tsp ts_sample(0x01C0)
#define reg_clk_gating_ip_tsp_s 0
#define reg_clk_gating_ip_tsp_e 15
#define reg_clk_gating_ip_tso ts_sample(0x01C4)
#define reg_clk_gating_ip_tso_s 0
#define reg_clk_gating_ip_tso_e 15
#define reg_clk_gating_ip_dscrmb ts_sample(0x01C8)
#define reg_clk_gating_ip_dscrmb_s 0
#define reg_clk_gating_ip_dscrmb_e 15
#define reg_ts_sample_debug_0 ts_sample(0x01F4)
#define reg_ts_sample_debug_0_s 0
#define reg_ts_sample_debug_0_e 15
#define reg_ts_sample_debug_1 ts_sample(0x01F8)
#define reg_ts_sample_debug_1_s 0
#define reg_ts_sample_debug_1_e 7
#define reg_debug_sel ts_sample(0x01FC)
#define reg_debug_sel_s 0
#define reg_debug_sel_e 15
