#ifndef DISP_LB_BKA326_H
#define DISP_LB_BKA326_H

#define DISP_LB_BKA326 0x01464C00

//Page DISP_LB_BKA326
#define REG_0004_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x004)
    #define REG_0004_DISP_LB_BKA326_REG_DISPLAY_RDY_ACK_LINE_DIFF Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_0004_DISP_LB_BKA326_REG_DISPLAY_UNDERRUN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x008)
    #define REG_0008_DISP_LB_BKA326_REG_DISPLAY_UNDERRUN_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0008_DISP_LB_BKA326_REG_DISPLAY_UNDERRUN_CLR_P Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0018_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x018)
    #define REG_0018_DISP_LB_BKA326_REG_DISP_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_001C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x01C)
    #define REG_001C_DISP_LB_BKA326_REG_DISP_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0040_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x040)
    #define REG_0040_DISP_LB_BKA326_REG_H_PROTECT_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0040_DISP_LB_BKA326_REG_H_PROTECT_MODE Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0044_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x044)
    #define REG_0044_DISP_LB_BKA326_REG_H_PROTECT_HSIZE_USR Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_0044_DISP_LB_BKA326_REG_H_PROTECT_HSIZE_USR_MD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0048_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x048)
    #define REG_0048_DISP_LB_BKA326_REG_CUT_POINT_PRE_USR Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_0048_DISP_LB_BKA326_REG_CUT_POINT_USR_MD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_004C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x04C)
    #define REG_004C_DISP_LB_BKA326_REG_CUT_POINT_POST_USR Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0084_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x084)
    #define REG_0084_DISP_LB_BKA326_REG_PAT_R_MONITOR Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0088_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x088)
    #define REG_0088_DISP_LB_BKA326_REG_PAT_G_MONITOR Fld(12,0,AC_MSKW10)//[11:0]
#define REG_008C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x08C)
    #define REG_008C_DISP_LB_BKA326_REG_PAT_B_MONITOR Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0094_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x094)
    #define REG_0094_DISP_LB_BKA326_REG_PAT_COLOR_R Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0098_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x098)
    #define REG_0098_DISP_LB_BKA326_REG_PAT_COLOR_G Fld(12,0,AC_MSKW10)//[11:0]
#define REG_009C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x09C)
    #define REG_009C_DISP_LB_BKA326_REG_PAT_COLOR_B Fld(12,0,AC_MSKW10)//[11:0]
#define REG_00A0_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0A0)
    #define REG_00A0_DISP_LB_BKA326_REG_PAT_MONITOR_H Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A4_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0A4)
    #define REG_00A4_DISP_LB_BKA326_REG_PAT_MONITOR_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A8_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0A8)
    #define REG_00A8_DISP_LB_BKA326_REG_PAT_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_00A8_DISP_LB_BKA326_REG_PAT_USR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00AC_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0AC)
    #define REG_00AC_DISP_LB_BKA326_REG_PAT_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00B0_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0B0)
    #define REG_00B0_DISP_LB_BKA326_REG_PAT_DATA_SEL Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_00B0_DISP_LB_BKA326_REG_PAT_COLOR Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_00B0_DISP_LB_BKA326_REG_PAT_DELTA Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00B0_DISP_LB_BKA326_REG_PAT_GEN_CTRL_EN Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00B4_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0B4)
    #define REG_00B4_DISP_LB_BKA326_REG_PAT_SC_FACTOR Fld(9,0,AC_MSKW10)//[8:0]
    #define REG_00B4_DISP_LB_BKA326_REG_PAT_SEED Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00B8_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0B8)
    #define REG_00B8_DISP_LB_BKA326_REG_PAT_T_CTRL Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_00B8_DISP_LB_BKA326_REG_PAT_COLOR_FLAT Fld(12,0,AC_MSKW10)//[11:0]
#define REG_00BC_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0BC)
    #define REG_00BC_DISP_LB_BKA326_REG_DISP_PAT_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C4_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0C4)
    #define REG_00C4_DISP_LB_BKA326_REG_PAT_VCNT Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_00C4_DISP_LB_BKA326_REG_PAT_VCNT_EQ Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C8_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0C8)
    #define REG_00C8_DISP_LB_BKA326_REG_PAT_HCNT Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_00C8_DISP_LB_BKA326_REG_PAT_HCNT_EQ Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00CC_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0CC)
    #define REG_00CC_DISP_LB_BKA326_REG_PAT_CRC_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00D0_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x0D0)
    #define REG_00D0_DISP_LB_BKA326_REG_PAT_CRC_OUT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x100)
    #define REG_0100_DISP_LB_BKA326_REG_R_VALUE Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_0100_DISP_LB_BKA326_REG_BOUNDARY_MD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0104_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x104)
    #define REG_0104_DISP_LB_BKA326_REG_G_VALUE Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0108_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x108)
    #define REG_0108_DISP_LB_BKA326_REG_B_VALUE Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_0108_DISP_LB_BKA326_REG_H_CROP_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0108_DISP_LB_BKA326_REG_V_CROP_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0108_DISP_LB_BKA326_REG_HV_INSERT_ENABLE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_010C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x10C)
    #define REG_010C_DISP_LB_BKA326_REG_H_ST Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0110_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x110)
    #define REG_0110_DISP_LB_BKA326_REG_H_LENGTH Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0114_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x114)
    #define REG_0114_DISP_LB_BKA326_REG_INS_BLK_HPRE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0118_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x118)
    #define REG_0118_DISP_LB_BKA326_REG_HFDE_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_011C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x11C)
    #define REG_011C_DISP_LB_BKA326_REG_VCROP_ACK_MD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_011C_DISP_LB_BKA326_REG_DE_START_TRIG_MD Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_011C_DISP_LB_BKA326_REG_SW_TRIG_DE_START Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_011C_DISP_LB_BKA326_REG_HW_RD_TRIG_DE_START Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0120_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x120)
    #define REG_0120_DISP_LB_BKA326_REG_INS_BLK_VS_DELAY_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_012C_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x12C)
    #define REG_012C_DISP_LB_BKA326_REG_V_ST Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0130_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x130)
    #define REG_0130_DISP_LB_BKA326_REG_V_LENGTH Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0134_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x134)
    #define REG_0134_DISP_LB_BKA326_REG_INS_BLK_VPRE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0138_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x138)
    #define REG_0138_DISP_LB_BKA326_REG_VFDE_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01C0_DISP_LB_BKA326 (DISP_LB_BKA326 + 0x1C0)
    #define REG_01C0_DISP_LB_BKA326_REG_DISP_SRC_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01C0_DISP_LB_BKA326_REG_DISP_DST_SW_RST Fld(1,1,AC_MSKB0)//[1:1]

#endif