/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_SCSCL_H
#define _DT_BINDINGS_CLK_MT5896_SCSCL_H

#define CLK_SCSCL_XTAL_12M_INT_CK	1
#define CLK_SCSCL_XTAL_24M_INT_CK	2
#define CLK_SCSCL_MCU_NONPM_INT_CK	3
#define CLK_SCSCL_RIU_NONPM_INT_CK	4
#define CLK_SCSCL_V2_ODCLK_INT_CK	6
#define CLK_SCSCL_SMI_INT_CK	7
#define CLK_SCSCL_MCU_XC_INT_CK	8
#define CLK_SCSCL_RIU_XC_INT_CK	9
#define CLK_SCSCL_MCU_BUS_INT_CK	10
#define CLK_SCSCL_XC_FD_INT_CK	11
#define CLK_SCSCL_XC_OD_INT_CK	12
#define CLK_SCSCL_XC_OD_DELTA_INT_CK	13
#define CLK_SCSCL_XC_FS_INT_CK	14
#define CLK_SCSCL_XC_FN_INT_CK	15
#define CLK_SCSCL_HSY_SP_SRAM_INT_CK	16
#define CLK_SCSCL_HSY_SP3_SRAM_INT_CK	17
#define CLK_SCSCL_HVSP_STP2_SRAM_INT_CK	18
#define CLK_SCSCL_HVSP_STP1_SRAM_INT_CK	19
#define CLK_SCSCL_VIP_PQ_SRAM_INT_CK	20
#define CLK_SCSCL_GUCD_18_SRAM_INT_CK	21
#define CLK_SCSCL_GUCD_256_SRAM_INT_CK	22
#define CLK_SCSCL_DELTA_B2P_SRAM_INT_CK	23
#define CLK_SCSCL_LCE_SCL_SRAM_INT_CK	24
#define CLK_SCSCL_NR	25

#endif
