#ifndef _GOPG_HVSP4_BK_H
#define _GOPG_HVSP4_BK_H

#define GOPG_HVSP4_BKA4DA 0x0149B400

//Page GOPG_HVSP4_BKA4DA
#define REG_0004_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x004)
    #define REG_0004_GOPG_HVSP4_BKA4DA_REG_INI_FACTOR_HO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0008_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x008)
    #define REG_0008_GOPG_HVSP4_BKA4DA_REG_INI_FACTOR_HO_1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_000C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x00C)
    #define REG_000C_GOPG_HVSP4_BKA4DA_REG_INI_FACTOR_VE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0010_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x010)
    #define REG_0010_GOPG_HVSP4_BKA4DA_REG_INI_FACTOR_VE_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_001C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x01C)
    #define REG_001C_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_HO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x020)
    #define REG_0020_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_HO_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0020_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_HO_MSB Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_0020_GOPG_HVSP4_BKA4DA_REG_SCALE_HO_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0020_GOPG_HVSP4_BKA4DA_REG_H_SHIFT_MODE_EN Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0024_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x024)
    #define REG_0024_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_VE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x028)
    #define REG_0028_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_VE_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0028_GOPG_HVSP4_BKA4DA_REG_SCALE_VE_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0028_GOPG_HVSP4_BKA4DA_REG_V_SHIFT_MODE_EN Fld(1,9,AC_MSKB1)//[9:9]
#define REG_002C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x02C)
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_MODE_Y_HO Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_MODE_C_HO Fld(2,1,AC_MSKB0)//[2:1]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_MODE_A_HO Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_C_RAM_EN_HO Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_Y_RAM_EN_HO Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_MODE_Y_VE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_MODE_C_VE Fld(2,9,AC_MSKB1)//[10:9]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_MODE_A_VE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_C_RAM_EN_VE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_002C_GOPG_HVSP4_BKA4DA_REG_Y_RAM_EN_VE Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0030_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x030)
    #define REG_0030_GOPG_HVSP4_BKA4DA_REG_HSP_DITH_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0030_GOPG_HVSP4_BKA4DA_REG_VSP_DITH_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0030_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_EN_C Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0030_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_EN_Y Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0030_GOPG_HVSP4_BKA4DA_REG_VSP_CORING_EN_C Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0030_GOPG_HVSP4_BKA4DA_REG_VSP_CORING_EN_Y Fld(1,11,AC_MSKB1)//[11:11]
#define REG_0034_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x034)
    #define REG_0034_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_TH_C Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0034_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_TH_Y Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0038_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x038)
    #define REG_0038_GOPG_HVSP4_BKA4DA_REG_VSP_CORING_TH_C Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0038_GOPG_HVSP4_BKA4DA_REG_VSP_CORING_TH_Y Fld(5,8,AC_MSKB1)//[12:8]
#define REG_003C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x03C)
    #define REG_003C_GOPG_HVSP4_BKA4DA_REG_VSP_ALPHA_BLD_A_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_003C_GOPG_HVSP4_BKA4DA_REG_VSP_ALPHA_BLD_RGB_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_003C_GOPG_HVSP4_BKA4DA_REG_HSP_ALPHA_BLD_A_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_003C_GOPG_HVSP4_BKA4DA_REG_HSP_ALPHA_BLD_RGB_EN Fld(1,3,AC_MSKB0)//[3:3]
#define REG_004C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x04C)
    #define REG_004C_GOPG_HVSP4_BKA4DA_REG_HSP_6TAP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_004C_GOPG_HVSP4_BKA4DA_REG_HSP_8TAP_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_004C_GOPG_HVSP4_BKA4DA_REG_HSP_10TAP_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0050_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x050)
    #define REG_0050_GOPG_HVSP4_BKA4DA_REG_COEF0_00_Y_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0054_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x054)
    #define REG_0054_GOPG_HVSP4_BKA4DA_REG_COEF1_00_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0058_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x058)
    #define REG_0058_GOPG_HVSP4_BKA4DA_REG_COEF2_00_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_005C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x05C)
    #define REG_005C_GOPG_HVSP4_BKA4DA_REG_COEF3_00_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0060_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x060)
    #define REG_0060_GOPG_HVSP4_BKA4DA_REG_COEF4_00_Y_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0064_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x064)
    #define REG_0064_GOPG_HVSP4_BKA4DA_REG_COEF0_25_Y_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0068_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x068)
    #define REG_0068_GOPG_HVSP4_BKA4DA_REG_COEF1_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_006C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x06C)
    #define REG_006C_GOPG_HVSP4_BKA4DA_REG_COEF2_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0070_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x070)
    #define REG_0070_GOPG_HVSP4_BKA4DA_REG_COEF3_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0074_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x074)
    #define REG_0074_GOPG_HVSP4_BKA4DA_REG_COEF4_25_Y_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0078_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x078)
    #define REG_0078_GOPG_HVSP4_BKA4DA_REG_COEF5_25_Y_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_007C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x07C)
    #define REG_007C_GOPG_HVSP4_BKA4DA_REG_COEF6_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0080_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x080)
    #define REG_0080_GOPG_HVSP4_BKA4DA_REG_COEF7_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0084_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x084)
    #define REG_0084_GOPG_HVSP4_BKA4DA_REG_COEF8_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0088_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x088)
    #define REG_0088_GOPG_HVSP4_BKA4DA_REG_COEF9_25_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_008C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x08C)
    #define REG_008C_GOPG_HVSP4_BKA4DA_REG_COEF0_50_Y_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0090_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x090)
    #define REG_0090_GOPG_HVSP4_BKA4DA_REG_COEF1_50_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0094_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x094)
    #define REG_0094_GOPG_HVSP4_BKA4DA_REG_COEF2_50_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0098_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x098)
    #define REG_0098_GOPG_HVSP4_BKA4DA_REG_COEF3_50_Y_H Fld(10,0,AC_MSKW10)//[9:0]
#define REG_009C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x09C)
    #define REG_009C_GOPG_HVSP4_BKA4DA_REG_COEF4_50_Y_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00A0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0A0)
    #define REG_00A0_GOPG_HVSP4_BKA4DA_REG_H_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0A4)
    #define REG_00A4_GOPG_HVSP4_BKA4DA_REG_V_SIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0A8)
    #define REG_00A8_GOPG_HVSP4_BKA4DA_REG_SCL_H_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00AC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0AC)
    #define REG_00AC_GOPG_HVSP4_BKA4DA_REG_SCL_V_SIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00B0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0B0)
    #define REG_00B0_GOPG_HVSP4_BKA4DA_REG_DEBUG_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_00B0_GOPG_HVSP4_BKA4DA_REG_H_SIZE_RPT Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00B4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0B4)
    #define REG_00B4_GOPG_HVSP4_BKA4DA_REG_V_SIZE_RPT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00B8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0B8)
    #define REG_00B8_GOPG_HVSP4_BKA4DA_REG_SCL_H_SIZE_RPT Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00BC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0BC)
    #define REG_00BC_GOPG_HVSP4_BKA4DA_REG_SCL_V_SIZE_RPT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00C0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0C0)
    #define REG_00C0_GOPG_HVSP4_BKA4DA_REG_COEF0_00_C_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00C4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0C4)
    #define REG_00C4_GOPG_HVSP4_BKA4DA_REG_COEF1_00_C_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00C8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0C8)
    #define REG_00C8_GOPG_HVSP4_BKA4DA_REG_COEF0_25_C_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00CC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0CC)
    #define REG_00CC_GOPG_HVSP4_BKA4DA_REG_COEF1_25_C_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00D0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0D0)
    #define REG_00D0_GOPG_HVSP4_BKA4DA_REG_COEF2_25_C_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00D4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0D4)
    #define REG_00D4_GOPG_HVSP4_BKA4DA_REG_COEF3_25_C_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00D8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0D8)
    #define REG_00D8_GOPG_HVSP4_BKA4DA_REG_COEF0_50_C_H Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00DC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0DC)
    #define REG_00DC_GOPG_HVSP4_BKA4DA_REG_COEF1_50_C_H Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00E0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0E0)
    #define REG_00E0_GOPG_HVSP4_BKA4DA_REG_COEF0_00_Y_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00E4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0E4)
    #define REG_00E4_GOPG_HVSP4_BKA4DA_REG_COEF1_00_Y_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00E8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0E8)
    #define REG_00E8_GOPG_HVSP4_BKA4DA_REG_COEF0_25_Y_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00EC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0EC)
    #define REG_00EC_GOPG_HVSP4_BKA4DA_REG_COEF1_25_Y_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00F0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0F0)
    #define REG_00F0_GOPG_HVSP4_BKA4DA_REG_COEF2_25_Y_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00F4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0F4)
    #define REG_00F4_GOPG_HVSP4_BKA4DA_REG_COEF3_25_Y_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00F8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0F8)
    #define REG_00F8_GOPG_HVSP4_BKA4DA_REG_COEF0_50_Y_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00FC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x0FC)
    #define REG_00FC_GOPG_HVSP4_BKA4DA_REG_COEF1_50_Y_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0100_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x100)
    #define REG_0100_GOPG_HVSP4_BKA4DA_REG_COEF0_00_C_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0104_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x104)
    #define REG_0104_GOPG_HVSP4_BKA4DA_REG_COEF1_00_C_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0108_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x108)
    #define REG_0108_GOPG_HVSP4_BKA4DA_REG_COEF0_25_C_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_010C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x10C)
    #define REG_010C_GOPG_HVSP4_BKA4DA_REG_COEF1_25_C_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0110_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x110)
    #define REG_0110_GOPG_HVSP4_BKA4DA_REG_COEF2_25_C_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0114_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x114)
    #define REG_0114_GOPG_HVSP4_BKA4DA_REG_COEF3_25_C_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0118_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x118)
    #define REG_0118_GOPG_HVSP4_BKA4DA_REG_COEF0_50_C_V Fld(9,0,AC_MSKW10)//[8:0]
#define REG_011C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x11C)
    #define REG_011C_GOPG_HVSP4_BKA4DA_REG_COEF1_50_C_V Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0144_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x144)
    #define REG_0144_GOPG_HVSP4_BKA4DA_REG_PSEUDO_VCLR_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0144_GOPG_HVSP4_BKA4DA_REG_PSEUDO_VCLR_NO Fld(2,1,AC_MSKB0)//[2:1]
#define REG_014C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x14C)
    #define REG_014C_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_OFF Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_014C_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_GAIN Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_014C_GOPG_HVSP4_BKA4DA_REG_HSP_CORING_TH_UP Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_014C_GOPG_HVSP4_BKA4DA_REG_HSP_4TAP_BLEND_USER_MD Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_014C_GOPG_HVSP4_BKA4DA_REG_HSP_4TAP_BLEND_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0180_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x180)
    #define REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_BYPASS Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_BUFFER_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_ORDER_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_USR_MD Fld(1,4,AC_MSKB0)//[4:4]
#define REG_0188_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x188)
    #define REG_0188_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_EFFECT_MODE Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0188_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_DETECT_MODE Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0188_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_WEIGHT_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0188_GOPG_HVSP4_BKA4DA_REG_VSP_DE_RING_EFFECT_MODE Fld(2,8,AC_MSKB1)//[9:8]
#define REG_018C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x18C)
    #define REG_018C_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_W_OGAIN Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_018C_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_W_UGAIN Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0190_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x190)
    #define REG_0190_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_DIFF_OFFSET Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_0190_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_DIFF_GAIN Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0194_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x194)
    #define REG_0194_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_MIN_OFFSET Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0194_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_MIN_GAIN Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0194_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_GAIN Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0198_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x198)
    #define REG_0198_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_GAIN_OFFSET Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0198_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_SHORT_WIN_OFFSET Fld(4,4,AC_MSKB0)//[7:4]
#define REG_019C_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x19C)
    #define REG_019C_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_COMPLEX_DIFF_OFFSET Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_019C_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_COMPLEX_DIFF_GAIN Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01A0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1A0)
    #define REG_01A0_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_COMPLEX_MIN_OFFSET Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01A0_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_COMPLEX_MIN_GAIN Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_01A0_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_COMPLEX_GAIN Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_01A0_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_WIN_OVERLAP_1_PIXEL Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01A4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1A4)
    #define REG_01A4_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_DIFF_GAIN Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01A4_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_FLAT_W_OFFSET_C Fld(5,4,AC_MSKW10)//[8:4]
    #define REG_01A4_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_FLAT_W_OFFSET_N Fld(5,10,AC_MSKB1)//[14:10]
#define REG_01A8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1A8)
    #define REG_01A8_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_FLAT_W_GAIN Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_01A8_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_FLAT_W_SIG_GAIN Fld(7,8,AC_MSKB1)//[14:8]
#define REG_01AC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1AC)
    #define REG_01AC_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_FLAT_W_VAR_GAIN Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_01AC_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_FLAT_W_MINMAX_GAIN Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01B0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1B0)
    #define REG_01B0_GOPG_HVSP4_BKA4DA_REG_MODE_Y_HO_4TAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_01B4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1B4)
    #define REG_01B4_GOPG_HVSP4_BKA4DA_REG_COEF0_00_Y_H_4TAP Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01B8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1B8)
    #define REG_01B8_GOPG_HVSP4_BKA4DA_REG_COEF1_00_Y_H_4TAP Fld(11,0,AC_MSKW10)//[10:0]
#define REG_01BC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1BC)
    #define REG_01BC_GOPG_HVSP4_BKA4DA_REG_COEF0_25_Y_H_4TAP Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01C0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1C0)
    #define REG_01C0_GOPG_HVSP4_BKA4DA_REG_COEF1_25_Y_H_4TAP Fld(11,0,AC_MSKW10)//[10:0]
#define REG_01C4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1C4)
    #define REG_01C4_GOPG_HVSP4_BKA4DA_REG_COEF2_25_Y_H_4TAP Fld(11,0,AC_MSKW10)//[10:0]
#define REG_01C8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1C8)
    #define REG_01C8_GOPG_HVSP4_BKA4DA_REG_COEF3_25_Y_H_4TAP Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01CC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1CC)
    #define REG_01CC_GOPG_HVSP4_BKA4DA_REG_COEF0_50_Y_H_4TAP Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01D0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1D0)
    #define REG_01D0_GOPG_HVSP4_BKA4DA_REG_COEF1_50_Y_H_4TAP Fld(11,0,AC_MSKW10)//[10:0]
#define REG_01D4_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1D4)
    #define REG_01D4_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_UNDER_SHOOT Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_01D4_GOPG_HVSP4_BKA4DA_REG_HSP_DE_RING_OVER_SHOOT Fld(5,8,AC_MSKB1)//[12:8]
#define REG_01D8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1D8)
    #define REG_01D8_GOPG_HVSP4_BKA4DA_REG_VSP_DE_RING_UNDER_SHOOT Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_01D8_GOPG_HVSP4_BKA4DA_REG_VSP_DE_RING_OVER_SHOOT Fld(5,8,AC_MSKB1)//[12:8]
#define REG_01E0_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1E0)
    #define REG_01E0_GOPG_HVSP4_BKA4DA_REG_DELTA_HVSD_INPUT_UNDERRUN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01E0_GOPG_HVSP4_BKA4DA_REG_DELTA_HVSD_INPUT_UNDERRUN_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01E0_GOPG_HVSP4_BKA4DA_REG_DELTA_HVSD_INPUT_UNDERRUN_CLR_P Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01E0_GOPG_HVSP4_BKA4DA_REG_DELTA_HVSD_OUTPUT_UNDERRUN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01E0_GOPG_HVSP4_BKA4DA_REG_DELTA_HVSD_OUTPUT_UNDERRUN_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01E0_GOPG_HVSP4_BKA4DA_REG_DELTA_HVSD_OUTPUT_UNDERRUN_CLR_P Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01F8_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1F8)
    #define REG_01F8_GOPG_HVSP4_BKA4DA_REG_HVSP_SW_TRIG_P Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01F8_GOPG_HVSP4_BKA4DA_REG_HVSP_SW_TRIG_MODE Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01FC_GOPG_HVSP4_BKA4DA (GOPG_HVSP4_BKA4DA + 0x1FC)
    #define REG_01FC_GOPG_HVSP4_BKA4DA_REG_HVSP_IP_SWRST Fld(1,0,AC_MSKB0)//[0:0]

#endif
