#ifndef _CKGEN00_H
#define _CKGEN00_H

#define ckgen00 0x00204000

//Page CKGEN00_1
#define REG_0000_CKGEN00 (ckgen00 + 0x000)
    #define REG_0000_CKGEN00_REG_CKG_CALC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0008_CKGEN00 (ckgen00 + 0x008)
    #define REG_0008_CKGEN00_REG_CKG_CORECLK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0010_CKGEN00 (ckgen00 + 0x010)
    #define REG_0010_CKGEN00_REG_CKG_CORECLK_MID Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0018_CKGEN00 (ckgen00 + 0x018)
    #define REG_0018_CKGEN00_REG_CKG_SCLK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0020_CKGEN00 (ckgen00 + 0x020)
    #define REG_0020_CKGEN00_REG_CKG_SCLK_MID Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0028_CKGEN00 (ckgen00 + 0x028)
    #define REG_0028_CKGEN00_REG_CKG_BIU Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0030_CKGEN00 (ckgen00 + 0x030)
    #define REG_0030_CKGEN00_REG_CKG_CALC_MCUSYS Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0038_CKGEN00 (ckgen00 + 0x038)
    #define REG_0038_CKGEN00_REG_CKG_EMI0_MCUSYS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0040_CKGEN00 (ckgen00 + 0x040)
    #define REG_0040_CKGEN00_REG_CKG_EMI1_MCUSYS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0048_CKGEN00 (ckgen00 + 0x048)
    #define REG_0048_CKGEN00_REG_CKG_EMI2_MCUSYS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0050_CKGEN00 (ckgen00 + 0x050)
    #define REG_0050_CKGEN00_REG_CKG_MIPS_SYN_ARMPLL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0054_CKGEN00 (ckgen00 + 0x054)
    #define REG_0054_CKGEN00_REG_CKG_MIPS_SYN_ARM2PLL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0058_CKGEN00 (ckgen00 + 0x058)
    #define REG_0058_CKGEN00_REG_CKG_XTAL_MPLL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0060_CKGEN00 (ckgen00 + 0x060)
    #define REG_0060_CKGEN00_REG_CKG_PTP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0068_CKGEN00 (ckgen00 + 0x068)
    #define REG_0068_CKGEN00_REG_CKG_LZMA_MCUSYS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0070_CKGEN00 (ckgen00 + 0x070)
    #define REG_0070_CKGEN00_REG_CKG_MPU_MCUSYS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_00C0_CKGEN00_REG_CKG_BRIDGE_GPU_NODIE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_00C8_CKGEN00_REG_CKG_GPU_GPU_DIE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00CC_CKGEN00 (ckgen00 + 0x0CC)
    #define REG_00CC_CKGEN00_REG_FLOW_CTRL_RATE_GPU_PAR_GP_00CC Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00CC_CKGEN00_REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD_00CC Fld(1,12,AC_MSKB1)//[12:12]
#define REG_00D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_00D0_CKGEN00_REG_CKG_SHADER_CORE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_00D8_CKGEN00_REG_CKG_MIPS_SYN_ARMPLL_GPU Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_00F0_CKGEN00_REG_CKG_AIA_BUS Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00F0_CKGEN00_REG_CKG_AIA_BUS_AIA Fld(2,8,AC_MSKB1)//[9:8]
#define REG_00F4_CKGEN00 (ckgen00 + 0x0F4)
    #define REG_00F4_CKGEN00_REG_CKG_MIPS_SYN_ARMPLL_APU Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0100_CKGEN00 (ckgen00 + 0x100)
    #define REG_0100_CKGEN00_REG_CKG_MDLA Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0100_CKGEN00_REG_CKG_MDLA_AIA Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0108_CKGEN00 (ckgen00 + 0x108)
    #define REG_0108_CKGEN00_REG_CKG_XTAL_24M_AIA Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0110_CKGEN00 (ckgen00 + 0x110)
    #define REG_0110_CKGEN00_REG_CKG_EMI2_AIA Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0120_CKGEN00 (ckgen00 + 0x120)
    #define REG_0120_CKGEN00_REG_CKG_DRAMC_CH0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0128_CKGEN00 (ckgen00 + 0x128)
    #define REG_0128_CKGEN00_REG_CKG_DRAMC_CH2 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0130_CKGEN00 (ckgen00 + 0x130)
    #define REG_0130_CKGEN00_REG_CKG_DRAMC_CH4 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0138_CKGEN00 (ckgen00 + 0x138)
    #define REG_0138_CKGEN00_REG_CKG_DRAMC0_CGCLK_FAST_CHA Fld(2,0,AC_MSKB0)//[1:0]
#define REG_013C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_013C_CKGEN00_REG_CKG_DRAMC0_CGCLK_FAST_CHC_013C Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0140_CKGEN00 (ckgen00 + 0x140)
    #define REG_0140_CKGEN00_REG_CKG_XTAL_24M_DRAMC0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0148_CKGEN00 (ckgen00 + 0x148)
    #define REG_0148_CKGEN00_REG_CKG_DRAMC1_CGCLK_FAST_CHA Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0150_CKGEN00 (ckgen00 + 0x150)
    #define REG_0150_CKGEN00_REG_CKG_XTAL_24M_DRAMC1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0158_CKGEN00 (ckgen00 + 0x158)
    #define REG_0158_CKGEN00_REG_CKG_DRAMC2_CGCLK_FAST_CHA Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0160_CKGEN00 (ckgen00 + 0x160)
    #define REG_0160_CKGEN00_REG_CKG_XTAL_24M_DRAMC2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0168_CKGEN00 (ckgen00 + 0x168)
    #define REG_0168_CKGEN00_REG_CKG_EMI0_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0170_CKGEN00 (ckgen00 + 0x170)
    #define REG_0170_CKGEN00_REG_CKG_EMI1_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0178_CKGEN00 (ckgen00 + 0x178)
    #define REG_0178_CKGEN00_REG_CKG_EMI2_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0180_CKGEN00 (ckgen00 + 0x180)
    #define REG_0180_CKGEN00_REG_CKG_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0188_CKGEN00 (ckgen00 + 0x188)
    #define REG_0188_CKGEN00_REG_CKG_EMI0_DEB_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0190_CKGEN00 (ckgen00 + 0x190)
    #define REG_0190_CKGEN00_REG_CKG_EMI1_DEB_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0198_CKGEN00 (ckgen00 + 0x198)
    #define REG_0198_CKGEN00_REG_CKG_EMI2_DEB_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_01A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_01A0_CKGEN00_REG_CKG_XTAL_12M_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_01A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_01A8_CKGEN00_REG_CKG_XTAL_24M_IP_WRAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_01B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_01B0_CKGEN00_REG_CKG_DRAMC0_PLL54M_108M_01B0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_01D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_01D8_CKGEN00_REG_CKG_SMI Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01D8_CKGEN00_REG_CKG_SMI_DEMOD0 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01D8_CKGEN00_REG_CKG_SMI_FRCIOPMRV55 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01D8_CKGEN00_REG_CKG_SMI_FRCMEHALO Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01DC_CKGEN00 (ckgen00 + 0x1DC)
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCACE Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCIP Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCMW Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCNR Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCPQ Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCSCL Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCSR Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01DC_CKGEN00_REG_CKG_SMI_SCTCON Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_01E0_CKGEN00_REG_CKG_SMI_SCDV Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01E0_CKGEN00_REG_CKG_SMI_VDEC_SOC Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01E0_CKGEN00_REG_CKG_SMI_VDEC_CORE0 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01E0_CKGEN00_REG_CKG_SMI_VDEC_CORE1 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01E0_CKGEN00_REG_CKG_SMI_VDEC_CORE2 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01E0_CKGEN00_REG_CKG_SMI_RV55AUDIO Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01E4_CKGEN00 (ckgen00 + 0x1E4)
    #define REG_01E4_CKGEN00_REG_CKG_SMI_AUDIO_R2 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01E4_CKGEN00_REG_CKG_SMI_AIA Fld(2,6,AC_MSKB0)//[7:6]
#define REG_01E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_01E8_CKGEN00_REG_CKG_VIVA_SMI Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01E8_CKGEN00_REG_CKG_SMI_MHEG5 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01E8_CKGEN00_REG_CKG_SMI_HDMIRX Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01E8_CKGEN00_REG_CKG_SMI_TSP Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01E8_CKGEN00_REG_CKG_SMI_RV55FRC Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01E8_CKGEN00_REG_CKG_SMI_RV55PQU Fld(2,12,AC_MSKB1)//[13:12]
#define REG_01EC_CKGEN00 (ckgen00 + 0x1EC)
    #define REG_01EC_CKGEN00_REG_CKG_SMI_FRCCORE1_01EC Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01EC_CKGEN00_REG_CKG_SMI_FRCCORE2_01EC Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01EC_CKGEN00_REG_CKG_SMI_FRCCORE3_01EC Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01EC_CKGEN00_REG_CKG_SMI_FRCMISC_01EC Fld(2,6,AC_MSKB0)//[7:6]
#define REG_01F4_CKGEN00 (ckgen00 + 0x1F4)
    #define REG_01F4_CKGEN00_REG_CKG_VIVA_SMI_BRG_01F4 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0260_CKGEN00 (ckgen00 + 0x060)
    #define REG_0260_CKGEN00_REG_CKG_FRC_IMI Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0260_CKGEN00_REG_CKG_FRC_IMI_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0260_CKGEN00_REG_CKG_FRC_IMI_RV55FRC Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0260_CKGEN00_REG_CKG_FRC_IMI_RV55PQU Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0268_CKGEN00 (ckgen00 + 0x068)
    #define REG_0268_CKGEN00_REG_CKG_IMI Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0268_CKGEN00_REG_CKG_IMI_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0270_CKGEN00 (ckgen00 + 0x070)
    #define REG_0270_CKGEN00_REG_CKG_LZMA Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0278_CKGEN00 (ckgen00 + 0x078)
    #define REG_0278_CKGEN00_REG_CKG_XTAL_12M Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0278_CKGEN00_REG_CKG_XTAL_12M_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0278_CKGEN00_REG_CKG_XTAL_12M_GPU_DIE Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0280_CKGEN00 (ckgen00 + 0x080)
    #define REG_0280_CKGEN00_REG_CKG_XTAL_24M Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0280_CKGEN00_REG_CKG_XTAL_24M_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0280_CKGEN00_REG_CKG_XTAL_24M_GPU_DIE Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0280_CKGEN00_REG_CKG_XTAL_24M_GPU_NODIE Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0280_CKGEN00_REG_CKG_XTAL_24M_GPU_SHADER Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0284_CKGEN00 (ckgen00 + 0x084)
    #define REG_0284_CKGEN00_REG_CKG_XTAL_24M_TSP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_02B8_CKGEN00_REG_CKG_DEMOD_ADC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_02C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_02C0_CKGEN00_REG_CKG_XTAL_12M_DEMOD0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_02C8_CKGEN00_REG_CKG_XTAL_24M_DEMOD0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_02D0_CKGEN00_REG_CKG_ACIFIR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_02D8_CKGEN00_REG_CKG_ADCD Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_02E0_CKGEN00_REG_CKG_ATSC200_PH1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_02E8_CKGEN00_REG_CKG_ATSC200_PH3 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_02F0_CKGEN00_REG_CKG_ATSC25 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_02F8_CKGEN00_REG_CKG_ATSC400 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0300_CKGEN00 (ckgen00 + 0x100)
    #define REG_0300_CKGEN00_REG_CKG_ATSC50 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0308_CKGEN00 (ckgen00 + 0x108)
    #define REG_0308_CKGEN00_REG_CKG_ATSC_ADCD_SYNC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0310_CKGEN00 (ckgen00 + 0x110)
    #define REG_0310_CKGEN00_REG_CKG_ATSC_CE25 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0318_CKGEN00 (ckgen00 + 0x118)
    #define REG_0318_CKGEN00_REG_CKG_ATSC_EQ25 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0320_CKGEN00 (ckgen00 + 0x120)
    #define REG_0320_CKGEN00_REG_CKG_DMD_DMA Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0328_CKGEN00 (ckgen00 + 0x128)
    #define REG_0328_CKGEN00_REG_CKG_DTMB_ADC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0330_CKGEN00 (ckgen00 + 0x130)
    #define REG_0330_CKGEN00_REG_CKG_DTMB_BCH_DEMOD0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0338_CKGEN00 (ckgen00 + 0x138)
    #define REG_0338_CKGEN00_REG_CKG_DTMB_EQ0P25X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0340_CKGEN00 (ckgen00 + 0x140)
    #define REG_0340_CKGEN00_REG_CKG_DTMB_EQ0P5X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0348_CKGEN00 (ckgen00 + 0x148)
    #define REG_0348_CKGEN00_REG_CKG_DTMB_EQ1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0350_CKGEN00 (ckgen00 + 0x150)
    #define REG_0350_CKGEN00_REG_CKG_DTMB_EQ2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0358_CKGEN00 (ckgen00 + 0x158)
    #define REG_0358_CKGEN00_REG_CKG_DTMB_EQ2X_INNER12X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0360_CKGEN00 (ckgen00 + 0x160)
    #define REG_0360_CKGEN00_REG_CKG_DTMB_EQ2X_INNER2X_12X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0368_CKGEN00 (ckgen00 + 0x168)
    #define REG_0368_CKGEN00_REG_CKG_DTMB_EQ2X_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0370_CKGEN00 (ckgen00 + 0x170)
    #define REG_0370_CKGEN00_REG_CKG_DTMB_INNER12X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0378_CKGEN00 (ckgen00 + 0x178)
    #define REG_0378_CKGEN00_REG_CKG_DTMB_INNER12X_EQ0P25X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0380_CKGEN00 (ckgen00 + 0x180)
    #define REG_0380_CKGEN00_REG_CKG_DTMB_INNER12X_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0388_CKGEN00 (ckgen00 + 0x188)
    #define REG_0388_CKGEN00_REG_CKG_DTMB_INNER12X_INNER6X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0390_CKGEN00 (ckgen00 + 0x190)
    #define REG_0390_CKGEN00_REG_CKG_DTMB_INNER12X_INNER8X_TAP_COM Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0398_CKGEN00 (ckgen00 + 0x198)
    #define REG_0398_CKGEN00_REG_CKG_DTMB_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_03A0_CKGEN00_REG_CKG_DTMB_INNER1X_ATSC25 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_03A8_CKGEN00_REG_CKG_DTMB_INNER24X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_03B0_CKGEN00_REG_CKG_DTMB_INNER24X_ATSC_400 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_03B8_CKGEN00_REG_CKG_DTMB_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_03C0_CKGEN00_REG_CKG_DTMB_INNER2X_4X_SR1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_03C8_CKGEN00_REG_CKG_DTMB_INNER2X_SR0P5X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_03D0_CKGEN00_REG_CKG_DTMB_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_03D8_CKGEN00_REG_CKG_DTMB_INNER4X_ATSC50 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_03E0_CKGEN00_REG_CKG_DTMB_INNER4X_SR1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_03E8_CKGEN00_REG_CKG_DTMB_INNER6X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_03F0_CKGEN00_REG_CKG_DTMB_INNER8X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_03F8_CKGEN00_REG_CKG_DTMB_INNER8X_TAP_COM Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0400_CKGEN00 (ckgen00 + 0x000)
    #define REG_0400_CKGEN00_REG_CKG_DTMB_LDPC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0408_CKGEN00 (ckgen00 + 0x008)
    #define REG_0408_CKGEN00_REG_CKG_DTMB_LDPC2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0410_CKGEN00 (ckgen00 + 0x010)
    #define REG_0410_CKGEN00_REG_CKG_DTMB_OUTER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0418_CKGEN00 (ckgen00 + 0x018)
    #define REG_0418_CKGEN00_REG_CKG_DTMB_OUTER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0420_CKGEN00 (ckgen00 + 0x020)
    #define REG_0420_CKGEN00_REG_CKG_DTMB_OUTER8X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0428_CKGEN00 (ckgen00 + 0x028)
    #define REG_0428_CKGEN00_REG_CKG_DTMB_SRAM_DUMP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0430_CKGEN00 (ckgen00 + 0x030)
    #define REG_0430_CKGEN00_REG_CKG_DVBS2_BCH Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0438_CKGEN00 (ckgen00 + 0x038)
    #define REG_0438_CKGEN00_REG_CKG_DVBS2_DISEQC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0440_CKGEN00 (ckgen00 + 0x040)
    #define REG_0440_CKGEN00_REG_CKG_DVBS2_INNER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0448_CKGEN00 (ckgen00 + 0x048)
    #define REG_0448_CKGEN00_REG_CKG_DVBS2_OPPRO Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0450_CKGEN00 (ckgen00 + 0x050)
    #define REG_0450_CKGEN00_REG_CKG_DVBS_OUTER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0458_CKGEN00 (ckgen00 + 0x058)
    #define REG_0458_CKGEN00_REG_CKG_DVBS_OUTER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0460_CKGEN00 (ckgen00 + 0x060)
    #define REG_0460_CKGEN00_REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0468_CKGEN00 (ckgen00 + 0x068)
    #define REG_0468_CKGEN00_REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0470_CKGEN00 (ckgen00 + 0x070)
    #define REG_0470_CKGEN00_REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_MIU Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0478_CKGEN00 (ckgen00 + 0x078)
    #define REG_0478_CKGEN00_REG_CKG_DVBT2_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0480_CKGEN00 (ckgen00 + 0x080)
    #define REG_0480_CKGEN00_REG_CKG_DVBT2_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0488_CKGEN00 (ckgen00 + 0x088)
    #define REG_0488_CKGEN00_REG_CKG_DVBT2_INNER2X_SRD0P5X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0490_CKGEN00 (ckgen00 + 0x090)
    #define REG_0490_CKGEN00_REG_CKG_DVBT2_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0498_CKGEN00 (ckgen00 + 0x098)
    #define REG_0498_CKGEN00_REG_CKG_DVBT2_INNER4X_DVBTC_RS Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_04A0_CKGEN00_REG_CKG_DVBT2_INNER4X_S2_INNER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_04A8_CKGEN00_REG_CKG_DVBT_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_04B0_CKGEN00_REG_CKG_DVBT_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_04B8_CKGEN00_REG_CKG_DVBT_INNER2X_SRD0P5X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_04C0_CKGEN00_REG_CKG_DVBT_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_04C8_CKGEN00_REG_CKG_DVBT_OUTER1X_DEMOD0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_04D0_CKGEN00_REG_CKG_DVBT_OUTER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_04D8_CKGEN00_REG_CKG_DVBTC_ADC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_04E0_CKGEN00_REG_CKG_DVBTC_OUTER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_04E8_CKGEN00_REG_CKG_DVBTC_OUTER2X_ISDBT_OUTER_RS Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_04F0_CKGEN00_REG_CKG_DVBTC_RS Fld(2,0,AC_MSKB0)//[1:0]
#define REG_04F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_04F8_CKGEN00_REG_CKG_DVBTC_SRAM1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0500_CKGEN00 (ckgen00 + 0x100)
    #define REG_0500_CKGEN00_REG_CKG_DVBTC_SRAM3 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0508_CKGEN00 (ckgen00 + 0x108)
    #define REG_0508_CKGEN00_REG_CKG_DVBTC_SRAM4 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0510_CKGEN00 (ckgen00 + 0x110)
    #define REG_0510_CKGEN00_REG_CKG_DVBTC_TS Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0518_CKGEN00 (ckgen00 + 0x118)
    #define REG_0518_CKGEN00_REG_CKG_DVBTM_ADC0P5X_EQ0P5X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0520_CKGEN00 (ckgen00 + 0x120)
    #define REG_0520_CKGEN00_REG_CKG_DVBTM_ADC1X_EQ1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0528_CKGEN00 (ckgen00 + 0x128)
    #define REG_0528_CKGEN00_REG_CKG_DVBTM_SRAM_ADC_T22X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0530_CKGEN00 (ckgen00 + 0x130)
    #define REG_0530_CKGEN00_REG_CKG_DVBTM_SRAM_ADC_T22X_DVBTC_RS Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0538_CKGEN00 (ckgen00 + 0x138)
    #define REG_0538_CKGEN00_REG_CKG_DVBTM_SRAM_T11X_T22X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0540_CKGEN00 (ckgen00 + 0x140)
    #define REG_0540_CKGEN00_REG_CKG_DVBTM_SRAM_T11X_T24X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0548_CKGEN00 (ckgen00 + 0x148)
    #define REG_0548_CKGEN00_REG_CKG_DVBTM_SRAM_T12X_T22X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0550_CKGEN00 (ckgen00 + 0x150)
    #define REG_0550_CKGEN00_REG_CKG_DVBTM_SRAM_T12X_T24X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0558_CKGEN00 (ckgen00 + 0x158)
    #define REG_0558_CKGEN00_REG_CKG_DVBTM_SRAM_T12X_T24X_S2INNER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0560_CKGEN00 (ckgen00 + 0x160)
    #define REG_0560_CKGEN00_REG_CKG_DVBTM_SRAM_T12X_T24X_SRD1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0568_CKGEN00 (ckgen00 + 0x168)
    #define REG_0568_CKGEN00_REG_CKG_DVBTM_SRAM_T14X_T24X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0570_CKGEN00 (ckgen00 + 0x170)
    #define REG_0570_CKGEN00_REG_CKG_DVBTM_SRAM_T14X_T24X_S2INNER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0578_CKGEN00 (ckgen00 + 0x178)
    #define REG_0578_CKGEN00_REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0580_CKGEN00 (ckgen00 + 0x180)
    #define REG_0580_CKGEN00_REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0588_CKGEN00 (ckgen00 + 0x188)
    #define REG_0588_CKGEN00_REG_CKG_DVBTM_SRAM_T1OUTER1X_T24X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0590_CKGEN00 (ckgen00 + 0x190)
    #define REG_0590_CKGEN00_REG_CKG_ISDBT_INNER1X Fld(2,0,AC_MSKB0)//[1:0]

//Page CKGEN00_2
#define REG_0598_CKGEN00 (ckgen00 + 0x198)
    #define REG_0598_CKGEN00_REG_CKG_ISDBT_INNER1X_DVBT_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_05A0_CKGEN00_REG_CKG_ISDBT_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_05A8_CKGEN00_REG_CKG_ISDBT_INNER2X_DVBT_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_05B0_CKGEN00_REG_CKG_ISDBT_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_05B8_CKGEN00_REG_CKG_ISDBT_INNER4X_DVBT_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_05C0_CKGEN00_REG_CKG_ISDBT_INNER4X_DVBT_INNER4X_ADC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_05C8_CKGEN00_REG_CKG_ISDBT_OUTER12X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_05D0_CKGEN00_REG_CKG_ISDBT_OUTER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_05D8_CKGEN00_REG_CKG_ISDBT_OUTER1X_DVBT_OUTER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_05E0_CKGEN00_REG_CKG_ISDBT_OUTER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_05E8_CKGEN00_REG_CKG_ISDBT_OUTER6X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_05F0_CKGEN00_REG_CKG_ISDBT_OUTER6X_DVBT_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_05F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_05F8_CKGEN00_REG_CKG_ISDBT_OUTER6X_DVBT_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0600_CKGEN00 (ckgen00 + 0x000)
    #define REG_0600_CKGEN00_REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0608_CKGEN00 (ckgen00 + 0x008)
    #define REG_0608_CKGEN00_REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X_C Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0610_CKGEN00 (ckgen00 + 0x010)
    #define REG_0610_CKGEN00_REG_CKG_ISDBT_OUTER_RS Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0640_CKGEN00 (ckgen00 + 0x040)
    #define REG_0640_CKGEN00_REG_CKG_SRAM_SHARE_00_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0648_CKGEN00 (ckgen00 + 0x048)
    #define REG_0648_CKGEN00_REG_CKG_SRAM_SHARE_00_1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0650_CKGEN00 (ckgen00 + 0x050)
    #define REG_0650_CKGEN00_REG_CKG_SRAM_SHARE_01_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0658_CKGEN00 (ckgen00 + 0x058)
    #define REG_0658_CKGEN00_REG_CKG_SRAM_SHARE_02_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0660_CKGEN00 (ckgen00 + 0x060)
    #define REG_0660_CKGEN00_REG_CKG_SRAM_SHARE_03_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0668_CKGEN00 (ckgen00 + 0x068)
    #define REG_0668_CKGEN00_REG_CKG_SRAM_SHARE_03_1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0670_CKGEN00 (ckgen00 + 0x070)
    #define REG_0670_CKGEN00_REG_CKG_SRAM_SHARE_04_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0678_CKGEN00 (ckgen00 + 0x078)
    #define REG_0678_CKGEN00_REG_CKG_SRAM_SHARE_04_1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0680_CKGEN00 (ckgen00 + 0x080)
    #define REG_0680_CKGEN00_REG_CKG_SRAM_SHARE_05 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0688_CKGEN00 (ckgen00 + 0x088)
    #define REG_0688_CKGEN00_REG_CKG_SRAM_SHARE_06 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0690_CKGEN00 (ckgen00 + 0x090)
    #define REG_0690_CKGEN00_REG_CKG_SRAM_SHARE_07 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0698_CKGEN00 (ckgen00 + 0x098)
    #define REG_0698_CKGEN00_REG_CKG_SRAM_SHARE_08 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_06A0_CKGEN00_REG_CKG_SRAM_SHARE_09 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_06A8_CKGEN00_REG_CKG_SRAM_SHARE_10 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_06B0_CKGEN00_REG_CKG_SRAM_SHARE_11 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_06B8_CKGEN00_REG_CKG_SRAM_SHARE_12 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_06C0_CKGEN00_REG_CKG_SRAM_SHARE_13 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_06C8_CKGEN00_REG_CKG_SRAM_SHARE_14_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_06D0_CKGEN00_REG_CKG_SRAM_SHARE_14_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_06D8_CKGEN00_REG_CKG_SRAM_SHARE_15_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_06E0_CKGEN00_REG_CKG_SRAM_SHARE_15_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_06E8_CKGEN00_REG_CKG_SRAM_SHARE_16 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_06F0_CKGEN00_REG_CKG_SRAM_SHARE_18 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_06F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_06F8_CKGEN00_REG_CKG_SRAM_SHARE_19 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0700_CKGEN00 (ckgen00 + 0x100)
    #define REG_0700_CKGEN00_REG_CKG_SRAM_SHARE_20 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0708_CKGEN00 (ckgen00 + 0x108)
    #define REG_0708_CKGEN00_REG_CKG_SRAM_SHARE_21 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0710_CKGEN00 (ckgen00 + 0x110)
    #define REG_0710_CKGEN00_REG_CKG_SRAM_SHARE_22 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0718_CKGEN00 (ckgen00 + 0x118)
    #define REG_0718_CKGEN00_REG_CKG_SRAM_SHARE_23 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0720_CKGEN00 (ckgen00 + 0x120)
    #define REG_0720_CKGEN00_REG_CKG_SRAM_SHARE_24 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0728_CKGEN00 (ckgen00 + 0x128)
    #define REG_0728_CKGEN00_REG_CKG_SRAM_SHARE_26 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0730_CKGEN00 (ckgen00 + 0x130)
    #define REG_0730_CKGEN00_REG_CKG_SRAM_SHARE_27 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0738_CKGEN00 (ckgen00 + 0x138)
    #define REG_0738_CKGEN00_REG_CKG_SRAM_SHARE_28 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0740_CKGEN00 (ckgen00 + 0x140)
    #define REG_0740_CKGEN00_REG_CKG_SRAM_SHARE_29 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0748_CKGEN00 (ckgen00 + 0x148)
    #define REG_0748_CKGEN00_REG_CKG_SRAM_SHARE_34 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0750_CKGEN00 (ckgen00 + 0x150)
    #define REG_0750_CKGEN00_REG_CKG_SRAM_SHARE_35 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0758_CKGEN00 (ckgen00 + 0x158)
    #define REG_0758_CKGEN00_REG_CKG_SRAM_SHARE_36 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0760_CKGEN00 (ckgen00 + 0x160)
    #define REG_0760_CKGEN00_REG_CKG_SRAM_SHARE_40 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0768_CKGEN00 (ckgen00 + 0x168)
    #define REG_0768_CKGEN00_REG_CKG_SRAM_SHARE_42 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0770_CKGEN00 (ckgen00 + 0x170)
    #define REG_0770_CKGEN00_REG_CKG_SRAM_SHARE_44 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0778_CKGEN00 (ckgen00 + 0x178)
    #define REG_0778_CKGEN00_REG_CKG_SRAM_SHARE_46 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0780_CKGEN00 (ckgen00 + 0x180)
    #define REG_0780_CKGEN00_REG_CKG_SRAM_SHARE_47 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0788_CKGEN00 (ckgen00 + 0x188)
    #define REG_0788_CKGEN00_REG_CKG_SRAM_SHARE_50_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0790_CKGEN00 (ckgen00 + 0x190)
    #define REG_0790_CKGEN00_REG_CKG_SRAM_SHARE_52_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0798_CKGEN00 (ckgen00 + 0x198)
    #define REG_0798_CKGEN00_REG_CKG_SRAM_SHARE_53_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_07A0_CKGEN00_REG_CKG_SRAM_SHARE_55_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_07A8_CKGEN00_REG_CKG_SRAM_SHARE_56 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_07B0_CKGEN00_REG_CKG_SRAM_SHARE_57 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_07B8_CKGEN00_REG_CKG_SRAM_SHARE_58 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_07C0_CKGEN00_REG_CKG_SRAM_SHARE_59 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_07C8_CKGEN00_REG_CKG_SRAM_SHARE_60 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_07D0_CKGEN00_REG_CKG_SRAM_SHARE_61 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_07D8_CKGEN00_REG_CKG_SRAM_SHARE_62 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_07E0_CKGEN00_REG_CKG_SRAM_SHARE_64 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_07E8_CKGEN00_REG_CKG_SRAM_SHARE_66 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_07F0_CKGEN00_REG_CKG_SRAM_SHARE_67 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_07F8_CKGEN00_REG_CKG_SRAM_SHARE_68_0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0800_CKGEN00 (ckgen00 + 0x000)
    #define REG_0800_CKGEN00_REG_CKG_SRAM_SHARE_68_2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0808_CKGEN00 (ckgen00 + 0x008)
    #define REG_0808_CKGEN00_REG_CKG_SRAM_SHARE_69_0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0810_CKGEN00 (ckgen00 + 0x010)
    #define REG_0810_CKGEN00_REG_CKG_SRAM_SHARE_70 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0818_CKGEN00 (ckgen00 + 0x018)
    #define REG_0818_CKGEN00_REG_CKG_SRAM_SHARE_71 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0820_CKGEN00 (ckgen00 + 0x020)
    #define REG_0820_CKGEN00_REG_CKG_SRAM_SHARE_77 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0828_CKGEN00 (ckgen00 + 0x028)
    #define REG_0828_CKGEN00_REG_CKG_SRAM_SHARE_79 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0830_CKGEN00 (ckgen00 + 0x030)
    #define REG_0830_CKGEN00_REG_CKG_SRAM_SHARE_81 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0838_CKGEN00 (ckgen00 + 0x038)
    #define REG_0838_CKGEN00_REG_CKG_SRAM_SHARE_85 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0840_CKGEN00 (ckgen00 + 0x040)
    #define REG_0840_CKGEN00_REG_CKG_SRAM_SHARE_87 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0848_CKGEN00 (ckgen00 + 0x048)
    #define REG_0848_CKGEN00_REG_CKG_SRAM_SHARE_89 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0850_CKGEN00 (ckgen00 + 0x050)
    #define REG_0850_CKGEN00_REG_CKG_SRAM_SHARE_91 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0858_CKGEN00 (ckgen00 + 0x058)
    #define REG_0858_CKGEN00_REG_CKG_SRAM_SHARE_92 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0860_CKGEN00 (ckgen00 + 0x060)
    #define REG_0860_CKGEN00_REG_CKG_SRAM_SHARE_93 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0868_CKGEN00 (ckgen00 + 0x068)
    #define REG_0868_CKGEN00_REG_CKG_SRAM_SHARE_94 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0870_CKGEN00 (ckgen00 + 0x070)
    #define REG_0870_CKGEN00_REG_CKG_SRAM_SHARE_96 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0878_CKGEN00 (ckgen00 + 0x078)
    #define REG_0878_CKGEN00_REG_CKG_SRAM_SHARE_98 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0880_CKGEN00 (ckgen00 + 0x080)
    #define REG_0880_CKGEN00_REG_CKG_SRAM_SHARE_99 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0888_CKGEN00 (ckgen00 + 0x088)
    #define REG_0888_CKGEN00_REG_CKG_SRAM_SHARE_100 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0890_CKGEN00 (ckgen00 + 0x090)
    #define REG_0890_CKGEN00_REG_CKG_SRAM_SHARE_103 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0898_CKGEN00 (ckgen00 + 0x098)
    #define REG_0898_CKGEN00_REG_CKG_SRAM_SHARE_105 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_08A0_CKGEN00_REG_CKG_SRAM_SHARE_107 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_08A8_CKGEN00_REG_CKG_SRAM_SHARE_109 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_08B0_CKGEN00_REG_CKG_SRAM_SHARE_110 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_08B8_CKGEN00_REG_CKG_SRAM_SHARE_111 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_08C0_CKGEN00_REG_CKG_SRAM_SHARE_112 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_08C8_CKGEN00_REG_CKG_SRAM_SHARE_124 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_08D0_CKGEN00_REG_CKG_SRAM_SHARE_128 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_08D8_CKGEN00_REG_CKG_SRAM_SHARE_129 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_08E0_CKGEN00_REG_CKG_SRAM_SHARE_130 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_08E8_CKGEN00_REG_CKG_SRAM_SHARE_131 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_08F0_CKGEN00_REG_CKG_SRAM_SHARE_132 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_08F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_08F8_CKGEN00_REG_CKG_SRAM_SHARE_134_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0900_CKGEN00 (ckgen00 + 0x100)
    #define REG_0900_CKGEN00_REG_CKG_SRAM_SHARE_134_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0908_CKGEN00 (ckgen00 + 0x108)
    #define REG_0908_CKGEN00_REG_CKG_SRAM_SHARE_136_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0910_CKGEN00 (ckgen00 + 0x110)
    #define REG_0910_CKGEN00_REG_CKG_SRAM_SHARE_136_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0918_CKGEN00 (ckgen00 + 0x118)
    #define REG_0918_CKGEN00_REG_CKG_SRAM_SHARE_137_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0920_CKGEN00 (ckgen00 + 0x120)
    #define REG_0920_CKGEN00_REG_CKG_SRAM_SHARE_137_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0928_CKGEN00 (ckgen00 + 0x128)
    #define REG_0928_CKGEN00_REG_CKG_SRAM_SHARE_138_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0930_CKGEN00 (ckgen00 + 0x130)
    #define REG_0930_CKGEN00_REG_CKG_SRAM_SHARE_138_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0938_CKGEN00 (ckgen00 + 0x138)
    #define REG_0938_CKGEN00_REG_CKG_SRAM_SHARE_139_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0940_CKGEN00 (ckgen00 + 0x140)
    #define REG_0940_CKGEN00_REG_CKG_SRAM_SHARE_139_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0948_CKGEN00 (ckgen00 + 0x148)
    #define REG_0948_CKGEN00_REG_CKG_SRAM_SHARE_140_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0950_CKGEN00 (ckgen00 + 0x150)
    #define REG_0950_CKGEN00_REG_CKG_SRAM_SHARE_140_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0958_CKGEN00 (ckgen00 + 0x158)
    #define REG_0958_CKGEN00_REG_CKG_SRAM_SHARE_141_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0960_CKGEN00 (ckgen00 + 0x160)
    #define REG_0960_CKGEN00_REG_CKG_SRAM_SHARE_141_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0968_CKGEN00 (ckgen00 + 0x168)
    #define REG_0968_CKGEN00_REG_CKG_SRAM_SHARE_142_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0970_CKGEN00 (ckgen00 + 0x170)
    #define REG_0970_CKGEN00_REG_CKG_SRAM_SHARE_142_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0978_CKGEN00 (ckgen00 + 0x178)
    #define REG_0978_CKGEN00_REG_CKG_SRAM_SHARE_143_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0980_CKGEN00 (ckgen00 + 0x180)
    #define REG_0980_CKGEN00_REG_CKG_SRAM_SHARE_143_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0988_CKGEN00 (ckgen00 + 0x188)
    #define REG_0988_CKGEN00_REG_CKG_SRAM_SHARE_144_R Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0990_CKGEN00 (ckgen00 + 0x190)
    #define REG_0990_CKGEN00_REG_CKG_SRAM_SHARE_144_W Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0998_CKGEN00 (ckgen00 + 0x198)
    #define REG_0998_CKGEN00_REG_CKG_TDP_JL_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_09A0_CKGEN00_REG_CKG_TDP_JL_INNER4X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_09A8_CKGEN00_REG_CKG_TDP_TEQ_INNER1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_09B0_CKGEN00_REG_CKG_TDP_TEQ_INNER2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_09B8_CKGEN00_REG_CKG_TR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_09C0_CKGEN00_REG_CKG_TS_IN Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_09C8_CKGEN00_REG_CKG_VIFDBB_144M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_09D0_CKGEN00_REG_CKG_VIFDBB_43M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_09D8_CKGEN00_REG_CKG_VIFDBB_86M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_09E0_CKGEN00_REG_CKG_VIFDBB_DAC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_09E8_CKGEN00_REG_CKG_VIFDBB_VDAC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_09F0_CKGEN00_REG_CKG_VIFDBB_VDAC_TMP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_09F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_09F8_CKGEN00_REG_CKG_DEINTER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A00_CKGEN00 (ckgen00 + 0x000)
    #define REG_0A00_CKGEN00_REG_CKG_DTMB_BCH_DEMOD1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A08_CKGEN00 (ckgen00 + 0x008)
    #define REG_0A08_CKGEN00_REG_CKG_DTMB_OUTER1X_DEMOD1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A10_CKGEN00 (ckgen00 + 0x010)
    #define REG_0A10_CKGEN00_REG_CKG_DVBS2_DEMAPPER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A18_CKGEN00 (ckgen00 + 0x018)
    #define REG_0A18_CKGEN00_REG_CKG_DVBS2_DVBT2_DEMAPPER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A20_CKGEN00 (ckgen00 + 0x020)
    #define REG_0A20_CKGEN00_REG_CKG_DVBS2_OUTER_FIFO_IN Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A28_CKGEN00 (ckgen00 + 0x028)
    #define REG_0A28_CKGEN00_REG_CKG_DVBT2_DEMAPPER Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A30_CKGEN00 (ckgen00 + 0x030)
    #define REG_0A30_CKGEN00_REG_CKG_DVBT2_DVBS2_OUTER_FIFO_IN Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A38_CKGEN00 (ckgen00 + 0x038)
    #define REG_0A38_CKGEN00_REG_CKG_DVBT2_OUTER_FIFO_IN Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A40_CKGEN00 (ckgen00 + 0x040)
    #define REG_0A40_CKGEN00_REG_CKG_DVBT2_S2_BCH Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A48_CKGEN00 (ckgen00 + 0x048)
    #define REG_0A48_CKGEN00_REG_CKG_DVBT2_S2_BCH_OUT Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A50_CKGEN00 (ckgen00 + 0x050)
    #define REG_0A50_CKGEN00_REG_CKG_LDPC1X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A58_CKGEN00 (ckgen00 + 0x058)
    #define REG_0A58_CKGEN00_REG_CKG_LDPC2X Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A60_CKGEN00 (ckgen00 + 0x060)
    #define REG_0A60_CKGEN00_REG_CKG_SRAM_DVBT2_S2_BCH_ME Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A68_CKGEN00 (ckgen00 + 0x068)
    #define REG_0A68_CKGEN00_REG_CKG_SRAM_LDPC1X_ME Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A70_CKGEN00 (ckgen00 + 0x070)
    #define REG_0A70_CKGEN00_REG_CKG_SRAM_LDPC2X_ME Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A78_CKGEN00 (ckgen00 + 0x078)
    #define REG_0A78_CKGEN00_REG_CKG_XTAL_24M_DEMOD1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0AB8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_0AB8_CKGEN00_REG_CKG_XTAL_12M_DEMOD1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B10_CKGEN00 (ckgen00 + 0x110)
    #define REG_0B10_CKGEN00_REG_CKG_AESDMA Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0B10_CKGEN00_REG_CKG_AESDMA_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0B18_CKGEN00 (ckgen00 + 0x118)
    #define REG_0B18_CKGEN00_REG_CKG_PARSER Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0B18_CKGEN00_REG_CKG_VIVA_PARSER Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0B18_CKGEN00_REG_CKG_PARSER_TSP Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0B28_CKGEN00 (ckgen00 + 0x128)
    #define REG_0B28_CKGEN00_REG_CKG_SMART2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0B28_CKGEN00_REG_CKG_SMART2_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0B30_CKGEN00 (ckgen00 + 0x130)
    #define REG_0B30_CKGEN00_REG_CKG_SMART Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0B30_CKGEN00_REG_CKG_SMART_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0B38_CKGEN00 (ckgen00 + 0x138)
    #define REG_0B38_CKGEN00_REG_CKG_TSO2_OUT_DIV_MN_SRC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B40_CKGEN00 (ckgen00 + 0x140)
    #define REG_0B40_CKGEN00_REG_CKG_TSO_OUT_DIV_MN_SRC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B48_CKGEN00 (ckgen00 + 0x148)
    #define REG_0B48_CKGEN00_REG_CKG_TSP Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0B48_CKGEN00_REG_CKG_TSP_TSP Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0B50_CKGEN00 (ckgen00 + 0x150)
    #define REG_0B50_CKGEN00_REG_CKG_FIQ0_27M Fld(5,0,AC_MSKB0)//[4:0]

//Page CKGEN00_3
#define REG_0B58_CKGEN00 (ckgen00 + 0x158)
    #define REG_0B58_CKGEN00_REG_CKG_MM0_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B60_CKGEN00 (ckgen00 + 0x160)
    #define REG_0B60_CKGEN00_REG_CKG_MM1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B68_CKGEN00 (ckgen00 + 0x168)
    #define REG_0B68_CKGEN00_REG_CKG_PVR1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B70_CKGEN00 (ckgen00 + 0x170)
    #define REG_0B70_CKGEN00_REG_CKG_PVR2_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B78_CKGEN00 (ckgen00 + 0x178)
    #define REG_0B78_CKGEN00_REG_CKG_PVR3_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B80_CKGEN00 (ckgen00 + 0x180)
    #define REG_0B80_CKGEN00_REG_CKG_PVR4_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B88_CKGEN00 (ckgen00 + 0x188)
    #define REG_0B88_CKGEN00_REG_CKG_STAMP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0B90_CKGEN00 (ckgen00 + 0x190)
    #define REG_0B90_CKGEN00_REG_CKG_SYN_STC0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B98_CKGEN00 (ckgen00 + 0x198)
    #define REG_0B98_CKGEN00_REG_CKG_SYN_STC1 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BA0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_0BA0_CKGEN00_REG_CKG_SYN_STC2 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BA8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_0BA8_CKGEN00_REG_CKG_SYN_STC3 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BB0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_0BB0_CKGEN00_REG_CKG_SYS_TIME0_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BB8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_0BB8_CKGEN00_REG_CKG_SYS_TIME1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BC0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_0BC0_CKGEN00_REG_CKG_SYS_TIME2_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BC8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_0BC8_CKGEN00_REG_CKG_SYS_TIME3_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BD0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_0BD0_CKGEN00_REG_CKG_TLV0_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BD8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_0BD8_CKGEN00_REG_CKG_TLV1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BE0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_0BE0_CKGEN00_REG_CKG_TLV2_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BE8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_0BE8_CKGEN00_REG_CKG_TSIF0_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BF0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_0BF0_CKGEN00_REG_CKG_TSO2_CH1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0BF8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_0BF8_CKGEN00_REG_CKG_TSO2_CH5_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C00_CKGEN00 (ckgen00 + 0x000)
    #define REG_0C00_CKGEN00_REG_CKG_TSO2_CH6_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C08_CKGEN00 (ckgen00 + 0x008)
    #define REG_0C08_CKGEN00_REG_CKG_P_TSO2_OUT Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C10_CKGEN00 (ckgen00 + 0x010)
    #define REG_0C10_CKGEN00_REG_CKG_TSO_CH1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C18_CKGEN00 (ckgen00 + 0x018)
    #define REG_0C18_CKGEN00_REG_CKG_TSO_CH5_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C20_CKGEN00 (ckgen00 + 0x020)
    #define REG_0C20_CKGEN00_REG_CKG_TSO_CH6_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C28_CKGEN00 (ckgen00 + 0x028)
    #define REG_0C28_CKGEN00_REG_CKG_P_TSO_OUT Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C30_CKGEN00 (ckgen00 + 0x030)
    #define REG_0C30_CKGEN00_REG_CKG_SMART2_SYNTH_432 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C30_CKGEN00_REG_CKG_SMART2_SYNTH_432_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0C38_CKGEN00 (ckgen00 + 0x038)
    #define REG_0C38_CKGEN00_REG_CKG_SMART2_SYNTH_27 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C38_CKGEN00_REG_CKG_SMART2_SYNTH_27_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0C40_CKGEN00 (ckgen00 + 0x040)
    #define REG_0C40_CKGEN00_REG_CKG_SMART_SYNTH_432 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C40_CKGEN00_REG_CKG_SMART_SYNTH_432_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0C48_CKGEN00 (ckgen00 + 0x048)
    #define REG_0C48_CKGEN00_REG_CKG_SMART_SYNTH_27 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C48_CKGEN00_REG_CKG_SMART_SYNTH_27_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0C50_CKGEN00 (ckgen00 + 0x050)
    #define REG_0C50_CKGEN00_REG_CKG_PATH0_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C58_CKGEN00 (ckgen00 + 0x058)
    #define REG_0C58_CKGEN00_REG_CKG_PATH1_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C60_CKGEN00 (ckgen00 + 0x060)
    #define REG_0C60_CKGEN00_REG_CKG_PATH2_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C68_CKGEN00 (ckgen00 + 0x068)
    #define REG_0C68_CKGEN00_REG_CKG_PATH_FI_27M Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0C94_CKGEN00 (ckgen00 + 0x094)
    #define REG_0C94_CKGEN00_REG_CKG_SYNTH_PCM_TRX_256FS_VIVALDI9_0C94 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C98_CKGEN00 (ckgen00 + 0x098)
    #define REG_0C98_CKGEN00_REG_CKG_AUSDM_3M Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CA0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_0CA0_CKGEN00_REG_CKG_BCLK_I2S_ENCODER2 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CA8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_0CA8_CKGEN00_REG_CKG_BCLK_I2S_ENCODER Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CB0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_0CB0_CKGEN00_REG_CKG_EARC_TX_PLL_256FS_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CB4_CKGEN00 (ckgen00 + 0x0B4)
    #define REG_0CB4_CKGEN00_REG_CKG_EARC_TX_PLL_256FS_MUX_0CB4 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CB8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_0CB8_CKGEN00_REG_CKG_VIVA_AB3_MAC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0CC0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_0CC0_CKGEN00_REG_CKG_VIVA_AB_MAC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CC8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_0CC8_CKGEN00_REG_CKG_VIVA_ADC_512FS Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CD0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_0CD0_CKGEN00_REG_CKG_VIVA_AUDMA_V2_R1_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CD8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_0CD8_CKGEN00_REG_CKG_VIVA_AUDMA_V2_R1_SYNTH_REF Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0CE0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_0CE0_CKGEN00_REG_CKG_VIVA_AUDMA_V2_R2_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CE8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_0CE8_CKGEN00_REG_CKG_VIVA_AUDMA_V2_R2_SYNTH_REF Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0CF0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_0CF0_CKGEN00_REG_CKG_VIVA_AUPLL_IN Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CF8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_0CF8_CKGEN00_REG_CKG_VIVA_BCLK_I2S_DECODER2 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D00_CKGEN00 (ckgen00 + 0x100)
    #define REG_0D00_CKGEN00_REG_CKG_VIVA_BCLK_I2S_DECODER Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D08_CKGEN00 (ckgen00 + 0x108)
    #define REG_0D08_CKGEN00_REG_CKG_VIVA_BI2S_SYNTH_REF2 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0D10_CKGEN00 (ckgen00 + 0x110)
    #define REG_0D10_CKGEN00_REG_CKG_VIVA_CH1_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D18_CKGEN00 (ckgen00 + 0x118)
    #define REG_0D18_CKGEN00_REG_CKG_VIVA_CH2_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D20_CKGEN00 (ckgen00 + 0x120)
    #define REG_0D20_CKGEN00_REG_CKG_VIVA_CH3_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D28_CKGEN00 (ckgen00 + 0x128)
    #define REG_0D28_CKGEN00_REG_CKG_VIVA_CH4_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D30_CKGEN00 (ckgen00 + 0x130)
    #define REG_0D30_CKGEN00_REG_CKG_VIVA_CH5_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D38_CKGEN00 (ckgen00 + 0x138)
    #define REG_0D38_CKGEN00_REG_CKG_VIVA_CH6_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D40_CKGEN00 (ckgen00 + 0x140)
    #define REG_0D40_CKGEN00_REG_CKG_VIVA_CH7_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D48_CKGEN00 (ckgen00 + 0x148)
    #define REG_0D48_CKGEN00_REG_CKG_VIVA_CH8_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D50_CKGEN00 (ckgen00 + 0x150)
    #define REG_0D50_CKGEN00_REG_CKG_VIVA_CH9_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D58_CKGEN00 (ckgen00 + 0x158)
    #define REG_0D58_CKGEN00_REG_CKG_VIVA_CODEC_SH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D60_CKGEN00 (ckgen00 + 0x160)
    #define REG_0D60_CKGEN00_REG_CKG_VIVA_DAC_512FS Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D68_CKGEN00 (ckgen00 + 0x168)
    #define REG_0D68_CKGEN00_REG_CKG_VIVA_DSP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0D70_CKGEN00 (ckgen00 + 0x170)
    #define REG_0D70_CKGEN00_REG_CKG_VIVA_DVB1_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D78_CKGEN00 (ckgen00 + 0x178)
    #define REG_0D78_CKGEN00_REG_CKG_VIVA_DVB1_TIMING_GEN_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D80_CKGEN00 (ckgen00 + 0x180)
    #define REG_0D80_CKGEN00_REG_CKG_VIVA_DVB2_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D88_CKGEN00 (ckgen00 + 0x188)
    #define REG_0D88_CKGEN00_REG_CKG_VIVA_DVB2_TIMING_GEN_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D90_CKGEN00 (ckgen00 + 0x190)
    #define REG_0D90_CKGEN00_REG_CKG_VIVA_DVB3_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D98_CKGEN00 (ckgen00 + 0x198)
    #define REG_0D98_CKGEN00_REG_CKG_VIVA_DVB3_TIMING_GEN_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DA0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_0DA0_CKGEN00_REG_CKG_VIVA_DVB4_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0DA8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_0DA8_CKGEN00_REG_CKG_VIVA_DVB4_TIMING_GEN_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DB0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_0DB0_CKGEN00_REG_CKG_VIVA_DVB5_TIMING_GEN_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DB8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_0DB8_CKGEN00_REG_CKG_VIVA_DVB6_TIMING_GEN_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DC0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_0DC0_CKGEN00_REG_CKG_VIVA_EARC_TX_32XCHXFS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DC8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_0DC8_CKGEN00_REG_CKG_VIVA_EARC_TX_32XFS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DD0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_0DD0_CKGEN00_REG_CKG_VIVA_EARC_TX_64XCHXFS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DD8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_0DD8_CKGEN00_REG_CKG_VIVA_EARC_TX_GPA_SYNTH_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DE0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_0DE0_CKGEN00_REG_CKG_VIVA_EARC_TX_PLL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DE8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_0DE8_CKGEN00_REG_CKG_VIVA_EARC_TX_SOURCE_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DF0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_0DF0_CKGEN00_REG_CKG_VIVA_EARC_TX_SYNTH_IIR_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DF8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_0DF8_CKGEN00_REG_CKG_VIVA_EARC_TX_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0E00_CKGEN00 (ckgen00 + 0x000)
    #define REG_0E00_CKGEN00_REG_CKG_VIVA_FM_DEMODULATOR Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0E08_CKGEN00 (ckgen00 + 0x008)
    #define REG_0E08_CKGEN00_REG_CKG_VIVA_GPA_240FSO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E10_CKGEN00 (ckgen00 + 0x010)
    #define REG_0E10_CKGEN00_REG_CKG_VIVA_GPA_256FSO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E18_CKGEN00 (ckgen00 + 0x018)
    #define REG_0E18_CKGEN00_REG_CKG_VIVA_GPA_480FSO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E20_CKGEN00 (ckgen00 + 0x020)
    #define REG_0E20_CKGEN00_REG_CKG_VIVA_HDMI_RX2_MPLL_432 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E28_CKGEN00 (ckgen00 + 0x028)
    #define REG_0E28_CKGEN00_REG_CKG_VIVA_HDMI_RX2_S2P_128FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E30_CKGEN00 (ckgen00 + 0x030)
    #define REG_0E30_CKGEN00_REG_CKG_VIVA_HDMI_RX2_S2P_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E38_CKGEN00 (ckgen00 + 0x038)
    #define REG_0E38_CKGEN00_REG_CKG_VIVA_HDMI_RX2_SYNTH_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E40_CKGEN00 (ckgen00 + 0x040)
    #define REG_0E40_CKGEN00_REG_CKG_VIVA_HDMI_RX2_V2A_TIME_STAMP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E48_CKGEN00 (ckgen00 + 0x048)
    #define REG_0E48_CKGEN00_REG_CKG_VIVA_HDMI_RX_MPLL_432 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E50_CKGEN00 (ckgen00 + 0x050)
    #define REG_0E50_CKGEN00_REG_CKG_VIVA_HDMI_RX_S2P_128FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E58_CKGEN00 (ckgen00 + 0x058)
    #define REG_0E58_CKGEN00_REG_CKG_VIVA_HDMI_RX_S2P_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E60_CKGEN00 (ckgen00 + 0x060)
    #define REG_0E60_CKGEN00_REG_CKG_VIVA_HDMI_RX_SYNTH_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E68_CKGEN00 (ckgen00 + 0x068)
    #define REG_0E68_CKGEN00_REG_CKG_VIVA_HDMI_RX_V2A_TIME_STAMP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E70_CKGEN00 (ckgen00 + 0x070)
    #define REG_0E70_CKGEN00_REG_CKG_VIVA_HDMI_TX_128FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E78_CKGEN00 (ckgen00 + 0x078)
    #define REG_0E78_CKGEN00_REG_CKG_VIVA_HDMI_TX_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E80_CKGEN00 (ckgen00 + 0x080)
    #define REG_0E80_CKGEN00_REG_CKG_VIVA_I2S_2_BCLK_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0E88_CKGEN00 (ckgen00 + 0x088)
    #define REG_0E88_CKGEN00_REG_CKG_VIVA_I2S_BCLK_DG2 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E90_CKGEN00 (ckgen00 + 0x090)
    #define REG_0E90_CKGEN00_REG_CKG_VIVA_I2S_BCLK_DG Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E98_CKGEN00 (ckgen00 + 0x098)
    #define REG_0E98_CKGEN00_REG_CKG_VIVA_I2S_BCLK_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0EA0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_0EA0_CKGEN00_REG_CKG_VIVA_I2S_MCLK_SYNTH_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0EA8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_0EA8_CKGEN00_REG_CKG_VIVA_I2S_SYNTH_REF Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0EB0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_0EB0_CKGEN00_REG_CKG_VIVA_I2S_TRX_BCLK_TIMING_GEN Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0EB8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_0EB8_CKGEN00_REG_CKG_VIVA_I2S_TRX_SYNTH_REF Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0EC0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_0EC0_CKGEN00_REG_CKG_VIVA_I2S_TX_FIFO_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0EC8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_0EC8_CKGEN00_REG_CKG_VIVA_MCLK_I2S_DECODER2 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0ED0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_0ED0_CKGEN00_REG_CKG_VIVA_MCLK_I2S_DECODER Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0ED8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_0ED8_CKGEN00_REG_CKG_VIVA_MCLK_I2S_ENCODER2 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0EE0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_0EE0_CKGEN00_REG_CKG_VIVA_MCLK_I2S_ENCODER Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0EE8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_0EE8_CKGEN00_REG_CKG_VIVA_NPCM2_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0EF0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_0EF0_CKGEN00_REG_CKG_VIVA_NPCM3_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0EF8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_0EF8_CKGEN00_REG_CKG_VIVA_NPCM4_256FS_TIMING_GEN Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F00_CKGEN00 (ckgen00 + 0x100)
    #define REG_0F00_CKGEN00_REG_CKG_VIVA_NPCM4_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F08_CKGEN00 (ckgen00 + 0x108)
    #define REG_0F08_CKGEN00_REG_CKG_VIVA_NPCM5_256FS_TIMING_GEN Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F10_CKGEN00 (ckgen00 + 0x110)
    #define REG_0F10_CKGEN00_REG_CKG_VIVA_NPCM5_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F18_CKGEN00 (ckgen00 + 0x118)
    #define REG_0F18_CKGEN00_REG_CKG_VIVA_NPCM_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F20_CKGEN00 (ckgen00 + 0x120)
    #define REG_0F20_CKGEN00_REG_CKG_VIVA_PCM_CLK_216 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F28_CKGEN00 (ckgen00 + 0x128)
    #define REG_0F28_CKGEN00_REG_CKG_VIVA_PCM_CLK_AUPLL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F2C_CKGEN00 (ckgen00 + 0x12C)
    #define REG_0F2C_CKGEN00_REG_CKG_R2_VIVALDI9 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F30_CKGEN00 (ckgen00 + 0x130)
    #define REG_0F30_CKGEN00_REG_CKG_VIVA_R2_WB Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0F30_CKGEN00_REG_CKG_AU_R2_WB Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0F30_CKGEN00_REG_CKG_MCU_WB_RV55AUDIO Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0F38_CKGEN00 (ckgen00 + 0x138)
    #define REG_0F38_CKGEN00_REG_CKG_VIVA_RIU_BRG_R2 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F3C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_0F3C_CKGEN00_REG_CKG_MCU_WB_RV55FRC_0F3C Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0F3C_CKGEN00_REG_CKG_MCU_WB_RV55PQU_0F3C Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0F40_CKGEN00 (ckgen00 + 0x140)
    #define REG_0F40_CKGEN00_REG_CKG_VIVA_RIU_R2 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F48_CKGEN00 (ckgen00 + 0x148)
    #define REG_0F48_CKGEN00_REG_CKG_VIVA_SH Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F50_CKGEN00 (ckgen00 + 0x150)
    #define REG_0F50_CKGEN00_REG_CKG_VIVA_SIF_ADC_CIC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F58_CKGEN00 (ckgen00 + 0x158)
    #define REG_0F58_CKGEN00_REG_CKG_VIVA_SIF_ADC_R2B_FIFO_IN Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F60_CKGEN00 (ckgen00 + 0x160)
    #define REG_0F60_CKGEN00_REG_CKG_VIVA_SIF_ADC_R2B Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F68_CKGEN00 (ckgen00 + 0x168)
    #define REG_0F68_CKGEN00_REG_CKG_SIF_CORDIC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0F70_CKGEN00 (ckgen00 + 0x170)
    #define REG_0F70_CKGEN00_REG_CKG_VIVA_SIF_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F78_CKGEN00 (ckgen00 + 0x178)
    #define REG_0F78_CKGEN00_REG_CKG_VIVA_SIN_GEN Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F80_CKGEN00 (ckgen00 + 0x180)
    #define REG_0F80_CKGEN00_REG_CKG_VIVA_SPDIF_EXTEARC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F88_CKGEN00 (ckgen00 + 0x188)
    #define REG_0F88_CKGEN00_REG_CKG_VIVA_SPDIF_RX_128FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F90_CKGEN00 (ckgen00 + 0x190)
    #define REG_0F90_CKGEN00_REG_CKG_VIVA_SPDIF_RX_DG Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0F98_CKGEN00 (ckgen00 + 0x198)
    #define REG_0F98_CKGEN00_REG_CKG_VIVA_SPDIF_RX_SYNTH_REF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0FA0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_0FA0_CKGEN00_REG_CKG_VIVA_SPDIF_TX2_128FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FA8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_0FA8_CKGEN00_REG_CKG_VIVA_SPDIF_TX2_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FB0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_0FB0_CKGEN00_REG_CKG_VIVA_SPDIF_TX_128FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FB8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_0FB8_CKGEN00_REG_CKG_VIVA_SPDIF_TX_256FS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FC0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_0FC0_CKGEN00_REG_CKG_VIVA_SPDIF_TX_SYNTH_REF Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FC8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_0FC8_CKGEN00_REG_CKG_VIVA_SYNTH_2ND_ORDER Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0FD0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_0FD0_CKGEN00_REG_CKG_VIVA_SYNTH_CODEC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0FD8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_0FD8_CKGEN00_REG_CKG_VIVA_TEST_BUS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FE0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_0FE0_CKGEN00_REG_CKG_VIVA_VBDMA_MCU Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FE8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_0FE8_CKGEN00_REG_CKG_VIVA_XTAL_12M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0FF0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_0FF0_CKGEN00_REG_CKG_VIVA_XTAL_24M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0FF8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_0FF8_CKGEN00_REG_CKG_AU_R2_DFS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1000_CKGEN00 (ckgen00 + 0x000)
    #define REG_1000_CKGEN00_REG_CKG_AU_R2_PLL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1008_CKGEN00 (ckgen00 + 0x008)
    #define REG_1008_CKGEN00_REG_CKG_XTAL_12M_RV55AUDIO Fld(2,0,AC_MSKB0)//[1:0]
#define REG_100C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_100C_CKGEN00_REG_CKG_XTAL_24M_RV55AUDIO Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1010_CKGEN00 (ckgen00 + 0x010)
    #define REG_1010_CKGEN00_REG_CKG_XTAL_12M_AUDIO_R2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1014_CKGEN00 (ckgen00 + 0x014)
    #define REG_1014_CKGEN00_REG_CKG_XTAL_24M_AUDIO_R2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1018_CKGEN00 (ckgen00 + 0x018)
    #define REG_1018_CKGEN00_REG_CKG_RV55AUDIO Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1020_CKGEN00 (ckgen00 + 0x020)
    #define REG_1020_CKGEN00_REG_CKG_AUDMA_V2_R1_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1028_CKGEN00 (ckgen00 + 0x028)
    #define REG_1028_CKGEN00_REG_CKG_BCLK_I2S_ENCODER2_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1030_CKGEN00 (ckgen00 + 0x030)
    #define REG_1030_CKGEN00_REG_CKG_BCLK_I2S_ENCODER_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1058_CKGEN00 (ckgen00 + 0x058)
    #define REG_1058_CKGEN00_REG_CKG_CH5_256FSI_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1060_CKGEN00 (ckgen00 + 0x060)
    #define REG_1060_CKGEN00_REG_CKG_CH6_256FSI_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1068_CKGEN00 (ckgen00 + 0x068)
    #define REG_1068_CKGEN00_REG_CKG_CH7_256FSI_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1070_CKGEN00 (ckgen00 + 0x070)
    #define REG_1070_CKGEN00_REG_CKG_CH8_256FSI_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1078_CKGEN00 (ckgen00 + 0x078)
    #define REG_1078_CKGEN00_REG_CKG_CH9_256FSI_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1080_CKGEN00 (ckgen00 + 0x080)
    #define REG_1080_CKGEN00_REG_CKG_DEC1_SYNTH_HDMI_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1088_CKGEN00 (ckgen00 + 0x088)
    #define REG_1088_CKGEN00_REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN00_4
#define REG_1090_CKGEN00 (ckgen00 + 0x090)
    #define REG_1090_CKGEN00_REG_CKG_DEC2_SYNTH_HDMI_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1098_CKGEN00 (ckgen00 + 0x098)
    #define REG_1098_CKGEN00_REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_10A0_CKGEN00_REG_CKG_DEC3_SYNTH_HDMI_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_10A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_10A8_CKGEN00_REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_10B0_CKGEN00_REG_CKG_DEC4_SYNTH_HDMI_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_10B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_10B8_CKGEN00_REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_10C0_CKGEN00_REG_CKG_DECODER1_FUNCTION_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_10C8_CKGEN00_REG_CKG_DECODER2_FUNCTION_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_10D0_CKGEN00_REG_CKG_DECODER3_FUNCTION_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_10D8_CKGEN00_REG_CKG_DECODER4_FUNCTION_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_10E0_CKGEN00_REG_CKG_EARC_TX_GPA_SYNTH_MUX Fld(2,0,AC_MSKB0)//[1:0]
#define REG_10E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_10E8_CKGEN00_REG_CKG_EARC_TX_SOURCE_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_10F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_10F0_CKGEN00_REG_CKG_HDMI2_PATGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_10F8_CKGEN00_REG_CKG_HDMI_PATGEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1100_CKGEN00 (ckgen00 + 0x100)
    #define REG_1100_CKGEN00_REG_CKG_HDMI_RX_BYPASS_TO_TX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1108_CKGEN00 (ckgen00 + 0x108)
    #define REG_1108_CKGEN00_REG_CKG_HDMI_TX_256FS_MUX0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1110_CKGEN00 (ckgen00 + 0x110)
    #define REG_1110_CKGEN00_REG_CKG_HDMI_TX_256FS_MUX1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1118_CKGEN00 (ckgen00 + 0x118)
    #define REG_1118_CKGEN00_REG_CKG_HDMI_TX_TO_I2S_TX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1120_CKGEN00 (ckgen00 + 0x120)
    #define REG_1120_CKGEN00_REG_CKG_I2S_2_SYNTH_SSC_MUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1128_CKGEN00 (ckgen00 + 0x128)
    #define REG_1128_CKGEN00_REG_CKG_I2S_CH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1130_CKGEN00 (ckgen00 + 0x130)
    #define REG_1130_CKGEN00_REG_CKG_I2S_SYNTH_SSC_MUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1138_CKGEN00 (ckgen00 + 0x138)
    #define REG_1138_CKGEN00_REG_CKG_PCM_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1140_CKGEN00 (ckgen00 + 0x140)
    #define REG_1140_CKGEN00_REG_CKG_R2_WB_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1148_CKGEN00 (ckgen00 + 0x148)
    #define REG_1148_CKGEN00_REG_CKG_SPDIF_EXTEARC_128FS_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1150_CKGEN00 (ckgen00 + 0x150)
    #define REG_1150_CKGEN00_REG_CKG_SPDIF_EXTEARC_256FS_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1158_CKGEN00 (ckgen00 + 0x158)
    #define REG_1158_CKGEN00_REG_CKG_SPDIF_EXTEARC_MUX Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1160_CKGEN00 (ckgen00 + 0x160)
    #define REG_1160_CKGEN00_REG_CKG_SPDIF_EXTEARC_MUX0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1168_CKGEN00 (ckgen00 + 0x168)
    #define REG_1168_CKGEN00_REG_CKG_SPDIF_TX2_GPA_SYNTH_MUX Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1170_CKGEN00 (ckgen00 + 0x170)
    #define REG_1170_CKGEN00_REG_CKG_SPDIF_TX2_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1178_CKGEN00 (ckgen00 + 0x178)
    #define REG_1178_CKGEN00_REG_CKG_SPDIF_TX_GPA_SYNTH_MUX Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1180_CKGEN00 (ckgen00 + 0x180)
    #define REG_1180_CKGEN00_REG_CKG_SPDIF_TX_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1184_CKGEN00 (ckgen00 + 0x184)
    #define REG_1184_CKGEN00_REG_CKG_VIVA_I2S_TX_2_FIFO_256FS Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1188_CKGEN00 (ckgen00 + 0x188)
    #define REG_1188_CKGEN00_REG_CKG_EARC_AUDIO_EARC_DMACRO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1190_CKGEN00 (ckgen00 + 0x190)
    #define REG_1190_CKGEN00_REG_CKG_AUSDM_3M_CK Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1194_CKGEN00 (ckgen00 + 0x194)
    #define REG_1194_CKGEN00_REG_CKG_CH10_256FSI_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1198_CKGEN00 (ckgen00 + 0x198)
    #define REG_1198_CKGEN00_REG_CKG_CH_M1_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_119C_CKGEN00 (ckgen00 + 0x19C)
    #define REG_119C_CKGEN00_REG_CKG_CH_M2_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_11A0_CKGEN00_REG_CKG_CH_M3_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11A4_CKGEN00 (ckgen00 + 0x1A4)
    #define REG_11A4_CKGEN00_REG_CKG_CH_M4_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_11A8_CKGEN00_REG_CKG_CH_M5_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11AC_CKGEN00 (ckgen00 + 0x1AC)
    #define REG_11AC_CKGEN00_REG_CKG_CH_M6_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_11B0_CKGEN00_REG_CKG_CH_M7_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11B4_CKGEN00 (ckgen00 + 0x1B4)
    #define REG_11B4_CKGEN00_REG_CKG_CH_M8_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_11B8_CKGEN00_REG_CKG_CH_M9_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11BC_CKGEN00 (ckgen00 + 0x1BC)
    #define REG_11BC_CKGEN00_REG_CKG_CH_M10_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_11C0_CKGEN00_REG_CKG_CH_M11_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11C4_CKGEN00 (ckgen00 + 0x1C4)
    #define REG_11C4_CKGEN00_REG_CKG_CH_M12_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_11C8_CKGEN00_REG_CKG_CH_M13_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11CC_CKGEN00 (ckgen00 + 0x1CC)
    #define REG_11CC_CKGEN00_REG_CKG_CH_M14_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_11D0_CKGEN00_REG_CKG_CH_M15_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11D4_CKGEN00 (ckgen00 + 0x1D4)
    #define REG_11D4_CKGEN00_REG_CKG_CH_M16_256FSI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_11D8_CKGEN00_REG_CKG_DAP_TCK_VIVALDI9 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_11D8_CKGEN00_REG_CKG_DAP_TCK_RV55AUDIO Fld(2,8,AC_MSKB1)//[9:8]
#define REG_11DC_CKGEN00 (ckgen00 + 0x1DC)
    #define REG_11DC_CKGEN00_REG_CKG_DAP_VIVALDI9 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_11DC_CKGEN00_REG_CKG_DAP_RV55AUDIO Fld(2,8,AC_MSKB1)//[9:8]
#define REG_11E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_11E0_CKGEN00_REG_CKG_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11E4_CKGEN00 (ckgen00 + 0x1E4)
    #define REG_11E4_CKGEN00_REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_11E8_CKGEN00_REG_CKG_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11EC_CKGEN00 (ckgen00 + 0x1EC)
    #define REG_11EC_CKGEN00_REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_11F0_CKGEN00_REG_CKG_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11F4_CKGEN00 (ckgen00 + 0x1F4)
    #define REG_11F4_CKGEN00_REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_11F8_CKGEN00_REG_CKG_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11FC_CKGEN00 (ckgen00 + 0x1FC)
    #define REG_11FC_CKGEN00_REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1200_CKGEN00 (ckgen00 + 0x000)
    #define REG_1200_CKGEN00_REG_CKG_RV_TCK_VIVALDI9 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1200_CKGEN00_REG_CKG_RV_TCK_RV55AUDIO Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1204_CKGEN00 (ckgen00 + 0x004)
    #define REG_1204_CKGEN00_REG_CKG_RV_VIVALDI9 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1208_CKGEN00 (ckgen00 + 0x008)
    #define REG_1208_CKGEN00_REG_CKG_VIVA_CH10_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_120C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_120C_CKGEN00_REG_CKG_VIVA_CH_M1_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1210_CKGEN00 (ckgen00 + 0x010)
    #define REG_1210_CKGEN00_REG_CKG_VIVA_CH_M2_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1214_CKGEN00 (ckgen00 + 0x014)
    #define REG_1214_CKGEN00_REG_CKG_VIVA_CH_M3_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1218_CKGEN00 (ckgen00 + 0x018)
    #define REG_1218_CKGEN00_REG_CKG_VIVA_CH_M4_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_121C_CKGEN00 (ckgen00 + 0x01C)
    #define REG_121C_CKGEN00_REG_CKG_VIVA_CH_M5_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1220_CKGEN00 (ckgen00 + 0x020)
    #define REG_1220_CKGEN00_REG_CKG_VIVA_CH_M6_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1224_CKGEN00 (ckgen00 + 0x024)
    #define REG_1224_CKGEN00_REG_CKG_VIVA_CH_M7_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1228_CKGEN00 (ckgen00 + 0x028)
    #define REG_1228_CKGEN00_REG_CKG_VIVA_CH_M8_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_122C_CKGEN00 (ckgen00 + 0x02C)
    #define REG_122C_CKGEN00_REG_CKG_VIVA_CH_M9_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1230_CKGEN00 (ckgen00 + 0x030)
    #define REG_1230_CKGEN00_REG_CKG_VIVA_CH_M10_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1234_CKGEN00 (ckgen00 + 0x034)
    #define REG_1234_CKGEN00_REG_CKG_VIVA_CH_M11_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1238_CKGEN00 (ckgen00 + 0x038)
    #define REG_1238_CKGEN00_REG_CKG_VIVA_CH_M12_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_123C_CKGEN00 (ckgen00 + 0x03C)
    #define REG_123C_CKGEN00_REG_CKG_VIVA_CH_M13_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1240_CKGEN00 (ckgen00 + 0x040)
    #define REG_1240_CKGEN00_REG_CKG_VIVA_CH_M14_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1244_CKGEN00 (ckgen00 + 0x044)
    #define REG_1244_CKGEN00_REG_CKG_VIVA_CH_M15_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1248_CKGEN00 (ckgen00 + 0x048)
    #define REG_1248_CKGEN00_REG_CKG_VIVA_CH_M16_256FSI Fld(3,0,AC_MSKB0)//[2:0]
#define REG_124C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_124C_CKGEN00_REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1250_CKGEN00 (ckgen00 + 0x050)
    #define REG_1250_CKGEN00_REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1254_CKGEN00 (ckgen00 + 0x054)
    #define REG_1254_CKGEN00_REG_CKG_VIVA_I2S_TDM_1X16TX32B_FIFO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1258_CKGEN00 (ckgen00 + 0x058)
    #define REG_1258_CKGEN00_REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK Fld(5,0,AC_MSKB0)//[4:0]
#define REG_125C_CKGEN00 (ckgen00 + 0x05C)
    #define REG_125C_CKGEN00_REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1260_CKGEN00 (ckgen00 + 0x060)
    #define REG_1260_CKGEN00_REG_CKG_VIVA_I2S_TDM_6X16TX32B_FIFO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1264_CKGEN00 (ckgen00 + 0x064)
    #define REG_1264_CKGEN00_REG_CKG_VIVA_SRC_MAC_BSPLINE Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1268_CKGEN00 (ckgen00 + 0x068)
    #define REG_1268_CKGEN00_REG_CKG_DISP_MFDEC Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1268_CKGEN00_REG_CKG_DISP_MFDEC_GPU_NODIE Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1268_CKGEN00_REG_CKG_DISP_MFDEC_GPU_PAR_GP_1268 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1268_CKGEN00_REG_CKG_DISP_MFDEC_GPU_1268 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_126C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_126C_CKGEN00_REG_CKG_DISP_MFDEC_SCNR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1270_CKGEN00 (ckgen00 + 0x070)
    #define REG_1270_CKGEN00_REG_CKG_GPD Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1270_CKGEN00_REG_CKG_GPD_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1278_CKGEN00 (ckgen00 + 0x078)
    #define REG_1278_CKGEN00_REG_CKG_NJPD Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1278_CKGEN00_REG_CKG_NJPD_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1280_CKGEN00 (ckgen00 + 0x080)
    #define REG_1280_CKGEN00_REG_CKG_VDEC_LAE Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1288_CKGEN00 (ckgen00 + 0x088)
    #define REG_1288_CKGEN00_REG_CKG_VDEC_LAE_SLOW Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1288_CKGEN00_REG_CKG_VDEC_BUS_VDEC_SOC Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1288_CKGEN00_REG_CKG_VDEC_BUS_VDEC_CORE0 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1288_CKGEN00_REG_CKG_VDEC_BUS_VDEC_CORE1 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_1288_CKGEN00_REG_CKG_VDEC_BUS_VDEC_CORE2 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_1290_CKGEN00 (ckgen00 + 0x090)
    #define REG_1290_CKGEN00_REG_CKG_VDEC_SYS Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1290_CKGEN00_REG_CKG_VDEC_SYS_VDEC_SOC Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1290_CKGEN00_REG_CKG_VDEC_SYS_VDEC_CORE0 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1290_CKGEN00_REG_CKG_VDEC_SYS_VDEC_CORE1 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_1290_CKGEN00_REG_CKG_VDEC_SYS_VDEC_CORE2 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_1298_CKGEN00 (ckgen00 + 0x098)
    #define REG_1298_CKGEN00_REG_CKG_VDEC_SYS_SLOW Fld(4,0,AC_MSKB0)//[3:0]
#define REG_12A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_12A0_CKGEN00_REG_CKG_VDEC_LAT0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_12A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_12A8_CKGEN00_REG_CKG_VDEC_LAT1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_12B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_12B0_CKGEN00_REG_CKG_GCE_F26M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_12B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_12B8_CKGEN00_REG_CKG_XTAL_24M_VDEC_CORE0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_12C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_12C0_CKGEN00_REG_CKG_XTAL_24M_VDEC_CORE1 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_12C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_12C8_CKGEN00_REG_CKG_XTAL_24M_VDEC_CORE2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1400_CKGEN00 (ckgen00 + 0x000)
    #define REG_1400_CKGEN00_REG_SW_EN_CALC2CALC_MCUSYS Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1440_CKGEN00 (ckgen00 + 0x040)
    #define REG_1440_CKGEN00_REG_SW_EN_BRIDGE2GPU_NODIE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1444_CKGEN00 (ckgen00 + 0x044)
    #define REG_1444_CKGEN00_REG_SW_EN_GPU2GPU_DIE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1444_CKGEN00_REG_SW_EN_GPU_DFS2GPU_PAR_GP_1444 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1448_CKGEN00 (ckgen00 + 0x048)
    #define REG_1448_CKGEN00_REG_SW_EN_SC2SHADER Fld(1,0,AC_MSKB0)//[0:0]
#define REG_144C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_144C_CKGEN00_REG_SW_EN_XTAL_12M2MET Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1450_CKGEN00 (ckgen00 + 0x050)
    #define REG_1450_CKGEN00_REG_SW_EN_XTAL_24M2SYSCOUNT Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1450_CKGEN00_REG_SW_EN_XTAL_24M2XTAL Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1460_CKGEN00 (ckgen00 + 0x060)
    #define REG_1460_CKGEN00_REG_SW_EN_BUS_NODIE2AIATOP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1460_CKGEN00_REG_SW_EN_BUS_NODIE2SMI Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1464_CKGEN00 (ckgen00 + 0x064)
    #define REG_1464_CKGEN00_REG_SW_EN_XTAL_24M2AIATOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_146C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_146C_CKGEN00_REG_SW_EN_DRAMC0_CGCLK_FAST_CHC2DRAMC0_146C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1474_CKGEN00 (ckgen00 + 0x074)
    #define REG_1474_CKGEN00_REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1478_CKGEN00 (ckgen00 + 0x078)
    #define REG_1478_CKGEN00_REG_SW_EN_DRAMC1_CGCLK_FAST_CHA2DRAMC1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_147C_CKGEN00 (ckgen00 + 0x07C)
    #define REG_147C_CKGEN00_REG_SW_EN_DRAMC2_CGCLK_FAST_CHA2DRAMC2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1480_CKGEN00 (ckgen00 + 0x080)
    #define REG_1480_CKGEN00_REG_SW_EN_OCC_SRC_2162DRAMC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1484_CKGEN00 (ckgen00 + 0x084)
    #define REG_1484_CKGEN00_REG_SW_EN_OCC_SRC_2162DRAMC1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1488_CKGEN00 (ckgen00 + 0x088)
    #define REG_1488_CKGEN00_REG_SW_EN_OCC_SRC_2162DRAMC2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_148C_CKGEN00 (ckgen00 + 0x08C)
    #define REG_148C_CKGEN00_REG_SW_EN_XTAL_24M2DRAMC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1490_CKGEN00 (ckgen00 + 0x090)
    #define REG_1490_CKGEN00_REG_SW_EN_XTAL_24M2DRAMC1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1494_CKGEN00 (ckgen00 + 0x094)
    #define REG_1494_CKGEN00_REG_SW_EN_XTAL_24M2DRAMC2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1498_CKGEN00 (ckgen00 + 0x098)
    #define REG_1498_CKGEN00_REG_SW_EN_EMI0_DEB2IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_149C_CKGEN00 (ckgen00 + 0x09C)
    #define REG_149C_CKGEN00_REG_SW_EN_EMI02IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_14A0_CKGEN00_REG_SW_EN_EMI1_DEB2IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14A4_CKGEN00 (ckgen00 + 0x0A4)
    #define REG_14A4_CKGEN00_REG_SW_EN_EMI12IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_14A8_CKGEN00_REG_SW_EN_EMI2_DEB2IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14AC_CKGEN00 (ckgen00 + 0x0AC)
    #define REG_14AC_CKGEN00_REG_SW_EN_EMI22IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14AC_CKGEN00_REG_SW_EN_EMI22XPU Fld(1,1,AC_MSKB0)//[1:1]
#define REG_14B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_14B0_CKGEN00_REG_SW_EN_IP_WRAP2IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B4_CKGEN00 (ckgen00 + 0x0B4)
    #define REG_14B4_CKGEN00_REG_SW_EN_XTAL_12M2IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_14B8_CKGEN00_REG_SW_EN_XTAL_24M2IP_WRAP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14BC_CKGEN00 (ckgen00 + 0x0BC)
    #define REG_14BC_CKGEN00_REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0_14BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E4_CKGEN00 (ckgen00 + 0x0E4)
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2AIA_SMI Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2AUDIO_R2 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2CMDQ Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2CORE0 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2CORE1 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2CORE2 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2SMI_DEMOD0 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2DSCRMB Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2FRCIOPMRV55 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2FRCMEHALO Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2GE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2GMAC Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2GPD Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_14E4_CKGEN00_REG_SW_EN_SMI2JPD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14E8_CKGEN00 (ckgen00 + 0x14E8)
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MAC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_BDMA Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_DEMURA Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_FUART Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_M2MCU Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_MIIC0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_MIIC1 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_MIIC2 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_MIIC3 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MCU_XD2MIU Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2MHEG5_SMI Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2RV55AUDIO Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2RV55FRC Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2RV55PQU Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2SCACE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_14E8_CKGEN00_REG_SW_EN_SMI2SCDV Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14EC_CKGEN00 (ckgen00 + 0x14EC)
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCIP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCM Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCMO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCMW Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCNR Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCPQ Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCSCL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCSR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SCTCON Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SMI Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SOC Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2SSUSB Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2TSO Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2TSO2 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2TSP Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_14EC_CKGEN00_REG_SW_EN_SMI2VD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14F0_CKGEN00 (ckgen00 + 0x14F0)
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2VD_PES_PARSER Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2SMI_LARB_SCMW Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2LARB_TSP Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI_AESDMA2DSCRMB Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI_TSP2TSP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI_FCIE2FCIE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI_UHC2UHC Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_14F0_CKGEN00_REG_SW_EN_VIVA_SMI2SMI Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2DEMOD0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2DEMOD0_DVBTM Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2DEMOD0_ISDBT Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2DEMOD0_DTMB Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2DEMOD0_ADC_DUMP Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2MCU_MSPI0 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2MCU_MSPI1 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_14F0_CKGEN00_REG_SW_EN_SMI2MCU_MSPI2 Fld(1,15,AC_MSKB1)//[15:15]

//Page CKGEN00_5
#define REG_14F4_CKGEN00 (ckgen00 + 0x14F4)
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2MCU_MSPI3 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2MCU_MSPI4 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2MCU_MSPI5 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2MCU_MSPI6 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2MCU_MSPI7 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2MCU_MSPI_CILINK Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2PEXTP Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2UFS Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2SCDISP_14F4 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_14F4_CKGEN00_REG_SW_EN_VIVA_SMI2SMI_BRG_14F4 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2FRCCORE1_14F4 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2FRCCORE2_14F4 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2FRCCORE3_14F4 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2FRCMISC_14F4 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI_SSUSB2SSUSB_14F4 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_14F4_CKGEN00_REG_SW_EN_SMI2RV55PQU_SMI_14F4 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_14F8_CKGEN00_REG_SW_EN_SMI2SMI_FRCCORE1_14F8 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_14F8_CKGEN00_REG_SW_EN_SMI2GCE_14F8 Fld(1,1,AC_MSKB0)//[1:1]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SMI_LARB_SCIP Fld(1,2,AC_MSKB0)//[2:2]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SMI_LARB_SCNR Fld(1,3,AC_MSKB0)//[3:3]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SCTCON_LARB Fld(1,4,AC_MSKB0)//[4:4]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SCDISP_LARB Fld(1,5,AC_MSKB0)//[5:5]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2FRCIOPMRV55_LARB Fld(1,6,AC_MSKB0)//[6:6]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2FRCMEHALO_LARB Fld(1,7,AC_MSKB0)//[7:7]
    #define V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2FRCMI_GALS_SLICE Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1500_CKGEN00 (ckgen00 + 0x1500)
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SMI_GALS_SCMW Fld(1,1,AC_MSKB0)//[1:1]
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SMI_GALS_SCIP Fld(1,2,AC_MSKB0)//[2:2]
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SMI_GALS_SCNR Fld(1,3,AC_MSKB0)//[3:3]
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SCTCON_GALS Fld(1,4,AC_MSKB0)//[4:4]
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SCDISP_GALS Fld(1,5,AC_MSKB0)//[5:5]
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2FRCIOPMRV55_GALS Fld(1,6,AC_MSKB0)//[6:6]
    #define V3_REG_1500_CKGEN00_REG_SW_EN_SMI2FRCMEHALO_GALS Fld(1,7,AC_MSKB0)//[7:7]
#define REG_1520_CKGEN00 (ckgen00 + 0x120)
    #define REG_1520_CKGEN00_REG_SW_EN_FRC_IMI2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1520_CKGEN00_REG_SW_EN_FRC_IMI2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1520_CKGEN00_REG_SW_EN_FRC_IMI2RV55FRC Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1520_CKGEN00_REG_SW_EN_FRC_IMI2RV55PQU Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1524_CKGEN00 (ckgen00 + 0x124)
    #define REG_1524_CKGEN00_REG_SW_EN_IMI2SHARE_SRAM_IMI Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1524_CKGEN00_REG_SW_EN_IMI2UFS Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1524_CKGEN00_REG_SW_EN_IMI2TSP Fld(1,2,AC_MSKB0)//[2:2]
#define REG_153C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_BDMA Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_DEMURA Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_FUART Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_M2MCU Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_M2RIU Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MCUIF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MIIC0 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MIIC1 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MIIC2 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MIIC3 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2MCU_XD2MIU Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2PAD_TOP Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_153C_CKGEN00_REG_SW_EN_XTAL_12M2PREARB2PMRIU Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1540_CKGEN00 (ckgen00 + 0x140)
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2TEST_CTRL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2VD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI1 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI2 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI3 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI4 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI5 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI6 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI7 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1540_CKGEN00_REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK Fld(1,13,AC_MSKB1)//[13:13]
#define REG_1558_CKGEN00 (ckgen00 + 0x158)
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2DSCRMB Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2GMAC Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2PEXTP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2SSUSB Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2TOP Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1558_CKGEN00_REG_SW_EN_XTAL_24M2USB20 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1578_CKGEN00 (ckgen00 + 0x178)
    #define REG_1578_CKGEN00_REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_157C_CKGEN00 (ckgen00 + 0x17C)
    #define REG_157C_CKGEN00_REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1580_CKGEN00 (ckgen00 + 0x180)
    #define REG_1580_CKGEN00_REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1584_CKGEN00 (ckgen00 + 0x184)
    #define REG_1584_CKGEN00_REG_SW_EN_ACIFIR2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1588_CKGEN00 (ckgen00 + 0x188)
    #define REG_1588_CKGEN00_REG_SW_EN_ADCD_I_IN2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_158C_CKGEN00 (ckgen00 + 0x18C)
    #define REG_158C_CKGEN00_REG_SW_EN_ADCD_I_OUT2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1590_CKGEN00 (ckgen00 + 0x190)
    #define REG_1590_CKGEN00_REG_SW_EN_ADCD_Q_IN2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1594_CKGEN00 (ckgen00 + 0x194)
    #define REG_1594_CKGEN00_REG_SW_EN_ADCD_Q_OUT2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1598_CKGEN00 (ckgen00 + 0x198)
    #define REG_1598_CKGEN00_REG_SW_EN_ADCD2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_159C_CKGEN00 (ckgen00 + 0x19C)
    #define REG_159C_CKGEN00_REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_15A0_CKGEN00_REG_SW_EN_ATSC_CE252DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A4_CKGEN00 (ckgen00 + 0x1A4)
    #define REG_15A4_CKGEN00_REG_SW_EN_ATSC_EQ252DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_15A8_CKGEN00_REG_SW_EN_ATSC200_PH12DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15AC_CKGEN00 (ckgen00 + 0x1AC)
    #define REG_15AC_CKGEN00_REG_SW_EN_ATSC200_PH32DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_15B0_CKGEN00_REG_SW_EN_ATSC252DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B4_CKGEN00 (ckgen00 + 0x1B4)
    #define REG_15B4_CKGEN00_REG_SW_EN_ATSC4002DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_15B8_CKGEN00_REG_SW_EN_ATSC502DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15BC_CKGEN00 (ckgen00 + 0x1BC)
    #define REG_15BC_CKGEN00_REG_SW_EN_DEC_XTAL_I2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_15C0_CKGEN00_REG_SW_EN_DEC_XTAL_Q2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C4_CKGEN00 (ckgen00 + 0x1C4)
    #define REG_15C4_CKGEN00_REG_SW_EN_DEINTER2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_15C8_CKGEN00_REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15CC_CKGEN00 (ckgen00 + 0x1CC)
    #define REG_15CC_CKGEN00_REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_15D0_CKGEN00_REG_SW_EN_DMD_DMA2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D4_CKGEN00 (ckgen00 + 0x1D4)
    #define REG_15D4_CKGEN00_REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_15D8_CKGEN00_REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15DC_CKGEN00 (ckgen00 + 0x1DC)
    #define REG_15DC_CKGEN00_REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_15E0_CKGEN00_REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E4_CKGEN00 (ckgen00 + 0x1E4)
    #define REG_15E4_CKGEN00_REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_15E8_CKGEN00_REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15EC_CKGEN00 (ckgen00 + 0x1EC)
    #define REG_15EC_CKGEN00_REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_15F0_CKGEN00_REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F4_CKGEN00 (ckgen00 + 0x1F4)
    #define REG_15F4_CKGEN00_REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_15F8_CKGEN00_REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15FC_CKGEN00 (ckgen00 + 0x1FC)
    #define REG_15FC_CKGEN00_REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1600_CKGEN00 (ckgen00 + 0x000)
    #define REG_1600_CKGEN00_REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1604_CKGEN00 (ckgen00 + 0x004)
    #define REG_1604_CKGEN00_REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1608_CKGEN00 (ckgen00 + 0x008)
    #define REG_1608_CKGEN00_REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_160C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_160C_CKGEN00_REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1610_CKGEN00 (ckgen00 + 0x010)
    #define REG_1610_CKGEN00_REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1614_CKGEN00 (ckgen00 + 0x014)
    #define REG_1614_CKGEN00_REG_SW_EN_DTMB_ADC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1618_CKGEN00 (ckgen00 + 0x018)
    #define REG_1618_CKGEN00_REG_SW_EN_DTMB_BCH2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_161C_CKGEN00 (ckgen00 + 0x01C)
    #define REG_161C_CKGEN00_REG_SW_EN_DTMB_BCH2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1620_CKGEN00 (ckgen00 + 0x020)
    #define REG_1620_CKGEN00_REG_SW_EN_DTMB_EQ0P25X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1624_CKGEN00 (ckgen00 + 0x024)
    #define REG_1624_CKGEN00_REG_SW_EN_DTMB_EQ0P5X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1628_CKGEN00 (ckgen00 + 0x028)
    #define REG_1628_CKGEN00_REG_SW_EN_DTMB_EQ1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_162C_CKGEN00 (ckgen00 + 0x02C)
    #define REG_162C_CKGEN00_REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1630_CKGEN00 (ckgen00 + 0x030)
    #define REG_1630_CKGEN00_REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1634_CKGEN00 (ckgen00 + 0x034)
    #define REG_1634_CKGEN00_REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1638_CKGEN00 (ckgen00 + 0x038)
    #define REG_1638_CKGEN00_REG_SW_EN_DTMB_EQ2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_163C_CKGEN00 (ckgen00 + 0x03C)
    #define REG_163C_CKGEN00_REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1640_CKGEN00 (ckgen00 + 0x040)
    #define REG_1640_CKGEN00_REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1644_CKGEN00 (ckgen00 + 0x044)
    #define REG_1644_CKGEN00_REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1648_CKGEN00 (ckgen00 + 0x048)
    #define REG_1648_CKGEN00_REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_164C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_164C_CKGEN00_REG_SW_EN_DTMB_INNER12X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1650_CKGEN00 (ckgen00 + 0x050)
    #define REG_1650_CKGEN00_REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1654_CKGEN00 (ckgen00 + 0x054)
    #define REG_1654_CKGEN00_REG_SW_EN_DTMB_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1658_CKGEN00 (ckgen00 + 0x058)
    #define REG_1658_CKGEN00_REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_165C_CKGEN00 (ckgen00 + 0x05C)
    #define REG_165C_CKGEN00_REG_SW_EN_DTMB_INNER24X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1660_CKGEN00 (ckgen00 + 0x060)
    #define REG_1660_CKGEN00_REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1664_CKGEN00 (ckgen00 + 0x064)
    #define REG_1664_CKGEN00_REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1668_CKGEN00 (ckgen00 + 0x068)
    #define REG_1668_CKGEN00_REG_SW_EN_DTMB_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_166C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_166C_CKGEN00_REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1670_CKGEN00 (ckgen00 + 0x070)
    #define REG_1670_CKGEN00_REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1674_CKGEN00 (ckgen00 + 0x074)
    #define REG_1674_CKGEN00_REG_SW_EN_DTMB_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1678_CKGEN00 (ckgen00 + 0x078)
    #define REG_1678_CKGEN00_REG_SW_EN_DTMB_INNER6X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_167C_CKGEN00 (ckgen00 + 0x07C)
    #define REG_167C_CKGEN00_REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1680_CKGEN00 (ckgen00 + 0x080)
    #define REG_1680_CKGEN00_REG_SW_EN_DTMB_INNER8X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1684_CKGEN00 (ckgen00 + 0x084)
    #define REG_1684_CKGEN00_REG_SW_EN_DTMB_LDPC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1688_CKGEN00 (ckgen00 + 0x088)
    #define REG_1688_CKGEN00_REG_SW_EN_DTMB_LDPC2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_168C_CKGEN00 (ckgen00 + 0x08C)
    #define REG_168C_CKGEN00_REG_SW_EN_DTMB_OUTER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1690_CKGEN00 (ckgen00 + 0x090)
    #define REG_1690_CKGEN00_REG_SW_EN_DTMB_OUTER1X2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1694_CKGEN00 (ckgen00 + 0x094)
    #define REG_1694_CKGEN00_REG_SW_EN_DTMB_OUTER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1698_CKGEN00 (ckgen00 + 0x098)
    #define REG_1698_CKGEN00_REG_SW_EN_DTMB_OUTER8X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_169C_CKGEN00 (ckgen00 + 0x09C)
    #define REG_169C_CKGEN00_REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_16A0_CKGEN00_REG_SW_EN_DVBS_OUTER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A4_CKGEN00 (ckgen00 + 0x0A4)
    #define REG_16A4_CKGEN00_REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_16A8_CKGEN00_REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16AC_CKGEN00 (ckgen00 + 0x0AC)
    #define REG_16AC_CKGEN00_REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_16B0_CKGEN00_REG_SW_EN_DVBS_OUTER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B4_CKGEN00 (ckgen00 + 0x0B4)
    #define REG_16B4_CKGEN00_REG_SW_EN_DVBS2_BCH2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_16B8_CKGEN00_REG_SW_EN_DVBS2_DEMAPPER2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16BC_CKGEN00 (ckgen00 + 0x0BC)
    #define REG_16BC_CKGEN00_REG_SW_EN_DVBS2_DISEQC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_16C0_CKGEN00_REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C4_CKGEN00 (ckgen00 + 0x0C4)
    #define REG_16C4_CKGEN00_REG_SW_EN_DVBS2_INNER2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_16C8_CKGEN00_REG_SW_EN_DVBS2_OPPRO2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16CC_CKGEN00 (ckgen00 + 0x0CC)
    #define REG_16CC_CKGEN00_REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_16D0_CKGEN00_REG_SW_EN_DVBT_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D4_CKGEN00 (ckgen00 + 0x0D4)
    #define REG_16D4_CKGEN00_REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_16D8_CKGEN00_REG_SW_EN_DVBT_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16DC_CKGEN00 (ckgen00 + 0x0DC)
    #define REG_16DC_CKGEN00_REG_SW_EN_DVBT_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_16E0_CKGEN00_REG_SW_EN_DVBT_OUTER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E4_CKGEN00 (ckgen00 + 0x0E4)
    #define REG_16E4_CKGEN00_REG_SW_EN_DVBT_OUTER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_16E8_CKGEN00_REG_SW_EN_DVBT2_DEMAPPER2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16EC_CKGEN00 (ckgen00 + 0x0EC)
    #define REG_16EC_CKGEN00_REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_16F0_CKGEN00_REG_SW_EN_DVBT2_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F4_CKGEN00 (ckgen00 + 0x0F4)
    #define REG_16F4_CKGEN00_REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_16F8_CKGEN00_REG_SW_EN_DVBT2_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16FC_CKGEN00 (ckgen00 + 0x0FC)
    #define REG_16FC_CKGEN00_REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1700_CKGEN00 (ckgen00 + 0x100)
    #define REG_1700_CKGEN00_REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1704_CKGEN00 (ckgen00 + 0x104)
    #define REG_1704_CKGEN00_REG_SW_EN_DVBT2_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1708_CKGEN00 (ckgen00 + 0x108)
    #define REG_1708_CKGEN00_REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_170C_CKGEN00 (ckgen00 + 0x10C)
    #define REG_170C_CKGEN00_REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1710_CKGEN00 (ckgen00 + 0x110)
    #define REG_1710_CKGEN00_REG_SW_EN_DVBT2_S2_BCH2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1718_CKGEN00 (ckgen00 + 0x118)
    #define REG_1718_CKGEN00_REG_SW_EN_DVBTC_ADC_I2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1720_CKGEN00 (ckgen00 + 0x120)
    #define REG_1720_CKGEN00_REG_SW_EN_DVBTC_ADC_Q2DMD_ANA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1724_CKGEN00 (ckgen00 + 0x124)
    #define REG_1724_CKGEN00_REG_SW_EN_DVBTC_ADC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1728_CKGEN00 (ckgen00 + 0x128)
    #define REG_1728_CKGEN00_REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_172C_CKGEN00 (ckgen00 + 0x12C)
    #define REG_172C_CKGEN00_REG_SW_EN_DVBTC_OUTER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1730_CKGEN00 (ckgen00 + 0x130)
    #define REG_1730_CKGEN00_REG_SW_EN_DVBTC_RS2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1734_CKGEN00 (ckgen00 + 0x134)
    #define REG_1734_CKGEN00_REG_SW_EN_DVBTC_SRAM12DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1738_CKGEN00 (ckgen00 + 0x138)
    #define REG_1738_CKGEN00_REG_SW_EN_DVBTC_SRAM32DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_173C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_173C_CKGEN00_REG_SW_EN_DVBTC_SRAM42DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1740_CKGEN00 (ckgen00 + 0x140)
    #define REG_1740_CKGEN00_REG_SW_EN_DVBTC_TS2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1744_CKGEN00 (ckgen00 + 0x144)
    #define REG_1744_CKGEN00_REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1748_CKGEN00 (ckgen00 + 0x148)
    #define REG_1748_CKGEN00_REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_174C_CKGEN00 (ckgen00 + 0x14C)
    #define REG_174C_CKGEN00_REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1750_CKGEN00 (ckgen00 + 0x150)
    #define REG_1750_CKGEN00_REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1754_CKGEN00 (ckgen00 + 0x154)
    #define REG_1754_CKGEN00_REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1758_CKGEN00 (ckgen00 + 0x158)
    #define REG_1758_CKGEN00_REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_175C_CKGEN00 (ckgen00 + 0x15C)
    #define REG_175C_CKGEN00_REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1760_CKGEN00 (ckgen00 + 0x160)
    #define REG_1760_CKGEN00_REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1764_CKGEN00 (ckgen00 + 0x164)
    #define REG_1764_CKGEN00_REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1768_CKGEN00 (ckgen00 + 0x168)
    #define REG_1768_CKGEN00_REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_176C_CKGEN00 (ckgen00 + 0x16C)
    #define REG_176C_CKGEN00_REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1770_CKGEN00 (ckgen00 + 0x170)
    #define REG_1770_CKGEN00_REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1774_CKGEN00 (ckgen00 + 0x174)
    #define REG_1774_CKGEN00_REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1778_CKGEN00 (ckgen00 + 0x178)
    #define REG_1778_CKGEN00_REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_177C_CKGEN00 (ckgen00 + 0x17C)
    #define REG_177C_CKGEN00_REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1780_CKGEN00 (ckgen00 + 0x180)
    #define REG_1780_CKGEN00_REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1784_CKGEN00 (ckgen00 + 0x184)
    #define REG_1784_CKGEN00_REG_SW_EN_ISDBT_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1788_CKGEN00 (ckgen00 + 0x188)
    #define REG_1788_CKGEN00_REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_178C_CKGEN00 (ckgen00 + 0x18C)
    #define REG_178C_CKGEN00_REG_SW_EN_ISDBT_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1790_CKGEN00 (ckgen00 + 0x190)
    #define REG_1790_CKGEN00_REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1794_CKGEN00 (ckgen00 + 0x194)
    #define REG_1794_CKGEN00_REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN00_6
#define REG_1798_CKGEN00 (ckgen00 + 0x198)
    #define REG_1798_CKGEN00_REG_SW_EN_ISDBT_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_179C_CKGEN00 (ckgen00 + 0x19C)
    #define REG_179C_CKGEN00_REG_SW_EN_ISDBT_OUTER_RS2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_17A0_CKGEN00_REG_SW_EN_ISDBT_OUTER12X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A4_CKGEN00 (ckgen00 + 0x1A4)
    #define REG_17A4_CKGEN00_REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_17A8_CKGEN00_REG_SW_EN_ISDBT_OUTER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17AC_CKGEN00 (ckgen00 + 0x1AC)
    #define REG_17AC_CKGEN00_REG_SW_EN_ISDBT_OUTER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_17B0_CKGEN00_REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B4_CKGEN00 (ckgen00 + 0x1B4)
    #define REG_17B4_CKGEN00_REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_17B8_CKGEN00_REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17BC_CKGEN00 (ckgen00 + 0x1BC)
    #define REG_17BC_CKGEN00_REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_17C0_CKGEN00_REG_SW_EN_ISDBT_OUTER6X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C4_CKGEN00 (ckgen00 + 0x1C4)
    #define REG_17C4_CKGEN00_REG_SW_EN_LDPC1X2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_17C8_CKGEN00_REG_SW_EN_LDPC2X2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_17E0_CKGEN00_REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E4_CKGEN00 (ckgen00 + 0x1E4)
    #define REG_17E4_CKGEN00_REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_17E8_CKGEN00_REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17EC_CKGEN00 (ckgen00 + 0x1EC)
    #define REG_17EC_CKGEN00_REG_SW_EN_SRAM_SHARE_00_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_17F0_CKGEN00_REG_SW_EN_SRAM_SHARE_00_12DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F4_CKGEN00 (ckgen00 + 0x1F4)
    #define REG_17F4_CKGEN00_REG_SW_EN_SRAM_SHARE_01_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_17F8_CKGEN00_REG_SW_EN_SRAM_SHARE_02_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17FC_CKGEN00 (ckgen00 + 0x1FC)
    #define REG_17FC_CKGEN00_REG_SW_EN_SRAM_SHARE_03_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1800_CKGEN00 (ckgen00 + 0x000)
    #define REG_1800_CKGEN00_REG_SW_EN_SRAM_SHARE_03_12DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1804_CKGEN00 (ckgen00 + 0x004)
    #define REG_1804_CKGEN00_REG_SW_EN_SRAM_SHARE_04_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1808_CKGEN00 (ckgen00 + 0x008)
    #define REG_1808_CKGEN00_REG_SW_EN_SRAM_SHARE_04_12DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_180C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_180C_CKGEN00_REG_SW_EN_SRAM_SHARE_052DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1810_CKGEN00 (ckgen00 + 0x010)
    #define REG_1810_CKGEN00_REG_SW_EN_SRAM_SHARE_062DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1814_CKGEN00 (ckgen00 + 0x014)
    #define REG_1814_CKGEN00_REG_SW_EN_SRAM_SHARE_072DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1818_CKGEN00 (ckgen00 + 0x018)
    #define REG_1818_CKGEN00_REG_SW_EN_SRAM_SHARE_082DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_181C_CKGEN00 (ckgen00 + 0x01C)
    #define REG_181C_CKGEN00_REG_SW_EN_SRAM_SHARE_092DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1820_CKGEN00 (ckgen00 + 0x020)
    #define REG_1820_CKGEN00_REG_SW_EN_SRAM_SHARE_102DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1824_CKGEN00 (ckgen00 + 0x024)
    #define REG_1824_CKGEN00_REG_SW_EN_SRAM_SHARE_112DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1828_CKGEN00 (ckgen00 + 0x028)
    #define REG_1828_CKGEN00_REG_SW_EN_SRAM_SHARE_122DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_182C_CKGEN00 (ckgen00 + 0x02C)
    #define REG_182C_CKGEN00_REG_SW_EN_SRAM_SHARE_132DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1830_CKGEN00 (ckgen00 + 0x030)
    #define REG_1830_CKGEN00_REG_SW_EN_SRAM_SHARE_14_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1834_CKGEN00 (ckgen00 + 0x034)
    #define REG_1834_CKGEN00_REG_SW_EN_SRAM_SHARE_14_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1838_CKGEN00 (ckgen00 + 0x038)
    #define REG_1838_CKGEN00_REG_SW_EN_SRAM_SHARE_15_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_183C_CKGEN00 (ckgen00 + 0x03C)
    #define REG_183C_CKGEN00_REG_SW_EN_SRAM_SHARE_15_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1840_CKGEN00 (ckgen00 + 0x040)
    #define REG_1840_CKGEN00_REG_SW_EN_SRAM_SHARE_162DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1844_CKGEN00 (ckgen00 + 0x044)
    #define REG_1844_CKGEN00_REG_SW_EN_SRAM_SHARE_182DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1848_CKGEN00 (ckgen00 + 0x048)
    #define REG_1848_CKGEN00_REG_SW_EN_SRAM_SHARE_192DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_184C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_184C_CKGEN00_REG_SW_EN_SRAM_SHARE_202DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1850_CKGEN00 (ckgen00 + 0x050)
    #define REG_1850_CKGEN00_REG_SW_EN_SRAM_SHARE_212DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1854_CKGEN00 (ckgen00 + 0x054)
    #define REG_1854_CKGEN00_REG_SW_EN_SRAM_SHARE_222DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1858_CKGEN00 (ckgen00 + 0x058)
    #define REG_1858_CKGEN00_REG_SW_EN_SRAM_SHARE_232DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_185C_CKGEN00 (ckgen00 + 0x05C)
    #define REG_185C_CKGEN00_REG_SW_EN_SRAM_SHARE_242DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1860_CKGEN00 (ckgen00 + 0x060)
    #define REG_1860_CKGEN00_REG_SW_EN_SRAM_SHARE_262DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1864_CKGEN00 (ckgen00 + 0x064)
    #define REG_1864_CKGEN00_REG_SW_EN_SRAM_SHARE_272DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1868_CKGEN00 (ckgen00 + 0x068)
    #define REG_1868_CKGEN00_REG_SW_EN_SRAM_SHARE_282DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_186C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_186C_CKGEN00_REG_SW_EN_SRAM_SHARE_292DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1870_CKGEN00 (ckgen00 + 0x070)
    #define REG_1870_CKGEN00_REG_SW_EN_SRAM_SHARE_342DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1874_CKGEN00 (ckgen00 + 0x074)
    #define REG_1874_CKGEN00_REG_SW_EN_SRAM_SHARE_352DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1878_CKGEN00 (ckgen00 + 0x078)
    #define REG_1878_CKGEN00_REG_SW_EN_SRAM_SHARE_362DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_187C_CKGEN00 (ckgen00 + 0x07C)
    #define REG_187C_CKGEN00_REG_SW_EN_SRAM_SHARE_402DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1880_CKGEN00 (ckgen00 + 0x080)
    #define REG_1880_CKGEN00_REG_SW_EN_SRAM_SHARE_422DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1884_CKGEN00 (ckgen00 + 0x084)
    #define REG_1884_CKGEN00_REG_SW_EN_SRAM_SHARE_442DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1888_CKGEN00 (ckgen00 + 0x088)
    #define REG_1888_CKGEN00_REG_SW_EN_SRAM_SHARE_462DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_188C_CKGEN00 (ckgen00 + 0x08C)
    #define REG_188C_CKGEN00_REG_SW_EN_SRAM_SHARE_472DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1890_CKGEN00 (ckgen00 + 0x090)
    #define REG_1890_CKGEN00_REG_SW_EN_SRAM_SHARE_50_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1894_CKGEN00 (ckgen00 + 0x094)
    #define REG_1894_CKGEN00_REG_SW_EN_SRAM_SHARE_52_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1898_CKGEN00 (ckgen00 + 0x098)
    #define REG_1898_CKGEN00_REG_SW_EN_SRAM_SHARE_53_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_189C_CKGEN00 (ckgen00 + 0x09C)
    #define REG_189C_CKGEN00_REG_SW_EN_SRAM_SHARE_55_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_18A0_CKGEN00_REG_SW_EN_SRAM_SHARE_562DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A4_CKGEN00 (ckgen00 + 0x0A4)
    #define REG_18A4_CKGEN00_REG_SW_EN_SRAM_SHARE_572DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_18A8_CKGEN00_REG_SW_EN_SRAM_SHARE_582DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18AC_CKGEN00 (ckgen00 + 0x0AC)
    #define REG_18AC_CKGEN00_REG_SW_EN_SRAM_SHARE_592DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_18B0_CKGEN00_REG_SW_EN_SRAM_SHARE_602DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B4_CKGEN00 (ckgen00 + 0x0B4)
    #define REG_18B4_CKGEN00_REG_SW_EN_SRAM_SHARE_612DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_18B8_CKGEN00_REG_SW_EN_SRAM_SHARE_622DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18BC_CKGEN00 (ckgen00 + 0x0BC)
    #define REG_18BC_CKGEN00_REG_SW_EN_SRAM_SHARE_642DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_18C0_CKGEN00_REG_SW_EN_SRAM_SHARE_662DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C4_CKGEN00 (ckgen00 + 0x0C4)
    #define REG_18C4_CKGEN00_REG_SW_EN_SRAM_SHARE_672DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_18C8_CKGEN00_REG_SW_EN_SRAM_SHARE_68_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18CC_CKGEN00 (ckgen00 + 0x0CC)
    #define REG_18CC_CKGEN00_REG_SW_EN_SRAM_SHARE_68_22DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_18D0_CKGEN00_REG_SW_EN_SRAM_SHARE_69_02DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D4_CKGEN00 (ckgen00 + 0x0D4)
    #define REG_18D4_CKGEN00_REG_SW_EN_SRAM_SHARE_702DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_18D8_CKGEN00_REG_SW_EN_SRAM_SHARE_712DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18DC_CKGEN00 (ckgen00 + 0x0DC)
    #define REG_18DC_CKGEN00_REG_SW_EN_SRAM_SHARE_772DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_18E0_CKGEN00_REG_SW_EN_SRAM_SHARE_792DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E4_CKGEN00 (ckgen00 + 0x0E4)
    #define REG_18E4_CKGEN00_REG_SW_EN_SRAM_SHARE_812DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_18E8_CKGEN00_REG_SW_EN_SRAM_SHARE_852DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18EC_CKGEN00 (ckgen00 + 0x0EC)
    #define REG_18EC_CKGEN00_REG_SW_EN_SRAM_SHARE_872DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_18F0_CKGEN00_REG_SW_EN_SRAM_SHARE_892DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F4_CKGEN00 (ckgen00 + 0x0F4)
    #define REG_18F4_CKGEN00_REG_SW_EN_SRAM_SHARE_912DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_18F8_CKGEN00_REG_SW_EN_SRAM_SHARE_922DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18FC_CKGEN00 (ckgen00 + 0x0FC)
    #define REG_18FC_CKGEN00_REG_SW_EN_SRAM_SHARE_932DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1900_CKGEN00 (ckgen00 + 0x100)
    #define REG_1900_CKGEN00_REG_SW_EN_SRAM_SHARE_942DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1904_CKGEN00 (ckgen00 + 0x104)
    #define REG_1904_CKGEN00_REG_SW_EN_SRAM_SHARE_962DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1908_CKGEN00 (ckgen00 + 0x108)
    #define REG_1908_CKGEN00_REG_SW_EN_SRAM_SHARE_982DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_190C_CKGEN00 (ckgen00 + 0x10C)
    #define REG_190C_CKGEN00_REG_SW_EN_SRAM_SHARE_992DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1910_CKGEN00 (ckgen00 + 0x110)
    #define REG_1910_CKGEN00_REG_SW_EN_SRAM_SHARE_1002DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1914_CKGEN00 (ckgen00 + 0x114)
    #define REG_1914_CKGEN00_REG_SW_EN_SRAM_SHARE_1032DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1918_CKGEN00 (ckgen00 + 0x118)
    #define REG_1918_CKGEN00_REG_SW_EN_SRAM_SHARE_1052DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_191C_CKGEN00 (ckgen00 + 0x11C)
    #define REG_191C_CKGEN00_REG_SW_EN_SRAM_SHARE_1072DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1920_CKGEN00 (ckgen00 + 0x120)
    #define REG_1920_CKGEN00_REG_SW_EN_SRAM_SHARE_1092DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1924_CKGEN00 (ckgen00 + 0x124)
    #define REG_1924_CKGEN00_REG_SW_EN_SRAM_SHARE_1102DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1928_CKGEN00 (ckgen00 + 0x128)
    #define REG_1928_CKGEN00_REG_SW_EN_SRAM_SHARE_1112DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_192C_CKGEN00 (ckgen00 + 0x12C)
    #define REG_192C_CKGEN00_REG_SW_EN_SRAM_SHARE_1122DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1930_CKGEN00 (ckgen00 + 0x130)
    #define REG_1930_CKGEN00_REG_SW_EN_SRAM_SHARE_1242DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1934_CKGEN00 (ckgen00 + 0x134)
    #define REG_1934_CKGEN00_REG_SW_EN_SRAM_SHARE_1282DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1938_CKGEN00 (ckgen00 + 0x138)
    #define REG_1938_CKGEN00_REG_SW_EN_SRAM_SHARE_1292DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_193C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_193C_CKGEN00_REG_SW_EN_SRAM_SHARE_1302DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1940_CKGEN00 (ckgen00 + 0x140)
    #define REG_1940_CKGEN00_REG_SW_EN_SRAM_SHARE_1312DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1944_CKGEN00 (ckgen00 + 0x144)
    #define REG_1944_CKGEN00_REG_SW_EN_SRAM_SHARE_1322DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1948_CKGEN00 (ckgen00 + 0x148)
    #define REG_1948_CKGEN00_REG_SW_EN_SRAM_SHARE_134_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_194C_CKGEN00 (ckgen00 + 0x14C)
    #define REG_194C_CKGEN00_REG_SW_EN_SRAM_SHARE_134_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1950_CKGEN00 (ckgen00 + 0x150)
    #define REG_1950_CKGEN00_REG_SW_EN_SRAM_SHARE_136_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1954_CKGEN00 (ckgen00 + 0x154)
    #define REG_1954_CKGEN00_REG_SW_EN_SRAM_SHARE_136_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1958_CKGEN00 (ckgen00 + 0x158)
    #define REG_1958_CKGEN00_REG_SW_EN_SRAM_SHARE_137_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_195C_CKGEN00 (ckgen00 + 0x15C)
    #define REG_195C_CKGEN00_REG_SW_EN_SRAM_SHARE_137_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1960_CKGEN00 (ckgen00 + 0x160)
    #define REG_1960_CKGEN00_REG_SW_EN_SRAM_SHARE_138_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1964_CKGEN00 (ckgen00 + 0x164)
    #define REG_1964_CKGEN00_REG_SW_EN_SRAM_SHARE_138_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1968_CKGEN00 (ckgen00 + 0x168)
    #define REG_1968_CKGEN00_REG_SW_EN_SRAM_SHARE_139_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_196C_CKGEN00 (ckgen00 + 0x16C)
    #define REG_196C_CKGEN00_REG_SW_EN_SRAM_SHARE_139_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1970_CKGEN00 (ckgen00 + 0x170)
    #define REG_1970_CKGEN00_REG_SW_EN_SRAM_SHARE_140_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1974_CKGEN00 (ckgen00 + 0x174)
    #define REG_1974_CKGEN00_REG_SW_EN_SRAM_SHARE_140_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1978_CKGEN00 (ckgen00 + 0x178)
    #define REG_1978_CKGEN00_REG_SW_EN_SRAM_SHARE_141_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_197C_CKGEN00 (ckgen00 + 0x17C)
    #define REG_197C_CKGEN00_REG_SW_EN_SRAM_SHARE_141_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1980_CKGEN00 (ckgen00 + 0x180)
    #define REG_1980_CKGEN00_REG_SW_EN_SRAM_SHARE_142_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1984_CKGEN00 (ckgen00 + 0x184)
    #define REG_1984_CKGEN00_REG_SW_EN_SRAM_SHARE_142_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1988_CKGEN00 (ckgen00 + 0x188)
    #define REG_1988_CKGEN00_REG_SW_EN_SRAM_SHARE_143_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_198C_CKGEN00 (ckgen00 + 0x18C)
    #define REG_198C_CKGEN00_REG_SW_EN_SRAM_SHARE_143_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1990_CKGEN00 (ckgen00 + 0x190)
    #define REG_1990_CKGEN00_REG_SW_EN_SRAM_SHARE_144_R2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1994_CKGEN00 (ckgen00 + 0x194)
    #define REG_1994_CKGEN00_REG_SW_EN_SRAM_SHARE_144_W2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1998_CKGEN00 (ckgen00 + 0x198)
    #define REG_1998_CKGEN00_REG_SW_EN_TDP_JL_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_199C_CKGEN00 (ckgen00 + 0x19C)
    #define REG_199C_CKGEN00_REG_SW_EN_TDP_JL_INNER4X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_19A0_CKGEN00_REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A4_CKGEN00 (ckgen00 + 0x1A4)
    #define REG_19A4_CKGEN00_REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_19A8_CKGEN00_REG_SW_EN_TR2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19AC_CKGEN00 (ckgen00 + 0x1AC)
    #define REG_19AC_CKGEN00_REG_SW_EN_TS_IN2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_19B0_CKGEN00_REG_SW_EN_VIFDBB_144M2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B4_CKGEN00 (ckgen00 + 0x1B4)
    #define REG_19B4_CKGEN00_REG_SW_EN_VIFDBB_43M2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_19B8_CKGEN00_REG_SW_EN_VIFDBB_86M2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19BC_CKGEN00 (ckgen00 + 0x1BC)
    #define REG_19BC_CKGEN00_REG_SW_EN_VIFDBB_DAC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_19C0_CKGEN00_REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C4_CKGEN00 (ckgen00 + 0x1C4)
    #define REG_19C4_CKGEN00_REG_SW_EN_VIFDBB_VDAC2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_19C8_CKGEN00_REG_SW_EN_XTAL_12M2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19CC_CKGEN00 (ckgen00 + 0x1CC)
    #define REG_19CC_CKGEN00_REG_SW_EN_XTAL_24M2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_19D0_CKGEN00_REG_SW_EN_XTAL_24M2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D4_CKGEN00 (ckgen00 + 0x1D4)
    #define REG_19D4_CKGEN00_REG_SW_EN_XTAL_12M2DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A00_CKGEN00 (ckgen00 + 0x000)
    #define REG_1A00_CKGEN00_REG_SW_EN_AESDMA2DSCRMB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A0C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_1A0C_CKGEN00_REG_SW_EN_CILINK_2B_RX2CILINK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A10_CKGEN00 (ckgen00 + 0x010)
    #define REG_1A10_CKGEN00_REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A14_CKGEN00 (ckgen00 + 0x014)
    #define REG_1A14_CKGEN00_REG_SW_EN_CILINK_2B_TX2CILINK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A18_CKGEN00 (ckgen00 + 0x018)
    #define REG_1A18_CKGEN00_REG_SW_EN_CILINK_IF2CILINK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A24_CKGEN00 (ckgen00 + 0x024)
    #define REG_1A24_CKGEN00_REG_SW_EN_SMART_SYNTH_272PIU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A28_CKGEN00 (ckgen00 + 0x028)
    #define REG_1A28_CKGEN00_REG_SW_EN_SMART_SYNTH_4322PIU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A2C_CKGEN00 (ckgen00 + 0x02C)
    #define REG_1A2C_CKGEN00_REG_SW_EN_SMART2_SYNTH_272PIU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A30_CKGEN00 (ckgen00 + 0x030)
    #define REG_1A30_CKGEN00_REG_SW_EN_SMART2_SYNTH_4322PIU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A34_CKGEN00 (ckgen00 + 0x034)
    #define REG_1A34_CKGEN00_REG_SW_EN_SMART22PIU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A38_CKGEN00 (ckgen00 + 0x038)
    #define REG_1A38_CKGEN00_REG_SW_EN_SMART2PIU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A48_CKGEN00 (ckgen00 + 0x048)
    #define REG_1A48_CKGEN00_REG_SW_EN_FIQ0_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A4C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_1A4C_CKGEN00_REG_SW_EN_MM0_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A50_CKGEN00 (ckgen00 + 0x050)
    #define REG_1A50_CKGEN00_REG_SW_EN_MM1_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A54_CKGEN00 (ckgen00 + 0x054)
    #define REG_1A54_CKGEN00_REG_SW_EN_PARSER2TSP Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A54_CKGEN00_REG_SW_EN_PARSER2VD_PES_PARSER Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1A54_CKGEN00_REG_SW_EN_VIVA_PARSER2PARSER Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1A58_CKGEN00 (ckgen00 + 0x058)
    #define REG_1A58_CKGEN00_REG_SW_EN_PVR1_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A5C_CKGEN00 (ckgen00 + 0x05C)
    #define REG_1A5C_CKGEN00_REG_SW_EN_PVR2_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A60_CKGEN00 (ckgen00 + 0x060)
    #define REG_1A60_CKGEN00_REG_SW_EN_PVR3_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A64_CKGEN00 (ckgen00 + 0x064)
    #define REG_1A64_CKGEN00_REG_SW_EN_PVR4_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A6C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_1A6C_CKGEN00_REG_SW_EN_STAMP2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A70_CKGEN00 (ckgen00 + 0x070)
    #define REG_1A70_CKGEN00_REG_SW_EN_STAMP2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A74_CKGEN00 (ckgen00 + 0x074)
    #define REG_1A74_CKGEN00_REG_SW_EN_STAMP2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A78_CKGEN00 (ckgen00 + 0x078)
    #define REG_1A78_CKGEN00_REG_SW_EN_SYN_STC02TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A7C_CKGEN00 (ckgen00 + 0x07C)
    #define REG_1A7C_CKGEN00_REG_SW_EN_SYN_STC12TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN00_7
#define REG_1A80_CKGEN00 (ckgen00 + 0x080)
    #define REG_1A80_CKGEN00_REG_SW_EN_SYN_STC22TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A84_CKGEN00 (ckgen00 + 0x084)
    #define REG_1A84_CKGEN00_REG_SW_EN_SYN_STC32TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A88_CKGEN00 (ckgen00 + 0x088)
    #define REG_1A88_CKGEN00_REG_SW_EN_SYS_TIME0_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A8C_CKGEN00 (ckgen00 + 0x08C)
    #define REG_1A8C_CKGEN00_REG_SW_EN_SYS_TIME1_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A90_CKGEN00 (ckgen00 + 0x090)
    #define REG_1A90_CKGEN00_REG_SW_EN_SYS_TIME2_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A94_CKGEN00 (ckgen00 + 0x094)
    #define REG_1A94_CKGEN00_REG_SW_EN_SYS_TIME3_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A98_CKGEN00 (ckgen00 + 0x098)
    #define REG_1A98_CKGEN00_REG_SW_EN_TLV0_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A9C_CKGEN00 (ckgen00 + 0x09C)
    #define REG_1A9C_CKGEN00_REG_SW_EN_TLV1_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AA0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_1AA0_CKGEN00_REG_SW_EN_TLV2_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AA8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_1AA8_CKGEN00_REG_SW_EN_TS_ALP02TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AAC_CKGEN00 (ckgen00 + 0x0AC)
    #define REG_1AAC_CKGEN00_REG_SW_EN_TS_ALP12TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB4_CKGEN00 (ckgen00 + 0x0B4)
    #define REG_1AB4_CKGEN00_REG_SW_EN_TS_SAMPLE2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_1AB8_CKGEN00_REG_SW_EN_TS_TX_C12CILINK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ABC_CKGEN00 (ckgen00 + 0x0BC)
    #define REG_1ABC_CKGEN00_REG_SW_EN_TS_TX_C22CILINK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AC0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_1AC0_CKGEN00_REG_SW_EN_TS0_IN_DFT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AC4_CKGEN00 (ckgen00 + 0x0C4)
    #define REG_1AC4_CKGEN00_REG_SW_EN_TS02TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AC8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_1AC8_CKGEN00_REG_SW_EN_TS1_IN_DFT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ACC_CKGEN00 (ckgen00 + 0x0CC)
    #define REG_1ACC_CKGEN00_REG_SW_EN_TS12TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_1AD0_CKGEN00_REG_SW_EN_TS2_IN_DFT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD4_CKGEN00 (ckgen00 + 0x0D4)
    #define REG_1AD4_CKGEN00_REG_SW_EN_TS22TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_1AD8_CKGEN00_REG_SW_EN_TS3_IN_DFT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ADC_CKGEN00 (ckgen00 + 0x0DC)
    #define REG_1ADC_CKGEN00_REG_SW_EN_TS4_IN_DFT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_1AE0_CKGEN00_REG_SW_EN_TS5_IN_DFT2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE4_CKGEN00 (ckgen00 + 0x0E4)
    #define REG_1AE4_CKGEN00_REG_SW_EN_TSFI2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_1AE8_CKGEN00_REG_SW_EN_TSIF0_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AEC_CKGEN00 (ckgen00 + 0x0EC)
    #define REG_1AEC_CKGEN00_REG_SW_EN_TSO_CH1_27M2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_1AF0_CKGEN00_REG_SW_EN_TSO_CH12TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF4_CKGEN00 (ckgen00 + 0x0F4)
    #define REG_1AF4_CKGEN00_REG_SW_EN_TSO_CH5_27M2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_1AF8_CKGEN00_REG_SW_EN_TSO_CH52TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AFC_CKGEN00 (ckgen00 + 0x0FC)
    #define REG_1AFC_CKGEN00_REG_SW_EN_TSO_CH6_27M2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B00_CKGEN00 (ckgen00 + 0x100)
    #define REG_1B00_CKGEN00_REG_SW_EN_TSO_CH62TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B04_CKGEN00 (ckgen00 + 0x104)
    #define REG_1B04_CKGEN00_REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B08_CKGEN00 (ckgen00 + 0x108)
    #define REG_1B08_CKGEN00_REG_SW_EN_TSO_OUT2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B0C_CKGEN00 (ckgen00 + 0x10C)
    #define REG_1B0C_CKGEN00_REG_SW_EN_TSO_S2P12TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B10_CKGEN00 (ckgen00 + 0x110)
    #define REG_1B10_CKGEN00_REG_SW_EN_TSO_S2P2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B14_CKGEN00 (ckgen00 + 0x114)
    #define REG_1B14_CKGEN00_REG_SW_EN_TSO_TRACE_IN2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B18_CKGEN00 (ckgen00 + 0x118)
    #define REG_1B18_CKGEN00_REG_SW_EN_TSO_TRACE2TSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B1C_CKGEN00 (ckgen00 + 0x11C)
    #define REG_1B1C_CKGEN00_REG_SW_EN_TSO2_CH1_27M2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B20_CKGEN00 (ckgen00 + 0x120)
    #define REG_1B20_CKGEN00_REG_SW_EN_TSO2_CH12TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B24_CKGEN00 (ckgen00 + 0x124)
    #define REG_1B24_CKGEN00_REG_SW_EN_TSO2_CH5_27M2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B28_CKGEN00 (ckgen00 + 0x128)
    #define REG_1B28_CKGEN00_REG_SW_EN_TSO2_CH52TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B2C_CKGEN00 (ckgen00 + 0x12C)
    #define REG_1B2C_CKGEN00_REG_SW_EN_TSO2_CH6_27M2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B30_CKGEN00 (ckgen00 + 0x130)
    #define REG_1B30_CKGEN00_REG_SW_EN_TSO2_CH62TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B34_CKGEN00 (ckgen00 + 0x134)
    #define REG_1B34_CKGEN00_REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B38_CKGEN00 (ckgen00 + 0x138)
    #define REG_1B38_CKGEN00_REG_SW_EN_TSO2_OUT2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B3C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_1B3C_CKGEN00_REG_SW_EN_TSO2_S2P12TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B40_CKGEN00 (ckgen00 + 0x140)
    #define REG_1B40_CKGEN00_REG_SW_EN_TSO2_S2P2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B44_CKGEN00 (ckgen00 + 0x144)
    #define REG_1B44_CKGEN00_REG_SW_EN_TSO2_TRACE_IN2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B48_CKGEN00 (ckgen00 + 0x148)
    #define REG_1B48_CKGEN00_REG_SW_EN_TSO2_TRACE2TSO2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B4C_CKGEN00 (ckgen00 + 0x14C)
    #define REG_1B4C_CKGEN00_REG_SW_EN_TSP2DSCRMB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B50_CKGEN00 (ckgen00 + 0x150)
    #define REG_1B50_CKGEN00_REG_SW_EN_TSP2TSO Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B50_CKGEN00_REG_SW_EN_TSP2TSO2 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B50_CKGEN00_REG_SW_EN_TSP2TSP Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1B54_CKGEN00 (ckgen00 + 0x154)
    #define REG_1B54_CKGEN00_REG_SW_EN_TS_TLV02TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B58_CKGEN00 (ckgen00 + 0x158)
    #define REG_1B58_CKGEN00_REG_SW_EN_TS_TLV12TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B5C_CKGEN00 (ckgen00 + 0x15C)
    #define REG_1B5C_CKGEN00_REG_SW_EN_TS_TLV22TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B60_CKGEN00 (ckgen00 + 0x160)
    #define REG_1B60_CKGEN00_REG_SW_EN_PATH0_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B64_CKGEN00 (ckgen00 + 0x164)
    #define REG_1B64_CKGEN00_REG_SW_EN_PATH1_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B68_CKGEN00 (ckgen00 + 0x168)
    #define REG_1B68_CKGEN00_REG_SW_EN_PATH2_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B6C_CKGEN00 (ckgen00 + 0x16C)
    #define REG_1B6C_CKGEN00_REG_SW_EN_PATH_FI_27M2TSP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B80_CKGEN00 (ckgen00 + 0x180)
    #define REG_1B80_CKGEN00_REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS_1B80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B84_CKGEN00 (ckgen00 + 0x184)
    #define REG_1B84_CKGEN00_REG_SW_EN_AU_R2_DFS2AUDIO_R2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B88_CKGEN00 (ckgen00 + 0x188)
    #define REG_1B88_CKGEN00_REG_SW_EN_AU_R2_PLL2AUDIO_R2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B8C_CKGEN00 (ckgen00 + 0x18C)
    #define REG_1B8C_CKGEN00_REG_SW_EN_AU_R2_WB2AUDIO_R2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B90_CKGEN00 (ckgen00 + 0x190)
    #define REG_1B90_CKGEN00_REG_SW_EN_AUSDM_3M2AUSDM_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B94_CKGEN00 (ckgen00 + 0x194)
    #define REG_1B94_CKGEN00_REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B98_CKGEN00 (ckgen00 + 0x198)
    #define REG_1B98_CKGEN00_REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B9C_CKGEN00 (ckgen00 + 0x19C)
    #define REG_1B9C_CKGEN00_REG_SW_EN_EARC_AUDIO2EARC_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BA0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_1BA0_CKGEN00_REG_SW_EN_VIVA_AB_MAC2AB_MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BA4_CKGEN00 (ckgen00 + 0x1A4)
    #define REG_1BA4_CKGEN00_REG_SW_EN_VIVA_AB3_MAC2AB3_MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BA8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_1BA8_CKGEN00_REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BAC_CKGEN00 (ckgen00 + 0x1AC)
    #define REG_1BAC_CKGEN00_REG_SW_EN_VIVA_AU_MCU2AU_MCU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BB0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_1BB0_CKGEN00_REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BB4_CKGEN00 (ckgen00 + 0x1B4)
    #define REG_1BB4_CKGEN00_REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BB8_CKGEN00 (ckgen00 + 0x1B8)
    #define REG_1BB8_CKGEN00_REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BBC_CKGEN00 (ckgen00 + 0x1BC)
    #define REG_1BBC_CKGEN00_REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC0_CKGEN00 (ckgen00 + 0x1C0)
    #define REG_1BC0_CKGEN00_REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC4_CKGEN00 (ckgen00 + 0x1C4)
    #define REG_1BC4_CKGEN00_REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC8_CKGEN00 (ckgen00 + 0x1C8)
    #define REG_1BC8_CKGEN00_REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BCC_CKGEN00 (ckgen00 + 0x1CC)
    #define REG_1BCC_CKGEN00_REG_SW_EN_VIVA_BCLK_I2S_DECODER2BCLK_I2S_DECODER Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD0_CKGEN00 (ckgen00 + 0x1D0)
    #define REG_1BD0_CKGEN00_REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD4_CKGEN00 (ckgen00 + 0x1D4)
    #define REG_1BD4_CKGEN00_REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD8_CKGEN00 (ckgen00 + 0x1D8)
    #define REG_1BD8_CKGEN00_REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BDC_CKGEN00 (ckgen00 + 0x1DC)
    #define REG_1BDC_CKGEN00_REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE0_CKGEN00 (ckgen00 + 0x1E0)
    #define REG_1BE0_CKGEN00_REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE4_CKGEN00 (ckgen00 + 0x1E4)
    #define REG_1BE4_CKGEN00_REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE8_CKGEN00 (ckgen00 + 0x1E8)
    #define REG_1BE8_CKGEN00_REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BEC_CKGEN00 (ckgen00 + 0x1EC)
    #define REG_1BEC_CKGEN00_REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_1BF0_CKGEN00_REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF4_CKGEN00 (ckgen00 + 0x1F4)
    #define REG_1BF4_CKGEN00_REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_1BF8_CKGEN00_REG_SW_EN_VIVA_CODEC_SH2CODEC_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BFC_CKGEN00 (ckgen00 + 0x1FC)
    #define REG_1BFC_CKGEN00_REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C00_CKGEN00 (ckgen00 + 0x000)
    #define REG_1C00_CKGEN00_REG_SW_EN_VIVA_DSP2DSP_230 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C04_CKGEN00 (ckgen00 + 0x004)
    #define REG_1C04_CKGEN00_REG_SW_EN_VIVA_DSP2DSP_230_1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C08_CKGEN00 (ckgen00 + 0x008)
    #define REG_1C08_CKGEN00_REG_SW_EN_VIVA_DSP2DSP_230_2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C0C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_1C0C_CKGEN00_REG_SW_EN_VIVA_DSP2DSP_230_3 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C10_CKGEN00 (ckgen00 + 0x010)
    #define REG_1C10_CKGEN00_REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C14_CKGEN00 (ckgen00 + 0x014)
    #define REG_1C14_CKGEN00_REG_SW_EN_VIVA_DSP2DSP_230_TM Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C18_CKGEN00 (ckgen00 + 0x018)
    #define REG_1C18_CKGEN00_REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C1C_CKGEN00 (ckgen00 + 0x01C)
    #define REG_1C1C_CKGEN00_REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C20_CKGEN00 (ckgen00 + 0x020)
    #define REG_1C20_CKGEN00_REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C24_CKGEN00 (ckgen00 + 0x024)
    #define REG_1C24_CKGEN00_REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C28_CKGEN00 (ckgen00 + 0x028)
    #define REG_1C28_CKGEN00_REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C2C_CKGEN00 (ckgen00 + 0x02C)
    #define REG_1C2C_CKGEN00_REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C30_CKGEN00 (ckgen00 + 0x030)
    #define REG_1C30_CKGEN00_REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C34_CKGEN00 (ckgen00 + 0x034)
    #define REG_1C34_CKGEN00_REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C38_CKGEN00 (ckgen00 + 0x038)
    #define REG_1C38_CKGEN00_REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C3C_CKGEN00 (ckgen00 + 0x03C)
    #define REG_1C3C_CKGEN00_REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C40_CKGEN00 (ckgen00 + 0x040)
    #define REG_1C40_CKGEN00_REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C44_CKGEN00 (ckgen00 + 0x044)
    #define REG_1C44_CKGEN00_REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C48_CKGEN00 (ckgen00 + 0x048)
    #define REG_1C48_CKGEN00_REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C4C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_1C4C_CKGEN00_REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C50_CKGEN00 (ckgen00 + 0x050)
    #define REG_1C50_CKGEN00_REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C54_CKGEN00 (ckgen00 + 0x054)
    #define REG_1C54_CKGEN00_REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C58_CKGEN00 (ckgen00 + 0x058)
    #define REG_1C58_CKGEN00_REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C5C_CKGEN00 (ckgen00 + 0x05C)
    #define REG_1C5C_CKGEN00_REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C60_CKGEN00 (ckgen00 + 0x060)
    #define REG_1C60_CKGEN00_REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C64_CKGEN00 (ckgen00 + 0x064)
    #define REG_1C64_CKGEN00_REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C68_CKGEN00 (ckgen00 + 0x068)
    #define REG_1C68_CKGEN00_REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C6C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_1C6C_CKGEN00_REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C70_CKGEN00 (ckgen00 + 0x070)
    #define REG_1C70_CKGEN00_REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C74_CKGEN00 (ckgen00 + 0x074)
    #define REG_1C74_CKGEN00_REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C78_CKGEN00 (ckgen00 + 0x078)
    #define REG_1C78_CKGEN00_REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C7C_CKGEN00 (ckgen00 + 0x07C)
    #define REG_1C7C_CKGEN00_REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C80_CKGEN00 (ckgen00 + 0x080)
    #define REG_1C80_CKGEN00_REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C84_CKGEN00 (ckgen00 + 0x084)
    #define REG_1C84_CKGEN00_REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C88_CKGEN00 (ckgen00 + 0x088)
    #define REG_1C88_CKGEN00_REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C8C_CKGEN00 (ckgen00 + 0x08C)
    #define REG_1C8C_CKGEN00_REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C90_CKGEN00 (ckgen00 + 0x090)
    #define REG_1C90_CKGEN00_REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C94_CKGEN00 (ckgen00 + 0x094)
    #define REG_1C94_CKGEN00_REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C98_CKGEN00 (ckgen00 + 0x098)
    #define REG_1C98_CKGEN00_REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C9C_CKGEN00 (ckgen00 + 0x09C)
    #define REG_1C9C_CKGEN00_REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA0_CKGEN00 (ckgen00 + 0x0A0)
    #define REG_1CA0_CKGEN00_REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA4_CKGEN00 (ckgen00 + 0x0A4)
    #define REG_1CA4_CKGEN00_REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA8_CKGEN00 (ckgen00 + 0x0A8)
    #define REG_1CA8_CKGEN00_REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CAC_CKGEN00 (ckgen00 + 0x0AC)
    #define REG_1CAC_CKGEN00_REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB0_CKGEN00 (ckgen00 + 0x0B0)
    #define REG_1CB0_CKGEN00_REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB4_CKGEN00 (ckgen00 + 0x0B4)
    #define REG_1CB4_CKGEN00_REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB8_CKGEN00 (ckgen00 + 0x0B8)
    #define REG_1CB8_CKGEN00_REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CBC_CKGEN00 (ckgen00 + 0x0BC)
    #define REG_1CBC_CKGEN00_REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_1CC0_CKGEN00_REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC4_CKGEN00 (ckgen00 + 0x0C4)
    #define REG_1CC4_CKGEN00_REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_1CC8_CKGEN00_REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CCC_CKGEN00 (ckgen00 + 0x0CC)
    #define REG_1CCC_CKGEN00_REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_1CD0_CKGEN00_REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD4_CKGEN00 (ckgen00 + 0x0D4)
    #define REG_1CD4_CKGEN00_REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_1CD8_CKGEN00_REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CDC_CKGEN00 (ckgen00 + 0x0DC)
    #define REG_1CDC_CKGEN00_REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_1CE0_CKGEN00_REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE4_CKGEN00 (ckgen00 + 0x0E4)
    #define REG_1CE4_CKGEN00_REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_1CE8_CKGEN00_REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CEC_CKGEN00 (ckgen00 + 0x0EC)
    #define REG_1CEC_CKGEN00_REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF0_CKGEN00 (ckgen00 + 0x0F0)
    #define REG_1CF0_CKGEN00_REG_SW_EN_VIVA_R2_WB2R2_WB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF4_CKGEN00 (ckgen00 + 0x0F4)
    #define REG_1CF4_CKGEN00_REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_1CF8_CKGEN00_REG_SW_EN_VIVA_RIU_R22RIU_R2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CFC_CKGEN00 (ckgen00 + 0x0FC)
    #define REG_1CFC_CKGEN00_REG_SW_EN_VIVA_SH2CH1_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D00_CKGEN00 (ckgen00 + 0x100)
    #define REG_1D00_CKGEN00_REG_SW_EN_VIVA_SH2CH2_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D04_CKGEN00 (ckgen00 + 0x104)
    #define REG_1D04_CKGEN00_REG_SW_EN_VIVA_SH2CH3_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D08_CKGEN00 (ckgen00 + 0x108)
    #define REG_1D08_CKGEN00_REG_SW_EN_VIVA_SH2CH4_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D0C_CKGEN00 (ckgen00 + 0x10C)
    #define REG_1D0C_CKGEN00_REG_SW_EN_VIVA_SH2CH5_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D10_CKGEN00 (ckgen00 + 0x110)
    #define REG_1D10_CKGEN00_REG_SW_EN_VIVA_SH2CH6_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D14_CKGEN00 (ckgen00 + 0x114)
    #define REG_1D14_CKGEN00_REG_SW_EN_VIVA_SH2CH7_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D18_CKGEN00 (ckgen00 + 0x118)
    #define REG_1D18_CKGEN00_REG_SW_EN_VIVA_SH2CH8_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D1C_CKGEN00 (ckgen00 + 0x11C)
    #define REG_1D1C_CKGEN00_REG_SW_EN_VIVA_SH2CH9_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D20_CKGEN00 (ckgen00 + 0x120)
    #define REG_1D20_CKGEN00_REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D24_CKGEN00 (ckgen00 + 0x124)
    #define REG_1D24_CKGEN00_REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN00_8
#define REG_1D28_CKGEN00 (ckgen00 + 0x128)
    #define REG_1D28_CKGEN00_REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D2C_CKGEN00 (ckgen00 + 0x12C)
    #define REG_1D2C_CKGEN00_REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D30_CKGEN00 (ckgen00 + 0x130)
    #define REG_1D30_CKGEN00_REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D34_CKGEN00 (ckgen00 + 0x134)
    #define REG_1D34_CKGEN00_REG_SW_EN_VIVA_SIN_GEN2SIN_GEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D38_CKGEN00 (ckgen00 + 0x138)
    #define REG_1D38_CKGEN00_REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D3C_CKGEN00 (ckgen00 + 0x13C)
    #define REG_1D3C_CKGEN00_REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D40_CKGEN00 (ckgen00 + 0x140)
    #define REG_1D40_CKGEN00_REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D44_CKGEN00 (ckgen00 + 0x144)
    #define REG_1D44_CKGEN00_REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D48_CKGEN00 (ckgen00 + 0x148)
    #define REG_1D48_CKGEN00_REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D4C_CKGEN00 (ckgen00 + 0x14C)
    #define REG_1D4C_CKGEN00_REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D50_CKGEN00 (ckgen00 + 0x150)
    #define REG_1D50_CKGEN00_REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D54_CKGEN00 (ckgen00 + 0x154)
    #define REG_1D54_CKGEN00_REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D58_CKGEN00 (ckgen00 + 0x158)
    #define REG_1D58_CKGEN00_REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D5C_CKGEN00 (ckgen00 + 0x15C)
    #define REG_1D5C_CKGEN00_REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D60_CKGEN00 (ckgen00 + 0x160)
    #define REG_1D60_CKGEN00_REG_SW_EN_VIVA_TEST_BUS2TEST_BUS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D64_CKGEN00 (ckgen00 + 0x164)
    #define REG_1D64_CKGEN00_REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D68_CKGEN00 (ckgen00 + 0x168)
    #define REG_1D68_CKGEN00_REG_SW_EN_VIVA_XTAL_12M2XTAL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1D68_CKGEN00_REG_SW_EN_XTAL_12M2AUDIO_R2 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1D6C_CKGEN00 (ckgen00 + 0x16C)
    #define REG_1D6C_CKGEN00_REG_SW_EN_VIVA_XTAL_24M2XTAL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D70_CKGEN00 (ckgen00 + 0x170)
    #define REG_1D70_CKGEN00_REG_SW_EN_RV_TCK2RV55AUDIO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D74_CKGEN00 (ckgen00 + 0x174)
    #define REG_1D74_CKGEN00_REG_SW_EN_RV55AUDIO2RV55AUDIO Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1D74_CKGEN00_REG_SW_EN_RV55AUDIO2RV55DFS Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1D78_CKGEN00 (ckgen00 + 0x178)
    #define REG_1D78_CKGEN00_REG_SW_EN_MCU_WB2RV55AUDIO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D7C_CKGEN00 (ckgen00 + 0x17C)
    #define REG_1D7C_CKGEN00_REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D80_CKGEN00 (ckgen00 + 0x180)
    #define REG_1D80_CKGEN00_REG_SW_EN_MCU_WB2RV55FRC_1D80 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1D80_CKGEN00_REG_SW_EN_MCU_WB2RV55PQU_1D80 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_1D90_CKGEN00 (ckgen00 + 0x190)
    #define REG_1D90_CKGEN00_REG_SW_EN_GPD2GPD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D98_CKGEN00 (ckgen00 + 0x198)
    #define REG_1D98_CKGEN00_REG_SW_EN_NJPD2JPD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1DA0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_1DA0_CKGEN00_REG_SW_EN_VDEC_BUS2CORE0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DA0_CKGEN00_REG_SW_EN_VDEC_BUS2CORE1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1DA0_CKGEN00_REG_SW_EN_VDEC_BUS2CORE2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1DA0_CKGEN00_REG_SW_EN_GCE_F26M2GCE_BIU Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1DA4_CKGEN00 (ckgen00 + 0x1A4)
    #define REG_1DA4_CKGEN00_REG_SW_EN_VDEC_BUS2SOC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1DA8_CKGEN00 (ckgen00 + 0x1A8)
    #define REG_1DA8_CKGEN00_REG_SW_EN_VDEC_LAT02SOC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1DAC_CKGEN00 (ckgen00 + 0x1AC)
    #define REG_1DAC_CKGEN00_REG_SW_EN_VDEC_LAT12SOC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DAC_CKGEN00_REG_SW_EN_VDEC_SYS2CORE0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1DAC_CKGEN00_REG_SW_EN_VDEC_SYS2CORE1 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1DAC_CKGEN00_REG_SW_EN_VDEC_SYS2CORE2 Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1DB0_CKGEN00 (ckgen00 + 0x1B0)
    #define REG_1DB0_CKGEN00_REG_SW_EN_VDEC_SYS2SOC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DB0_CKGEN00_REG_SW_EN_XTAL_24M2CORE0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1DB0_CKGEN00_REG_SW_EN_XTAL_24M2CORE1 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1DB4_CKGEN00 (ckgen00 + 0x1B4)
    #define REG_1DB4_CKGEN00_REG_SW_EN_XTAL_24M2CORE2 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1E00_CKGEN00 (ckgen00 + 0x000)
    #define REG_1E00_CKGEN00_REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E04_CKGEN00 (ckgen00 + 0x004)
    #define REG_1E04_CKGEN00_REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E08_CKGEN00 (ckgen00 + 0x008)
    #define REG_1E08_CKGEN00_REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E0C_CKGEN00 (ckgen00 + 0x00C)
    #define REG_1E0C_CKGEN00_REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E10_CKGEN00 (ckgen00 + 0x010)
    #define REG_1E10_CKGEN00_REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E14_CKGEN00 (ckgen00 + 0x014)
    #define REG_1E14_CKGEN00_REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E18_CKGEN00 (ckgen00 + 0x018)
    #define REG_1E18_CKGEN00_REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E1C_CKGEN00 (ckgen00 + 0x01C)
    #define REG_1E1C_CKGEN00_REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E20_CKGEN00 (ckgen00 + 0x020)
    #define REG_1E20_CKGEN00_REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E24_CKGEN00 (ckgen00 + 0x024)
    #define REG_1E24_CKGEN00_REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E28_CKGEN00 (ckgen00 + 0x028)
    #define REG_1E28_CKGEN00_REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E2C_CKGEN00 (ckgen00 + 0x02C)
    #define REG_1E2C_CKGEN00_REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E30_CKGEN00 (ckgen00 + 0x030)
    #define REG_1E30_CKGEN00_REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E34_CKGEN00 (ckgen00 + 0x034)
    #define REG_1E34_CKGEN00_REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E38_CKGEN00 (ckgen00 + 0x038)
    #define REG_1E38_CKGEN00_REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E3C_CKGEN00 (ckgen00 + 0x03C)
    #define REG_1E3C_CKGEN00_REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E40_CKGEN00 (ckgen00 + 0x040)
    #define REG_1E40_CKGEN00_REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E44_CKGEN00 (ckgen00 + 0x044)
    #define REG_1E44_CKGEN00_REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E48_CKGEN00 (ckgen00 + 0x048)
    #define REG_1E48_CKGEN00_REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E4C_CKGEN00 (ckgen00 + 0x04C)
    #define REG_1E4C_CKGEN00_REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E50_CKGEN00 (ckgen00 + 0x050)
    #define REG_1E50_CKGEN00_REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E54_CKGEN00 (ckgen00 + 0x054)
    #define REG_1E54_CKGEN00_REG_SW_EN_VIVA_SH2CH10_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E58_CKGEN00 (ckgen00 + 0x058)
    #define REG_1E58_CKGEN00_REG_SW_EN_VIVA_SH2CH_M1_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E5C_CKGEN00 (ckgen00 + 0x05C)
    #define REG_1E5C_CKGEN00_REG_SW_EN_VIVA_SH2CH_M2_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E60_CKGEN00 (ckgen00 + 0x060)
    #define REG_1E60_CKGEN00_REG_SW_EN_VIVA_SH2CH_M3_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E64_CKGEN00 (ckgen00 + 0x064)
    #define REG_1E64_CKGEN00_REG_SW_EN_VIVA_SH2CH_M4_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E68_CKGEN00 (ckgen00 + 0x068)
    #define REG_1E68_CKGEN00_REG_SW_EN_VIVA_SH2CH_M5_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E6C_CKGEN00 (ckgen00 + 0x06C)
    #define REG_1E6C_CKGEN00_REG_SW_EN_VIVA_SH2CH_M6_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E70_CKGEN00 (ckgen00 + 0x070)
    #define REG_1E70_CKGEN00_REG_SW_EN_VIVA_SH2CH_M7_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E74_CKGEN00 (ckgen00 + 0x074)
    #define REG_1E74_CKGEN00_REG_SW_EN_VIVA_SH2CH_M8_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E78_CKGEN00 (ckgen00 + 0x078)
    #define REG_1E78_CKGEN00_REG_SW_EN_VIVA_SH2CH_M9_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E7C_CKGEN00 (ckgen00 + 0x07C)
    #define REG_1E7C_CKGEN00_REG_SW_EN_VIVA_SH2CH_M10_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E80_CKGEN00 (ckgen00 + 0x080)
    #define REG_1E80_CKGEN00_REG_SW_EN_VIVA_SH2CH_M11_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E84_CKGEN00 (ckgen00 + 0x084)
    #define REG_1E84_CKGEN00_REG_SW_EN_VIVA_SH2CH_M12_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E88_CKGEN00 (ckgen00 + 0x088)
    #define REG_1E88_CKGEN00_REG_SW_EN_VIVA_SH2CH_M13_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E8C_CKGEN00 (ckgen00 + 0x08C)
    #define REG_1E8C_CKGEN00_REG_SW_EN_VIVA_SH2CH_M14_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E90_CKGEN00 (ckgen00 + 0x090)
    #define REG_1E90_CKGEN00_REG_SW_EN_VIVA_SH2CH_M15_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E94_CKGEN00 (ckgen00 + 0x094)
    #define REG_1E94_CKGEN00_REG_SW_EN_VIVA_SH2CH_M16_SH Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E98_CKGEN00 (ckgen00 + 0x098)
    #define REG_1E98_CKGEN00_REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E9C_CKGEN00 (ckgen00 + 0x09C)
    #define REG_1E9C_CKGEN00_REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP_1E9C Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E9C_CKGEN00_REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK_1E9C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1EC0_CKGEN00 (ckgen00 + 0x0C0)
    #define REG_1EC0_CKGEN00_REG_PD_SYS3PLL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EC0_CKGEN00_REG_PD_SYS3PLL_CLK_DIV2P5 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1EC0_CKGEN00_REG_PD_SYS3PLL_CLK_DIV2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1EC0_CKGEN00_REG_PD_SYS3PLL_CLK_DIV3 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1EC4_CKGEN00 (ckgen00 + 0x0C4)
    #define REG_1EC4_CKGEN00_REG_PD_SYS3PLL_CLK_DIV5 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EC4_CKGEN00_REG_PD_SYS3PLL_POSTDIV Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1EC4_CKGEN00_REG_PD_SYS3PLL_CLK_DIV30 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1EC8_CKGEN00 (ckgen00 + 0x0C8)
    #define REG_1EC8_CKGEN00_REG_EN_SYS3PLL_VCO_DIV3 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EC8_CKGEN00_REG_EN_SYS3PLL_OCC_DIV128 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1EC8_CKGEN00_REG_EN_SYS3PLL_XTAL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1EC8_CKGEN00_REG_EN_SYS3PLL_TEST Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1ECC_CKGEN00 (ckgen00 + 0x0CC)
    #define REG_1ECC_CKGEN00_REG_EN_SYS3PLL_PRDT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1ECC_CKGEN00_REG_EN_SYS3PLL_RST Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1ED0_CKGEN00 (ckgen00 + 0x0D0)
    #define REG_1ED0_CKGEN00_REG_GC_SYS3PLL_INPUT_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1ED4_CKGEN00 (ckgen00 + 0x0D4)
    #define REG_1ED4_CKGEN00_REG_GC_SYS3PLL_CP_SW Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1ED4_CKGEN00_REG_GC_SYS3PLL_ICTRL Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1ED8_CKGEN00 (ckgen00 + 0x0D8)
    #define REG_1ED8_CKGEN00_REG_GC_SYS3PLL_OUTPUT_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1ED8_CKGEN00_REG_GC_SYS3PLL_OUTPUT_DIV Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1EDC_CKGEN00 (ckgen00 + 0x0DC)
    #define REG_1EDC_CKGEN00_REG_GC_SYS3PLL_LOOPDIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1EE0_CKGEN00 (ckgen00 + 0x0E0)
    #define REG_1EE0_CKGEN00_REG_GC_SYS3PLL_LOOPDIV_SECOND Fld(8,0,AC_FULLB0)//[7:0]
#define REG_1EE8_CKGEN00 (ckgen00 + 0x0E8)
    #define REG_1EE8_CKGEN00_REG_RO_SYS3PLL_LOCK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1EF8_CKGEN00 (ckgen00 + 0x0F8)
    #define REG_1EF8_CKGEN00_REG_TEST_SYS3PLL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F00_CKGEN00 (ckgen00 + 0x100)
    #define REG_1F00_CKGEN00_REG_PD_GPUBRDGPLL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F00_CKGEN00_REG_PD_GPUBRDGPLL_CLK_DIV2P5 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F00_CKGEN00_REG_PD_GPUBRDGPLL_CLK_DIV2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F00_CKGEN00_REG_PD_GPUBRDGPLL_CLK_DIV3 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1F04_CKGEN00 (ckgen00 + 0x104)
    #define REG_1F04_CKGEN00_REG_PD_GPUBRDGPLL_CLK_DIV5 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F04_CKGEN00_REG_PD_GPUBRDGPLL_POSTDIV Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F04_CKGEN00_REG_PD_GPUBRDGPLL_CLK_DIV30 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1F08_CKGEN00 (ckgen00 + 0x108)
    #define REG_1F08_CKGEN00_REG_EN_GPUBRDGPLL_VCO_DIV3 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F08_CKGEN00_REG_EN_GPUBRDGPLL_OCC_DIV128 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F08_CKGEN00_REG_EN_GPUBRDGPLL_XTAL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F08_CKGEN00_REG_EN_GPUBRDGPLL_TEST Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1F0C_CKGEN00 (ckgen00 + 0x10C)
    #define REG_1F0C_CKGEN00_REG_EN_GPUBRDGPLL_PRDT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F0C_CKGEN00_REG_EN_GPUBRDGPLL_RST Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1F10_CKGEN00 (ckgen00 + 0x110)
    #define REG_1F10_CKGEN00_REG_GC_GPUBRDGPLL_INPUT_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1F14_CKGEN00 (ckgen00 + 0x114)
    #define REG_1F14_CKGEN00_REG_GC_GPUBRDGPLL_CP_SW Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1F14_CKGEN00_REG_GC_GPUBRDGPLL_ICTRL Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1F18_CKGEN00 (ckgen00 + 0x118)
    #define REG_1F18_CKGEN00_REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1F18_CKGEN00_REG_GC_GPUBRDGPLL_OUTPUT_DIV Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1F1C_CKGEN00 (ckgen00 + 0x11C)
    #define REG_1F1C_CKGEN00_REG_GC_GPUBRDGPLL_LOOPDIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1F20_CKGEN00 (ckgen00 + 0x120)
    #define REG_1F20_CKGEN00_REG_GC_GPUBRDGPLL_LOOPDIV_SECOND Fld(8,0,AC_FULLB0)//[7:0]
#define REG_1F28_CKGEN00 (ckgen00 + 0x128)
    #define REG_1F28_CKGEN00_REG_RO_GPUBRDGPLL_LOCK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F38_CKGEN00 (ckgen00 + 0x138)
    #define REG_1F38_CKGEN00_REG_TEST_GPUBRDGPLL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F40_CKGEN00 (ckgen00 + 0x140)
    #define REG_1F40_CKGEN00_REG_PD_APUBUSPLL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F40_CKGEN00_REG_PD_APUBUSPLL_CLK_DIV2P5 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F40_CKGEN00_REG_PD_APUBUSPLL_CLK_DIV2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F40_CKGEN00_REG_PD_APUBUSPLL_CLK_DIV3 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1F44_CKGEN00 (ckgen00 + 0x144)
    #define REG_1F44_CKGEN00_REG_PD_APUBUSPLL_CLK_DIV5 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F44_CKGEN00_REG_PD_APUBUSPLL_POSTDIV Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F44_CKGEN00_REG_PD_APUBUSPLL_CLK_DIV30 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1F48_CKGEN00 (ckgen00 + 0x148)
    #define REG_1F48_CKGEN00_REG_EN_APUBUSPLL_VCO_DIV3 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F48_CKGEN00_REG_EN_APUBUSPLL_OCC_DIV128 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F48_CKGEN00_REG_EN_APUBUSPLL_XTAL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F48_CKGEN00_REG_EN_APUBUSPLL_TEST Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1F4C_CKGEN00 (ckgen00 + 0x14C)
    #define REG_1F4C_CKGEN00_REG_EN_APUBUSPLL_PRDT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F4C_CKGEN00_REG_EN_APUBUSPLL_RST Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1F50_CKGEN00 (ckgen00 + 0x150)
    #define REG_1F50_CKGEN00_REG_GC_APUBUSPLL_INPUT_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1F54_CKGEN00 (ckgen00 + 0x154)
    #define REG_1F54_CKGEN00_REG_GC_APUBUSPLL_CP_SW Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1F54_CKGEN00_REG_GC_APUBUSPLL_ICTRL Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1F58_CKGEN00 (ckgen00 + 0x158)
    #define REG_1F58_CKGEN00_REG_GC_APUBUSPLL_OUTPUT_DIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1F58_CKGEN00_REG_GC_APUBUSPLL_OUTPUT_DIV Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1F5C_CKGEN00 (ckgen00 + 0x15C)
    #define REG_1F5C_CKGEN00_REG_GC_APUBUSPLL_LOOPDIV_FIRST Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1F60_CKGEN00 (ckgen00 + 0x160)
    #define REG_1F60_CKGEN00_REG_GC_APUBUSPLL_LOOPDIV_SECOND Fld(8,0,AC_FULLB0)//[7:0]
#define REG_1F68_CKGEN00 (ckgen00 + 0x168)
    #define REG_1F68_CKGEN00_REG_RO_APUBUSPLL_LOCK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F78_CKGEN00 (ckgen00 + 0x178)
    #define REG_1F78_CKGEN00_REG_TEST_APUBUSPLL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F80_CKGEN00 (ckgen00 + 0x180)
    #define REG_1F80_CKGEN00_REG_CKG_DVBTM_TS_DIVNUM Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_1F80_CKGEN00_REG_CKG_ATSC_DVB_DIV_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_1F80_CKGEN00_REG_CKG_ATSC_DVBTC_TS_INV Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F80_CKGEN00_REG_CKG_DVBTM_TS_OUT_MODE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F80_CKGEN00_REG_CKG_DEMOD_TEST_IN_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F80_CKGEN00_REG_CKG_TSOUT_PH_TUN_EN Fld(1,14,AC_MSKB1)//[14:14]
#define REG_1F84_CKGEN00 (ckgen00 + 0x184)
    #define REG_1F84_CKGEN00_REG_ATSC_DVB_DIV_RESET Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F88_CKGEN00 (ckgen00 + 0x188)
    #define REG_1F88_CKGEN00_REG_CKG_ATSC_TS Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1F8C_CKGEN00 (ckgen00 + 0x18C)
    #define REG_1F8C_CKGEN00_REG_CKG_DVBTC_TS_TOP Fld(4,8,AC_MSKB1)//[11:8]
#define REG_1F90_CKGEN00 (ckgen00 + 0x190)
    #define REG_1F90_CKGEN00_REG_CKG_TSOUT_PH_TUN_NUM Fld(5,8,AC_MSKB1)//[12:8]
#define REG_1F94_CKGEN00 (ckgen00 + 0x194)
    #define REG_1F94_CKGEN00_REG_CKG_VIFDBB_DAC_TOP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1F98_CKGEN00 (ckgen00 + 0x198)
    #define REG_1F98_CKGEN00_REG_CKG_DACA2 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1F98_CKGEN00_REG_CKG_DACB2 Fld(4,8,AC_MSKB1)//[11:8]
#define REG_1FA0_CKGEN00 (ckgen00 + 0x1A0)
    #define REG_1FA0_CKGEN00_REG_CKG_VD_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1FA0_CKGEN00_REG_CKG_VD_BUF_SEL Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1FF0_CKGEN00 (ckgen00 + 0x1F0)
    #define REG_1FF0_CKGEN00_REG_CKGEN00_DUMMY0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF4_CKGEN00 (ckgen00 + 0x1F4)
    #define REG_1FF4_CKGEN00_REG_CKGEN00_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF8_CKGEN00 (ckgen00 + 0x1F8)
    #define REG_1FF8_CKGEN00_REG_CKGEN00_DUMMY2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FFC_CKGEN00 (ckgen00 + 0x1FC)
    #define REG_1FFC_CKGEN00_REG_CKGEN00_DUMMY3 Fld(16,0,AC_FULLW10)//[15:0]

#endif