/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
 * Copyright (c) 2023 MediaTek Inc.
 */

#define GOPC_BKA4D3 0x0149A600

//Page GOPC_BKA4D3
#define REG_0004_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x004)
    #define REG_0004_GOPC_BKA4D3_REG_GOP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_GOPC_BKA4D3_REG_MIRROR_V Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0004_GOPC_BKA4D3_REG_DATA_FMT Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0004_GOPC_BKA4D3_REG_UV_SWAP Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0004_GOPC_BKA4D3_REG_YC_SWAP Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0004_GOPC_BKA4D3_REG_AD_SWAP Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0004_GOPC_BKA4D3_REG_422TO444_MD Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0004_GOPC_BKA4D3_REG_PIX_ALPHA_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0004_GOPC_BKA4D3_REG_ALPHA_INV Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x008)
    #define REG_0008_GOPC_BKA4D3_REG_DRAM_BASE_STR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x00C)
    #define REG_000C_GOPC_BKA4D3_REG_DRAM_BASE_STR_1 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0010_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x010)
    #define REG_0010_GOPC_BKA4D3_REG_PIC_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0014_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x014)
    #define REG_0014_GOPC_BKA4D3_REG_PIC_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0018_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x018)
    #define REG_0018_GOPC_BKA4D3_REG_PIC_X_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_001C_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x01C)
    #define REG_001C_GOPC_BKA4D3_REG_PIC_Y_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0020_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x020)
    #define REG_0020_GOPC_BKA4D3_REG_DISP_HSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0024_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x024)
    #define REG_0024_GOPC_BKA4D3_REG_DISP_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0028_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x028)
    #define REG_0028_GOPC_BKA4D3_REG_DISP_HSTR Fld(13,0,AC_MSKW10)//[12:0]
#define REG_002C_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x02C)
    #define REG_002C_GOPC_BKA4D3_REG_DISP_VSTR Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0030_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x030)
    #define REG_0030_GOPC_BKA4D3_REG_ALPHA_DEF0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0030_GOPC_BKA4D3_REG_ALPHA_DEF1 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0034_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x034)
    #define REG_0034_GOPC_BKA4D3_REG_ALPHA_DEF2 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0034_GOPC_BKA4D3_REG_ALPHA_DEF3 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0038_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x038)
    #define REG_0038_GOPC_BKA4D3_REG_SCROLL_H_LEN Fld(14,0,AC_MSKW10)//[13:0]
#define REG_003C_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x03C)
    #define REG_003C_GOPC_BKA4D3_REG_SCROLL_H_STOP_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0040_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x040)
    #define REG_0040_GOPC_BKA4D3_REG_SCROLL_V_LEN Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0044_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x044)
    #define REG_0044_GOPC_BKA4D3_REG_SCROLL_V_STOP_POS Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0048_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x048)
    #define REG_0048_GOPC_BKA4D3_REG_SCROLL_RATE Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0048_GOPC_BKA4D3_REG_SCROLL_H_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0048_GOPC_BKA4D3_REG_SCROLL_V_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0048_GOPC_BKA4D3_REG_SCROLL_H_STOP_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0048_GOPC_BKA4D3_REG_SCROLL_V_STOP_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0048_GOPC_BKA4D3_REG_PRE_ALPHA_MD Fld(1,12,AC_MSKB1)//[12:12]
#define REG_004C_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x04C)
    #define REG_004C_GOPC_BKA4D3_REG_TRANS_CLR_KEY_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x050)
    #define REG_0050_GOPC_BKA4D3_REG_TRANS_CLR_KEY_1 Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_0050_GOPC_BKA4D3_REG_TRANS_CLR_GRAY_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0050_GOPC_BKA4D3_REG_TRANS_CLR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0054_GOPC_BKA4D3 (GOPC_BKA4D3 + 0x054)
    #define REG_0054_GOPC_BKA4D3_REG_TSTPAT_PARA_X Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0054_GOPC_BKA4D3_REG_TSTPAT_PARA_Y Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0054_GOPC_BKA4D3_REG_TSTPAT_PARA_X_DUP Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0054_GOPC_BKA4D3_REG_TSTPAT_PARA_Y_DUP Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0054_GOPC_BKA4D3_REG_TSTPAT_STG_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0054_GOPC_BKA4D3_REG_TSTPAT_TGEN_EN Fld(1,15,AC_MSKB1)//[15:15]

