#ifndef _DEMURA_BKA377_V004_H
#define _DEMURA_BKA377_V004_H
#define DEMURA_BKA377_V004 0x146EE00

//Page DEMURA_BKA377_V004
#define REG_0004_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x004)
	#define REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004 Fld(7,0,AC_MSKB0)//[6:0]
	#define REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEG_0004 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0008_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x008)
	#define REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_000C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x00C)
	#define REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0010_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x010)
	#define REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0014_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x014)
	#define REG_0014_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_RD_R_DATA_0014 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0018_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x018)
	#define REG_0018_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_RD_G_DATA_0018 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_001C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x01C)
	#define REG_001C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_RD_B_DATA_001C Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0020_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x020)
	#define REG_0020_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_BIST_FAIL_E_0020 Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_0020_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_BIST_FAIL_LB_0020 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0024_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x024)
	#define REG_0024_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_BIST_FAIL_O_0024 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0030_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x030)
	#define REG_0030_DEMURA_BKA377_V004_REG_PCID_LUT_ADL_DEPTH_0030 Fld(10,0,AC_MSKW10)//[9:0]
	#define REG_0030_DEMURA_BKA377_V004_REG_PCID_LUT_ADL_1DRV3_0030 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0034_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x034)
	#define REG_0034_DEMURA_BKA377_V004_REG_PCID_DUMMY1_0034 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0038_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x038)
	#define REG_0038_DEMURA_BKA377_V004_REG_PCID_DUMMY2_0038 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_003C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x03C)
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_DITHER_EN_003C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_CH_SEL_003C Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_MODE_003C Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_BYPASS_003C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_TOGGLE_003C Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEL_003C Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_EO_SEL_003C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_HW_DL_CLR_003C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_W0_003C Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_RD_003C Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0040_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x040)
	#define REG_0040_DEMURA_BKA377_V004_REG_DMC_BLACK_LIMIT_0040 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0044_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x044)
	#define REG_0044_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL1_0044 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0048_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x048)
	#define REG_0048_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL2_0048 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_004C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x04C)
	#define REG_004C_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL3_004C Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0050_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x050)
	#define REG_0050_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL4_0050 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0054_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x054)
	#define REG_0054_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL5_0054 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0058_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x058)
	#define REG_0058_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL6_0058 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_005C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x05C)
	#define REG_005C_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL7_005C Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0060_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x060)
	#define REG_0060_DEMURA_BKA377_V004_REG_DMC_PLANE_LEVEL8_0060 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0064_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x064)
	#define REG_0064_DEMURA_BKA377_V004_REG_DMC_WHITE_LIMIT_0064 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0068_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x068)
	#define REG_0068_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG1_0068 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0068_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG2_0068 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0068_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG3_0068 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0068_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG4_0068 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_006C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x06C)
	#define REG_006C_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG5_006C Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_006C_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG6_006C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_006C_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG7_006C Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_006C_DEMURA_BKA377_V004_REG_DMC_DATA_R_MAG8_006C Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0070_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x070)
	#define REG_0070_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG1_0070 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0070_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG2_0070 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0070_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG3_0070 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0070_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG4_0070 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0074_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x074)
	#define REG_0074_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG5_0074 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0074_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG6_0074 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0074_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG7_0074 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0074_DEMURA_BKA377_V004_REG_DMC_DATA_G_MAG8_0074 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0078_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x078)
	#define REG_0078_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG1_0078 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0078_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG2_0078 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0078_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG3_0078 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0078_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG4_0078 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_007C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x07C)
	#define REG_007C_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG5_007C Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_007C_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG6_007C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_007C_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG7_007C Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_007C_DEMURA_BKA377_V004_REG_DMC_DATA_B_MAG8_007C Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0080_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x080)
	#define REG_0080_DEMURA_BKA377_V004_REG_DMC_PLANE_B1_COEF_0080 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0084_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x084)
	#define REG_0084_DEMURA_BKA377_V004_REG_DMC_PLANE_12_COEF_0084 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0088_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x088)
	#define REG_0088_DEMURA_BKA377_V004_REG_DMC_PLANE_23_COEF_0088 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_008C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x08C)
	#define REG_008C_DEMURA_BKA377_V004_REG_DMC_PLANE_34_COEF_008C Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0090_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x090)
	#define REG_0090_DEMURA_BKA377_V004_REG_DMC_PLANE_45_COEF_0090 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0094_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x094)
	#define REG_0094_DEMURA_BKA377_V004_REG_DMC_PLANE_56_COEF_0094 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0098_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x098)
	#define REG_0098_DEMURA_BKA377_V004_REG_DMC_PLANE_67_COEF_0098 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_009C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x09C)
	#define REG_009C_DEMURA_BKA377_V004_REG_DMC_PLANE_78_COEF_009C Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A0_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0A0)
	#define REG_00A0_DEMURA_BKA377_V004_REG_DMC_PLANE_8W_COEF_00A0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A4_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0A4)
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_B1_KS22_00A4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_12_KS22_00A4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_23_KS22_00A4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_34_KS22_00A4 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_45_KS22_00A4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_56_KS22_00A4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_67_KS22_00A4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_78_KS22_00A4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_00A4_DEMURA_BKA377_V004_REG_DMC_PLANE_8W_KS22_00A4 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_00A8_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0A8)
	#define REG_00A8_DEMURA_BKA377_V004_REG_DMC_PLANE_NUM_00A8 Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_00A8_DEMURA_BKA377_V004_REG_DMC_BLOCK_SIZE_00A8 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_00A8_DEMURA_BKA377_V004_REG_DMC_RGB_MODE_00A8 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_00A8_DEMURA_BKA377_V004_REG_DMC_V_BLOCK_00A8 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_00A8_DEMURA_BKA377_V004_REG_DMC_H_BLOCK_00A8 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_00AC_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0AC)
	#define REG_00AC_DEMURA_BKA377_V004_REG_DMC_H_LUT_NUM_00AC Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B0_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0B0)
	#define REG_00B0_DEMURA_BKA377_V004_REG_DMC_V_LUT_NUM_00B0 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B4_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0B4)
	#define REG_00B4_DEMURA_BKA377_V004_REG_DMC_DUMMY1_00B4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B8_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0B8)
	#define REG_00B8_DEMURA_BKA377_V004_REG_DMC_DUMMY2_00B8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0BC)
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_B_EN_00BC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_G_EN_00BC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_R_EN_00BC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_FMT_CONVERT_EN_00BC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_DITHER_EN_00BC Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_BYPASS_00BC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_BW_STATUS_00BC Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_BW_STATUS_EN_00BC Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_DITHER_PSE_RST_NUM_00BC Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_00BC_DEMURA_BKA377_V004_REG_DMC_DITHER_RST_E_4_FRAME_00BC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C0_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0C0)
	#define REG_00C0_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET1_00C0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00C4_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0C4)
	#define REG_00C4_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET2_00C4 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00C8_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0C8)
	#define REG_00C8_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET3_00C8 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00CC_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0CC)
	#define REG_00CC_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET4_00CC Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00D0_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0D0)
	#define REG_00D0_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET5_00D0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00D4_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0D4)
	#define REG_00D4_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET6_00D4 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00D8_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0D8)
	#define REG_00D8_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET7_00D8 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00DC_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0DC)
	#define REG_00DC_DEMURA_BKA377_V004_REG_DMC_DATA_R_OFFSET8_00DC Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00E0_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0E0)
	#define REG_00E0_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET1_00E0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00E4_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0E4)
	#define REG_00E4_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET2_00E4 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00E8_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0E8)
	#define REG_00E8_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET3_00E8 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00EC_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0EC)
	#define REG_00EC_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET4_00EC Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00F0_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0F0)
	#define REG_00F0_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET5_00F0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00F4_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0F4)
	#define REG_00F4_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET6_00F4 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00F8_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0F8)
	#define REG_00F8_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET7_00F8 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00FC_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x0FC)
	#define REG_00FC_DEMURA_BKA377_V004_REG_DMC_DATA_G_OFFSET8_00FC Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0100_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x100)
	#define REG_0100_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET1_0100 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0104_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x104)
	#define REG_0104_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET2_0104 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0108_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x108)
	#define REG_0108_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET3_0108 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_010C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x10C)
	#define REG_010C_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET4_010C Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0110_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x110)
	#define REG_0110_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET5_0110 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0114_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x114)
	#define REG_0114_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET6_0114 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0118_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x118)
	#define REG_0118_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET7_0118 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_011C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x11C)
	#define REG_011C_DEMURA_BKA377_V004_REG_DMC_DATA_B_OFFSET8_011C Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0120_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x120)
	#define REG_0120_DEMURA_BKA377_V004_REG_DMC_PANEL_H_SIZE_0120 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0124_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x124)
	#define REG_0124_DEMURA_BKA377_V004_REG_DMC_PRELOAD_LINE_0124 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0128_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x128)
	#define REG_0128_DEMURA_BKA377_V004_REG_DMC_MONO_MODE_Q_H_R_0128 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0128_DEMURA_BKA377_V004_REG_DMC_MONO_MODE_R_H_R_0128 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_012C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x12C)
	#define REG_012C_DEMURA_BKA377_V004_REG_DMC_GRID_LINE_COLOR_012C Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_012C_DEMURA_BKA377_V004_REG_DMC_GRID_LINE_SIZE_012C Fld(3,12,AC_MSKB1)//[14:12]
	#define REG_012C_DEMURA_BKA377_V004_REG_DMC_GRID_LINE_EN_012C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0130_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x130)
	#define REG_0130_DEMURA_BKA377_V004_REG_DMC_FLOW_LEN_0130 Fld(11,0,AC_MSKW10)//[10:0]
	#define REG_0130_DEMURA_BKA377_V004_REG_DMC_FLOW_CTRL_EN_0130 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0138_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x138)
	#define REG_0138_DEMURA_BKA377_V004_REG_DMC_BIST_FAIL_FMT_0138 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0138_DEMURA_BKA377_V004_REG_DMC_BIST_FAIL_0138 Fld(6,10,AC_MSKB1)//[15:10]
#define REG_013C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x13C)
	#define REG_013C_DEMURA_BKA377_V004_REG_DMC_FMTCV_GROUP_NUM_013C Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_013C_DEMURA_BKA377_V004_REG_DMC_FMTCV_FLOW_PERIOD_013C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0140_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x140)
	#define REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_EN_0140 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_RB_SWAP_EN_0140 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_XTR_EN_0140 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_PANEL_TYPE_SEL_0140 Fld(3,5,AC_MSKB0)//[7:5]
	#define REG_0140_DEMURA_BKA377_V004_REG_PCID_HW_CFG_0140 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0144_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x144)
	#define REG_0144_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT0_0144 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_0144_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT1_0144 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0148_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x148)
	#define REG_0148_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT2_0148 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_0148_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT3_0148 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_014C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x14C)
	#define REG_014C_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT4_014C Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_014C_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT5_014C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0150_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x150)
	#define REG_0150_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT6_0150 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_0150_DEMURA_BKA377_V004_REG_PCID_PIXELOD_POLARITY_LUT7_0150 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0154_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x154)
	#define REG_0154_DEMURA_BKA377_V004_REG_PCID_PIXELOD_XTR_THRD_0_0154 Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0158_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x158)
	#define REG_0158_DEMURA_BKA377_V004_REG_PCID_PIXELOD_XTR_THRD_1_0158 Fld(10,0,AC_MSKW10)//[9:0]
#define REG_015C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x15C)
	#define REG_015C_DEMURA_BKA377_V004_REG_PCID_PIXELOD_XTR_THRD_WHITE_015C Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0160_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x160)
	#define REG_0160_DEMURA_BKA377_V004_REG_PCID_PIXELOD_XTR_THRD_BLACK_0160 Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0174_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x174)
	#define REG_0174_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_BDRY_MASK_L_0174 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0178_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x178)
	#define REG_0178_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_BDRY_MASK_R_0178 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_017C_DEMURA_BKA377_V004 (DEMURA_BKA377_V004 + 0x17C)
	#define REG_017C_DEMURA_BKA377_V004_REG_PCID_LINEOD_VOFFSET_017C Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_017C_DEMURA_BKA377_V004_REG_PCID_LINEOD_DUMMY_LINE_NUM_017C Fld(4,12,AC_MSKB1)//[15:12]
#endif