#define OLED_TOP_BKA3AF 0x01475E00

//Page OLED_TOP_BKA3AF
#define REG_007C_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x07C)
    #define REG_007C_OLED_TOP_BKA3AF_REG_REPORT_DBG_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A0_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x0A0)
    #define REG_00A0_OLED_TOP_BKA3AF_REG_OLED_VCLK_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00A0_OLED_TOP_BKA3AF_REG_OLED_ACLK_SW_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00A0_OLED_TOP_BKA3AF_REG_OLED_HCLK_SW_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00A0_OLED_TOP_BKA3AF_REG_OLED_AHB_WP_SW_RST Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00A0_OLED_TOP_BKA3AF_REG_OLED_AHB_ALL_SW_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00A0_OLED_TOP_BKA3AF_REG_OLED_ALL_SW_RST Fld(1,7,AC_MSKB0)//[7:7]
#define REG_0100_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x100)
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_CORE_BYPASS Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_BYPASS_ALL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_VCLK_FORCE_OFF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_ACLK_FORCE_OFF Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_HCLK_FORCE_OFF Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_VCLK_FORCE_ON Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_ACLK_FORCE_ON Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0100_OLED_TOP_BKA3AF_REG_OLED_HCLK_FORCE_ON Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0120_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x120)
    #define REG_0120_OLED_TOP_BKA3AF_REG_OLED_OMETA_TRIG_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0124_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x124)
    #define REG_0124_OLED_TOP_BKA3AF_REG_OLED_OMETA_DATA_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0128_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x128)
    #define REG_0128_OLED_TOP_BKA3AF_REG_OLED_FID_USER_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0128_OLED_TOP_BKA3AF_REG_OLED_FID_USER_VALUE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0128_OLED_TOP_BKA3AF_REG_OLED_FID_VS_DB_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_012C_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x12C)
    #define REG_012C_OLED_TOP_BKA3AF_REG_OLED_OSD_ALPHA_INV Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0130_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x130)
    #define REG_0130_OLED_TOP_BKA3AF_REG_REPORT_INPUT_HCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0134_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x134)
    #define REG_0134_OLED_TOP_BKA3AF_REG_REPORT_INPUT_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0138_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x138)
    #define REG_0138_OLED_TOP_BKA3AF_REG_REPORT_OUTPUT_HCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_013C_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x13C)
    #define REG_013C_OLED_TOP_BKA3AF_REG_REPORT_OUTPUT_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0140_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x140)
    #define REG_0140_OLED_TOP_BKA3AF_REG_IP_PAT0_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0140_OLED_TOP_BKA3AF_REG_IP_PAT0_SEL_Y Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0140_OLED_TOP_BKA3AF_REG_IP_PAT0_SEL_U Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0140_OLED_TOP_BKA3AF_REG_IP_PAT0_SEL_V Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0144_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x144)
    #define REG_0144_OLED_TOP_BKA3AF_REG_IP_PAT0_VALUE_Y Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0148_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x148)
    #define REG_0148_OLED_TOP_BKA3AF_REG_IP_PAT0_VALUE_U Fld(10,0,AC_MSKW10)//[9:0]
#define REG_014C_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x14C)
    #define REG_014C_OLED_TOP_BKA3AF_REG_IP_PAT0_VALUE_V Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0150_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x150)
    #define REG_0150_OLED_TOP_BKA3AF_REG_IP_PAT1_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0150_OLED_TOP_BKA3AF_REG_IP_PAT1_SEL_Y Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0150_OLED_TOP_BKA3AF_REG_IP_PAT1_SEL_U Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0150_OLED_TOP_BKA3AF_REG_IP_PAT1_SEL_V Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0154_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x154)
    #define REG_0154_OLED_TOP_BKA3AF_REG_IP_PAT1_VALUE_Y Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0158_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x158)
    #define REG_0158_OLED_TOP_BKA3AF_REG_IP_PAT1_VALUE_U Fld(10,0,AC_MSKW10)//[9:0]
#define REG_015C_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x15C)
    #define REG_015C_OLED_TOP_BKA3AF_REG_IP_PAT1_VALUE_V Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0160_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x160)
    #define REG_0160_OLED_TOP_BKA3AF_REG_IP_PAT_HSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0180_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x180)
    #define REG_0180_OLED_TOP_BKA3AF_REG_AHB_CRC_EN_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0180_OLED_TOP_BKA3AF_REG_AHB_CRC_AUTO_MODE_0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0180_OLED_TOP_BKA3AF_REG_AHB_CRC_CLR_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0180_OLED_TOP_BKA3AF_REG_AHB_CRC_DONE_0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x184)
    #define REG_0184_OLED_TOP_BKA3AF_REG_AHB_CRC_ST_TRIG_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0184_OLED_TOP_BKA3AF_REG_AHB_CRC_END_TRIG_0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0188_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x188)
    #define REG_0188_OLED_TOP_BKA3AF_REG_AHB_CRC_OUT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x190)
    #define REG_0190_OLED_TOP_BKA3AF_REG_AHB_CRC_ST_ADDR_0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x194)
    #define REG_0194_OLED_TOP_BKA3AF_REG_AHB_CRC_ST_ADDR_0_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0198_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x198)
    #define REG_0198_OLED_TOP_BKA3AF_REG_AHB_CRC_END_ADDR_0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x19C)
    #define REG_019C_OLED_TOP_BKA3AF_REG_AHB_CRC_END_ADDR_0_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C0_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1C0)
    #define REG_01C0_OLED_TOP_BKA3AF_REG_AHB_DEBUG_CLR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01C0_OLED_TOP_BKA3AF_REG_AHB_DEBUG_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01C0_OLED_TOP_BKA3AF_REG_AHB_DEBUG_CNT_LIVE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01C0_OLED_TOP_BKA3AF_REG_AHB_DEBUG_SEL0 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_01C4_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1C4)
    #define REG_01C4_OLED_TOP_BKA3AF_REG_AHB_DEBUG_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1C8)
    #define REG_01C8_OLED_TOP_BKA3AF_REG_REPORT_AHB_ADDR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1CC)
    #define REG_01CC_OLED_TOP_BKA3AF_REG_REPORT_AHB_ADDR_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D0_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1D0)
    #define REG_01D0_OLED_TOP_BKA3AF_REG_REPORT_AHB_WDATA_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1D4)
    #define REG_01D4_OLED_TOP_BKA3AF_REG_REPORT_AHB_WDATA_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D8_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1D8)
    #define REG_01D8_OLED_TOP_BKA3AF_REG_REPORT_AHB_CNT0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F8_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1F8)
    #define REG_01F8_OLED_TOP_BKA3AF_REG_IP_INT2_TARGET_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_OLED_TOP_BKA3AF (OLED_TOP_BKA3AF + 0x1FC)
    #define REG_01FC_OLED_TOP_BKA3AF_REG_IP_INT2_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01FC_OLED_TOP_BKA3AF_REG_OLED_IOMMU_MSB Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01FC_OLED_TOP_BKA3AF_REG_OLED_IVS_SELECT Fld(1,12,AC_MSKB1)//[12:12]

