#define PAFRC_BKA324 0x01464800

//Page PAFRC_BKA324_1
#define REG_0004_PAFRC_BKA324 (PAFRC_BKA324 + 0x004)
    #define REG_0004_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF16 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0004_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF16 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0008_PAFRC_BKA324 (PAFRC_BKA324 + 0x008)
    #define REG_0008_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF16 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0008_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF16 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_000C_PAFRC_BKA324 (PAFRC_BKA324 + 0x00C)
    #define REG_000C_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF16 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_000C_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF16 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0010_PAFRC_BKA324 (PAFRC_BKA324 + 0x010)
    #define REG_0010_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0010_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0020_PAFRC_BKA324 (PAFRC_BKA324 + 0x020)
    #define REG_0020_PAFRC_BKA324_REG_VAC_POLARITY_LUT0 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0024_PAFRC_BKA324 (PAFRC_BKA324 + 0x024)
    #define REG_0024_PAFRC_BKA324_REG_VAC_POLARITY_LUT1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0028_PAFRC_BKA324 (PAFRC_BKA324 + 0x028)
    #define REG_0028_PAFRC_BKA324_REG_VAC_POLARITY_LUT2 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_002C_PAFRC_BKA324 (PAFRC_BKA324 + 0x02C)
    #define REG_002C_PAFRC_BKA324_REG_VAC_POLARITY_LUT3 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_003C_PAFRC_BKA324 (PAFRC_BKA324 + 0x03C)
    #define REG_003C_PAFRC_BKA324_REG_PANEL_GAMMA_ADVAC_BLD_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_003C_PAFRC_BKA324_REG_PANEL_GAMMA_ADVAC_BLD_DITHER_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_003C_PAFRC_BKA324_REG_PANEL_GAMMA_IN_RBSWAP_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_003C_PAFRC_BKA324_REG_PANEL_GAMMA_OUT_RBSWAP_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_003C_PAFRC_BKA324_REG_VAC_ADVAC_BLD_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_003C_PAFRC_BKA324_REG_VAC_ADVAC_BLD_DITHER_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_003C_PAFRC_BKA324_REG_VAC_IN_RBSWAP_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_003C_PAFRC_BKA324_REG_VAC_OUT_RBSWAP_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_003C_PAFRC_BKA324_REG_VAC_BF_PANEL_GAMMA_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_003C_PAFRC_BKA324_REG_VAC_CURVE_FIT_MAX_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_003C_PAFRC_BKA324_REG_VAC_CURVE_FIT_DITHER_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_003C_PAFRC_BKA324_REG_VAC_CURVE_FIT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0040_PAFRC_BKA324 (PAFRC_BKA324 + 0x040)
    #define REG_0040_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0040_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0044_PAFRC_BKA324 (PAFRC_BKA324 + 0x044)
    #define REG_0044_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0044_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0048_PAFRC_BKA324 (PAFRC_BKA324 + 0x048)
    #define REG_0048_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0048_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_004C_PAFRC_BKA324 (PAFRC_BKA324 + 0x04C)
    #define REG_004C_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_004C_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0050_PAFRC_BKA324 (PAFRC_BKA324 + 0x050)
    #define REG_0050_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0050_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0054_PAFRC_BKA324 (PAFRC_BKA324 + 0x054)
    #define REG_0054_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0054_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0058_PAFRC_BKA324 (PAFRC_BKA324 + 0x058)
    #define REG_0058_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0058_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_005C_PAFRC_BKA324 (PAFRC_BKA324 + 0x05C)
    #define REG_005C_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_005C_PAFRC_BKA324_REG_VAC_RLUT0_LVL_COEF15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0060_PAFRC_BKA324 (PAFRC_BKA324 + 0x060)
    #define REG_0060_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0060_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0064_PAFRC_BKA324 (PAFRC_BKA324 + 0x064)
    #define REG_0064_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0064_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0068_PAFRC_BKA324 (PAFRC_BKA324 + 0x068)
    #define REG_0068_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0068_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_006C_PAFRC_BKA324 (PAFRC_BKA324 + 0x06C)
    #define REG_006C_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_006C_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0070_PAFRC_BKA324 (PAFRC_BKA324 + 0x070)
    #define REG_0070_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0070_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0074_PAFRC_BKA324 (PAFRC_BKA324 + 0x074)
    #define REG_0074_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0074_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0078_PAFRC_BKA324 (PAFRC_BKA324 + 0x078)
    #define REG_0078_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0078_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_007C_PAFRC_BKA324 (PAFRC_BKA324 + 0x07C)
    #define REG_007C_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_007C_PAFRC_BKA324_REG_VAC_RLUT1_LVL_COEF15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0080_PAFRC_BKA324 (PAFRC_BKA324 + 0x080)
    #define REG_0080_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0080_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0084_PAFRC_BKA324 (PAFRC_BKA324 + 0x084)
    #define REG_0084_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0084_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0088_PAFRC_BKA324 (PAFRC_BKA324 + 0x088)
    #define REG_0088_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0088_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_008C_PAFRC_BKA324 (PAFRC_BKA324 + 0x08C)
    #define REG_008C_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_008C_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0090_PAFRC_BKA324 (PAFRC_BKA324 + 0x090)
    #define REG_0090_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0090_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0094_PAFRC_BKA324 (PAFRC_BKA324 + 0x094)
    #define REG_0094_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0094_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0098_PAFRC_BKA324 (PAFRC_BKA324 + 0x098)
    #define REG_0098_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0098_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_009C_PAFRC_BKA324 (PAFRC_BKA324 + 0x09C)
    #define REG_009C_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_009C_PAFRC_BKA324_REG_VAC_GLUT0_LVL_COEF15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00A0_PAFRC_BKA324 (PAFRC_BKA324 + 0x0A0)
    #define REG_00A0_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00A0_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00A4_PAFRC_BKA324 (PAFRC_BKA324 + 0x0A4)
    #define REG_00A4_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00A4_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00A8_PAFRC_BKA324 (PAFRC_BKA324 + 0x0A8)
    #define REG_00A8_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00A8_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00AC_PAFRC_BKA324 (PAFRC_BKA324 + 0x0AC)
    #define REG_00AC_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00AC_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B0_PAFRC_BKA324 (PAFRC_BKA324 + 0x0B0)
    #define REG_00B0_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B0_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B4_PAFRC_BKA324 (PAFRC_BKA324 + 0x0B4)
    #define REG_00B4_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B4_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B8_PAFRC_BKA324 (PAFRC_BKA324 + 0x0B8)
    #define REG_00B8_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B8_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00BC_PAFRC_BKA324 (PAFRC_BKA324 + 0x0BC)
    #define REG_00BC_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00BC_PAFRC_BKA324_REG_VAC_GLUT1_LVL_COEF15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C0_PAFRC_BKA324 (PAFRC_BKA324 + 0x0C0)
    #define REG_00C0_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C0_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_PAFRC_BKA324 (PAFRC_BKA324 + 0x0C4)
    #define REG_00C4_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C4_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C8_PAFRC_BKA324 (PAFRC_BKA324 + 0x0C8)
    #define REG_00C8_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C8_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_PAFRC_BKA324 (PAFRC_BKA324 + 0x0CC)
    #define REG_00CC_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00CC_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D0_PAFRC_BKA324 (PAFRC_BKA324 + 0x0D0)
    #define REG_00D0_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D0_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D4_PAFRC_BKA324 (PAFRC_BKA324 + 0x0D4)
    #define REG_00D4_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D4_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D8_PAFRC_BKA324 (PAFRC_BKA324 + 0x0D8)
    #define REG_00D8_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D8_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00DC_PAFRC_BKA324 (PAFRC_BKA324 + 0x0DC)
    #define REG_00DC_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00DC_PAFRC_BKA324_REG_VAC_BLUT0_LVL_COEF15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00E0_PAFRC_BKA324 (PAFRC_BKA324 + 0x0E0)
    #define REG_00E0_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00E0_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00E4_PAFRC_BKA324 (PAFRC_BKA324 + 0x0E4)
    #define REG_00E4_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00E4_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00E8_PAFRC_BKA324 (PAFRC_BKA324 + 0x0E8)
    #define REG_00E8_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00E8_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00EC_PAFRC_BKA324 (PAFRC_BKA324 + 0x0EC)
    #define REG_00EC_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00EC_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00F0_PAFRC_BKA324 (PAFRC_BKA324 + 0x0F0)
    #define REG_00F0_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00F0_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00F4_PAFRC_BKA324 (PAFRC_BKA324 + 0x0F4)
    #define REG_00F4_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00F4_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00F8_PAFRC_BKA324 (PAFRC_BKA324 + 0x0F8)
    #define REG_00F8_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00F8_PAFRC_BKA324_REG_VAC_BLUT1_LVL_COEF13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00FC_PAFRC_BKA324 (PAFRC_BKA324 + 0x0FC)
    #define REG_00FC_PAFRC_BKA324_REG_FRC_ON Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00FC_PAFRC_BKA324_REG_TCON_OFF_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00FC_PAFRC_BKA324_REG_DITH_BITS Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00FC_PAFRC_BKA324_REG_POL_TYPE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00FC_PAFRC_BKA324_REG_BOOST_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00FC_PAFRC_BKA324_REG_DITHER_BIT_1 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00FC_PAFRC_BKA324_REG_LSB_ALIGNMENT_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_00FC_PAFRC_BKA324_REG_BYPASS_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_13B Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0100_PAFRC_BKA324 (PAFRC_BKA324 + 0x100)
    #define REG_0100_PAFRC_BKA324_REG_G_V_SWAP Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0100_PAFRC_BKA324_REG_G_H_SWAP Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0100_PAFRC_BKA324_REG_B_D_SWAP Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0100_PAFRC_BKA324_REG_BOX_FR_SW Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0100_PAFRC_BKA324_REG_BOX4X4_FR_SW Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0100_PAFRC_BKA324_REG_BOX8X8_ROT_UNIT Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0100_PAFRC_BKA324_REG_BOX_FREEZE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0100_PAFRC_BKA324_REG_BOX_ROTATE_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0100_PAFRC_BKA324_REG_TOP_BOX_UNIT_FLAG Fld(2,5,AC_MSKB0)//[6:5]
    #define REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0100_PAFRC_BKA324_REG_TOP_BOX_SHRINK Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0100_PAFRC_BKA324_REG_FR_C2_BIT Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0100_PAFRC_BKA324_REG_C2X2_ROT_B_DIR_S Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0100_PAFRC_BKA324_REG_D2X2_ROT_B_DIR_S Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0104_PAFRC_BKA324 (PAFRC_BKA324 + 0x104)
    #define REG_0104_PAFRC_BKA324_REG_A2X2_ROT_R_DIR Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0104_PAFRC_BKA324_REG_B2X2_ROT_R_DIR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0104_PAFRC_BKA324_REG_C2X2_ROT_R_DIR Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0104_PAFRC_BKA324_REG_D2X2_ROT_R_DIR Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0104_PAFRC_BKA324_REG_C2X2_ROT_R_DIR_S Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0104_PAFRC_BKA324_REG_D2X2_ROT_R_DIR_S Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0104_PAFRC_BKA324_REG_A2X2_ROT_G_DIR Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0104_PAFRC_BKA324_REG_B2X2_ROT_G_DIR Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0104_PAFRC_BKA324_REG_C2X2_ROT_G_DIR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0104_PAFRC_BKA324_REG_D2X2_ROT_G_DIR Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0104_PAFRC_BKA324_REG_C2X2_ROT_G_DIR_S Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0104_PAFRC_BKA324_REG_D2X2_ROT_G_DIR_S Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0104_PAFRC_BKA324_REG_A2X2_ROT_B_DIR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0104_PAFRC_BKA324_REG_B2X2_ROT_B_DIR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0104_PAFRC_BKA324_REG_C2X2_ROT_B_DIR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0104_PAFRC_BKA324_REG_D2X2_ROT_B_DIR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0108_PAFRC_BKA324 (PAFRC_BKA324 + 0x108)
    #define REG_0108_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_0108_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_010C_PAFRC_BKA324 (PAFRC_BKA324 + 0x10C)
    #define REG_010C_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ3 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_010C_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0110_PAFRC_BKA324 (PAFRC_BKA324 + 0x110)
    #define REG_0110_PAFRC_BKA324_REG_TOP_BOX_FR_C2_SEQ12 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_0110_PAFRC_BKA324_REG_TOP_BOX_FR_C2_SEQ34 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0114_PAFRC_BKA324 (PAFRC_BKA324 + 0x114)
    #define REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_00 Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_01 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_11 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_10 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0114_PAFRC_BKA324_REG_BOX_A_ROT_DIR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0114_PAFRC_BKA324_REG_BOX_B_ROT_DIR Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0114_PAFRC_BKA324_REG_BOX_C_ROT_DIR Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0114_PAFRC_BKA324_REG_BOX_D_ROT_DIR Fld(1,4,AC_MSKB0)//[4:4]
#define REG_0118_PAFRC_BKA324 (PAFRC_BKA324 + 0x118)
    #define REG_0118_PAFRC_BKA324_REG_A_LU_00 Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_0118_PAFRC_BKA324_REG_A_RU_01 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0118_PAFRC_BKA324_REG_A_RD_11 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0118_PAFRC_BKA324_REG_A_LD_10 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0118_PAFRC_BKA324_REG_B_LU_00 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0118_PAFRC_BKA324_REG_B_RU_01 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0118_PAFRC_BKA324_REG_B_RD_11 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0118_PAFRC_BKA324_REG_B_LD_10 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_011C_PAFRC_BKA324 (PAFRC_BKA324 + 0x11C)
    #define REG_011C_PAFRC_BKA324_REG_C_LU_00 Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_011C_PAFRC_BKA324_REG_C_RU_01 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_011C_PAFRC_BKA324_REG_C_RD_11 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_011C_PAFRC_BKA324_REG_C_LD_10 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_011C_PAFRC_BKA324_REG_D_LU_00 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_011C_PAFRC_BKA324_REG_D_RU_01 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_011C_PAFRC_BKA324_REG_D_RD_11 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_011C_PAFRC_BKA324_REG_D_LD_10 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0120_PAFRC_BKA324 (PAFRC_BKA324 + 0x120)
    #define REG_0120_PAFRC_BKA324_REG_C_LU_00_S Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_0120_PAFRC_BKA324_REG_C_RU_01_S Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0120_PAFRC_BKA324_REG_C_RD_11_S Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0120_PAFRC_BKA324_REG_C_LD_10_S Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0120_PAFRC_BKA324_REG_D_LU_00_S Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0120_PAFRC_BKA324_REG_D_RU_01_S Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0120_PAFRC_BKA324_REG_D_RD_11_S Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0120_PAFRC_BKA324_REG_D_LD_10_S Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0124_PAFRC_BKA324 (PAFRC_BKA324 + 0x124)
    #define REG_0124_PAFRC_BKA324_REG_BOX_A_LU_00 Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_0124_PAFRC_BKA324_REG_BOX_A_RU_01 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0124_PAFRC_BKA324_REG_BOX_A_RD_11 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0124_PAFRC_BKA324_REG_BOX_A_LD_10 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0124_PAFRC_BKA324_REG_BOX_B_LU_00 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0124_PAFRC_BKA324_REG_BOX_B_RU_01 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0124_PAFRC_BKA324_REG_BOX_B_RD_11 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0124_PAFRC_BKA324_REG_BOX_B_LD_10 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0128_PAFRC_BKA324 (PAFRC_BKA324 + 0x128)
    #define REG_0128_PAFRC_BKA324_REG_BOX_C_LU_00 Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_0128_PAFRC_BKA324_REG_BOX_C_RU_01 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0128_PAFRC_BKA324_REG_BOX_C_RD_11 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0128_PAFRC_BKA324_REG_BOX_C_LD_10 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0128_PAFRC_BKA324_REG_BOX_D_LU_00 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0128_PAFRC_BKA324_REG_BOX_D_RU_01 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0128_PAFRC_BKA324_REG_BOX_D_RD_11 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0128_PAFRC_BKA324_REG_BOX_D_LD_10 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_012C_PAFRC_BKA324 (PAFRC_BKA324 + 0x12C)
    #define REG_012C_PAFRC_BKA324_REG_RST_E_4_FRAME Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_012C_PAFRC_BKA324_REG_PSEUDO_DE_SHIFT_ONLY Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_012C_PAFRC_BKA324_REG_PSE_RST_NUM Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_012C_PAFRC_BKA324_REG_13B_CLAMP_MODE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_012C_PAFRC_BKA324_REG_DEBUG_MODE Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_012C_PAFRC_BKA324_REG_DEBUG_EN Fld(1,7,AC_MSKB0)//[7:7]
#define REG_017C_PAFRC_BKA324 (PAFRC_BKA324 + 0x17C)
    #define REG_017C_PAFRC_BKA324_REG_BRI_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_017C_PAFRC_BKA324_REG_CON_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_017C_PAFRC_BKA324_REG_OP2_CB_DITHER_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_017C_PAFRC_BKA324_REG_R_BRI_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
    #define V2_REG_017C_PAFRC_BKA324_REG_R_BRI_OFFSET Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0180_PAFRC_BKA324 (PAFRC_BKA324 + 0x180)
    #define REG_0180_PAFRC_BKA324_REG_RGB_DATA_PATH Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_0180_PAFRC_BKA324_REG_OP2_CB_INPUT_MUTE Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0180_PAFRC_BKA324_REG_OP2_CB_DB_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0180_PAFRC_BKA324_REG_G_BRI_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
    #define V2_REG_0180_PAFRC_BKA324_REG_G_BRI_OFFSET Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0184_PAFRC_BKA324 (PAFRC_BKA324 + 0x184)
    #define REG_0184_PAFRC_BKA324_REG_B_BRI_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
    #define V2_REG_0184_PAFRC_BKA324_REG_B_BRI_OFFSET Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0188_PAFRC_BKA324 (PAFRC_BKA324 + 0x188)
    #define REG_0188_PAFRC_BKA324_REG_R_CON_GAIN Fld(13,0,AC_MSKW10)//[12:0]
#define REG_018C_PAFRC_BKA324 (PAFRC_BKA324 + 0x18C)
    #define REG_018C_PAFRC_BKA324_REG_G_CON_GAIN Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0190_PAFRC_BKA324 (PAFRC_BKA324 + 0x190)
    #define REG_0190_PAFRC_BKA324_REG_B_CON_GAIN Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0194_PAFRC_BKA324 (PAFRC_BKA324 + 0x194)
    #define REG_0194_PAFRC_BKA324_REG_W_BRI_OFFSET Fld(11,0,AC_MSKW10)//[10:0]
    #define V2_REG_0194_PAFRC_BKA324_REG_W_BRI_OFFSET Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0198_PAFRC_BKA324 (PAFRC_BKA324 + 0x198)
    #define REG_0198_PAFRC_BKA324_REG_W_CON_GAIN Fld(13,0,AC_MSKW10)//[12:0]
#define REG_019C_PAFRC_BKA324 (PAFRC_BKA324 + 0x19C)
    #define REG_019C_PAFRC_BKA324_REG_BOOST_MODE_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_019C_PAFRC_BKA324_REG_GAMMA_EXT_2048 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_019C_PAFRC_BKA324_REG_GAMMA_OUT_IS_1_10P1 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_019C_PAFRC_BKA324_REG_BLEND_SATURATION_DITH Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_019C_PAFRC_BKA324_REG_PA_AWB_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_019C_PAFRC_BKA324_REG_SATURATION_BLEND_MODE_EN Fld(1,5,AC_MSKB0)//[5:5]

//Page PAFRC_BKA324_2
#define REG_01A4_PAFRC_BKA324 (PAFRC_BKA324 + 0x1A4)
    #define REG_01A4_PAFRC_BKA324_REG_GAMMA_2LUT_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01A4_PAFRC_BKA324_REG_GAMMA_LUT_SEL Fld(1,13,AC_MSKB1)//[13:13]
#define REG_01A8_PAFRC_BKA324 (PAFRC_BKA324 + 0x1A8)
    #define REG_01A8_PAFRC_BKA324_REG_GAMMA_2LUT_MODE_SEL Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01B0_PAFRC_BKA324 (PAFRC_BKA324 + 0x1B0)
    #define REG_01B0_PAFRC_BKA324_REG_GAMMA_BYPASS Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01B0_PAFRC_BKA324_REG_GAMMA_ADR Fld(10,0,AC_MSKW10)//[9:0]
    #define V2_REG_01B0_PAFRC_BKA324_REG_GAMMA_ADR Fld(11,0,AC_MSKW10)//[10:0]
#define REG_01B4_PAFRC_BKA324 (PAFRC_BKA324 + 0x1B4)
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_HW_DL_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_RD_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_ONE_DRV3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_REVERSE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_DITHER_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_BW_FLAG Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_DGA_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_WR_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_REPEAT_MAX Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_CH_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_OUT_IS_EXTEND Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01B4_PAFRC_BKA324_REG_GAMMA_BW_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01B8_PAFRC_BKA324 (PAFRC_BKA324 + 0x1B8)
    #define REG_01B8_PAFRC_BKA324_REG_GAMMA_DATA Fld(12,0,AC_MSKW10)//[11:0]
    #define V2_REG_01B8_PAFRC_BKA324_REG_GAMMA_DATA Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01C4_PAFRC_BKA324 (PAFRC_BKA324 + 0x1C4)
    #define REG_01C4_PAFRC_BKA324_REG_GAMMA_RD_DATA Fld(12,0,AC_MSKW10)//[11:0]
    #define V2_REG_01C4_PAFRC_BKA324_REG_GAMMA_RD_DATA Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01D8_PAFRC_BKA324 (PAFRC_BKA324 + 0x1D8)
    #define REG_01D8_PAFRC_BKA324_REG_GAMMA_BISTFAIL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01DC_PAFRC_BKA324 (PAFRC_BKA324 + 0x1DC)
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_W_R Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_B_R Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_G_R Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_R_R Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_W_L Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_B_L Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_G_L Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01DC_PAFRC_BKA324_REG_GAMMA_DGA_CH_LOC_R_L Fld(2,0,AC_MSKB0)//[1:0]

