/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_SCMW_H
#define _DT_BINDINGS_CLK_MT5896_SCMW_H

#define CLK_SCMW_XTAL_24M_INT_CK	1
#define CLK_SCMW_MCU_NONPM_INT_CK	2
#define CLK_SCMW_RIU_NONPM_INT_CK	3
#define CLK_SCMW_SMI_INT_CK	4
#define CLK_SCMW_MCU_XC_INT_CK	5
#define CLK_SCMW_RIU_XC_INT_CK	6
#define CLK_SCMW_V1_ODCLK_INT_CK	7
#define CLK_SCMW_XC_FD_INT_CK	8
#define CLK_SCMW_XC_FS_INT_CK	9
#define CLK_SCMW_XC_FN_INT_CK	10
#define CLK_SCMW_XC_OD_INT_CK	11
#define CLK_SCMW_FRC_FCLK_2XPLUS_INT_CK	12
#define CLK_SCMW_XVYCC_SRAM_INT_CK	14
#define CLK_SCMW_RGB_3DLUT_SRAM_INT_CK	15
#define CLK_SCMW_PQ_GAMMA_SRAM_INT_CK	16
#define CLK_SCMW_DIP1_HVSP_SRAM_INT_CK	18
#define CLK_SCMW_DIP1_XVYCC_SRAM_INT_CK	19
#define CLK_SCMW_NR	20

#endif
