/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_ADCPLL_H
#define _DT_BINDINGS_CLK_MT5896_ADCPLL_H

#define CLK_ADCPLL_RIU_NONPM_INT_CK	1
#define CLK_ADCPLL_CLKD_ADC_P_INT_CK	2
#define CLK_ADCPLL_CLKD_ATOP_INT_CK	3
#define CLK_ADCPLL_CLKD_ATOP_INTERNAL_INT_CK	4
#define CLK_ADCPLL_R_INT_INT_CK	5
#define CLK_ADCPLL_G_INT_INT_CK	6
#define CLK_ADCPLL_B_INT_INT_CK	7
#define CLK_ADCPLL_Y_INT_INT_CK	8
#define CLK_ADCPLL_ISOG_INT_CK	9
#define CLK_ADCPLL_XTAL12_INT_CK	10
#define CLK_ADCPLL_XTAL12_4INTERRUPT_INT_CK	11
#define CLK_ADCPLL_XTAL12_4PLUGDET_INT_CK	12
#define CLK_ADCPLL_XTAL24_INT_CK	13
#define CLK_ADCPLL_ADCPLL200_INT_CK	14
#define CLK_ADCPLL_ADCPLL400_INT_CK	15
#define CLK_ADCPLL_VDPLL400_INT_CK	16
#define CLK_ADCPLL_CLKPLL_INT_CK	17
#define CLK_ADCPLL_R_ADC_INT_CK	18
#define CLK_ADCPLL_G_ADC_INT_CK	19
#define CLK_ADCPLL_B_ADC_INT_CK	20
#define CLK_ADCPLL_Y_ADC_INT_CK	21
#define CLK_ADCPLL_YUV_ADC_INT_CK	22
#define CLK_ADCPLL_ICLAMP_RGB_INT_CK	23
#define CLK_ADCPLL_ADC_INT_CK	24
#define CLK_ADCPLL_VD_INT_CK	25
#define CLK_ADCPLL_ADC2SC_INT_CK	26
#define CLK_ADCPLL_FBLANK_INT_CK	27
#define CLK_ADCPLL_FSCX2_FB2ATOP_INT_CK	28
#define CLK_ADCPLL_NCO_CLK_INT_CK	29
#define CLK_ADCPLL_VD_NCO_CLK_INT_CK	30
#define CLK_ADCPLL_ADC2MIU_INT_CK	31
#define CLK_ADCPLL_ADC2MIUSC_INT_CK	32
#define CLK_ADCPLL_CLK_TSTBUS_INT_CK	33
#define CLK_ADCPLL_CLK_TSTBUS_DIV_INT_CK	34
#define CLK_ADCPLL_VD_DIV2_EN_TO_TOP_INT_CK	35
#define CLK_ADCPLL_CVBS_DAC_A_DIGITAL0_INT_CK	36
#define CLK_ADCPLL_CVBS_DAC_A_DIGITAL1_INT_CK	37
#define CLK_ADCPLL_CVBS_DAC_A_DIGITAL0_MUX_INT_CK	38
#define CLK_ADCPLL_FSC_VD_INT_CK	39
#define CLK_ADCPLL_VD_ICLAMP_INT_CK	40
#define CLK_ADCPLL_ADCPLLB_MPLL_216M_INT_CK	41
#define CLK_ADCPLL_DIG_216_INT_CK	42
#define CLK_ADCPLL_DIG_108_INT_CK	43
#define CLK_ADCPLL_OCC_SLOW_62P4M_INT_CK	44
#define CLK_ADCPLL_NR	45

#endif
