#ifndef _MODA3_H
#define _MODA3_H

#define moda3 0x00484A00

//Page MODA3
#define REG_0008_MODA3 (moda3 + 0x008)
    #define REG_0008_MODA3_REG_GCR_DS_POL_CH_59_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_MODA3 (moda3 + 0x00C)
    #define REG_000C_MODA3_REG_GCR_DS_POL_CH_59_40_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0010_MODA3 (moda3 + 0x010)
    #define REG_0010_MODA3_REG_GCR_PE_EN_CH_59_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_MODA3 (moda3 + 0x014)
    #define REG_0014_MODA3_REG_GCR_PE_EN_CH_59_40_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0018_MODA3 (moda3 + 0x018)
    #define REG_0018_MODA3_REG_GCR_EN_RINT_CH_59_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_MODA3 (moda3 + 0x01C)
    #define REG_001C_MODA3_REG_GCR_EN_RINT_CH_59_40_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0020_MODA3 (moda3 + 0x020)
    #define REG_0020_MODA3_REG_GCR_EN_VBY1_CH_59_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_MODA3 (moda3 + 0x024)
    #define REG_0024_MODA3_REG_GCR_EN_VBY1_CH_59_40_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0028_MODA3 (moda3 + 0x028)
    #define REG_0028_MODA3_REG_GCR_TTL_LPM_EN_CH_59_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_MODA3 (moda3 + 0x02C)
    #define REG_002C_MODA3_REG_GCR_TTL_LPM_EN_CH_59_40_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0030_MODA3 (moda3 + 0x030)
    #define REG_0030_MODA3_REG_GCR_EN_XSWING_CH_59_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_MODA3 (moda3 + 0x034)
    #define REG_0034_MODA3_REG_GCR_EN_XSWING_CH_59_40_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0060_MODA3 (moda3 + 0x060)
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH40 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH41 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH42 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH43 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH44 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH45 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH46 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0060_MODA3_REG_OUTPUT_CONF_CH47 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0064_MODA3 (moda3 + 0x064)
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH48 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH49 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH50 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH51 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH52 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH53 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH54 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0064_MODA3_REG_OUTPUT_CONF_CH55 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0068_MODA3 (moda3 + 0x068)
    #define REG_0068_MODA3_REG_OUTPUT_CONF_CH56 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0068_MODA3_REG_OUTPUT_CONF_CH57 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0068_MODA3_REG_OUTPUT_CONF_CH58 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0068_MODA3_REG_OUTPUT_CONF_CH59 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0070_MODA3 (moda3 + 0x070)
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH40 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH41 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH42 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH43 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH44 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH45 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH46 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0070_MODA3_REG_FTUNE_SKEW_CH47 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0074_MODA3 (moda3 + 0x074)
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH48 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH49 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH50 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH51 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH52 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH53 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH54 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0074_MODA3_REG_FTUNE_SKEW_CH55 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0078_MODA3 (moda3 + 0x078)
    #define REG_0078_MODA3_REG_FTUNE_SKEW_CH56 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0078_MODA3_REG_FTUNE_SKEW_CH57 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0078_MODA3_REG_FTUNE_SKEW_CH58 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0078_MODA3_REG_FTUNE_SKEW_CH59 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0080_MODA3 (moda3 + 0x080)
    #define REG_0080_MODA3_REG_GCR_PE_ADJ_CH40 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0080_MODA3_REG_GCR_PE_ADJ_CH41 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0084_MODA3 (moda3 + 0x084)
    #define REG_0084_MODA3_REG_GCR_PE_ADJ_CH42 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0084_MODA3_REG_GCR_PE_ADJ_CH43 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0088_MODA3 (moda3 + 0x088)
    #define REG_0088_MODA3_REG_GCR_PE_ADJ_CH44 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0088_MODA3_REG_GCR_PE_ADJ_CH45 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_008C_MODA3 (moda3 + 0x08C)
    #define REG_008C_MODA3_REG_GCR_PE_ADJ_CH46 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_008C_MODA3_REG_GCR_PE_ADJ_CH47 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0090_MODA3 (moda3 + 0x090)
    #define REG_0090_MODA3_REG_GCR_PE_ADJ_CH48 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0090_MODA3_REG_GCR_PE_ADJ_CH49 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0094_MODA3 (moda3 + 0x094)
    #define REG_0094_MODA3_REG_GCR_PE_ADJ_CH50 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0094_MODA3_REG_GCR_PE_ADJ_CH51 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0098_MODA3 (moda3 + 0x098)
    #define REG_0098_MODA3_REG_GCR_PE_ADJ_CH52 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0098_MODA3_REG_GCR_PE_ADJ_CH53 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_009C_MODA3 (moda3 + 0x09C)
    #define REG_009C_MODA3_REG_GCR_PE_ADJ_CH54 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_009C_MODA3_REG_GCR_PE_ADJ_CH55 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A0_MODA3 (moda3 + 0x0A0)
    #define REG_00A0_MODA3_REG_GCR_PE_ADJ_CH56 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00A0_MODA3_REG_GCR_PE_ADJ_CH57 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A4_MODA3 (moda3 + 0x0A4)
    #define REG_00A4_MODA3_REG_GCR_PE_ADJ_CH58 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00A4_MODA3_REG_GCR_PE_ADJ_CH59 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00B0_MODA3 (moda3 + 0x0B0)
    #define REG_00B0_MODA3_REG_GCR_ICON_CH40 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B0_MODA3_REG_GCR_ICON_CH41 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B4_MODA3 (moda3 + 0x0B4)
    #define REG_00B4_MODA3_REG_GCR_ICON_CH42 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B4_MODA3_REG_GCR_ICON_CH43 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B8_MODA3 (moda3 + 0x0B8)
    #define REG_00B8_MODA3_REG_GCR_ICON_CH44 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B8_MODA3_REG_GCR_ICON_CH45 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00BC_MODA3 (moda3 + 0x0BC)
    #define REG_00BC_MODA3_REG_GCR_ICON_CH46 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00BC_MODA3_REG_GCR_ICON_CH47 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C0_MODA3 (moda3 + 0x0C0)
    #define REG_00C0_MODA3_REG_GCR_ICON_CH48 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C0_MODA3_REG_GCR_ICON_CH49 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_MODA3 (moda3 + 0x0C4)
    #define REG_00C4_MODA3_REG_GCR_ICON_CH50 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C4_MODA3_REG_GCR_ICON_CH51 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C8_MODA3 (moda3 + 0x0C8)
    #define REG_00C8_MODA3_REG_GCR_ICON_CH52 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C8_MODA3_REG_GCR_ICON_CH53 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_MODA3 (moda3 + 0x0CC)
    #define REG_00CC_MODA3_REG_GCR_ICON_CH54 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00CC_MODA3_REG_GCR_ICON_CH55 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D0_MODA3 (moda3 + 0x0D0)
    #define REG_00D0_MODA3_REG_GCR_ICON_CH56 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D0_MODA3_REG_GCR_ICON_CH57 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D4_MODA3 (moda3 + 0x0D4)
    #define REG_00D4_MODA3_REG_GCR_ICON_CH58 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D4_MODA3_REG_GCR_ICON_CH59 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00E0_MODA3 (moda3 + 0x0E0)
    #define REG_00E0_MODA3_REG_GCR_RCON_CH40 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E0_MODA3_REG_GCR_RCON_CH41 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00E4_MODA3 (moda3 + 0x0E4)
    #define REG_00E4_MODA3_REG_GCR_RCON_CH42 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E4_MODA3_REG_GCR_RCON_CH43 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00E8_MODA3 (moda3 + 0x0E8)
    #define REG_00E8_MODA3_REG_GCR_RCON_CH44 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E8_MODA3_REG_GCR_RCON_CH45 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00EC_MODA3 (moda3 + 0x0EC)
    #define REG_00EC_MODA3_REG_GCR_RCON_CH46 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00EC_MODA3_REG_GCR_RCON_CH47 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F0_MODA3 (moda3 + 0x0F0)
    #define REG_00F0_MODA3_REG_GCR_RCON_CH48 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F0_MODA3_REG_GCR_RCON_CH49 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F4_MODA3 (moda3 + 0x0F4)
    #define REG_00F4_MODA3_REG_GCR_RCON_CH50 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F4_MODA3_REG_GCR_RCON_CH51 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F8_MODA3 (moda3 + 0x0F8)
    #define REG_00F8_MODA3_REG_GCR_RCON_CH52 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F8_MODA3_REG_GCR_RCON_CH53 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00FC_MODA3 (moda3 + 0x0FC)
    #define REG_00FC_MODA3_REG_GCR_RCON_CH54 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00FC_MODA3_REG_GCR_RCON_CH55 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0100_MODA3 (moda3 + 0x100)
    #define REG_0100_MODA3_REG_GCR_RCON_CH56 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0100_MODA3_REG_GCR_RCON_CH57 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0104_MODA3 (moda3 + 0x104)
    #define REG_0104_MODA3_REG_GCR_RCON_CH58 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0104_MODA3_REG_GCR_RCON_CH59 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0110_MODA3 (moda3 + 0x110)
    #define REG_0110_MODA3_REG_RINT_SEL_CH40 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0110_MODA3_REG_RINT_SEL_CH41 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0110_MODA3_REG_RINT_SEL_CH42 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0110_MODA3_REG_RINT_SEL_CH43 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0114_MODA3 (moda3 + 0x114)
    #define REG_0114_MODA3_REG_RINT_SEL_CH44 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0114_MODA3_REG_RINT_SEL_CH45 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0114_MODA3_REG_RINT_SEL_CH46 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0114_MODA3_REG_RINT_SEL_CH47 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0118_MODA3 (moda3 + 0x118)
    #define REG_0118_MODA3_REG_RINT_SEL_CH48 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0118_MODA3_REG_RINT_SEL_CH49 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0118_MODA3_REG_RINT_SEL_CH50 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0118_MODA3_REG_RINT_SEL_CH51 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_011C_MODA3 (moda3 + 0x11C)
    #define REG_011C_MODA3_REG_RINT_SEL_CH52 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_011C_MODA3_REG_RINT_SEL_CH53 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_011C_MODA3_REG_RINT_SEL_CH54 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_011C_MODA3_REG_RINT_SEL_CH55 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0120_MODA3 (moda3 + 0x120)
    #define REG_0120_MODA3_REG_RINT_SEL_CH56 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0120_MODA3_REG_RINT_SEL_CH57 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0120_MODA3_REG_RINT_SEL_CH58 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0120_MODA3_REG_RINT_SEL_CH59 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0124_MODA3 (moda3 + 0x124)
    #define REG_0124_MODA3_REG_GCR_TEST_PRE_LDO_CH40 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0124_MODA3_REG_GCR_TEST_PRE_LDO_CH41 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0124_MODA3_REG_GCR_TEST_PRE_LDO_CH42 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0124_MODA3_REG_GCR_TEST_PRE_LDO_CH43 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0128_MODA3 (moda3 + 0x128)
    #define REG_0128_MODA3_REG_GCR_TEST_PRE_LDO_CH44 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0128_MODA3_REG_GCR_TEST_PRE_LDO_CH45 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0128_MODA3_REG_GCR_TEST_PRE_LDO_CH46 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0128_MODA3_REG_GCR_TEST_PRE_LDO_CH47 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_012C_MODA3 (moda3 + 0x12C)
    #define REG_012C_MODA3_REG_GCR_TEST_PRE_LDO_CH48 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_012C_MODA3_REG_GCR_TEST_PRE_LDO_CH49 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_012C_MODA3_REG_GCR_TEST_PRE_LDO_CH50 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_012C_MODA3_REG_GCR_TEST_PRE_LDO_CH51 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0130_MODA3 (moda3 + 0x130)
    #define REG_0130_MODA3_REG_GCR_TEST_PRE_LDO_CH52 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0130_MODA3_REG_GCR_TEST_PRE_LDO_CH53 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0130_MODA3_REG_GCR_TEST_PRE_LDO_CH54 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0130_MODA3_REG_GCR_TEST_PRE_LDO_CH55 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0134_MODA3 (moda3 + 0x134)
    #define REG_0134_MODA3_REG_GCR_TEST_PRE_LDO_CH56 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0134_MODA3_REG_GCR_TEST_PRE_LDO_CH57 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0134_MODA3_REG_GCR_TEST_PRE_LDO_CH58 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0134_MODA3_REG_GCR_TEST_PRE_LDO_CH59 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0140_MODA3 (moda3 + 0x140)
    #define REG_0140_MODA3_REG_GCR_VBY1_VREG_CH40 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0140_MODA3_REG_GCR_VBY1_VREG_CH41 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0140_MODA3_REG_GCR_VBY1_VREG_CH42 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0140_MODA3_REG_GCR_VBY1_VREG_CH43 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0144_MODA3 (moda3 + 0x144)
    #define REG_0144_MODA3_REG_GCR_VBY1_VREG_CH44 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0144_MODA3_REG_GCR_VBY1_VREG_CH45 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0144_MODA3_REG_GCR_VBY1_VREG_CH46 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0144_MODA3_REG_GCR_VBY1_VREG_CH47 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0148_MODA3 (moda3 + 0x148)
    #define REG_0148_MODA3_REG_GCR_VBY1_VREG_CH48 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0148_MODA3_REG_GCR_VBY1_VREG_CH49 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0148_MODA3_REG_GCR_VBY1_VREG_CH50 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0148_MODA3_REG_GCR_VBY1_VREG_CH51 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_014C_MODA3 (moda3 + 0x14C)
    #define REG_014C_MODA3_REG_GCR_VBY1_VREG_CH52 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_014C_MODA3_REG_GCR_VBY1_VREG_CH53 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_014C_MODA3_REG_GCR_VBY1_VREG_CH54 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_014C_MODA3_REG_GCR_VBY1_VREG_CH55 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0150_MODA3 (moda3 + 0x150)
    #define REG_0150_MODA3_REG_GCR_VBY1_VREG_CH56 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0150_MODA3_REG_GCR_VBY1_VREG_CH57 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0150_MODA3_REG_GCR_VBY1_VREG_CH58 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0150_MODA3_REG_GCR_VBY1_VREG_CH59 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0154_MODA3 (moda3 + 0x154)
    #define REG_0154_MODA3_REG_DRV_MODE_CH40 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0154_MODA3_REG_DRV_MODE_CH41 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0154_MODA3_REG_DRV_MODE_CH42 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0154_MODA3_REG_DRV_MODE_CH43 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0154_MODA3_REG_DRV_MODE_CH44 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0154_MODA3_REG_DRV_MODE_CH45 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0154_MODA3_REG_DRV_MODE_CH46 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0154_MODA3_REG_DRV_MODE_CH47 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0158_MODA3 (moda3 + 0x158)
    #define REG_0158_MODA3_REG_DRV_MODE_CH48 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0158_MODA3_REG_DRV_MODE_CH49 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0158_MODA3_REG_DRV_MODE_CH50 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0158_MODA3_REG_DRV_MODE_CH51 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0158_MODA3_REG_DRV_MODE_CH52 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0158_MODA3_REG_DRV_MODE_CH53 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0158_MODA3_REG_DRV_MODE_CH54 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0158_MODA3_REG_DRV_MODE_CH55 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_015C_MODA3 (moda3 + 0x15C)
    #define REG_015C_MODA3_REG_DRV_MODE_CH56 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_015C_MODA3_REG_DRV_MODE_CH57 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_015C_MODA3_REG_DRV_MODE_CH58 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_015C_MODA3_REG_DRV_MODE_CH59 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0168_MODA3 (moda3 + 0x168)
    #define REG_0168_MODA3_REG_BIAS_CON_OFFSET_CH40 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0168_MODA3_REG_BIAS_CON_OFFSET_CH41 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0168_MODA3_REG_BIAS_CON_OFFSET_CH42 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0168_MODA3_REG_BIAS_CON_OFFSET_CH43 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_016C_MODA3 (moda3 + 0x16C)
    #define REG_016C_MODA3_REG_BIAS_CON_OFFSET_CH44 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_016C_MODA3_REG_BIAS_CON_OFFSET_CH45 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_016C_MODA3_REG_BIAS_CON_OFFSET_CH46 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_016C_MODA3_REG_BIAS_CON_OFFSET_CH47 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0170_MODA3 (moda3 + 0x170)
    #define REG_0170_MODA3_REG_BIAS_CON_OFFSET_CH48 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0170_MODA3_REG_BIAS_CON_OFFSET_CH49 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0170_MODA3_REG_BIAS_CON_OFFSET_CH50 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0170_MODA3_REG_BIAS_CON_OFFSET_CH51 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0174_MODA3 (moda3 + 0x174)
    #define REG_0174_MODA3_REG_BIAS_CON_OFFSET_CH52 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0174_MODA3_REG_BIAS_CON_OFFSET_CH53 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0174_MODA3_REG_BIAS_CON_OFFSET_CH54 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0174_MODA3_REG_BIAS_CON_OFFSET_CH55 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0178_MODA3 (moda3 + 0x178)
    #define REG_0178_MODA3_REG_BIAS_CON_OFFSET_CH56 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0178_MODA3_REG_BIAS_CON_OFFSET_CH57 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0178_MODA3_REG_BIAS_CON_OFFSET_CH58 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0178_MODA3_REG_BIAS_CON_OFFSET_CH59 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0180_MODA3 (moda3 + 0x180)
    #define REG_0180_MODA3_REG_GPO_OEZ_119_80_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0184_MODA3 (moda3 + 0x184)
    #define REG_0184_MODA3_REG_GPO_OEZ_119_80_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_MODA3 (moda3 + 0x188)
    #define REG_0188_MODA3_REG_GPO_OEZ_119_80_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_018C_MODA3 (moda3 + 0x18C)
    #define REG_018C_MODA3_REG_GPO_DATA_119_80_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_MODA3 (moda3 + 0x190)
    #define REG_0190_MODA3_REG_GPO_DATA_119_80_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_MODA3 (moda3 + 0x194)
    #define REG_0194_MODA3_REG_GPO_DATA_119_80_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0198_MODA3 (moda3 + 0x198)
    #define REG_0198_MODA3_REG_GPI_DATA_119_80_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_MODA3 (moda3 + 0x19C)
    #define REG_019C_MODA3_REG_GPI_DATA_119_80_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_MODA3 (moda3 + 0x1A0)
    #define REG_01A0_MODA3_REG_GPI_DATA_119_80_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01A4_MODA3 (moda3 + 0x1A4)
    #define REG_01A4_MODA3_REG_EXT_EN_119_80_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A8_MODA3 (moda3 + 0x1A8)
    #define REG_01A8_MODA3_REG_EXT_EN_119_80_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01AC_MODA3 (moda3 + 0x1AC)
    #define REG_01AC_MODA3_REG_EXT_EN_119_80_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01B0_MODA3 (moda3 + 0x1B0)
    #define REG_01B0_MODA3_REG_TTL_EN_119_80_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B4_MODA3 (moda3 + 0x1B4)
    #define REG_01B4_MODA3_REG_TTL_EN_119_80_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B8_MODA3 (moda3 + 0x1B8)
    #define REG_01B8_MODA3_REG_TTL_EN_119_80_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01C0_MODA3 (moda3 + 0x1C0)
    #define REG_01C0_MODA3_REG_V1_2_PRBS_DET_CH_SEL Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_01C0_MODA3_REG_V1_2_TEST_PRBS_EN Fld(1,12,AC_MSKB1)//[12:12]
#define REG_01C4_MODA3 (moda3 + 0x1C4)
    #define REG_01C4_MODA3_REG_V1_2_PRBS_BIT_ERROR_CNT Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01C4_MODA3_REG_V1_2_PRBS_BIT_ERROR_CNT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01C4_MODA3_REG_V1_2_PRBS_COMPARE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01EC_MODA3 (moda3 + 0x1EC)
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_40 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_41 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_42 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_43 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_44 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_45 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_46 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01EC_MODA3_REG_TEST_DATA_SEL_47 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F0_MODA3 (moda3 + 0x1F0)
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_48 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_49 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_50 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_51 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_52 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_53 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_54 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01F0_MODA3_REG_TEST_DATA_SEL_55 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F4_MODA3 (moda3 + 0x1F4)
    #define REG_01F4_MODA3_REG_TEST_DATA_SEL_56 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01F4_MODA3_REG_TEST_DATA_SEL_57 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01F4_MODA3_REG_TEST_DATA_SEL_58 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F4_MODA3_REG_TEST_DATA_SEL_59 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_01F8_MODA3 (moda3 + 0x1F8)
    #define REG_01F8_MODA3_REG_MOD_A_DUMMY0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_MODA3 (moda3 + 0x1FC)
    #define REG_01FC_MODA3_REG_MOD_A_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]

#endif
