/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)*/
#define TCON_4K 0x488000

//Page TCON_4K
#define REG_0004_TCON_4K (TCON_4K + 0x004)
	#define REG_0004_TCON_4K_REG_4K2K_TCON_0004 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0004_TCON_4K_REG_SUBPIX_MAP_TYPE_0004 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0004_TCON_4K_REG_LTD_ZLOOP_WBLINE_0004 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0008_TCON_4K (TCON_4K + 0x008)
	#define REG_0008_TCON_4K_REG_STRUCTURE_TYPE_0008 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0008_TCON_4K_REG_VLD_BITMAP_WRAP_0008 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0008_TCON_4K_REG_VLD_BITMAP_0008 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_000C_TCON_4K (TCON_4K + 0x00C)
	#define REG_000C_TCON_4K_REG_LB_WR_ADDR_INI_000C Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0010_TCON_4K (TCON_4K + 0x010)
	#define REG_0010_TCON_4K_REG_0SUB_EP1_SEL_0010 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0010_TCON_4K_REG_0SUB_EP0_SEL_0010 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0010_TCON_4K_REG_0SUB_FP1_SEL_0010 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0010_TCON_4K_REG_0SUB_FP0_SEL_0010 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_0014_TCON_4K (TCON_4K + 0x014)
	#define REG_0014_TCON_4K_REG_1SUB_EP1_SEL_0014 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0014_TCON_4K_REG_1SUB_EP0_SEL_0014 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0014_TCON_4K_REG_1SUB_FP1_SEL_0014 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0014_TCON_4K_REG_1SUB_FP0_SEL_0014 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_0018_TCON_4K (TCON_4K + 0x018)
	#define REG_0018_TCON_4K_REG_2SUB_EP1_SEL_0018 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0018_TCON_4K_REG_2SUB_EP0_SEL_0018 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0018_TCON_4K_REG_2SUB_FP1_SEL_0018 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0018_TCON_4K_REG_2SUB_FP0_SEL_0018 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_001C_TCON_4K (TCON_4K + 0x01C)
	#define REG_001C_TCON_4K_REG_SYNC_DELAY_001C Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_001C_TCON_4K_REG_OUT_DE_DELAY_SEL_001C Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_001C_TCON_4K_REG_OUT_DE_DELAY_EN_001C Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_001C_TCON_4K_REG_DRD_SHIFT_NEW_MD_001C Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0020_TCON_4K (TCON_4K + 0x020)
	#define REG_0020_TCON_4K_REG_HDE_SIZE_0020 Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_0024_TCON_4K (TCON_4K + 0x024)
	#define REG_0024_TCON_4K_REG_RBASE0_ADDR_0024 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0028_TCON_4K (TCON_4K + 0x028)
	#define REG_0028_TCON_4K_REG_RBASE1_ADDR_0028 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_002C_TCON_4K (TCON_4K + 0x02C)
	#define REG_002C_TCON_4K_REG_RBASE2_ADDR_002C Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0030_TCON_4K (TCON_4K + 0x030)
	#define REG_0030_TCON_4K_REG_RBASE3_ADDR_0030 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0034_TCON_4K (TCON_4K + 0x034)
	#define REG_0034_TCON_4K_REG_RBASE4_ADDR_0034 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0038_TCON_4K (TCON_4K + 0x038)
	#define REG_0038_TCON_4K_REG_RBASE5_ADDR_0038 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_003C_TCON_4K (TCON_4K + 0x03C)
	#define REG_003C_TCON_4K_REG_RBASEX_LEN_003C Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0040_TCON_4K (TCON_4K + 0x040)
	#define REG_0040_TCON_4K_REG_DUMMY_EP2_SEL_0040 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0040_TCON_4K_REG_ODDEVEN_SWAP_0040 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0040_TCON_4K_REG_VIRTUAL_AS_DUMMY_0040 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0040_TCON_4K_REG_READ_TRIG_SEL_0040 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0040_TCON_4K_REG_RBASEX_WRAP_0040 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0040_TCON_4K_REG_KEEP_BLANKING_DE_OUT_0040 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0040_TCON_4K_REG_BLANKING_MASK_LB_WR_0040 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0040_TCON_4K_REG_BLANKING_MASK_LB_RD_0040 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0040_TCON_4K_REG_DRD_DUMMY_EP2_SEL_0040 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_0044_TCON_4K (TCON_4K + 0x044)
	#define REG_0044_TCON_4K_REG_DUMMY_PIX_DATA_0044 Fld(10, 0, AC_MSKW10)//[9:0]
#define REG_0048_TCON_4K (TCON_4K + 0x048)
	#define REG_0048_TCON_4K_REG_VBLANK_PIX_KEEP_EN_0048 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_004C_TCON_4K (TCON_4K + 0x04C)
	#define REG_004C_TCON_4K_REG_INSERT_FRONT_DUMMY_004C Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_004C_TCON_4K_REG_INSERT_END_DUMMY_004C Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_004C_TCON_4K_REG_INSERT_END_DUMMY_DEC_004C Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_004C_TCON_4K_REG_TCON_4K_POST_RB_SWAP_004C Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_004C_TCON_4K_REG_TCON_4K_POST_OE_SWAP_004C Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0050_TCON_4K (TCON_4K + 0x050)
	#define REG_0050_TCON_4K_REG_FAKE_HSYNC_WID_0050 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0050_TCON_4K_REG_BLK_SAV_POW_0050 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0054_TCON_4K (TCON_4K + 0x054)
	#define REG_0054_TCON_4K_REG_RD_2ND_DE_DLY_0054 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0058_TCON_4K (TCON_4K + 0x058)
	#define REG_0058_TCON_4K_REG_RD_3RD_DE_DLY_0058 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_005C_TCON_4K (TCON_4K + 0x05C)
	#define REG_005C_TCON_4K_REG_FAKE_HSYNC_1_DLY_005C Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0060_TCON_4K (TCON_4K + 0x060)
	#define REG_0060_TCON_4K_REG_FAKE_HSYNC_2_DLY_0060 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0064_TCON_4K (TCON_4K + 0x064)
	#define REG_0064_TCON_4K_REG_DATA0_R_MAP_0064 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0064_TCON_4K_REG_DATA0_G_MAP_0064 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0068_TCON_4K (TCON_4K + 0x068)
	#define REG_0068_TCON_4K_REG_DATA0_B_MAP_0068 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0068_TCON_4K_REG_DATA1_R_MAP_0068 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_006C_TCON_4K (TCON_4K + 0x06C)
	#define REG_006C_TCON_4K_REG_DATA1_G_MAP_006C Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_006C_TCON_4K_REG_DATA1_B_MAP_006C Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0070_TCON_4K (TCON_4K + 0x070)
	#define REG_0070_TCON_4K_REG_DATA2_R_MAP_0070 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0070_TCON_4K_REG_DATA2_G_MAP_0070 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0074_TCON_4K (TCON_4K + 0x074)
	#define REG_0074_TCON_4K_REG_DATA2_B_MAP_0074 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0074_TCON_4K_REG_DATA3_R_MAP_0074 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0078_TCON_4K (TCON_4K + 0x078)
	#define REG_0078_TCON_4K_REG_DATA3_G_MAP_0078 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0078_TCON_4K_REG_DATA3_B_MAP_0078 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_007C_TCON_4K (TCON_4K + 0x07C)
	#define REG_007C_TCON_4K_REG_DATA4_R_MAP_007C Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_007C_TCON_4K_REG_DATA4_G_MAP_007C Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0080_TCON_4K (TCON_4K + 0x080)
	#define REG_0080_TCON_4K_REG_DATA4_B_MAP_0080 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0080_TCON_4K_REG_DATA5_R_MAP_0080 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0084_TCON_4K (TCON_4K + 0x084)
	#define REG_0084_TCON_4K_REG_DATA5_G_MAP_0084 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0084_TCON_4K_REG_DATA5_B_MAP_0084 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0088_TCON_4K (TCON_4K + 0x088)
	#define REG_0088_TCON_4K_REG_DATA6_R_MAP_0088 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0088_TCON_4K_REG_DATA6_G_MAP_0088 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_008C_TCON_4K (TCON_4K + 0x08C)
	#define REG_008C_TCON_4K_REG_DATA6_B_MAP_008C Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_008C_TCON_4K_REG_DATA7_R_MAP_008C Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0090_TCON_4K (TCON_4K + 0x090)
	#define REG_0090_TCON_4K_REG_DATA7_G_MAP_0090 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0090_TCON_4K_REG_DATA7_B_MAP_0090 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_00C0_TCON_4K (TCON_4K + 0x0C0)
	#define REG_00C0_TCON_4K_REG_DRD_1SUB_EP1_SEL_00C0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_00C0_TCON_4K_REG_DRD_1SUB_EP0_SEL_00C0 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00C0_TCON_4K_REG_DRD_1SUB_FP1_SEL_00C0 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_00C0_TCON_4K_REG_DRD_1SUB_FP0_SEL_00C0 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_00C4_TCON_4K (TCON_4K + 0x0C4)
	#define REG_00C4_TCON_4K_REG_DRD_2SUB_EP1_SEL_00C4 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_00C4_TCON_4K_REG_DRD_2SUB_EP0_SEL_00C4 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00C4_TCON_4K_REG_DRD_2SUB_FP1_SEL_00C4 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_00C4_TCON_4K_REG_DRD_2SUB_FP0_SEL_00C4 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_00C8_TCON_4K (TCON_4K + 0x0C8)
	#define REG_00C8_TCON_4K_REG_DRD_0SUB_EP1_SEL_00C8 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_00C8_TCON_4K_REG_DRD_0SUB_EP0_SEL_00C8 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00C8_TCON_4K_REG_DRD_0SUB_FP1_SEL_00C8 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_00C8_TCON_4K_REG_DRD_0SUB_FP0_SEL_00C8 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_00F0_TCON_4K (TCON_4K + 0x0F0)
	#define REG_00F0_TCON_4K_REG_SP_JUMP_POS_00F0 Fld(11, 0, AC_MSKW10)//[10:0]
	#define REG_00F0_TCON_4K_REG_SP_JUMP_FLAG_00F0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_00F0_TCON_4K_REG_SP_JUMP_EN_00F0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00F4_TCON_4K (TCON_4K + 0x0F4)
	#define REG_00F4_TCON_4K_REG_SP_JUMP_DEST_ADDR_00F4 Fld(11, 0, AC_MSKW10)//[10:0]
	#define REG_00F4_TCON_4K_REG_SP_JUMP_DEST_FLAG_00F4 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_00F8_TCON_4K (TCON_4K + 0x0F8)
	#define REG_00F8_TCON_4K_REG_INSERT_FRONT_DUMMY_ADJUST_POSI_00F8 Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_00F8_TCON_4K_REG_INSERT_FRONT_DUMMY_ADJUST_MD_00F8 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_00FC_TCON_4K (TCON_4K + 0x0FC)
	#define REG_00FC_TCON_4K_REG_READ_DLY_00FC Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_00FC_TCON_4K_REG_READ_DLY_EN_00FC Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0100_TCON_4K (TCON_4K + 0x100)
	#define REG_0100_TCON_4K_REG_RBASE6_ADDR_0100 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_0104_TCON_4K (TCON_4K + 0x104)
	#define REG_0104_TCON_4K_REG_RBASE7_ADDR_0104 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_018C_TCON_4K (TCON_4K + 0x18C)
	#define REG_018C_TCON_4K_REG_MAP_PER_LINE_CHG_018C Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_018C_TCON_4K_REG_MAP_MODE_INI_018C Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_018C_TCON_4K_REG_MAP_MODE_VFDE_MASK_018C Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0190_TCON_4K (TCON_4K + 0x190)
	#define REG_0190_TCON_4K_REG_DATA0_R_MAP_MODE1_0190 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0190_TCON_4K_REG_DATA0_G_MAP_MODE1_0190 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0194_TCON_4K (TCON_4K + 0x194)
	#define REG_0194_TCON_4K_REG_DATA0_B_MAP_MODE1_0194 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0194_TCON_4K_REG_DATA1_R_MAP_MODE1_0194 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0198_TCON_4K (TCON_4K + 0x198)
	#define REG_0198_TCON_4K_REG_DATA1_G_MAP_MODE1_0198 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0198_TCON_4K_REG_DATA1_B_MAP_MODE1_0198 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_019C_TCON_4K (TCON_4K + 0x19C)
	#define REG_019C_TCON_4K_REG_DATA2_R_MAP_MODE1_019C Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_019C_TCON_4K_REG_DATA2_G_MAP_MODE1_019C Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01A0_TCON_4K (TCON_4K + 0x1A0)
	#define REG_01A0_TCON_4K_REG_DATA2_B_MAP_MODE1_01A0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01A0_TCON_4K_REG_DATA3_R_MAP_MODE1_01A0 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01A4_TCON_4K (TCON_4K + 0x1A4)
	#define REG_01A4_TCON_4K_REG_DATA3_G_MAP_MODE1_01A4 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01A4_TCON_4K_REG_DATA3_B_MAP_MODE1_01A4 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01A8_TCON_4K (TCON_4K + 0x1A8)
	#define REG_01A8_TCON_4K_REG_DATA4_R_MAP_MODE1_01A8 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01A8_TCON_4K_REG_DATA4_G_MAP_MODE1_01A8 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01AC_TCON_4K (TCON_4K + 0x1AC)
	#define REG_01AC_TCON_4K_REG_DATA4_B_MAP_MODE1_01AC Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01AC_TCON_4K_REG_DATA5_R_MAP_MODE1_01AC Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01B0_TCON_4K (TCON_4K + 0x1B0)
	#define REG_01B0_TCON_4K_REG_DATA5_G_MAP_MODE1_01B0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01B0_TCON_4K_REG_DATA5_B_MAP_MODE1_01B0 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01B4_TCON_4K (TCON_4K + 0x1B4)
	#define REG_01B4_TCON_4K_REG_DATA6_R_MAP_MODE1_01B4 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01B4_TCON_4K_REG_DATA6_G_MAP_MODE1_01B4 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01B8_TCON_4K (TCON_4K + 0x1B8)
	#define REG_01B8_TCON_4K_REG_DATA6_B_MAP_MODE1_01B8 Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01B8_TCON_4K_REG_DATA7_R_MAP_MODE1_01B8 Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01BC_TCON_4K (TCON_4K + 0x1BC)
	#define REG_01BC_TCON_4K_REG_DATA7_G_MAP_MODE1_01BC Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_01BC_TCON_4K_REG_DATA7_B_MAP_MODE1_01BC Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_01C0_TCON_4K (TCON_4K + 0x1C0)
	#define REG_01C0_TCON_4K_REG_GPO_HS_LTD_ONLY_01C0 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_01C4_TCON_4K (TCON_4K + 0x1C4)
	#define REG_01C4_TCON_4K_REG_DUMY_R_01C4 Fld(10, 0, AC_MSKW10)//[9:0]
#define REG_01C8_TCON_4K (TCON_4K + 0x1C8)
	#define REG_01C8_TCON_4K_REG_DUMY_G_01C8 Fld(10, 0, AC_MSKW10)//[9:0]
#define REG_01CC_TCON_4K (TCON_4K + 0x1CC)
	#define REG_01CC_TCON_4K_REG_DUMY_B_01CC Fld(10, 0, AC_MSKW10)//[9:0]
#define REG_01D0_TCON_4K (TCON_4K + 0x1D0)
	#define REG_01D0_TCON_4K_REG_DUMY_FRONT_HDE_MASK_01D0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_01D0_TCON_4K_REG_DUMY_EN_01D0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_01D0_TCON_4K_REG_DUMY_LINE_COLOR_EN_01D0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_01D0_TCON_4K_REG_DUMY_INIT_PTR_TRIG_01D0 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_01D0_TCON_4K_REG_DUMY_H_MIRROR_01D0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_01D0_TCON_4K_REG_DUMY_TOTAL_LB_NUM_01D0 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_01D0_TCON_4K_REG_DUMY_LINE_WORK_ON_VBK_01D0 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_01D0_TCON_4K_REG_DUMY_LB01_REPEAT_01D0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01D4_TCON_4K (TCON_4K + 0x1D4)
	#define REG_01D4_TCON_4K_REG_DUMY_LB_WADR_INI_01D4 Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_01D8_TCON_4K (TCON_4K + 0x1D8)
	#define REG_01D8_TCON_4K_REG_DUMY_INSERT_DUMY_LINE_01D8 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_01D8_TCON_4K_REG_DUMY_VDE_EXTEN_01D8 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_01D8_TCON_4K_REG_DUMY_INIT_RPTR_01D8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_01D8_TCON_4K_REG_DUMY_INIT_WPTR_01D8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01DC_TCON_4K (TCON_4K + 0x1DC)
	#define REG_01DC_TCON_4K_REG_ACC_GAIN_GPO_SEL_01DC Fld(5, 0, AC_MSKB0)//[4:0]
#define REG_01E0_TCON_4K (TCON_4K + 0x1E0)
	#define REG_01E0_TCON_4K_REG_4KTCON_MINI_PATH_01E0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01E0_TCON_4K_REG_OD_MODE_01E0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01E0_TCON_4K_REG_6X2_MODE_01E0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_01E0_TCON_4K_REG_SPLIT_2PAIR_EN_01E0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_01E0_TCON_4K_REG_SPLIT_2PAIR_SWAP_01E0 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_01E4_TCON_4K (TCON_4K + 0x1E4)
	#define REG_01E4_TCON_4K_REG_P2P_CRC_EN_01E4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01E4_TCON_4K_REG_P2P_CRC_CLR_01E4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01E4_TCON_4K_REG_P2P_CRC_ALL_CLR_01E4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_01E4_TCON_4K_REG_P2P_CRC_CH_SEL_01E4 Fld(5, 4, AC_MSKW10)//[8:4]
	#define REG_01E4_TCON_4K_REG_P2P_CRC_ERROR_01E4 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01E8_TCON_4K (TCON_4K + 0x1E8)
	#define REG_01E8_TCON_4K_REG_P2P_CRC_VALUE_01E8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01EC_TCON_4K (TCON_4K + 0x1EC)
	#define REG_01EC_TCON_4K_REG_REPEAT_SHIFT_MODE_LINE0_01EC Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_01F0_TCON_4K (TCON_4K + 0x1F0)
	#define REG_01F0_TCON_4K_REG_SHIFT_MODE_LINE0_01F0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_01F0_TCON_4K_REG_SHIFT_MODE_LINE1_01F0 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_01F0_TCON_4K_REG_SHIFT_MODE_LINE2_01F0 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_01F0_TCON_4K_REG_SHIFT_MODE_LINE3_01F0 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_01F4_TCON_4K (TCON_4K + 0x1F4)
	#define REG_01F4_TCON_4K_REG_SHIFT_MODE_LINE4_01F4 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_01F4_TCON_4K_REG_SHIFT_MODE_LINE5_01F4 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_01F4_TCON_4K_REG_SHIFT_MODE_LINE6_01F4 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_01F4_TCON_4K_REG_SHIFT_MODE_LINE7_01F4 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_01F8_TCON_4K (TCON_4K + 0x1F8)
	#define REG_01F8_TCON_4K_REG_DUMMY0_01F8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01FC_TCON_4K (TCON_4K + 0x1FC)
	#define REG_01FC_TCON_4K_REG_DUMMY1_01FC Fld(16, 0, AC_FULLW10)//[15:0]
