#ifndef _MODV22_H
#define _MODV22_H

#define modv22 0x00485600

//Page MODV22
#define REG_0004_MODV22 (modv22 + 0x004)
    #define REG_0004_MODV22_REG_VBY1_8PTO16P_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_MODV22_REG_VBY1_16PTO32P_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0004_MODV22_REG_VBY1_32PTO64P_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0004_MODV22_REG_VBY1_3D_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0004_MODV22_REG_VBY1_HS_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0004_MODV22_REG_VBY1_LR_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0004_MODV22_REG_VBY1_VS_INV Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0004_MODV22_REG_VBY1_MUTE Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0004_MODV22_REG_VBY1_MUTE_VDB Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0004_MODV22_REG_VBY1_MUTE_UPD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_MODV22 (modv22 + 0x008)
    #define REG_0008_MODV22_REG_FORMAT_MAP Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0008_MODV22_REG_VBY1_16CH_CKEN_31_16 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0008_MODV22_REG_VBY1_16CH_CKEN_47_32 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0008_MODV22_REG_VBY1_16CH_CKEN_63_48 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0018_MODV22 (modv22 + 0x018)
    #define REG_0018_MODV22_REG_VBY1_CRC_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0018_MODV22_REG_VBY1_CRC_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0018_MODV22_REG_VBY1_CRC_ALL_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0018_MODV22_REG_VBY1_CRC_CH_SEL Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_0018_MODV22_REG_VBY1_CRC_ERROR Fld(1,15,AC_MSKB1)//[15:15]
#define REG_001C_MODV22 (modv22 + 0x01C)
    #define REG_001C_MODV22_REG_VBY1_CRC_VALUE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_MODV22 (modv22 + 0x020)
    #define REG_0020_MODV22_REG_META_DATA_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0020_MODV22_REG_META_TEST_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0020_MODV22_REG_META_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0020_MODV22_REG_META_DELAY_AUTO Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0020_MODV22_REG_META_DELAY_NUM Fld(4,8,AC_MSKB1)//[11:8]
#define REG_0024_MODV22 (modv22 + 0x024)
    #define REG_0024_MODV22_REG_META_DATA_NUM Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_MODV22 (modv22 + 0x028)
    #define REG_0028_MODV22_REG_META_HS_SEL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_MODV22 (modv22 + 0x02C)
    #define REG_002C_MODV22_REG_META_DELAY_CHG_CNT Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_002C_MODV22_REG_META_DELAY_CHG_CLR Fld(1,7,AC_MSKB0)//[7:7]
#define REG_0030_MODV22 (modv22 + 0x030)
    #define REG_0030_MODV22_REG_META_REPORT_DELAY Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_MODV22 (modv22 + 0x040)
    #define REG_0040_MODV22_REG_VBY1_CTRL_FIELD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_MODV22 (modv22 + 0x044)
    #define REG_0044_MODV22_REG_VBY1_CTRL_FIELD_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_MODV22 (modv22 + 0x048)
    #define REG_0048_MODV22_REG_VBY1_CTRL_FIELD_2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_004C_MODV22 (modv22 + 0x04C)
    #define REG_004C_MODV22_REG_VBY1_CTRL_FIELD_3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_MODV22 (modv22 + 0x050)
    #define REG_0050_MODV22_REG_VBY1_CTRL_FIELD_4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_MODV22 (modv22 + 0x054)
    #define REG_0054_MODV22_REG_VBY1_CTRL_FIELD_5 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0058_MODV22 (modv22 + 0x058)
    #define REG_0058_MODV22_REG_VBY1_CTRL_FIELD_6 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_005C_MODV22 (modv22 + 0x05C)
    #define REG_005C_MODV22_REG_VBY1_CTRL_FIELD_7 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_MODV22 (modv22 + 0x060)
    #define REG_0060_MODV22_REG_VBY1_CTRL_FIELD_8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_MODV22 (modv22 + 0x064)
    #define REG_0064_MODV22_REG_VBY1_CTRL_FIELD_9 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_MODV22 (modv22 + 0x068)
    #define REG_0068_MODV22_REG_VBY1_CTRL_FIELD_10 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_006C_MODV22 (modv22 + 0x06C)
    #define REG_006C_MODV22_REG_VBY1_CTRL_FIELD_11 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_MODV22 (modv22 + 0x070)
    #define REG_0070_MODV22_REG_VBY1_CTRL_FIELD_12 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_MODV22 (modv22 + 0x074)
    #define REG_0074_MODV22_REG_VBY1_CTRL_FIELD_13 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0078_MODV22 (modv22 + 0x078)
    #define REG_0078_MODV22_REG_VBY1_CTRL_FIELD_14 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_007C_MODV22 (modv22 + 0x07C)
    #define REG_007C_MODV22_REG_VBY1_CTRL_FIELD_15 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0080_MODV22 (modv22 + 0x080)
    #define REG_0080_MODV22_REG_VBY1_CTRL_FIELD_16 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0084_MODV22 (modv22 + 0x084)
    #define REG_0084_MODV22_REG_VBY1_CTRL_FIELD_17 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_MODV22 (modv22 + 0x088)
    #define REG_0088_MODV22_REG_VBY1_CTRL_FIELD_18 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_008C_MODV22 (modv22 + 0x08C)
    #define REG_008C_MODV22_REG_VBY1_CTRL_FIELD_19 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_MODV22 (modv22 + 0x090)
    #define REG_0090_MODV22_REG_VBY1_CTRL_FIELD_20 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0094_MODV22 (modv22 + 0x094)
    #define REG_0094_MODV22_REG_VBY1_CTRL_FIELD_21 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0098_MODV22 (modv22 + 0x098)
    #define REG_0098_MODV22_REG_VBY1_CTRL_FIELD_22 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_009C_MODV22 (modv22 + 0x09C)
    #define REG_009C_MODV22_REG_VBY1_CTRL_FIELD_23 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A0_MODV22 (modv22 + 0x0A0)
    #define REG_00A0_MODV22_REG_VBY1_CTRL_FIELD_24 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_MODV22 (modv22 + 0x0A4)
    #define REG_00A4_MODV22_REG_VBY1_CTRL_FIELD_25 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A8_MODV22 (modv22 + 0x0A8)
    #define REG_00A8_MODV22_REG_VBY1_CTRL_FIELD_26 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00AC_MODV22 (modv22 + 0x0AC)
    #define REG_00AC_MODV22_REG_VBY1_CTRL_FIELD_27 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B0_MODV22 (modv22 + 0x0B0)
    #define REG_00B0_MODV22_REG_VBY1_CTRL_FIELD_28 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B4_MODV22 (modv22 + 0x0B4)
    #define REG_00B4_MODV22_REG_VBY1_CTRL_FIELD_29 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B8_MODV22 (modv22 + 0x0B8)
    #define REG_00B8_MODV22_REG_VBY1_CTRL_FIELD_30 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_MODV22 (modv22 + 0x0BC)
    #define REG_00BC_MODV22_REG_VBY1_CTRL_FIELD_31 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C0_MODV22 (modv22 + 0x0C0)
    #define REG_00C0_MODV22_REG_VBY1_CTRL_FIELD_32 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_MODV22 (modv22 + 0x0C4)
    #define REG_00C4_MODV22_REG_VBY1_CTRL_FIELD_33 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_MODV22 (modv22 + 0x0C8)
    #define REG_00C8_MODV22_REG_VBY1_CTRL_FIELD_34 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_MODV22 (modv22 + 0x0CC)
    #define REG_00CC_MODV22_REG_VBY1_CTRL_FIELD_35 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_MODV22 (modv22 + 0x0D0)
    #define REG_00D0_MODV22_REG_VBY1_CTRL_FIELD_36 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_MODV22 (modv22 + 0x0D4)
    #define REG_00D4_MODV22_REG_VBY1_CTRL_FIELD_37 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_MODV22 (modv22 + 0x0D8)
    #define REG_00D8_MODV22_REG_VBY1_CTRL_FIELD_38 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_MODV22 (modv22 + 0x0DC)
    #define REG_00DC_MODV22_REG_VBY1_CTRL_FIELD_39 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_MODV22 (modv22 + 0x0E0)
    #define REG_00E0_MODV22_REG_VBY1_CTRL_FIELD_40 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_MODV22 (modv22 + 0x0E4)
    #define REG_00E4_MODV22_REG_VBY1_CTRL_FIELD_41 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_MODV22 (modv22 + 0x0E8)
    #define REG_00E8_MODV22_REG_VBY1_CTRL_FIELD_42 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_MODV22 (modv22 + 0x0EC)
    #define REG_00EC_MODV22_REG_VBY1_CTRL_FIELD_43 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_MODV22 (modv22 + 0x0F0)
    #define REG_00F0_MODV22_REG_VBY1_CTRL_FIELD_44 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_MODV22 (modv22 + 0x0F4)
    #define REG_00F4_MODV22_REG_VBY1_CTRL_FIELD_45 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_MODV22 (modv22 + 0x0F8)
    #define REG_00F8_MODV22_REG_VBY1_CTRL_FIELD_46 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00FC_MODV22 (modv22 + 0x0FC)
    #define REG_00FC_MODV22_REG_VBY1_CTRL_FIELD_47 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_MODV22 (modv22 + 0x100)
    #define REG_0100_MODV22_REG_SWAP_BIT_00 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0100_MODV22_REG_SWAP_BIT_01 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0104_MODV22 (modv22 + 0x104)
    #define REG_0104_MODV22_REG_SWAP_BIT_02 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0104_MODV22_REG_SWAP_BIT_03 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0108_MODV22 (modv22 + 0x108)
    #define REG_0108_MODV22_REG_SWAP_BIT_04 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0108_MODV22_REG_SWAP_BIT_05 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_010C_MODV22 (modv22 + 0x10C)
    #define REG_010C_MODV22_REG_SWAP_BIT_06 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_010C_MODV22_REG_SWAP_BIT_07 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0110_MODV22 (modv22 + 0x110)
    #define REG_0110_MODV22_REG_SWAP_BIT_08 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0110_MODV22_REG_SWAP_BIT_09 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0114_MODV22 (modv22 + 0x114)
    #define REG_0114_MODV22_REG_SWAP_BIT_10 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0114_MODV22_REG_SWAP_BIT_11 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0118_MODV22 (modv22 + 0x118)
    #define REG_0118_MODV22_REG_SWAP_BIT_12 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0118_MODV22_REG_SWAP_BIT_13 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_011C_MODV22 (modv22 + 0x11C)
    #define REG_011C_MODV22_REG_SWAP_BIT_14 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_011C_MODV22_REG_SWAP_BIT_15 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0120_MODV22 (modv22 + 0x120)
    #define REG_0120_MODV22_REG_SWAP_BIT_16 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0120_MODV22_REG_SWAP_BIT_17 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0124_MODV22 (modv22 + 0x124)
    #define REG_0124_MODV22_REG_SWAP_BIT_18 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0124_MODV22_REG_SWAP_BIT_19 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0128_MODV22 (modv22 + 0x128)
    #define REG_0128_MODV22_REG_SWAP_BIT_20 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0128_MODV22_REG_SWAP_BIT_21 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_012C_MODV22 (modv22 + 0x12C)
    #define REG_012C_MODV22_REG_SWAP_BIT_22 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_012C_MODV22_REG_SWAP_BIT_23 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0130_MODV22 (modv22 + 0x130)
    #define REG_0130_MODV22_REG_SWAP_BIT_24 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0130_MODV22_REG_SWAP_BIT_25 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0134_MODV22 (modv22 + 0x134)
    #define REG_0134_MODV22_REG_SWAP_BIT_26 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0134_MODV22_REG_SWAP_BIT_27 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0138_MODV22 (modv22 + 0x138)
    #define REG_0138_MODV22_REG_SWAP_BIT_28 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0138_MODV22_REG_SWAP_BIT_29 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_013C_MODV22 (modv22 + 0x13C)
    #define REG_013C_MODV22_REG_SWAP_BIT_30 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_013C_MODV22_REG_SWAP_BIT_31 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0140_MODV22 (modv22 + 0x140)
    #define REG_0140_MODV22_REG_SWAP_BIT_32 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0140_MODV22_REG_SWAP_BIT_33 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0144_MODV22 (modv22 + 0x144)
    #define REG_0144_MODV22_REG_SWAP_BIT_34 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0144_MODV22_REG_SWAP_BIT_35 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0148_MODV22 (modv22 + 0x148)
    #define REG_0148_MODV22_REG_SWAP_BIT_36 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0148_MODV22_REG_SWAP_BIT_37 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_014C_MODV22 (modv22 + 0x14C)
    #define REG_014C_MODV22_REG_SWAP_BIT_38 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_014C_MODV22_REG_SWAP_BIT_39 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0180_MODV22 (modv22 + 0x180)
    #define REG_0180_MODV22_REG_VBY1_ST_MCU Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0180_MODV22_REG_VBY1_STATE Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0180_MODV22_REG_VBY1_CTL_MCU Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0180_MODV22_REG_VBY1_POWER_ON Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0180_MODV22_REG_VBY1_HTPDN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0180_MODV22_REG_VBY1_PLL_LOCK Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0180_MODV22_REG_VBY1_LOCKN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0180_MODV22_REG_VBY1_ENC_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0180_MODV22_REG_VBY1_SCR_ON Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0180_MODV22_REG_VBY1_SCR_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0180_MODV22_REG_VBY1_SCR_RST Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0184_MODV22 (modv22 + 0x184)
    #define REG_0184_MODV22_REG_VBY1_LOCK_VIDEO Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0184_MODV22_REG_VBY1_ALN_DE_CNT Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_0184_MODV22_REG_VBY1_ALN_PIX_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0188_MODV22 (modv22 + 0x188)
    #define REG_0188_MODV22_REG_VBY1_BYTE_MODE Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0188_MODV22_REG_VBY1_PRBS7_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_018C_MODV22 (modv22 + 0x18C)
    #define REG_018C_MODV22_REG_VBY1_TEST_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_018C_MODV22_REG_VBY1_TEST_DATA Fld(10,0,AC_MSKW10)//[9:0]
#define REG_019C_MODV22 (modv22 + 0x19C)
    #define REG_019C_MODV22_REG_VBY1_VS_MATCH Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_019C_MODV22_REG_VBY1_FIFO_RPTR_ALIGN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_019C_MODV22_REG_VBY1_HW_LOCK Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_019C_MODV22_REG_VBY1_HALF_FIFO Fld(1,2,AC_MSKB0)//[2:2]
#define REG_01A0_MODV22 (modv22 + 0x1A0)
    #define REG_01A0_MODV22_REG_VBY1_SWAP_CH00 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01A0_MODV22_REG_VBY1_SWAP_CH01 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01A4_MODV22 (modv22 + 0x1A4)
    #define REG_01A4_MODV22_REG_VBY1_SWAP_CH02 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01A4_MODV22_REG_VBY1_SWAP_CH03 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01A8_MODV22 (modv22 + 0x1A8)
    #define REG_01A8_MODV22_REG_VBY1_SWAP_CH04 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01A8_MODV22_REG_VBY1_SWAP_CH05 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01AC_MODV22 (modv22 + 0x1AC)
    #define REG_01AC_MODV22_REG_VBY1_SWAP_CH06 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01AC_MODV22_REG_VBY1_SWAP_CH07 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01B0_MODV22 (modv22 + 0x1B0)
    #define REG_01B0_MODV22_REG_VBY1_SWAP_CH08 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01B0_MODV22_REG_VBY1_SWAP_CH09 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01B4_MODV22 (modv22 + 0x1B4)
    #define REG_01B4_MODV22_REG_VBY1_SWAP_CH10 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01B4_MODV22_REG_VBY1_SWAP_CH11 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01B8_MODV22 (modv22 + 0x1B8)
    #define REG_01B8_MODV22_REG_VBY1_SWAP_CH12 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01B8_MODV22_REG_VBY1_SWAP_CH13 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01BC_MODV22 (modv22 + 0x1BC)
    #define REG_01BC_MODV22_REG_VBY1_SWAP_CH14 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01BC_MODV22_REG_VBY1_SWAP_CH15 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01C0_MODV22 (modv22 + 0x1C0)
    #define REG_01C0_MODV22_REG_VBY1_SWAP_CH16 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01C0_MODV22_REG_VBY1_SWAP_CH17 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01C4_MODV22 (modv22 + 0x1C4)
    #define REG_01C4_MODV22_REG_VBY1_SWAP_CH18 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01C4_MODV22_REG_VBY1_SWAP_CH19 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01C8_MODV22 (modv22 + 0x1C8)
    #define REG_01C8_MODV22_REG_VBY1_SWAP_CH20 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01C8_MODV22_REG_VBY1_SWAP_CH21 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01CC_MODV22 (modv22 + 0x1CC)
    #define REG_01CC_MODV22_REG_VBY1_SWAP_CH22 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01CC_MODV22_REG_VBY1_SWAP_CH23 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01D0_MODV22 (modv22 + 0x1D0)
    #define REG_01D0_MODV22_REG_VBY1_SWAP_CH24 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01D0_MODV22_REG_VBY1_SWAP_CH25 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01D4_MODV22 (modv22 + 0x1D4)
    #define REG_01D4_MODV22_REG_VBY1_SWAP_CH26 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01D4_MODV22_REG_VBY1_SWAP_CH27 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01D8_MODV22 (modv22 + 0x1D8)
    #define REG_01D8_MODV22_REG_VBY1_SWAP_CH28 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01D8_MODV22_REG_VBY1_SWAP_CH29 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01DC_MODV22 (modv22 + 0x1DC)
    #define REG_01DC_MODV22_REG_VBY1_SWAP_CH30 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_01DC_MODV22_REG_VBY1_SWAP_CH31 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01F0_MODV22 (modv22 + 0x1F0)
    #define REG_01F0_MODV22_REG_VBY1_FSM_TRACER_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_01F0_MODV22_REG_VBY1_FSM_TRACER_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01F0_MODV22_REG_VBY1_FSM_TRACER_STATE Fld(3,0,AC_MSKB0)//[2:0]
#define REG_01F8_MODV22 (modv22 + 0x1F8)
    #define REG_01F8_MODV22_REG_UNLOCK_CNT_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01F8_MODV22_REG_UNLOCK_CNT Fld(7,0,AC_MSKB0)//[6:0]
#define REG_01FC_MODV22 (modv22 + 0x1FC)
    #define REG_01FC_MODV22_REG_VBY1_HTPDN_VIDEO_R Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_01FC_MODV22_REG_VBY1_LOCKN_VIDEO_R Fld(1,4,AC_MSKB0)//[4:4]

#endif
