// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Copyright (c) 2020 MediaTek Inc.
 * Author Kevin Ho <kevin-yc.ho@mediatek.com>
 */

#ifndef _DT_BINDINGS_PINCTRL_MT5896_H
#define _DT_BINDINGS_PINCTRL_MT5896_H

/* pad mux: pin function value: vale */
#define PMUX_FUNC_0 0x0
#define PMUX_FUNC_1 0x1
#define PMUX_FUNC_2 0x2
#define PMUX_FUNC_3 0x3
#define PMUX_FUNC_4 0x4
#define PMUX_FUNC_5 0x5
#define PMUX_FUNC_6 0x6
#define PMUX_FUNC_7 0x7
#define PMUX_FUNC_8 0x8
#define PMUX_FUNC_9 0x9

/* pad mux: pin and offset mapping: offset/bitmask */
#define PMUX_PAD_GPIO0 0x00 0x0f
#define PMUX_PAD_GPIO1 0x00 0xf0
#define PMUX_PAD_GPIO2 0x01 0x0f
#define PMUX_PAD_GPIO3 0x01 0xf0
#define PMUX_PAD_GPIO4 0x04 0x0f
#define PMUX_PAD_GPIO5 0x04 0xf0
#define PMUX_PAD_GPIO6 0x05 0x0f
#define PMUX_PAD_GPIO7 0x05 0xf0
#define PMUX_PAD_GPIO8 0x08 0x0f
#define PMUX_PAD_GPIO9 0x08 0xf0
#define PMUX_PAD_GPIO10 0x09 0x0f
#define PMUX_PAD_I2SOUT_MCLK_A 0x09 0xf0
#define PMUX_PAD_I2SOUT_WS_A 0x0C 0x0f
#define PMUX_PAD_I2SOUT_BCK_A 0x0C 0xf0
#define PMUX_PAD_I2SOUT_SD0_A 0x0D 0x0f
#define PMUX_PAD_I2SOUT_SD1_A 0x0D 0xf0
#define PMUX_PAD_I2SOUT_SD2_A 0x010 0x0f
#define PMUX_PAD_I2SOUT_SD3_A 0x010 0xf0
#define PMUX_PAD_I2SOUT_SD4_A 0x011 0x0f
#define PMUX_PAD_I2SIN_WS_A 0x011 0xf0
#define PMUX_PAD_I2SOUT_SD5_A 0x014 0x0f
#define PMUX_PAD_I2SOUT_MCLK_B 0x014 0xf0
#define PMUX_PAD_I2SOUT_WS_B 0x015 0x0f
#define PMUX_PAD_I2SOUT_BCK_B 0x015 0xf0
#define PMUX_PAD_I2SOUT_SD0_B 0x018 0x0f
#define PMUX_PAD_I2SIN_BCK_A 0x018 0xf0
#define PMUX_PAD_I2SIN_SD0_A 0x019 0x0f
#define PMUX_PAD_I2SIN_MCLK_A 0x019 0xf0
#define PMUX_PAD_I2SIN_SD1_A 0x01C 0x0f
#define PMUX_PAD_I2SIN_SD2_A 0x01C 0xf0
#define PMUX_PAD_I2SIN_SD3_A 0x01D 0x0f
#define PMUX_PAD_I2SIN_MCLK_B 0x01D 0xf0
#define PMUX_PAD_I2SIN_BCK_B 0x20 0x0f
#define PMUX_PAD_I2SIN_WS_B 0x20 0xf0
#define PMUX_PAD_I2SIN_SD0_B 0x21 0x0f
#define PMUX_PAD_AU_SPI_CK 0x21 0xf0
#define PMUX_PAD_AU_SPI_MOSI 0x24 0x0f
#define PMUX_PAD_AU_SPI_MISO 0x24 0xf0
#define PMUX_PAD_AU_SPI_CS0 0x25 0x0f
#define PMUX_PAD_AU_SPI_CS1 0x25 0xf0
#define PMUX_PAD_AU_SPI_CS2 0x28 0x0f
#define PMUX_PAD_AU_SPI_CS3 0x28 0xf0
#define PMUX_PAD_GPIO42 0x29 0x0f
#define PMUX_PAD_GPIO43 0x29 0xf0
#define PMUX_PAD_GPIO44 0x2C 0x0f
#define PMUX_PAD_GPIO45 0x2C 0xf0
#define PMUX_PAD_GPIO46 0x2D 0x0f
#define PMUX_PAD_GPIO47 0x2D 0xf0
#define PMUX_PAD_GPIO48 0x30 0x0f
#define PMUX_PAD_VB1_HTPDN_V1 0x30 0xf0
#define PMUX_PAD_VB1_LOCKN_V1 0x31 0x0f
#define PMUX_PAD_VB1_HTPDN_V2 0x31 0xf0
#define PMUX_PAD_VB1_LOCKN_V2 0x34 0x0f
#define PMUX_PAD_VB1_LOCKN_OSD 0x34 0xf0
#define PMUX_PAD_VB1_HTPDN_OSD 0x35 0x0f
#define PMUX_PAD_GPIO55 0x35 0xf0
#define PMUX_PAD_GPIO56 0x38 0x0f
#define PMUX_PAD_GPIO57 0x38 0xf0
#define PMUX_PAD_GPIO58 0x39 0x0f
#define PMUX_PAD_GPIO59 0x39 0xf0
#define PMUX_PAD_GPIO60 0x3C 0x0f
#define PMUX_PAD_GPIO61 0x3C 0xf0
#define PMUX_PAD_GPIO62 0x3D 0x0f
#define PMUX_PAD_GPIO63 0x3D 0xf0
#define PMUX_PAD_GPIO64 0x40 0x0f
#define PMUX_PAD_GPIO65 0x40 0xf0
#define PMUX_PAD_TUNER_FREEZE_SEQ 0x41 0x0f
#define PMUX_PAD_GPIO67 0x41 0xf0
#define PMUX_PAD_GPIO68 0x44 0x0f
#define PMUX_PAD_GPIO69 0x44 0xf0
#define PMUX_PAD_GPIO70 0x45 0x0f
#define PMUX_PAD_GPIO71 0x45 0xf0
#define PMUX_PAD_GPIO72 0x48 0x0f
#define PMUX_PAD_OSDA0 0x48 0xf0
#define PMUX_PAD_OSCL0 0x49 0x0f
#define PMUX_PAD_OSDA1 0x49 0xf0
#define PMUX_PAD_OSCL1 0x4C 0x0f
#define PMUX_PAD_OSCL3 0x4C 0xf0
#define PMUX_PAD_OSDA3 0x4D 0x0f
#define PMUX_PAD_SPI_CLK 0x4D 0xf0
#define PMUX_PAD_SPI_MOSI 0x50 0x0f
#define PMUX_PAD_SPI_MISO 0x50 0xf0
#define PMUX_PAD_SPI_CS 0x51 0x0f
#define PMUX_PAD_INT 0x51 0xf0
#define PMUX_PAD_CIL_DEMOD0_CLK 0x54 0x0f
#define PMUX_PAD_CIL_TX_CLK 0x54 0xf0
#define PMUX_PAD_CIL_TX0_D0 0x55 0x0f
#define PMUX_PAD_CIL_TX0_D1 0x55 0xf0
#define PMUX_PAD_CIL_RX_CLK 0x58 0x0f
#define PMUX_PAD_CIL_RX0_D0 0x58 0xf0
#define PMUX_PAD_CIL_RX0_D1 0x59 0x0f
#define PMUX_PAD_CIL_DEMOD1_CLK 0x59 0xf0
#define PMUX_PAD_CIL_TX1_D0 0x5C 0x0f
#define PMUX_PAD_CIL_TX1_D1 0x5C 0xf0
#define PMUX_PAD_CIL_RX1_D0 0x5D 0x0f
#define PMUX_PAD_CIL_RX1_D1 0x5D 0xf0
#define PMUX_PAD_CI_RESET 0x60 0x0f
#define PMUX_PAD_DEMOD_RST 0x60 0xf0
#define PMUX_PAD_DEMOD_TSCLK 0x61 0x0f
#define PMUX_PAD_DEMOD_TSVAL 0x61 0xf0
#define PMUX_PAD_DEMOD_TSSYNC 0x64 0x0f
#define PMUX_PAD_DEMOD_TSDATA0 0x64 0xf0
#define PMUX_PAD_DEMOD_TSDATA1 0x65 0x0f
#define PMUX_PAD_DEMOD_TSDATA2 0x65 0xf0
#define PMUX_PAD_DEMOD_TSDATA3 0x68 0x0f
#define PMUX_PAD_DEMOD_TSDATA4 0x68 0xf0
#define PMUX_PAD_DEMOD_TSDATA5 0x69 0x0f
#define PMUX_PAD_DEMOD_TSDATA6 0x69 0xf0
#define PMUX_PAD_DEMOD_TSDATA7 0x6C 0x0f
#define PMUX_PAD_DEMOD_TS2_VAL 0x6C 0xf0
#define PMUX_PAD_DEMOD_TS2_SYNC 0x6D 0x0f
#define PMUX_PAD_DEMOD_TS2_D0 0x6D 0xf0
#define PMUX_PAD_DEMOD_TS2_CLK 0x70 0x0f
#define PMUX_PAD_EMMC_RST 0x70 0xf0
#define PMUX_PAD_EMMC_CLK 0x71 0x0f
#define PMUX_PAD_EMMC_DS 0x71 0xf0
#define PMUX_PAD_EMMC_CMD 0x74 0x0f
#define PMUX_PAD_EMMC_D0 0x74 0xf0
#define PMUX_PAD_EMMC_D1 0x75 0x0f
#define PMUX_PAD_EMMC_D2 0x75 0xf0
#define PMUX_PAD_EMMC_D3 0x78 0x0f
#define PMUX_PAD_EMMC_D4 0x78 0xf0
#define PMUX_PAD_EMMC_D5 0x79 0x0f
#define PMUX_PAD_EMMC_D6 0x79 0xf0
#define PMUX_PAD_EMMC_D7 0x7C 0x0f
#define PMUX_PAD_USB_DM_P0 0x7C 0xf0
#define PMUX_PAD_USB_DP_P0 0x7D 0x0f
#define PMUX_PAD_USB_DM_P1 0x7D 0xf0
#define PMUX_PAD_USB_DP_P1 0x80 0x0f
#define PMUX_PAD_USB_DM_P3 0x80 0xf0
#define PMUX_PAD_USB_DP_P3 0x81 0x0f
#define PMUX_PAD_ASPDIFI 0x81 0xf0
#define PMUX_PAD_ASPDIFO0 0x84 0x0f
#define PMUX_PAD_U1RX 0x84 0xf0
#define PMUX_PAD_U1TX 0x85 0x0f
#define PMUX_PAD_OSDA2 0x85 0xf0
#define PMUX_PAD_OSCL2 0x88 0x0f
#define PMUX_PAD_DISEQC_OUT_DIG 0x88 0xf0
#define PMUX_PAD_DISEQC_IN_DIG 0x89 0x0f

/* pad mux: pm domain pin and offset mapping: offset/bitmask */
#define PMUX_PM_PAD_OPCTRL0 0x00 0x0f
#define PMUX_PM_PAD_OPCTRL1 0x00 0xf0
#define PMUX_PM_PAD_OPCTRL2 0x01 0x0f
#define PMUX_PM_PAD_OPCTRL3 0x01 0xf0
#define PMUX_PM_PAD_OPCTRL4 0x04 0x0f
#define PMUX_PM_PAD_OPCTRL5 0x04 0xf0
#define PMUX_PM_PAD_OPCTRL6 0x05 0x0f
#define PMUX_PM_PAD_OPCTRL7 0x05 0xf0
#define PMUX_PM_PAD_OPCTRL8 0x08 0x0f
#define PMUX_PM_PAD_OPCTRL9 0x08 0xf0
#define PMUX_PM_PAD_OPCTRL10 0x09 0x0f
#define PMUX_PM_PAD_OPCTRL11 0x09 0xf0
#define PMUX_PM_PAD_OPCTRL12 0x0C 0x0f
#define PMUX_PM_PAD_OPCTRL13 0x0C 0xf0
#define PMUX_PM_PAD_OPCTRL14 0x0D 0x0f
#define PMUX_PM_PAD_OPCTRL15 0x0D 0xf0
#define PMUX_PM_PAD_OPCTRL16 0x010 0x0f
#define PMUX_PM_PAD_OPCTRL17 0x010 0xf0
#define PMUX_PM_PAD_OPCTRL18 0x011 0x0f
#define PMUX_PM_PAD_OPCTRL19 0x011 0xf0
#define PMUX_PM_PAD_OPCTRL20 0x014 0x0f
#define PMUX_PM_PAD_OPCTRL21 0x014 0xf0
#define PMUX_PM_PAD_OPCTRL22 0x015 0x0f
#define PMUX_PM_PAD_U2TX 0x015 0xf0
#define PMUX_PM_PAD_U2RX 0x018 0x0f
#define PMUX_PM_PAD_DDCA_DA 0x018 0xf0
#define PMUX_PM_PAD_DDCA_CK 0x019 0x0f
#define PMUX_PM_PAD_PWR_CTRL 0x019 0xf0
#define PMUX_PM_PAD_IRIN 0x01C 0x0f
#define PMUX_PM_PAD_LED_PWM0 0x01C 0xf0
#define PMUX_PM_PAD_LED_PWM1 0x01D 0x0f
#define PMUX_PM_PAD_LED_PWM2 0x01D 0xf0
#define PMUX_PM_PAD_LED_PWM3 0x20 0x0f
#define PMUX_PM_PAD_PHYLED0 0x20 0xf0
#define PMUX_PM_PAD_PHYLED1 0x21 0x0f
#define PMUX_PM_PAD_HDMI_CEC 0x21 0xf0
#define PMUX_PM_PAD_HDMI_A_HPD 0x24 0x0f
#define PMUX_PM_PAD_HDMI_A_PWR5V 0x24 0xf0
#define PMUX_PM_PAD_HDMI_A_SDA 0x25 0x0f
#define PMUX_PM_PAD_HDMI_A_SCL 0x25 0xf0
#define PMUX_PM_PAD_HDMI_B_HPD 0x28 0x0f
#define PMUX_PM_PAD_HDMI_B_PWR5V 0x28 0xf0
#define PMUX_PM_PAD_HDMI_B_SDA 0x29 0x0f
#define PMUX_PM_PAD_HDMI_B_SCL 0x29 0xf0
#define PMUX_PM_PAD_HDMI_C_HPD 0x2C 0x0f
#define PMUX_PM_PAD_HDMI_C_PWR5V 0x2C 0xf0
#define PMUX_PM_PAD_HDMI_C_SDA 0x2D 0x0f
#define PMUX_PM_PAD_HDMI_C_SCL 0x2D 0xf0
#define PMUX_PM_PAD_HDMI_D_HPD 0x30 0x0f
#define PMUX_PM_PAD_HDMI_D_PWR5V 0x30 0xf0
#define PMUX_PM_PAD_HDMI_D_SDA 0x31 0x0f
#define PMUX_PM_PAD_HDMI_D_SCL 0x31 0xf0
#define PMUX_PM_PAD_SAR0 0x34 0x0f
#define PMUX_PM_PAD_SAR1 0x34 0xf0
#define PMUX_PM_PAD_SAR2 0x35 0x0f
#define PMUX_PM_PAD_SAR3 0x35 0xf0
#define PMUX_PM_PAD_SAR4 0x38 0x0f
#define PMUX_PM_PAD_SAR5 0x38 0xf0
#define PMUX_PM_PAD_SAR6 0x39 0x0f
#define PMUX_PM_PAD_SAR7 0x39 0xf0
#define PMUX_PM_PAD_SAR8 0x3C 0x0f
#define PMUX_PM_PAD_SAR9 0x3C 0xf0
#define PMUX_PM_PAD_I2C_TU_SDA 0x3D 0x0f
#define PMUX_PM_PAD_I2C_TU_SCL 0x3D 0xf0
#define PMUX_PM_PAD_MIC_BCK 0x40 0x0f
#define PMUX_PM_PAD_MIC_SD0 0x40 0xf0
#define PMUX_PM_PAD_MIC_SD1 0x41 0x0f
#define PMUX_PM_PAD_USB_DM_P2 0x41 0xf0
#define PMUX_PM_PAD_USB_DP_P2 0x44 0x0f
#define PMUX_PM_PAD_PMU_RSTCTL 0x44 0xf0
#define PMUX_PM_PAD_PMU_BL_ON 0x45 0x0f
#define PMUX_PM_PAD_PMU_P_HL 0x45 0xf0
#define PMUX_PM_PAD_PMU_P_ON1 0x48 0x0f
#define PMUX_PM_PAD_PMU_P_ON2 0x48 0xf0
#define PMUX_PM_PAD_RGMII_TXCTL 0x49 0x0f
#define PMUX_PM_PAD_RGMII_TXC 0x49 0xf0
#define PMUX_PM_PAD_RGMII_TXD0 0x4C 0x0f
#define PMUX_PM_PAD_RGMII_TXD1 0x4C 0xf0
#define PMUX_PM_PAD_RGMII_TXD2 0x4D 0x0f
#define PMUX_PM_PAD_RGMII_TXD3 0x4D 0xf0
#define PMUX_PM_PAD_RGMII_RXC 0x50 0x0f
#define PMUX_PM_PAD_RGMII_RXCTL 0x50 0xf0
#define PMUX_PM_PAD_RGMII_RXD0 0x51 0x0f
#define PMUX_PM_PAD_RGMII_RXD1 0x51 0xf0
#define PMUX_PM_PAD_RGMII_RXD2 0x54 0x0f
#define PMUX_PM_PAD_RGMII_RXD3 0x54 0xf0
#define PMUX_PM_PAD_RGMII_MDC 0x55 0x0f
#define PMUX_PM_PAD_RGMII_MDIO 0x55 0xf0
#define PMUX_PM_PAD_RGMII_RESET 0x58 0x0f
#define PMUX_PM_PAD_RGMII_PMEB 0x58 0xf0
#define PMUX_PM_PAD_PCIE2_WAKEN 0x59 0x0f
#define PMUX_PM_PAD_PCIE2_PERSTB 0x59 0xf0
#define PMUX_PM_PAD_PCIE2_PWR_CTL 0x5C 0x0f
#define PMUX_PM_PAD_PCIE2_CLKREQN 0x5C 0xf0
#define PMUX_PM_PAD_BOOTUP_NOTE 0x5D 0x0f
#define PMUX_PM_PAD_U3RX 0x5D 0xf0
#define PMUX_PM_PAD_U3TX 0x60 0x0f

/* pad conf: driving: bitmask/value */
#define PCONF_DRV_2MA	0x07 0x00
#define PCONF_DRV_4MA	0x07 0x01
#define PCONF_DRV_6MA	0x07 0x02
#define PCONF_DRV_8MA	0x07 0x03
#define PCONF_DRV_10MA	0x07 0x04
#define PCONF_DRV_12MA	0x07 0x05
#define PCONF_DRV_14MA	0x07 0x06
#define PCONF_DRV_16MA	0x07 0x07

/* pad conf: bias pull down/up: bitmask/value */
#define PCONF_BIAS_HIZ		0x18 0x00
#define PCONF_BIAS_PULLUP	0x18 0x08
#define PCONF_BIAS_PULLDOWN	0x18 0x10

/* pad conf: pin and offset mapping: offset */
#define PCONF_PAD_GPIO0 0x000
#define PCONF_PAD_GPIO1 0x008
#define PCONF_PAD_GPIO2 0x010
#define PCONF_PAD_GPIO3 0x018
#define PCONF_PAD_GPIO4 0x020
#define PCONF_PAD_GPIO5 0x028
#define PCONF_PAD_GPIO6 0x030
#define PCONF_PAD_GPIO7 0x038
#define PCONF_PAD_GPIO8 0x040
#define PCONF_PAD_GPIO9 0x048
#define PCONF_PAD_GPIO10 0x050
#define PCONF_PAD_I2SOUT_MCLK_A 0x058
#define PCONF_PAD_I2SOUT_WS_A 0x060
#define PCONF_PAD_I2SOUT_BCK_A 0x068
#define PCONF_PAD_I2SOUT_SD0_A 0x070
#define PCONF_PAD_I2SOUT_SD1_A 0x078
#define PCONF_PAD_I2SOUT_SD2_A 0x080
#define PCONF_PAD_I2SOUT_SD3_A 0x088
#define PCONF_PAD_I2SOUT_SD4_A 0x090
#define PCONF_PAD_I2SIN_WS_A 0x098
#define PCONF_PAD_I2SOUT_SD5_A 0x0A0
#define PCONF_PAD_I2SOUT_MCLK_B 0x0A8
#define PCONF_PAD_I2SOUT_WS_B 0x0B0
#define PCONF_PAD_I2SOUT_BCK_B 0x0B8
#define PCONF_PAD_I2SOUT_SD0_B 0x0C0
#define PCONF_PAD_I2SIN_BCK_A 0x0C8
#define PCONF_PAD_I2SIN_SD0_A 0x0D0
#define PCONF_PAD_I2SIN_MCLK_A 0x0D8
#define PCONF_PAD_I2SIN_SD1_A 0x0E0
#define PCONF_PAD_I2SIN_SD2_A 0x0E8
#define PCONF_PAD_I2SIN_SD3_A 0x0F0
#define PCONF_PAD_I2SIN_MCLK_B 0x0F8
#define PCONF_PAD_I2SIN_BCK_B 0x100
#define PCONF_PAD_I2SIN_WS_B 0x108
#define PCONF_PAD_I2SIN_SD0_B 0x110
#define PCONF_PAD_AU_SPI_CK 0x118
#define PCONF_PAD_AU_SPI_MOSI 0x120
#define PCONF_PAD_AU_SPI_MISO 0x128
#define PCONF_PAD_AU_SPI_CS0 0x130
#define PCONF_PAD_AU_SPI_CS1 0x138
#define PCONF_PAD_AU_SPI_CS2 0x140
#define PCONF_PAD_AU_SPI_CS3 0x148
#define PCONF_PAD_GPIO42 0x150
#define PCONF_PAD_GPIO43 0x158
#define PCONF_PAD_GPIO44 0x160
#define PCONF_PAD_GPIO45 0x168
#define PCONF_PAD_GPIO46 0x170
#define PCONF_PAD_GPIO47 0x178
#define PCONF_PAD_GPIO48 0x180
#define PCONF_PAD_VB1_HTPDN_V1 0x188
#define PCONF_PAD_VB1_LOCKN_V1 0x190
#define PCONF_PAD_VB1_HTPDN_V2 0x198
#define PCONF_PAD_VB1_LOCKN_V2 0x1A0
#define PCONF_PAD_VB1_LOCKN_OSD 0x1A8
#define PCONF_PAD_VB1_HTPDN_OSD 0x1B0
#define PCONF_PAD_GPIO55 0x1B8
#define PCONF_PAD_GPIO56 0x1C0
#define PCONF_PAD_GPIO57 0x1C8
#define PCONF_PAD_GPIO58 0x1D0
#define PCONF_PAD_GPIO59 0x1D8
#define PCONF_PAD_GPIO60 0x1E0
#define PCONF_PAD_GPIO61 0x1E8
#define PCONF_PAD_GPIO62 0x1F0
#define PCONF_PAD_GPIO63 0x1F8
#define PCONF_PAD_GPIO64 0x200
#define PCONF_PAD_GPIO65 0x208
#define PCONF_PAD_TUNER_FREEZE_SEQ 0x210
#define PCONF_PAD_GPIO67 0x218
#define PCONF_PAD_GPIO68 0x220
#define PCONF_PAD_GPIO69 0x228
#define PCONF_PAD_GPIO70 0x230
#define PCONF_PAD_GPIO71 0x238
#define PCONF_PAD_GPIO72 0x240
#define PCONF_PAD_OSDA0 0x248
#define PCONF_PAD_OSCL0 0x250
#define PCONF_PAD_OSDA1 0x258
#define PCONF_PAD_OSCL1 0x260
#define PCONF_PAD_OSCL3 0x268
#define PCONF_PAD_OSDA3 0x270
#define PCONF_PAD_SPI_CLK 0x278
#define PCONF_PAD_SPI_MOSI 0x280
#define PCONF_PAD_SPI_MISO 0x288
#define PCONF_PAD_SPI_CS 0x290
#define PCONF_PAD_INT 0x298
#define PCONF_PAD_CIL_DEMOD0_CLK 0x2A0
#define PCONF_PAD_CIL_TX_CLK 0x2A8
#define PCONF_PAD_CIL_TX0_D0 0x2B0
#define PCONF_PAD_CIL_TX0_D1 0x2B8
#define PCONF_PAD_CIL_RX_CLK 0x2C0
#define PCONF_PAD_CIL_RX0_D0 0x2C8
#define PCONF_PAD_CIL_RX0_D1 0x2D0
#define PCONF_PAD_CIL_DEMOD1_CLK 0x2D8
#define PCONF_PAD_CIL_TX1_D0 0x2E0
#define PCONF_PAD_CIL_TX1_D1 0x2E8
#define PCONF_PAD_CIL_RX1_D0 0x2F0
#define PCONF_PAD_CIL_RX1_D1 0x2F8
#define PCONF_PAD_CI_RESET 0x300
#define PCONF_PAD_DEMOD_RST 0x308
#define PCONF_PAD_DEMOD_TSCLK 0x310
#define PCONF_PAD_DEMOD_TSVAL 0x318
#define PCONF_PAD_DEMOD_TSSYNC 0x320
#define PCONF_PAD_DEMOD_TSDATA0 0x328
#define PCONF_PAD_DEMOD_TSDATA1 0x330
#define PCONF_PAD_DEMOD_TSDATA2 0x338
#define PCONF_PAD_DEMOD_TSDATA3 0x340
#define PCONF_PAD_DEMOD_TSDATA4 0x348
#define PCONF_PAD_DEMOD_TSDATA5 0x350
#define PCONF_PAD_DEMOD_TSDATA6 0x358
#define PCONF_PAD_DEMOD_TSDATA7 0x360
#define PCONF_PAD_DEMOD_TS2_VAL 0x368
#define PCONF_PAD_DEMOD_TS2_SYNC 0x370
#define PCONF_PAD_DEMOD_TS2_D0 0x378
#define PCONF_PAD_DEMOD_TS2_CLK 0x380
#define PCONF_PAD_EMMC_RST 0x388
#define PCONF_PAD_EMMC_CLK 0x390
#define PCONF_PAD_EMMC_DS 0x398
#define PCONF_PAD_EMMC_CMD 0x3A0
#define PCONF_PAD_EMMC_D0 0x3A8
#define PCONF_PAD_EMMC_D1 0x3B0
#define PCONF_PAD_EMMC_D2 0x3B8
#define PCONF_PAD_EMMC_D3 0x3C0
#define PCONF_PAD_EMMC_D4 0x3C8
#define PCONF_PAD_EMMC_D5 0x3D0
#define PCONF_PAD_EMMC_D6 0x3D8
#define PCONF_PAD_EMMC_D7 0x3E0
#define PCONF_PAD_USB_DM_P0 0x3E8
#define PCONF_PAD_USB_DP_P0 0x3F0
#define PCONF_PAD_USB_DM_P1 0x3F8
#define PCONF_PAD_USB_DP_P1 0x400
#define PCONF_PAD_USB_DM_P3 0x408
#define PCONF_PAD_USB_DP_P3 0x410
#define PCONF_PAD_ASPDIFI 0x418
#define PCONF_PAD_ASPDIFO0 0x420
#define PCONF_PAD_U1RX 0x428
#define PCONF_PAD_U1TX 0x430
#define PCONF_PAD_OSDA2 0x438
#define PCONF_PAD_OSCL2 0x440
#define PCONF_PAD_DISEQC_OUT_DIG 0x448
#define PCONF_PAD_DISEQC_IN_DIG 0x450

/* pad conf: pm domain pin and offset mapping: offset */
#define PCONF_PM_PAD_OPCTRL0 0x000
#define PCONF_PM_PAD_OPCTRL1 0x008
#define PCONF_PM_PAD_OPCTRL2 0x010
#define PCONF_PM_PAD_OPCTRL3 0x018
#define PCONF_PM_PAD_OPCTRL4 0x020
#define PCONF_PM_PAD_OPCTRL5 0x028
#define PCONF_PM_PAD_OPCTRL6 0x030
#define PCONF_PM_PAD_OPCTRL7 0x038
#define PCONF_PM_PAD_OPCTRL8 0x040
#define PCONF_PM_PAD_OPCTRL9 0x048
#define PCONF_PM_PAD_OPCTRL10 0x050
#define PCONF_PM_PAD_OPCTRL11 0x058
#define PCONF_PM_PAD_OPCTRL12 0x060
#define PCONF_PM_PAD_OPCTRL13 0x068
#define PCONF_PM_PAD_OPCTRL14 0x070
#define PCONF_PM_PAD_OPCTRL15 0x078
#define PCONF_PM_PAD_OPCTRL16 0x080
#define PCONF_PM_PAD_OPCTRL17 0x088
#define PCONF_PM_PAD_OPCTRL18 0x090
#define PCONF_PM_PAD_OPCTRL19 0x098
#define PCONF_PM_PAD_OPCTRL20 0x0A0
#define PCONF_PM_PAD_OPCTRL21 0x0A8
#define PCONF_PM_PAD_OPCTRL22 0x0B0
#define PCONF_PM_PAD_U2TX 0x0B8
#define PCONF_PM_PAD_U2RX 0x0C0
#define PCONF_PM_PAD_DDCA_DA 0x0C8
#define PCONF_PM_PAD_DDCA_CK 0x0D0
#define PCONF_PM_PAD_PWR_CTRL 0x0D8
#define PCONF_PM_PAD_IRIN 0x0E0
#define PCONF_PM_PAD_LED_PWM0 0x0E8
#define PCONF_PM_PAD_LED_PWM1 0x0F0
#define PCONF_PM_PAD_LED_PWM2 0x0F8
#define PCONF_PM_PAD_LED_PWM3 0x100
#define PCONF_PM_PAD_PHYLED0 0x108
#define PCONF_PM_PAD_PHYLED1 0x110
#define PCONF_PM_PAD_HDMI_CEC 0x118
#define PCONF_PM_PAD_HDMI_A_HPD 0x120
#define PCONF_PM_PAD_HDMI_A_PWR5V 0x128
#define PCONF_PM_PAD_HDMI_A_SDA 0x130
#define PCONF_PM_PAD_HDMI_A_SCL 0x138
#define PCONF_PM_PAD_HDMI_B_HPD 0x140
#define PCONF_PM_PAD_HDMI_B_PWR5V 0x148
#define PCONF_PM_PAD_HDMI_B_SDA 0x150
#define PCONF_PM_PAD_HDMI_B_SCL 0x158
#define PCONF_PM_PAD_HDMI_C_HPD 0x160
#define PCONF_PM_PAD_HDMI_C_PWR5V 0x168
#define PCONF_PM_PAD_HDMI_C_SDA 0x170
#define PCONF_PM_PAD_HDMI_C_SCL 0x178
#define PCONF_PM_PAD_HDMI_D_HPD 0x180
#define PCONF_PM_PAD_HDMI_D_PWR5V 0x188
#define PCONF_PM_PAD_HDMI_D_SDA 0x190
#define PCONF_PM_PAD_HDMI_D_SCL 0x198
#define PCONF_PM_PAD_SAR0 0x1A0
#define PCONF_PM_PAD_SAR1 0x1A8
#define PCONF_PM_PAD_SAR2 0x1B0
#define PCONF_PM_PAD_SAR3 0x1B8
#define PCONF_PM_PAD_SAR4 0x1C0
#define PCONF_PM_PAD_SAR5 0x1C8
#define PCONF_PM_PAD_SAR6 0x1D0
#define PCONF_PM_PAD_SAR7 0x1D8
#define PCONF_PM_PAD_SAR8 0x1E0
#define PCONF_PM_PAD_SAR9 0x1E8
#define PCONF_PM_PAD_I2C_TU_SDA 0x1F0
#define PCONF_PM_PAD_I2C_TU_SCL 0x1F8
#define PCONF_PM_PAD_MIC_BCK 0x200
#define PCONF_PM_PAD_MIC_SD0 0x208
#define PCONF_PM_PAD_MIC_SD1 0x210
#define PCONF_PM_PAD_USB_DM_P2 0x218
#define PCONF_PM_PAD_USB_DP_P2 0x220
#define PCONF_PM_PAD_PMU_RSTCTL 0x228
#define PCONF_PM_PAD_PMU_BL_ON 0x230
#define PCONF_PM_PAD_PMU_P_HL 0x238
#define PCONF_PM_PAD_PMU_P_ON1 0x240
#define PCONF_PM_PAD_PMU_P_ON2 0x248
#define PCONF_PM_PAD_RGMII_TXCTL 0x250
#define PCONF_PM_PAD_RGMII_TXC 0x258
#define PCONF_PM_PAD_RGMII_TXD0 0x260
#define PCONF_PM_PAD_RGMII_TXD1 0x268
#define PCONF_PM_PAD_RGMII_TXD2 0x270
#define PCONF_PM_PAD_RGMII_TXD3 0x278
#define PCONF_PM_PAD_RGMII_RXC 0x280
#define PCONF_PM_PAD_RGMII_RXCTL 0x288
#define PCONF_PM_PAD_RGMII_RXD0 0x290
#define PCONF_PM_PAD_RGMII_RXD1 0x298
#define PCONF_PM_PAD_RGMII_RXD2 0x2A0
#define PCONF_PM_PAD_RGMII_RXD3 0x2A8
#define PCONF_PM_PAD_RGMII_MDC 0x2B0
#define PCONF_PM_PAD_RGMII_MDIO 0x2B8
#define PCONF_PM_PAD_RGMII_RESET 0x2C0
#define PCONF_PM_PAD_RGMII_PMEB 0x2C8
#define PCONF_PM_PAD_PCIE2_WAKEN 0x2D0
#define PCONF_PM_PAD_PCIE2_PERSTB 0x2D8
#define PCONF_PM_PAD_PCIE2_PWR_CTL 0x2E0
#define PCONF_PM_PAD_PCIE2_CLKREQN 0x2E8
#define PCONF_PM_PAD_BOOTUP_NOTE 0x2F0
#define PCONF_PM_PAD_U3RX 0x2F8
#define PCONF_PM_PAD_U3TX 0x300


#endif
