/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_SCACE_H
#define _DT_BINDINGS_CLK_MT5896_SCACE_H

#define CLK_SCACE_XTAL_12M_INT_CK	1
#define CLK_SCACE_XTAL_24M_INT_CK	2
#define CLK_SCACE_MCU_NONPM_INT_CK	3
#define CLK_SCACE_RIU_NONPM_INT_CK	4
#define CLK_SCACE_SMI_INT_CK	5
#define CLK_SCACE_MCU_XC_INT_CK	6
#define CLK_SCACE_RIU_XC_INT_CK	7
#define CLK_SCACE_XC_FS_INT_CK	8
#define CLK_SCACE_HSY_8P3_SRAM_INT_CK	12
#define CLK_SCACE_HSY_8P_SRAM_INT_CK	13
#define CLK_SCACE_VIP_ACE_SRAM_INT_CK	14
#define CLK_SCACE_GUCD_18_LUT2_SRAM_INT_CK	15
#define CLK_SCACE_GUCD_256_LUT2_SRAM_INT_CK	16
#define CLK_SCACE_DELTA_B2P2_SRAM_INT_CK	17
#define CLK_SCACE_LCE_ACE_SRAM_INT_CK	18
#define CLK_SCACE_NR	19

#endif
