/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_FIX_ADC_H
#define _DT_BINDINGS_CLK_MT5896_FIX_ADC_H

#define CLK_ADC_ADCPLLA_MPLL_CLK432_P_CK	1
#define CLK_ADC_ADCPLLB_MPLL_CLK432_P_CK	2
#define CLK_ADC_CLK_DIG_216_CK	3
#define CLK_ADC_CLK_DIG_108_CK	4
#define CLK_ADC_CLKPLL_ATOP_CK	5
#define CLK_ADC_CLKD_R_ATOP_CK	6
#define CLK_ADC_CLKD_R_ATOP_INT_CK	7
#define CLK_ADC_CLKD_G_ATOP_CK	8
#define CLK_ADC_CLKD_G_ATOP_INT_CK	9
#define CLK_ADC_CLKD_B_ATOP_CK	10
#define CLK_ADC_CLKD_B_ATOP_INT_CK	11
#define CLK_ADC_VD_DIV2_EN_TO_LOCAL_CK	12
#define CLK_ADC_CLKD_VD_ATOP_CK	13
#define CLK_ADC_CLKD_VD_ATOP_INT_CK	14
#define CLK_ADC_CLKD_2ICLAMP_S_CK	15
#define CLK_ADC_NCO_CLK_CK	16
#define CLK_ADC_VD_NCO_CLK_CK	17
#define CLK_ADC_CK_CVBS_DAC_A_DIGITAL_P_CK	18
#define CLK_ADC_CLK_TSTBUS_CK	19
#define CLK_ADC_CLK_TSTBUS_DIV_CK	20
#define CLK_ADC_ADCPLLB_MPLL_216M_CK	21
#define CLK_ADC_RIU_VD_CK	22
#define CLK_ADC_ADC_CK	23
#define CLK_ADC_ADCPLB_MPLL_CK	24
#define CLK_ADC_CK_CVBS_DAC_A_DIGITAL_P_BUF_CK	25
#define CLK_ADC_ADC_VIF	26
#define CLK_ADC_ADC_CLK_VD	27
#define CLK_ADC_ADC_CLK_DAC_EXTERNAL	28
#define CLK_ADC_ADC_CLK_VD2X	29
#define CLK_ADC_ADC_CLK_VD_32FSC	30
#define CLK_ADC_ADC_CLK_VD_ADC	31
#define CLK_ADC_FIX_N	32

#endif
