#define CKGEN01_V004 0x206000

//Page CKGEN01_V004
#define REG_0000_CKGEN01_V004 (CKGEN01_V004 + 0x000)
	#define REG_0000_CKGEN01_V004_REG_CKG_G_ADC2MIU_0000 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0000_CKGEN01_V004_REG_CKG_I_ADC2MIU_0000 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0000_CKGEN01_V004_REG_CKG_S_ADC2MIU_0000 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0008_CKGEN01_V004 (CKGEN01_V004 + 0x008)
	#define REG_0008_CKGEN01_V004_REG_CKG_G_ADC2MIUSC_0008 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0008_CKGEN01_V004_REG_CKG_I_ADC2MIUSC_0008 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0008_CKGEN01_V004_REG_CKG_S_ADC2MIUSC_0008 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0010_CKGEN01_V004 (CKGEN01_V004 + 0x010)
	#define REG_0010_CKGEN01_V004_REG_CKG_G_ADC2SC_0010 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0010_CKGEN01_V004_REG_CKG_I_ADC2SC_0010 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0010_CKGEN01_V004_REG_CKG_S_ADC2SC_0010 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0018_CKGEN01_V004 (CKGEN01_V004 + 0x018)
	#define REG_0018_CKGEN01_V004_REG_CKG_G_ADC_0018 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0018_CKGEN01_V004_REG_CKG_I_ADC_0018 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0018_CKGEN01_V004_REG_CKG_S_ADC_0018 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0020_CKGEN01_V004 (CKGEN01_V004 + 0x020)
	#define REG_0020_CKGEN01_V004_REG_CKG_G_ADCPLL200_0020 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0020_CKGEN01_V004_REG_CKG_I_ADCPLL200_0020 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0028_CKGEN01_V004 (CKGEN01_V004 + 0x028)
	#define REG_0028_CKGEN01_V004_REG_CKG_G_ADCPLL400_0028 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0028_CKGEN01_V004_REG_CKG_I_ADCPLL400_0028 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0030_CKGEN01_V004 (CKGEN01_V004 + 0x030)
	#define REG_0030_CKGEN01_V004_REG_CKG_G_ADCPLLB_MPLL_216M_0030 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0030_CKGEN01_V004_REG_CKG_I_ADCPLLB_MPLL_216M_0030 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0038_CKGEN01_V004 (CKGEN01_V004 + 0x038)
	#define REG_0038_CKGEN01_V004_REG_CKG_G_B_ADC_0038 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0038_CKGEN01_V004_REG_CKG_I_B_ADC_0038 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0038_CKGEN01_V004_REG_CKG_S_B_ADC_0038 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0040_CKGEN01_V004 (CKGEN01_V004 + 0x040)
	#define REG_0040_CKGEN01_V004_REG_CKG_G_B_INT_0040 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0040_CKGEN01_V004_REG_CKG_I_B_INT_0040 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0040_CKGEN01_V004_REG_CKG_S_B_INT_0040 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0058_CKGEN01_V004 (CKGEN01_V004 + 0x058)
	#define REG_0058_CKGEN01_V004_REG_CKG_G_CLKD_ADC_P_0058 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0058_CKGEN01_V004_REG_CKG_I_CLKD_ADC_P_0058 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0058_CKGEN01_V004_REG_CKG_S_CLKD_ADC_P_0058 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0060_CKGEN01_V004 (CKGEN01_V004 + 0x060)
	#define REG_0060_CKGEN01_V004_REG_CKG_G_CLKD_ATOP_0060 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0060_CKGEN01_V004_REG_CKG_I_CLKD_ATOP_0060 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0060_CKGEN01_V004_REG_CKG_S_CLKD_ATOP_0060 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0068_CKGEN01_V004 (CKGEN01_V004 + 0x068)
	#define REG_0068_CKGEN01_V004_REG_CKG_G_CLKD_ATOP_INTERNAL_0068 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0068_CKGEN01_V004_REG_CKG_I_CLKD_ATOP_INTERNAL_0068 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0068_CKGEN01_V004_REG_CKG_S_CLKD_ATOP_INTERNAL_0068 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0070_CKGEN01_V004 (CKGEN01_V004 + 0x070)
	#define REG_0070_CKGEN01_V004_REG_CKG_G_CLKPLL_0070 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0070_CKGEN01_V004_REG_CKG_I_CLKPLL_0070 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0078_CKGEN01_V004 (CKGEN01_V004 + 0x078)
	#define REG_0078_CKGEN01_V004_REG_CKG_G_CVBS_DAC_A_DIGITAL0_0078 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0078_CKGEN01_V004_REG_CKG_I_CVBS_DAC_A_DIGITAL0_0078 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0078_CKGEN01_V004_REG_CKG_S_CVBS_DAC_A_DIGITAL0_0078 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0080_CKGEN01_V004 (CKGEN01_V004 + 0x080)
	#define REG_0080_CKGEN01_V004_REG_CKG_G_CVBS_DAC_A_DIGITAL0_MUX_0080 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0080_CKGEN01_V004_REG_CKG_I_CVBS_DAC_A_DIGITAL0_MUX_0080 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0080_CKGEN01_V004_REG_CKG_S_CVBS_DAC_A_DIGITAL0_MUX_0080 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0088_CKGEN01_V004 (CKGEN01_V004 + 0x088)
	#define REG_0088_CKGEN01_V004_REG_CKG_G_CVBS_DAC_A_DIGITAL1_0088 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0088_CKGEN01_V004_REG_CKG_I_CVBS_DAC_A_DIGITAL1_0088 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0088_CKGEN01_V004_REG_CKG_S_CVBS_DAC_A_DIGITAL1_0088 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0090_CKGEN01_V004 (CKGEN01_V004 + 0x090)
	#define REG_0090_CKGEN01_V004_REG_CKG_G_DIG_108_0090 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0090_CKGEN01_V004_REG_CKG_I_DIG_108_0090 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0098_CKGEN01_V004 (CKGEN01_V004 + 0x098)
	#define REG_0098_CKGEN01_V004_REG_CKG_G_DIG_216_0098 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0098_CKGEN01_V004_REG_CKG_I_DIG_216_0098 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_00A0_CKGEN01_V004 (CKGEN01_V004 + 0x0A0)
	#define REG_00A0_CKGEN01_V004_REG_CKG_G_FBLANK_00A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00A0_CKGEN01_V004_REG_CKG_I_FBLANK_00A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00A0_CKGEN01_V004_REG_CKG_S_FBLANK_00A0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_00A8_CKGEN01_V004 (CKGEN01_V004 + 0x0A8)
	#define REG_00A8_CKGEN01_V004_REG_CKG_G_FSC_VD_00A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00A8_CKGEN01_V004_REG_CKG_I_FSC_VD_00A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_00B0_CKGEN01_V004 (CKGEN01_V004 + 0x0B0)
	#define REG_00B0_CKGEN01_V004_REG_CKG_G_FSCX2_FB2ATOP_00B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00B0_CKGEN01_V004_REG_CKG_I_FSCX2_FB2ATOP_00B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00B0_CKGEN01_V004_REG_CKG_S_FSCX2_FB2ATOP_00B0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_00B8_CKGEN01_V004 (CKGEN01_V004 + 0x0B8)
	#define REG_00B8_CKGEN01_V004_REG_CKG_G_G_ADC_00B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00B8_CKGEN01_V004_REG_CKG_I_G_ADC_00B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00B8_CKGEN01_V004_REG_CKG_S_G_ADC_00B8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_00C0_CKGEN01_V004 (CKGEN01_V004 + 0x0C0)
	#define REG_00C0_CKGEN01_V004_REG_CKG_G_G_INT_00C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00C0_CKGEN01_V004_REG_CKG_I_G_INT_00C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00C0_CKGEN01_V004_REG_CKG_S_G_INT_00C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_00C8_CKGEN01_V004 (CKGEN01_V004 + 0x0C8)
	#define REG_00C8_CKGEN01_V004_REG_CKG_G_ICLAMP_RGB_00C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00C8_CKGEN01_V004_REG_CKG_I_ICLAMP_RGB_00C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00C8_CKGEN01_V004_REG_CKG_S_ICLAMP_RGB_00C8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_00D0_CKGEN01_V004 (CKGEN01_V004 + 0x0D0)
	#define REG_00D0_CKGEN01_V004_REG_CKG_G_ISOG_00D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00D0_CKGEN01_V004_REG_CKG_I_ISOG_00D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_00E0_CKGEN01_V004 (CKGEN01_V004 + 0x0E0)
	#define REG_00E0_CKGEN01_V004_REG_CKG_G_NCO_CLK_00E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00E0_CKGEN01_V004_REG_CKG_I_NCO_CLK_00E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_00F0_CKGEN01_V004 (CKGEN01_V004 + 0x0F0)
	#define REG_00F0_CKGEN01_V004_REG_CKG_G_R_ADC_00F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00F0_CKGEN01_V004_REG_CKG_I_R_ADC_00F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00F0_CKGEN01_V004_REG_CKG_S_R_ADC_00F0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_00F8_CKGEN01_V004 (CKGEN01_V004 + 0x0F8)
	#define REG_00F8_CKGEN01_V004_REG_CKG_G_R_INT_00F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00F8_CKGEN01_V004_REG_CKG_I_R_INT_00F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00F8_CKGEN01_V004_REG_CKG_S_R_INT_00F8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0108_CKGEN01_V004 (CKGEN01_V004 + 0x108)
	#define REG_0108_CKGEN01_V004_REG_CKG_G_VD_ICLAMP_0108 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0108_CKGEN01_V004_REG_CKG_I_VD_ICLAMP_0108 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0110_CKGEN01_V004 (CKGEN01_V004 + 0x110)
	#define REG_0110_CKGEN01_V004_REG_CKG_G_VD_ADCPLL_0110 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0110_CKGEN01_V004_REG_CKG_I_VD_ADCPLL_0110 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0110_CKGEN01_V004_REG_CKG_S_VD_ADCPLL_0110 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0118_CKGEN01_V004 (CKGEN01_V004 + 0x118)
	#define REG_0118_CKGEN01_V004_REG_CKG_G_VD_NCO_CLK_0118 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0118_CKGEN01_V004_REG_CKG_I_VD_NCO_CLK_0118 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0120_CKGEN01_V004 (CKGEN01_V004 + 0x120)
	#define REG_0120_CKGEN01_V004_REG_CKG_G_VDPLL400_0120 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0120_CKGEN01_V004_REG_CKG_I_VDPLL400_0120 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0128_CKGEN01_V004 (CKGEN01_V004 + 0x128)
	#define REG_0128_CKGEN01_V004_REG_CKG_G_XTAL12_4INTERRUPT_0128 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0128_CKGEN01_V004_REG_CKG_I_XTAL12_4INTERRUPT_0128 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0130_CKGEN01_V004 (CKGEN01_V004 + 0x130)
	#define REG_0130_CKGEN01_V004_REG_CKG_G_XTAL12_4PLUGDET_0130 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0130_CKGEN01_V004_REG_CKG_I_XTAL12_4PLUGDET_0130 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0138_CKGEN01_V004 (CKGEN01_V004 + 0x138)
	#define REG_0138_CKGEN01_V004_REG_CKG_G_XTAL12_0138 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0138_CKGEN01_V004_REG_CKG_I_XTAL12_0138 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0140_CKGEN01_V004 (CKGEN01_V004 + 0x140)
	#define REG_0140_CKGEN01_V004_REG_CKG_G_XTAL24_0140 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0140_CKGEN01_V004_REG_CKG_I_XTAL24_0140 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0148_CKGEN01_V004 (CKGEN01_V004 + 0x148)
	#define REG_0148_CKGEN01_V004_REG_CKG_G_Y_ADC_0148 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0148_CKGEN01_V004_REG_CKG_I_Y_ADC_0148 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0148_CKGEN01_V004_REG_CKG_S_Y_ADC_0148 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0150_CKGEN01_V004 (CKGEN01_V004 + 0x150)
	#define REG_0150_CKGEN01_V004_REG_CKG_G_Y_INT_0150 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0150_CKGEN01_V004_REG_CKG_I_Y_INT_0150 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0150_CKGEN01_V004_REG_CKG_S_Y_INT_0150 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0158_CKGEN01_V004 (CKGEN01_V004 + 0x158)
	#define REG_0158_CKGEN01_V004_REG_CKG_G_YUV_ADC_0158 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0158_CKGEN01_V004_REG_CKG_I_YUV_ADC_0158 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0158_CKGEN01_V004_REG_CKG_S_YUV_ADC_0158 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0160_CKGEN01_V004 (CKGEN01_V004 + 0x160)
	#define REG_0160_CKGEN01_V004_REG_CKG_G_ADCPLB_MPLL_MHEG5_0160 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0160_CKGEN01_V004_REG_CKG_I_ADCPLB_MPLL_MHEG5_0160 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0168_CKGEN01_V004 (CKGEN01_V004 + 0x168)
	#define REG_0168_CKGEN01_V004_REG_CKG_G_GPO_00_0168 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0168_CKGEN01_V004_REG_CKG_I_GPO_00_0168 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0168_CKGEN01_V004_REG_CKG_S_GPO_00_0168 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0168_CKGEN01_V004_REG_CKG_G_GPO_01_0168 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0168_CKGEN01_V004_REG_CKG_I_GPO_01_0168 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0168_CKGEN01_V004_REG_CKG_S_GPO_01_0168 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0168_CKGEN01_V004_REG_CKG_G_GPO_02_0168 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0168_CKGEN01_V004_REG_CKG_I_GPO_02_0168 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0168_CKGEN01_V004_REG_CKG_S_GPO_02_0168 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0168_CKGEN01_V004_REG_CKG_G_GPO_03_0168 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0168_CKGEN01_V004_REG_CKG_I_GPO_03_0168 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0168_CKGEN01_V004_REG_CKG_S_GPO_03_0168 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0170_CKGEN01_V004 (CKGEN01_V004 + 0x170)
	#define REG_0170_CKGEN01_V004_REG_CKG_G_GPO_04_0170 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0170_CKGEN01_V004_REG_CKG_I_GPO_04_0170 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0170_CKGEN01_V004_REG_CKG_S_GPO_04_0170 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0170_CKGEN01_V004_REG_CKG_G_GPO_05_0170 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0170_CKGEN01_V004_REG_CKG_I_GPO_05_0170 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0170_CKGEN01_V004_REG_CKG_S_GPO_05_0170 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0170_CKGEN01_V004_REG_CKG_G_GPO_06_0170 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0170_CKGEN01_V004_REG_CKG_I_GPO_06_0170 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0170_CKGEN01_V004_REG_CKG_S_GPO_06_0170 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0170_CKGEN01_V004_REG_CKG_G_GPO_07_0170 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0170_CKGEN01_V004_REG_CKG_I_GPO_07_0170 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0170_CKGEN01_V004_REG_CKG_S_GPO_07_0170 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0178_CKGEN01_V004 (CKGEN01_V004 + 0x178)
	#define REG_0178_CKGEN01_V004_REG_CKG_G_GPO_08_0178 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0178_CKGEN01_V004_REG_CKG_I_GPO_08_0178 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0178_CKGEN01_V004_REG_CKG_S_GPO_08_0178 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0178_CKGEN01_V004_REG_CKG_G_GPO_09_0178 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0178_CKGEN01_V004_REG_CKG_I_GPO_09_0178 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0178_CKGEN01_V004_REG_CKG_S_GPO_09_0178 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0178_CKGEN01_V004_REG_CKG_G_GPO_10_0178 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0178_CKGEN01_V004_REG_CKG_I_GPO_10_0178 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0178_CKGEN01_V004_REG_CKG_S_GPO_10_0178 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0178_CKGEN01_V004_REG_CKG_G_GPO_11_0178 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0178_CKGEN01_V004_REG_CKG_I_GPO_11_0178 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0178_CKGEN01_V004_REG_CKG_S_GPO_11_0178 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0180_CKGEN01_V004 (CKGEN01_V004 + 0x180)
	#define REG_0180_CKGEN01_V004_REG_CKG_G_GPO_12_0180 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0180_CKGEN01_V004_REG_CKG_I_GPO_12_0180 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0180_CKGEN01_V004_REG_CKG_S_GPO_12_0180 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0180_CKGEN01_V004_REG_CKG_G_GPO_13_0180 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0180_CKGEN01_V004_REG_CKG_I_GPO_13_0180 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0180_CKGEN01_V004_REG_CKG_S_GPO_13_0180 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0180_CKGEN01_V004_REG_CKG_G_GPO_14_0180 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0180_CKGEN01_V004_REG_CKG_I_GPO_14_0180 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0180_CKGEN01_V004_REG_CKG_S_GPO_14_0180 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0180_CKGEN01_V004_REG_CKG_G_GPO_15_0180 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0180_CKGEN01_V004_REG_CKG_I_GPO_15_0180 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0180_CKGEN01_V004_REG_CKG_S_GPO_15_0180 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0188_CKGEN01_V004 (CKGEN01_V004 + 0x188)
	#define REG_0188_CKGEN01_V004_REG_CKG_G_GPO_16_0188 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0188_CKGEN01_V004_REG_CKG_I_GPO_16_0188 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0188_CKGEN01_V004_REG_CKG_S_GPO_16_0188 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0188_CKGEN01_V004_REG_CKG_G_GPO_17_0188 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0188_CKGEN01_V004_REG_CKG_I_GPO_17_0188 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0188_CKGEN01_V004_REG_CKG_S_GPO_17_0188 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0188_CKGEN01_V004_REG_CKG_G_GPO_18_0188 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0188_CKGEN01_V004_REG_CKG_I_GPO_18_0188 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0188_CKGEN01_V004_REG_CKG_S_GPO_18_0188 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0188_CKGEN01_V004_REG_CKG_G_GPO_19_0188 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0188_CKGEN01_V004_REG_CKG_I_GPO_19_0188 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0188_CKGEN01_V004_REG_CKG_S_GPO_19_0188 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0190_CKGEN01_V004 (CKGEN01_V004 + 0x190)
	#define REG_0190_CKGEN01_V004_REG_CKG_G_GPO_20_0190 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0190_CKGEN01_V004_REG_CKG_I_GPO_20_0190 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0190_CKGEN01_V004_REG_CKG_S_GPO_20_0190 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0190_CKGEN01_V004_REG_CKG_G_GPO_21_0190 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0190_CKGEN01_V004_REG_CKG_I_GPO_21_0190 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0190_CKGEN01_V004_REG_CKG_S_GPO_21_0190 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0190_CKGEN01_V004_REG_CKG_G_GPO_22_0190 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0190_CKGEN01_V004_REG_CKG_I_GPO_22_0190 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0190_CKGEN01_V004_REG_CKG_S_GPO_22_0190 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0190_CKGEN01_V004_REG_CKG_G_GPO_23_0190 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0190_CKGEN01_V004_REG_CKG_I_GPO_23_0190 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0190_CKGEN01_V004_REG_CKG_S_GPO_23_0190 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0198_CKGEN01_V004 (CKGEN01_V004 + 0x198)
	#define REG_0198_CKGEN01_V004_REG_CKG_G_GPO_ZONE_0198 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0198_CKGEN01_V004_REG_CKG_I_GPO_ZONE_0198 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0198_CKGEN01_V004_REG_CKG_S_GPO_ZONE_0198 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0198_CKGEN01_V004_REG_CKG_G_PWM_DAC_0198 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0198_CKGEN01_V004_REG_CKG_I_PWM_DAC_0198 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0198_CKGEN01_V004_REG_CKG_S_PWM_DAC_0198 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0198_CKGEN01_V004_REG_CKG_S_GPO_0198 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_01E0_CKGEN01_V004 (CKGEN01_V004 + 0x1E0)
	#define REG_01E0_CKGEN01_V004_REG_CKG_RV55AUDIO_DAP_01E0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_01E8_CKGEN01_V004 (CKGEN01_V004 + 0x1E8)
	#define REG_01E8_CKGEN01_V004_REG_CKG_G_FRC_FCLK_01E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01E8_CKGEN01_V004_REG_CKG_I_FRC_FCLK_01E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01E8_CKGEN01_V004_REG_CKG_S_FRC_FCLK_01E8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_01EC_CKGEN01_V004 (CKGEN01_V004 + 0x1EC)
	#define REG_01EC_CKGEN01_V004_REG_CKG_G_DAP_01EC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01EC_CKGEN01_V004_REG_CKG_I_DAP_01EC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01EC_CKGEN01_V004_REG_CKG_S_DAP_01EC Fld(2,2,AC_MSKB0)//[3:2]
#define REG_01F0_CKGEN01_V004 (CKGEN01_V004 + 0x1F0)
	#define REG_01F0_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2X_01F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01F0_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2X_01F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01F0_CKGEN01_V004_REG_CKG_S_FRC_FCLK_2X_01F0 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01F0_CKGEN01_V004_REG_CKG_G_XC_IP_AUL_CLK_MERGE_01F0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01F0_CKGEN01_V004_REG_CKG_I_XC_IP_AUL_CLK_MERGE_01F0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01F0_CKGEN01_V004_REG_CKG_S_XC_IP_AUL_CLK_MERGE_01F0 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_01F4_CKGEN01_V004 (CKGEN01_V004 + 0x1F4)
	#define REG_01F4_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2X_FRCCORE1_01F4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01F4_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2X_FRCCORE1_01F4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01F4_CKGEN01_V004_REG_CKG_S_FRC_FCLK_2X_FRCCORE1_01F4 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01F4_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2X_FRCCORE2_01F4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01F4_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2X_FRCCORE2_01F4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01F4_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2X_FRCCORE3_01F4 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01F4_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2X_FRCCORE3_01F4 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01F4_CKGEN01_V004_REG_CKG_S_FRC_FCLK_2X_FRCCORE3_01F4 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_01F8_CKGEN01_V004 (CKGEN01_V004 + 0x1F8)
	#define REG_01F8_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2XPLUS_01F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01F8_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2XPLUS_01F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01F8_CKGEN01_V004_REG_CKG_S_FRC_FCLK_2XPLUS_01F8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01F8_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2XPLUS_SCBE_01F8 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01F8_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2XPLUS_SCBE_01F8 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_01F8_CKGEN01_V004_REG_CKG_G_FRC_FCLK_2XPLUS_SCIP_01F8 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01F8_CKGEN01_V004_REG_CKG_I_FRC_FCLK_2XPLUS_SCIP_01F8 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0208_CKGEN01_V004 (CKGEN01_V004 + 0x208)
	#define REG_0208_CKGEN01_V004_REG_CKG_RV55FRC_0208 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0214_CKGEN01_V004 (CKGEN01_V004 + 0x214)
	#define REG_0214_CKGEN01_V004_REG_CKG_G_RV55DAP_JTAG_TCK_FRCMISC_0214 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0214_CKGEN01_V004_REG_CKG_I_RV55DAP_JTAG_TCK_FRCMISC_0214 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_0220_CKGEN01_V004 (CKGEN01_V004 + 0x220)
	#define REG_0220_CKGEN01_V004_REG_CKG_RV55PQU_0220 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0240_CKGEN01_V004 (CKGEN01_V004 + 0x240)
	#define REG_0240_CKGEN01_V004_REG_CKG_G_DAP_FRCMISC_0240 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0240_CKGEN01_V004_REG_CKG_I_DAP_FRCMISC_0240 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0248_CKGEN01_V004 (CKGEN01_V004 + 0x248)
	#define REG_0248_CKGEN01_V004_REG_CKG_G_XTAL_24M_FRCCORE1_0248 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0248_CKGEN01_V004_REG_CKG_I_XTAL_24M_FRCCORE1_0248 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0250_CKGEN01_V004 (CKGEN01_V004 + 0x250)
	#define REG_0250_CKGEN01_V004_REG_CKG_G_XTAL_24M_FRCCORE2_0250 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0250_CKGEN01_V004_REG_CKG_I_XTAL_24M_FRCCORE2_0250 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_025C_CKGEN01_V004 (CKGEN01_V004 + 0x25C)
	#define REG_025C_CKGEN01_V004_REG_CKG_G_XTAL_12M_MISC_025C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_025C_CKGEN01_V004_REG_CKG_I_XTAL_12M_MISC_025C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0290_CKGEN01_V004 (CKGEN01_V004 + 0x290)
	#define REG_0290_CKGEN01_V004_REG_CKG_G_XTAL_24M_FRCCORE3_0290 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0290_CKGEN01_V004_REG_CKG_I_XTAL_24M_FRCCORE3_0290 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02A0_CKGEN01_V004 (CKGEN01_V004 + 0x2A0)
	#define REG_02A0_CKGEN01_V004_REG_CKG_G_GE_02A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02A0_CKGEN01_V004_REG_CKG_I_GE_02A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02A0_CKGEN01_V004_REG_CKG_S_GE_02A0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_02B0_CKGEN01_V004 (CKGEN01_V004 + 0x2B0)
	#define REG_02B0_CKGEN01_V004_REG_CKG_G_HDMI_R2_02B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02B0_CKGEN01_V004_REG_CKG_I_HDMI_R2_02B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02B0_CKGEN01_V004_REG_CKG_S_HDMI_R2_02B0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_02B8_CKGEN01_V004 (CKGEN01_V004 + 0x2B8)
	#define REG_02B8_CKGEN01_V004_REG_CKG_G_HDMIRX_TIMESTAMP_02B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02B8_CKGEN01_V004_REG_CKG_I_HDMIRX_TIMESTAMP_02B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02C0_CKGEN01_V004 (CKGEN01_V004 + 0x2C0)
	#define REG_02C0_CKGEN01_V004_REG_CKG_G_128FS_FB_S0_02C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02C0_CKGEN01_V004_REG_CKG_I_128FS_FB_S0_02C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02C0_CKGEN01_V004_REG_CKG_S_128FS_FB_S0_02C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_02C8_CKGEN01_V004 (CKGEN01_V004 + 0x2C8)
	#define REG_02C8_CKGEN01_V004_REG_CKG_G_128FS_FB_S1_02C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02C8_CKGEN01_V004_REG_CKG_I_128FS_FB_S1_02C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02C8_CKGEN01_V004_REG_CKG_S_128FS_FB_S1_02C8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_02D0_CKGEN01_V004 (CKGEN01_V004 + 0x2D0)
	#define REG_02D0_CKGEN01_V004_REG_CKG_G_128FS_S0_02D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02D0_CKGEN01_V004_REG_CKG_I_128FS_S0_02D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02D0_CKGEN01_V004_REG_CKG_S_128FS_S0_02D0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_02D8_CKGEN01_V004 (CKGEN01_V004 + 0x2D8)
	#define REG_02D8_CKGEN01_V004_REG_CKG_G_128FS_S1_02D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02D8_CKGEN01_V004_REG_CKG_I_128FS_S1_02D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02D8_CKGEN01_V004_REG_CKG_S_128FS_S1_02D8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_02E0_CKGEN01_V004 (CKGEN01_V004 + 0x2E0)
	#define REG_02E0_CKGEN01_V004_REG_CKG_G_216_02E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02E0_CKGEN01_V004_REG_CKG_I_216_02E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02E0_CKGEN01_V004_REG_CKG_S_216_02E0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_02E8_CKGEN01_V004 (CKGEN01_V004 + 0x2E8)
	#define REG_02E8_CKGEN01_V004_REG_CKG_G_256FS_S0_02E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02E8_CKGEN01_V004_REG_CKG_I_256FS_S0_02E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02E8_CKGEN01_V004_REG_CKG_S_256FS_S0_02E8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_02F0_CKGEN01_V004 (CKGEN01_V004 + 0x2F0)
	#define REG_02F0_CKGEN01_V004_REG_CKG_G_256FS_S1_02F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02F0_CKGEN01_V004_REG_CKG_I_256FS_S1_02F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02F0_CKGEN01_V004_REG_CKG_S_256FS_S1_02F0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_02F8_CKGEN01_V004 (CKGEN01_V004 + 0x2F8)
	#define REG_02F8_CKGEN01_V004_REG_CKG_G_432_02F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02F8_CKGEN01_V004_REG_CKG_I_432_02F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_02F8_CKGEN01_V004_REG_CKG_S_432_02F8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0300_CKGEN01_V004 (CKGEN01_V004 + 0x300)
	#define REG_0300_CKGEN01_V004_REG_CKG_G_864_0300 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0300_CKGEN01_V004_REG_CKG_I_864_0300 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0300_CKGEN01_V004_REG_CKG_S_864_0300 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0308_CKGEN01_V004 (CKGEN01_V004 + 0x308)
	#define REG_0308_CKGEN01_V004_REG_CKG_G_CLK_DET_INNER_MISC_0_0308 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0308_CKGEN01_V004_REG_CKG_I_CLK_DET_INNER_MISC_0_0308 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0308_CKGEN01_V004_REG_CKG_S_CLK_DET_INNER_MISC_0_0308 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0310_CKGEN01_V004 (CKGEN01_V004 + 0x310)
	#define REG_0310_CKGEN01_V004_REG_CKG_G_CLK_DET_INNER_MISC_0_0_0310 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0310_CKGEN01_V004_REG_CKG_I_CLK_DET_INNER_MISC_0_0_0310 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0310_CKGEN01_V004_REG_CKG_S_CLK_DET_INNER_MISC_0_0_0310 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0318_CKGEN01_V004 (CKGEN01_V004 + 0x318)
	#define REG_0318_CKGEN01_V004_REG_CKG_G_CLK_DET_INNER_MISC_1_0318 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0318_CKGEN01_V004_REG_CKG_I_CLK_DET_INNER_MISC_1_0318 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0318_CKGEN01_V004_REG_CKG_S_CLK_DET_INNER_MISC_1_0318 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0320_CKGEN01_V004 (CKGEN01_V004 + 0x320)
	#define REG_0320_CKGEN01_V004_REG_CKG_G_CLK_DET_INNER_MISC_1_0_0320 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0320_CKGEN01_V004_REG_CKG_I_CLK_DET_INNER_MISC_1_0_0320 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0320_CKGEN01_V004_REG_CKG_S_CLK_DET_INNER_MISC_1_0_0320 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0328_CKGEN01_V004 (CKGEN01_V004 + 0x328)
	#define REG_0328_CKGEN01_V004_REG_CKG_G_CTS_SYNTH_S0_0328 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0328_CKGEN01_V004_REG_CKG_I_CTS_SYNTH_S0_0328 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0328_CKGEN01_V004_REG_CKG_S_CTS_SYNTH_S0_0328 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0330_CKGEN01_V004 (CKGEN01_V004 + 0x330)
	#define REG_0330_CKGEN01_V004_REG_CKG_G_CTS_SYNTH_S0_0_0330 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0330_CKGEN01_V004_REG_CKG_I_CTS_SYNTH_S0_0_0330 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0330_CKGEN01_V004_REG_CKG_S_CTS_SYNTH_S0_0_0330 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0338_CKGEN01_V004 (CKGEN01_V004 + 0x338)
	#define REG_0338_CKGEN01_V004_REG_CKG_G_CTS_SYNTH_S1_0338 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0338_CKGEN01_V004_REG_CKG_I_CTS_SYNTH_S1_0338 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0338_CKGEN01_V004_REG_CKG_S_CTS_SYNTH_S1_0338 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0340_CKGEN01_V004 (CKGEN01_V004 + 0x340)
	#define REG_0340_CKGEN01_V004_REG_CKG_G_CTS_SYNTH_S1_0_0340 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0340_CKGEN01_V004_REG_CKG_I_CTS_SYNTH_S1_0_0340 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0340_CKGEN01_V004_REG_CKG_S_CTS_SYNTH_S1_0_0340 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0348_CKGEN01_V004 (CKGEN01_V004 + 0x348)
	#define REG_0348_CKGEN01_V004_REG_CKG_G_DSC_ENGINE_0348 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0348_CKGEN01_V004_REG_CKG_I_DSC_ENGINE_0348 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0348_CKGEN01_V004_REG_CKG_S_DSC_ENGINE_0348 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0350_CKGEN01_V004 (CKGEN01_V004 + 0x350)
	#define REG_0350_CKGEN01_V004_REG_CKG_G_DVI2MIU_RD_S0_0350 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0350_CKGEN01_V004_REG_CKG_I_DVI2MIU_RD_S0_0350 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0350_CKGEN01_V004_REG_CKG_S_DVI2MIU_RD_S0_0350 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0358_CKGEN01_V004 (CKGEN01_V004 + 0x358)
	#define REG_0358_CKGEN01_V004_REG_CKG_G_DVI2MIU_RD_S1_0358 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0358_CKGEN01_V004_REG_CKG_I_DVI2MIU_RD_S1_0358 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0358_CKGEN01_V004_REG_CKG_S_DVI2MIU_RD_S1_0358 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0360_CKGEN01_V004 (CKGEN01_V004 + 0x360)
	#define REG_0360_CKGEN01_V004_REG_CKG_G_DVI2MIU_WR_S0_0360 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0360_CKGEN01_V004_REG_CKG_I_DVI2MIU_WR_S0_0360 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0360_CKGEN01_V004_REG_CKG_S_DVI2MIU_WR_S0_0360 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0368_CKGEN01_V004 (CKGEN01_V004 + 0x368)
	#define REG_0368_CKGEN01_V004_REG_CKG_G_DVI2MIU_WR_S0_0_0368 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0368_CKGEN01_V004_REG_CKG_I_DVI2MIU_WR_S0_0_0368 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0368_CKGEN01_V004_REG_CKG_S_DVI2MIU_WR_S0_0_0368 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0370_CKGEN01_V004 (CKGEN01_V004 + 0x370)
	#define REG_0370_CKGEN01_V004_REG_CKG_G_DVI2MIU_WR_S0_1_0370 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0370_CKGEN01_V004_REG_CKG_I_DVI2MIU_WR_S0_1_0370 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0370_CKGEN01_V004_REG_CKG_S_DVI2MIU_WR_S0_1_0370 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0398_CKGEN01_V004 (CKGEN01_V004 + 0x398)
	#define REG_0398_CKGEN01_V004_REG_CKG_G_DVI2MIU_WR_S1_0398 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0398_CKGEN01_V004_REG_CKG_I_DVI2MIU_WR_S1_0398 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0398_CKGEN01_V004_REG_CKG_S_DVI2MIU_WR_S1_0398 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_03A0_CKGEN01_V004 (CKGEN01_V004 + 0x3A0)
	#define REG_03A0_CKGEN01_V004_REG_CKG_G_DVI2MIU_WR_S1_0_03A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03A0_CKGEN01_V004_REG_CKG_I_DVI2MIU_WR_S1_0_03A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03A0_CKGEN01_V004_REG_CKG_S_DVI2MIU_WR_S1_0_03A0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_03A8_CKGEN01_V004 (CKGEN01_V004 + 0x3A8)
	#define REG_03A8_CKGEN01_V004_REG_CKG_G_DVI2MIU_WR_S1_1_03A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03A8_CKGEN01_V004_REG_CKG_I_DVI2MIU_WR_S1_1_03A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03A8_CKGEN01_V004_REG_CKG_S_DVI2MIU_WR_S1_1_03A8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_03D0_CKGEN01_V004 (CKGEN01_V004 + 0x3D0)
	#define REG_03D0_CKGEN01_V004_REG_CKG_G_EARC_AUDIO_03D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03D0_CKGEN01_V004_REG_CKG_I_EARC_AUDIO_03D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03D0_CKGEN01_V004_REG_CKG_S_EARC_AUDIO_03D0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_03D8_CKGEN01_V004 (CKGEN01_V004 + 0x3D8)
	#define REG_03D8_CKGEN01_V004_REG_CKG_G_EARC_CM_03D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03D8_CKGEN01_V004_REG_CKG_I_EARC_CM_03D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03D8_CKGEN01_V004_REG_CKG_S_EARC_CM_03D8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_03E0_CKGEN01_V004 (CKGEN01_V004 + 0x3E0)
	#define REG_03E0_CKGEN01_V004_REG_CKG_G_EARC_DEBOUNCE_03E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03E0_CKGEN01_V004_REG_CKG_I_EARC_DEBOUNCE_03E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03E8_CKGEN01_V004 (CKGEN01_V004 + 0x3E8)
	#define REG_03E8_CKGEN01_V004_REG_CKG_G_EARC_DM_PRBS_03E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03E8_CKGEN01_V004_REG_CKG_I_EARC_DM_PRBS_03E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03E8_CKGEN01_V004_REG_CKG_S_EARC_DM_PRBS_03E8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_03F0_CKGEN01_V004 (CKGEN01_V004 + 0x3F0)
	#define REG_03F0_CKGEN01_V004_REG_CKG_G_LINK_DSCD_03F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03F0_CKGEN01_V004_REG_CKG_I_LINK_DSCD_03F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03F0_CKGEN01_V004_REG_CKG_S_LINK_DSCD_03F0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_03F8_CKGEN01_V004 (CKGEN01_V004 + 0x3F8)
	#define REG_03F8_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEC_MISC_0_03F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03F8_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEC_MISC_0_03F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_03F8_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEC_MISC_0_03F8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0400_CKGEN01_V004 (CKGEN01_V004 + 0x400)
	#define REG_0400_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEC_MISC_0_0_0400 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0400_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEC_MISC_0_0_0400 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0400_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEC_MISC_0_0_0400 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0408_CKGEN01_V004 (CKGEN01_V004 + 0x408)
	#define REG_0408_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEC_MISC_1_0408 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0408_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEC_MISC_1_0408 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0408_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEC_MISC_1_0408 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0410_CKGEN01_V004 (CKGEN01_V004 + 0x410)
	#define REG_0410_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEC_MISC_1_0_0410 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0410_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEC_MISC_1_0_0410 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0410_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEC_MISC_1_0_0410 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0418_CKGEN01_V004 (CKGEN01_V004 + 0x418)
	#define REG_0418_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEP_MISC_0_0418 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0418_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEP_MISC_0_0418 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0418_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEP_MISC_0_0418 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0420_CKGEN01_V004 (CKGEN01_V004 + 0x420)
	#define REG_0420_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEP_MISC_0_0_0420 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0420_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEP_MISC_0_0_0420 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0420_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEP_MISC_0_0_0420 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0428_CKGEN01_V004 (CKGEN01_V004 + 0x428)
	#define REG_0428_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEP_MISC_1_0428 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0428_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEP_MISC_1_0428 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0428_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEP_MISC_1_0428 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0430_CKGEN01_V004 (CKGEN01_V004 + 0x430)
	#define REG_0430_CKGEN01_V004_REG_CKG_G_P0_CLK_DET_DEP_MISC_1_0_0430 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0430_CKGEN01_V004_REG_CKG_I_P0_CLK_DET_DEP_MISC_1_0_0430 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0430_CKGEN01_V004_REG_CKG_S_P0_CLK_DET_DEP_MISC_1_0_0430 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0438_CKGEN01_V004 (CKGEN01_V004 + 0x438)
	#define REG_0438_CKGEN01_V004_REG_CKG_G_P0_LINK_0438 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0438_CKGEN01_V004_REG_CKG_I_P0_LINK_0438 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0438_CKGEN01_V004_REG_CKG_S_P0_LINK_0438 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0440_CKGEN01_V004 (CKGEN01_V004 + 0x440)
	#define REG_0440_CKGEN01_V004_REG_CKG_G_P0_PIX_1P_0440 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0440_CKGEN01_V004_REG_CKG_I_P0_PIX_1P_0440 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0440_CKGEN01_V004_REG_CKG_S_P0_PIX_1P_0440 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0448_CKGEN01_V004 (CKGEN01_V004 + 0x448)
	#define REG_0448_CKGEN01_V004_REG_CKG_G_P0_PIX_8P_0448 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0448_CKGEN01_V004_REG_CKG_I_P0_PIX_8P_0448 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0448_CKGEN01_V004_REG_CKG_S_P0_PIX_8P_0448 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0450_CKGEN01_V004 (CKGEN01_V004 + 0x450)
	#define REG_0450_CKGEN01_V004_REG_CKG_G_P0_PIX_DC_MUX_0450 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0450_CKGEN01_V004_REG_CKG_I_P0_PIX_DC_MUX_0450 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0450_CKGEN01_V004_REG_CKG_S_P0_PIX_DC_MUX_0450 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0458_CKGEN01_V004 (CKGEN01_V004 + 0x458)
	#define REG_0458_CKGEN01_V004_REG_CKG_G_P0_PIX_RCV_MUX_0458 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0458_CKGEN01_V004_REG_CKG_I_P0_PIX_RCV_MUX_0458 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0458_CKGEN01_V004_REG_CKG_S_P0_PIX_RCV_MUX_0458 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0460_CKGEN01_V004 (CKGEN01_V004 + 0x460)
	#define REG_0460_CKGEN01_V004_REG_CKG_G_P0_PIX_REP_1P_0460 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0460_CKGEN01_V004_REG_CKG_I_P0_PIX_REP_1P_0460 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0460_CKGEN01_V004_REG_CKG_S_P0_PIX_REP_1P_0460 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0468_CKGEN01_V004 (CKGEN01_V004 + 0x468)
	#define REG_0468_CKGEN01_V004_REG_CKG_G_P0_PIX_TMDSPLL_0468 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0468_CKGEN01_V004_REG_CKG_I_P0_PIX_TMDSPLL_0468 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0468_CKGEN01_V004_REG_CKG_S_P0_PIX_TMDSPLL_0468 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0478_CKGEN01_V004 (CKGEN01_V004 + 0x478)
	#define REG_0478_CKGEN01_V004_REG_CKG_G_P0_PIX_XC_MUX_0478 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0478_CKGEN01_V004_REG_CKG_I_P0_PIX_XC_MUX_0478 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0478_CKGEN01_V004_REG_CKG_S_P0_PIX_XC_MUX_0478 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0480_CKGEN01_V004 (CKGEN01_V004 + 0x480)
	#define REG_0480_CKGEN01_V004_REG_CKG_G_P0_TIMING_DET_DEC_0480 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0480_CKGEN01_V004_REG_CKG_I_P0_TIMING_DET_DEC_0480 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0480_CKGEN01_V004_REG_CKG_S_P0_TIMING_DET_DEC_0480 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0488_CKGEN01_V004 (CKGEN01_V004 + 0x488)
	#define REG_0488_CKGEN01_V004_REG_CKG_G_P0_TIMING_DET_DEP_0488 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0488_CKGEN01_V004_REG_CKG_I_P0_TIMING_DET_DEP_0488 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0488_CKGEN01_V004_REG_CKG_S_P0_TIMING_DET_DEP_0488 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0490_CKGEN01_V004 (CKGEN01_V004 + 0x490)
	#define REG_0490_CKGEN01_V004_REG_CKG_G_P0_TIMING_DET_DTOP_0490 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0490_CKGEN01_V004_REG_CKG_I_P0_TIMING_DET_DTOP_0490 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0490_CKGEN01_V004_REG_CKG_S_P0_TIMING_DET_DTOP_0490 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0498_CKGEN01_V004 (CKGEN01_V004 + 0x498)
	#define REG_0498_CKGEN01_V004_REG_CKG_G_P0_TMDS_FRL_8P_0498 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0498_CKGEN01_V004_REG_CKG_I_P0_TMDS_FRL_8P_0498 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0498_CKGEN01_V004_REG_CKG_S_P0_TMDS_FRL_8P_0498 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04A0_CKGEN01_V004 (CKGEN01_V004 + 0x4A0)
	#define REG_04A0_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP_1P_04A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04A0_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP_1P_04A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04A0_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP_1P_04A0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04A8_CKGEN01_V004 (CKGEN01_V004 + 0x4A8)
	#define REG_04A8_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP_4P_04A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04A8_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP_4P_04A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04A8_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP_4P_04A8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04B0_CKGEN01_V004 (CKGEN01_V004 + 0x4B0)
	#define REG_04B0_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP_8P_04B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04B0_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP_8P_04B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04B0_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP_8P_04B0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04B8_CKGEN01_V004 (CKGEN01_V004 + 0x4B8)
	#define REG_04B8_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP_MUX_04B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04B8_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP_MUX_04B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04B8_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP_MUX_04B8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04C0_CKGEN01_V004 (CKGEN01_V004 + 0x4C0)
	#define REG_04C0_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDMI_1P_04C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04C0_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDMI_1P_04C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04C0_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDMI_1P_04C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04C8_CKGEN01_V004 (CKGEN01_V004 + 0x4C8)
	#define REG_04C8_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDMI_8P_04C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04C8_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDMI_8P_04C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04C8_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDMI_8P_04C8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04D0_CKGEN01_V004 (CKGEN01_V004 + 0x4D0)
	#define REG_04D0_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDMI_MUX_04D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04D0_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDMI_MUX_04D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04D0_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDMI_MUX_04D0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04D8_CKGEN01_V004 (CKGEN01_V004 + 0x4D8)
	#define REG_04D8_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEC_MISC_0_04D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04D8_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEC_MISC_0_04D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04D8_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEC_MISC_0_04D8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04E0_CKGEN01_V004 (CKGEN01_V004 + 0x4E0)
	#define REG_04E0_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEC_MISC_0_0_04E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04E0_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEC_MISC_0_0_04E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04E0_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEC_MISC_0_0_04E0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04E8_CKGEN01_V004 (CKGEN01_V004 + 0x4E8)
	#define REG_04E8_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEC_MISC_1_04E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04E8_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEC_MISC_1_04E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04E8_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEC_MISC_1_04E8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04F0_CKGEN01_V004 (CKGEN01_V004 + 0x4F0)
	#define REG_04F0_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEC_MISC_1_0_04F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04F0_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEC_MISC_1_0_04F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04F0_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEC_MISC_1_0_04F0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_04F8_CKGEN01_V004 (CKGEN01_V004 + 0x4F8)
	#define REG_04F8_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEP_MISC_0_04F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04F8_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEP_MISC_0_04F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_04F8_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEP_MISC_0_04F8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0500_CKGEN01_V004 (CKGEN01_V004 + 0x500)
	#define REG_0500_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEP_MISC_0_0_0500 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0500_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEP_MISC_0_0_0500 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0500_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEP_MISC_0_0_0500 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0508_CKGEN01_V004 (CKGEN01_V004 + 0x508)
	#define REG_0508_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEP_MISC_1_0508 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0508_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEP_MISC_1_0508 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0508_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEP_MISC_1_0508 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0510_CKGEN01_V004 (CKGEN01_V004 + 0x510)
	#define REG_0510_CKGEN01_V004_REG_CKG_G_P1_CLK_DET_DEP_MISC_1_0_0510 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0510_CKGEN01_V004_REG_CKG_I_P1_CLK_DET_DEP_MISC_1_0_0510 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0510_CKGEN01_V004_REG_CKG_S_P1_CLK_DET_DEP_MISC_1_0_0510 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0518_CKGEN01_V004 (CKGEN01_V004 + 0x518)
	#define REG_0518_CKGEN01_V004_REG_CKG_G_P1_LINK_0518 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0518_CKGEN01_V004_REG_CKG_I_P1_LINK_0518 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0518_CKGEN01_V004_REG_CKG_S_P1_LINK_0518 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0520_CKGEN01_V004 (CKGEN01_V004 + 0x520)
	#define REG_0520_CKGEN01_V004_REG_CKG_G_P1_PIX_1P_0520 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0520_CKGEN01_V004_REG_CKG_I_P1_PIX_1P_0520 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0520_CKGEN01_V004_REG_CKG_S_P1_PIX_1P_0520 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0528_CKGEN01_V004 (CKGEN01_V004 + 0x528)
	#define REG_0528_CKGEN01_V004_REG_CKG_G_P1_PIX_8P_0528 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0528_CKGEN01_V004_REG_CKG_I_P1_PIX_8P_0528 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0528_CKGEN01_V004_REG_CKG_S_P1_PIX_8P_0528 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0530_CKGEN01_V004 (CKGEN01_V004 + 0x530)
	#define REG_0530_CKGEN01_V004_REG_CKG_G_P1_PIX_DC_MUX_0530 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0530_CKGEN01_V004_REG_CKG_I_P1_PIX_DC_MUX_0530 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0530_CKGEN01_V004_REG_CKG_S_P1_PIX_DC_MUX_0530 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0538_CKGEN01_V004 (CKGEN01_V004 + 0x538)
	#define REG_0538_CKGEN01_V004_REG_CKG_G_P1_PIX_RCV_MUX_0538 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0538_CKGEN01_V004_REG_CKG_I_P1_PIX_RCV_MUX_0538 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0538_CKGEN01_V004_REG_CKG_S_P1_PIX_RCV_MUX_0538 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0540_CKGEN01_V004 (CKGEN01_V004 + 0x540)
	#define REG_0540_CKGEN01_V004_REG_CKG_G_P1_PIX_REP_1P_0540 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0540_CKGEN01_V004_REG_CKG_I_P1_PIX_REP_1P_0540 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0540_CKGEN01_V004_REG_CKG_S_P1_PIX_REP_1P_0540 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0548_CKGEN01_V004 (CKGEN01_V004 + 0x548)
	#define REG_0548_CKGEN01_V004_REG_CKG_G_P1_PIX_TMDSPLL_0548 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0548_CKGEN01_V004_REG_CKG_I_P1_PIX_TMDSPLL_0548 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0548_CKGEN01_V004_REG_CKG_S_P1_PIX_TMDSPLL_0548 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0558_CKGEN01_V004 (CKGEN01_V004 + 0x558)
	#define REG_0558_CKGEN01_V004_REG_CKG_G_P1_PIX_XC_MUX_0558 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0558_CKGEN01_V004_REG_CKG_I_P1_PIX_XC_MUX_0558 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0558_CKGEN01_V004_REG_CKG_S_P1_PIX_XC_MUX_0558 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0560_CKGEN01_V004 (CKGEN01_V004 + 0x560)
	#define REG_0560_CKGEN01_V004_REG_CKG_G_P1_TIMING_DET_DEC_0560 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0560_CKGEN01_V004_REG_CKG_I_P1_TIMING_DET_DEC_0560 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0560_CKGEN01_V004_REG_CKG_S_P1_TIMING_DET_DEC_0560 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0568_CKGEN01_V004 (CKGEN01_V004 + 0x568)
	#define REG_0568_CKGEN01_V004_REG_CKG_G_P1_TIMING_DET_DEP_0568 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0568_CKGEN01_V004_REG_CKG_I_P1_TIMING_DET_DEP_0568 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0568_CKGEN01_V004_REG_CKG_S_P1_TIMING_DET_DEP_0568 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0570_CKGEN01_V004 (CKGEN01_V004 + 0x570)
	#define REG_0570_CKGEN01_V004_REG_CKG_G_P1_TIMING_DET_DTOP_0570 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0570_CKGEN01_V004_REG_CKG_I_P1_TIMING_DET_DTOP_0570 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0570_CKGEN01_V004_REG_CKG_S_P1_TIMING_DET_DTOP_0570 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0578_CKGEN01_V004 (CKGEN01_V004 + 0x578)
	#define REG_0578_CKGEN01_V004_REG_CKG_G_P1_TMDS_FRL_8P_0578 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0578_CKGEN01_V004_REG_CKG_I_P1_TMDS_FRL_8P_0578 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0578_CKGEN01_V004_REG_CKG_S_P1_TMDS_FRL_8P_0578 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0580_CKGEN01_V004 (CKGEN01_V004 + 0x580)
	#define REG_0580_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP_1P_0580 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0580_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP_1P_0580 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0580_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP_1P_0580 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0588_CKGEN01_V004 (CKGEN01_V004 + 0x588)
	#define REG_0588_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP_4P_0588 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0588_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP_4P_0588 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0588_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP_4P_0588 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0590_CKGEN01_V004 (CKGEN01_V004 + 0x590)
	#define REG_0590_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP_8P_0590 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0590_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP_8P_0590 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0590_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP_8P_0590 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0598_CKGEN01_V004 (CKGEN01_V004 + 0x598)
	#define REG_0598_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP_MUX_0598 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0598_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP_MUX_0598 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0598_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP_MUX_0598 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05A0_CKGEN01_V004 (CKGEN01_V004 + 0x5A0)
	#define REG_05A0_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDMI_1P_05A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05A0_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDMI_1P_05A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05A0_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDMI_1P_05A0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05A8_CKGEN01_V004 (CKGEN01_V004 + 0x5A8)
	#define REG_05A8_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDMI_8P_05A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05A8_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDMI_8P_05A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05A8_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDMI_8P_05A8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05B0_CKGEN01_V004 (CKGEN01_V004 + 0x5B0)
	#define REG_05B0_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDMI_MUX_05B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05B0_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDMI_MUX_05B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05B0_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDMI_MUX_05B0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05B8_CKGEN01_V004 (CKGEN01_V004 + 0x5B8)
	#define REG_05B8_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEC_MISC_0_05B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05B8_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEC_MISC_0_05B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05B8_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEC_MISC_0_05B8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05C0_CKGEN01_V004 (CKGEN01_V004 + 0x5C0)
	#define REG_05C0_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEC_MISC_0_0_05C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05C0_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEC_MISC_0_0_05C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05C0_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEC_MISC_0_0_05C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05C8_CKGEN01_V004 (CKGEN01_V004 + 0x5C8)
	#define REG_05C8_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEC_MISC_1_05C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05C8_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEC_MISC_1_05C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05C8_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEC_MISC_1_05C8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05D0_CKGEN01_V004 (CKGEN01_V004 + 0x5D0)
	#define REG_05D0_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEC_MISC_1_0_05D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05D0_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEC_MISC_1_0_05D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05D0_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEC_MISC_1_0_05D0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05D8_CKGEN01_V004 (CKGEN01_V004 + 0x5D8)
	#define REG_05D8_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEP_MISC_0_05D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05D8_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEP_MISC_0_05D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05D8_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEP_MISC_0_05D8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05E0_CKGEN01_V004 (CKGEN01_V004 + 0x5E0)
	#define REG_05E0_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEP_MISC_0_0_05E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05E0_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEP_MISC_0_0_05E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05E0_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEP_MISC_0_0_05E0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05E8_CKGEN01_V004 (CKGEN01_V004 + 0x5E8)
	#define REG_05E8_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEP_MISC_1_05E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05E8_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEP_MISC_1_05E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05E8_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEP_MISC_1_05E8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05F0_CKGEN01_V004 (CKGEN01_V004 + 0x5F0)
	#define REG_05F0_CKGEN01_V004_REG_CKG_G_P2_CLK_DET_DEP_MISC_1_0_05F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05F0_CKGEN01_V004_REG_CKG_I_P2_CLK_DET_DEP_MISC_1_0_05F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05F0_CKGEN01_V004_REG_CKG_S_P2_CLK_DET_DEP_MISC_1_0_05F0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_05F8_CKGEN01_V004 (CKGEN01_V004 + 0x5F8)
	#define REG_05F8_CKGEN01_V004_REG_CKG_G_P2_LINK_05F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05F8_CKGEN01_V004_REG_CKG_I_P2_LINK_05F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_05F8_CKGEN01_V004_REG_CKG_S_P2_LINK_05F8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0600_CKGEN01_V004 (CKGEN01_V004 + 0x600)
	#define REG_0600_CKGEN01_V004_REG_CKG_G_P2_PIX_1P_0600 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0600_CKGEN01_V004_REG_CKG_I_P2_PIX_1P_0600 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0600_CKGEN01_V004_REG_CKG_S_P2_PIX_1P_0600 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0608_CKGEN01_V004 (CKGEN01_V004 + 0x608)
	#define REG_0608_CKGEN01_V004_REG_CKG_G_P2_PIX_8P_0608 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0608_CKGEN01_V004_REG_CKG_I_P2_PIX_8P_0608 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0608_CKGEN01_V004_REG_CKG_S_P2_PIX_8P_0608 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0610_CKGEN01_V004 (CKGEN01_V004 + 0x610)
	#define REG_0610_CKGEN01_V004_REG_CKG_G_P2_PIX_DC_MUX_0610 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0610_CKGEN01_V004_REG_CKG_I_P2_PIX_DC_MUX_0610 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0610_CKGEN01_V004_REG_CKG_S_P2_PIX_DC_MUX_0610 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0618_CKGEN01_V004 (CKGEN01_V004 + 0x618)
	#define REG_0618_CKGEN01_V004_REG_CKG_G_P2_PIX_RCV_MUX_0618 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0618_CKGEN01_V004_REG_CKG_I_P2_PIX_RCV_MUX_0618 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0618_CKGEN01_V004_REG_CKG_S_P2_PIX_RCV_MUX_0618 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0620_CKGEN01_V004 (CKGEN01_V004 + 0x620)
	#define REG_0620_CKGEN01_V004_REG_CKG_G_P2_PIX_REP_1P_0620 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0620_CKGEN01_V004_REG_CKG_I_P2_PIX_REP_1P_0620 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0620_CKGEN01_V004_REG_CKG_S_P2_PIX_REP_1P_0620 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0628_CKGEN01_V004 (CKGEN01_V004 + 0x628)
	#define REG_0628_CKGEN01_V004_REG_CKG_G_P2_PIX_TMDSPLL_0628 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0628_CKGEN01_V004_REG_CKG_I_P2_PIX_TMDSPLL_0628 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0628_CKGEN01_V004_REG_CKG_S_P2_PIX_TMDSPLL_0628 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0638_CKGEN01_V004 (CKGEN01_V004 + 0x638)
	#define REG_0638_CKGEN01_V004_REG_CKG_G_P2_PIX_XC_MUX_0638 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0638_CKGEN01_V004_REG_CKG_I_P2_PIX_XC_MUX_0638 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0638_CKGEN01_V004_REG_CKG_S_P2_PIX_XC_MUX_0638 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0640_CKGEN01_V004 (CKGEN01_V004 + 0x640)
	#define REG_0640_CKGEN01_V004_REG_CKG_G_P2_TIMING_DET_DEC_0640 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0640_CKGEN01_V004_REG_CKG_I_P2_TIMING_DET_DEC_0640 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0640_CKGEN01_V004_REG_CKG_S_P2_TIMING_DET_DEC_0640 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0648_CKGEN01_V004 (CKGEN01_V004 + 0x648)
	#define REG_0648_CKGEN01_V004_REG_CKG_G_P2_TIMING_DET_DEP_0648 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0648_CKGEN01_V004_REG_CKG_I_P2_TIMING_DET_DEP_0648 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0648_CKGEN01_V004_REG_CKG_S_P2_TIMING_DET_DEP_0648 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0650_CKGEN01_V004 (CKGEN01_V004 + 0x650)
	#define REG_0650_CKGEN01_V004_REG_CKG_G_P2_TIMING_DET_DTOP_0650 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0650_CKGEN01_V004_REG_CKG_I_P2_TIMING_DET_DTOP_0650 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0650_CKGEN01_V004_REG_CKG_S_P2_TIMING_DET_DTOP_0650 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0658_CKGEN01_V004 (CKGEN01_V004 + 0x658)
	#define REG_0658_CKGEN01_V004_REG_CKG_G_P2_TMDS_FRL_8P_0658 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0658_CKGEN01_V004_REG_CKG_I_P2_TMDS_FRL_8P_0658 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0658_CKGEN01_V004_REG_CKG_S_P2_TMDS_FRL_8P_0658 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0660_CKGEN01_V004 (CKGEN01_V004 + 0x660)
	#define REG_0660_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP_1P_0660 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0660_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP_1P_0660 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0660_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP_1P_0660 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0668_CKGEN01_V004 (CKGEN01_V004 + 0x668)
	#define REG_0668_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP_4P_0668 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0668_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP_4P_0668 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0668_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP_4P_0668 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0670_CKGEN01_V004 (CKGEN01_V004 + 0x670)
	#define REG_0670_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP_8P_0670 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0670_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP_8P_0670 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0670_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP_8P_0670 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0678_CKGEN01_V004 (CKGEN01_V004 + 0x678)
	#define REG_0678_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP_MUX_0678 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0678_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP_MUX_0678 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0678_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP_MUX_0678 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0680_CKGEN01_V004 (CKGEN01_V004 + 0x680)
	#define REG_0680_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDMI_1P_0680 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0680_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDMI_1P_0680 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0680_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDMI_1P_0680 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0688_CKGEN01_V004 (CKGEN01_V004 + 0x688)
	#define REG_0688_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDMI_8P_0688 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0688_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDMI_8P_0688 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0688_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDMI_8P_0688 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0690_CKGEN01_V004 (CKGEN01_V004 + 0x690)
	#define REG_0690_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDMI_MUX_0690 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0690_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDMI_MUX_0690 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0690_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDMI_MUX_0690 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0698_CKGEN01_V004 (CKGEN01_V004 + 0x698)
	#define REG_0698_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEC_MISC_0_0698 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0698_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEC_MISC_0_0698 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0698_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEC_MISC_0_0698 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06A0_CKGEN01_V004 (CKGEN01_V004 + 0x6A0)
	#define REG_06A0_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEC_MISC_0_0_06A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06A0_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEC_MISC_0_0_06A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06A0_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEC_MISC_0_0_06A0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06A8_CKGEN01_V004 (CKGEN01_V004 + 0x6A8)
	#define REG_06A8_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEC_MISC_1_06A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06A8_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEC_MISC_1_06A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06A8_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEC_MISC_1_06A8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06B0_CKGEN01_V004 (CKGEN01_V004 + 0x6B0)
	#define REG_06B0_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEC_MISC_1_0_06B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06B0_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEC_MISC_1_0_06B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06B0_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEC_MISC_1_0_06B0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06B8_CKGEN01_V004 (CKGEN01_V004 + 0x6B8)
	#define REG_06B8_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEP_MISC_0_06B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06B8_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEP_MISC_0_06B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06B8_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEP_MISC_0_06B8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06C0_CKGEN01_V004 (CKGEN01_V004 + 0x6C0)
	#define REG_06C0_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEP_MISC_0_0_06C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06C0_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEP_MISC_0_0_06C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06C0_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEP_MISC_0_0_06C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06C8_CKGEN01_V004 (CKGEN01_V004 + 0x6C8)
	#define REG_06C8_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEP_MISC_1_06C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06C8_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEP_MISC_1_06C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06C8_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEP_MISC_1_06C8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06D0_CKGEN01_V004 (CKGEN01_V004 + 0x6D0)
	#define REG_06D0_CKGEN01_V004_REG_CKG_G_P3_CLK_DET_DEP_MISC_1_0_06D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06D0_CKGEN01_V004_REG_CKG_I_P3_CLK_DET_DEP_MISC_1_0_06D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06D0_CKGEN01_V004_REG_CKG_S_P3_CLK_DET_DEP_MISC_1_0_06D0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06D8_CKGEN01_V004 (CKGEN01_V004 + 0x6D8)
	#define REG_06D8_CKGEN01_V004_REG_CKG_G_P3_LINK_06D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06D8_CKGEN01_V004_REG_CKG_I_P3_LINK_06D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06D8_CKGEN01_V004_REG_CKG_S_P3_LINK_06D8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06E0_CKGEN01_V004 (CKGEN01_V004 + 0x6E0)
	#define REG_06E0_CKGEN01_V004_REG_CKG_G_P3_PIX_1P_06E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06E0_CKGEN01_V004_REG_CKG_I_P3_PIX_1P_06E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06E0_CKGEN01_V004_REG_CKG_S_P3_PIX_1P_06E0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06E8_CKGEN01_V004 (CKGEN01_V004 + 0x6E8)
	#define REG_06E8_CKGEN01_V004_REG_CKG_G_P3_PIX_8P_06E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06E8_CKGEN01_V004_REG_CKG_I_P3_PIX_8P_06E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06E8_CKGEN01_V004_REG_CKG_S_P3_PIX_8P_06E8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06F0_CKGEN01_V004 (CKGEN01_V004 + 0x6F0)
	#define REG_06F0_CKGEN01_V004_REG_CKG_G_P3_PIX_DC_MUX_06F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06F0_CKGEN01_V004_REG_CKG_I_P3_PIX_DC_MUX_06F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06F0_CKGEN01_V004_REG_CKG_S_P3_PIX_DC_MUX_06F0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_06F8_CKGEN01_V004 (CKGEN01_V004 + 0x6F8)
	#define REG_06F8_CKGEN01_V004_REG_CKG_G_P3_PIX_RCV_MUX_06F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06F8_CKGEN01_V004_REG_CKG_I_P3_PIX_RCV_MUX_06F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_06F8_CKGEN01_V004_REG_CKG_S_P3_PIX_RCV_MUX_06F8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0700_CKGEN01_V004 (CKGEN01_V004 + 0x700)
	#define REG_0700_CKGEN01_V004_REG_CKG_G_P3_PIX_REP_1P_0700 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0700_CKGEN01_V004_REG_CKG_I_P3_PIX_REP_1P_0700 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0700_CKGEN01_V004_REG_CKG_S_P3_PIX_REP_1P_0700 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0708_CKGEN01_V004 (CKGEN01_V004 + 0x708)
	#define REG_0708_CKGEN01_V004_REG_CKG_G_P3_PIX_TMDSPLL_0708 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0708_CKGEN01_V004_REG_CKG_I_P3_PIX_TMDSPLL_0708 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0708_CKGEN01_V004_REG_CKG_S_P3_PIX_TMDSPLL_0708 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0718_CKGEN01_V004 (CKGEN01_V004 + 0x718)
	#define REG_0718_CKGEN01_V004_REG_CKG_G_P3_PIX_XC_MUX_0718 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0718_CKGEN01_V004_REG_CKG_I_P3_PIX_XC_MUX_0718 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0718_CKGEN01_V004_REG_CKG_S_P3_PIX_XC_MUX_0718 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0720_CKGEN01_V004 (CKGEN01_V004 + 0x720)
	#define REG_0720_CKGEN01_V004_REG_CKG_G_P3_TIMING_DET_DEC_0720 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0720_CKGEN01_V004_REG_CKG_I_P3_TIMING_DET_DEC_0720 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0720_CKGEN01_V004_REG_CKG_S_P3_TIMING_DET_DEC_0720 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0728_CKGEN01_V004 (CKGEN01_V004 + 0x728)
	#define REG_0728_CKGEN01_V004_REG_CKG_G_P3_TIMING_DET_DEP_0728 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0728_CKGEN01_V004_REG_CKG_I_P3_TIMING_DET_DEP_0728 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0728_CKGEN01_V004_REG_CKG_S_P3_TIMING_DET_DEP_0728 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0730_CKGEN01_V004 (CKGEN01_V004 + 0x730)
	#define REG_0730_CKGEN01_V004_REG_CKG_G_P3_TIMING_DET_DTOP_0730 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0730_CKGEN01_V004_REG_CKG_I_P3_TIMING_DET_DTOP_0730 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0730_CKGEN01_V004_REG_CKG_S_P3_TIMING_DET_DTOP_0730 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0738_CKGEN01_V004 (CKGEN01_V004 + 0x738)
	#define REG_0738_CKGEN01_V004_REG_CKG_G_P3_TMDS_FRL_8P_0738 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0738_CKGEN01_V004_REG_CKG_I_P3_TMDS_FRL_8P_0738 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0738_CKGEN01_V004_REG_CKG_S_P3_TMDS_FRL_8P_0738 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0740_CKGEN01_V004 (CKGEN01_V004 + 0x740)
	#define REG_0740_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP_1P_0740 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0740_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP_1P_0740 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0740_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP_1P_0740 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0748_CKGEN01_V004 (CKGEN01_V004 + 0x748)
	#define REG_0748_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP_4P_0748 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0748_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP_4P_0748 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0748_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP_4P_0748 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0750_CKGEN01_V004 (CKGEN01_V004 + 0x750)
	#define REG_0750_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP_8P_0750 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0750_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP_8P_0750 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0750_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP_8P_0750 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0758_CKGEN01_V004 (CKGEN01_V004 + 0x758)
	#define REG_0758_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP_MUX_0758 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0758_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP_MUX_0758 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0758_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP_MUX_0758 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0760_CKGEN01_V004 (CKGEN01_V004 + 0x760)
	#define REG_0760_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDMI_1P_0760 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0760_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDMI_1P_0760 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0760_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDMI_1P_0760 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0768_CKGEN01_V004 (CKGEN01_V004 + 0x768)
	#define REG_0768_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDMI_8P_0768 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0768_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDMI_8P_0768 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0768_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDMI_8P_0768 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0770_CKGEN01_V004 (CKGEN01_V004 + 0x770)
	#define REG_0770_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDMI_MUX_0770 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0770_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDMI_MUX_0770 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0770_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDMI_MUX_0770 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0778_CKGEN01_V004 (CKGEN01_V004 + 0x778)
	#define REG_0778_CKGEN01_V004_REG_CKG_G_PIX_TMDSPLL_DSCD_0778 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0778_CKGEN01_V004_REG_CKG_I_PIX_TMDSPLL_DSCD_0778 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0778_CKGEN01_V004_REG_CKG_S_PIX_TMDSPLL_DSCD_0778 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0780_CKGEN01_V004 (CKGEN01_V004 + 0x780)
	#define REG_0780_CKGEN01_V004_REG_CKG_G_PIX_XC_S0_0780 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0780_CKGEN01_V004_REG_CKG_I_PIX_XC_S0_0780 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0780_CKGEN01_V004_REG_CKG_S_PIX_XC_S0_0780 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0788_CKGEN01_V004 (CKGEN01_V004 + 0x788)
	#define REG_0788_CKGEN01_V004_REG_CKG_G_PIX_XC_S1_0788 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0788_CKGEN01_V004_REG_CKG_I_PIX_XC_S1_0788 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0788_CKGEN01_V004_REG_CKG_S_PIX_XC_S1_0788 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0790_CKGEN01_V004 (CKGEN01_V004 + 0x790)
	#define REG_0790_CKGEN01_V004_REG_CKG_G_R2_HDMI_0790 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0790_CKGEN01_V004_REG_CKG_I_R2_HDMI_0790 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0798_CKGEN01_V004 (CKGEN01_V004 + 0x798)
	#define REG_0798_CKGEN01_V004_REG_CKG_G_TIMING_DET_DTOP_0798 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0798_CKGEN01_V004_REG_CKG_I_TIMING_DET_DTOP_0798 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0798_CKGEN01_V004_REG_CKG_S_TIMING_DET_DTOP_0798 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_07A0_CKGEN01_V004 (CKGEN01_V004 + 0x7A0)
	#define REG_07A0_CKGEN01_V004_REG_CKG_G_TMDS_AUDIO_S0_07A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07A0_CKGEN01_V004_REG_CKG_I_TMDS_AUDIO_S0_07A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07A0_CKGEN01_V004_REG_CKG_S_TMDS_AUDIO_S0_07A0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_07A8_CKGEN01_V004 (CKGEN01_V004 + 0x7A8)
	#define REG_07A8_CKGEN01_V004_REG_CKG_G_TMDS_AUDIO_S0_0_07A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07A8_CKGEN01_V004_REG_CKG_I_TMDS_AUDIO_S0_0_07A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07A8_CKGEN01_V004_REG_CKG_S_TMDS_AUDIO_S0_0_07A8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_07B0_CKGEN01_V004 (CKGEN01_V004 + 0x7B0)
	#define REG_07B0_CKGEN01_V004_REG_CKG_G_TMDS_AUDIO_S1_07B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07B0_CKGEN01_V004_REG_CKG_I_TMDS_AUDIO_S1_07B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07B0_CKGEN01_V004_REG_CKG_S_TMDS_AUDIO_S1_07B0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_07B8_CKGEN01_V004 (CKGEN01_V004 + 0x7B8)
	#define REG_07B8_CKGEN01_V004_REG_CKG_G_TMDS_AUDIO_S1_0_07B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07B8_CKGEN01_V004_REG_CKG_I_TMDS_AUDIO_S1_0_07B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07B8_CKGEN01_V004_REG_CKG_S_TMDS_AUDIO_S1_0_07B8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_07C0_CKGEN01_V004 (CKGEN01_V004 + 0x7C0)
	#define REG_07C0_CKGEN01_V004_REG_CKG_G_TMDS_DSCD_07C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07C0_CKGEN01_V004_REG_CKG_I_TMDS_DSCD_07C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07C0_CKGEN01_V004_REG_CKG_S_TMDS_DSCD_07C0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_07C8_CKGEN01_V004 (CKGEN01_V004 + 0x7C8)
	#define REG_07C8_CKGEN01_V004_REG_CKG_G_XTAL_24_07C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07C8_CKGEN01_V004_REG_CKG_I_XTAL_24_07C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07D0_CKGEN01_V004 (CKGEN01_V004 + 0x7D0)
	#define REG_07D0_CKGEN01_V004_REG_CKG_G_XTAL_HDMI_12_07D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07D0_CKGEN01_V004_REG_CKG_I_XTAL_HDMI_12_07D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07D0_CKGEN01_V004_REG_CKG_S_XTAL_HDMI_12_07D0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_07D8_CKGEN01_V004 (CKGEN01_V004 + 0x7D8)
	#define REG_07D8_CKGEN01_V004_REG_CKG_G_P0_TMDSPLL_TEST_DIG_07D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07D8_CKGEN01_V004_REG_CKG_I_P0_TMDSPLL_TEST_DIG_07D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07D8_CKGEN01_V004_REG_CKG_S_P0_TMDSPLL_TEST_DIG_07D8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_07E0_CKGEN01_V004 (CKGEN01_V004 + 0x7E0)
	#define REG_07E0_CKGEN01_V004_REG_CKG_G_P1_TMDSPLL_TEST_DIG_07E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07E0_CKGEN01_V004_REG_CKG_I_P1_TMDSPLL_TEST_DIG_07E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07E0_CKGEN01_V004_REG_CKG_S_P1_TMDSPLL_TEST_DIG_07E0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_07E8_CKGEN01_V004 (CKGEN01_V004 + 0x7E8)
	#define REG_07E8_CKGEN01_V004_REG_CKG_G_P2_TMDSPLL_TEST_DIG_07E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07E8_CKGEN01_V004_REG_CKG_I_P2_TMDSPLL_TEST_DIG_07E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07E8_CKGEN01_V004_REG_CKG_S_P2_TMDSPLL_TEST_DIG_07E8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_07F0_CKGEN01_V004 (CKGEN01_V004 + 0x7F0)
	#define REG_07F0_CKGEN01_V004_REG_CKG_G_P3_TMDSPLL_TEST_DIG_07F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07F0_CKGEN01_V004_REG_CKG_I_P3_TMDSPLL_TEST_DIG_07F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07F0_CKGEN01_V004_REG_CKG_S_P3_TMDSPLL_TEST_DIG_07F0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_07F8_CKGEN01_V004 (CKGEN01_V004 + 0x7F8)
	#define REG_07F8_CKGEN01_V004_REG_CKG_G_128FS_FB_S0_FF_07F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07F8_CKGEN01_V004_REG_CKG_I_128FS_FB_S0_FF_07F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07F8_CKGEN01_V004_REG_CKG_S_128FS_FB_S0_FF_07F8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0800_CKGEN01_V004 (CKGEN01_V004 + 0x800)
	#define REG_0800_CKGEN01_V004_REG_CKG_G_128FS_FB_S1_FF_0800 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0800_CKGEN01_V004_REG_CKG_I_128FS_FB_S1_FF_0800 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0800_CKGEN01_V004_REG_CKG_S_128FS_FB_S1_FF_0800 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0808_CKGEN01_V004 (CKGEN01_V004 + 0x808)
	#define REG_0808_CKGEN01_V004_REG_CKG_G_PIX_PKT_0808 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0808_CKGEN01_V004_REG_CKG_I_PIX_PKT_0808 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0808_CKGEN01_V004_REG_CKG_S_PIX_PKT_0808 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0810_CKGEN01_V004 (CKGEN01_V004 + 0x810)
	#define REG_0810_CKGEN01_V004_REG_CKG_G_TMDS_PKT_0810 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0810_CKGEN01_V004_REG_CKG_I_TMDS_PKT_0810 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0810_CKGEN01_V004_REG_CKG_S_TMDS_PKT_0810 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0818_CKGEN01_V004 (CKGEN01_V004 + 0x818)
	#define REG_0818_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP_CIPHER_1P_0818 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0818_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP_CIPHER_1P_0818 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0818_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP_CIPHER_1P_0818 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0818_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP_CIPHER_8P_0818 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0818_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP_CIPHER_8P_0818 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0818_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP_CIPHER_8P_0818 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0820_CKGEN01_V004 (CKGEN01_V004 + 0x820)
	#define REG_0820_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP_CIPHER_1P_0820 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0820_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP_CIPHER_1P_0820 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0820_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP_CIPHER_1P_0820 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0820_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP_CIPHER_8P_0820 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0820_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP_CIPHER_8P_0820 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0820_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP_CIPHER_8P_0820 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0828_CKGEN01_V004 (CKGEN01_V004 + 0x828)
	#define REG_0828_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP_CIPHER_1P_0828 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0828_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP_CIPHER_1P_0828 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0828_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP_CIPHER_1P_0828 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0828_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP_CIPHER_8P_0828 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0828_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP_CIPHER_8P_0828 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0828_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP_CIPHER_8P_0828 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0830_CKGEN01_V004 (CKGEN01_V004 + 0x830)
	#define REG_0830_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP_CIPHER_1P_0830 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0830_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP_CIPHER_1P_0830 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0830_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP_CIPHER_1P_0830 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0830_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP_CIPHER_8P_0830 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0830_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP_CIPHER_8P_0830 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0830_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP_CIPHER_8P_0830 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0834_CKGEN01_V004 (CKGEN01_V004 + 0x834)
	#define REG_0834_CKGEN01_V004_REG_CKG_G_P0_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0834_CKGEN01_V004_REG_CKG_I_P0_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0834_CKGEN01_V004_REG_CKG_S_P0_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0834_CKGEN01_V004_REG_CKG_G_P1_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0834_CKGEN01_V004_REG_CKG_I_P1_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0834_CKGEN01_V004_REG_CKG_S_P1_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0834_CKGEN01_V004_REG_CKG_G_P2_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0834_CKGEN01_V004_REG_CKG_I_P2_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0834_CKGEN01_V004_REG_CKG_S_P2_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0834_CKGEN01_V004_REG_CKG_G_P3_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0834_CKGEN01_V004_REG_CKG_I_P3_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0834_CKGEN01_V004_REG_CKG_S_P3_TMDS_HDCP14_CIPHER_1P_0834 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_08E0_CKGEN01_V004 (CKGEN01_V004 + 0x8E0)
	#define REG_08E0_CKGEN01_V004_REG_CKG_G_DET_RCLK_08E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08E0_CKGEN01_V004_REG_CKG_I_DET_RCLK_08E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_08E0_CKGEN01_V004_REG_CKG_S_DET_RCLK_08E0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_08E8_CKGEN01_V004 (CKGEN01_V004 + 0x8E8)
	#define REG_08E8_CKGEN01_V004_REG_CKG_G_DET_WCLK_08E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08E8_CKGEN01_V004_REG_CKG_I_DET_WCLK_08E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_08E8_CKGEN01_V004_REG_CKG_S_DET_WCLK_08E8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_08F0_CKGEN01_V004 (CKGEN01_V004 + 0x8F0)
	#define REG_08F0_CKGEN01_V004_REG_CKG_G_LPLL_ODCLK_08F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08F0_CKGEN01_V004_REG_CKG_I_LPLL_ODCLK_08F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_08F0_CKGEN01_V004_REG_CKG_S_LPLL_ODCLK_08F0 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_08F8_CKGEN01_V004 (CKGEN01_V004 + 0x8F8)
	#define REG_08F8_CKGEN01_V004_REG_CKG_G_LPLL_ODCLK_NODIV_08F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08F8_CKGEN01_V004_REG_CKG_I_LPLL_ODCLK_NODIV_08F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0900_CKGEN01_V004 (CKGEN01_V004 + 0x900)
	#define REG_0900_CKGEN01_V004_REG_CKG_G_LPLL_SYN_432_0900 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0900_CKGEN01_V004_REG_CKG_I_LPLL_SYN_432_0900 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0910_CKGEN01_V004 (CKGEN01_V004 + 0x910)
	#define REG_0910_CKGEN01_V004_REG_CKG_G_MOD_A_ODCLK_0910 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0910_CKGEN01_V004_REG_CKG_I_MOD_A_ODCLK_0910 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0910_CKGEN01_V004_REG_CKG_S_MOD_A_ODCLK_0910 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0918_CKGEN01_V004 (CKGEN01_V004 + 0x918)
	#define REG_0918_CKGEN01_V004_REG_CKG_G_MOD_D_ODCLK_0918 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0918_CKGEN01_V004_REG_CKG_I_MOD_D_ODCLK_0918 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0918_CKGEN01_V004_REG_CKG_S_MOD_D_ODCLK_0918 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_091C_CKGEN01_V004 (CKGEN01_V004 + 0x91C)
	#define REG_091C_CKGEN01_V004_REG_CKG_G_MOD_O_SR_WCLK_091C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_091C_CKGEN01_V004_REG_CKG_I_MOD_O_SR_WCLK_091C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_091C_CKGEN01_V004_REG_CKG_S_MOD_O_SR_WCLK_091C Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0920_CKGEN01_V004 (CKGEN01_V004 + 0x920)
	#define REG_0920_CKGEN01_V004_REG_CKG_G_MOD_V1_SR_WCLK_0920 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0920_CKGEN01_V004_REG_CKG_I_MOD_V1_SR_WCLK_0920 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0920_CKGEN01_V004_REG_CKG_S_MOD_V1_SR_WCLK_0920 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0924_CKGEN01_V004 (CKGEN01_V004 + 0x924)
	#define REG_0924_CKGEN01_V004_REG_CKG_G_MOD_V2_SR_WCLK_0924 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0924_CKGEN01_V004_REG_CKG_I_MOD_V2_SR_WCLK_0924 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0924_CKGEN01_V004_REG_CKG_S_MOD_V2_SR_WCLK_0924 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0928_CKGEN01_V004 (CKGEN01_V004 + 0x928)
	#define REG_0928_CKGEN01_V004_REG_CKG_G_O_MOD_SR_RCLK_0928 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0928_CKGEN01_V004_REG_CKG_I_O_MOD_SR_RCLK_0928 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0928_CKGEN01_V004_REG_CKG_S_O_MOD_SR_RCLK_0928 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0930_CKGEN01_V004 (CKGEN01_V004 + 0x930)
	#define REG_0930_CKGEN01_V004_REG_CKG_G_O_ODCLK_0930 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0930_CKGEN01_V004_REG_CKG_I_O_ODCLK_0930 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0930_CKGEN01_V004_REG_CKG_S_O_ODCLK_0930 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0938_CKGEN01_V004 (CKGEN01_V004 + 0x938)
	#define REG_0938_CKGEN01_V004_REG_CKG_G_O_ODCLK_STG1_0938 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0938_CKGEN01_V004_REG_CKG_I_O_ODCLK_STG1_0938 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0938_CKGEN01_V004_REG_CKG_S_O_ODCLK_STG1_0938 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0940_CKGEN01_V004 (CKGEN01_V004 + 0x940)
	#define REG_0940_CKGEN01_V004_REG_CKG_G_O_ODCLK_STG2_0940 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0940_CKGEN01_V004_REG_CKG_I_O_ODCLK_STG2_0940 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0940_CKGEN01_V004_REG_CKG_S_O_ODCLK_STG2_0940 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0948_CKGEN01_V004 (CKGEN01_V004 + 0x948)
	#define REG_0948_CKGEN01_V004_REG_CKG_G_O_ODCLK_STG3_0948 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0948_CKGEN01_V004_REG_CKG_I_O_ODCLK_STG3_0948 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0948_CKGEN01_V004_REG_CKG_S_O_ODCLK_STG3_0948 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0950_CKGEN01_V004 (CKGEN01_V004 + 0x950)
	#define REG_0950_CKGEN01_V004_REG_CKG_G_O_ODCLK_STG4_0950 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0950_CKGEN01_V004_REG_CKG_I_O_ODCLK_STG4_0950 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0950_CKGEN01_V004_REG_CKG_S_O_ODCLK_STG4_0950 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0958_CKGEN01_V004 (CKGEN01_V004 + 0x958)
	#define REG_0958_CKGEN01_V004_REG_CKG_G_O_ODCLK_STG5_0958 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0958_CKGEN01_V004_REG_CKG_I_O_ODCLK_STG5_0958 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0958_CKGEN01_V004_REG_CKG_S_O_ODCLK_STG5_0958 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0960_CKGEN01_V004 (CKGEN01_V004 + 0x960)
	#define REG_0960_CKGEN01_V004_REG_CKG_G_O_ODCLK_STG6_0960 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0960_CKGEN01_V004_REG_CKG_I_O_ODCLK_STG6_0960 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0960_CKGEN01_V004_REG_CKG_S_O_ODCLK_STG6_0960 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0968_CKGEN01_V004 (CKGEN01_V004 + 0x968)
	#define REG_0968_CKGEN01_V004_REG_CKG_G_PWM_0968 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0968_CKGEN01_V004_REG_CKG_I_PWM_0968 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0968_CKGEN01_V004_REG_CKG_S_PWM_0968 Fld(5,2,AC_MSKB0)//[6:2]
#define REG_0970_CKGEN01_V004 (CKGEN01_V004 + 0x970)
	#define REG_0970_CKGEN01_V004_REG_CKG_G_V1_MOD_SR_RCLK_0970 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0970_CKGEN01_V004_REG_CKG_I_V1_MOD_SR_RCLK_0970 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0970_CKGEN01_V004_REG_CKG_S_V1_MOD_SR_RCLK_0970 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0978_CKGEN01_V004 (CKGEN01_V004 + 0x978)
	#define REG_0978_CKGEN01_V004_REG_CKG_G_V1_ODCLK_0978 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0978_CKGEN01_V004_REG_CKG_I_V1_ODCLK_0978 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0978_CKGEN01_V004_REG_CKG_S_V1_ODCLK_0978 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0980_CKGEN01_V004 (CKGEN01_V004 + 0x980)
	#define REG_0980_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG1_0980 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0980_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG1_0980 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0980_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG1_0980 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0988_CKGEN01_V004 (CKGEN01_V004 + 0x988)
	#define REG_0988_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG2_0988 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0988_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG2_0988 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0988_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG2_0988 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0990_CKGEN01_V004 (CKGEN01_V004 + 0x990)
	#define REG_0990_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG3_0990 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0990_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG3_0990 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0990_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG3_0990 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0998_CKGEN01_V004 (CKGEN01_V004 + 0x998)
	#define REG_0998_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG4_0998 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0998_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG4_0998 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0998_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG4_0998 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09A0_CKGEN01_V004 (CKGEN01_V004 + 0x9A0)
	#define REG_09A0_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG5_09A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09A0_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG5_09A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09A0_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG5_09A0 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09A8_CKGEN01_V004 (CKGEN01_V004 + 0x9A8)
	#define REG_09A8_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG6_09A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09A8_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG6_09A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09A8_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG6_09A8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09B0_CKGEN01_V004 (CKGEN01_V004 + 0x9B0)
	#define REG_09B0_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG7_09B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09B0_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG7_09B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09B0_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG7_09B0 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09B8_CKGEN01_V004 (CKGEN01_V004 + 0x9B8)
	#define REG_09B8_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG8_09B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09B8_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG8_09B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09B8_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG8_09B8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09C0_CKGEN01_V004 (CKGEN01_V004 + 0x9C0)
	#define REG_09C0_CKGEN01_V004_REG_CKG_G_V2_MOD_SR_RCLK_09C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09C0_CKGEN01_V004_REG_CKG_I_V2_MOD_SR_RCLK_09C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09C0_CKGEN01_V004_REG_CKG_S_V2_MOD_SR_RCLK_09C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_09C8_CKGEN01_V004 (CKGEN01_V004 + 0x9C8)
	#define REG_09C8_CKGEN01_V004_REG_CKG_G_V2_ODCLK_09C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09C8_CKGEN01_V004_REG_CKG_I_V2_ODCLK_09C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09C8_CKGEN01_V004_REG_CKG_S_V2_ODCLK_09C8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09D0_CKGEN01_V004 (CKGEN01_V004 + 0x9D0)
	#define REG_09D0_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG1_09D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09D0_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG1_09D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09D0_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG1_09D0 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09D8_CKGEN01_V004 (CKGEN01_V004 + 0x9D8)
	#define REG_09D8_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG2_09D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09D8_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG2_09D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09D8_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG2_09D8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09E0_CKGEN01_V004 (CKGEN01_V004 + 0x9E0)
	#define REG_09E0_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG3_09E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09E0_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG3_09E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09E0_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG3_09E0 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09E8_CKGEN01_V004 (CKGEN01_V004 + 0x9E8)
	#define REG_09E8_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG4_09E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09E8_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG4_09E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09E8_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG4_09E8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09F0_CKGEN01_V004 (CKGEN01_V004 + 0x9F0)
	#define REG_09F0_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG5_09F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09F0_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG5_09F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09F0_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG5_09F0 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_09F8_CKGEN01_V004 (CKGEN01_V004 + 0x9F8)
	#define REG_09F8_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG6_09F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09F8_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG6_09F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_09F8_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG6_09F8 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0A00_CKGEN01_V004 (CKGEN01_V004 + 0xA00)
	#define REG_0A00_CKGEN01_V004_REG_CKG_G_V2_ODCLK_STG7_0A00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A00_CKGEN01_V004_REG_CKG_I_V2_ODCLK_STG7_0A00 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A00_CKGEN01_V004_REG_CKG_S_V2_ODCLK_STG7_0A00 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0A08_CKGEN01_V004 (CKGEN01_V004 + 0xA08)
	#define REG_0A08_CKGEN01_V004_REG_CKG_G_O_MOD_SR_RCLK_FINIAL_0A08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A08_CKGEN01_V004_REG_CKG_I_O_MOD_SR_RCLK_FINIAL_0A08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A08_CKGEN01_V004_REG_CKG_S_O_MOD_SR_RCLK_FINIAL_0A08 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A10_CKGEN01_V004 (CKGEN01_V004 + 0xA10)
	#define REG_0A10_CKGEN01_V004_REG_CKG_G_O_MOD_SR_RCLK_PRE0_0A10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A10_CKGEN01_V004_REG_CKG_I_O_MOD_SR_RCLK_PRE0_0A10 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A10_CKGEN01_V004_REG_CKG_S_O_MOD_SR_RCLK_PRE0_0A10 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A18_CKGEN01_V004 (CKGEN01_V004 + 0xA18)
	#define REG_0A18_CKGEN01_V004_REG_CKG_G_O_MOD_SR_RCLK_PRE1_0A18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A18_CKGEN01_V004_REG_CKG_I_O_MOD_SR_RCLK_PRE1_0A18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A18_CKGEN01_V004_REG_CKG_S_O_MOD_SR_RCLK_PRE1_0A18 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A20_CKGEN01_V004 (CKGEN01_V004 + 0xA20)
	#define REG_0A20_CKGEN01_V004_REG_CKG_G_V1_MOD_SR_RCLK_FINIAL_0A20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A20_CKGEN01_V004_REG_CKG_I_V1_MOD_SR_RCLK_FINIAL_0A20 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A20_CKGEN01_V004_REG_CKG_S_V1_MOD_SR_RCLK_FINIAL_0A20 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A28_CKGEN01_V004 (CKGEN01_V004 + 0xA28)
	#define REG_0A28_CKGEN01_V004_REG_CKG_G_V1_MOD_SR_RCLK_PRE0_0A28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A28_CKGEN01_V004_REG_CKG_I_V1_MOD_SR_RCLK_PRE0_0A28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A28_CKGEN01_V004_REG_CKG_S_V1_MOD_SR_RCLK_PRE0_0A28 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A30_CKGEN01_V004 (CKGEN01_V004 + 0xA30)
	#define REG_0A30_CKGEN01_V004_REG_CKG_G_V1_MOD_SR_RCLK_PRE1_0A30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A30_CKGEN01_V004_REG_CKG_I_V1_MOD_SR_RCLK_PRE1_0A30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A30_CKGEN01_V004_REG_CKG_S_V1_MOD_SR_RCLK_PRE1_0A30 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A38_CKGEN01_V004 (CKGEN01_V004 + 0xA38)
	#define REG_0A38_CKGEN01_V004_REG_CKG_G_V2_MOD_SR_RCLK_FINIAL_0A38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A38_CKGEN01_V004_REG_CKG_I_V2_MOD_SR_RCLK_FINIAL_0A38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A38_CKGEN01_V004_REG_CKG_S_V2_MOD_SR_RCLK_FINIAL_0A38 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A40_CKGEN01_V004 (CKGEN01_V004 + 0xA40)
	#define REG_0A40_CKGEN01_V004_REG_CKG_G_V2_MOD_SR_RCLK_PRE0_0A40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A40_CKGEN01_V004_REG_CKG_I_V2_MOD_SR_RCLK_PRE0_0A40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A40_CKGEN01_V004_REG_CKG_S_V2_MOD_SR_RCLK_PRE0_0A40 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A48_CKGEN01_V004 (CKGEN01_V004 + 0xA48)
	#define REG_0A48_CKGEN01_V004_REG_CKG_G_V2_MOD_SR_RCLK_PRE1_0A48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A48_CKGEN01_V004_REG_CKG_I_V2_MOD_SR_RCLK_PRE1_0A48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A48_CKGEN01_V004_REG_CKG_S_V2_MOD_SR_RCLK_PRE1_0A48 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A50_CKGEN01_V004 (CKGEN01_V004 + 0xA50)
	#define REG_0A50_CKGEN01_V004_REG_CKG_G_IDCLK_MOD_0A50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A50_CKGEN01_V004_REG_CKG_I_IDCLK_MOD_0A50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A50_CKGEN01_V004_REG_CKG_S_IDCLK_MOD_0A50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0A58_CKGEN01_V004 (CKGEN01_V004 + 0xA58)
	#define REG_0A58_CKGEN01_V004_REG_CKG_G_V1_ODCLK_STG9_0A58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A58_CKGEN01_V004_REG_CKG_I_V1_ODCLK_STG9_0A58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A58_CKGEN01_V004_REG_CKG_S_V1_ODCLK_STG9_0A58 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0A60_CKGEN01_V004 (CKGEN01_V004 + 0xA60)
	#define REG_0A60_CKGEN01_V004_REG_CKG_G_XTAL_12M_MOD_0A60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A60_CKGEN01_V004_REG_CKG_I_XTAL_12M_MOD_0A60 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A68_CKGEN01_V004 (CKGEN01_V004 + 0xA68)
	#define REG_0A68_CKGEN01_V004_REG_CKG_G_XTAL_24M_MOD_0A68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A68_CKGEN01_V004_REG_CKG_I_XTAL_24M_MOD_0A68 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A6C_CKGEN01_V004 (CKGEN01_V004 + 0xA6C)
	#define REG_0A6C_CKGEN01_V004_REG_CKG_G_VERIMATRIX_ODCLK_SCTC_0A6C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_I_VERIMATRIX_ODCLK_SCTC_0A6C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_S_VERIMATRIX_ODCLK_SCTC_0A6C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_G_VERIMATRIX_SRAM_0A6C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_I_VERIMATRIX_SRAM_0A6C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_S_VERIMATRIX_SRAM_0A6C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_G_XC_VERIMATRIX_SCTC_0A6C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_I_XC_VERIMATRIX_SCTC_0A6C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A6C_CKGEN01_V004_REG_CKG_S_VERIMATRIX_ODCLK_MUX_0A6C Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0A70_CKGEN01_V004 (CKGEN01_V004 + 0xA70)
	#define REG_0A70_CKGEN01_V004_REG_CKG_G_XC_LINEOD_PAFRC_SCTC_0A70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A70_CKGEN01_V004_REG_CKG_I_XC_LINEOD_PAFRC_SCTC_0A70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A70_CKGEN01_V004_REG_CKG_G_XC_OD_1P_SCTC_0A70 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0A70_CKGEN01_V004_REG_CKG_I_XC_OD_1P_SCTC_0A70 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0A70_CKGEN01_V004_REG_CKG_G_XC_OD_B2P_SCTC_0A70 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A70_CKGEN01_V004_REG_CKG_I_XC_OD_B2P_SCTC_0A70 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A70_CKGEN01_V004_REG_CKG_G_XC_OD_F2P_SCTC_0A70 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0A70_CKGEN01_V004_REG_CKG_I_XC_OD_F2P_SCTC_0A70 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0A78_CKGEN01_V004 (CKGEN01_V004 + 0xA78)
	#define REG_0A78_CKGEN01_V004_REG_CKG_G_XC_OD_PAFRC_SCTC_0A78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A78_CKGEN01_V004_REG_CKG_I_XC_OD_PAFRC_SCTC_0A78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A78_CKGEN01_V004_REG_CKG_G_XC_OD_VAC_SCTC_0A78 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0A78_CKGEN01_V004_REG_CKG_I_XC_OD_VAC_SCTC_0A78 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_0A7C_CKGEN01_V004 (CKGEN01_V004 + 0xA7C)
	#define REG_0A7C_CKGEN01_V004_REG_CKG_G_XC_OD_DELTA_SCIP_0A7C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A7C_CKGEN01_V004_REG_CKG_I_XC_OD_DELTA_SCIP_0A7C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A80_CKGEN01_V004 (CKGEN01_V004 + 0xA80)
	#define REG_0A80_CKGEN01_V004_REG_CKG_G_XC_OD_DELTA_SCBE_0A80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A80_CKGEN01_V004_REG_CKG_I_XC_OD_DELTA_SCBE_0A80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A80_CKGEN01_V004_REG_CKG_G_XC_OD_DELTA_SCSCL_0A80 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A80_CKGEN01_V004_REG_CKG_I_XC_OD_DELTA_SCSCL_0A80 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0A84_CKGEN01_V004 (CKGEN01_V004 + 0xA84)
	#define REG_0A84_CKGEN01_V004_REG_CKG_G_V2_ODCLK_SCBE_TMP_0A84 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A84_CKGEN01_V004_REG_CKG_I_V2_ODCLK_SCBE_TMP_0A84 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A84_CKGEN01_V004_REG_CKG_S_V2_ODCLK_SCBE_TMP_0A84 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_0A88_CKGEN01_V004 (CKGEN01_V004 + 0xA88)
	#define REG_0A88_CKGEN01_V004_REG_V1_V2_O_ODCLK_FROM_MOD_0A88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A88_CKGEN01_V004_REG_MOKONA_O_ODCLK_FROM_MOD_0A88 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A8C_CKGEN01_V004 (CKGEN01_V004 + 0xA8C)
	#define REG_0A8C_CKGEN01_V004_REG_CKG_G_V1_ODCLK_SCIP_TMP_0A8C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A8C_CKGEN01_V004_REG_CKG_I_V1_ODCLK_SCIP_TMP_0A8C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A8C_CKGEN01_V004_REG_CKG_S_V1_ODCLK_SCIP_TMP_0A8C Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_0A8C_CKGEN01_V004_REG_CKG_G_V2_ODCLK_SCIP_TMP_0A8C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A8C_CKGEN01_V004_REG_CKG_I_V2_ODCLK_SCIP_TMP_0A8C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A8C_CKGEN01_V004_REG_CKG_S_V2_ODCLK_SCIP_TMP_0A8C Fld(4,10,AC_MSKB1)//[13:10]
#define REG_0A90_CKGEN01_V004 (CKGEN01_V004 + 0xA90)
	#define REG_0A90_CKGEN01_V004_REG_CKG_G_V1_ODCLK_SCTC_TMP_0A90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A90_CKGEN01_V004_REG_CKG_I_V1_ODCLK_SCTC_TMP_0A90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A90_CKGEN01_V004_REG_CKG_S_V1_ODCLK_SCTC_TMP_0A90 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_0A90_CKGEN01_V004_REG_CKG_G_V1_ODCLK_SCDISP_TMP_0A90 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A90_CKGEN01_V004_REG_CKG_I_V1_ODCLK_SCDISP_TMP_0A90 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A90_CKGEN01_V004_REG_CKG_S_V1_ODCLK_SCDISP_TMP_0A90 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_0A94_CKGEN01_V004 (CKGEN01_V004 + 0xA94)
	#define REG_0A94_CKGEN01_V004_REG_CKG_G_V1_ODCLK_SCBE_TMP_0A94 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A94_CKGEN01_V004_REG_CKG_I_V1_ODCLK_SCBE_TMP_0A94 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A94_CKGEN01_V004_REG_CKG_S_V1_ODCLK_SCBE_TMP_0A94 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_0A98_CKGEN01_V004 (CKGEN01_V004 + 0xA98)
	#define REG_0A98_CKGEN01_V004_REG_CKG_G_V2_ODCLK_SCTC_TMP_0A98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A98_CKGEN01_V004_REG_CKG_I_V2_ODCLK_SCTC_TMP_0A98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A98_CKGEN01_V004_REG_CKG_S_V2_ODCLK_SCTC_TMP_0A98 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_0A98_CKGEN01_V004_REG_CKG_G_B2P_ODCLK_SCIP_TMP_0A98 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A98_CKGEN01_V004_REG_CKG_I_B2P_ODCLK_SCIP_TMP_0A98 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A98_CKGEN01_V004_REG_CKG_S_B2P_ODCLK_SCIP_TMP_0A98 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_0A9C_CKGEN01_V004 (CKGEN01_V004 + 0xA9C)
	#define REG_0A9C_CKGEN01_V004_REG_CKG_G_O_ODCLK_SCTC_TMP_0A9C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A9C_CKGEN01_V004_REG_CKG_I_O_ODCLK_SCTC_TMP_0A9C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0A9C_CKGEN01_V004_REG_CKG_S_O_ODCLK_SCTC_TMP_0A9C Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_0A9C_CKGEN01_V004_REG_CKG_G_1P_ODCLK_SCIP_TMP_0A9C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0A9C_CKGEN01_V004_REG_CKG_I_1P_ODCLK_SCIP_TMP_0A9C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0A9C_CKGEN01_V004_REG_CKG_S_1P_ODCLK_SCIP_TMP_0A9C Fld(4,10,AC_MSKB1)//[13:10]
#define REG_0AA0_CKGEN01_V004 (CKGEN01_V004 + 0xAA0)
	#define REG_0AA0_CKGEN01_V004_REG_CKG_G_XC_DC0_0AA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AA0_CKGEN01_V004_REG_CKG_I_XC_DC0_0AA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AA0_CKGEN01_V004_REG_CKG_S_XC_DC0_0AA0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0AA4_CKGEN01_V004 (CKGEN01_V004 + 0xAA4)
	#define REG_0AA4_CKGEN01_V004_REG_CKG_G_XC_SUB1_DC0_0AA4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AA4_CKGEN01_V004_REG_CKG_I_XC_SUB1_DC0_0AA4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AA4_CKGEN01_V004_REG_CKG_S_XC_SUB1_DC0_0AA4 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0AA8_CKGEN01_V004 (CKGEN01_V004 + 0xAA8)
	#define REG_0AA8_CKGEN01_V004_REG_CKG_G_XC_SUB_DC0_0AA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AA8_CKGEN01_V004_REG_CKG_I_XC_SUB_DC0_0AA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AA8_CKGEN01_V004_REG_CKG_S_XC_SUB_DC0_0AA8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0AAC_CKGEN01_V004 (CKGEN01_V004 + 0xAAC)
	#define REG_0AAC_CKGEN01_V004_REG_CKG_G_XC_VEIN_SCIP_0AAC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AAC_CKGEN01_V004_REG_CKG_I_XC_VEIN_SCIP_0AAC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AAC_CKGEN01_V004_REG_CKG_S_XC_VEIN_SCIP_0AAC Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0AB0_CKGEN01_V004 (CKGEN01_V004 + 0xAB0)
	#define REG_0AB0_CKGEN01_V004_REG_CKG_G_XC_B2R_0AB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AB0_CKGEN01_V004_REG_CKG_I_XC_B2R_0AB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AB0_CKGEN01_V004_REG_CKG_S_XC_B2R_0AB0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0AB4_CKGEN01_V004 (CKGEN01_V004 + 0xAB4)
	#define REG_0AB4_CKGEN01_V004_REG_CKG_G_XC_OD_META_SCTC_0AB4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AB4_CKGEN01_V004_REG_CKG_I_XC_OD_META_SCTC_0AB4 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0AB8_CKGEN01_V004 (CKGEN01_V004 + 0xAB8)
	#define REG_0AB8_CKGEN01_V004_REG_CKG_G_XC_B2R_SUB_0AB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AB8_CKGEN01_V004_REG_CKG_I_XC_B2R_SUB_0AB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AB8_CKGEN01_V004_REG_CKG_S_XC_B2R_SUB_0AB8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0ABC_CKGEN01_V004 (CKGEN01_V004 + 0xABC)
	#define REG_0ABC_CKGEN01_V004_REG_CKG_G_XC_OD_DELTA_META_SCTC_0ABC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0ABC_CKGEN01_V004_REG_CKG_I_XC_OD_DELTA_META_SCTC_0ABC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0AC0_CKGEN01_V004 (CKGEN01_V004 + 0xAC0)
	#define REG_0AC0_CKGEN01_V004_REG_CKG_G_XC_ED_0AC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AC0_CKGEN01_V004_REG_CKG_I_XC_ED_0AC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AC0_CKGEN01_V004_REG_CKG_S_XC_ED_0AC0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0AC4_CKGEN01_V004 (CKGEN01_V004 + 0xAC4)
	#define REG_0AC4_CKGEN01_V004_REG_CKG_G_XC_OD_OSD_META_SCTC_0AC4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AC4_CKGEN01_V004_REG_CKG_I_XC_OD_OSD_META_SCTC_0AC4 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0AC8_CKGEN01_V004 (CKGEN01_V004 + 0xAC8)
	#define REG_0AC8_CKGEN01_V004_REG_CKG_G_XC_FD_0AC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AC8_CKGEN01_V004_REG_CKG_I_XC_FD_0AC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AC8_CKGEN01_V004_REG_CKG_S_XC_FD_0AC8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0AC8_CKGEN01_V004_REG_CKG_G_XC_FD_SCIP_0AC8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0AC8_CKGEN01_V004_REG_CKG_I_XC_FD_SCIP_0AC8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0ACC_CKGEN01_V004 (CKGEN01_V004 + 0xACC)
	#define REG_0ACC_CKGEN01_V004_REG_CKG_G_V1_META_ODCLK_SCTC_0ACC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0ACC_CKGEN01_V004_REG_CKG_I_V1_META_ODCLK_SCTC_0ACC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0ACC_CKGEN01_V004_REG_CKG_S_V1_META_ODCLK_SCTC_0ACC Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0AD0_CKGEN01_V004 (CKGEN01_V004 + 0xAD0)
	#define REG_0AD0_CKGEN01_V004_REG_CKG_G_XC_FN_0AD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AD0_CKGEN01_V004_REG_CKG_I_XC_FN_0AD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AD0_CKGEN01_V004_REG_CKG_S_XC_FN_0AD0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0AD4_CKGEN01_V004 (CKGEN01_V004 + 0xAD4)
	#define REG_0AD4_CKGEN01_V004_REG_CKG_G_V2_META_ODCLK_SCTC_0AD4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AD4_CKGEN01_V004_REG_CKG_I_V2_META_ODCLK_SCTC_0AD4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AD4_CKGEN01_V004_REG_CKG_S_V2_META_ODCLK_SCTC_0AD4 Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0AD8_CKGEN01_V004 (CKGEN01_V004 + 0xAD8)
	#define REG_0AD8_CKGEN01_V004_REG_CKG_G_XC_FS_0AD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AD8_CKGEN01_V004_REG_CKG_I_XC_FS_0AD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AD8_CKGEN01_V004_REG_CKG_S_XC_FS_0AD8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0AD8_CKGEN01_V004_REG_CKG_G_XC_FS_SCIP_0AD8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0AD8_CKGEN01_V004_REG_CKG_I_XC_FS_SCIP_0AD8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0ADC_CKGEN01_V004 (CKGEN01_V004 + 0xADC)
	#define REG_0ADC_CKGEN01_V004_REG_CKG_G_O_META_ODCLK_SCTC_0ADC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0ADC_CKGEN01_V004_REG_CKG_I_O_META_ODCLK_SCTC_0ADC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0ADC_CKGEN01_V004_REG_CKG_S_O_META_ODCLK_SCTC_0ADC Fld(4,2,AC_MSKB0)//[5:2]
#define REG_0AE0_CKGEN01_V004 (CKGEN01_V004 + 0xAE0)
	#define REG_0AE0_CKGEN01_V004_REG_CKG_G_XC_OD_0AE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AE0_CKGEN01_V004_REG_CKG_I_XC_OD_0AE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AE0_CKGEN01_V004_REG_CKG_S_XC_OD_0AE0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0AE0_CKGEN01_V004_REG_CKG_G_XC_OD_SCIP_0AE0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0AE0_CKGEN01_V004_REG_CKG_I_XC_OD_SCIP_0AE0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0AE4_CKGEN01_V004 (CKGEN01_V004 + 0xAE4)
	#define REG_0AE4_CKGEN01_V004_REG_CKG_G_XC_OD_1P_SCIP_0AE4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AE4_CKGEN01_V004_REG_CKG_I_XC_OD_1P_SCIP_0AE4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AE4_CKGEN01_V004_REG_CKG_G_XC_OD_B2P_SCIP_0AE4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0AE4_CKGEN01_V004_REG_CKG_I_XC_OD_B2P_SCIP_0AE4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0AE4_CKGEN01_V004_REG_CKG_G_XC_TTLIN_SCIP_0AE4 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0AE4_CKGEN01_V004_REG_CKG_I_XC_TTLIN_SCIP_0AE4 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0AE4_CKGEN01_V004_REG_CKG_S_XC_TTLIN_SCIP_0AE4 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_0AE8_CKGEN01_V004 (CKGEN01_V004 + 0xAE8)
	#define REG_0AE8_CKGEN01_V004_REG_CKG_G_XC_SLOW_0AE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AE8_CKGEN01_V004_REG_CKG_I_XC_SLOW_0AE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AE8_CKGEN01_V004_REG_CKG_S_XC_SLOW_0AE8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0AF0_CKGEN01_V004 (CKGEN01_V004 + 0xAF0)
	#define REG_0AF0_CKGEN01_V004_REG_CKG_G_XC_SRS_0AF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AF0_CKGEN01_V004_REG_CKG_I_XC_SRS_0AF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AF0_CKGEN01_V004_REG_CKG_S_XC_SRS_0AF0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0AF8_CKGEN01_V004 (CKGEN01_V004 + 0xAF8)
	#define REG_0AF8_CKGEN01_V004_REG_CKG_G_RGB_3DLUT_SCBE_0AF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AF8_CKGEN01_V004_REG_CKG_I_RGB_3DLUT_SCBE_0AF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AF8_CKGEN01_V004_REG_CKG_S_RGB_3DLUT_SCBE_0AF8 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0AF8_CKGEN01_V004_REG_CKG_G_XC_VOP_SCBE_0AF8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0AF8_CKGEN01_V004_REG_CKG_I_XC_VOP_SCBE_0AF8 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0AF8_CKGEN01_V004_REG_CKG_S_XC_VOP_SCBE_0AF8 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_0AFC_CKGEN01_V004 (CKGEN01_V004 + 0xAFC)
	#define REG_0AFC_CKGEN01_V004_REG_CKG_G_XVYCC_SCBE_0AFC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AFC_CKGEN01_V004_REG_CKG_I_XVYCC_SCBE_0AFC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0AFC_CKGEN01_V004_REG_CKG_S_XVYCC_SCBE_0AFC Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0B10_CKGEN01_V004 (CKGEN01_V004 + 0xB10)
	#define REG_0B10_CKGEN01_V004_REG_CKG_G_XC_DC0_SCIP_0B10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B10_CKGEN01_V004_REG_CKG_I_XC_DC0_SCIP_0B10 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B18_CKGEN01_V004 (CKGEN01_V004 + 0xB18)
	#define REG_0B18_CKGEN01_V004_REG_CKG_G_XC_DBG2MIU_SCIP_0B18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B18_CKGEN01_V004_REG_CKG_I_XC_DBG2MIU_SCIP_0B18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B18_CKGEN01_V004_REG_CKG_S_XC_DBG2MIU_SCIP_0B18 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0B20_CKGEN01_V004 (CKGEN01_V004 + 0xB20)
	#define REG_0B20_CKGEN01_V004_REG_CKG_G_XC_ED0_SCIP_0B20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B20_CKGEN01_V004_REG_CKG_I_XC_ED0_SCIP_0B20 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B28_CKGEN01_V004 (CKGEN01_V004 + 0xB28)
	#define REG_0B28_CKGEN01_V004_REG_CKG_G_XC_ED1_SCIP_0B28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B28_CKGEN01_V004_REG_CKG_I_XC_ED1_SCIP_0B28 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B30_CKGEN01_V004 (CKGEN01_V004 + 0xB30)
	#define REG_0B30_CKGEN01_V004_REG_CKG_G_XC_FN_SCIP_0B30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B30_CKGEN01_V004_REG_CKG_I_XC_FN_SCIP_0B30 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B38_CKGEN01_V004 (CKGEN01_V004 + 0xB38)
	#define REG_0B38_CKGEN01_V004_REG_CKG_G_XC_ID0_SCIP_0B38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B38_CKGEN01_V004_REG_CKG_I_XC_ID0_SCIP_0B38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B38_CKGEN01_V004_REG_CKG_S_XC_ID0_SCIP_0B38 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B40_CKGEN01_V004 (CKGEN01_V004 + 0xB40)
	#define REG_0B40_CKGEN01_V004_REG_CKG_G_XC_ID1_SCIP_0B40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B40_CKGEN01_V004_REG_CKG_I_XC_ID1_SCIP_0B40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B40_CKGEN01_V004_REG_CKG_S_XC_ID1_SCIP_0B40 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B48_CKGEN01_V004 (CKGEN01_V004 + 0xB48)
	#define REG_0B48_CKGEN01_V004_REG_CKG_G_XTAL_24M_SCIP_0B48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B48_CKGEN01_V004_REG_CKG_I_XTAL_24M_SCIP_0B48 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B50_CKGEN01_V004 (CKGEN01_V004 + 0xB50)
	#define REG_0B50_CKGEN01_V004_REG_CKG_G_XTAL_12M_SCIP_0B50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B50_CKGEN01_V004_REG_CKG_I_XTAL_12M_SCIP_0B50 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B58_CKGEN01_V004 (CKGEN01_V004 + 0xB58)
	#define REG_0B58_CKGEN01_V004_REG_CKG_G_XTAL_IP1_SCIP_0B58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B58_CKGEN01_V004_REG_CKG_I_XTAL_IP1_SCIP_0B58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B58_CKGEN01_V004_REG_CKG_S_XTAL_IP1_SCIP_0B58 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0BA0_CKGEN01_V004 (CKGEN01_V004 + 0xBA0)
	#define REG_0BA0_CKGEN01_V004_REG_CKG_G_XC_FN_SCBE_0BA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_I_XC_FN_SCBE_0BA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_G_XC_OD_SCBE_0BA0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_I_XC_OD_SCBE_0BA0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_G_XC_FS_SCBE_0BA0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_I_XC_FS_SCBE_0BA0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_G_XC_FD_SCBE_0BA0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0BA0_CKGEN01_V004_REG_CKG_I_XC_FD_SCBE_0BA0 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0BA8_CKGEN01_V004 (CKGEN01_V004 + 0xBA8)
	#define REG_0BA8_CKGEN01_V004_REG_CKG_G_XTAL_24M_SCBE_0BA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BA8_CKGEN01_V004_REG_CKG_I_XTAL_24M_SCBE_0BA8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0BC0_CKGEN01_V004 (CKGEN01_V004 + 0xBC0)
	#define REG_0BC0_CKGEN01_V004_REG_CKG_G_XTAL_12M_SCBE_0BC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BC0_CKGEN01_V004_REG_CKG_I_XTAL_12M_SCBE_0BC0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0BE8_CKGEN01_V004 (CKGEN01_V004 + 0xBE8)
	#define REG_0BE8_CKGEN01_V004_REG_CKG_G_XC_SRS_SCBE_0BE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BE8_CKGEN01_V004_REG_CKG_I_XC_SRS_SCBE_0BE8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C00_CKGEN01_V004 (CKGEN01_V004 + 0xC00)
	#define REG_0C00_CKGEN01_V004_REG_CKG_G_XC_FD_SCTC_0C00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C00_CKGEN01_V004_REG_CKG_I_XC_FD_SCTC_0C00 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C08_CKGEN01_V004 (CKGEN01_V004 + 0xC08)
	#define REG_0C08_CKGEN01_V004_REG_CKG_G_XC_FN_SCTC_0C08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C08_CKGEN01_V004_REG_CKG_I_XC_FN_SCTC_0C08 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C10_CKGEN01_V004 (CKGEN01_V004 + 0xC10)
	#define REG_0C10_CKGEN01_V004_REG_CKG_G_XC_OD_SCTC_0C10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C10_CKGEN01_V004_REG_CKG_I_XC_OD_SCTC_0C10 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C18_CKGEN01_V004 (CKGEN01_V004 + 0xC18)
	#define REG_0C18_CKGEN01_V004_REG_CKG_G_XTAL_12M_SCTC_0C18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C18_CKGEN01_V004_REG_CKG_I_XTAL_12M_SCTC_0C18 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C20_CKGEN01_V004 (CKGEN01_V004 + 0xC20)
	#define REG_0C20_CKGEN01_V004_REG_CKG_G_XTAL_24M_SCTC_0C20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C20_CKGEN01_V004_REG_CKG_I_XTAL_24M_SCTC_0C20 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C40_CKGEN01_V004 (CKGEN01_V004 + 0xC40)
	#define REG_0C40_CKGEN01_V004_REG_CKG_G_XCPLL_SYN_0C40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C40_CKGEN01_V004_REG_CKG_I_XCPLL_SYN_0C40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C40_CKGEN01_V004_REG_CKG_S_XCPLL_SYN_0C40 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0C48_CKGEN01_V004 (CKGEN01_V004 + 0xC48)
	#define REG_0C48_CKGEN01_V004_REG_CKG_G_DELTA_B2P2_SRAM_0C48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C48_CKGEN01_V004_REG_CKG_I_DELTA_B2P2_SRAM_0C48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C48_CKGEN01_V004_REG_CKG_S_DELTA_B2P2_SRAM_0C48 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C50_CKGEN01_V004 (CKGEN01_V004 + 0xC50)
	#define REG_0C50_CKGEN01_V004_REG_CKG_G_GUCD_18_LUT2_SRAM_0C50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C50_CKGEN01_V004_REG_CKG_I_GUCD_18_LUT2_SRAM_0C50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C50_CKGEN01_V004_REG_CKG_S_GUCD_18_LUT2_SRAM_0C50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C58_CKGEN01_V004 (CKGEN01_V004 + 0xC58)
	#define REG_0C58_CKGEN01_V004_REG_CKG_G_GUCD_256_LUT2_SRAM_0C58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C58_CKGEN01_V004_REG_CKG_I_GUCD_256_LUT2_SRAM_0C58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C58_CKGEN01_V004_REG_CKG_S_GUCD_256_LUT2_SRAM_0C58 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C60_CKGEN01_V004 (CKGEN01_V004 + 0xC60)
	#define REG_0C60_CKGEN01_V004_REG_CKG_G_HSY_8P3_SRAM_0C60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C60_CKGEN01_V004_REG_CKG_I_HSY_8P3_SRAM_0C60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C60_CKGEN01_V004_REG_CKG_S_HSY_8P3_SRAM_0C60 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C68_CKGEN01_V004 (CKGEN01_V004 + 0xC68)
	#define REG_0C68_CKGEN01_V004_REG_CKG_G_HSY_8P_SRAM_0C68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C68_CKGEN01_V004_REG_CKG_I_HSY_8P_SRAM_0C68 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C68_CKGEN01_V004_REG_CKG_S_HSY_8P_SRAM_0C68 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C6C_CKGEN01_V004 (CKGEN01_V004 + 0xC6C)
	#define REG_0C6C_CKGEN01_V004_REG_CKG_G_DIP1_HVSP_SRAM_0C6C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C6C_CKGEN01_V004_REG_CKG_I_DIP1_HVSP_SRAM_0C6C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C6C_CKGEN01_V004_REG_CKG_S_DIP1_HVSP_SRAM_0C6C Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C70_CKGEN01_V004 (CKGEN01_V004 + 0xC70)
	#define REG_0C70_CKGEN01_V004_REG_CKG_G_LCE_ACE_SRAM_0C70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C70_CKGEN01_V004_REG_CKG_I_LCE_ACE_SRAM_0C70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C70_CKGEN01_V004_REG_CKG_S_LCE_ACE_SRAM_0C70 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C74_CKGEN01_V004 (CKGEN01_V004 + 0xC74)
	#define REG_0C74_CKGEN01_V004_REG_CKG_G_DIP1_XVYCC_SRAM_0C74 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C74_CKGEN01_V004_REG_CKG_I_DIP1_XVYCC_SRAM_0C74 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C74_CKGEN01_V004_REG_CKG_S_DIP1_XVYCC_SRAM_0C74 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C80_CKGEN01_V004 (CKGEN01_V004 + 0xC80)
	#define REG_0C80_CKGEN01_V004_REG_CKG_G_RGB_3DLUT_SRAM_0C80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C80_CKGEN01_V004_REG_CKG_I_RGB_3DLUT_SRAM_0C80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C80_CKGEN01_V004_REG_CKG_S_RGB_3DLUT_SRAM_0C80 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C88_CKGEN01_V004 (CKGEN01_V004 + 0xC88)
	#define REG_0C88_CKGEN01_V004_REG_CKG_G_VIP_ACE_SRAM_0C88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C88_CKGEN01_V004_REG_CKG_I_VIP_ACE_SRAM_0C88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C88_CKGEN01_V004_REG_CKG_S_VIP_ACE_SRAM_0C88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C90_CKGEN01_V004 (CKGEN01_V004 + 0xC90)
	#define REG_0C90_CKGEN01_V004_REG_CKG_G_XVYCC_SRAM_0C90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C90_CKGEN01_V004_REG_CKG_I_XVYCC_SRAM_0C90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C90_CKGEN01_V004_REG_CKG_S_XVYCC_SRAM_0C90 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C98_CKGEN01_V004 (CKGEN01_V004 + 0xC98)
	#define REG_0C98_CKGEN01_V004_REG_CKG_G_DV_HW5_C2_SRAM_0C98 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0C98_CKGEN01_V004_REG_CKG_I_DV_HW5_C2_SRAM_0C98 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0C98_CKGEN01_V004_REG_CKG_S_DV_HW5_C2_SRAM_0C98 Fld(1,6,AC_MSKB0)//[6:6]
#define REG_0CA0_CKGEN01_V004 (CKGEN01_V004 + 0xCA0)
	#define REG_0CA0_CKGEN01_V004_REG_CKG_G_DC0_SRAM_0CA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CA0_CKGEN01_V004_REG_CKG_I_DC0_SRAM_0CA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CA0_CKGEN01_V004_REG_CKG_S_DC0_SRAM_TMP_0CA0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CA8_CKGEN01_V004 (CKGEN01_V004 + 0xCA8)
	#define REG_0CA8_CKGEN01_V004_REG_CKG_G_UCD_ST_SRAM_0CA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CA8_CKGEN01_V004_REG_CKG_I_UCD_ST_SRAM_0CA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CA8_CKGEN01_V004_REG_CKG_S_UCD_ST_SRAM_TMP_0CA8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CB0_CKGEN01_V004 (CKGEN01_V004 + 0xCB0)
	#define REG_0CB0_CKGEN01_V004_REG_CKG_G_XC_ADC_SCIP_0CB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CB0_CKGEN01_V004_REG_CKG_I_XC_ADC_SCIP_0CB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CB0_CKGEN01_V004_REG_CKG_S_XC_ADC_SCIP_0CB0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CB8_CKGEN01_V004 (CKGEN01_V004 + 0xCB8)
	#define REG_0CB8_CKGEN01_V004_REG_CKG_G_XC_SUB_DC0_SCIP_0CB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CB8_CKGEN01_V004_REG_CKG_I_XC_SUB_DC0_SCIP_0CB8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0CBC_CKGEN01_V004 (CKGEN01_V004 + 0xCBC)
	#define REG_0CBC_CKGEN01_V004_REG_CKG_G_XC_SUB1_DC0_SCIP_0CBC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CBC_CKGEN01_V004_REG_CKG_I_XC_SUB1_DC0_SCIP_0CBC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0CC0_CKGEN01_V004 (CKGEN01_V004 + 0xCC0)
	#define REG_0CC0_CKGEN01_V004_REG_CKG_G_XC_DISP_MFDEC_SCIP_0CC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CC0_CKGEN01_V004_REG_CKG_I_XC_DISP_MFDEC_SCIP_0CC0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0CC8_CKGEN01_V004 (CKGEN01_V004 + 0xCC8)
	#define REG_0CC8_CKGEN01_V004_REG_CKG_G_XC_HD2MIU_M_SCIP_0CC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CC8_CKGEN01_V004_REG_CKG_I_XC_HD2MIU_M_SCIP_0CC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CC8_CKGEN01_V004_REG_CKG_S_XC_HD2MIU_M_SCIP_0CC8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CD0_CKGEN01_V004 (CKGEN01_V004 + 0xCD0)
	#define REG_0CD0_CKGEN01_V004_REG_CKG_G_XC_HD2MIU_S_SCIP_0CD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CD0_CKGEN01_V004_REG_CKG_I_XC_HD2MIU_S_SCIP_0CD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CD0_CKGEN01_V004_REG_CKG_S_XC_HD2MIU_S_SCIP_0CD0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CD8_CKGEN01_V004 (CKGEN01_V004 + 0xCD8)
	#define REG_0CD8_CKGEN01_V004_REG_CKG_G_XC_HDMI0_SCIP_0CD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CD8_CKGEN01_V004_REG_CKG_I_XC_HDMI0_SCIP_0CD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CD8_CKGEN01_V004_REG_CKG_S_XC_HDMI0_SCIP_0CD8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CE0_CKGEN01_V004 (CKGEN01_V004 + 0xCE0)
	#define REG_0CE0_CKGEN01_V004_REG_CKG_G_XC_HDMI1_SCIP_0CE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CE0_CKGEN01_V004_REG_CKG_I_XC_HDMI1_SCIP_0CE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CE0_CKGEN01_V004_REG_CKG_S_XC_HDMI1_SCIP_0CE0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CE8_CKGEN01_V004 (CKGEN01_V004 + 0xCE8)
	#define REG_0CE8_CKGEN01_V004_REG_CKG_G_XC_HDMI2_SCIP_0CE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CE8_CKGEN01_V004_REG_CKG_I_XC_HDMI2_SCIP_0CE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CE8_CKGEN01_V004_REG_CKG_S_XC_HDMI2_SCIP_0CE8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CF0_CKGEN01_V004 (CKGEN01_V004 + 0xCF0)
	#define REG_0CF0_CKGEN01_V004_REG_CKG_G_XC_HDMI3_SCIP_0CF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CF0_CKGEN01_V004_REG_CKG_I_XC_HDMI3_SCIP_0CF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CF0_CKGEN01_V004_REG_CKG_S_XC_HDMI3_SCIP_0CF0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CF8_CKGEN01_V004 (CKGEN01_V004 + 0xCF8)
	#define REG_0CF8_CKGEN01_V004_REG_CKG_G_XC_IP2_SRC_SCIP_0CF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CF8_CKGEN01_V004_REG_CKG_I_XC_IP2_SRC_SCIP_0CF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CF8_CKGEN01_V004_REG_CKG_S_XC_IP2_SRC_SCIP_0CF8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D00_CKGEN01_V004 (CKGEN01_V004 + 0xD00)
	#define REG_0D00_CKGEN01_V004_REG_CKG_G_XC_SLOW_SCIP_0D00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D00_CKGEN01_V004_REG_CKG_I_XC_SLOW_SCIP_0D00 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0D08_CKGEN01_V004 (CKGEN01_V004 + 0xD08)
	#define REG_0D08_CKGEN01_V004_REG_CKG_G_XC_TGEN_WIN_SCIP_0D08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D08_CKGEN01_V004_REG_CKG_I_XC_TGEN_WIN_SCIP_0D08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D08_CKGEN01_V004_REG_CKG_S_XC_TGEN_WIN_SCIP_0D08 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0D10_CKGEN01_V004 (CKGEN01_V004 + 0xD10)
	#define REG_0D10_CKGEN01_V004_REG_CKG_G_XC_UCD_STAT_SCIP_0D10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D10_CKGEN01_V004_REG_CKG_I_XC_UCD_STAT_SCIP_0D10 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0D18_CKGEN01_V004 (CKGEN01_V004 + 0xD18)
	#define REG_0D18_CKGEN01_V004_REG_CKG_G_XC_VD_SCIP_0D18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D18_CKGEN01_V004_REG_CKG_I_XC_VD_SCIP_0D18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D18_CKGEN01_V004_REG_CKG_G_DV_HW5_C1_0D18 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0D18_CKGEN01_V004_REG_CKG_I_DV_HW5_C1_0D18 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0D18_CKGEN01_V004_REG_CKG_S_DV_HW5_C1_0D18 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_0D20_CKGEN01_V004 (CKGEN01_V004 + 0xD20)
	#define REG_0D20_CKGEN01_V004_REG_CKG_G_XC_VE_SCIP_0D20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D20_CKGEN01_V004_REG_CKG_I_XC_VE_SCIP_0D20 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D20_CKGEN01_V004_REG_CKG_S_XC_VE_SCIP_0D20 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D28_CKGEN01_V004 (CKGEN01_V004 + 0xD28)
	#define REG_0D28_CKGEN01_V004_REG_CKG_G_XC_VEDAC_0D28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D28_CKGEN01_V004_REG_CKG_I_XC_VEDAC_0D28 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0D30_CKGEN01_V004 (CKGEN01_V004 + 0xD30)
	#define REG_0D30_CKGEN01_V004_REG_CKG_G_DBK_HW_SRAM_0D30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D30_CKGEN01_V004_REG_CKG_I_DBK_HW_SRAM_0D30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D30_CKGEN01_V004_REG_CKG_S_DBK_HW_SRAM_0D30 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D38_CKGEN01_V004 (CKGEN01_V004 + 0xD38)
	#define REG_0D38_CKGEN01_V004_REG_CKG_G_HDR_SRAM_0D38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D38_CKGEN01_V004_REG_CKG_I_HDR_SRAM_0D38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D38_CKGEN01_V004_REG_CKG_S_HDR_SRAM_0D38 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0D38_CKGEN01_V004_REG_CKG_G_HDR_3D_SRAM_0D38 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0D38_CKGEN01_V004_REG_CKG_I_HDR_3D_SRAM_0D38 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0D38_CKGEN01_V004_REG_CKG_S_HDR_3D_SRAM_0D38 Fld(1,6,AC_MSKB0)//[6:6]
#define REG_0D40_CKGEN01_V004 (CKGEN01_V004 + 0xD40)
	#define REG_0D40_CKGEN01_V004_REG_CKG_G_SPF_HDBK_SRAM_0D40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D40_CKGEN01_V004_REG_CKG_I_SPF_HDBK_SRAM_0D40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D40_CKGEN01_V004_REG_CKG_S_SPF_HDBK_SRAM_0D40 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D48_CKGEN01_V004 (CKGEN01_V004 + 0xD48)
	#define REG_0D48_CKGEN01_V004_REG_CKG_G_VDBK_SRAM_0D48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D48_CKGEN01_V004_REG_CKG_I_VDBK_SRAM_0D48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D48_CKGEN01_V004_REG_CKG_S_VDBK_SRAM_0D48 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D50_CKGEN01_V004 (CKGEN01_V004 + 0xD50)
	#define REG_0D50_CKGEN01_V004_REG_CKG_G_DELTA_B2P_SRAM_0D50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D50_CKGEN01_V004_REG_CKG_I_DELTA_B2P_SRAM_0D50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D50_CKGEN01_V004_REG_CKG_S_DELTA_B2P_SRAM_0D50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D58_CKGEN01_V004 (CKGEN01_V004 + 0xD58)
	#define REG_0D58_CKGEN01_V004_REG_CKG_G_GUCD_18_SRAM_0D58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D58_CKGEN01_V004_REG_CKG_I_GUCD_18_SRAM_0D58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D58_CKGEN01_V004_REG_CKG_S_GUCD_18_SRAM_0D58 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D60_CKGEN01_V004 (CKGEN01_V004 + 0xD60)
	#define REG_0D60_CKGEN01_V004_REG_CKG_G_GUCD_256_SRAM_0D60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D60_CKGEN01_V004_REG_CKG_I_GUCD_256_SRAM_0D60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D60_CKGEN01_V004_REG_CKG_S_GUCD_256_SRAM_0D60 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D68_CKGEN01_V004 (CKGEN01_V004 + 0xD68)
	#define REG_0D68_CKGEN01_V004_REG_CKG_G_HSY_SP3_SRAM_0D68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D68_CKGEN01_V004_REG_CKG_I_HSY_SP3_SRAM_0D68 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D68_CKGEN01_V004_REG_CKG_S_HSY_SP3_SRAM_0D68 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D70_CKGEN01_V004 (CKGEN01_V004 + 0xD70)
	#define REG_0D70_CKGEN01_V004_REG_CKG_G_HSY_SP_SRAM_0D70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D70_CKGEN01_V004_REG_CKG_I_HSY_SP_SRAM_0D70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D70_CKGEN01_V004_REG_CKG_S_HSY_SP_SRAM_0D70 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D78_CKGEN01_V004 (CKGEN01_V004 + 0xD78)
	#define REG_0D78_CKGEN01_V004_REG_CKG_G_HVSP_STP1_SRAM_0D78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D78_CKGEN01_V004_REG_CKG_I_HVSP_STP1_SRAM_0D78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D78_CKGEN01_V004_REG_CKG_S_HVSP_STP1_SRAM_0D78 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D80_CKGEN01_V004 (CKGEN01_V004 + 0xD80)
	#define REG_0D80_CKGEN01_V004_REG_CKG_G_HVSP_STP2_SRAM_0D80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D80_CKGEN01_V004_REG_CKG_I_HVSP_STP2_SRAM_0D80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D80_CKGEN01_V004_REG_CKG_S_HVSP_STP2_SRAM_0D80 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D88_CKGEN01_V004 (CKGEN01_V004 + 0xD88)
	#define REG_0D88_CKGEN01_V004_REG_CKG_G_LCE_SCL_SRAM_0D88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D88_CKGEN01_V004_REG_CKG_I_LCE_SCL_SRAM_0D88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D88_CKGEN01_V004_REG_CKG_S_LCE_SCL_SRAM_0D88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D90_CKGEN01_V004 (CKGEN01_V004 + 0xD90)
	#define REG_0D90_CKGEN01_V004_REG_CKG_G_VIP_PQ_SRAM_0D90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D90_CKGEN01_V004_REG_CKG_I_VIP_PQ_SRAM_0D90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D90_CKGEN01_V004_REG_CKG_S_VIP_PQ_SRAM_0D90 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D98_CKGEN01_V004 (CKGEN01_V004 + 0xD98)
	#define REG_0D98_CKGEN01_V004_REG_CKG_G_AISR_SRAM_0D98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D98_CKGEN01_V004_REG_CKG_I_AISR_SRAM_0D98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D98_CKGEN01_V004_REG_CKG_S_AISR_SRAM_0D98 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D9C_CKGEN01_V004 (CKGEN01_V004 + 0xD9C)
	#define REG_0D9C_CKGEN01_V004_REG_CKG_G_AISR_HVSP_SRAM_0D9C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D9C_CKGEN01_V004_REG_CKG_I_AISR_HVSP_SRAM_0D9C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D9C_CKGEN01_V004_REG_CKG_S_AISR_HVSP_SRAM_0D9C Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0DB0_CKGEN01_V004 (CKGEN01_V004 + 0xDB0)
	#define REG_0DB0_CKGEN01_V004_REG_CKG_DEMURA_SRAM_0DB0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DB8_CKGEN01_V004 (CKGEN01_V004 + 0xDB8)
	#define REG_0DB8_CKGEN01_V004_REG_CKG_G_GOP0_SRAM_0DB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DB8_CKGEN01_V004_REG_CKG_I_GOP0_SRAM_0DB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DB8_CKGEN01_V004_REG_CKG_S_GOP0_SRAM_TMP_0DB8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DC0_CKGEN01_V004 (CKGEN01_V004 + 0xDC0)
	#define REG_0DC0_CKGEN01_V004_REG_CKG_G_GOP1_SRAM_0DC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DC0_CKGEN01_V004_REG_CKG_I_GOP1_SRAM_0DC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DC0_CKGEN01_V004_REG_CKG_S_GOP1_SRAM_TMP_0DC0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DC8_CKGEN01_V004 (CKGEN01_V004 + 0xDC8)
	#define REG_0DC8_CKGEN01_V004_REG_CKG_G_GOP2_SRAM_0DC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DC8_CKGEN01_V004_REG_CKG_I_GOP2_SRAM_0DC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DC8_CKGEN01_V004_REG_CKG_S_GOP2_SRAM_TMP_0DC8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DD0_CKGEN01_V004 (CKGEN01_V004 + 0xDD0)
	#define REG_0DD0_CKGEN01_V004_REG_CKG_G_GOP3_SRAM_0DD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DD0_CKGEN01_V004_REG_CKG_I_GOP3_SRAM_0DD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DD0_CKGEN01_V004_REG_CKG_S_GOP3_SRAM_TMP_0DD0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DD4_CKGEN01_V004 (CKGEN01_V004 + 0xDD4)
	#define REG_0DD4_CKGEN01_V004_REG_CKG_G_OD_SRAM_0DD4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_I_OD_SRAM_0DD4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_S_OD_SRAM_TMP_0DD4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_G_PCID_SRAM_0DD4 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_I_PCID_SRAM_0DD4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_S_PCID_SRAM_TMP_0DD4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_G_VAC_SRAM_0DD4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_I_VAC_SRAM_0DD4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_0DD4_CKGEN01_V004_REG_CKG_S_VAC_SRAM_TMP_0DD4 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_0DD8_CKGEN01_V004 (CKGEN01_V004 + 0xDD8)
	#define REG_0DD8_CKGEN01_V004_REG_CKG_G_LD_EDGE2D_SRAM_0DD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DD8_CKGEN01_V004_REG_CKG_I_LD_EDGE2D_SRAM_0DD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DD8_CKGEN01_V004_REG_CKG_S_LD_EDGE2D_SRAM_TMP_0DD8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DE0_CKGEN01_V004 (CKGEN01_V004 + 0xDE0)
	#define REG_0DE0_CKGEN01_V004_REG_CKG_G_LDCOMP_SRAM_0DE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DE0_CKGEN01_V004_REG_CKG_I_LDCOMP_SRAM_0DE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DE0_CKGEN01_V004_REG_CKG_S_LDCOMP_SRAM_TMP_0DE0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DEC_CKGEN01_V004 (CKGEN01_V004 + 0xDEC)
	#define REG_0DEC_CKGEN01_V004_REG_CKG_G_PQ_GA_SRAM_0DEC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DEC_CKGEN01_V004_REG_CKG_I_PQ_GA_SRAM_0DEC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DEC_CKGEN01_V004_REG_CKG_S_PQ_GA_SRAM_TMP_0DEC Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DF0_CKGEN01_V004 (CKGEN01_V004 + 0xDF0)
	#define REG_0DF0_CKGEN01_V004_REG_CKG_G_LDMCG_SRAM_0DF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DF0_CKGEN01_V004_REG_CKG_I_LDMCG_SRAM_0DF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DF0_CKGEN01_V004_REG_CKG_S_LDMCG_SRAM_TMP_0DF0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DF8_CKGEN01_V004 (CKGEN01_V004 + 0xDF8)
	#define REG_0DF8_CKGEN01_V004_REG_CKG_LPQ_PA_SRAM_0DF8 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E00_CKGEN01_V004 (CKGEN01_V004 + 0xE00)
	#define REG_0E00_CKGEN01_V004_REG_CKG_OSD_DV_HW5_SRAM_0E00 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E08_CKGEN01_V004 (CKGEN01_V004 + 0xE08)
	#define REG_0E08_CKGEN01_V004_REG_CKG_G_PADJ_SRAM_0E08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E08_CKGEN01_V004_REG_CKG_I_PADJ_SRAM_0E08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E08_CKGEN01_V004_REG_CKG_S_PADJ_SRAM_TMP_0E08 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E10_CKGEN01_V004 (CKGEN01_V004 + 0xE10)
	#define REG_0E10_CKGEN01_V004_REG_CKG_G_PANEL_GA_SRAM_0E10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E10_CKGEN01_V004_REG_CKG_I_PANEL_GA_SRAM_0E10 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E10_CKGEN01_V004_REG_CKG_S_PANEL_GA_SRAM_TMP_0E10 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E14_CKGEN01_V004 (CKGEN01_V004 + 0xE14)
	#define REG_0E14_CKGEN01_V004_REG_CKG_G_SIDCLK_HD0_SCIP_0E14 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E14_CKGEN01_V004_REG_CKG_I_SIDCLK_HD0_SCIP_0E14 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E14_CKGEN01_V004_REG_CKG_S_SIDCLK_HD0_SCIP_0E14 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E18_CKGEN01_V004 (CKGEN01_V004 + 0xE18)
	#define REG_0E18_CKGEN01_V004_REG_CKG_G_SIDCLK_HD1_SCIP_0E18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E18_CKGEN01_V004_REG_CKG_I_SIDCLK_HD1_SCIP_0E18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E18_CKGEN01_V004_REG_CKG_S_SIDCLK_HD1_SCIP_0E18 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E1C_CKGEN01_V004 (CKGEN01_V004 + 0xE1C)
	#define REG_0E1C_CKGEN01_V004_REG_CKG_G_SIDCLK_HD2_SCIP_0E1C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E1C_CKGEN01_V004_REG_CKG_I_SIDCLK_HD2_SCIP_0E1C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E1C_CKGEN01_V004_REG_CKG_S_SIDCLK_HD2_SCIP_0E1C Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E20_CKGEN01_V004 (CKGEN01_V004 + 0xE20)
	#define REG_0E20_CKGEN01_V004_REG_CKG_G_SIDCLK_HD3_SCIP_0E20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E20_CKGEN01_V004_REG_CKG_I_SIDCLK_HD3_SCIP_0E20 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E20_CKGEN01_V004_REG_CKG_S_SIDCLK_HD3_SCIP_0E20 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E24_CKGEN01_V004 (CKGEN01_V004 + 0xE24)
	#define REG_0E24_CKGEN01_V004_REG_CKG_G_XC_DIP0_SCIP_0E24 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E24_CKGEN01_V004_REG_CKG_I_XC_DIP0_SCIP_0E24 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E24_CKGEN01_V004_REG_CKG_S_XC_DIP0_SCIP_0E24 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E28_CKGEN01_V004 (CKGEN01_V004 + 0xE28)
	#define REG_0E28_CKGEN01_V004_REG_CKG_G_XC_DIP1_SCIP_0E28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E28_CKGEN01_V004_REG_CKG_I_XC_DIP1_SCIP_0E28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E28_CKGEN01_V004_REG_CKG_S_XC_DIP1_SCIP_0E28 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E2C_CKGEN01_V004 (CKGEN01_V004 + 0xE2C)
	#define REG_0E2C_CKGEN01_V004_REG_CKG_G_XC_DIP2_SCIP_0E2C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E2C_CKGEN01_V004_REG_CKG_I_XC_DIP2_SCIP_0E2C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E2C_CKGEN01_V004_REG_CKG_S_XC_DIP2_SCIP_0E2C Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E38_CKGEN01_V004 (CKGEN01_V004 + 0xE38)
	#define REG_0E38_CKGEN01_V004_REG_CKG_G_XC_GOP_SCL_SCTC_0E38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E38_CKGEN01_V004_REG_CKG_I_XC_GOP_SCL_SCTC_0E38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E38_CKGEN01_V004_REG_CKG_S_XC_GOP_SCL_SCTC_0E38 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E3C_CKGEN01_V004 (CKGEN01_V004 + 0xE3C)
	#define REG_0E3C_CKGEN01_V004_REG_CKG_G_XC_GOP_SCTC_0E3C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E3C_CKGEN01_V004_REG_CKG_I_XC_GOP_SCTC_0E3C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0E48_CKGEN01_V004 (CKGEN01_V004 + 0xE48)
	#define REG_0E48_CKGEN01_V004_REG_CKG_G_XC_OD_DELTA_SCTC_0E48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E48_CKGEN01_V004_REG_CKG_I_XC_OD_DELTA_SCTC_0E48 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0E4C_CKGEN01_V004 (CKGEN01_V004 + 0xE4C)
	#define REG_0E4C_CKGEN01_V004_REG_CKG_G_XC_OD_DIV2_SCTC_0E4C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E4C_CKGEN01_V004_REG_CKG_I_XC_OD_DIV2_SCTC_0E4C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E4C_CKGEN01_V004_REG_CKG_G_XC_OD_DIV2_SCIP_0E4C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0E4C_CKGEN01_V004_REG_CKG_I_XC_OD_DIV2_SCIP_0E4C Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0E50_CKGEN01_V004 (CKGEN01_V004 + 0xE50)
	#define REG_0E50_CKGEN01_V004_REG_CKG_G_XC_OD_DIV4_SCTC_0E50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E50_CKGEN01_V004_REG_CKG_I_XC_OD_DIV4_SCTC_0E50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E50_CKGEN01_V004_REG_CKG_S_XC_OD_DIV4_SCTC_0E50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E54_CKGEN01_V004 (CKGEN01_V004 + 0xE54)
	#define REG_0E54_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_ED_0E54 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0E54_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_ED_SLD_0E54 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E58_CKGEN01_V004 (CKGEN01_V004 + 0xE58)
	#define REG_0E58_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_FN_0E58 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0E58_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_FN_SLD_0E58 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E5C_CKGEN01_V004 (CKGEN01_V004 + 0xE5C)
	#define REG_0E5C_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_FS_0E5C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0E5C_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_FS_SLD_0E5C Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E60_CKGEN01_V004 (CKGEN01_V004 + 0xE60)
	#define REG_0E60_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_FD_0E60 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0E60_CKGEN01_V004_REG_FLOW_CTRL_RATE_XC_FD_SLD_0E60 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E68_CKGEN01_V004 (CKGEN01_V004 + 0xE68)
	#define REG_0E68_CKGEN01_V004_REG_CKG_G_XC_OD_OSD_SCTC_0E68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E68_CKGEN01_V004_REG_CKG_I_XC_OD_OSD_SCTC_0E68 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0E70_CKGEN01_V004 (CKGEN01_V004 + 0xE70)
	#define REG_0E70_CKGEN01_V004_REG_CKG_G_XC_FS_SCTC_0E70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E70_CKGEN01_V004_REG_CKG_I_XC_FS_SCTC_0E70 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0E78_CKGEN01_V004 (CKGEN01_V004 + 0xE78)
	#define REG_0E78_CKGEN01_V004_REG_CKG_G_XC_SC2FPLL_SCIP_0E78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E78_CKGEN01_V004_REG_CKG_I_XC_SC2FPLL_SCIP_0E78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E78_CKGEN01_V004_REG_CKG_S_XC_SC2FPLL_SCIP_0E78 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0E80_CKGEN01_V004 (CKGEN01_V004 + 0xE80)
	#define REG_0E80_CKGEN01_V004_REG_GATE_XC_ED_0E80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0E84_CKGEN01_V004 (CKGEN01_V004 + 0xE84)
	#define REG_0E84_CKGEN01_V004_REG_GATE_XC_FN_0E84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0E88_CKGEN01_V004 (CKGEN01_V004 + 0xE88)
	#define REG_0E88_CKGEN01_V004_REG_GATE_XC_FS_0E88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0E8C_CKGEN01_V004 (CKGEN01_V004 + 0xE8C)
	#define REG_0E8C_CKGEN01_V004_REG_GATE_XC_FD_0E8C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0ED8_CKGEN01_V004 (CKGEN01_V004 + 0xED8)
	#define REG_0ED8_CKGEN01_V004_REG_CKG_G_IRS_MHEG5_0ED8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0ED8_CKGEN01_V004_REG_CKG_I_IRS_MHEG5_0ED8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0EE0_CKGEN01_V004 (CKGEN01_V004 + 0xEE0)
	#define REG_0EE0_CKGEN01_V004_REG_CKG_G_MCU_MAIL0_0EE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EE0_CKGEN01_V004_REG_CKG_I_MCU_MAIL0_0EE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EE0_CKGEN01_V004_REG_CKG_S_MCU_MAIL0_0EE0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0EE8_CKGEN01_V004 (CKGEN01_V004 + 0xEE8)
	#define REG_0EE8_CKGEN01_V004_REG_CKG_G_MCU_MAIL1_0EE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EE8_CKGEN01_V004_REG_CKG_I_MCU_MAIL1_0EE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EE8_CKGEN01_V004_REG_CKG_S_MCU_MAIL1_0EE8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0EF0_CKGEN01_V004 (CKGEN01_V004 + 0xEF0)
	#define REG_0EF0_CKGEN01_V004_REG_CKG_G_VD2X_0EF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EF0_CKGEN01_V004_REG_CKG_I_VD2X_0EF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EF0_CKGEN01_V004_REG_CKG_S_VD2X_0EF0 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0EF0_CKGEN01_V004_REG_CKG_G_VD2X_MHEG5_0EF0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0EF0_CKGEN01_V004_REG_CKG_I_VD2X_MHEG5_0EF0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0EF8_CKGEN01_V004 (CKGEN01_V004 + 0xEF8)
	#define REG_0EF8_CKGEN01_V004_REG_CKG_G_VD_32FSC_0EF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EF8_CKGEN01_V004_REG_CKG_I_VD_32FSC_0EF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EF8_CKGEN01_V004_REG_CKG_S_VD_32FSC_0EF8 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0EF8_CKGEN01_V004_REG_CKG_G_VD_32FSC_MHEG5_0EF8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0EF8_CKGEN01_V004_REG_CKG_I_VD_32FSC_MHEG5_0EF8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0F00_CKGEN01_V004 (CKGEN01_V004 + 0xF00)
	#define REG_0F00_CKGEN01_V004_REG_CKG_G_VD_0F00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F00_CKGEN01_V004_REG_CKG_I_VD_0F00 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F00_CKGEN01_V004_REG_CKG_S_VD_0F00 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0F00_CKGEN01_V004_REG_CKG_G_VD_MHEG5_0F00 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0F00_CKGEN01_V004_REG_CKG_I_VD_MHEG5_0F00 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0F08_CKGEN01_V004 (CKGEN01_V004 + 0xF08)
	#define REG_0F08_CKGEN01_V004_REG_CKG_G_CMBAI_0F08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F08_CKGEN01_V004_REG_CKG_I_CMBAI_0F08 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F10_CKGEN01_V004 (CKGEN01_V004 + 0xF10)
	#define REG_0F10_CKGEN01_V004_REG_CKG_G_CMBAO_0F10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F10_CKGEN01_V004_REG_CKG_I_CMBAO_0F10 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F18_CKGEN01_V004 (CKGEN01_V004 + 0xF18)
	#define REG_0F18_CKGEN01_V004_REG_CKG_G_CMBBI_0F18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F18_CKGEN01_V004_REG_CKG_I_CMBBI_0F18 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F20_CKGEN01_V004 (CKGEN01_V004 + 0xF20)
	#define REG_0F20_CKGEN01_V004_REG_CKG_G_CMBBO_0F20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F20_CKGEN01_V004_REG_CKG_I_CMBBO_0F20 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F40_CKGEN01_V004 (CKGEN01_V004 + 0xF40)
	#define REG_0F40_CKGEN01_V004_REG_CKG_G_VE_0F40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F40_CKGEN01_V004_REG_CKG_I_VE_0F40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F40_CKGEN01_V004_REG_CKG_S_VE_0F40 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F48_CKGEN01_V004 (CKGEN01_V004 + 0xF48)
	#define REG_0F48_CKGEN01_V004_REG_CKG_G_VEDAC_0F48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F48_CKGEN01_V004_REG_CKG_I_VEDAC_0F48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F48_CKGEN01_V004_REG_CKG_S_VEDAC_0F48 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0F50_CKGEN01_V004 (CKGEN01_V004 + 0xF50)
	#define REG_0F50_CKGEN01_V004_REG_CKG_G_VENC_0F50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F50_CKGEN01_V004_REG_CKG_I_VENC_0F50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F50_CKGEN01_V004_REG_CKG_S_VENC_0F50 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0F50_CKGEN01_V004_REG_CKG_G_VENC_MHEG5_0F50 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0F50_CKGEN01_V004_REG_CKG_I_VENC_MHEG5_0F50 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0F68_CKGEN01_V004 (CKGEN01_V004 + 0xF68)
	#define REG_0F68_CKGEN01_V004_REG_CKG_S_SMI_FCIE_SEL_0F68 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F70_CKGEN01_V004 (CKGEN01_V004 + 0xF70)
	#define REG_0F70_CKGEN01_V004_REG_CKG_G_ECC_0F70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F70_CKGEN01_V004_REG_CKG_I_ECC_0F70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F70_CKGEN01_V004_REG_CKG_S_ECC_0F70 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_0F70_CKGEN01_V004_REG_CKG_G_ECC_TSP_0F70 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0F70_CKGEN01_V004_REG_CKG_I_ECC_TSP_0F70 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0F78_CKGEN01_V004 (CKGEN01_V004 + 0xF78)
	#define REG_0F78_CKGEN01_V004_REG_CKG_G_FCIE_0F78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F78_CKGEN01_V004_REG_CKG_I_FCIE_0F78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F78_CKGEN01_V004_REG_CKG_S_FCIE_0F78 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_0F78_CKGEN01_V004_REG_CKG_G_FCIE_TSP_0F78 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0F78_CKGEN01_V004_REG_CKG_I_FCIE_TSP_0F78 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0F78_CKGEN01_V004_REG_CKG_S_FCIE_TSP_0F78 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0F80_CKGEN01_V004 (CKGEN01_V004 + 0xF80)
	#define REG_0F80_CKGEN01_V004_REG_CKG_S_FCIE_SYN_0F80 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F90_CKGEN01_V004 (CKGEN01_V004 + 0xF90)
	#define REG_0F90_CKGEN01_V004_REG_CKG_G_GMAC_AHB_0F90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F90_CKGEN01_V004_REG_CKG_I_GMAC_AHB_0F90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F90_CKGEN01_V004_REG_CKG_S_GMAC_AHB_0F90 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0F90_CKGEN01_V004_REG_CKG_G_GMAC_AHB_MHEG5_0F90 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0F90_CKGEN01_V004_REG_CKG_I_GMAC_AHB_MHEG5_0F90 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0F98_CKGEN01_V004 (CKGEN01_V004 + 0xF98)
	#define REG_0F98_CKGEN01_V004_REG_CKG_G_GMAC_RX_MHEG5_0F98 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0F98_CKGEN01_V004_REG_CKG_I_GMAC_RX_MHEG5_0F98 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0FA0_CKGEN01_V004 (CKGEN01_V004 + 0xFA0)
	#define REG_0FA0_CKGEN01_V004_REG_CKG_G_GMAC_TX_MHEG5_0FA0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0FA0_CKGEN01_V004_REG_CKG_I_GMAC_TX_MHEG5_0FA0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0FC0_CKGEN01_V004 (CKGEN01_V004 + 0xFC0)
	#define REG_0FC0_CKGEN01_V004_REG_CKG_PEXTP_TL_0FC0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0FC4_CKGEN01_V004 (CKGEN01_V004 + 0xFC4)
	#define REG_0FC4_CKGEN01_V004_REG_CKG_G_SSUSB_USB20_PHY_CLK_TSP_0FC4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FC4_CKGEN01_V004_REG_CKG_I_SSUSB_USB20_PHY_CLK_TSP_0FC4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FC4_CKGEN01_V004_REG_CKG_S_SSUSB_USB20_PHY_CLK_TSP_0FC4 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FC8_CKGEN01_V004 (CKGEN01_V004 + 0xFC8)
	#define REG_0FC8_CKGEN01_V004_REG_CKG_G_SSUSB_USB20_PHY_CLK_1P_TSP_0FC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FC8_CKGEN01_V004_REG_CKG_I_SSUSB_USB20_PHY_CLK_1P_TSP_0FC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FC8_CKGEN01_V004_REG_CKG_S_SSUSB_USB20_PHY_CLK_1P_TSP_0FC8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FCC_CKGEN01_V004 (CKGEN01_V004 + 0xFCC)
	#define REG_0FCC_CKGEN01_V004_REG_CKG_G_SSUSB_USB20_PHY_CLK_2P_TSP_0FCC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FCC_CKGEN01_V004_REG_CKG_I_SSUSB_USB20_PHY_CLK_2P_TSP_0FCC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FCC_CKGEN01_V004_REG_CKG_S_SSUSB_USB20_PHY_CLK_2P_TSP_0FCC Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FD0_CKGEN01_V004 (CKGEN01_V004 + 0xFD0)
	#define REG_0FD0_CKGEN01_V004_REG_CKG_G_SSUSB_FRMCNT_TSP_0FD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FD0_CKGEN01_V004_REG_CKG_I_SSUSB_FRMCNT_TSP_0FD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FD0_CKGEN01_V004_REG_CKG_S_SSUSB_FRMCNT_TSP_0FD0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0FD0_CKGEN01_V004_REG_CKG_G_SSUSB_MISC_48M_TSP_0FD0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0FD0_CKGEN01_V004_REG_CKG_I_SSUSB_MISC_48M_TSP_0FD0 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_0FD4_CKGEN01_V004 (CKGEN01_V004 + 0xFD4)
	#define REG_0FD4_CKGEN01_V004_REG_CKG_G_SSUSB_PCLK_TSP_0FD4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FD4_CKGEN01_V004_REG_CKG_I_SSUSB_PCLK_TSP_0FD4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FD4_CKGEN01_V004_REG_CKG_S_SSUSB_PCLK_TSP_0FD4 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FE8_CKGEN01_V004 (CKGEN01_V004 + 0xFE8)
	#define REG_0FE8_CKGEN01_V004_REG_CKG_G_SSUSB_SYS_TSP_0FE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FE8_CKGEN01_V004_REG_CKG_I_SSUSB_SYS_TSP_0FE8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0FEC_CKGEN01_V004 (CKGEN01_V004 + 0xFEC)
	#define REG_0FEC_CKGEN01_V004_REG_CKG_G_SSUSB_XHCI_TSP_0FEC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FEC_CKGEN01_V004_REG_CKG_I_SSUSB_XHCI_TSP_0FEC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0FF0_CKGEN01_V004 (CKGEN01_V004 + 0xFF0)
	#define REG_0FF0_CKGEN01_V004_REG_CKG_G_USBPHY240_TSP_0FF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FF0_CKGEN01_V004_REG_CKG_I_USBPHY240_TSP_0FF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FF0_CKGEN01_V004_REG_CKG_S_USBPHY240_TSP_0FF0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FF4_CKGEN01_V004 (CKGEN01_V004 + 0xFF4)
	#define REG_0FF4_CKGEN01_V004_REG_CKG_G_USBPHY240_MUX_TSP_0FF4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FF4_CKGEN01_V004_REG_CKG_I_USBPHY240_MUX_TSP_0FF4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FF4_CKGEN01_V004_REG_CKG_S_USBPHY240_MUX_TSP_0FF4 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FF8_CKGEN01_V004 (CKGEN01_V004 + 0xFF8)
	#define REG_0FF8_CKGEN01_V004_REG_CKG_G_USBPHY30_TSP_0FF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FF8_CKGEN01_V004_REG_CKG_I_USBPHY30_TSP_0FF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FF8_CKGEN01_V004_REG_CKG_S_USBPHY30_TSP_0FF8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FFC_CKGEN01_V004 (CKGEN01_V004 + 0xFFC)
	#define REG_0FFC_CKGEN01_V004_REG_CKG_S_SMI_UHC_SEL_0FFC Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1000_CKGEN01_V004 (CKGEN01_V004 + 0x1000)
	#define REG_1000_CKGEN01_V004_REG_CKG_UFS_1000 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1008_CKGEN01_V004 (CKGEN01_V004 + 0x1008)
	#define REG_1008_CKGEN01_V004_REG_CKG_UFS_AES_1008 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1018_CKGEN01_V004 (CKGEN01_V004 + 0x1018)
	#define REG_1018_CKGEN01_V004_REG_CKG_UFS_UNIPRO_CG_SYN_1018 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1020_CKGEN01_V004 (CKGEN01_V004 + 0x1020)
	#define REG_1020_CKGEN01_V004_REG_CKG_S_SMI_AESDMA_SEL_1020 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1028_CKGEN01_V004 (CKGEN01_V004 + 0x1028)
	#define REG_1028_CKGEN01_V004_REG_CKG_S_SMI_TSP_SEL_1028 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1028_CKGEN01_V004_REG_CKG_G_SMI_SSUSB_SEL_1028 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1028_CKGEN01_V004_REG_CKG_I_SMI_SSUSB_SEL_1028 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1038_CKGEN01_V004 (CKGEN01_V004 + 0x1038)
	#define REG_1038_CKGEN01_V004_REG_CKG_G_R2_FRC_FRCMISC_1038 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1038_CKGEN01_V004_REG_CKG_I_R2_FRC_FRCMISC_1038 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1038_CKGEN01_V004_REG_CKG_G_FRC_R2_1038 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1038_CKGEN01_V004_REG_CKG_I_FRC_R2_1038 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1038_CKGEN01_V004_REG_CKG_S_FRC_R2_1038 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_1040_CKGEN01_V004 (CKGEN01_V004 + 0x1040)
	#define REG_1040_CKGEN01_V004_REG_CKG_G_MCU_NONPM_1040 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1040_CKGEN01_V004_REG_CKG_I_MCU_NONPM_1040 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1040_CKGEN01_V004_REG_CKG_S_MCU_NONPM_1040 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1040_CKGEN01_V004_REG_CKG_G_MCU_NONPM_DEMOD0_1040 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1040_CKGEN01_V004_REG_CKG_I_MCU_NONPM_DEMOD0_1040 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1040_CKGEN01_V004_REG_CKG_G_MCU_NONPM_FRCMISC_1040 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1040_CKGEN01_V004_REG_CKG_I_MCU_NONPM_FRCMISC_1040 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_1044_CKGEN01_V004 (CKGEN01_V004 + 0x1044)
	#define REG_1044_CKGEN01_V004_REG_CKG_G_MCU_NONPM_FRCCORE1_1044 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1044_CKGEN01_V004_REG_CKG_I_MCU_NONPM_FRCCORE1_1044 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1044_CKGEN01_V004_REG_CKG_G_MCU_NONPM_FRCCORE2_1044 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1044_CKGEN01_V004_REG_CKG_I_MCU_NONPM_FRCCORE2_1044 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1044_CKGEN01_V004_REG_CKG_G_MCU_NONPM_FRCCORE3_1044 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1044_CKGEN01_V004_REG_CKG_I_MCU_NONPM_FRCCORE3_1044 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_1048_CKGEN01_V004 (CKGEN01_V004 + 0x1048)
	#define REG_1048_CKGEN01_V004_REG_CKG_G_MCU_NONPM_SCIP_1048 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1048_CKGEN01_V004_REG_CKG_I_MCU_NONPM_SCIP_1048 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1048_CKGEN01_V004_REG_CKG_G_MCU_NONPM_SCBE_1048 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1048_CKGEN01_V004_REG_CKG_I_MCU_NONPM_SCBE_1048 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1050_CKGEN01_V004 (CKGEN01_V004 + 0x1050)
	#define REG_1050_CKGEN01_V004_REG_CKG_G_MCU_NONPM_SCTC_1050 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1050_CKGEN01_V004_REG_CKG_I_MCU_NONPM_SCTC_1050 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1050_CKGEN01_V004_REG_CKG_G_MCU_NONPM_MHEG5_1050 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1050_CKGEN01_V004_REG_CKG_I_MCU_NONPM_MHEG5_1050 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1050_CKGEN01_V004_REG_CKG_G_MCU_NONPM_GPU_PAR_GP_1050 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1050_CKGEN01_V004_REG_CKG_I_MCU_NONPM_GPU_PAR_GP_1050 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1058_CKGEN01_V004 (CKGEN01_V004 + 0x1058)
	#define REG_1058_CKGEN01_V004_REG_CKG_G_MCU_NONPM_HDMIRX_1058 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1058_CKGEN01_V004_REG_CKG_I_MCU_NONPM_HDMIRX_1058 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1058_CKGEN01_V004_REG_CKG_G_MCU_NONPM_IP_WRAP_1058 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1058_CKGEN01_V004_REG_CKG_I_MCU_NONPM_IP_WRAP_1058 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1058_CKGEN01_V004_REG_CKG_G_MCU_NONPM_VIVA_1058 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1058_CKGEN01_V004_REG_CKG_I_MCU_NONPM_VIVA_1058 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1058_CKGEN01_V004_REG_CKG_G_MCU_NONPM_TSP_1058 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1058_CKGEN01_V004_REG_CKG_I_MCU_NONPM_TSP_1058 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_1060_CKGEN01_V004 (CKGEN01_V004 + 0x1060)
	#define REG_1060_CKGEN01_V004_REG_CKG_G_SEC_R2_TSP_1060 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1060_CKGEN01_V004_REG_CKG_I_SEC_R2_TSP_1060 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1060_CKGEN01_V004_REG_CKG_S_SEC_R2_TSP_1060 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_10E0_CKGEN01_V004 (CKGEN01_V004 + 0x10E0)
	#define REG_10E0_CKGEN01_V004_REG_CKG_G_MCU_AU_10E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_10E0_CKGEN01_V004_REG_CKG_I_MCU_AU_10E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_10E0_CKGEN01_V004_REG_CKG_S_MCU_AU_10E0 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_10E0_CKGEN01_V004_REG_CKG_G_VIVA_AU_MCU_10E0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_10E0_CKGEN01_V004_REG_CKG_I_VIVA_AU_MCU_10E0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_10E0_CKGEN01_V004_REG_CKG_S_VIVA_AU_MCU_10E0 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_10E8_CKGEN01_V004 (CKGEN01_V004 + 0x10E8)
	#define REG_10E8_CKGEN01_V004_REG_CKG_G_MCU_AU_AURV55_10E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_10E8_CKGEN01_V004_REG_CKG_I_MCU_AU_AURV55_10E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_10F8_CKGEN01_V004 (CKGEN01_V004 + 0x10F8)
	#define REG_10F8_CKGEN01_V004_REG_CKG_G_MCU_CODEC_10F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_10F8_CKGEN01_V004_REG_CKG_I_MCU_CODEC_10F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_10F8_CKGEN01_V004_REG_CKG_S_MCU_CODEC_10F8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1110_CKGEN01_V004 (CKGEN01_V004 + 0x1110)
	#define REG_1110_CKGEN01_V004_REG_CKG_G_MCU_DMD_1110 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1110_CKGEN01_V004_REG_CKG_I_MCU_DMD_1110 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1110_CKGEN01_V004_REG_CKG_S_MCU_DMD_1110 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1110_CKGEN01_V004_REG_CKG_G_MCU_DMD_DEMOD0_1110 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1110_CKGEN01_V004_REG_CKG_I_MCU_DMD_DEMOD0_1110 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1128_CKGEN01_V004 (CKGEN01_V004 + 0x1128)
	#define REG_1128_CKGEN01_V004_REG_CKG_G_MCU_FRC_1128 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1128_CKGEN01_V004_REG_CKG_I_MCU_FRC_1128 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1128_CKGEN01_V004_REG_CKG_S_MCU_FRC_1128 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1130_CKGEN01_V004 (CKGEN01_V004 + 0x1130)
	#define REG_1130_CKGEN01_V004_REG_CKG_G_MCU_FRC_FRCMISC_1130 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1130_CKGEN01_V004_REG_CKG_I_MCU_FRC_FRCMISC_1130 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1140_CKGEN01_V004 (CKGEN01_V004 + 0x1140)
	#define REG_1140_CKGEN01_V004_REG_CKG_G_MCU_HDMI_1140 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1140_CKGEN01_V004_REG_CKG_I_MCU_HDMI_1140 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1140_CKGEN01_V004_REG_CKG_S_MCU_HDMI_1140 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1140_CKGEN01_V004_REG_CKG_G_MCU_HDMI_HDMIRX_1140 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1140_CKGEN01_V004_REG_CKG_I_MCU_HDMI_HDMIRX_1140 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1140_CKGEN01_V004_REG_CKG_S_MCU_HDMI_HDMIRX_1140 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1144_CKGEN01_V004 (CKGEN01_V004 + 0x1144)
	#define REG_1144_CKGEN01_V004_REG_CKG_G_F2P_ODCLK_SCTC_TMP_1144 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1144_CKGEN01_V004_REG_CKG_I_F2P_ODCLK_SCTC_TMP_1144 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1144_CKGEN01_V004_REG_CKG_S_F2P_ODCLK_SCTC_TMP_1144 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_1144_CKGEN01_V004_REG_CKG_G_F2P_ODCLK_1144 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1144_CKGEN01_V004_REG_CKG_I_F2P_ODCLK_1144 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1144_CKGEN01_V004_REG_CKG_S_F2P_ODCLK_1144 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_1148_CKGEN01_V004 (CKGEN01_V004 + 0x1148)
	#define REG_1148_CKGEN01_V004_REG_CKG_G_B2P_ODCLK_SCTC_TMP_1148 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1148_CKGEN01_V004_REG_CKG_I_B2P_ODCLK_SCTC_TMP_1148 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1148_CKGEN01_V004_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_1148_CKGEN01_V004_REG_CKG_G_B2P_ODCLK_1148 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1148_CKGEN01_V004_REG_CKG_I_B2P_ODCLK_1148 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1148_CKGEN01_V004_REG_CKG_S_B2P_ODCLK_1148 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_114C_CKGEN01_V004 (CKGEN01_V004 + 0x114C)
	#define REG_114C_CKGEN01_V004_REG_CKG_G_1P_ODCLK_SCTC_TMP_114C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_114C_CKGEN01_V004_REG_CKG_I_1P_ODCLK_SCTC_TMP_114C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_114C_CKGEN01_V004_REG_CKG_S_1P_ODCLK_SCTC_TMP_114C Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_114C_CKGEN01_V004_REG_CKG_G_1P_ODCLK_114C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_114C_CKGEN01_V004_REG_CKG_I_1P_ODCLK_114C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_114C_CKGEN01_V004_REG_CKG_S_1P_ODCLK_114C Fld(4,10,AC_MSKB1)//[13:10]
#define REG_1150_CKGEN01_V004 (CKGEN01_V004 + 0x1150)
	#define REG_1150_CKGEN01_V004_REG_CKG_G_VAC_ODCLK_SCTC_TMP_1150 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1150_CKGEN01_V004_REG_CKG_I_VAC_ODCLK_SCTC_TMP_1150 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1150_CKGEN01_V004_REG_CKG_S_VAC_ODCLK_SCTC_TMP_1150 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_1150_CKGEN01_V004_REG_CKG_G_VAC_ODCLK_1150 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1150_CKGEN01_V004_REG_CKG_I_VAC_ODCLK_1150 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1150_CKGEN01_V004_REG_CKG_S_VAC_ODCLK_1150 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_1154_CKGEN01_V004 (CKGEN01_V004 + 0x1154)
	#define REG_1154_CKGEN01_V004_REG_CKG_G_PAFRC_ODCLK_SCTC_TMP_1154 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1154_CKGEN01_V004_REG_CKG_I_PAFRC_ODCLK_SCTC_TMP_1154 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1154_CKGEN01_V004_REG_CKG_S_PAFRC_ODCLK_SCTC_TMP_1154 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_1154_CKGEN01_V004_REG_CKG_G_PAFRC_ODCLK_1154 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1154_CKGEN01_V004_REG_CKG_I_PAFRC_ODCLK_1154 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1154_CKGEN01_V004_REG_CKG_S_PAFRC_ODCLK_1154 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_1158_CKGEN01_V004 (CKGEN01_V004 + 0x1158)
	#define REG_1158_CKGEN01_V004_REG_CKG_G_LINEOD_ODCLK_SCTC_TMP_1158 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1158_CKGEN01_V004_REG_CKG_I_LINEOD_ODCLK_SCTC_TMP_1158 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1158_CKGEN01_V004_REG_CKG_S_LINEOD_ODCLK_SCTC_TMP_1158 Fld(4,2,AC_MSKB0)//[5:2]
	#define REG_1158_CKGEN01_V004_REG_CKG_G_LINEOD_ODCLK_1158 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1158_CKGEN01_V004_REG_CKG_I_LINEOD_ODCLK_1158 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1158_CKGEN01_V004_REG_CKG_S_LINEOD_ODCLK_1158 Fld(4,10,AC_MSKB1)//[13:10]
#define REG_1170_CKGEN01_V004 (CKGEN01_V004 + 0x1170)
	#define REG_1170_CKGEN01_V004_REG_CKG_G_MCU_SC_1170 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1170_CKGEN01_V004_REG_CKG_I_MCU_SC_1170 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1170_CKGEN01_V004_REG_CKG_S_MCU_SC_1170 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1170_CKGEN01_V004_REG_CKG_G_MCU_XC_SCIP_1170 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1170_CKGEN01_V004_REG_CKG_I_MCU_XC_SCIP_1170 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1178_CKGEN01_V004 (CKGEN01_V004 + 0x1178)
	#define REG_1178_CKGEN01_V004_REG_CKG_G_MCU_XC_SCBE_1178 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1178_CKGEN01_V004_REG_CKG_I_MCU_XC_SCBE_1178 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1178_CKGEN01_V004_REG_CKG_G_MCU_XC_SCTC_1178 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1178_CKGEN01_V004_REG_CKG_I_MCU_XC_SCTC_1178 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_11A0_CKGEN01_V004 (CKGEN01_V004 + 0x11A0)
	#define REG_11A0_CKGEN01_V004_REG_CKG_G_MCU_VD_11A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11A0_CKGEN01_V004_REG_CKG_I_MCU_VD_11A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_11A0_CKGEN01_V004_REG_CKG_S_MCU_VD_11A0 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_11A0_CKGEN01_V004_REG_CKG_G_MCU_VD_MHEG5_11A0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_11A0_CKGEN01_V004_REG_CKG_I_MCU_VD_MHEG5_11A0 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_11B8_CKGEN01_V004 (CKGEN01_V004 + 0x11B8)
	#define REG_11B8_CKGEN01_V004_REG_CKG_G_MCU_BUS_11B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11B8_CKGEN01_V004_REG_CKG_I_MCU_BUS_11B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_11B8_CKGEN01_V004_REG_CKG_S_MCU_BUS_11B8 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_11B8_CKGEN01_V004_REG_CKG_G_MCU_BUS_SCBE_11B8 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_11B8_CKGEN01_V004_REG_CKG_I_MCU_BUS_SCBE_11B8 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_11B8_CKGEN01_V004_REG_CKG_G_AU_MCU_BUS_11B8 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_11B8_CKGEN01_V004_REG_CKG_I_AU_MCU_BUS_11B8 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_11B8_CKGEN01_V004_REG_CKG_S_AU_MCU_BUS_11B8 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_11C0_CKGEN01_V004 (CKGEN01_V004 + 0x11C0)
	#define REG_11C0_CKGEN01_V004_REG_CKG_G_MCU_BUS_DEMOD0_11C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11C0_CKGEN01_V004_REG_CKG_I_MCU_BUS_DEMOD0_11C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_11C0_CKGEN01_V004_REG_CKG_G_MCU_BUS_HDMIRX_11C0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_11C0_CKGEN01_V004_REG_CKG_I_MCU_BUS_HDMIRX_11C0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_11C0_CKGEN01_V004_REG_CKG_G_MCU_BUS_MHEG5_11C0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_11C0_CKGEN01_V004_REG_CKG_I_MCU_BUS_MHEG5_11C0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_11C0_CKGEN01_V004_REG_CKG_G_MCU_BUS_FRCMISC_11C0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_11C0_CKGEN01_V004_REG_CKG_I_MCU_BUS_FRCMISC_11C0 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_11C4_CKGEN01_V004 (CKGEN01_V004 + 0x11C4)
	#define REG_11C4_CKGEN01_V004_REG_CKG_G_MCU_BUS_TSP_11C4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_11C4_CKGEN01_V004_REG_CKG_I_MCU_BUS_TSP_11C4 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_11F0_CKGEN01_V004 (CKGEN01_V004 + 0x11F0)
	#define REG_11F0_CKGEN01_V004_REG_CKG_G_MIIC0_11F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11F0_CKGEN01_V004_REG_CKG_I_MIIC0_11F0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_11F0_CKGEN01_V004_REG_CKG_S_MIIC0_11F0 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_11F0_CKGEN01_V004_REG_CKG_G_MIIC0_MHEG5_11F0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_11F0_CKGEN01_V004_REG_CKG_I_MIIC0_MHEG5_11F0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_11F8_CKGEN01_V004 (CKGEN01_V004 + 0x11F8)
	#define REG_11F8_CKGEN01_V004_REG_CKG_G_MIIC1_11F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11F8_CKGEN01_V004_REG_CKG_I_MIIC1_11F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_11F8_CKGEN01_V004_REG_CKG_S_MIIC1_11F8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_11F8_CKGEN01_V004_REG_CKG_G_MIIC1_MHEG5_11F8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_11F8_CKGEN01_V004_REG_CKG_I_MIIC1_MHEG5_11F8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1200_CKGEN01_V004 (CKGEN01_V004 + 0x1200)
	#define REG_1200_CKGEN01_V004_REG_CKG_G_MIIC2_1200 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1200_CKGEN01_V004_REG_CKG_I_MIIC2_1200 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1200_CKGEN01_V004_REG_CKG_S_MIIC2_1200 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1200_CKGEN01_V004_REG_CKG_G_MIIC2_MHEG5_1200 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1200_CKGEN01_V004_REG_CKG_I_MIIC2_MHEG5_1200 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1208_CKGEN01_V004 (CKGEN01_V004 + 0x1208)
	#define REG_1208_CKGEN01_V004_REG_CKG_G_MIIC3_1208 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1208_CKGEN01_V004_REG_CKG_I_MIIC3_1208 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1208_CKGEN01_V004_REG_CKG_S_MIIC3_1208 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1208_CKGEN01_V004_REG_CKG_G_MIIC3_MHEG5_1208 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1208_CKGEN01_V004_REG_CKG_I_MIIC3_MHEG5_1208 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1210_CKGEN01_V004 (CKGEN01_V004 + 0x1210)
	#define REG_1210_CKGEN01_V004_REG_CKG_G_MIIC4_1210 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1210_CKGEN01_V004_REG_CKG_I_MIIC4_1210 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1210_CKGEN01_V004_REG_CKG_S_MIIC4_1210 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1210_CKGEN01_V004_REG_CKG_G_MIIC4_MHEG5_1210 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1210_CKGEN01_V004_REG_CKG_I_MIIC4_MHEG5_1210 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1218_CKGEN01_V004 (CKGEN01_V004 + 0x1218)
	#define REG_1218_CKGEN01_V004_REG_CKG_G_PCM_1218 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1218_CKGEN01_V004_REG_CKG_I_PCM_1218 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1218_CKGEN01_V004_REG_CKG_S_PCM_1218 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1218_CKGEN01_V004_REG_CKG_G_PCM_MHEG5_1218 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1218_CKGEN01_V004_REG_CKG_I_PCM_MHEG5_1218 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1220_CKGEN01_V004 (CKGEN01_V004 + 0x1220)
	#define REG_1220_CKGEN01_V004_REG_CKG_S_KG1_1220 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1230_CKGEN01_V004 (CKGEN01_V004 + 0x1230)
	#define REG_1230_CKGEN01_V004_REG_CKG_G_MSPI_CILINK_1230 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1230_CKGEN01_V004_REG_CKG_I_MSPI_CILINK_1230 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1230_CKGEN01_V004_REG_CKG_S_MSPI_CILINK_1230 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1230_CKGEN01_V004_REG_CKG_G_MSPI_CILINK_MHEG5_1230 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1230_CKGEN01_V004_REG_CKG_I_MSPI_CILINK_MHEG5_1230 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1238_CKGEN01_V004 (CKGEN01_V004 + 0x1238)
	#define REG_1238_CKGEN01_V004_REG_CKG_G_MSPI_CILINK_DIV_1238 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1238_CKGEN01_V004_REG_CKG_I_MSPI_CILINK_DIV_1238 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1238_CKGEN01_V004_REG_CKG_S_MSPI_CILINK_DIV_1238 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1240_CKGEN01_V004 (CKGEN01_V004 + 0x1240)
	#define REG_1240_CKGEN01_V004_REG_CKG_G_MSPI0_1240 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1240_CKGEN01_V004_REG_CKG_I_MSPI0_1240 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1240_CKGEN01_V004_REG_CKG_S_MSPI0_1240 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1240_CKGEN01_V004_REG_CKG_G_MSPI0_MHEG5_1240 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1240_CKGEN01_V004_REG_CKG_I_MSPI0_MHEG5_1240 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1248_CKGEN01_V004 (CKGEN01_V004 + 0x1248)
	#define REG_1248_CKGEN01_V004_REG_CKG_G_MSPI0_DIV_1248 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1248_CKGEN01_V004_REG_CKG_I_MSPI0_DIV_1248 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1248_CKGEN01_V004_REG_CKG_S_MSPI0_DIV_1248 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1250_CKGEN01_V004 (CKGEN01_V004 + 0x1250)
	#define REG_1250_CKGEN01_V004_REG_CKG_G_MSPI1_1250 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1250_CKGEN01_V004_REG_CKG_I_MSPI1_1250 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1250_CKGEN01_V004_REG_CKG_S_MSPI1_1250 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1250_CKGEN01_V004_REG_CKG_G_MSPI1_MHEG5_1250 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1250_CKGEN01_V004_REG_CKG_I_MSPI1_MHEG5_1250 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1258_CKGEN01_V004 (CKGEN01_V004 + 0x1258)
	#define REG_1258_CKGEN01_V004_REG_CKG_G_MSPI1_DIV_1258 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1258_CKGEN01_V004_REG_CKG_I_MSPI1_DIV_1258 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1258_CKGEN01_V004_REG_CKG_S_MSPI1_DIV_1258 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1260_CKGEN01_V004 (CKGEN01_V004 + 0x1260)
	#define REG_1260_CKGEN01_V004_REG_CKG_G_MSPI2_1260 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1260_CKGEN01_V004_REG_CKG_I_MSPI2_1260 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1260_CKGEN01_V004_REG_CKG_S_MSPI2_1260 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1260_CKGEN01_V004_REG_CKG_G_MSPI2_MHEG5_1260 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1260_CKGEN01_V004_REG_CKG_I_MSPI2_MHEG5_1260 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1268_CKGEN01_V004 (CKGEN01_V004 + 0x1268)
	#define REG_1268_CKGEN01_V004_REG_CKG_G_MSPI2_DIV_1268 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1268_CKGEN01_V004_REG_CKG_I_MSPI2_DIV_1268 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1268_CKGEN01_V004_REG_CKG_S_MSPI2_DIV_1268 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1270_CKGEN01_V004 (CKGEN01_V004 + 0x1270)
	#define REG_1270_CKGEN01_V004_REG_CKG_G_MSPI3_1270 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1270_CKGEN01_V004_REG_CKG_I_MSPI3_1270 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1270_CKGEN01_V004_REG_CKG_S_MSPI3_1270 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1270_CKGEN01_V004_REG_CKG_G_MSPI3_MHEG5_1270 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1270_CKGEN01_V004_REG_CKG_I_MSPI3_MHEG5_1270 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1278_CKGEN01_V004 (CKGEN01_V004 + 0x1278)
	#define REG_1278_CKGEN01_V004_REG_CKG_G_MSPI3_DIV_1278 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1278_CKGEN01_V004_REG_CKG_I_MSPI3_DIV_1278 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1278_CKGEN01_V004_REG_CKG_S_MSPI3_DIV_1278 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1280_CKGEN01_V004 (CKGEN01_V004 + 0x1280)
	#define REG_1280_CKGEN01_V004_REG_CKG_G_MSPI4_1280 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1280_CKGEN01_V004_REG_CKG_I_MSPI4_1280 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1280_CKGEN01_V004_REG_CKG_S_MSPI4_1280 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1280_CKGEN01_V004_REG_CKG_G_MSPI4_MHEG5_1280 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1280_CKGEN01_V004_REG_CKG_I_MSPI4_MHEG5_1280 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1288_CKGEN01_V004 (CKGEN01_V004 + 0x1288)
	#define REG_1288_CKGEN01_V004_REG_CKG_G_MSPI4_DIV_1288 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1288_CKGEN01_V004_REG_CKG_I_MSPI4_DIV_1288 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1288_CKGEN01_V004_REG_CKG_S_MSPI4_DIV_1288 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1290_CKGEN01_V004 (CKGEN01_V004 + 0x1290)
	#define REG_1290_CKGEN01_V004_REG_CKG_G_MSPI5_1290 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1290_CKGEN01_V004_REG_CKG_I_MSPI5_1290 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1290_CKGEN01_V004_REG_CKG_S_MSPI5_1290 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1290_CKGEN01_V004_REG_CKG_G_MSPI5_MHEG5_1290 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1290_CKGEN01_V004_REG_CKG_I_MSPI5_MHEG5_1290 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1298_CKGEN01_V004 (CKGEN01_V004 + 0x1298)
	#define REG_1298_CKGEN01_V004_REG_CKG_G_MSPI5_DIV_1298 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1298_CKGEN01_V004_REG_CKG_I_MSPI5_DIV_1298 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1298_CKGEN01_V004_REG_CKG_S_MSPI5_DIV_1298 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_12A0_CKGEN01_V004 (CKGEN01_V004 + 0x12A0)
	#define REG_12A0_CKGEN01_V004_REG_CKG_G_MSPI6_12A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12A0_CKGEN01_V004_REG_CKG_I_MSPI6_12A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12A0_CKGEN01_V004_REG_CKG_S_MSPI6_12A0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_12A0_CKGEN01_V004_REG_CKG_G_MSPI6_MHEG5_12A0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_12A0_CKGEN01_V004_REG_CKG_I_MSPI6_MHEG5_12A0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_12A8_CKGEN01_V004 (CKGEN01_V004 + 0x12A8)
	#define REG_12A8_CKGEN01_V004_REG_CKG_G_MSPI6_DIV_12A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12A8_CKGEN01_V004_REG_CKG_I_MSPI6_DIV_12A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12A8_CKGEN01_V004_REG_CKG_S_MSPI6_DIV_12A8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_12B0_CKGEN01_V004 (CKGEN01_V004 + 0x12B0)
	#define REG_12B0_CKGEN01_V004_REG_CKG_G_MSPI7_12B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12B0_CKGEN01_V004_REG_CKG_I_MSPI7_12B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12B0_CKGEN01_V004_REG_CKG_S_MSPI7_12B0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_12B0_CKGEN01_V004_REG_CKG_G_MSPI7_MHEG5_12B0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_12B0_CKGEN01_V004_REG_CKG_I_MSPI7_MHEG5_12B0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_12B8_CKGEN01_V004 (CKGEN01_V004 + 0x12B8)
	#define REG_12B8_CKGEN01_V004_REG_CKG_G_MSPI7_DIV_12B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12B8_CKGEN01_V004_REG_CKG_I_MSPI7_DIV_12B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12B8_CKGEN01_V004_REG_CKG_S_MSPI7_DIV_12B8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_12C0_CKGEN01_V004 (CKGEN01_V004 + 0x12C0)
	#define REG_12C0_CKGEN01_V004_REG_CKG_G_FRC_MSPI0_12C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12C0_CKGEN01_V004_REG_CKG_I_FRC_MSPI0_12C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12C0_CKGEN01_V004_REG_CKG_S_FRC_MSPI0_12C0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_12C8_CKGEN01_V004 (CKGEN01_V004 + 0x12C8)
	#define REG_12C8_CKGEN01_V004_REG_CKG_G_FRC_MSPI0_FRCMISC_12C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12C8_CKGEN01_V004_REG_CKG_I_FRC_MSPI0_FRCMISC_12C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_12D0_CKGEN01_V004 (CKGEN01_V004 + 0x12D0)
	#define REG_12D0_CKGEN01_V004_REG_CKG_G_FRC_MSPI0_DIV_12D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12D0_CKGEN01_V004_REG_CKG_I_FRC_MSPI0_DIV_12D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12D0_CKGEN01_V004_REG_CKG_S_FRC_MSPI0_DIV_12D0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_12E8_CKGEN01_V004 (CKGEN01_V004 + 0x12E8)
	#define REG_12E8_CKGEN01_V004_REG_CKG_G_SPI_12E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12E8_CKGEN01_V004_REG_CKG_I_SPI_12E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_12E8_CKGEN01_V004_REG_CKG_S_SPI_12E8 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_12E8_CKGEN01_V004_REG_CKG_G_SPI_MHEG5_12E8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_12E8_CKGEN01_V004_REG_CKG_I_SPI_MHEG5_12E8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1368_CKGEN01_V004 (CKGEN01_V004 + 0x1368)
	#define REG_1368_CKGEN01_V004_REG_CKG_G_UART0_1368 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1368_CKGEN01_V004_REG_CKG_I_UART0_1368 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1368_CKGEN01_V004_REG_CKG_S_UART0_1368 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1368_CKGEN01_V004_REG_CKG_G_UART0_MHEG5_1368 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1368_CKGEN01_V004_REG_CKG_I_UART0_MHEG5_1368 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1370_CKGEN01_V004 (CKGEN01_V004 + 0x1370)
	#define REG_1370_CKGEN01_V004_REG_CKG_G_UART0_SYNTH_1370 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1370_CKGEN01_V004_REG_CKG_I_UART0_SYNTH_1370 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1370_CKGEN01_V004_REG_CKG_S_UART0_SYNTH_1370 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1378_CKGEN01_V004 (CKGEN01_V004 + 0x1378)
	#define REG_1378_CKGEN01_V004_REG_CKG_G_UART1_1378 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1378_CKGEN01_V004_REG_CKG_I_UART1_1378 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1378_CKGEN01_V004_REG_CKG_S_UART1_1378 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1378_CKGEN01_V004_REG_CKG_G_UART1_MHEG5_1378 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1378_CKGEN01_V004_REG_CKG_I_UART1_MHEG5_1378 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1380_CKGEN01_V004 (CKGEN01_V004 + 0x1380)
	#define REG_1380_CKGEN01_V004_REG_CKG_G_UART1_SYNTH_1380 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1380_CKGEN01_V004_REG_CKG_I_UART1_SYNTH_1380 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1380_CKGEN01_V004_REG_CKG_S_UART1_SYNTH_1380 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1388_CKGEN01_V004 (CKGEN01_V004 + 0x1388)
	#define REG_1388_CKGEN01_V004_REG_CKG_G_UART2_1388 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1388_CKGEN01_V004_REG_CKG_I_UART2_1388 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1388_CKGEN01_V004_REG_CKG_S_UART2_1388 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1388_CKGEN01_V004_REG_CKG_G_UART2_MHEG5_1388 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1388_CKGEN01_V004_REG_CKG_I_UART2_MHEG5_1388 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1390_CKGEN01_V004 (CKGEN01_V004 + 0x1390)
	#define REG_1390_CKGEN01_V004_REG_CKG_G_UART2_SYNTH_1390 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1390_CKGEN01_V004_REG_CKG_I_UART2_SYNTH_1390 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1390_CKGEN01_V004_REG_CKG_S_UART2_SYNTH_1390 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1398_CKGEN01_V004 (CKGEN01_V004 + 0x1398)
	#define REG_1398_CKGEN01_V004_REG_CKG_G_FRC_UART0_1398 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1398_CKGEN01_V004_REG_CKG_I_FRC_UART0_1398 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1398_CKGEN01_V004_REG_CKG_S_FRC_UART0_1398 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1398_CKGEN01_V004_REG_CKG_G_FRC_UART0_FRCMISC_1398 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1398_CKGEN01_V004_REG_CKG_I_FRC_UART0_FRCMISC_1398 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_13A0_CKGEN01_V004 (CKGEN01_V004 + 0x13A0)
	#define REG_13A0_CKGEN01_V004_REG_CKG_G_FRC_UART0_SYNTH_13A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13A0_CKGEN01_V004_REG_CKG_I_FRC_UART0_SYNTH_13A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13A0_CKGEN01_V004_REG_CKG_S_FRC_UART0_SYNTH_13A0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_13A8_CKGEN01_V004 (CKGEN01_V004 + 0x13A8)
	#define REG_13A8_CKGEN01_V004_REG_CKG_G_FRC_UART1_13A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13A8_CKGEN01_V004_REG_CKG_I_FRC_UART1_13A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13A8_CKGEN01_V004_REG_CKG_S_FRC_UART1_13A8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_13A8_CKGEN01_V004_REG_CKG_G_FRC_UART1_FRCMISC_13A8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_13A8_CKGEN01_V004_REG_CKG_I_FRC_UART1_FRCMISC_13A8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_13B0_CKGEN01_V004 (CKGEN01_V004 + 0x13B0)
	#define REG_13B0_CKGEN01_V004_REG_CKG_G_FRC_UART1_SYNTH_13B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13B0_CKGEN01_V004_REG_CKG_I_FRC_UART1_SYNTH_13B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13B0_CKGEN01_V004_REG_CKG_S_FRC_UART1_SYNTH_13B0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_13B8_CKGEN01_V004 (CKGEN01_V004 + 0x13B8)
	#define REG_13B8_CKGEN01_V004_REG_CKG_G_FUART0_13B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13B8_CKGEN01_V004_REG_CKG_I_FUART0_13B8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13B8_CKGEN01_V004_REG_CKG_S_FUART0_13B8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_13B8_CKGEN01_V004_REG_CKG_G_FUART0_MHEG5_13B8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_13B8_CKGEN01_V004_REG_CKG_I_FUART0_MHEG5_13B8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_13C0_CKGEN01_V004 (CKGEN01_V004 + 0x13C0)
	#define REG_13C0_CKGEN01_V004_REG_CKG_G_FUART0_SYNTH_13C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13C0_CKGEN01_V004_REG_CKG_I_FUART0_SYNTH_13C0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13C0_CKGEN01_V004_REG_CKG_S_FUART0_SYNTH_13C0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_13C8_CKGEN01_V004 (CKGEN01_V004 + 0x13C8)
	#define REG_13C8_CKGEN01_V004_REG_CKG_G_AU_UART0_13C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13C8_CKGEN01_V004_REG_CKG_I_AU_UART0_13C8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13C8_CKGEN01_V004_REG_CKG_S_AU_UART0_13C8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_13C8_CKGEN01_V004_REG_CKG_G_AU_UART1_13C8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_13C8_CKGEN01_V004_REG_CKG_I_AU_UART1_13C8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_13C8_CKGEN01_V004_REG_CKG_S_AU_UART1_13C8 Fld(2,6,AC_MSKB0)//[7:6]
	#define REG_13C8_CKGEN01_V004_REG_CKG_G_AU_UART0_VIVA_13C8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_13C8_CKGEN01_V004_REG_CKG_I_AU_UART0_VIVA_13C8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_13D0_CKGEN01_V004 (CKGEN01_V004 + 0x13D0)
	#define REG_13D0_CKGEN01_V004_REG_CKG_G_AU_UART0_SYNTH_13D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13D0_CKGEN01_V004_REG_CKG_I_AU_UART0_SYNTH_13D0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13D0_CKGEN01_V004_REG_CKG_S_AU_UART0_SYNTH_13D0 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_13D0_CKGEN01_V004_REG_CKG_G_AU_UART1_SYNTH_13D0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_13D0_CKGEN01_V004_REG_CKG_I_AU_UART1_SYNTH_13D0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_13D0_CKGEN01_V004_REG_CKG_S_AU_UART1_SYNTH_13D0 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_13D8_CKGEN01_V004 (CKGEN01_V004 + 0x13D8)
	#define REG_13D8_CKGEN01_V004_REG_CKG_G_FRC_FUART0_13D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13D8_CKGEN01_V004_REG_CKG_I_FRC_FUART0_13D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13D8_CKGEN01_V004_REG_CKG_S_FRC_FUART0_13D8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_13D8_CKGEN01_V004_REG_CKG_G_FRC_FUART0_FRCMISC_13D8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_13D8_CKGEN01_V004_REG_CKG_I_FRC_FUART0_FRCMISC_13D8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_13E0_CKGEN01_V004 (CKGEN01_V004 + 0x13E0)
	#define REG_13E0_CKGEN01_V004_REG_CKG_G_FRC_FUART0_SYNTH_13E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13E0_CKGEN01_V004_REG_CKG_I_FRC_FUART0_SYNTH_13E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_13E0_CKGEN01_V004_REG_CKG_S_FRC_FUART0_SYNTH_13E0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_13E8_CKGEN01_V004 (CKGEN01_V004 + 0x13E8)
	#define REG_13E8_CKGEN01_V004_REG_CKG_G_AU_UART1_VIVA_13E8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_13E8_CKGEN01_V004_REG_CKG_I_AU_UART1_VIVA_13E8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_13F0_CKGEN01_V004 (CKGEN01_V004 + 0x13F0)
	#define REG_13F0_CKGEN01_V004_REG_CKG_G_VIVA_TSP_BRIDGE_13F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_13F0_CKGEN01_V004_REG_CKG_I_VIVA_TSP_BRIDGE_13F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1488_CKGEN01_V004 (CKGEN01_V004 + 0x1488)
	#define REG_1488_CKGEN01_V004_REG_SW_EN_CLK_PIX_PKT2MAC_1488 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1490_CKGEN01_V004 (CKGEN01_V004 + 0x1490)
	#define REG_1490_CKGEN01_V004_REG_SW_EN_CLK_TMDS_PKT2MAC_1490 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1498_CKGEN01_V004 (CKGEN01_V004 + 0x1498)
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_002GPO_1498 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_012GPO_1498 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_022GPO_1498 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_032GPO_1498 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_042GPO_1498 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_052GPO_1498 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_062GPO_1498 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_072GPO_1498 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_082GPO_1498 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_092GPO_1498 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_102GPO_1498 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_112GPO_1498 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_122GPO_1498 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_132GPO_1498 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_142GPO_1498 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1498_CKGEN01_V004_REG_SW_EN_GPO_152GPO_1498 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14A0_CKGEN01_V004 (CKGEN01_V004 + 0x14A0)
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_162GPO_14A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_172GPO_14A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_182GPO_14A0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_192GPO_14A0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_202GPO_14A0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_212GPO_14A0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_222GPO_14A0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_232GPO_14A0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_GPO_ZONE2GPO_14A0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_MOD_V1_SR_WCLK2TCON_14A0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_PWM_DAC2PWM_DAC_14A0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG72TCON_14A0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_14A0_CKGEN01_V004_REG_SW_EN_XTAL_12M2TCON_14A0 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_14A4_CKGEN01_V004 (CKGEN01_V004 + 0x14A4)
	#define REG_14A4_CKGEN01_V004_REG_SW_EN_CLKD_ADC2DACA2ADC_TOP_DATA_14A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14A8_CKGEN01_V004 (CKGEN01_V004 + 0x14A8)
	#define REG_14A8_CKGEN01_V004_REG_SW_EN_CLKD_ADC2ADC_TOP_DATA_14A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14AC_CKGEN01_V004 (CKGEN01_V004 + 0x14AC)
	#define REG_14AC_CKGEN01_V004_REG_SW_EN_CLKD_ADC2GEMIU2ADC_TOP_DATA_14AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B0_CKGEN01_V004 (CKGEN01_V004 + 0x14B0)
	#define REG_14B0_CKGEN01_V004_REG_SW_EN_CLKD_ADC2SC2ADC_TOP_DATA_14B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B4_CKGEN01_V004 (CKGEN01_V004 + 0x14B4)
	#define REG_14B4_CKGEN01_V004_REG_SW_EN_CLKD_FBLANK2ADC_TOP_DATA_14B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B8_CKGEN01_V004 (CKGEN01_V004 + 0x14B8)
	#define REG_14B8_CKGEN01_V004_REG_SW_EN_CLKD_VD2ADC_TOP_DATA_14B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14BC_CKGEN01_V004 (CKGEN01_V004 + 0x14BC)
	#define REG_14BC_CKGEN01_V004_REG_SW_EN_CLKFSCX2_VD2ADC_TOP_DATA_14BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C0_CKGEN01_V004 (CKGEN01_V004 + 0x14C0)
	#define REG_14C0_CKGEN01_V004_REG_SW_EN_ADC2ADC_14C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C4_CKGEN01_V004 (CKGEN01_V004 + 0x14C4)
	#define REG_14C4_CKGEN01_V004_REG_SW_EN_ADC2MIU2ADC_14C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C8_CKGEN01_V004 (CKGEN01_V004 + 0x14C8)
	#define REG_14C8_CKGEN01_V004_REG_SW_EN_ADC2MIUSC2ADC_14C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14CC_CKGEN01_V004 (CKGEN01_V004 + 0x14CC)
	#define REG_14CC_CKGEN01_V004_REG_SW_EN_ADC2SC2ADC_14CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D0_CKGEN01_V004 (CKGEN01_V004 + 0x14D0)
	#define REG_14D0_CKGEN01_V004_REG_SW_EN_OCC_SLOW2ADC_14D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D4_CKGEN01_V004 (CKGEN01_V004 + 0x14D4)
	#define REG_14D4_CKGEN01_V004_REG_SW_EN_ADCPLL4002ADC_14D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D8_CKGEN01_V004 (CKGEN01_V004 + 0x14D8)
	#define REG_14D8_CKGEN01_V004_REG_SW_EN_B_ADC2ADC_14D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14DC_CKGEN01_V004 (CKGEN01_V004 + 0x14DC)
	#define REG_14DC_CKGEN01_V004_REG_SW_EN_B_INT2ADC_14DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E0_CKGEN01_V004 (CKGEN01_V004 + 0x14E0)
	#define REG_14E0_CKGEN01_V004_REG_SW_EN_CLKPLL2ADC_14E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E4_CKGEN01_V004 (CKGEN01_V004 + 0x14E4)
	#define REG_14E4_CKGEN01_V004_REG_SW_EN_CVBS_DAC_A_DIGITAL0_MUX2ADC_14E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E8_CKGEN01_V004 (CKGEN01_V004 + 0x14E8)
	#define REG_14E8_CKGEN01_V004_REG_SW_EN_CVBS_DAC_A_DIGITAL02ADC_14E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14EC_CKGEN01_V004 (CKGEN01_V004 + 0x14EC)
	#define REG_14EC_CKGEN01_V004_REG_SW_EN_CVBS_DAC_A_DIGITAL12ADC_14EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14F0_CKGEN01_V004 (CKGEN01_V004 + 0x14F0)
	#define REG_14F0_CKGEN01_V004_REG_SW_EN_DIG_2162ADC_14F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14F4_CKGEN01_V004 (CKGEN01_V004 + 0x14F4)
	#define REG_14F4_CKGEN01_V004_REG_SW_EN_FBLANK2ADC_14F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14F8_CKGEN01_V004 (CKGEN01_V004 + 0x14F8)
	#define REG_14F8_CKGEN01_V004_REG_SW_EN_FSC_VD2ADC_14F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1500_CKGEN01_V004 (CKGEN01_V004 + 0x1500)
	#define REG_1500_CKGEN01_V004_REG_SW_EN_G_ADC2ADC_1500 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1504_CKGEN01_V004 (CKGEN01_V004 + 0x1504)
	#define REG_1504_CKGEN01_V004_REG_SW_EN_G_INT2ADC_1504 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1508_CKGEN01_V004 (CKGEN01_V004 + 0x1508)
	#define REG_1508_CKGEN01_V004_REG_SW_EN_ISOG2ADC_1508 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1510_CKGEN01_V004 (CKGEN01_V004 + 0x1510)
	#define REG_1510_CKGEN01_V004_REG_SW_EN_NCO_CLK2ADC_1510 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1518_CKGEN01_V004 (CKGEN01_V004 + 0x1518)
	#define REG_1518_CKGEN01_V004_REG_SW_EN_R_ADC2ADC_1518 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_151C_CKGEN01_V004 (CKGEN01_V004 + 0x151C)
	#define REG_151C_CKGEN01_V004_REG_SW_EN_R_INT2ADC_151C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1520_CKGEN01_V004 (CKGEN01_V004 + 0x1520)
	#define REG_1520_CKGEN01_V004_REG_SW_EN_VD_ICLAMP2ADC_1520 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1524_CKGEN01_V004 (CKGEN01_V004 + 0x1524)
	#define REG_1524_CKGEN01_V004_REG_SW_EN_VD_ICLAMP2VIDEO_ATOP_1524 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1528_CKGEN01_V004 (CKGEN01_V004 + 0x1528)
	#define REG_1528_CKGEN01_V004_REG_SW_EN_VD_NCO_CLK2ADC_1528 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_152C_CKGEN01_V004 (CKGEN01_V004 + 0x152C)
	#define REG_152C_CKGEN01_V004_REG_SW_EN_VD2ADC_152C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1530_CKGEN01_V004 (CKGEN01_V004 + 0x1530)
	#define REG_1530_CKGEN01_V004_REG_SW_EN_VDPLL4002ADC_1530 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1534_CKGEN01_V004 (CKGEN01_V004 + 0x1534)
	#define REG_1534_CKGEN01_V004_REG_SW_EN_XTAL12_4INTERRUPT2ADC_1534 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1538_CKGEN01_V004 (CKGEN01_V004 + 0x1538)
	#define REG_1538_CKGEN01_V004_REG_SW_EN_XTAL12_4PLUGDET2ADC_1538 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_153C_CKGEN01_V004 (CKGEN01_V004 + 0x153C)
	#define REG_153C_CKGEN01_V004_REG_SW_EN_XTAL122ADC_153C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1540_CKGEN01_V004 (CKGEN01_V004 + 0x1540)
	#define REG_1540_CKGEN01_V004_REG_SW_EN_XTAL242ADC_1540 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1544_CKGEN01_V004 (CKGEN01_V004 + 0x1544)
	#define REG_1544_CKGEN01_V004_REG_SW_EN_Y_ADC2ADC_1544 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1548_CKGEN01_V004 (CKGEN01_V004 + 0x1548)
	#define REG_1548_CKGEN01_V004_REG_SW_EN_Y_INT2ADC_1548 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_154C_CKGEN01_V004 (CKGEN01_V004 + 0x154C)
	#define REG_154C_CKGEN01_V004_REG_SW_EN_YUV_ADC2ADC_154C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1550_CKGEN01_V004 (CKGEN01_V004 + 0x1550)
	#define REG_1550_CKGEN01_V004_REG_SW_EN_ADCPLB_MPLL2ADC_1550 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1554_CKGEN01_V004 (CKGEN01_V004 + 0x1554)
	#define REG_1554_CKGEN01_V004_REG_SW_EN_GCE_F26M2GCE_BIU_1554 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1554_CKGEN01_V004_REG_SW_EN_GCE_F26M2VDEC_SOC_MBIST_1554 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1554_CKGEN01_V004_REG_SW_EN_SMI_GCE2GCE_BIU_1554 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1554_CKGEN01_V004_REG_SW_EN_VDEC_SYS_F2CORE0_1554 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1554_CKGEN01_V004_REG_SW_EN_VDEC_SYS_S2CORE0_1554 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1554_CKGEN01_V004_REG_SW_EN_XIU2GCE_BIU_1554 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_1558_CKGEN01_V004 (CKGEN01_V004 + 0x1558)
	#define REG_1558_CKGEN01_V004_REG_SW_EN_SMI2CORE0_MERGE_1558 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1558_CKGEN01_V004_REG_SW_EN_VDEC_SYS_F2CORE0_MERGE_1558 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1558_CKGEN01_V004_REG_SW_EN_VDEC_SYS_S2CORE0_MERGE_1558 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1558_CKGEN01_V004_REG_SW_EN_VDEC_BUS2CORE0_MERGE_1558 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1560_CKGEN01_V004 (CKGEN01_V004 + 0x1560)
	#define REG_1560_CKGEN01_V004_REG_SW_EN_XC_IP_AUL_CLK_MERGE2SCIP_1560 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1564_CKGEN01_V004 (CKGEN01_V004 + 0x1564)
	#define REG_1564_CKGEN01_V004_REG_SW_EN_DISP_MFDEC2GPU_PAR_GP_1564 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1564_CKGEN01_V004_REG_SW_EN_DISP_MFDEC2SCNR_1564 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1568_CKGEN01_V004 (CKGEN01_V004 + 0x1568)
	#define REG_1568_CKGEN01_V004_REG_SW_EN_DAP2AUDEC_1568 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_156C_CKGEN01_V004 (CKGEN01_V004 + 0x156C)
	#define REG_156C_CKGEN01_V004_REG_SW_EN_DAP2AUSND_156C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1570_CKGEN01_V004 (CKGEN01_V004 + 0x1570)
	#define REG_1570_CKGEN01_V004_REG_SW_EN_DAP2FRCMISC_1570 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1574_CKGEN01_V004 (CKGEN01_V004 + 0x1574)
	#define REG_1574_CKGEN01_V004_REG_SW_EN_DAP2AUDAP_1574 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1578_CKGEN01_V004 (CKGEN01_V004 + 0x1578)
	#define REG_1578_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2X2FRCCORE1_1578 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1578_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2X2FRCCORE3_1578 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_157C_CKGEN01_V004 (CKGEN01_V004 + 0x157C)
	#define REG_157C_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2XPLUS2FRCCORE1_157C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_157C_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2XPLUS2SCIP_157C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_157C_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2XPLUS2SCBE_157C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_157C_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2XPLUS2SCNR_157C Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1580_CKGEN01_V004 (CKGEN01_V004 + 0x1580)
	#define REG_1580_CKGEN01_V004_REG_SW_EN_FRC_FCLK2FRCCORE2_1580 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1588_CKGEN01_V004 (CKGEN01_V004 + 0x1588)
	#define REG_1588_CKGEN01_V004_REG_SW_EN_R2_FRC2FRCMISC_1588 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_159C_CKGEN01_V004 (CKGEN01_V004 + 0x159C)
	#define REG_159C_CKGEN01_V004_REG_SW_EN_RV55DAP_JTAG_TCK2FRCMISC_159C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B0_CKGEN01_V004 (CKGEN01_V004 + 0x15B0)
	#define REG_15B0_CKGEN01_V004_REG_SW_EN_XTAL2AURV55MBIST_15B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B4_CKGEN01_V004 (CKGEN01_V004 + 0x15B4)
	#define REG_15B4_CKGEN01_V004_REG_SW_EN_XTAL_12M2FRCMISC_15B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B8_CKGEN01_V004 (CKGEN01_V004 + 0x15B8)
	#define REG_15B8_CKGEN01_V004_REG_SW_EN_XTAL2AUDEC_15B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15BC_CKGEN01_V004 (CKGEN01_V004 + 0x15BC)
	#define REG_15BC_CKGEN01_V004_REG_SW_EN_XTAL2AUSND_15BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C0_CKGEN01_V004 (CKGEN01_V004 + 0x15C0)
	#define REG_15C0_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRCCORE1_15C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_15C0_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRCCORE2_15C0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_15C0_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRCCORE3_15C0 Fld(1,4,AC_MSKB0)//[4:4]
#define REG_15C4_CKGEN01_V004 (CKGEN01_V004 + 0x15C4)
	#define REG_15C4_CKGEN01_V004_REG_SW_EN_WB2AUDEC_15C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C8_CKGEN01_V004 (CKGEN01_V004 + 0x15C8)
	#define REG_15C8_CKGEN01_V004_REG_SW_EN_WB2AUSND_15C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15CC_CKGEN01_V004 (CKGEN01_V004 + 0x15CC)
	#define REG_15CC_CKGEN01_V004_REG_SW_EN_GE_FIFO_R2GE_15CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D0_CKGEN01_V004 (CKGEN01_V004 + 0x15D0)
	#define REG_15D0_CKGEN01_V004_REG_SW_EN_GE_FIFO_W2GE_15D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D4_CKGEN01_V004 (CKGEN01_V004 + 0x15D4)
	#define REG_15D4_CKGEN01_V004_REG_SW_EN_GE_PSRAM2GE_15D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D8_CKGEN01_V004 (CKGEN01_V004 + 0x15D8)
	#define REG_15D8_CKGEN01_V004_REG_SW_EN_GE2GE_15D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15DC_CKGEN01_V004 (CKGEN01_V004 + 0x15DC)
	#define REG_15DC_CKGEN01_V004_REG_SW_EN_V1_ODCLK2SCTC_15DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E0_CKGEN01_V004 (CKGEN01_V004 + 0x15E0)
	#define REG_15E0_CKGEN01_V004_REG_SW_EN_XTAL_24M2SEC_R2_15E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E4_CKGEN01_V004 (CKGEN01_V004 + 0x15E4)
	#define REG_15E4_CKGEN01_V004_REG_SW_EN_CLK_128FS_FB_S02MAC_15E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E8_CKGEN01_V004 (CKGEN01_V004 + 0x15E8)
	#define REG_15E8_CKGEN01_V004_REG_SW_EN_CLK_128FS_FB_S12MAC_15E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15EC_CKGEN01_V004 (CKGEN01_V004 + 0x15EC)
	#define REG_15EC_CKGEN01_V004_REG_SW_EN_CLK_128FS_S02MAC_15EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F0_CKGEN01_V004 (CKGEN01_V004 + 0x15F0)
	#define REG_15F0_CKGEN01_V004_REG_SW_EN_CLK_128FS_S12MAC_15F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F4_CKGEN01_V004 (CKGEN01_V004 + 0x15F4)
	#define REG_15F4_CKGEN01_V004_REG_SW_EN_CLK_2162MAC_15F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F8_CKGEN01_V004 (CKGEN01_V004 + 0x15F8)
	#define REG_15F8_CKGEN01_V004_REG_SW_EN_CLK_CTS_SYNTH_S02MAC_15F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15FC_CKGEN01_V004 (CKGEN01_V004 + 0x15FC)
	#define REG_15FC_CKGEN01_V004_REG_SW_EN_CLK_CTS_SYNTH_S12MAC_15FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1600_CKGEN01_V004 (CKGEN01_V004 + 0x1600)
	#define REG_1600_CKGEN01_V004_REG_SW_EN_CLK_DET_INNER_MISC_02MAC_1600 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1604_CKGEN01_V004 (CKGEN01_V004 + 0x1604)
	#define REG_1604_CKGEN01_V004_REG_SW_EN_CLK_DET_INNER_MISC_12MAC_1604 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1608_CKGEN01_V004 (CKGEN01_V004 + 0x1608)
	#define REG_1608_CKGEN01_V004_REG_SW_EN_CLK_DSC_ENGINE2DSC_1608 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_160C_CKGEN01_V004 (CKGEN01_V004 + 0x160C)
	#define REG_160C_CKGEN01_V004_REG_SW_EN_CLK_DVI2MIU_RD_S02MAC_160C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1610_CKGEN01_V004 (CKGEN01_V004 + 0x1610)
	#define REG_1610_CKGEN01_V004_REG_SW_EN_CLK_DVI2MIU_RD_S12MAC_1610 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1614_CKGEN01_V004 (CKGEN01_V004 + 0x1614)
	#define REG_1614_CKGEN01_V004_REG_SW_EN_CLK_DVI2MIU_WR_S02MAC_1614 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1618_CKGEN01_V004 (CKGEN01_V004 + 0x1618)
	#define REG_1618_CKGEN01_V004_REG_SW_EN_CLK_DVI2MIU_WR_S12MAC_1618 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_161C_CKGEN01_V004 (CKGEN01_V004 + 0x161C)
	#define REG_161C_CKGEN01_V004_REG_SW_EN_CLK_LINK_DSCD2MAC_161C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1620_CKGEN01_V004 (CKGEN01_V004 + 0x1620)
	#define REG_1620_CKGEN01_V004_REG_SW_EN_CLK_MPLL_4322MAC_1620 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1624_CKGEN01_V004 (CKGEN01_V004 + 0x1624)
	#define REG_1624_CKGEN01_V004_REG_SW_EN_CLK_MPLL_8642PHY_1624 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1628_CKGEN01_V004 (CKGEN01_V004 + 0x1628)
	#define REG_1628_CKGEN01_V004_REG_SW_EN_CLK_PIX_TMDSPLL_DSCD2MAC_1628 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_162C_CKGEN01_V004 (CKGEN01_V004 + 0x162C)
	#define REG_162C_CKGEN01_V004_REG_SW_EN_CLK_PIX_XC_S02MAC_162C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1630_CKGEN01_V004 (CKGEN01_V004 + 0x1630)
	#define REG_1630_CKGEN01_V004_REG_SW_EN_CLK_PIX_XC_S12MAC_1630 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1634_CKGEN01_V004 (CKGEN01_V004 + 0x1634)
	#define REG_1634_CKGEN01_V004_REG_SW_EN_CLK_R2_HDMI2MAC_1634 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1638_CKGEN01_V004 (CKGEN01_V004 + 0x1638)
	#define REG_1638_CKGEN01_V004_REG_SW_EN_CLK_TIMING_DET_DTOP2MAC_1638 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_163C_CKGEN01_V004 (CKGEN01_V004 + 0x163C)
	#define REG_163C_CKGEN01_V004_REG_SW_EN_CLK_TMDS_AUDIO_S02MAC_163C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1640_CKGEN01_V004 (CKGEN01_V004 + 0x1640)
	#define REG_1640_CKGEN01_V004_REG_SW_EN_CLK_TMDS_AUDIO_S12MAC_1640 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1644_CKGEN01_V004 (CKGEN01_V004 + 0x1644)
	#define REG_1644_CKGEN01_V004_REG_SW_EN_CLK_TMDS_DSCD2MAC_1644 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1648_CKGEN01_V004 (CKGEN01_V004 + 0x1648)
	#define REG_1648_CKGEN01_V004_REG_SW_EN_CLK_XTAL_242MAC_1648 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_164C_CKGEN01_V004 (CKGEN01_V004 + 0x164C)
	#define REG_164C_CKGEN01_V004_REG_SW_EN_CLK_XTAL_HDMI_122MAC_164C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1650_CKGEN01_V004 (CKGEN01_V004 + 0x1650)
	#define REG_1650_CKGEN01_V004_REG_SW_EN_EARC_AUDIO2EARC_1650 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1654_CKGEN01_V004 (CKGEN01_V004 + 0x1654)
	#define REG_1654_CKGEN01_V004_REG_SW_EN_EARC_CM2EARC_1654 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1658_CKGEN01_V004 (CKGEN01_V004 + 0x1658)
	#define REG_1658_CKGEN01_V004_REG_SW_EN_EARC_DEBOUNCE2EARC_1658 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_165C_CKGEN01_V004 (CKGEN01_V004 + 0x165C)
	#define REG_165C_CKGEN01_V004_REG_SW_EN_EARC_DM_PRBS2EARC_165C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1660_CKGEN01_V004 (CKGEN01_V004 + 0x1660)
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP_CIPHER_1P2MAC_1660 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP_CIPHER_8P2MAC_1660 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP_CIPHER_1P2MAC_1660 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP_CIPHER_8P2MAC_1660 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP_CIPHER_1P2MAC_1660 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP_CIPHER_8P2MAC_1660 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP_CIPHER_1P2MAC_1660 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP_CIPHER_8P2MAC_1660 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP14_CIPHER_1P2MAC_1660 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP14_CIPHER_1P2MAC_1660 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP14_CIPHER_1P2MAC_1660 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1660_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP14_CIPHER_1P2MAC_1660 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1664_CKGEN01_V004 (CKGEN01_V004 + 0x1664)
	#define REG_1664_CKGEN01_V004_REG_SW_EN_P0_CLK_DET_DEC_MISC_02MAC_1664 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1668_CKGEN01_V004 (CKGEN01_V004 + 0x1668)
	#define REG_1668_CKGEN01_V004_REG_SW_EN_P0_CLK_DET_DEC_MISC_12MAC_1668 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_166C_CKGEN01_V004 (CKGEN01_V004 + 0x166C)
	#define REG_166C_CKGEN01_V004_REG_SW_EN_P0_CLK_DET_DEP_MISC_02MAC_166C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1670_CKGEN01_V004 (CKGEN01_V004 + 0x1670)
	#define REG_1670_CKGEN01_V004_REG_SW_EN_P0_CLK_DET_DEP_MISC_12MAC_1670 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1674_CKGEN01_V004 (CKGEN01_V004 + 0x1674)
	#define REG_1674_CKGEN01_V004_REG_SW_EN_P0_CLK_LINK2MAC_1674 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1678_CKGEN01_V004 (CKGEN01_V004 + 0x1678)
	#define REG_1678_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_1P2MAC_1678 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_167C_CKGEN01_V004 (CKGEN01_V004 + 0x167C)
	#define REG_167C_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_8P2MAC_167C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1680_CKGEN01_V004 (CKGEN01_V004 + 0x1680)
	#define REG_1680_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_DC_MUX2MAC_1680 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1684_CKGEN01_V004 (CKGEN01_V004 + 0x1684)
	#define REG_1684_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_RCV_MUX2MAC_1684 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1688_CKGEN01_V004 (CKGEN01_V004 + 0x1688)
	#define REG_1688_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_REP_1P2MAC_1688 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_168C_CKGEN01_V004 (CKGEN01_V004 + 0x168C)
	#define REG_168C_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_TMDSPLL2MAC_168C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1690_CKGEN01_V004 (CKGEN01_V004 + 0x1690)
	#define REG_1690_CKGEN01_V004_REG_SW_EN_P0_CLK_PIX_XC_MUX2MAC_1690 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1694_CKGEN01_V004 (CKGEN01_V004 + 0x1694)
	#define REG_1694_CKGEN01_V004_REG_SW_EN_P0_CLK_TIMING_DET_DEC2MAC_1694 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1698_CKGEN01_V004 (CKGEN01_V004 + 0x1698)
	#define REG_1698_CKGEN01_V004_REG_SW_EN_P0_CLK_TIMING_DET_DEP2MAC_1698 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_169C_CKGEN01_V004 (CKGEN01_V004 + 0x169C)
	#define REG_169C_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_FRL_8P2MAC_169C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A0_CKGEN01_V004 (CKGEN01_V004 + 0x16A0)
	#define REG_16A0_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP_1P2MAC_16A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A4_CKGEN01_V004 (CKGEN01_V004 + 0x16A4)
	#define REG_16A4_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP_4P2MAC_16A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A8_CKGEN01_V004 (CKGEN01_V004 + 0x16A8)
	#define REG_16A8_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP_8P2MAC_16A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16AC_CKGEN01_V004 (CKGEN01_V004 + 0x16AC)
	#define REG_16AC_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDCP_MUX2MAC_16AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B0_CKGEN01_V004 (CKGEN01_V004 + 0x16B0)
	#define REG_16B0_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDMI_1P2MAC_16B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B4_CKGEN01_V004 (CKGEN01_V004 + 0x16B4)
	#define REG_16B4_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDMI_8P2MAC_16B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B8_CKGEN01_V004 (CKGEN01_V004 + 0x16B8)
	#define REG_16B8_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDS_HDMI_MUX2MAC_16B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16BC_CKGEN01_V004 (CKGEN01_V004 + 0x16BC)
	#define REG_16BC_CKGEN01_V004_REG_SW_EN_P1_CLK_DET_DEC_MISC_02MAC_16BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C0_CKGEN01_V004 (CKGEN01_V004 + 0x16C0)
	#define REG_16C0_CKGEN01_V004_REG_SW_EN_P1_CLK_DET_DEC_MISC_12MAC_16C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C4_CKGEN01_V004 (CKGEN01_V004 + 0x16C4)
	#define REG_16C4_CKGEN01_V004_REG_SW_EN_P1_CLK_DET_DEP_MISC_02MAC_16C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C8_CKGEN01_V004 (CKGEN01_V004 + 0x16C8)
	#define REG_16C8_CKGEN01_V004_REG_SW_EN_P1_CLK_DET_DEP_MISC_12MAC_16C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16CC_CKGEN01_V004 (CKGEN01_V004 + 0x16CC)
	#define REG_16CC_CKGEN01_V004_REG_SW_EN_P1_CLK_LINK2MAC_16CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D0_CKGEN01_V004 (CKGEN01_V004 + 0x16D0)
	#define REG_16D0_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_1P2MAC_16D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D4_CKGEN01_V004 (CKGEN01_V004 + 0x16D4)
	#define REG_16D4_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_8P2MAC_16D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D8_CKGEN01_V004 (CKGEN01_V004 + 0x16D8)
	#define REG_16D8_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_DC_MUX2MAC_16D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16DC_CKGEN01_V004 (CKGEN01_V004 + 0x16DC)
	#define REG_16DC_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_RCV_MUX2MAC_16DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E0_CKGEN01_V004 (CKGEN01_V004 + 0x16E0)
	#define REG_16E0_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_REP_1P2MAC_16E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E4_CKGEN01_V004 (CKGEN01_V004 + 0x16E4)
	#define REG_16E4_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_TMDSPLL2MAC_16E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E8_CKGEN01_V004 (CKGEN01_V004 + 0x16E8)
	#define REG_16E8_CKGEN01_V004_REG_SW_EN_P1_CLK_PIX_XC_MUX2MAC_16E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16EC_CKGEN01_V004 (CKGEN01_V004 + 0x16EC)
	#define REG_16EC_CKGEN01_V004_REG_SW_EN_P1_CLK_TIMING_DET_DEC2MAC_16EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F0_CKGEN01_V004 (CKGEN01_V004 + 0x16F0)
	#define REG_16F0_CKGEN01_V004_REG_SW_EN_P1_CLK_TIMING_DET_DEP2MAC_16F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F4_CKGEN01_V004 (CKGEN01_V004 + 0x16F4)
	#define REG_16F4_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_FRL_8P2MAC_16F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F8_CKGEN01_V004 (CKGEN01_V004 + 0x16F8)
	#define REG_16F8_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP_1P2MAC_16F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16FC_CKGEN01_V004 (CKGEN01_V004 + 0x16FC)
	#define REG_16FC_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP_4P2MAC_16FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1700_CKGEN01_V004 (CKGEN01_V004 + 0x1700)
	#define REG_1700_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP_8P2MAC_1700 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1704_CKGEN01_V004 (CKGEN01_V004 + 0x1704)
	#define REG_1704_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDCP_MUX2MAC_1704 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1708_CKGEN01_V004 (CKGEN01_V004 + 0x1708)
	#define REG_1708_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDMI_1P2MAC_1708 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_170C_CKGEN01_V004 (CKGEN01_V004 + 0x170C)
	#define REG_170C_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDMI_8P2MAC_170C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1710_CKGEN01_V004 (CKGEN01_V004 + 0x1710)
	#define REG_1710_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDS_HDMI_MUX2MAC_1710 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1714_CKGEN01_V004 (CKGEN01_V004 + 0x1714)
	#define REG_1714_CKGEN01_V004_REG_SW_EN_P2_CLK_DET_DEC_MISC_02MAC_1714 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1718_CKGEN01_V004 (CKGEN01_V004 + 0x1718)
	#define REG_1718_CKGEN01_V004_REG_SW_EN_P2_CLK_DET_DEC_MISC_12MAC_1718 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_171C_CKGEN01_V004 (CKGEN01_V004 + 0x171C)
	#define REG_171C_CKGEN01_V004_REG_SW_EN_P2_CLK_DET_DEP_MISC_02MAC_171C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1720_CKGEN01_V004 (CKGEN01_V004 + 0x1720)
	#define REG_1720_CKGEN01_V004_REG_SW_EN_P2_CLK_DET_DEP_MISC_12MAC_1720 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1724_CKGEN01_V004 (CKGEN01_V004 + 0x1724)
	#define REG_1724_CKGEN01_V004_REG_SW_EN_P2_CLK_LINK2MAC_1724 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1728_CKGEN01_V004 (CKGEN01_V004 + 0x1728)
	#define REG_1728_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_1P2MAC_1728 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_172C_CKGEN01_V004 (CKGEN01_V004 + 0x172C)
	#define REG_172C_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_8P2MAC_172C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1730_CKGEN01_V004 (CKGEN01_V004 + 0x1730)
	#define REG_1730_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_DC_MUX2MAC_1730 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1734_CKGEN01_V004 (CKGEN01_V004 + 0x1734)
	#define REG_1734_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_RCV_MUX2MAC_1734 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1738_CKGEN01_V004 (CKGEN01_V004 + 0x1738)
	#define REG_1738_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_REP_1P2MAC_1738 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_173C_CKGEN01_V004 (CKGEN01_V004 + 0x173C)
	#define REG_173C_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_TMDSPLL2MAC_173C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1740_CKGEN01_V004 (CKGEN01_V004 + 0x1740)
	#define REG_1740_CKGEN01_V004_REG_SW_EN_P2_CLK_PIX_XC_MUX2MAC_1740 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1744_CKGEN01_V004 (CKGEN01_V004 + 0x1744)
	#define REG_1744_CKGEN01_V004_REG_SW_EN_P2_CLK_TIMING_DET_DEC2MAC_1744 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1748_CKGEN01_V004 (CKGEN01_V004 + 0x1748)
	#define REG_1748_CKGEN01_V004_REG_SW_EN_P2_CLK_TIMING_DET_DEP2MAC_1748 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_174C_CKGEN01_V004 (CKGEN01_V004 + 0x174C)
	#define REG_174C_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_FRL_8P2MAC_174C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1750_CKGEN01_V004 (CKGEN01_V004 + 0x1750)
	#define REG_1750_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP_1P2MAC_1750 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1754_CKGEN01_V004 (CKGEN01_V004 + 0x1754)
	#define REG_1754_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP_4P2MAC_1754 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1758_CKGEN01_V004 (CKGEN01_V004 + 0x1758)
	#define REG_1758_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP_8P2MAC_1758 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_175C_CKGEN01_V004 (CKGEN01_V004 + 0x175C)
	#define REG_175C_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDCP_MUX2MAC_175C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1760_CKGEN01_V004 (CKGEN01_V004 + 0x1760)
	#define REG_1760_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDMI_1P2MAC_1760 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1764_CKGEN01_V004 (CKGEN01_V004 + 0x1764)
	#define REG_1764_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDMI_8P2MAC_1764 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1768_CKGEN01_V004 (CKGEN01_V004 + 0x1768)
	#define REG_1768_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDS_HDMI_MUX2MAC_1768 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_176C_CKGEN01_V004 (CKGEN01_V004 + 0x176C)
	#define REG_176C_CKGEN01_V004_REG_SW_EN_P3_CLK_DET_DEC_MISC_02MAC_176C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1770_CKGEN01_V004 (CKGEN01_V004 + 0x1770)
	#define REG_1770_CKGEN01_V004_REG_SW_EN_P3_CLK_DET_DEC_MISC_12MAC_1770 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1774_CKGEN01_V004 (CKGEN01_V004 + 0x1774)
	#define REG_1774_CKGEN01_V004_REG_SW_EN_P3_CLK_DET_DEP_MISC_02MAC_1774 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1778_CKGEN01_V004 (CKGEN01_V004 + 0x1778)
	#define REG_1778_CKGEN01_V004_REG_SW_EN_P3_CLK_DET_DEP_MISC_12MAC_1778 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_177C_CKGEN01_V004 (CKGEN01_V004 + 0x177C)
	#define REG_177C_CKGEN01_V004_REG_SW_EN_P3_CLK_LINK2MAC_177C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1780_CKGEN01_V004 (CKGEN01_V004 + 0x1780)
	#define REG_1780_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_1P2MAC_1780 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1784_CKGEN01_V004 (CKGEN01_V004 + 0x1784)
	#define REG_1784_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_8P2MAC_1784 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1788_CKGEN01_V004 (CKGEN01_V004 + 0x1788)
	#define REG_1788_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_DC_MUX2MAC_1788 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_178C_CKGEN01_V004 (CKGEN01_V004 + 0x178C)
	#define REG_178C_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_RCV_MUX2MAC_178C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1790_CKGEN01_V004 (CKGEN01_V004 + 0x1790)
	#define REG_1790_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_REP_1P2MAC_1790 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1794_CKGEN01_V004 (CKGEN01_V004 + 0x1794)
	#define REG_1794_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_TMDSPLL2MAC_1794 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1798_CKGEN01_V004 (CKGEN01_V004 + 0x1798)
	#define REG_1798_CKGEN01_V004_REG_SW_EN_P3_CLK_PIX_XC_MUX2MAC_1798 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_179C_CKGEN01_V004 (CKGEN01_V004 + 0x179C)
	#define REG_179C_CKGEN01_V004_REG_SW_EN_P3_CLK_TIMING_DET_DEC2MAC_179C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A0_CKGEN01_V004 (CKGEN01_V004 + 0x17A0)
	#define REG_17A0_CKGEN01_V004_REG_SW_EN_P3_CLK_TIMING_DET_DEP2MAC_17A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A4_CKGEN01_V004 (CKGEN01_V004 + 0x17A4)
	#define REG_17A4_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_FRL_8P2MAC_17A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A8_CKGEN01_V004 (CKGEN01_V004 + 0x17A8)
	#define REG_17A8_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP_1P2MAC_17A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17AC_CKGEN01_V004 (CKGEN01_V004 + 0x17AC)
	#define REG_17AC_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP_4P2MAC_17AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B0_CKGEN01_V004 (CKGEN01_V004 + 0x17B0)
	#define REG_17B0_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP_8P2MAC_17B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B4_CKGEN01_V004 (CKGEN01_V004 + 0x17B4)
	#define REG_17B4_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDCP_MUX2MAC_17B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B8_CKGEN01_V004 (CKGEN01_V004 + 0x17B8)
	#define REG_17B8_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDMI_1P2MAC_17B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17BC_CKGEN01_V004 (CKGEN01_V004 + 0x17BC)
	#define REG_17BC_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDMI_8P2MAC_17BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C0_CKGEN01_V004 (CKGEN01_V004 + 0x17C0)
	#define REG_17C0_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDS_HDMI_MUX2MAC_17C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C4_CKGEN01_V004 (CKGEN01_V004 + 0x17C4)
	#define REG_17C4_CKGEN01_V004_REG_SW_EN_XC_LPLL_DIV42SCTC_17C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C8_CKGEN01_V004 (CKGEN01_V004 + 0x17C8)
	#define REG_17C8_CKGEN01_V004_REG_SW_EN_O_ODCLK2SCTC_17C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17CC_CKGEN01_V004 (CKGEN01_V004 + 0x17CC)
	#define REG_17CC_CKGEN01_V004_REG_SW_EN_V2_ODCLK2SCTC_17CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17D0_CKGEN01_V004 (CKGEN01_V004 + 0x17D0)
	#define REG_17D0_CKGEN01_V004_REG_SW_EN_XC_GOP_SCL2SCTC_17D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17D4_CKGEN01_V004 (CKGEN01_V004 + 0x17D4)
	#define REG_17D4_CKGEN01_V004_REG_SW_EN_XC_GOP2SCTC_17D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17D8_CKGEN01_V004 (CKGEN01_V004 + 0x17D8)
	#define REG_17D8_CKGEN01_V004_REG_SW_EN_XC_OD_1P2SCTC_17D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17DC_CKGEN01_V004 (CKGEN01_V004 + 0x17DC)
	#define REG_17DC_CKGEN01_V004_REG_SW_EN_XC_OD_B2P2SCTC_17DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E0_CKGEN01_V004 (CKGEN01_V004 + 0x17E0)
	#define REG_17E0_CKGEN01_V004_REG_SW_EN_XC_OD_DELTA2SCTC_17E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_17E0_CKGEN01_V004_REG_SW_EN_XC_OD_DELTA2SCIP_17E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_17E0_CKGEN01_V004_REG_SW_EN_XC_OD_1P2SCIP_17E0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_17E0_CKGEN01_V004_REG_SW_EN_XC_OD_B2P2SCIP_17E0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_17E0_CKGEN01_V004_REG_SW_EN_XC_TTLIN2SCIP_17E0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_17E0_CKGEN01_V004_REG_SW_EN_XC_OD_DELTA2SCSCL_17E0 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_17E4_CKGEN01_V004 (CKGEN01_V004 + 0x17E4)
	#define REG_17E4_CKGEN01_V004_REG_SW_EN_XC_OD_F2P2SCTC_17E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E8_CKGEN01_V004 (CKGEN01_V004 + 0x17E8)
	#define REG_17E8_CKGEN01_V004_REG_SW_EN_XC_OD_LINEOD2SCTC_17E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17EC_CKGEN01_V004 (CKGEN01_V004 + 0x17EC)
	#define REG_17EC_CKGEN01_V004_REG_SW_EN_XC_OD_DIV22SCTC_17EC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_17EC_CKGEN01_V004_REG_SW_EN_XC_OD_DIV22SCIP_17EC Fld(1,8,AC_MSKB1)//[8:8]
#define REG_17F4_CKGEN01_V004 (CKGEN01_V004 + 0x17F4)
	#define REG_17F4_CKGEN01_V004_REG_SW_EN_DET_RCLK2DET_17F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F8_CKGEN01_V004 (CKGEN01_V004 + 0x17F8)
	#define REG_17F8_CKGEN01_V004_REG_SW_EN_DET_WCLK2DET_17F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17FC_CKGEN01_V004 (CKGEN01_V004 + 0x17FC)
	#define REG_17FC_CKGEN01_V004_REG_SW_EN_IDCLK2FPLL_17FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1800_CKGEN01_V004 (CKGEN01_V004 + 0x1800)
	#define REG_1800_CKGEN01_V004_REG_SW_EN_LPLL_ODCLK_NODIV2FPLL_1800 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1800_CKGEN01_V004_REG_SW_EN_LPLL_ODCLK_NODIV2TTL_1800 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1804_CKGEN01_V004 (CKGEN01_V004 + 0x1804)
	#define REG_1804_CKGEN01_V004_REG_SW_EN_LPLL_ODCLK2FPLL_1804 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1808_CKGEN01_V004 (CKGEN01_V004 + 0x1808)
	#define REG_1808_CKGEN01_V004_REG_SW_EN_LPLL_SYN_4322FPLL_1808 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1810_CKGEN01_V004 (CKGEN01_V004 + 0x1810)
	#define REG_1810_CKGEN01_V004_REG_SW_EN_MOD_A_ODCLK2MOD_A_1810 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1814_CKGEN01_V004 (CKGEN01_V004 + 0x1814)
	#define REG_1814_CKGEN01_V004_REG_SW_EN_MOD_D_ODCLK2MOD_D_1814 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1814_CKGEN01_V004_REG_SW_EN_MOD_D_ODCLK2LVDS_1814 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1814_CKGEN01_V004_REG_SW_EN_MOD_D_ODCLK2TTL_1814 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1818_CKGEN01_V004 (CKGEN01_V004 + 0x1818)
	#define REG_1818_CKGEN01_V004_REG_SW_EN_MOD_O_SR_WCLK2O_1818 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1818_CKGEN01_V004_REG_SW_EN_MOD_O_SR_WCLK2VBY1_O_1818 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_181C_CKGEN01_V004 (CKGEN01_V004 + 0x181C)
	#define REG_181C_CKGEN01_V004_REG_SW_EN_MOD_V1_SR_WCLK2V1_181C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_181C_CKGEN01_V004_REG_SW_EN_MOD_V1_SR_WCLK2VBY1_V1_181C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1820_CKGEN01_V004 (CKGEN01_V004 + 0x1820)
	#define REG_1820_CKGEN01_V004_REG_SW_EN_MOD_V2_SR_WCLK2V2_1820 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1820_CKGEN01_V004_REG_SW_EN_MOD_V2_SR_WCLK2VBY1_V2_1820 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1824_CKGEN01_V004 (CKGEN01_V004 + 0x1824)
	#define REG_1824_CKGEN01_V004_REG_SW_EN_O_MOD_SR_RCLK2O_1824 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1828_CKGEN01_V004 (CKGEN01_V004 + 0x1828)
	#define REG_1828_CKGEN01_V004_REG_SW_EN_O_ODCLK_STG12O_1828 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_182C_CKGEN01_V004 (CKGEN01_V004 + 0x182C)
	#define REG_182C_CKGEN01_V004_REG_SW_EN_O_ODCLK_STG22O_182C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1830_CKGEN01_V004 (CKGEN01_V004 + 0x1830)
	#define REG_1830_CKGEN01_V004_REG_SW_EN_O_ODCLK_STG32O_1830 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1834_CKGEN01_V004 (CKGEN01_V004 + 0x1834)
	#define REG_1834_CKGEN01_V004_REG_SW_EN_O_ODCLK_STG42O_1834 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1838_CKGEN01_V004 (CKGEN01_V004 + 0x1838)
	#define REG_1838_CKGEN01_V004_REG_SW_EN_O_ODCLK_STG52O_1838 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_183C_CKGEN01_V004 (CKGEN01_V004 + 0x183C)
	#define REG_183C_CKGEN01_V004_REG_SW_EN_O_ODCLK_STG62O_183C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1840_CKGEN01_V004 (CKGEN01_V004 + 0x1840)
	#define REG_1840_CKGEN01_V004_REG_SW_EN_O_ODCLK2O_1840 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1844_CKGEN01_V004 (CKGEN01_V004 + 0x1844)
	#define REG_1844_CKGEN01_V004_REG_SW_EN_PWM2PWM_1844 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1848_CKGEN01_V004 (CKGEN01_V004 + 0x1848)
	#define REG_1848_CKGEN01_V004_REG_SW_EN_V1_MOD_SR_RCLK2V1_1848 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_184C_CKGEN01_V004 (CKGEN01_V004 + 0x184C)
	#define REG_184C_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG12V1_184C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1850_CKGEN01_V004 (CKGEN01_V004 + 0x1850)
	#define REG_1850_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG22V1_1850 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1854_CKGEN01_V004 (CKGEN01_V004 + 0x1854)
	#define REG_1854_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG32V1_1854 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1858_CKGEN01_V004 (CKGEN01_V004 + 0x1858)
	#define REG_1858_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG42V1_1858 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_185C_CKGEN01_V004 (CKGEN01_V004 + 0x185C)
	#define REG_185C_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG52V1_185C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1860_CKGEN01_V004 (CKGEN01_V004 + 0x1860)
	#define REG_1860_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG62V1_1860 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1864_CKGEN01_V004 (CKGEN01_V004 + 0x1864)
	#define REG_1864_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG72V1_1864 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1868_CKGEN01_V004 (CKGEN01_V004 + 0x1868)
	#define REG_1868_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG82V1_1868 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_186C_CKGEN01_V004 (CKGEN01_V004 + 0x186C)
	#define REG_186C_CKGEN01_V004_REG_SW_EN_V1_ODCLK2V1_186C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1870_CKGEN01_V004 (CKGEN01_V004 + 0x1870)
	#define REG_1870_CKGEN01_V004_REG_SW_EN_V2_MOD_SR_RCLK2V2_1870 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1874_CKGEN01_V004 (CKGEN01_V004 + 0x1874)
	#define REG_1874_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG12V2_1874 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1878_CKGEN01_V004 (CKGEN01_V004 + 0x1878)
	#define REG_1878_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG22V2_1878 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_187C_CKGEN01_V004 (CKGEN01_V004 + 0x187C)
	#define REG_187C_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG32V2_187C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1880_CKGEN01_V004 (CKGEN01_V004 + 0x1880)
	#define REG_1880_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG42V2_1880 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1884_CKGEN01_V004 (CKGEN01_V004 + 0x1884)
	#define REG_1884_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG52V2_1884 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1888_CKGEN01_V004 (CKGEN01_V004 + 0x1888)
	#define REG_1888_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG62V2_1888 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_188C_CKGEN01_V004 (CKGEN01_V004 + 0x188C)
	#define REG_188C_CKGEN01_V004_REG_SW_EN_V2_ODCLK_STG72V2_188C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1890_CKGEN01_V004 (CKGEN01_V004 + 0x1890)
	#define REG_1890_CKGEN01_V004_REG_SW_EN_V2_ODCLK2V2_1890 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1894_CKGEN01_V004 (CKGEN01_V004 + 0x1894)
	#define REG_1894_CKGEN01_V004_REG_SW_EN_XTAL_12M2MOD_A_1894 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1894_CKGEN01_V004_REG_SW_EN_XTAL_12M2PWM_1894 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1898_CKGEN01_V004 (CKGEN01_V004 + 0x1898)
	#define REG_1898_CKGEN01_V004_REG_SW_EN_XTAL_24M2FPLL_1898 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_189C_CKGEN01_V004 (CKGEN01_V004 + 0x189C)
	#define REG_189C_CKGEN01_V004_REG_SW_EN_O_MOD_SR_RCLK_FINIAL2O_189C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A0_CKGEN01_V004 (CKGEN01_V004 + 0x18A0)
	#define REG_18A0_CKGEN01_V004_REG_SW_EN_O_MOD_SR_RCLK_PRE02O_18A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A4_CKGEN01_V004 (CKGEN01_V004 + 0x18A4)
	#define REG_18A4_CKGEN01_V004_REG_SW_EN_O_MOD_SR_RCLK_PRE12O_18A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A8_CKGEN01_V004 (CKGEN01_V004 + 0x18A8)
	#define REG_18A8_CKGEN01_V004_REG_SW_EN_V1_MOD_SR_RCLK_FINIAL2V1_18A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18AC_CKGEN01_V004 (CKGEN01_V004 + 0x18AC)
	#define REG_18AC_CKGEN01_V004_REG_SW_EN_V1_MOD_SR_RCLK_PRE02V1_18AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B0_CKGEN01_V004 (CKGEN01_V004 + 0x18B0)
	#define REG_18B0_CKGEN01_V004_REG_SW_EN_V1_MOD_SR_RCLK_PRE12V1_18B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B4_CKGEN01_V004 (CKGEN01_V004 + 0x18B4)
	#define REG_18B4_CKGEN01_V004_REG_SW_EN_V2_MOD_SR_RCLK_FINIAL2V2_18B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B8_CKGEN01_V004 (CKGEN01_V004 + 0x18B8)
	#define REG_18B8_CKGEN01_V004_REG_SW_EN_V2_MOD_SR_RCLK_PRE02V2_18B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18BC_CKGEN01_V004 (CKGEN01_V004 + 0x18BC)
	#define REG_18BC_CKGEN01_V004_REG_SW_EN_V2_MOD_SR_RCLK_PRE12V2_18BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C0_CKGEN01_V004 (CKGEN01_V004 + 0x18C0)
	#define REG_18C0_CKGEN01_V004_REG_SW_EN_V1_ODCLK_STG92V1_18C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C4_CKGEN01_V004 (CKGEN01_V004 + 0x18C4)
	#define REG_18C4_CKGEN01_V004_REG_SW_EN_PQ_GA_SRAM2SCDISP_18C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C8_CKGEN01_V004 (CKGEN01_V004 + 0x18C8)
	#define REG_18C8_CKGEN01_V004_REG_SW_EN_AISR_HVSP_SRAM2SCSR_18C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18CC_CKGEN01_V004 (CKGEN01_V004 + 0x18CC)
	#define REG_18CC_CKGEN01_V004_REG_SW_EN_XC_FS2SCTC_18CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D0_CKGEN01_V004 (CKGEN01_V004 + 0x18D0)
	#define REG_18D0_CKGEN01_V004_REG_SW_EN_XC_OD_OSD2SCTC_18D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D4_CKGEN01_V004 (CKGEN01_V004 + 0x18D4)
	#define REG_18D4_CKGEN01_V004_REG_SW_EN_AISR_SRAM2SCSR_18D4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_18D4_CKGEN01_V004_REG_SW_EN_AISR_SRAM_PH_12SCSR_18D4 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_18D8_CKGEN01_V004 (CKGEN01_V004 + 0x18D8)
	#define REG_18D8_CKGEN01_V004_REG_SW_EN_DC0_SRAM2SCIP_TMP_18D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18DC_CKGEN01_V004 (CKGEN01_V004 + 0x18DC)
	#define REG_18DC_CKGEN01_V004_REG_SW_EN_DBK_HW_SRAM2SCPQ_18DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E4_CKGEN01_V004 (CKGEN01_V004 + 0x18E4)
	#define REG_18E4_CKGEN01_V004_REG_SW_EN_DELTA_B2P2_SRAM2SCACE_18E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E8_CKGEN01_V004 (CKGEN01_V004 + 0x18E8)
	#define REG_18E8_CKGEN01_V004_REG_SW_EN_XC_OD_PAFRC2SCTC_18E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18EC_CKGEN01_V004 (CKGEN01_V004 + 0x18EC)
	#define REG_18EC_CKGEN01_V004_REG_SW_EN_DV_HW5_C2_SRAM2SCPQ_18EC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_18F0_CKGEN01_V004 (CKGEN01_V004 + 0x18F0)
	#define REG_18F0_CKGEN01_V004_REG_SW_EN_GOP0_SRAM2SCTC_TMP_18F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F4_CKGEN01_V004 (CKGEN01_V004 + 0x18F4)
	#define REG_18F4_CKGEN01_V004_REG_SW_EN_GOP1_SRAM2SCTC_TMP_18F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F8_CKGEN01_V004 (CKGEN01_V004 + 0x18F8)
	#define REG_18F8_CKGEN01_V004_REG_SW_EN_GOP2_SRAM2SCTC_TMP_18F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18FC_CKGEN01_V004 (CKGEN01_V004 + 0x18FC)
	#define REG_18FC_CKGEN01_V004_REG_SW_EN_GOP3_SRAM2SCTC_TMP_18FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1900_CKGEN01_V004 (CKGEN01_V004 + 0x1900)
	#define REG_1900_CKGEN01_V004_REG_SW_EN_GUCD_18_LUT2_SRAM2SCACE_1900 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1904_CKGEN01_V004 (CKGEN01_V004 + 0x1904)
	#define REG_1904_CKGEN01_V004_REG_SW_EN_GUCD_18_SRAM2SCSCL_1904 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1908_CKGEN01_V004 (CKGEN01_V004 + 0x1908)
	#define REG_1908_CKGEN01_V004_REG_SW_EN_GUCD_256_LUT2_SRAM2SCACE_1908 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_190C_CKGEN01_V004 (CKGEN01_V004 + 0x190C)
	#define REG_190C_CKGEN01_V004_REG_SW_EN_HDR_3D_SRAM2SCPQ_190C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1910_CKGEN01_V004 (CKGEN01_V004 + 0x1910)
	#define REG_1910_CKGEN01_V004_REG_SW_EN_HSY_8P_SRAM2SCMW_1910 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1910_CKGEN01_V004_REG_SW_EN_HSY_8P_SRAM2SCACE_1910 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1914_CKGEN01_V004 (CKGEN01_V004 + 0x1914)
	#define REG_1914_CKGEN01_V004_REG_SW_EN_HSY_8P3_SRAM2SCMW_1914 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1914_CKGEN01_V004_REG_SW_EN_HSY_8P3_SRAM2SCACE_1914 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1924_CKGEN01_V004 (CKGEN01_V004 + 0x1924)
	#define REG_1924_CKGEN01_V004_REG_SW_EN_HVSP_STP2_SRAM2SCSCL_1924 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1928_CKGEN01_V004 (CKGEN01_V004 + 0x1928)
	#define REG_1928_CKGEN01_V004_REG_SW_EN_LCE_ACE_SRAM2SCACE_1928 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1930_CKGEN01_V004 (CKGEN01_V004 + 0x1930)
	#define REG_1930_CKGEN01_V004_REG_SW_EN_LD_EDGE2D_SRAM2SCDISP_1930 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1934_CKGEN01_V004 (CKGEN01_V004 + 0x1934)
	#define REG_1934_CKGEN01_V004_REG_SW_EN_LDCOMP_SRAM2SCDISP_1934 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1938_CKGEN01_V004 (CKGEN01_V004 + 0x1938)
	#define REG_1938_CKGEN01_V004_REG_SW_EN_LDM_GA_SRAM2SCTC_1938 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_193C_CKGEN01_V004 (CKGEN01_V004 + 0x193C)
	#define REG_193C_CKGEN01_V004_REG_SW_EN_LDMCG_SRAM2SCDISP_193C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1940_CKGEN01_V004 (CKGEN01_V004 + 0x1940)
	#define REG_1940_CKGEN01_V004_REG_SW_EN_LPQ_PA_SRAM2SCTC_1940 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1944_CKGEN01_V004 (CKGEN01_V004 + 0x1944)
	#define REG_1944_CKGEN01_V004_REG_SW_EN_XC_OD_VAC2SCTC_1944 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1948_CKGEN01_V004 (CKGEN01_V004 + 0x1948)
	#define REG_1948_CKGEN01_V004_REG_SW_EN_PADJ_SRAM2SCTC_TMP_1948 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_194C_CKGEN01_V004 (CKGEN01_V004 + 0x194C)
	#define REG_194C_CKGEN01_V004_REG_SW_EN_PANEL_GA_SRAM2SCTC_TMP_194C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1950_CKGEN01_V004 (CKGEN01_V004 + 0x1950)
	#define REG_1950_CKGEN01_V004_REG_SW_EN_PQ_GAMMA_SRAM2SCMW_1950 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1954_CKGEN01_V004 (CKGEN01_V004 + 0x1954)
	#define REG_1954_CKGEN01_V004_REG_SW_EN_RGB_3DLUT_SRAM2SCMW_1954 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1958_CKGEN01_V004 (CKGEN01_V004 + 0x1958)
	#define REG_1958_CKGEN01_V004_REG_SW_EN_HDR_SRAM2SCPQ_1958 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_195C_CKGEN01_V004 (CKGEN01_V004 + 0x195C)
	#define REG_195C_CKGEN01_V004_REG_SW_EN_SPF_HDBK_SRAM2SCPQ_195C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1960_CKGEN01_V004 (CKGEN01_V004 + 0x1960)
	#define REG_1960_CKGEN01_V004_REG_SW_EN_UCD_ST_SRAM2SCIP_TMP_1960 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1964_CKGEN01_V004 (CKGEN01_V004 + 0x1964)
	#define REG_1964_CKGEN01_V004_REG_SW_EN_VDBK_SRAM2SCPQ_1964 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1968_CKGEN01_V004 (CKGEN01_V004 + 0x1968)
	#define REG_1968_CKGEN01_V004_REG_SW_EN_VIP_ACE_SRAM2SCACE_1968 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1970_CKGEN01_V004 (CKGEN01_V004 + 0x1970)
	#define REG_1970_CKGEN01_V004_REG_SW_EN_XC_ADC2SCIP_1970 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1974_CKGEN01_V004 (CKGEN01_V004 + 0x1974)
	#define REG_1974_CKGEN01_V004_REG_SW_EN_XC_AISR2SCSR_1974 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1978_CKGEN01_V004 (CKGEN01_V004 + 0x1978)
	#define REG_1978_CKGEN01_V004_REG_SW_EN_XC_SUB_DC02SCIP_1978 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_197C_CKGEN01_V004 (CKGEN01_V004 + 0x197C)
	#define REG_197C_CKGEN01_V004_REG_SW_EN_XC_DC02SCIP_197C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1980_CKGEN01_V004 (CKGEN01_V004 + 0x1980)
	#define REG_1980_CKGEN01_V004_REG_SW_EN_XC_DBG2MIU2SCIP_1980 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1984_CKGEN01_V004 (CKGEN01_V004 + 0x1984)
	#define REG_1984_CKGEN01_V004_REG_SW_EN_XC_DISP_MFDEC2SCIP_1984 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1988_CKGEN01_V004 (CKGEN01_V004 + 0x1988)
	#define REG_1988_CKGEN01_V004_REG_SW_EN_XC_ED02SCIP_1988 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_198C_CKGEN01_V004 (CKGEN01_V004 + 0x198C)
	#define REG_198C_CKGEN01_V004_REG_SW_EN_XC_ED12SCIP_198C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1990_CKGEN01_V004 (CKGEN01_V004 + 0x1990)
	#define REG_1990_CKGEN01_V004_REG_SW_EN_XC_FD2SCTC_1990 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1990_CKGEN01_V004_REG_SW_EN_XC_FD2SCIP_1990 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1990_CKGEN01_V004_REG_SW_EN_XC_FD2SCBE_1990 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1990_CKGEN01_V004_REG_SW_EN_XC_FD_DV2SCTC_1990 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1990_CKGEN01_V004_REG_SW_EN_PCID_SRAM2SCTC_TMP_1990 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1990_CKGEN01_V004_REG_SW_EN_XC_FD2SCPQ_1990 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1994_CKGEN01_V004 (CKGEN01_V004 + 0x1994)
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCIP_1994 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCM_1994 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCMO_1994 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCNR_1994 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCPQ_DOLBY_1994 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCPQ_SPF_1994 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCBE_1994 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_XC_FN2SCTC_1994 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1994_CKGEN01_V004_REG_SW_EN_OD_SRAM2SCTC_TMP_1994 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1998_CKGEN01_V004 (CKGEN01_V004 + 0x1998)
	#define REG_1998_CKGEN01_V004_REG_SW_EN_XC_FS2SCACE_HSY_1998 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1998_CKGEN01_V004_REG_SW_EN_XC_FS2SCACE_VIP_1998 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1998_CKGEN01_V004_REG_SW_EN_XC_FS2SCACE_VOP2_1998 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1998_CKGEN01_V004_REG_SW_EN_XC_VOP2SCBE_1998 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1998_CKGEN01_V004_REG_SW_EN_XC_FS2SCBE_1998 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1998_CKGEN01_V004_REG_SW_EN_XC_FS2SCIP_1998 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1998_CKGEN01_V004_REG_SW_EN_VAC_SRAM2SCTC_TMP_1998 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_199C_CKGEN01_V004 (CKGEN01_V004 + 0x199C)
	#define REG_199C_CKGEN01_V004_REG_SW_EN_XC_HD2MIU_M2SCIP_199C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A0_CKGEN01_V004 (CKGEN01_V004 + 0x19A0)
	#define REG_19A0_CKGEN01_V004_REG_SW_EN_XC_HD2MIU_S2SCIP_19A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A4_CKGEN01_V004 (CKGEN01_V004 + 0x19A4)
	#define REG_19A4_CKGEN01_V004_REG_SW_EN_XC_HDMI02SCIP_19A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A8_CKGEN01_V004 (CKGEN01_V004 + 0x19A8)
	#define REG_19A8_CKGEN01_V004_REG_SW_EN_XC_HDMI12SCIP_19A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19AC_CKGEN01_V004 (CKGEN01_V004 + 0x19AC)
	#define REG_19AC_CKGEN01_V004_REG_SW_EN_XC_HDMI22SCIP_19AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B0_CKGEN01_V004 (CKGEN01_V004 + 0x19B0)
	#define REG_19B0_CKGEN01_V004_REG_SW_EN_XC_HDMI32SCIP_19B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B4_CKGEN01_V004 (CKGEN01_V004 + 0x19B4)
	#define REG_19B4_CKGEN01_V004_REG_SW_EN_XC_ID02SCIP_19B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B8_CKGEN01_V004 (CKGEN01_V004 + 0x19B8)
	#define REG_19B8_CKGEN01_V004_REG_SW_EN_XC_ID12SCIP_19B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19BC_CKGEN01_V004 (CKGEN01_V004 + 0x19BC)
	#define REG_19BC_CKGEN01_V004_REG_SW_EN_XC_IP2_SRC2SCIP_19BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C0_CKGEN01_V004 (CKGEN01_V004 + 0x19C0)
	#define REG_19C0_CKGEN01_V004_REG_SW_EN_XC_MFDEC2SCIP_19C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C4_CKGEN01_V004 (CKGEN01_V004 + 0x19C4)
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD2SCTC_19C4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD2SCIP_19C4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD2SCBE_19C4 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD_EDGE2SCTC_19C4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_DV_SRC2SCIP_19C4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_SC2FPLL2SCIP_19C4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD_DELTA2SCBE_19C4 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_VERIMATRIX_SRAM2SCTC_19C4 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD_VERIMATRIX2SCTC_19C4 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_19C8_CKGEN01_V004 (CKGEN01_V004 + 0x19C8)
	#define REG_19C8_CKGEN01_V004_REG_SW_EN_XC_SLOW2SCIP_19C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19CC_CKGEN01_V004 (CKGEN01_V004 + 0x19CC)
	#define REG_19CC_CKGEN01_V004_REG_SW_EN_XC_SR_ALAI2SCSR_19CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D0_CKGEN01_V004 (CKGEN01_V004 + 0x19D0)
	#define REG_19D0_CKGEN01_V004_REG_SW_EN_XC_SR_SRAM_SHARE2SCSR_19D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D4_CKGEN01_V004 (CKGEN01_V004 + 0x19D4)
	#define REG_19D4_CKGEN01_V004_REG_SW_EN_XC_SRS2SCBE_19D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D8_CKGEN01_V004 (CKGEN01_V004 + 0x19D8)
	#define REG_19D8_CKGEN01_V004_REG_SW_EN_XC_TGEN_WIN2SCIP_19D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19DC_CKGEN01_V004 (CKGEN01_V004 + 0x19DC)
	#define REG_19DC_CKGEN01_V004_REG_SW_EN_XC_UCD_STAT2SCIP_19DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19E0_CKGEN01_V004 (CKGEN01_V004 + 0x19E0)
	#define REG_19E0_CKGEN01_V004_REG_SW_EN_XC_VD2SCIP_19E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19E4_CKGEN01_V004 (CKGEN01_V004 + 0x19E4)
	#define REG_19E4_CKGEN01_V004_REG_SW_EN_XC_VE2SCIP_19E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19E8_CKGEN01_V004 (CKGEN01_V004 + 0x19E8)
	#define REG_19E8_CKGEN01_V004_REG_SW_EN_XCPLL_SYN2XCPLL_DMACRO_19E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19EC_CKGEN01_V004 (CKGEN01_V004 + 0x19EC)
	#define REG_19EC_CKGEN01_V004_REG_SW_EN_XTAL_12M2SCNR_19EC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_19EC_CKGEN01_V004_REG_SW_EN_XTAL_12M2SCBE_19EC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_19EC_CKGEN01_V004_REG_SW_EN_XTAL_12M2SCTC_19EC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_19EC_CKGEN01_V004_REG_SW_EN_XTAL_12M2SCIP_19EC Fld(1,6,AC_MSKB0)//[6:6]
#define REG_19F0_CKGEN01_V004 (CKGEN01_V004 + 0x19F0)
	#define REG_19F0_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCIP_19F0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_19F0_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCNR_19F0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_19F0_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCBE_19F0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_19F0_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCSR_19F0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_19F0_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCTC_19F0 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_19F4_CKGEN01_V004 (CKGEN01_V004 + 0x19F4)
	#define REG_19F4_CKGEN01_V004_REG_SW_EN_XTAL_IP12SCIP_19F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19F8_CKGEN01_V004 (CKGEN01_V004 + 0x19F8)
	#define REG_19F8_CKGEN01_V004_REG_SW_EN_XC_SUB1_DC02SCIP_19F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19FC_CKGEN01_V004 (CKGEN01_V004 + 0x19FC)
	#define REG_19FC_CKGEN01_V004_REG_SW_EN_XVYCC_SRAM2SCMW_19FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A00_CKGEN01_V004 (CKGEN01_V004 + 0x1A00)
	#define REG_1A00_CKGEN01_V004_REG_SW_EN_SIDCLK_HD02SCIP_1A00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A04_CKGEN01_V004 (CKGEN01_V004 + 0x1A04)
	#define REG_1A04_CKGEN01_V004_REG_SW_EN_SIDCLK_HD12SCIP_1A04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A08_CKGEN01_V004 (CKGEN01_V004 + 0x1A08)
	#define REG_1A08_CKGEN01_V004_REG_SW_EN_SIDCLK_HD22SCIP_1A08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A0C_CKGEN01_V004 (CKGEN01_V004 + 0x1A0C)
	#define REG_1A0C_CKGEN01_V004_REG_SW_EN_SIDCLK_HD32SCIP_1A0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A10_CKGEN01_V004 (CKGEN01_V004 + 0x1A10)
	#define REG_1A10_CKGEN01_V004_REG_SW_EN_XC_DIP02SCIP_1A10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A14_CKGEN01_V004 (CKGEN01_V004 + 0x1A14)
	#define REG_1A14_CKGEN01_V004_REG_SW_EN_XC_DIP12SCIP_1A14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A18_CKGEN01_V004 (CKGEN01_V004 + 0x1A18)
	#define REG_1A18_CKGEN01_V004_REG_SW_EN_XC_DIP22SCIP_1A18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A1C_CKGEN01_V004 (CKGEN01_V004 + 0x1A1C)
	#define REG_1A1C_CKGEN01_V004_REG_SW_EN_XC_VEDAC2SCIP_1A1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A20_CKGEN01_V004 (CKGEN01_V004 + 0x1A20)
	#define REG_1A20_CKGEN01_V004_REG_SW_EN_XC_VEIN2SCIP_1A20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A20_CKGEN01_V004_REG_SW_EN_DV_HW5_C12SCIP_1A20 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1A20_CKGEN01_V004_REG_SW_EN_V1_ODCLK2SCIP_1A20 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1A20_CKGEN01_V004_REG_SW_EN_V2_ODCLK2SCIP_1A20 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_1A24_CKGEN01_V004 (CKGEN01_V004 + 0x1A24)
	#define REG_1A24_CKGEN01_V004_REG_SW_EN_DIP1_HVSP_SRAM2SCMW_1A24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A28_CKGEN01_V004 (CKGEN01_V004 + 0x1A28)
	#define REG_1A28_CKGEN01_V004_REG_SW_EN_DIP1_XVYCC_SRAM2SCMW_1A28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A2C_CKGEN01_V004 (CKGEN01_V004 + 0x1A2C)
	#define REG_1A2C_CKGEN01_V004_REG_SW_EN_CMBAI2VD_1A2C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A30_CKGEN01_V004 (CKGEN01_V004 + 0x1A30)
	#define REG_1A30_CKGEN01_V004_REG_SW_EN_CMBAO2VD_1A30 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A34_CKGEN01_V004 (CKGEN01_V004 + 0x1A34)
	#define REG_1A34_CKGEN01_V004_REG_SW_EN_CMBBI2VD_1A34 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A38_CKGEN01_V004 (CKGEN01_V004 + 0x1A38)
	#define REG_1A38_CKGEN01_V004_REG_SW_EN_CMBBO2VD_1A38 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A3C_CKGEN01_V004 (CKGEN01_V004 + 0x1A3C)
	#define REG_1A3C_CKGEN01_V004_REG_SW_EN_MCU_MAIL02VD_1A3C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A40_CKGEN01_V004 (CKGEN01_V004 + 0x1A40)
	#define REG_1A40_CKGEN01_V004_REG_SW_EN_MCU_MAIL12VD_1A40 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A44_CKGEN01_V004 (CKGEN01_V004 + 0x1A44)
	#define REG_1A44_CKGEN01_V004_REG_SW_EN_VD_32FSC2VD_1A44 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A48_CKGEN01_V004 (CKGEN01_V004 + 0x1A48)
	#define REG_1A48_CKGEN01_V004_REG_SW_EN_VD2MHEG5_ADC_1A48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A48_CKGEN01_V004_REG_SW_EN_VD2VD_1A48 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A4C_CKGEN01_V004 (CKGEN01_V004 + 0x1A4C)
	#define REG_1A4C_CKGEN01_V004_REG_SW_EN_VD2X2MHEG5_ADC_1A4C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A4C_CKGEN01_V004_REG_SW_EN_VD2X2VD_1A4C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A50_CKGEN01_V004 (CKGEN01_V004 + 0x1A50)
	#define REG_1A50_CKGEN01_V004_REG_SW_EN_XC_OD_META2SCTC_1A50 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A54_CKGEN01_V004 (CKGEN01_V004 + 0x1A54)
	#define REG_1A54_CKGEN01_V004_REG_SW_EN_XC_OD_DELTA_META2SCTC_1A54 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A58_CKGEN01_V004 (CKGEN01_V004 + 0x1A58)
	#define REG_1A58_CKGEN01_V004_REG_SW_EN_VENC2VENC_1A58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A58_CKGEN01_V004_REG_SW_EN_VENC2VENC_IP_1A58 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A5C_CKGEN01_V004 (CKGEN01_V004 + 0x1A5C)
	#define REG_1A5C_CKGEN01_V004_REG_SW_EN_XC_OD_OSD_META2SCTC_1A5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A60_CKGEN01_V004 (CKGEN01_V004 + 0x1A60)
	#define REG_1A60_CKGEN01_V004_REG_SW_EN_CLK_IP_1X_N2FLASH_DMACRO_1A60 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A64_CKGEN01_V004 (CKGEN01_V004 + 0x1A64)
	#define REG_1A64_CKGEN01_V004_REG_SW_EN_CLK_IP_1X2FLASH_DMACRO_1A64 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A68_CKGEN01_V004 (CKGEN01_V004 + 0x1A68)
	#define REG_1A68_CKGEN01_V004_REG_SW_EN_CLK_M_2X_N2FLASH_DMACRO_1A68 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A6C_CKGEN01_V004 (CKGEN01_V004 + 0x1A6C)
	#define REG_1A6C_CKGEN01_V004_REG_SW_EN_CLK_M_2X2FLASH_DMACRO_1A6C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A70_CKGEN01_V004 (CKGEN01_V004 + 0x1A70)
	#define REG_1A70_CKGEN01_V004_REG_SW_EN_CLK_M_4X_MID2FLASH_DMACRO_1A70 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A74_CKGEN01_V004 (CKGEN01_V004 + 0x1A74)
	#define REG_1A74_CKGEN01_V004_REG_SW_EN_CLK_M_4X2FLASH_DMACRO_1A74 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A78_CKGEN01_V004 (CKGEN01_V004 + 0x1A78)
	#define REG_1A78_CKGEN01_V004_REG_SW_EN_FB_MCLK2FLASH_DMACRO_1A78 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A7C_CKGEN01_V004 (CKGEN01_V004 + 0x1A7C)
	#define REG_1A7C_CKGEN01_V004_REG_SW_EN_MPLL2FLASH_DMACRO_1A7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A80_CKGEN01_V004 (CKGEN01_V004 + 0x1A80)
	#define REG_1A80_CKGEN01_V004_REG_SW_EN_OSP2FLASH_DMACRO_1A80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A84_CKGEN01_V004 (CKGEN01_V004 + 0x1A84)
	#define REG_1A84_CKGEN01_V004_REG_SW_EN_ECC2FCIE_1A84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A88_CKGEN01_V004 (CKGEN01_V004 + 0x1A88)
	#define REG_1A88_CKGEN01_V004_REG_SW_EN_FCIE_N2FCIE_1A88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A8C_CKGEN01_V004 (CKGEN01_V004 + 0x1A8C)
	#define REG_1A8C_CKGEN01_V004_REG_SW_EN_FCIE2FCIE_1A8C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A90_CKGEN01_V004 (CKGEN01_V004 + 0x1A90)
	#define REG_1A90_CKGEN01_V004_REG_SW_EN_PAD_SD2SD_SDR_MACRO_1A90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A90_CKGEN01_V004_REG_SW_EN_FCIE2SD_SDR_MACRO_1A90 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A94_CKGEN01_V004 (CKGEN01_V004 + 0x1A94)
	#define REG_1A94_CKGEN01_V004_REG_SW_EN_EMMC_DQS_SKEW2EMMC_DQS_SKEW_1A94 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A94_CKGEN01_V004_REG_SW_EN_EMMC_DQS_SKEW2SD_DQS_SKEW_1A94 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A98_CKGEN01_V004 (CKGEN01_V004 + 0x1A98)
	#define REG_1A98_CKGEN01_V004_REG_SW_EN_EMMC_DQS_DLY_N2SKEW_LATCH_1A98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A98_CKGEN01_V004_REG_SW_EN_EMMC_DQS_DLY_N2DQS_1A98 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A9C_CKGEN01_V004 (CKGEN01_V004 + 0x1A9C)
	#define REG_1A9C_CKGEN01_V004_REG_SW_EN_EMMC_DQS_DLY_2ND_N2SKEW_LATCH_CMD_1A9C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AAC_CKGEN01_V004 (CKGEN01_V004 + 0x1AAC)
	#define REG_1AAC_CKGEN01_V004_REG_SW_EN_GMAC_AHB2GMAC_1AAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB0_CKGEN01_V004 (CKGEN01_V004 + 0x1AB0)
	#define REG_1AB0_CKGEN01_V004_REG_SW_EN_GMAC_REF2GMAC_1AB0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB4_CKGEN01_V004 (CKGEN01_V004 + 0x1AB4)
	#define REG_1AB4_CKGEN01_V004_REG_SW_EN_GMAC_RX2GMAC_1AB4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB8_CKGEN01_V004 (CKGEN01_V004 + 0x1AB8)
	#define REG_1AB8_CKGEN01_V004_REG_SW_EN_GMAC_TX2GMAC_1AB8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ACC_CKGEN01_V004 (CKGEN01_V004 + 0x1ACC)
	#define REG_1ACC_CKGEN01_V004_REG_SW_EN_AU_UART0_SYNTH2MCU_CKCTRL_TOP_1ACC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1ACC_CKGEN01_V004_REG_SW_EN_AU_UART1_SYNTH2MCU_CKCTRL_TOP_1ACC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1AD0_CKGEN01_V004 (CKGEN01_V004 + 0x1AD0)
	#define REG_1AD0_CKGEN01_V004_REG_SW_EN_AU_UART02AU_UART0_1AD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1AD0_CKGEN01_V004_REG_SW_EN_AU_UART12AU_UART1_1AD0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1AD4_CKGEN01_V004 (CKGEN01_V004 + 0x1AD4)
	#define REG_1AD4_CKGEN01_V004_REG_SW_EN_FRC_FUART0_SYNTH2MCU_CKCTRL_TOP_1AD4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD8_CKGEN01_V004 (CKGEN01_V004 + 0x1AD8)
	#define REG_1AD8_CKGEN01_V004_REG_SW_EN_FRC_FUART02FRCMISC_1AD8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ADC_CKGEN01_V004 (CKGEN01_V004 + 0x1ADC)
	#define REG_1ADC_CKGEN01_V004_REG_SW_EN_FRC_MSPI0_DIV2MCU_CKCTRL_TOP_1ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE0_CKGEN01_V004 (CKGEN01_V004 + 0x1AE0)
	#define REG_1AE0_CKGEN01_V004_REG_SW_EN_FRC_MSPI02FRCMISC_1AE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE4_CKGEN01_V004 (CKGEN01_V004 + 0x1AE4)
	#define REG_1AE4_CKGEN01_V004_REG_SW_EN_FRC_UART0_SYNTH2MCU_CKCTRL_TOP_1AE4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE8_CKGEN01_V004 (CKGEN01_V004 + 0x1AE8)
	#define REG_1AE8_CKGEN01_V004_REG_SW_EN_FRC_UART02FRCMISC_1AE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AEC_CKGEN01_V004 (CKGEN01_V004 + 0x1AEC)
	#define REG_1AEC_CKGEN01_V004_REG_SW_EN_FRC_UART1_SYNTH2MCU_CKCTRL_TOP_1AEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF0_CKGEN01_V004 (CKGEN01_V004 + 0x1AF0)
	#define REG_1AF0_CKGEN01_V004_REG_SW_EN_FRC_UART12FRCMISC_1AF0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF4_CKGEN01_V004 (CKGEN01_V004 + 0x1AF4)
	#define REG_1AF4_CKGEN01_V004_REG_SW_EN_FUART0_SYNTH2MCU_CKCTRL_TOP_1AF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF8_CKGEN01_V004 (CKGEN01_V004 + 0x1AF8)
	#define REG_1AF8_CKGEN01_V004_REG_SW_EN_FUART02MCU_FUART0_1AF8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AFC_CKGEN01_V004 (CKGEN01_V004 + 0x1AFC)
	#define REG_1AFC_CKGEN01_V004_REG_SW_EN_UART0_SYNTH2MCU_CKCTRL_TOP_1AFC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B00_CKGEN01_V004 (CKGEN01_V004 + 0x1B00)
	#define REG_1B00_CKGEN01_V004_REG_SW_EN_UART02MCU_UART0_1B00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B04_CKGEN01_V004 (CKGEN01_V004 + 0x1B04)
	#define REG_1B04_CKGEN01_V004_REG_SW_EN_UART1_SYNTH2MCU_CKCTRL_TOP_1B04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B08_CKGEN01_V004 (CKGEN01_V004 + 0x1B08)
	#define REG_1B08_CKGEN01_V004_REG_SW_EN_UART12MCU_UART1_1B08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B0C_CKGEN01_V004 (CKGEN01_V004 + 0x1B0C)
	#define REG_1B0C_CKGEN01_V004_REG_SW_EN_UART2_SYNTH2MCU_CKCTRL_TOP_1B0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B10_CKGEN01_V004 (CKGEN01_V004 + 0x1B10)
	#define REG_1B10_CKGEN01_V004_REG_SW_EN_UART22MCU_UART2_1B10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B18_CKGEN01_V004 (CKGEN01_V004 + 0x1B18)
	#define REG_1B18_CKGEN01_V004_REG_SW_EN_TSP2VIV_TSP_BRIDGE_1B18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B24_CKGEN01_V004 (CKGEN01_V004 + 0x1B24)
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_DVBT2_INNER4X_SRD0P5X_1B24 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_DVBT2_INNER4X_SRD0P5X_1B24 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_DVBT2_INNER8X_1B24 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_DVBT2_INNER8X_1B24 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_DVBTM_SRAM_T12X_T28X_1B24 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_DVBTM_SRAM_T12X_T28X_1B24 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_DVBTM_SRAM_T12X_T28X_SRD1X_1B24 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_DVBTM_SRAM_T12X_T28X_SRD1X_1B24 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_DVBTM_SRAM_T14X_T28X_SRD1X_VIFDAC_1B24 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_DVBTM_SRAM_T14X_T28X_SRD1X_VIFDAC_1B24 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_DVBTM_SRAM_T14X_T28X_SRD1X_VIFSSC_1B24 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_DVBTM_SRAM_T14X_T28X_SRD1X_VIFSSC_1B24 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_01_1B24 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_01_1B24 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B24_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_02_1B24 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B24_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_02_1B24 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B28_CKGEN01_V004 (CKGEN01_V004 + 0x1B28)
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_03_1B28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_03_1B28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_04_1B28 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_04_1B28 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_06_07_1B28 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_06_07_1B28 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_104_105_106_1B28 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_104_105_106_1B28 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_107_108_1B28 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_107_108_1B28 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_112_TO_119_1B28 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_112_TO_119_1B28 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_120_121_122_123_1B28 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_120_121_122_123_1B28 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B28_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_124_125_1B28 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B28_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_124_125_1B28 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B2C_CKGEN01_V004 (CKGEN01_V004 + 0x1B2C)
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_126_127_1B2C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_126_127_1B2C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_149_150_151_152_1B2C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_149_150_151_152_1B2C Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_155_1B2C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_155_1B2C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_156_R_1B2C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_156_R_1B2C Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_156_W_1B2C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_156_W_1B2C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_157_R_1B2C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_157_R_1B2C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_157_W_1B2C Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_157_W_1B2C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_16_17_1B2C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B2C_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_16_17_1B2C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B30_CKGEN01_V004 (CKGEN01_V004 + 0x1B30)
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_24_25_1B30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_24_25_1B30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_29_30_31_32_33_1B30 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_29_30_31_32_33_1B30 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_34_35_36_38_1B30 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_34_35_36_38_1B30 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_37_39_40_41_1B30 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_37_39_40_41_1B30 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_42_43_44_1B30 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_42_43_44_1B30 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_45_46_1B30 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_45_46_1B30 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_47_48_49_1B30 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_47_48_49_1B30 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B30_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_50_51_52_53_1B30 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B30_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_50_51_52_53_1B30 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B34_CKGEN01_V004 (CKGEN01_V004 + 0x1B34)
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_54_1B34 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_54_1B34 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_55_1B34 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_55_1B34 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_68_0_69_0_1B34 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_68_0_69_0_1B34 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_68_1_1B34 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_68_1_1B34 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_68_2_69_2_70_2_71_2_1B34 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_68_2_69_2_70_2_71_2_1B34 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_68_3_69_3_70_3_71_3_1B34 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_68_3_69_3_70_3_71_3_1B34 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_69_1_1B34 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_69_1_1B34 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B34_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_70_0_70_0_1B34 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B34_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_70_0_71_0_1B34 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B38_CKGEN01_V004 (CKGEN01_V004 + 0x1B38)
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_70_1_1B38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_70_1_1B38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_71_1_1B38 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_71_1_1B38 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_87_88_1B38 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_87_88_1B38 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_89_90_1B38 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_89_90_1B38 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_94_95_1B38 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_94_95_1B38 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_96_97_1B38 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_96_97_1B38 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B38_CKGEN01_V004_REG_CKG_G_SRAM_SHARE_99_100_101_102_1B38 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B38_CKGEN01_V004_REG_CKG_I_SRAM_SHARE_99_100_101_102_1B38 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_1B3C_CKGEN01_V004 (CKGEN01_V004 + 0x1B3C)
	#define REG_1B3C_CKGEN01_V004_REG_SW_EN_MCU_BUS2AUDEC_1B3C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B40_CKGEN01_V004 (CKGEN01_V004 + 0x1B40)
	#define REG_1B40_CKGEN01_V004_REG_SW_EN_MCU_BUS2AUSND_1B40 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B44_CKGEN01_V004 (CKGEN01_V004 + 0x1B44)
	#define REG_1B44_CKGEN01_V004_REG_SW_EN_MCU_AU2AUDAP_1B44 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B48_CKGEN01_V004 (CKGEN01_V004 + 0x1B48)
	#define REG_1B48_CKGEN01_V004_REG_SW_EN_MCU_NONPM2AURV55SMI_1B48 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B4C_CKGEN01_V004 (CKGEN01_V004 + 0x1B4C)
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2FRCMISC_1B4C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2MAC_1B4C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2SCBE_1B4C Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_AU_MCU_BUS2AU_MCU_1B4C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2DEMOD0_1B4C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2MCU_M2MCU_1B4C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2MCU_NONPM_RIU_BRIDGE_1B4C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2MCU_CODEC_RIU_BRIDGE_1B4C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2MCUSYS_XIU_BRIDGE_1B4C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2SCMW_1B4C Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_BUS2BLK_1B4C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B4C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SEC_R2_1B4C Fld(1,14,AC_MSKB1)//[14:14]
#define REG_1B54_CKGEN01_V004 (CKGEN01_V004 + 0x1B54)
	#define REG_1B54_CKGEN01_V004_REG_SW_EN_MCU_CODEC2MCU_CODEC_RIU_BRIDGE_1B54 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B54_CKGEN01_V004_REG_SW_EN_MCU_CODEC2SECURE_TOP_CODEC_1B54 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1B5C_CKGEN01_V004 (CKGEN01_V004 + 0x1B5C)
	#define REG_1B5C_CKGEN01_V004_REG_SW_EN_MCU_DMD2DEMOD0_1B5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B64_CKGEN01_V004 (CKGEN01_V004 + 0x1B64)
	#define REG_1B64_CKGEN01_V004_REG_SW_EN_MCU_FRC2FRCMISC_1B64 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1B6C_CKGEN01_V004 (CKGEN01_V004 + 0x1B6C)
	#define REG_1B6C_CKGEN01_V004_REG_SW_EN_MCU_HDMI2MAC_1B6C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1B74_CKGEN01_V004 (CKGEN01_V004 + 0x1B74)
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2CHIP_REG_1B74 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2CMDQ_1B74 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2DEMOD0_1B74 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2DSCRMB_1B74 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2FCIE_1B74 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2PAD_TOP_1B74 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_BDMA_VDEC_1B74 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2GE_1B74 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2GMAC_1B74 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2GPD_1B74 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2GPU_PAR_GP_1B74 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2INTR_CTRL_TOP_WP_1B74 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MAC_1B74 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B74_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_BDMA_1B74 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B78_CKGEN01_V004 (CKGEN01_V004 + 0x1B78)
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_DEMURA_1B78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_FUART_1B78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MAILBOX0_1B78 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MAILBOX1_1B78 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MAILBOX2_1B78 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MAILBOX3_1B78 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MAILBOX4_1B78 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MAILBOX5_1B78 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MCUIF_1B78 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MIIC0_1B78 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MIIC1_1B78 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MIIC2_1B78 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MIIC3_1B78 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MSPI_ALL_1B78 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_FMLY_ROM_1B78 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1B78_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_NONPM_RIU_BRIDGE_1B78 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B7C_CKGEN01_V004 (CKGEN01_V004 + 0x1B7C)
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_UART0_1B7C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_UART1_1B7C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_UART2_1B7C Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_XD2MIU_1B7C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCUSYS_XIU_BRIDGE_1B7C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MHEG5_SMI_1B7C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2PEXTP_1B7C Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2PREARB2PM_RIU_TOP_1B7C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B7C_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SCIP_1B7C Fld(1,14,AC_MSKB1)//[14:14]
#define REG_1B80_CKGEN01_V004 (CKGEN01_V004 + 0x1B80)
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SCNR_1B80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SCBE_1B80 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SCSR_1B80 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SCTC_1B80 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SMART0_1B80 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SMART1_1B80 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2SSUSB_1B80 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2TSP_1B80 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2TSP_SMI_1B80 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2UFS_1B80 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1B80_CKGEN01_V004_REG_SW_EN_MCU_NONPM2USB20_1B80 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B84_CKGEN01_V004 (CKGEN01_V004 + 0x1B84)
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2VD_1B84 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2VENC_1B84 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2IP_WRAP_1B84 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2VIVA_SMI_1B84 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2VIVA_VBDMA_1B84 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2FRCCORE1_1B84 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2FRCCORE2_1B84 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2FRCCORE3_1B84 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1B84_CKGEN01_V004_REG_SW_EN_MCU_NONPM2FRCMISC_1B84 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_1BAC_CKGEN01_V004 (CKGEN01_V004 + 0x1BAC)
	#define REG_1BAC_CKGEN01_V004_REG_SW_EN_MCU_VD2MCU_M2MCU_1BAC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1BAC_CKGEN01_V004_REG_SW_EN_MCU_VD2MCU_MCUIF_1BAC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1BAC_CKGEN01_V004_REG_SW_EN_MCU_VD2VD_1BAC Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1BB4_CKGEN01_V004 (CKGEN01_V004 + 0x1BB4)
	#define REG_1BB4_CKGEN01_V004_REG_SW_EN_MCU_XC2SCIP_1BB4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1BB4_CKGEN01_V004_REG_SW_EN_MCU_XC2SCNR_1BB4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1BB4_CKGEN01_V004_REG_SW_EN_MCU_XC2SCBE_1BB4 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1BB4_CKGEN01_V004_REG_SW_EN_MCU_XC2SCSR_1BB4 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1BB4_CKGEN01_V004_REG_SW_EN_MCU_XC2SCTC_1BB4 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_1BB8_CKGEN01_V004 (CKGEN01_V004 + 0x1BB8)
	#define REG_1BB8_CKGEN01_V004_REG_SW_EN_IRS2IRS_1BB8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BBC_CKGEN01_V004 (CKGEN01_V004 + 0x1BBC)
	#define REG_1BBC_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_IRS_1BBC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC0_CKGEN01_V004 (CKGEN01_V004 + 0x1BC0)
	#define REG_1BC0_CKGEN01_V004_REG_SW_EN_MCU_NONPM2MCU_MIIC4_1BC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC4_CKGEN01_V004 (CKGEN01_V004 + 0x1BC4)
	#define REG_1BC4_CKGEN01_V004_REG_SW_EN_MIIC02MCU_MIIC0_1BC4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC8_CKGEN01_V004 (CKGEN01_V004 + 0x1BC8)
	#define REG_1BC8_CKGEN01_V004_REG_SW_EN_MIIC12MCU_MIIC1_1BC8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BCC_CKGEN01_V004 (CKGEN01_V004 + 0x1BCC)
	#define REG_1BCC_CKGEN01_V004_REG_SW_EN_MIIC22MCU_MIIC2_1BCC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD0_CKGEN01_V004 (CKGEN01_V004 + 0x1BD0)
	#define REG_1BD0_CKGEN01_V004_REG_SW_EN_MIIC32MCU_MIIC3_1BD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD4_CKGEN01_V004 (CKGEN01_V004 + 0x1BD4)
	#define REG_1BD4_CKGEN01_V004_REG_SW_EN_MIIC42MCU_MIIC4_1BD4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD8_CKGEN01_V004 (CKGEN01_V004 + 0x1BD8)
	#define REG_1BD8_CKGEN01_V004_REG_SW_EN_PCM2PIU_1BD8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BDC_CKGEN01_V004 (CKGEN01_V004 + 0x1BDC)
	#define REG_1BDC_CKGEN01_V004_REG_SW_EN_SMI2MCU_MIIC4_1BDC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE0_CKGEN01_V004 (CKGEN01_V004 + 0x1BE0)
	#define REG_1BE0_CKGEN01_V004_REG_SW_EN_XTAL_12M2MCU_MIIC4_1BE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE4_CKGEN01_V004 (CKGEN01_V004 + 0x1BE4)
	#define REG_1BE4_CKGEN01_V004_REG_SW_EN_MSPI12MCU_MSPI1_1BE4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE8_CKGEN01_V004 (CKGEN01_V004 + 0x1BE8)
	#define REG_1BE8_CKGEN01_V004_REG_SW_EN_MSPI22MCU_MSPI2_1BE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BEC_CKGEN01_V004 (CKGEN01_V004 + 0x1BEC)
	#define REG_1BEC_CKGEN01_V004_REG_SW_EN_MSPI32MCU_MSPI3_1BEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF0_CKGEN01_V004 (CKGEN01_V004 + 0x1BF0)
	#define REG_1BF0_CKGEN01_V004_REG_SW_EN_MSPI42MCU_MSPI4_1BF0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF4_CKGEN01_V004 (CKGEN01_V004 + 0x1BF4)
	#define REG_1BF4_CKGEN01_V004_REG_SW_EN_MSPI52MCU_MSPI5_1BF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF8_CKGEN01_V004 (CKGEN01_V004 + 0x1BF8)
	#define REG_1BF8_CKGEN01_V004_REG_SW_EN_MSPI62MCU_MSPI6_1BF8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BFC_CKGEN01_V004 (CKGEN01_V004 + 0x1BFC)
	#define REG_1BFC_CKGEN01_V004_REG_SW_EN_MSPI72MCU_MSPI7_1BFC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C00_CKGEN01_V004 (CKGEN01_V004 + 0x1C00)
	#define REG_1C00_CKGEN01_V004_REG_SW_EN_MSPI_CILINK_DIV2MCU_CKCTRL_TOP_1C00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C04_CKGEN01_V004 (CKGEN01_V004 + 0x1C04)
	#define REG_1C04_CKGEN01_V004_REG_SW_EN_MSPI_CILINK2MCU_MSPI_CILINK_1C04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C08_CKGEN01_V004 (CKGEN01_V004 + 0x1C08)
	#define REG_1C08_CKGEN01_V004_REG_SW_EN_MSPI0_DIV2MCU_CKCTRL_TOP_1C08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C0C_CKGEN01_V004 (CKGEN01_V004 + 0x1C0C)
	#define REG_1C0C_CKGEN01_V004_REG_SW_EN_MSPI1_DIV2MCU_CKCTRL_TOP_1C0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C10_CKGEN01_V004 (CKGEN01_V004 + 0x1C10)
	#define REG_1C10_CKGEN01_V004_REG_SW_EN_MSPI2_DIV2MCU_CKCTRL_TOP_1C10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C14_CKGEN01_V004 (CKGEN01_V004 + 0x1C14)
	#define REG_1C14_CKGEN01_V004_REG_SW_EN_MSPI02MCU_MSPI0_1C14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C18_CKGEN01_V004 (CKGEN01_V004 + 0x1C18)
	#define REG_1C18_CKGEN01_V004_REG_SW_EN_MSPI3_DIV2MCU_CKCTRL_TOP_1C18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C1C_CKGEN01_V004 (CKGEN01_V004 + 0x1C1C)
	#define REG_1C1C_CKGEN01_V004_REG_SW_EN_MSPI4_DIV2MCU_CKCTRL_TOP_1C1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C20_CKGEN01_V004 (CKGEN01_V004 + 0x1C20)
	#define REG_1C20_CKGEN01_V004_REG_SW_EN_MSPI5_DIV2MCU_CKCTRL_TOP_1C20 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C24_CKGEN01_V004 (CKGEN01_V004 + 0x1C24)
	#define REG_1C24_CKGEN01_V004_REG_SW_EN_MSPI6_DIV2MCU_CKCTRL_TOP_1C24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C28_CKGEN01_V004 (CKGEN01_V004 + 0x1C28)
	#define REG_1C28_CKGEN01_V004_REG_SW_EN_MSPI7_DIV2MCU_CKCTRL_TOP_1C28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C34_CKGEN01_V004 (CKGEN01_V004 + 0x1C34)
	#define REG_1C34_CKGEN01_V004_REG_SW_EN_SPI2MCU_SPI_1C34 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1C34_CKGEN01_V004_REG_SW_EN_SPI2MCUSYS_XIU_BRIDGE_1C34 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1C7C_CKGEN01_V004 (CKGEN01_V004 + 0x1C7C)
	#define REG_1C7C_CKGEN01_V004_REG_SW_EN_UFS_AHB2UFS_1C7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB0_CKGEN01_V004 (CKGEN01_V004 + 0x1CB0)
	#define REG_1CB0_CKGEN01_V004_REG_SW_EN_XTAL_12M2MCU_BDMA_VDEC_1CB0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC0_CKGEN01_V004 (CKGEN01_V004 + 0x1CC0)
	#define REG_1CC0_CKGEN01_V004_REG_SW_EN_SSUSB_FRMCNT2SSUSB_1CC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC4_CKGEN01_V004 (CKGEN01_V004 + 0x1CC4)
	#define REG_1CC4_CKGEN01_V004_REG_SW_EN_SSUSB_PCLK_1P2SSUSB_1CC4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC8_CKGEN01_V004 (CKGEN01_V004 + 0x1CC8)
	#define REG_1CC8_CKGEN01_V004_REG_SW_EN_SSUSB_PCLK2SSUSB_1CC8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CCC_CKGEN01_V004 (CKGEN01_V004 + 0x1CCC)
	#define REG_1CCC_CKGEN01_V004_REG_SW_EN_SSUSB_SCL2SSUSB_1CCC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD0_CKGEN01_V004 (CKGEN01_V004 + 0x1CD0)
	#define REG_1CD0_CKGEN01_V004_REG_SW_EN_SSUSB_SDIN2SSUSB_1CD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD4_CKGEN01_V004 (CKGEN01_V004 + 0x1CD4)
	#define REG_1CD4_CKGEN01_V004_REG_SW_EN_SSUSB_SYS2SSUSB_1CD4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD8_CKGEN01_V004 (CKGEN01_V004 + 0x1CD8)
	#define REG_1CD8_CKGEN01_V004_REG_SW_EN_SSUSB_USB20_PHY_CLK_1P2SSUSB_1CD8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CDC_CKGEN01_V004 (CKGEN01_V004 + 0x1CDC)
	#define REG_1CDC_CKGEN01_V004_REG_SW_EN_SSUSB_USB20_PHY_CLK_2P2SSUSB_1CDC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE0_CKGEN01_V004 (CKGEN01_V004 + 0x1CE0)
	#define REG_1CE0_CKGEN01_V004_REG_SW_EN_SSUSB_USB20_PHY_CLK2SSUSB_1CE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE4_CKGEN01_V004 (CKGEN01_V004 + 0x1CE4)
	#define REG_1CE4_CKGEN01_V004_REG_SW_EN_SSUSB_XHCI2SSUSB_1CE4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE8_CKGEN01_V004 (CKGEN01_V004 + 0x1CE8)
	#define REG_1CE8_CKGEN01_V004_REG_SW_EN_USBPHY240_MUX2USB20_SHBG_1CE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CEC_CKGEN01_V004 (CKGEN01_V004 + 0x1CEC)
	#define REG_1CEC_CKGEN01_V004_REG_SW_EN_USBPHY2402USB20_SHBG_1CEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF0_CKGEN01_V004 (CKGEN01_V004 + 0x1CF0)
	#define REG_1CF0_CKGEN01_V004_REG_SW_EN_USBPHY302USB20_SHBG_1CF0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF4_CKGEN01_V004 (CKGEN01_V004 + 0x1CF4)
	#define REG_1CF4_CKGEN01_V004_REG_SW_EN_SSUSB_MISC_48M2SSUSB_1CF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF8_CKGEN01_V004 (CKGEN01_V004 + 0x1CF8)
	#define REG_1CF8_CKGEN01_V004_REG_SW_EN_SEC_R22SEC_R2_1CF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1CF8_CKGEN01_V004_REG_SW_EN_SMI2SEC_R2_1CF8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1D14_CKGEN01_V004 (CKGEN01_V004 + 0x1D14)
	#define REG_1D14_CKGEN01_V004_REG_SW_EN_P0_CLK_TMDSPLL_TEST_DIG2MAC_1D14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D18_CKGEN01_V004 (CKGEN01_V004 + 0x1D18)
	#define REG_1D18_CKGEN01_V004_REG_SW_EN_P1_CLK_TMDSPLL_TEST_DIG2MAC_1D18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D1C_CKGEN01_V004 (CKGEN01_V004 + 0x1D1C)
	#define REG_1D1C_CKGEN01_V004_REG_SW_EN_P2_CLK_TMDSPLL_TEST_DIG2MAC_1D1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D20_CKGEN01_V004 (CKGEN01_V004 + 0x1D20)
	#define REG_1D20_CKGEN01_V004_REG_SW_EN_P3_CLK_TMDSPLL_TEST_DIG2MAC_1D20 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D24_CKGEN01_V004 (CKGEN01_V004 + 0x1D24)
	#define REG_1D24_CKGEN01_V004_REG_SW_EN_CLK_128FS_FB_S0_FF2MAC_1D24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D28_CKGEN01_V004 (CKGEN01_V004 + 0x1D28)
	#define REG_1D28_CKGEN01_V004_REG_SW_EN_CLK_128FS_FB_S1_FF2MAC_1D28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D80_CKGEN01_V004 (CKGEN01_V004 + 0x1D80)
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2MHEG5_MBIST_1D80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2TSP_MBIST_1D80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2DEMOD0_MBIST_1D80 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2DEMOD1_MBIST_1D80 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2VDEC_CORE0_MBIST_1D80 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2DRAMC0_MBIST_1D80 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2GPU_PAR_GP_MBIST_1D80 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_CLK_XTAL_242HDMIRX_MBIST_1D80 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1D80_CKGEN01_V004_REG_SW_EN_XTAL_24M2IP_WRAP_MBIST_1D80 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1D84_CKGEN01_V004 (CKGEN01_V004 + 0x1D84)
	#define REG_1D84_CKGEN01_V004_REG_SW_EN_XTAL_24M2MCUSYS_MBIST_1D84 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1D84_CKGEN01_V004_REG_SW_EN_XTAL_24M2MOD_MBIST_1D84 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1D84_CKGEN01_V004_REG_SW_EN_VIVA_XTAL_24M2VIVALDI9_MBIST_1D84 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1D84_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCIP_MBIST_1D84 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1D84_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCNR_MBIST_1D84 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1D88_CKGEN01_V004 (CKGEN01_V004 + 0x1D88)
	#define REG_1D88_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCBE_MBIST_1D88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1D88_CKGEN01_V004_REG_SW_EN_XTAL_24M2SCTC_MBIST_1D88 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1D88_CKGEN01_V004_REG_SW_EN_XTAL_24M2VDEC_CORE0_MERGE_MBIST_1D88 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1D88_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRC_MBIST_1D88 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1DBC_CKGEN01_V004 (CKGEN01_V004 + 0x1DBC)
	#define REG_1DBC_CKGEN01_V004_REG_VDEC_CORE0_MERGE_TEST_ENABLE_1DBC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DBC_CKGEN01_V004_REG_VDEC_CORE0_MERGE_TEST_DIV_SEL_1DBC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DBC_CKGEN01_V004_REG_VDEC_CORE0_MERGE_TEST_SRC_SEL_1DBC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DC0_CKGEN01_V004 (CKGEN01_V004 + 0x1DC0)
	#define REG_1DC0_CKGEN01_V004_REG_ADCPLL_TEST_ENABLE_1DC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DC0_CKGEN01_V004_REG_ADCPLL_TEST_DIV_SEL_1DC0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DC0_CKGEN01_V004_REG_ADCPLL_TEST_SRC_SEL_1DC0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DC8_CKGEN01_V004 (CKGEN01_V004 + 0x1DC8)
	#define REG_1DC8_CKGEN01_V004_REG_DEMOD0_TEST_ENABLE_1DC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DC8_CKGEN01_V004_REG_DEMOD0_TEST_DIV_SEL_1DC8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DC8_CKGEN01_V004_REG_DEMOD0_TEST_SRC_SEL_1DC8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DCC_CKGEN01_V004 (CKGEN01_V004 + 0x1DCC)
	#define REG_1DCC_CKGEN01_V004_REG_DEMOD1_TEST_ENABLE_1DCC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DCC_CKGEN01_V004_REG_DEMOD1_TEST_DIV_SEL_1DCC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DCC_CKGEN01_V004_REG_DEMOD1_TEST_SRC_SEL_1DCC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DD4_CKGEN01_V004 (CKGEN01_V004 + 0x1DD4)
	#define REG_1DD4_CKGEN01_V004_REG_VDEC_CORE0_TEST_ENABLE_1DD4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DD4_CKGEN01_V004_REG_VDEC_CORE0_TEST_DIV_SEL_1DD4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DD4_CKGEN01_V004_REG_VDEC_CORE0_TEST_SRC_SEL_1DD4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DE0_CKGEN01_V004 (CKGEN01_V004 + 0x1DE0)
	#define REG_1DE0_CKGEN01_V004_REG_DRAMC0_TEST_ENABLE_1DE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DE0_CKGEN01_V004_REG_DRAMC0_TEST_DIV_SEL_1DE0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DE0_CKGEN01_V004_REG_DRAMC0_TEST_SRC_SEL_1DE0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DE4_CKGEN01_V004 (CKGEN01_V004 + 0x1DE4)
	#define REG_1DE4_CKGEN01_V004_REG_DRAMC1_TEST_ENABLE_1DE4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DE4_CKGEN01_V004_REG_DRAMC1_TEST_DIV_SEL_1DE4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DE4_CKGEN01_V004_REG_DRAMC1_TEST_SRC_SEL_1DE4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DE8_CKGEN01_V004 (CKGEN01_V004 + 0x1DE8)
	#define REG_1DE8_CKGEN01_V004_REG_MCUSYS2MI_SWITCH_TEST_ENABLE_1DE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DE8_CKGEN01_V004_REG_MCUSYS2MI_SWITCH_TEST_DIV_SEL_1DE8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DE8_CKGEN01_V004_REG_MCUSYS2MI_SWITCH_TEST_SRC_SEL_1DE8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DEC_CKGEN01_V004 (CKGEN01_V004 + 0x1DEC)
	#define REG_1DEC_CKGEN01_V004_REG_TOP_TEST_ENABLE_1DEC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DEC_CKGEN01_V004_REG_TOP_TEST_DIV_SEL_1DEC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DEC_CKGEN01_V004_REG_TOP_TEST_SRC_SEL_1DEC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DF0_CKGEN01_V004 (CKGEN01_V004 + 0x1DF0)
	#define REG_1DF0_CKGEN01_V004_REG_MHEG5_TEST_ENABLE_1DF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DF0_CKGEN01_V004_REG_MHEG5_TEST_DIV_SEL_1DF0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DF0_CKGEN01_V004_REG_MHEG5_TEST_SRC_SEL_1DF0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DF4_CKGEN01_V004 (CKGEN01_V004 + 0x1DF4)
	#define REG_1DF4_CKGEN01_V004_REG_MCUSYS_XIU2PM_TX_TEST_ENABLE_1DF4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DF4_CKGEN01_V004_REG_MCUSYS_XIU2PM_TX_TEST_DIV_SEL_1DF4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DF4_CKGEN01_V004_REG_MCUSYS_XIU2PM_TX_TEST_SRC_SEL_1DF4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DF8_CKGEN01_V004 (CKGEN01_V004 + 0x1DF8)
	#define REG_1DF8_CKGEN01_V004_REG_GPU_PAR_GP_TEST_ENABLE_1DF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DF8_CKGEN01_V004_REG_GPU_PAR_GP_TEST_DIV_SEL_1DF8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DF8_CKGEN01_V004_REG_GPU_PAR_GP_TEST_SRC_SEL_1DF8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DFC_CKGEN01_V004 (CKGEN01_V004 + 0x1DFC)
	#define REG_1DFC_CKGEN01_V004_REG_MCUSYS_DIE_TMP_TEST_ENABLE_1DFC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1DFC_CKGEN01_V004_REG_MCUSYS_DIE_TMP_TEST_DIV_SEL_1DFC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1DFC_CKGEN01_V004_REG_MCUSYS_DIE_TMP_TEST_SRC_SEL_1DFC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E00_CKGEN01_V004 (CKGEN01_V004 + 0x1E00)
	#define REG_1E00_CKGEN01_V004_REG_HDMIRX_TEST_ENABLE_1E00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E00_CKGEN01_V004_REG_HDMIRX_TEST_DIV_SEL_1E00 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E00_CKGEN01_V004_REG_HDMIRX_TEST_SRC_SEL_1E00 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E04_CKGEN01_V004 (CKGEN01_V004 + 0x1E04)
	#define REG_1E04_CKGEN01_V004_REG_IP_WRAP_TEST_ENABLE_1E04 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E04_CKGEN01_V004_REG_IP_WRAP_TEST_DIV_SEL_1E04 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E04_CKGEN01_V004_REG_IP_WRAP_TEST_SRC_SEL_1E04 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E08_CKGEN01_V004 (CKGEN01_V004 + 0x1E08)
	#define REG_1E08_CKGEN01_V004_REG_MCUSYS_TEST_ENABLE_1E08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E08_CKGEN01_V004_REG_MCUSYS_TEST_DIV_SEL_1E08 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E08_CKGEN01_V004_REG_MCUSYS_TEST_SRC_SEL_1E08 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E0C_CKGEN01_V004 (CKGEN01_V004 + 0x1E0C)
	#define REG_1E0C_CKGEN01_V004_REG_MOD_TEST_ENABLE_1E0C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E0C_CKGEN01_V004_REG_MOD_TEST_DIV_SEL_1E0C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E0C_CKGEN01_V004_REG_MOD_TEST_SRC_SEL_1E0C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E10_CKGEN01_V004 (CKGEN01_V004 + 0x1E10)
	#define REG_1E10_CKGEN01_V004_REG_MOD_DOT_TEST_ENABLE_1E10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E10_CKGEN01_V004_REG_MOD_DOT_TEST_DIV_SEL_1E10 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E10_CKGEN01_V004_REG_MOD_DOT_TEST_SRC_SEL_1E10 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E18_CKGEN01_V004 (CKGEN01_V004 + 0x1E18)
	#define REG_1E18_CKGEN01_V004_REG_VIVALDI9_TEST_ENABLE_1E18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E18_CKGEN01_V004_REG_VIVALDI9_TEST_DIV_SEL_1E18 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E18_CKGEN01_V004_REG_VIVALDI9_TEST_SRC_SEL_1E18 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E24_CKGEN01_V004 (CKGEN01_V004 + 0x1E24)
	#define REG_1E24_CKGEN01_V004_REG_TSP_TEST_ENABLE_1E24 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E24_CKGEN01_V004_REG_TSP_TEST_DIV_SEL_1E24 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E24_CKGEN01_V004_REG_TSP_TEST_SRC_SEL_1E24 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E28_CKGEN01_V004 (CKGEN01_V004 + 0x1E28)
	#define REG_1E28_CKGEN01_V004_REG_FRC_MISC_TEST_ENABLE_1E28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E28_CKGEN01_V004_REG_FRC_MISC_TEST_DIV_SEL_1E28 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E28_CKGEN01_V004_REG_FRC_MISC_TEST_SRC_SEL_1E28 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E34_CKGEN01_V004 (CKGEN01_V004 + 0x1E34)
	#define REG_1E34_CKGEN01_V004_REG_FRC_CORE1_TEST_ENABLE_1E34 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E34_CKGEN01_V004_REG_FRC_CORE1_TEST_DIV_SEL_1E34 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E34_CKGEN01_V004_REG_FRC_CORE1_TEST_SRC_SEL_1E34 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E38_CKGEN01_V004 (CKGEN01_V004 + 0x1E38)
	#define REG_1E38_CKGEN01_V004_REG_FRC_CORE2_TEST_ENABLE_1E38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E38_CKGEN01_V004_REG_FRC_CORE2_TEST_DIV_SEL_1E38 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E38_CKGEN01_V004_REG_FRC_CORE2_TEST_SRC_SEL_1E38 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E3C_CKGEN01_V004 (CKGEN01_V004 + 0x1E3C)
	#define REG_1E3C_CKGEN01_V004_REG_FRC_CORE3_TEST_ENABLE_1E3C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E3C_CKGEN01_V004_REG_FRC_CORE3_TEST_DIV_SEL_1E3C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E3C_CKGEN01_V004_REG_FRC_CORE3_TEST_SRC_SEL_1E3C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E48_CKGEN01_V004 (CKGEN01_V004 + 0x1E48)
	#define REG_1E48_CKGEN01_V004_REG_SCFE_TEST_ENABLE_1E48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E48_CKGEN01_V004_REG_SCFE_TEST_DIV_SEL_1E48 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E48_CKGEN01_V004_REG_SCFE_TEST_SRC_SEL_1E48 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E54_CKGEN01_V004 (CKGEN01_V004 + 0x1E54)
	#define REG_1E54_CKGEN01_V004_REG_SCBE_TEST_ENABLE_1E54 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E54_CKGEN01_V004_REG_SCBE_TEST_DIV_SEL_1E54 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E54_CKGEN01_V004_REG_SCBE_TEST_SRC_SEL_1E54 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E60_CKGEN01_V004 (CKGEN01_V004 + 0x1E60)
	#define REG_1E60_CKGEN01_V004_REG_SCTC_TEST_ENABLE_1E60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E60_CKGEN01_V004_REG_SCTC_TEST_DIV_SEL_1E60 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E60_CKGEN01_V004_REG_SCTC_TEST_SRC_SEL_1E60 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E64_CKGEN01_V004 (CKGEN01_V004 + 0x1E64)
	#define REG_1E64_CKGEN01_V004_REG_HDMIRX_DPHY0_TEST_ENABLE_1E64 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E64_CKGEN01_V004_REG_HDMIRX_DPHY0_TEST_DIV_SEL_1E64 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E64_CKGEN01_V004_REG_HDMIRX_DPHY0_TEST_SRC_SEL_1E64 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E68_CKGEN01_V004 (CKGEN01_V004 + 0x1E68)
	#define REG_1E68_CKGEN01_V004_REG_HDMIRX_APHY0_TEST_ENABLE_1E68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E68_CKGEN01_V004_REG_HDMIRX_APHY0_TEST_DIV_SEL_1E68 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E68_CKGEN01_V004_REG_HDMIRX_APHY0_TEST_SRC_SEL_1E68 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E6C_CKGEN01_V004 (CKGEN01_V004 + 0x1E6C)
	#define REG_1E6C_CKGEN01_V004_REG_AUSDM_TEST_ENABLE_1E6C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E6C_CKGEN01_V004_REG_AUSDM_TEST_DIV_SEL_1E6C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E6C_CKGEN01_V004_REG_AUSDM_TEST_SRC_SEL_1E6C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E74_CKGEN01_V004 (CKGEN01_V004 + 0x1E74)
	#define REG_1E74_CKGEN01_V004_REG_AUPLL_TEST_ENABLE_1E74 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E74_CKGEN01_V004_REG_AUPLL_TEST_DIV_SEL_1E74 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E74_CKGEN01_V004_REG_AUPLL_TEST_SRC_SEL_1E74 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E78_CKGEN01_V004 (CKGEN01_V004 + 0x1E78)
	#define REG_1E78_CKGEN01_V004_REG_MCUSYS_DIE_TEST_ENABLE_1E78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E78_CKGEN01_V004_REG_MCUSYS_DIE_TEST_DIV_SEL_1E78 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E78_CKGEN01_V004_REG_MCUSYS_DIE_TEST_SRC_SEL_1E78 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E7C_CKGEN01_V004 (CKGEN01_V004 + 0x1E7C)
	#define REG_1E7C_CKGEN01_V004_REG_DMD_ANA_MISC_TEST_ENABLE_1E7C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E7C_CKGEN01_V004_REG_DMD_ANA_MISC_TEST_DIV_SEL_1E7C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E7C_CKGEN01_V004_REG_DMD_ANA_MISC_TEST_SRC_SEL_1E7C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E80_CKGEN01_V004 (CKGEN01_V004 + 0x1E80)
	#define REG_1E80_CKGEN01_V004_REG_ARMPLL_TEST_ENABLE_1E80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E80_CKGEN01_V004_REG_ARMPLL_TEST_DIV_SEL_1E80 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E80_CKGEN01_V004_REG_ARMPLL_TEST_SRC_SEL_1E80 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E90_CKGEN01_V004 (CKGEN01_V004 + 0x1E90)
	#define REG_1E90_CKGEN01_V004_REG_EARC_DMACRO_TEST_ENABLE_1E90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E90_CKGEN01_V004_REG_EARC_DMACRO_TEST_DIV_SEL_1E90 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1E90_CKGEN01_V004_REG_EARC_DMACRO_TEST_SRC_SEL_1E90 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EA0_CKGEN01_V004 (CKGEN01_V004 + 0x1EA0)
	#define REG_1EA0_CKGEN01_V004_REG_FLASH_DMACRO_TEST_ENABLE_1EA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EA0_CKGEN01_V004_REG_FLASH_DMACRO_TEST_DIV_SEL_1EA0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EA0_CKGEN01_V004_REG_FLASH_DMACRO_TEST_SRC_SEL_1EA0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EA4_CKGEN01_V004 (CKGEN01_V004 + 0x1EA4)
	#define REG_1EA4_CKGEN01_V004_REG_FLASH_32BIF_TEST_ENABLE_1EA4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EA4_CKGEN01_V004_REG_FLASH_32BIF_TEST_DIV_SEL_1EA4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EA4_CKGEN01_V004_REG_FLASH_32BIF_TEST_SRC_SEL_1EA4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EA8_CKGEN01_V004 (CKGEN01_V004 + 0x1EA8)
	#define REG_1EA8_CKGEN01_V004_REG_FLASH_8BIT_TEST_ENABLE_1EA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EA8_CKGEN01_V004_REG_FLASH_8BIT_TEST_DIV_SEL_1EA8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EA8_CKGEN01_V004_REG_FLASH_8BIT_TEST_SRC_SEL_1EA8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EAC_CKGEN01_V004 (CKGEN01_V004 + 0x1EAC)
	#define REG_1EAC_CKGEN01_V004_REG_SD_SDR_MACRO_TEST_ENABLE_1EAC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EAC_CKGEN01_V004_REG_SD_SDR_MACRO_TEST_DIV_SEL_1EAC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EAC_CKGEN01_V004_REG_SD_SDR_MACRO_TEST_SRC_SEL_1EAC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EB0_CKGEN01_V004 (CKGEN01_V004 + 0x1EB0)
	#define REG_1EB0_CKGEN01_V004_REG_VDECPLL_DMACRO_TEST_ENABLE_1EB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EB0_CKGEN01_V004_REG_VDECPLL_DMACRO_TEST_DIV_SEL_1EB0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EB0_CKGEN01_V004_REG_VDECPLL_DMACRO_TEST_SRC_SEL_1EB0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EB4_CKGEN01_V004 (CKGEN01_V004 + 0x1EB4)
	#define REG_1EB4_CKGEN01_V004_REG_SYS0PLL_DMACRO_TEST_ENABLE_1EB4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EB4_CKGEN01_V004_REG_SYS0PLL_DMACRO_TEST_DIV_SEL_1EB4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EB4_CKGEN01_V004_REG_SYS0PLL_DMACRO_TEST_SRC_SEL_1EB4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EB8_CKGEN01_V004 (CKGEN01_V004 + 0x1EB8)
	#define REG_1EB8_CKGEN01_V004_REG_SYS1PLL_DMACRO_TEST_ENABLE_1EB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EB8_CKGEN01_V004_REG_SYS1PLL_DMACRO_TEST_DIV_SEL_1EB8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EB8_CKGEN01_V004_REG_SYS1PLL_DMACRO_TEST_SRC_SEL_1EB8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EBC_CKGEN01_V004 (CKGEN01_V004 + 0x1EBC)
	#define REG_1EBC_CKGEN01_V004_REG_SYS2PLL_DMACRO_TEST_ENABLE_1EBC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EBC_CKGEN01_V004_REG_SYS2PLL_DMACRO_TEST_DIV_SEL_1EBC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EBC_CKGEN01_V004_REG_SYS2PLL_DMACRO_TEST_SRC_SEL_1EBC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EC0_CKGEN01_V004 (CKGEN01_V004 + 0x1EC0)
	#define REG_1EC0_CKGEN01_V004_REG_RV55FRCPLL_DMACRO_TEST_ENABLE_1EC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EC0_CKGEN01_V004_REG_RV55FRCPLL_DMACRO_TEST_DIV_SEL_1EC0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EC0_CKGEN01_V004_REG_RV55FRCPLL_DMACRO_TEST_SRC_SEL_1EC0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EC4_CKGEN01_V004 (CKGEN01_V004 + 0x1EC4)
	#define REG_1EC4_CKGEN01_V004_REG_XCPLL_DMACRO_TEST_ENABLE_1EC4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EC4_CKGEN01_V004_REG_XCPLL_DMACRO_TEST_DIV_SEL_1EC4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EC4_CKGEN01_V004_REG_XCPLL_DMACRO_TEST_SRC_SEL_1EC4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1ECC_CKGEN01_V004 (CKGEN01_V004 + 0x1ECC)
	#define REG_1ECC_CKGEN01_V004_REG_SYS3PLL_DMACRO_TEST_ENABLE_1ECC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1ECC_CKGEN01_V004_REG_SYS3PLL_DMACRO_TEST_DIV_SEL_1ECC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1ECC_CKGEN01_V004_REG_SYS3PLL_DMACRO_TEST_SRC_SEL_1ECC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1ED0_CKGEN01_V004 (CKGEN01_V004 + 0x1ED0)
	#define REG_1ED0_CKGEN01_V004_REG_GPUBRDGPLL_DMACRO_TEST_ENABLE_1ED0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1ED0_CKGEN01_V004_REG_GPUBRDGPLL_DMACRO_TEST_DIV_SEL_1ED0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1ED0_CKGEN01_V004_REG_GPUBRDGPLL_DMACRO_TEST_SRC_SEL_1ED0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1ED8_CKGEN01_V004 (CKGEN01_V004 + 0x1ED8)
	#define REG_1ED8_CKGEN01_V004_REG_AURV55_TEST_ENABLE_1ED8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1ED8_CKGEN01_V004_REG_AURV55_TEST_DIV_SEL_1ED8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1ED8_CKGEN01_V004_REG_AURV55_TEST_SRC_SEL_1ED8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EEC_CKGEN01_V004 (CKGEN01_V004 + 0x1EEC)
	#define REG_1EEC_CKGEN01_V004_REG_DISP_MFDEC_BRG_TEST_ENABLE_1EEC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EEC_CKGEN01_V004_REG_DISP_MFDEC_BRG_TEST_DIV_SEL_1EEC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EEC_CKGEN01_V004_REG_DISP_MFDEC_BRG_TEST_SRC_SEL_1EEC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EF0_CKGEN01_V004 (CKGEN01_V004 + 0x1EF0)
	#define REG_1EF0_CKGEN01_V004_REG_HDMIRX_APHY1_TEST_ENABLE_1EF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EF0_CKGEN01_V004_REG_HDMIRX_APHY1_TEST_DIV_SEL_1EF0 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EF0_CKGEN01_V004_REG_HDMIRX_APHY1_TEST_SRC_SEL_1EF0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EF4_CKGEN01_V004 (CKGEN01_V004 + 0x1EF4)
	#define REG_1EF4_CKGEN01_V004_REG_HDMIRX_APHY2_TEST_ENABLE_1EF4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EF4_CKGEN01_V004_REG_HDMIRX_APHY2_TEST_DIV_SEL_1EF4 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EF4_CKGEN01_V004_REG_HDMIRX_APHY2_TEST_SRC_SEL_1EF4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EF8_CKGEN01_V004 (CKGEN01_V004 + 0x1EF8)
	#define REG_1EF8_CKGEN01_V004_REG_HDMIRX_APHY3_TEST_ENABLE_1EF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EF8_CKGEN01_V004_REG_HDMIRX_APHY3_TEST_DIV_SEL_1EF8 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EF8_CKGEN01_V004_REG_HDMIRX_APHY3_TEST_SRC_SEL_1EF8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EFC_CKGEN01_V004 (CKGEN01_V004 + 0x1EFC)
	#define REG_1EFC_CKGEN01_V004_REG_HDMIRX_DPHY1_TEST_ENABLE_1EFC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EFC_CKGEN01_V004_REG_HDMIRX_DPHY1_TEST_DIV_SEL_1EFC Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1EFC_CKGEN01_V004_REG_HDMIRX_DPHY1_TEST_SRC_SEL_1EFC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F00_CKGEN01_V004 (CKGEN01_V004 + 0x1F00)
	#define REG_1F00_CKGEN01_V004_REG_HDMIRX_DPHY2_TEST_ENABLE_1F00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F00_CKGEN01_V004_REG_HDMIRX_DPHY2_TEST_DIV_SEL_1F00 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1F00_CKGEN01_V004_REG_HDMIRX_DPHY2_TEST_SRC_SEL_1F00 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F04_CKGEN01_V004 (CKGEN01_V004 + 0x1F04)
	#define REG_1F04_CKGEN01_V004_REG_HDMIRX_DPHY3_TEST_ENABLE_1F04 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F04_CKGEN01_V004_REG_HDMIRX_DPHY3_TEST_DIV_SEL_1F04 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1F04_CKGEN01_V004_REG_HDMIRX_DPHY3_TEST_SRC_SEL_1F04 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F08_CKGEN01_V004 (CKGEN01_V004 + 0x1F08)
	#define REG_1F08_CKGEN01_V004_REG_USB20_PHY_TEST_ENABLE_1F08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F08_CKGEN01_V004_REG_USB20_PHY_TEST_DIV_SEL_1F08 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1F08_CKGEN01_V004_REG_USB20_PHY_TEST_SRC_SEL_1F08 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F0C_CKGEN01_V004 (CKGEN01_V004 + 0x1F0C)
	#define REG_1F0C_CKGEN01_V004_REG_USB30_PHY_TEST_ENABLE_1F0C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F0C_CKGEN01_V004_REG_USB30_PHY_TEST_DIV_SEL_1F0C Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1F0C_CKGEN01_V004_REG_USB30_PHY_TEST_SRC_SEL_1F0C Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F10_CKGEN01_V004 (CKGEN01_V004 + 0x1F10)
	#define REG_1F10_CKGEN01_V004_REG_UPLL_TEST_ENABLE_1F10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F10_CKGEN01_V004_REG_UPLL_TEST_DIV_SEL_1F10 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_1F10_CKGEN01_V004_REG_UPLL_TEST_SRC_SEL_1F10 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F38_CKGEN01_V004 (CKGEN01_V004 + 0x1F38)
	#define REG_1F38_CKGEN01_V004_REG_GATE_INV_WLOCK_PASSWD_1F38 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F3C_CKGEN01_V004 (CKGEN01_V004 + 0x1F3C)
	#define REG_1F3C_CKGEN01_V004_REG_ALL_SW_EN_PASSWD_1F3C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F40_CKGEN01_V004 (CKGEN01_V004 + 0x1F40)
	#define REG_1F40_CKGEN01_V004_REG_XCPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F40_CKGEN01_V004_REG_VDECPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F40_CKGEN01_V004_REG_SYS0PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F40_CKGEN01_V004_REG_SYS1PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F40_CKGEN01_V004_REG_SYS2PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F40_CKGEN01_V004_REG_SYS3PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1F40_CKGEN01_V004_REG_ARMPLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F40_CKGEN01_V004_REG_AUPLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F40_CKGEN01_V004_REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1F40_CKGEN01_V004_REG_RV55FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F40_CKGEN01_V004_REG_DMD_ANA_MISC_ALL_SW_EN_OVERWRITE_1F40 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1F40_CKGEN01_V004_REG_ADCPLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F44_CKGEN01_V004 (CKGEN01_V004 + 0x1F44)
	#define REG_1F44_CKGEN01_V004_REG_AUSDM_ALL_SW_EN_OVERWRITE_1F44 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F44_CKGEN01_V004_REG_EARC_DMACRO_ALL_SW_EN_OVERWRITE_1F44 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F44_CKGEN01_V004_REG_DEMOD1_ALL_SW_EN_OVERWRITE_1F44 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F44_CKGEN01_V004_REG_FLASH_8BIT_ALL_SW_EN_OVERWRITE_1F44 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F44_CKGEN01_V004_REG_FLASH_32BIF_ALL_SW_EN_OVERWRITE_1F44 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F44_CKGEN01_V004_REG_FLASH_DMACRO_ALL_SW_EN_OVERWRITE_1F44 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F44_CKGEN01_V004_REG_HDMIRX_APHY0_ALL_SW_EN_OVERWRITE_1F44 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F44_CKGEN01_V004_REG_HDMIRX_DPHY0_ALL_SW_EN_OVERWRITE_1F44 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F44_CKGEN01_V004_REG_IP_WRAP_ALL_SW_EN_OVERWRITE_1F44 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1F44_CKGEN01_V004_REG_MCUSYS2MI_SWITCH_ALL_SW_EN_OVERWRITE_1F44 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F44_CKGEN01_V004_REG_MHEG5_ALL_SW_EN_OVERWRITE_1F44 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1F44_CKGEN01_V004_REG_SD_SDR_MACRO_ALL_SW_EN_OVERWRITE_1F44 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F44_CKGEN01_V004_REG_MOD_DOT_ALL_SW_EN_OVERWRITE_1F44 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F48_CKGEN01_V004 (CKGEN01_V004 + 0x1F48)
	#define REG_1F48_CKGEN01_V004_REG_VDEC_CORE0_ALL_SW_EN_OVERWRITE_1F48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F48_CKGEN01_V004_REG_DEMOD0_ALL_SW_EN_OVERWRITE_1F48 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F48_CKGEN01_V004_REG_HDMIRX_ALL_SW_EN_OVERWRITE_1F48 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F48_CKGEN01_V004_REG_TOP_ALL_SW_EN_OVERWRITE_1F48 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F48_CKGEN01_V004_REG_VDEC_CORE0_MERGE_ALL_SW_EN_OVERWRITE_1F48 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1F48_CKGEN01_V004_REG_MCUSYS_ALL_SW_EN_OVERWRITE_1F48 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F48_CKGEN01_V004_REG_MCUSYS_DIE_ALL_SW_EN_OVERWRITE_1F48 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F48_CKGEN01_V004_REG_MCUSYS_XIU2PM_TX_ALL_SW_EN_OVERWRITE_1F48 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F48_CKGEN01_V004_REG_DISP_MFDEC_BRG_ALL_SW_EN_OVERWRITE_1F48 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1F48_CKGEN01_V004_REG_MOD_ALL_SW_EN_OVERWRITE_1F48 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F4C_CKGEN01_V004 (CKGEN01_V004 + 0x1F4C)
	#define REG_1F4C_CKGEN01_V004_REG_FRC_MISC_ALL_SW_EN_OVERWRITE_1F4C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F4C_CKGEN01_V004_REG_FRC_CORE1_ALL_SW_EN_OVERWRITE_1F4C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F4C_CKGEN01_V004_REG_FRC_CORE2_ALL_SW_EN_OVERWRITE_1F4C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F4C_CKGEN01_V004_REG_FRC_CORE3_ALL_SW_EN_OVERWRITE_1F4C Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F4C_CKGEN01_V004_REG_DRAMC0_ALL_SW_EN_OVERWRITE_1F4C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F4C_CKGEN01_V004_REG_DRAMC1_ALL_SW_EN_OVERWRITE_1F4C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F4C_CKGEN01_V004_REG_TSP_ALL_SW_EN_OVERWRITE_1F4C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1F4C_CKGEN01_V004_REG_GPU_PAR_GP_ALL_SW_EN_OVERWRITE_1F4C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1F4C_CKGEN01_V004_REG_SCFE_ALL_SW_EN_OVERWRITE_1F4C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F4C_CKGEN01_V004_REG_SCBE_ALL_SW_EN_OVERWRITE_1F4C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F4C_CKGEN01_V004_REG_SCTC_ALL_SW_EN_OVERWRITE_1F4C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1F4C_CKGEN01_V004_REG_VIVALDI9_ALL_SW_EN_OVERWRITE_1F4C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F50_CKGEN01_V004 (CKGEN01_V004 + 0x1F50)
	#define REG_1F50_CKGEN01_V004_REG_HDMIRX_APHY1_ALL_SW_EN_OVERWRITE_1F50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F50_CKGEN01_V004_REG_HDMIRX_APHY2_ALL_SW_EN_OVERWRITE_1F50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F50_CKGEN01_V004_REG_HDMIRX_APHY3_ALL_SW_EN_OVERWRITE_1F50 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F50_CKGEN01_V004_REG_HDMIRX_DPHY1_ALL_SW_EN_OVERWRITE_1F50 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F50_CKGEN01_V004_REG_HDMIRX_DPHY2_ALL_SW_EN_OVERWRITE_1F50 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F50_CKGEN01_V004_REG_HDMIRX_DPHY3_ALL_SW_EN_OVERWRITE_1F50 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F50_CKGEN01_V004_REG_AURV55_ALL_SW_EN_OVERWRITE_1F50 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F50_CKGEN01_V004_REG_VIVALDI9_TSP_BRIDGE_ALL_SW_EN_OVERWRITE_1F50 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F50_CKGEN01_V004_REG_USB20_PHY_ALL_SW_EN_OVERWRITE_1F50 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1F50_CKGEN01_V004_REG_USB30_PHY_ALL_SW_EN_OVERWRITE_1F50 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1F50_CKGEN01_V004_REG_UPLL_ALL_SW_EN_OVERWRITE_1F50 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1F60_CKGEN01_V004 (CKGEN01_V004 + 0x1F60)
	#define REG_1F60_CKGEN01_V004_REG_XCPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F60_CKGEN01_V004_REG_VDECPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F60_CKGEN01_V004_REG_SYS0PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F60_CKGEN01_V004_REG_SYS1PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F60_CKGEN01_V004_REG_SYS2PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F60_CKGEN01_V004_REG_SYS3PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1F60_CKGEN01_V004_REG_ARMPLL_ALL_SW_EN_VALUE_1F60 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F60_CKGEN01_V004_REG_AUPLL_ALL_SW_EN_VALUE_1F60 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F60_CKGEN01_V004_REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1F60_CKGEN01_V004_REG_RV55FRCPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F60_CKGEN01_V004_REG_DMD_ANA_MISC_ALL_SW_EN_VALUE_1F60 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1F60_CKGEN01_V004_REG_ADCPLL_ALL_SW_EN_VALUE_1F60 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F64_CKGEN01_V004 (CKGEN01_V004 + 0x1F64)
	#define REG_1F64_CKGEN01_V004_REG_AUSDM_ALL_SW_EN_VALUE_1F64 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F64_CKGEN01_V004_REG_EARC_DMACRO_ALL_SW_EN_VALUE_1F64 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F64_CKGEN01_V004_REG_DEMOD1_ALL_SW_EN_VALUE_1F64 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F64_CKGEN01_V004_REG_FLASH_8BIT_ALL_SW_EN_VALUE_1F64 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F64_CKGEN01_V004_REG_FLASH_32BIF_ALL_SW_EN_VALUE_1F64 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F64_CKGEN01_V004_REG_FLASH_DMACRO_ALL_SW_EN_VALUE_1F64 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F64_CKGEN01_V004_REG_HDMIRX_APHY0_ALL_SW_EN_VALUE_1F64 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F64_CKGEN01_V004_REG_HDMIRX_DPHY0_ALL_SW_EN_VALUE_1F64 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F64_CKGEN01_V004_REG_IP_WRAP_ALL_SW_EN_VALUE_1F64 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1F64_CKGEN01_V004_REG_MCUSYS2MI_SWITCH_ALL_SW_EN_VALUE_1F64 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F64_CKGEN01_V004_REG_MHEG5_ALL_SW_EN_VALUE_1F64 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1F64_CKGEN01_V004_REG_SD_SDR_MACRO_ALL_SW_EN_VALUE_1F64 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F64_CKGEN01_V004_REG_MOD_DOT_ALL_SW_EN_VALUE_1F64 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F68_CKGEN01_V004 (CKGEN01_V004 + 0x1F68)
	#define REG_1F68_CKGEN01_V004_REG_VDEC_CORE0_ALL_SW_EN_VALUE_1F68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F68_CKGEN01_V004_REG_DEMOD0_ALL_SW_EN_VALUE_1F68 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F68_CKGEN01_V004_REG_HDMIRX_ALL_SW_EN_VALUE_1F68 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F68_CKGEN01_V004_REG_TOP_ALL_SW_EN_VALUE_1F68 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F68_CKGEN01_V004_REG_VDEC_CORE0_MERGE_ALL_SW_EN_VALUE_1F68 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1F68_CKGEN01_V004_REG_MCUSYS_ALL_SW_EN_VALUE_1F68 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F68_CKGEN01_V004_REG_MCUSYS_DIE_ALL_SW_EN_VALUE_1F68 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F68_CKGEN01_V004_REG_MCUSYS_XIU2PM_TX_ALL_SW_EN_VALUE_1F68 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F68_CKGEN01_V004_REG_DISP_MFDEC_BRG_ALL_SW_EN_VALUE_1F68 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1F68_CKGEN01_V004_REG_MOD_ALL_SW_EN_VALUE_1F68 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F6C_CKGEN01_V004 (CKGEN01_V004 + 0x1F6C)
	#define REG_1F6C_CKGEN01_V004_REG_FRC_MISC_ALL_SW_EN_VALUE_1F6C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F6C_CKGEN01_V004_REG_FRC_CORE1_ALL_SW_EN_VALUE_1F6C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F6C_CKGEN01_V004_REG_FRC_CORE2_ALL_SW_EN_VALUE_1F6C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F6C_CKGEN01_V004_REG_FRC_CORE3_ALL_SW_EN_VALUE_1F6C Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F6C_CKGEN01_V004_REG_DRAMC0_ALL_SW_EN_VALUE_1F6C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F6C_CKGEN01_V004_REG_DRAMC1_ALL_SW_EN_VALUE_1F6C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F6C_CKGEN01_V004_REG_TSP_ALL_SW_EN_VALUE_1F6C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1F6C_CKGEN01_V004_REG_GPU_PAR_GP_ALL_SW_EN_VALUE_1F6C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1F6C_CKGEN01_V004_REG_SCFE_ALL_SW_EN_VALUE_1F6C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F6C_CKGEN01_V004_REG_SCBE_ALL_SW_EN_VALUE_1F6C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F6C_CKGEN01_V004_REG_SCTC_ALL_SW_EN_VALUE_1F6C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1F6C_CKGEN01_V004_REG_VIVALDI9_ALL_SW_EN_VALUE_1F6C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F70_CKGEN01_V004 (CKGEN01_V004 + 0x1F70)
	#define REG_1F70_CKGEN01_V004_REG_HDMIRX_APHY1_ALL_SW_EN_VALUE_1F70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F70_CKGEN01_V004_REG_HDMIRX_APHY2_ALL_SW_EN_VALUE_1F70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F70_CKGEN01_V004_REG_HDMIRX_APHY3_ALL_SW_EN_VALUE_1F70 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F70_CKGEN01_V004_REG_HDMIRX_DPHY1_ALL_SW_EN_VALUE_1F70 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F70_CKGEN01_V004_REG_HDMIRX_DPHY2_ALL_SW_EN_VALUE_1F70 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F70_CKGEN01_V004_REG_HDMIRX_DPHY3_ALL_SW_EN_VALUE_1F70 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1F70_CKGEN01_V004_REG_AURV55_ALL_SW_EN_VALUE_1F70 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1F70_CKGEN01_V004_REG_VIVALDI9_TSP_BRIDGE_ALL_SW_EN_VALUE_1F70 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F70_CKGEN01_V004_REG_USB20_PHY_ALL_SW_EN_VALUE_1F70 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1F70_CKGEN01_V004_REG_USB30_PHY_ALL_SW_EN_VALUE_1F70 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_1F74_CKGEN01_V004 (CKGEN01_V004 + 0x1F74)
	#define REG_1F74_CKGEN01_V004_REG_UPLL_ALL_SW_EN_VALUE_1F74 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F88_CKGEN01_V004 (CKGEN01_V004 + 0x1F88)
	#define REG_1F88_CKGEN01_V004_REG_SW_EN_CALC2TEST_CLK_CALCULATE_1F88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F90_CKGEN01_V004 (CKGEN01_V004 + 0x1F90)
	#define REG_1F90_CKGEN01_V004_REG_SW_EN_RIU_DMD2RIU_DFT_DEMOD1_1F90 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F98_CKGEN01_V004 (CKGEN01_V004 + 0x1F98)
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY0_1F98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY1_1F98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY2_1F98 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY3_1F98 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY0_1F98 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY1_1F98 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY2_1F98 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1F98_CKGEN01_V004_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY3_1F98 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1FA8_CKGEN01_V004 (CKGEN01_V004 + 0x1FA8)
	#define REG_1FA8_CKGEN01_V004_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCIP_1FA8 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1FA8_CKGEN01_V004_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCBE_1FA8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FA8_CKGEN01_V004_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCTC_1FA8 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_1FC0_CKGEN01_V004 (CKGEN01_V004 + 0x1FC0)
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_ADC_1FC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD0_1FC0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD1_1FC0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_1FC0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE_1FC0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC0_1FC0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_MHEG5_1FC0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_HDMIRX_1FC0 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_IP_WRAP_1FC0 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1FC0_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_MCUSYS_1FC0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1FC4_CKGEN01_V004 (CKGEN01_V004 + 0x1FC4)
	#define REG_1FC4_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_MOD_1FC4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FC4_CKGEN01_V004_REG_SW_EN_VIVA_RIU2RIU_DFT_VIVALDI9_1FC4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1FC4_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_TSP_1FC4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1FC4_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_FRCFE_1FC4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FC4_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCIP_1FC4 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_1FC8_CKGEN01_V004 (CKGEN01_V004 + 0x1FC8)
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCBE_1FC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCTC_1FC8 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY0_1FC8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY1_1FC8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY2_1FC8 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY3_1FC8 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY0_1FC8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY1_1FC8 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY2_1FC8 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY3_1FC8 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1FC8_CKGEN01_V004_REG_SW_EN_RIU_NONPM2REG_1FC8 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1FCC_CKGEN01_V004 (CKGEN01_V004 + 0x1FCC)
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_DVBT2_INNER4X_SRD0P5X2DEMOD0_1FCC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_DVBT2_INNER8X2DEMOD0_1FCC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_DVBTM_SRAM_T12X_T28X2DEMOD0_1FCC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_DVBTM_SRAM_T12X_T28X_SRD1X2DEMOD0_1FCC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_DVBTM_SRAM_T14X_T28X_SRD1X_VIFDAC2DEMOD0_1FCC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_DVBTM_SRAM_T14X_T28X_SRD1X_VIFSSC2DEMOD0_1FCC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_012DEMOD0_1FCC Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_022DEMOD0_1FCC Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_032DEMOD0_1FCC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_042DEMOD0_1FCC Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_06_072DEMOD0_1FCC Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_104_105_1062DEMOD0_1FCC Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_107_1082DEMOD0_1FCC Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_112_TO_1192DEMOD0_1FCC Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_120_121_122_1232DEMOD0_1FCC Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1FCC_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_124_1252DEMOD0_1FCC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1FD0_CKGEN01_V004 (CKGEN01_V004 + 0x1FD0)
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_126_1272DEMOD0_1FD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_149_150_151_1522DEMOD0_1FD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_1552DEMOD0_1FD0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_156_R2DEMOD0_1FD0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_156_W2DEMOD0_1FD0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_157_R2DEMOD0_1FD0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_157_W2DEMOD0_1FD0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_16_172DEMOD0_1FD0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_24_252DEMOD0_1FD0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_29_30_31_32_332DEMOD0_1FD0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_34_35_36_382DEMOD0_1FD0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_37_39_40_412DEMOD0_1FD0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_42_43_442DEMOD0_1FD0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_45_462DEMOD0_1FD0 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_47_48_492DEMOD0_1FD0 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_1FD0_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_50_51_52_532DEMOD0_1FD0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1FD4_CKGEN01_V004 (CKGEN01_V004 + 0x1FD4)
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_542DEMOD0_1FD4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_552DEMOD0_1FD4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_68_0_69_02DEMOD0_1FD4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_68_12DEMOD0_1FD4 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_68_2_69_2_70_2_71_22DEMOD0_1FD4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_68_3_69_3_70_3_71_32DEMOD0_1FD4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_69_12DEMOD0_1FD4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_70_0_71_02DEMOD0_1FD4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_70_12DEMOD0_1FD4 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_71_12DEMOD0_1FD4 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_87_882DEMOD0_1FD4 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_89_902DEMOD0_1FD4 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_94_952DEMOD0_1FD4 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_96_972DEMOD0_1FD4 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1FD4_CKGEN01_V004_REG_SW_EN_SRAM_SHARE_99_100_101_1022DEMOD0_1FD4 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_1FDC_CKGEN01_V004 (CKGEN01_V004 + 0x1FDC)
	#define REG_1FDC_CKGEN01_V004_REG_SW_EN_SMI2ZDEC_1FDC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1FE0_CKGEN01_V004 (CKGEN01_V004 + 0x1FE0)
	#define REG_1FE0_CKGEN01_V004_REG_SW_EN_SMI2MCU_BDMA_VDEC_1FE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1FE8_CKGEN01_V004 (CKGEN01_V004 + 0x1FE8)
	#define REG_1FE8_CKGEN01_V004_REG_CKG_OCC_SRC_FOR_TEST_DIV_1FE8 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1FEC_CKGEN01_V004 (CKGEN01_V004 + 0x1FEC)
	#define REG_1FEC_CKGEN01_V004_REG_SW_EN_OCC_SRC_FOR_TEST_DIV2TEST_CTRL_WP_1FEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1FF0_CKGEN01_V004 (CKGEN01_V004 + 0x1FF0)
	#define REG_1FF0_CKGEN01_V004_REG_CKGEN01_V004_DUMMY0_1FF0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF4_CKGEN01_V004 (CKGEN01_V004 + 0x1FF4)
	#define REG_1FF4_CKGEN01_V004_REG_CKGEN01_V004_DUMMY1_1FF4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF8_CKGEN01_V004 (CKGEN01_V004 + 0x1FF8)
	#define REG_1FF8_CKGEN01_V004_REG_CKGEN01_V004_DUMMY2_1FF8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FFC_CKGEN01_V004 (CKGEN01_V004 + 0x1FFC)
	#define REG_1FFC_CKGEN01_V004_REG_CKGEN01_V004_DUMMY3_1FFC Fld(16,0,AC_FULLW10)//[15:0]
