/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_REG00_H
#define _DT_BINDINGS_CLK_MT5896_REG00_H

#define ckgen00(Offset) Offset

#define reg_ckg_calc ckgen00(0x0000)
#define reg_ckg_calc_s 0
#define reg_ckg_calc_e 4
#define reg_ckg_coreclk ckgen00(0x0008)
#define reg_ckg_coreclk_s 0
#define reg_ckg_coreclk_e 2
#define reg_ckg_coreclk_mid ckgen00(0x0010)
#define reg_ckg_coreclk_mid_s 0
#define reg_ckg_coreclk_mid_e 2
#define reg_ckg_sclk ckgen00(0x0018)
#define reg_ckg_sclk_s 0
#define reg_ckg_sclk_e 2
#define reg_ckg_sclk_mid ckgen00(0x0020)
#define reg_ckg_sclk_mid_s 0
#define reg_ckg_sclk_mid_e 2
#define reg_ckg_biu ckgen00(0x0028)
#define reg_ckg_biu_s 0
#define reg_ckg_biu_e 2
#define reg_ckg_calc_mcusys ckgen00(0x0030)
#define reg_ckg_calc_mcusys_s 0
#define reg_ckg_calc_mcusys_e 4
#define reg_ckg_emi0_mcusys ckgen00(0x0038)
#define reg_ckg_emi0_mcusys_s 0
#define reg_ckg_emi0_mcusys_e 2
#define reg_ckg_emi1_mcusys ckgen00(0x0040)
#define reg_ckg_emi1_mcusys_s 0
#define reg_ckg_emi1_mcusys_e 2
#define reg_ckg_emi2_mcusys ckgen00(0x0048)
#define reg_ckg_emi2_mcusys_s 0
#define reg_ckg_emi2_mcusys_e 2
#define reg_ckg_mips_syn_armpll ckgen00(0x0050)
#define reg_ckg_mips_syn_armpll_s 0
#define reg_ckg_mips_syn_armpll_e 1
#define reg_ckg_mips_syn_arm2pll ckgen00(0x0054)
#define reg_ckg_mips_syn_arm2pll_s 0
#define reg_ckg_mips_syn_arm2pll_e 1
#define reg_ckg_xtal_mpll ckgen00(0x0058)
#define reg_ckg_xtal_mpll_s 0
#define reg_ckg_xtal_mpll_e 2
#define reg_ckg_ptp ckgen00(0x0060)
#define reg_ckg_ptp_s 0
#define reg_ckg_ptp_e 3
#define reg_ckg_lzma_mcusys ckgen00(0x0068)
#define reg_ckg_lzma_mcusys_s 0
#define reg_ckg_lzma_mcusys_e 2
#define reg_ckg_mpu_mcusys ckgen00(0x0070)
#define reg_ckg_mpu_mcusys_s 0
#define reg_ckg_mpu_mcusys_e 2
#define reg_ckg_bridge_gpu_nodie ckgen00(0x00C0)
#define reg_ckg_bridge_gpu_nodie_s 0
#define reg_ckg_bridge_gpu_nodie_e 1
#define reg_ckg_gpu_gpu_die ckgen00(0x00C8)
#define reg_ckg_gpu_gpu_die_s 0
#define reg_ckg_gpu_gpu_die_e 1
#define reg_ckg_shader_core ckgen00(0x00D0)
#define reg_ckg_shader_core_s 0
#define reg_ckg_shader_core_e 1
#define reg_ckg_mips_syn_armpll_gpu ckgen00(0x00D8)
#define reg_ckg_mips_syn_armpll_gpu_s 0
#define reg_ckg_mips_syn_armpll_gpu_e 1
#define reg_ckg_aia_bus ckgen00(0x00F0)
#define reg_ckg_aia_bus_s 0
#define reg_ckg_aia_bus_e 4
#define reg_ckg_aia_bus_aia ckgen00(0x00F0)
#define reg_ckg_aia_bus_aia_s 8
#define reg_ckg_aia_bus_aia_e 9
#define reg_ckg_mips_syn_armpll_apu ckgen00(0x00F4)
#define reg_ckg_mips_syn_armpll_apu_s 0
#define reg_ckg_mips_syn_armpll_apu_e 1
#define reg_ckg_mdla ckgen00(0x0100)
#define reg_ckg_mdla_s 0
#define reg_ckg_mdla_e 4
#define reg_ckg_mdla_aia ckgen00(0x0100)
#define reg_ckg_mdla_aia_s 8
#define reg_ckg_mdla_aia_e 9
#define reg_ckg_xtal_24m_aia ckgen00(0x0108)
#define reg_ckg_xtal_24m_aia_s 0
#define reg_ckg_xtal_24m_aia_e 1
#define reg_ckg_emi2_aia ckgen00(0x0110)
#define reg_ckg_emi2_aia_s 0
#define reg_ckg_emi2_aia_e 1
#define reg_ckg_dramc_ch0 ckgen00(0x0120)
#define reg_ckg_dramc_ch0_s 0
#define reg_ckg_dramc_ch0_e 3
#define reg_ckg_dramc_ch2 ckgen00(0x0128)
#define reg_ckg_dramc_ch2_s 0
#define reg_ckg_dramc_ch2_e 3
#define reg_ckg_dramc_ch4 ckgen00(0x0130)
#define reg_ckg_dramc_ch4_s 0
#define reg_ckg_dramc_ch4_e 3
#define reg_ckg_dramc0_cgclk_fast_cha ckgen00(0x0138)
#define reg_ckg_dramc0_cgclk_fast_cha_s 0
#define reg_ckg_dramc0_cgclk_fast_cha_e 1
#define reg_ckg_xtal_24m_dramc0 ckgen00(0x0140)
#define reg_ckg_xtal_24m_dramc0_s 0
#define reg_ckg_xtal_24m_dramc0_e 1
#define reg_ckg_dramc1_cgclk_fast_cha ckgen00(0x0148)
#define reg_ckg_dramc1_cgclk_fast_cha_s 0
#define reg_ckg_dramc1_cgclk_fast_cha_e 1
#define reg_ckg_xtal_24m_dramc1 ckgen00(0x0150)
#define reg_ckg_xtal_24m_dramc1_s 0
#define reg_ckg_xtal_24m_dramc1_e 1
#define reg_ckg_dramc2_cgclk_fast_cha ckgen00(0x0158)
#define reg_ckg_dramc2_cgclk_fast_cha_s 0
#define reg_ckg_dramc2_cgclk_fast_cha_e 1
#define reg_ckg_xtal_24m_dramc2 ckgen00(0x0160)
#define reg_ckg_xtal_24m_dramc2_s 0
#define reg_ckg_xtal_24m_dramc2_e 1
#define reg_ckg_emi0_ip_wrap ckgen00(0x0168)
#define reg_ckg_emi0_ip_wrap_s 0
#define reg_ckg_emi0_ip_wrap_e 1
#define reg_ckg_emi1_ip_wrap ckgen00(0x0170)
#define reg_ckg_emi1_ip_wrap_s 0
#define reg_ckg_emi1_ip_wrap_e 1
#define reg_ckg_emi2_ip_wrap ckgen00(0x0178)
#define reg_ckg_emi2_ip_wrap_s 0
#define reg_ckg_emi2_ip_wrap_e 1
#define reg_ckg_ip_wrap ckgen00(0x0180)
#define reg_ckg_ip_wrap_s 0
#define reg_ckg_ip_wrap_e 1
#define reg_ckg_emi0_deb_ip_wrap ckgen00(0x0188)
#define reg_ckg_emi0_deb_ip_wrap_s 0
#define reg_ckg_emi0_deb_ip_wrap_e 1
#define reg_ckg_emi1_deb_ip_wrap ckgen00(0x0190)
#define reg_ckg_emi1_deb_ip_wrap_s 0
#define reg_ckg_emi1_deb_ip_wrap_e 1
#define reg_ckg_emi2_deb_ip_wrap ckgen00(0x0198)
#define reg_ckg_emi2_deb_ip_wrap_s 0
#define reg_ckg_emi2_deb_ip_wrap_e 1
#define reg_ckg_xtal_12m_ip_wrap ckgen00(0x01A0)
#define reg_ckg_xtal_12m_ip_wrap_s 0
#define reg_ckg_xtal_12m_ip_wrap_e 1
#define reg_ckg_xtal_24m_ip_wrap ckgen00(0x01A8)
#define reg_ckg_xtal_24m_ip_wrap_s 0
#define reg_ckg_xtal_24m_ip_wrap_e 1
#define reg_ckg_smi ckgen00(0x01D8)
#define reg_ckg_smi_s 0
#define reg_ckg_smi_e 2
#define reg_ckg_smi_demod0 ckgen00(0x01D8)
#define reg_ckg_smi_demod0_s 8
#define reg_ckg_smi_demod0_e 9
#define reg_ckg_smi_frciopmrv55 ckgen00(0x01D8)
#define reg_ckg_smi_frciopmrv55_s 10
#define reg_ckg_smi_frciopmrv55_e 11
#define reg_ckg_smi_frcmehalo ckgen00(0x01D8)
#define reg_ckg_smi_frcmehalo_s 14
#define reg_ckg_smi_frcmehalo_e 15
#define reg_ckg_smi_scace ckgen00(0x01DC)
#define reg_ckg_smi_scace_s 0
#define reg_ckg_smi_scace_e 1
#define reg_ckg_smi_scip ckgen00(0x01DC)
#define reg_ckg_smi_scip_s 2
#define reg_ckg_smi_scip_e 3
#define reg_ckg_smi_scmw ckgen00(0x01DC)
#define reg_ckg_smi_scmw_s 4
#define reg_ckg_smi_scmw_e 5
#define reg_ckg_smi_scnr ckgen00(0x01DC)
#define reg_ckg_smi_scnr_s 6
#define reg_ckg_smi_scnr_e 7
#define reg_ckg_smi_scpq ckgen00(0x01DC)
#define reg_ckg_smi_scpq_s 8
#define reg_ckg_smi_scpq_e 9
#define reg_ckg_smi_scscl ckgen00(0x01DC)
#define reg_ckg_smi_scscl_s 10
#define reg_ckg_smi_scscl_e 11
#define reg_ckg_smi_scsr ckgen00(0x01DC)
#define reg_ckg_smi_scsr_s 12
#define reg_ckg_smi_scsr_e 13
#define reg_ckg_smi_sctcon ckgen00(0x01DC)
#define reg_ckg_smi_sctcon_s 14
#define reg_ckg_smi_sctcon_e 15
#define reg_ckg_smi_scdv ckgen00(0x01E0)
#define reg_ckg_smi_scdv_s 0
#define reg_ckg_smi_scdv_e 1
#define reg_ckg_smi_vdec_soc ckgen00(0x01E0)
#define reg_ckg_smi_vdec_soc_s 2
#define reg_ckg_smi_vdec_soc_e 3
#define reg_ckg_smi_vdec_core0 ckgen00(0x01E0)
#define reg_ckg_smi_vdec_core0_s 6
#define reg_ckg_smi_vdec_core0_e 7
#define reg_ckg_smi_vdec_core1 ckgen00(0x01E0)
#define reg_ckg_smi_vdec_core1_s 8
#define reg_ckg_smi_vdec_core1_e 9
#define reg_ckg_smi_vdec_core2 ckgen00(0x01E0)
#define reg_ckg_smi_vdec_core2_s 10
#define reg_ckg_smi_vdec_core2_e 11
#define reg_ckg_smi_rv55audio ckgen00(0x01E0)
#define reg_ckg_smi_rv55audio_s 14
#define reg_ckg_smi_rv55audio_e 15
#define reg_ckg_smi_audio_r2 ckgen00(0x01E4)
#define reg_ckg_smi_audio_r2_s 0
#define reg_ckg_smi_audio_r2_e 1
#define reg_ckg_smi_aia ckgen00(0x01E4)
#define reg_ckg_smi_aia_s 6
#define reg_ckg_smi_aia_e 7
#define reg_ckg_viva_smi ckgen00(0x01E8)
#define reg_ckg_viva_smi_s 0
#define reg_ckg_viva_smi_e 1
#define reg_ckg_smi_mheg5 ckgen00(0x01E8)
#define reg_ckg_smi_mheg5_s 4
#define reg_ckg_smi_mheg5_e 5
#define reg_ckg_smi_hdmirx ckgen00(0x01E8)
#define reg_ckg_smi_hdmirx_s 6
#define reg_ckg_smi_hdmirx_e 7
#define reg_ckg_smi_tsp ckgen00(0x01E8)
#define reg_ckg_smi_tsp_s 8
#define reg_ckg_smi_tsp_e 9
#define reg_ckg_smi_rv55frc ckgen00(0x01E8)
#define reg_ckg_smi_rv55frc_s 10
#define reg_ckg_smi_rv55frc_e 11
#define reg_ckg_smi_rv55pqu ckgen00(0x01E8)
#define reg_ckg_smi_rv55pqu_s 12
#define reg_ckg_smi_rv55pqu_e 13
#define reg_ckg_frc_imi ckgen00(0x0260)
#define reg_ckg_frc_imi_s 0
#define reg_ckg_frc_imi_e 3
#define reg_ckg_frc_imi_frciopmrv55 ckgen00(0x0260)
#define reg_ckg_frc_imi_frciopmrv55_s 8
#define reg_ckg_frc_imi_frciopmrv55_e 9
#define reg_ckg_frc_imi_rv55frc ckgen00(0x0260)
#define reg_ckg_frc_imi_rv55frc_s 10
#define reg_ckg_frc_imi_rv55frc_e 11
#define reg_ckg_frc_imi_rv55pqu ckgen00(0x0260)
#define reg_ckg_frc_imi_rv55pqu_s 12
#define reg_ckg_frc_imi_rv55pqu_e 13
#define reg_ckg_imi ckgen00(0x0268)
#define reg_ckg_imi_s 0
#define reg_ckg_imi_e 3
#define reg_ckg_imi_tsp ckgen00(0x0268)
#define reg_ckg_imi_tsp_s 8
#define reg_ckg_imi_tsp_e 9
#define reg_ckg_lzma ckgen00(0x0270)
#define reg_ckg_lzma_s 0
#define reg_ckg_lzma_e 3
#define reg_ckg_xtal_12m ckgen00(0x0278)
#define reg_ckg_xtal_12m_s 0
#define reg_ckg_xtal_12m_e 1
#define reg_ckg_xtal_12m_mheg5 ckgen00(0x0278)
#define reg_ckg_xtal_12m_mheg5_s 8
#define reg_ckg_xtal_12m_mheg5_e 9
#define reg_ckg_xtal_12m_gpu_die ckgen00(0x0278)
#define reg_ckg_xtal_12m_gpu_die_s 10
#define reg_ckg_xtal_12m_gpu_die_e 11
#define reg_ckg_xtal_24m ckgen00(0x0280)
#define reg_ckg_xtal_24m_s 0
#define reg_ckg_xtal_24m_e 1
#define reg_ckg_xtal_24m_mheg5 ckgen00(0x0280)
#define reg_ckg_xtal_24m_mheg5_s 8
#define reg_ckg_xtal_24m_mheg5_e 9
#define reg_ckg_xtal_24m_gpu_die ckgen00(0x0280)
#define reg_ckg_xtal_24m_gpu_die_s 10
#define reg_ckg_xtal_24m_gpu_die_e 11
#define reg_ckg_xtal_24m_gpu_nodie ckgen00(0x0280)
#define reg_ckg_xtal_24m_gpu_nodie_s 12
#define reg_ckg_xtal_24m_gpu_nodie_e 13
#define reg_ckg_xtal_24m_gpu_shader ckgen00(0x0280)
#define reg_ckg_xtal_24m_gpu_shader_s 14
#define reg_ckg_xtal_24m_gpu_shader_e 15
#define reg_ckg_xtal_24m_tsp ckgen00(0x0284)
#define reg_ckg_xtal_24m_tsp_s 0
#define reg_ckg_xtal_24m_tsp_e 1
#define reg_ckg_demod_adc ckgen00(0x02B8)
#define reg_ckg_demod_adc_s 0
#define reg_ckg_demod_adc_e 2
#define reg_ckg_xtal_12m_demod0 ckgen00(0x02C0)
#define reg_ckg_xtal_12m_demod0_s 0
#define reg_ckg_xtal_12m_demod0_e 1
#define reg_ckg_xtal_24m_demod0 ckgen00(0x02C8)
#define reg_ckg_xtal_24m_demod0_s 0
#define reg_ckg_xtal_24m_demod0_e 1
#define reg_ckg_acifir ckgen00(0x02D0)
#define reg_ckg_acifir_s 0
#define reg_ckg_acifir_e 1
#define reg_ckg_adcd ckgen00(0x02D8)
#define reg_ckg_adcd_s 0
#define reg_ckg_adcd_e 1
#define reg_ckg_atsc200_ph1 ckgen00(0x02E0)
#define reg_ckg_atsc200_ph1_s 0
#define reg_ckg_atsc200_ph1_e 1
#define reg_ckg_atsc200_ph3 ckgen00(0x02E8)
#define reg_ckg_atsc200_ph3_s 0
#define reg_ckg_atsc200_ph3_e 1
#define reg_ckg_atsc25 ckgen00(0x02F0)
#define reg_ckg_atsc25_s 0
#define reg_ckg_atsc25_e 1
#define reg_ckg_atsc400 ckgen00(0x02F8)
#define reg_ckg_atsc400_s 0
#define reg_ckg_atsc400_e 1
#define reg_ckg_atsc50 ckgen00(0x0300)
#define reg_ckg_atsc50_s 0
#define reg_ckg_atsc50_e 1
#define reg_ckg_atsc_adcd_sync ckgen00(0x0308)
#define reg_ckg_atsc_adcd_sync_s 0
#define reg_ckg_atsc_adcd_sync_e 1
#define reg_ckg_atsc_ce25 ckgen00(0x0310)
#define reg_ckg_atsc_ce25_s 0
#define reg_ckg_atsc_ce25_e 1
#define reg_ckg_atsc_eq25 ckgen00(0x0318)
#define reg_ckg_atsc_eq25_s 0
#define reg_ckg_atsc_eq25_e 1
#define reg_ckg_dmd_dma ckgen00(0x0320)
#define reg_ckg_dmd_dma_s 0
#define reg_ckg_dmd_dma_e 1
#define reg_ckg_dtmb_adc ckgen00(0x0328)
#define reg_ckg_dtmb_adc_s 0
#define reg_ckg_dtmb_adc_e 1
#define reg_ckg_dtmb_bch_demod0 ckgen00(0x0330)
#define reg_ckg_dtmb_bch_demod0_s 0
#define reg_ckg_dtmb_bch_demod0_e 1
#define reg_ckg_dtmb_eq0p25x ckgen00(0x0338)
#define reg_ckg_dtmb_eq0p25x_s 0
#define reg_ckg_dtmb_eq0p25x_e 1
#define reg_ckg_dtmb_eq0p5x ckgen00(0x0340)
#define reg_ckg_dtmb_eq0p5x_s 0
#define reg_ckg_dtmb_eq0p5x_e 1
#define reg_ckg_dtmb_eq1x ckgen00(0x0348)
#define reg_ckg_dtmb_eq1x_s 0
#define reg_ckg_dtmb_eq1x_e 1
#define reg_ckg_dtmb_eq2x ckgen00(0x0350)
#define reg_ckg_dtmb_eq2x_s 0
#define reg_ckg_dtmb_eq2x_e 1
#define reg_ckg_dtmb_eq2x_inner12x ckgen00(0x0358)
#define reg_ckg_dtmb_eq2x_inner12x_s 0
#define reg_ckg_dtmb_eq2x_inner12x_e 1
#define reg_ckg_dtmb_eq2x_inner2x_12x ckgen00(0x0360)
#define reg_ckg_dtmb_eq2x_inner2x_12x_s 0
#define reg_ckg_dtmb_eq2x_inner2x_12x_e 1
#define reg_ckg_dtmb_eq2x_inner4x ckgen00(0x0368)
#define reg_ckg_dtmb_eq2x_inner4x_s 0
#define reg_ckg_dtmb_eq2x_inner4x_e 1
#define reg_ckg_dtmb_inner12x ckgen00(0x0370)
#define reg_ckg_dtmb_inner12x_s 0
#define reg_ckg_dtmb_inner12x_e 1
#define reg_ckg_dtmb_inner12x_eq0p25x ckgen00(0x0378)
#define reg_ckg_dtmb_inner12x_eq0p25x_s 0
#define reg_ckg_dtmb_inner12x_eq0p25x_e 1
#define reg_ckg_dtmb_inner12x_inner4x ckgen00(0x0380)
#define reg_ckg_dtmb_inner12x_inner4x_s 0
#define reg_ckg_dtmb_inner12x_inner4x_e 1
#define reg_ckg_dtmb_inner12x_inner6x ckgen00(0x0388)
#define reg_ckg_dtmb_inner12x_inner6x_s 0
#define reg_ckg_dtmb_inner12x_inner6x_e 1
#define reg_ckg_dtmb_inner12x_inner8x_tap_com ckgen00(0x0390)
#define reg_ckg_dtmb_inner12x_inner8x_tap_com_s 0
#define reg_ckg_dtmb_inner12x_inner8x_tap_com_e 1
#define reg_ckg_dtmb_inner1x ckgen00(0x0398)
#define reg_ckg_dtmb_inner1x_s 0
#define reg_ckg_dtmb_inner1x_e 1
#define reg_ckg_dtmb_inner1x_atsc25 ckgen00(0x03A0)
#define reg_ckg_dtmb_inner1x_atsc25_s 0
#define reg_ckg_dtmb_inner1x_atsc25_e 1
#define reg_ckg_dtmb_inner24x ckgen00(0x03A8)
#define reg_ckg_dtmb_inner24x_s 0
#define reg_ckg_dtmb_inner24x_e 1
#define reg_ckg_dtmb_inner24x_atsc_400 ckgen00(0x03B0)
#define reg_ckg_dtmb_inner24x_atsc_400_s 0
#define reg_ckg_dtmb_inner24x_atsc_400_e 1
#define reg_ckg_dtmb_inner2x ckgen00(0x03B8)
#define reg_ckg_dtmb_inner2x_s 0
#define reg_ckg_dtmb_inner2x_e 1
#define reg_ckg_dtmb_inner2x_4x_sr1x ckgen00(0x03C0)
#define reg_ckg_dtmb_inner2x_4x_sr1x_s 0
#define reg_ckg_dtmb_inner2x_4x_sr1x_e 1
#define reg_ckg_dtmb_inner2x_sr0p5x ckgen00(0x03C8)
#define reg_ckg_dtmb_inner2x_sr0p5x_s 0
#define reg_ckg_dtmb_inner2x_sr0p5x_e 1
#define reg_ckg_dtmb_inner4x ckgen00(0x03D0)
#define reg_ckg_dtmb_inner4x_s 0
#define reg_ckg_dtmb_inner4x_e 1
#define reg_ckg_dtmb_inner4x_atsc50 ckgen00(0x03D8)
#define reg_ckg_dtmb_inner4x_atsc50_s 0
#define reg_ckg_dtmb_inner4x_atsc50_e 1
#define reg_ckg_dtmb_inner4x_sr1x ckgen00(0x03E0)
#define reg_ckg_dtmb_inner4x_sr1x_s 0
#define reg_ckg_dtmb_inner4x_sr1x_e 1
#define reg_ckg_dtmb_inner6x ckgen00(0x03E8)
#define reg_ckg_dtmb_inner6x_s 0
#define reg_ckg_dtmb_inner6x_e 1
#define reg_ckg_dtmb_inner8x ckgen00(0x03F0)
#define reg_ckg_dtmb_inner8x_s 0
#define reg_ckg_dtmb_inner8x_e 1
#define reg_ckg_dtmb_inner8x_tap_com ckgen00(0x03F8)
#define reg_ckg_dtmb_inner8x_tap_com_s 0
#define reg_ckg_dtmb_inner8x_tap_com_e 1
#define reg_ckg_dtmb_ldpc ckgen00(0x0400)
#define reg_ckg_dtmb_ldpc_s 0
#define reg_ckg_dtmb_ldpc_e 1
#define reg_ckg_dtmb_ldpc2x ckgen00(0x0408)
#define reg_ckg_dtmb_ldpc2x_s 0
#define reg_ckg_dtmb_ldpc2x_e 1
#define reg_ckg_dtmb_outer1x ckgen00(0x0410)
#define reg_ckg_dtmb_outer1x_s 0
#define reg_ckg_dtmb_outer1x_e 1
#define reg_ckg_dtmb_outer2x ckgen00(0x0418)
#define reg_ckg_dtmb_outer2x_s 0
#define reg_ckg_dtmb_outer2x_e 1
#define reg_ckg_dtmb_outer8x ckgen00(0x0420)
#define reg_ckg_dtmb_outer8x_s 0
#define reg_ckg_dtmb_outer8x_e 1
#define reg_ckg_dtmb_sram_dump ckgen00(0x0428)
#define reg_ckg_dtmb_sram_dump_s 0
#define reg_ckg_dtmb_sram_dump_e 1
#define reg_ckg_dvbs2_bch ckgen00(0x0430)
#define reg_ckg_dvbs2_bch_s 0
#define reg_ckg_dvbs2_bch_e 1
#define reg_ckg_dvbs2_diseqc ckgen00(0x0438)
#define reg_ckg_dvbs2_diseqc_s 0
#define reg_ckg_dvbs2_diseqc_e 1
#define reg_ckg_dvbs2_inner ckgen00(0x0440)
#define reg_ckg_dvbs2_inner_s 0
#define reg_ckg_dvbs2_inner_e 1
#define reg_ckg_dvbs2_oppro ckgen00(0x0448)
#define reg_ckg_dvbs2_oppro_s 0
#define reg_ckg_dvbs2_oppro_e 1
#define reg_ckg_dvbs_outer1x ckgen00(0x0450)
#define reg_ckg_dvbs_outer1x_s 0
#define reg_ckg_dvbs_outer1x_e 1
#define reg_ckg_dvbs_outer2x ckgen00(0x0458)
#define reg_ckg_dvbs_outer2x_s 0
#define reg_ckg_dvbs_outer2x_e 1
#define reg_ckg_dvbs_outer2x_dvbt_outer2x ckgen00(0x0460)
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_s 0
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_e 1
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x ckgen00(0x0468)
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_s 0
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_e 1
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_miu ckgen00(0x0470)
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_s 0
#define reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_e 1
#define reg_ckg_dvbt2_inner1x ckgen00(0x0478)
#define reg_ckg_dvbt2_inner1x_s 0
#define reg_ckg_dvbt2_inner1x_e 1
#define reg_ckg_dvbt2_inner2x ckgen00(0x0480)
#define reg_ckg_dvbt2_inner2x_s 0
#define reg_ckg_dvbt2_inner2x_e 1
#define reg_ckg_dvbt2_inner2x_srd0p5x ckgen00(0x0488)
#define reg_ckg_dvbt2_inner2x_srd0p5x_s 0
#define reg_ckg_dvbt2_inner2x_srd0p5x_e 1
#define reg_ckg_dvbt2_inner4x ckgen00(0x0490)
#define reg_ckg_dvbt2_inner4x_s 0
#define reg_ckg_dvbt2_inner4x_e 1
#define reg_ckg_dvbt2_inner4x_dvbtc_rs ckgen00(0x0498)
#define reg_ckg_dvbt2_inner4x_dvbtc_rs_s 0
#define reg_ckg_dvbt2_inner4x_dvbtc_rs_e 1
#define reg_ckg_dvbt2_inner4x_s2_inner ckgen00(0x04A0)
#define reg_ckg_dvbt2_inner4x_s2_inner_s 0
#define reg_ckg_dvbt2_inner4x_s2_inner_e 1
#define reg_ckg_dvbt_inner1x ckgen00(0x04A8)
#define reg_ckg_dvbt_inner1x_s 0
#define reg_ckg_dvbt_inner1x_e 1
#define reg_ckg_dvbt_inner2x ckgen00(0x04B0)
#define reg_ckg_dvbt_inner2x_s 0
#define reg_ckg_dvbt_inner2x_e 1
#define reg_ckg_dvbt_inner2x_srd0p5x ckgen00(0x04B8)
#define reg_ckg_dvbt_inner2x_srd0p5x_s 0
#define reg_ckg_dvbt_inner2x_srd0p5x_e 1
#define reg_ckg_dvbt_inner4x ckgen00(0x04C0)
#define reg_ckg_dvbt_inner4x_s 0
#define reg_ckg_dvbt_inner4x_e 1
#define reg_ckg_dvbt_outer1x_demod0 ckgen00(0x04C8)
#define reg_ckg_dvbt_outer1x_demod0_s 0
#define reg_ckg_dvbt_outer1x_demod0_e 1
#define reg_ckg_dvbt_outer2x ckgen00(0x04D0)
#define reg_ckg_dvbt_outer2x_s 0
#define reg_ckg_dvbt_outer2x_e 1
#define reg_ckg_dvbtc_adc ckgen00(0x04D8)
#define reg_ckg_dvbtc_adc_s 0
#define reg_ckg_dvbtc_adc_e 1
#define reg_ckg_dvbtc_outer2x ckgen00(0x04E0)
#define reg_ckg_dvbtc_outer2x_s 0
#define reg_ckg_dvbtc_outer2x_e 1
#define reg_ckg_dvbtc_outer2x_isdbt_outer_rs ckgen00(0x04E8)
#define reg_ckg_dvbtc_outer2x_isdbt_outer_rs_s 0
#define reg_ckg_dvbtc_outer2x_isdbt_outer_rs_e 1
#define reg_ckg_dvbtc_rs ckgen00(0x04F0)
#define reg_ckg_dvbtc_rs_s 0
#define reg_ckg_dvbtc_rs_e 1
#define reg_ckg_dvbtc_sram1 ckgen00(0x04F8)
#define reg_ckg_dvbtc_sram1_s 0
#define reg_ckg_dvbtc_sram1_e 1
#define reg_ckg_dvbtc_sram3 ckgen00(0x0500)
#define reg_ckg_dvbtc_sram3_s 0
#define reg_ckg_dvbtc_sram3_e 1
#define reg_ckg_dvbtc_sram4 ckgen00(0x0508)
#define reg_ckg_dvbtc_sram4_s 0
#define reg_ckg_dvbtc_sram4_e 1
#define reg_ckg_dvbtc_ts ckgen00(0x0510)
#define reg_ckg_dvbtc_ts_s 0
#define reg_ckg_dvbtc_ts_e 1
#define reg_ckg_dvbtm_adc0p5x_eq0p5x ckgen00(0x0518)
#define reg_ckg_dvbtm_adc0p5x_eq0p5x_s 0
#define reg_ckg_dvbtm_adc0p5x_eq0p5x_e 1
#define reg_ckg_dvbtm_adc1x_eq1x ckgen00(0x0520)
#define reg_ckg_dvbtm_adc1x_eq1x_s 0
#define reg_ckg_dvbtm_adc1x_eq1x_e 1
#define reg_ckg_dvbtm_sram_adc_t22x ckgen00(0x0528)
#define reg_ckg_dvbtm_sram_adc_t22x_s 0
#define reg_ckg_dvbtm_sram_adc_t22x_e 1
#define reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs ckgen00(0x0530)
#define reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs_s 0
#define reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs_e 1
#define reg_ckg_dvbtm_sram_t11x_t22x ckgen00(0x0538)
#define reg_ckg_dvbtm_sram_t11x_t22x_s 0
#define reg_ckg_dvbtm_sram_t11x_t22x_e 1
#define reg_ckg_dvbtm_sram_t11x_t24x ckgen00(0x0540)
#define reg_ckg_dvbtm_sram_t11x_t24x_s 0
#define reg_ckg_dvbtm_sram_t11x_t24x_e 1
#define reg_ckg_dvbtm_sram_t12x_t22x ckgen00(0x0548)
#define reg_ckg_dvbtm_sram_t12x_t22x_s 0
#define reg_ckg_dvbtm_sram_t12x_t22x_e 1
#define reg_ckg_dvbtm_sram_t12x_t24x ckgen00(0x0550)
#define reg_ckg_dvbtm_sram_t12x_t24x_s 0
#define reg_ckg_dvbtm_sram_t12x_t24x_e 1
#define reg_ckg_dvbtm_sram_t12x_t24x_s2inner ckgen00(0x0558)
#define reg_ckg_dvbtm_sram_t12x_t24x_s2inner_s 0
#define reg_ckg_dvbtm_sram_t12x_t24x_s2inner_e 1
#define reg_ckg_dvbtm_sram_t12x_t24x_srd1x ckgen00(0x0560)
#define reg_ckg_dvbtm_sram_t12x_t24x_srd1x_s 0
#define reg_ckg_dvbtm_sram_t12x_t24x_srd1x_e 1
#define reg_ckg_dvbtm_sram_t14x_t24x ckgen00(0x0568)
#define reg_ckg_dvbtm_sram_t14x_t24x_s 0
#define reg_ckg_dvbtm_sram_t14x_t24x_e 1
#define reg_ckg_dvbtm_sram_t14x_t24x_s2inner ckgen00(0x0570)
#define reg_ckg_dvbtm_sram_t14x_t24x_s2inner_s 0
#define reg_ckg_dvbtm_sram_t14x_t24x_s2inner_e 1
#define reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifdac ckgen00(0x0578)
#define reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifdac_s 0
#define reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifdac_e 1
#define reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc ckgen00(0x0580)
#define reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_s 0
#define reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_e 1
#define reg_ckg_dvbtm_sram_t1outer1x_t24x ckgen00(0x0588)
#define reg_ckg_dvbtm_sram_t1outer1x_t24x_s 0
#define reg_ckg_dvbtm_sram_t1outer1x_t24x_e 1
#define reg_ckg_isdbt_inner1x ckgen00(0x0590)
#define reg_ckg_isdbt_inner1x_s 0
#define reg_ckg_isdbt_inner1x_e 1
#define reg_ckg_isdbt_inner1x_dvbt_inner1x ckgen00(0x0598)
#define reg_ckg_isdbt_inner1x_dvbt_inner1x_s 0
#define reg_ckg_isdbt_inner1x_dvbt_inner1x_e 1
#define reg_ckg_isdbt_inner2x ckgen00(0x05A0)
#define reg_ckg_isdbt_inner2x_s 0
#define reg_ckg_isdbt_inner2x_e 1
#define reg_ckg_isdbt_inner2x_dvbt_inner2x ckgen00(0x05A8)
#define reg_ckg_isdbt_inner2x_dvbt_inner2x_s 0
#define reg_ckg_isdbt_inner2x_dvbt_inner2x_e 1
#define reg_ckg_isdbt_inner4x ckgen00(0x05B0)
#define reg_ckg_isdbt_inner4x_s 0
#define reg_ckg_isdbt_inner4x_e 1
#define reg_ckg_isdbt_inner4x_dvbt_inner4x ckgen00(0x05B8)
#define reg_ckg_isdbt_inner4x_dvbt_inner4x_s 0
#define reg_ckg_isdbt_inner4x_dvbt_inner4x_e 1
#define reg_ckg_isdbt_inner4x_dvbt_inner4x_adc ckgen00(0x05C0)
#define reg_ckg_isdbt_inner4x_dvbt_inner4x_adc_s 0
#define reg_ckg_isdbt_inner4x_dvbt_inner4x_adc_e 1
#define reg_ckg_isdbt_outer12x ckgen00(0x05C8)
#define reg_ckg_isdbt_outer12x_s 0
#define reg_ckg_isdbt_outer12x_e 1
#define reg_ckg_isdbt_outer1x ckgen00(0x05D0)
#define reg_ckg_isdbt_outer1x_s 0
#define reg_ckg_isdbt_outer1x_e 1
#define reg_ckg_isdbt_outer1x_dvbt_outer1x ckgen00(0x05D8)
#define reg_ckg_isdbt_outer1x_dvbt_outer1x_s 0
#define reg_ckg_isdbt_outer1x_dvbt_outer1x_e 1
#define reg_ckg_isdbt_outer4x ckgen00(0x05E0)
#define reg_ckg_isdbt_outer4x_s 0
#define reg_ckg_isdbt_outer4x_e 1
#define reg_ckg_isdbt_outer6x ckgen00(0x05E8)
#define reg_ckg_isdbt_outer6x_s 0
#define reg_ckg_isdbt_outer6x_e 1
#define reg_ckg_isdbt_outer6x_dvbt_inner1x ckgen00(0x05F0)
#define reg_ckg_isdbt_outer6x_dvbt_inner1x_s 0
#define reg_ckg_isdbt_outer6x_dvbt_inner1x_e 1
#define reg_ckg_isdbt_outer6x_dvbt_inner2x ckgen00(0x05F8)
#define reg_ckg_isdbt_outer6x_dvbt_inner2x_s 0
#define reg_ckg_isdbt_outer6x_dvbt_inner2x_e 1
#define reg_ckg_isdbt_outer6x_dvbt_outer2x ckgen00(0x0600)
#define reg_ckg_isdbt_outer6x_dvbt_outer2x_s 0
#define reg_ckg_isdbt_outer6x_dvbt_outer2x_e 1
#define reg_ckg_isdbt_outer6x_dvbt_outer2x_c ckgen00(0x0608)
#define reg_ckg_isdbt_outer6x_dvbt_outer2x_c_s 0
#define reg_ckg_isdbt_outer6x_dvbt_outer2x_c_e 1
#define reg_ckg_isdbt_outer_rs ckgen00(0x0610)
#define reg_ckg_isdbt_outer_rs_s 0
#define reg_ckg_isdbt_outer_rs_e 1
#define reg_ckg_sram_share_00_0 ckgen00(0x0640)
#define reg_ckg_sram_share_00_0_s 0
#define reg_ckg_sram_share_00_0_e 1
#define reg_ckg_sram_share_00_1 ckgen00(0x0648)
#define reg_ckg_sram_share_00_1_s 0
#define reg_ckg_sram_share_00_1_e 1
#define reg_ckg_sram_share_01_0 ckgen00(0x0650)
#define reg_ckg_sram_share_01_0_s 0
#define reg_ckg_sram_share_01_0_e 1
#define reg_ckg_sram_share_02_0 ckgen00(0x0658)
#define reg_ckg_sram_share_02_0_s 0
#define reg_ckg_sram_share_02_0_e 1
#define reg_ckg_sram_share_03_0 ckgen00(0x0660)
#define reg_ckg_sram_share_03_0_s 0
#define reg_ckg_sram_share_03_0_e 1
#define reg_ckg_sram_share_03_1 ckgen00(0x0668)
#define reg_ckg_sram_share_03_1_s 0
#define reg_ckg_sram_share_03_1_e 1
#define reg_ckg_sram_share_04_0 ckgen00(0x0670)
#define reg_ckg_sram_share_04_0_s 0
#define reg_ckg_sram_share_04_0_e 1
#define reg_ckg_sram_share_04_1 ckgen00(0x0678)
#define reg_ckg_sram_share_04_1_s 0
#define reg_ckg_sram_share_04_1_e 1
#define reg_ckg_sram_share_05 ckgen00(0x0680)
#define reg_ckg_sram_share_05_s 0
#define reg_ckg_sram_share_05_e 1
#define reg_ckg_sram_share_06 ckgen00(0x0688)
#define reg_ckg_sram_share_06_s 0
#define reg_ckg_sram_share_06_e 1
#define reg_ckg_sram_share_07 ckgen00(0x0690)
#define reg_ckg_sram_share_07_s 0
#define reg_ckg_sram_share_07_e 1
#define reg_ckg_sram_share_08 ckgen00(0x0698)
#define reg_ckg_sram_share_08_s 0
#define reg_ckg_sram_share_08_e 1
#define reg_ckg_sram_share_09 ckgen00(0x06A0)
#define reg_ckg_sram_share_09_s 0
#define reg_ckg_sram_share_09_e 1
#define reg_ckg_sram_share_10 ckgen00(0x06A8)
#define reg_ckg_sram_share_10_s 0
#define reg_ckg_sram_share_10_e 1
#define reg_ckg_sram_share_11 ckgen00(0x06B0)
#define reg_ckg_sram_share_11_s 0
#define reg_ckg_sram_share_11_e 1
#define reg_ckg_sram_share_12 ckgen00(0x06B8)
#define reg_ckg_sram_share_12_s 0
#define reg_ckg_sram_share_12_e 1
#define reg_ckg_sram_share_13 ckgen00(0x06C0)
#define reg_ckg_sram_share_13_s 0
#define reg_ckg_sram_share_13_e 1
#define reg_ckg_sram_share_14_r ckgen00(0x06C8)
#define reg_ckg_sram_share_14_r_s 0
#define reg_ckg_sram_share_14_r_e 1
#define reg_ckg_sram_share_14_w ckgen00(0x06D0)
#define reg_ckg_sram_share_14_w_s 0
#define reg_ckg_sram_share_14_w_e 1
#define reg_ckg_sram_share_15_r ckgen00(0x06D8)
#define reg_ckg_sram_share_15_r_s 0
#define reg_ckg_sram_share_15_r_e 1
#define reg_ckg_sram_share_15_w ckgen00(0x06E0)
#define reg_ckg_sram_share_15_w_s 0
#define reg_ckg_sram_share_15_w_e 1
#define reg_ckg_sram_share_16 ckgen00(0x06E8)
#define reg_ckg_sram_share_16_s 0
#define reg_ckg_sram_share_16_e 1
#define reg_ckg_sram_share_18 ckgen00(0x06F0)
#define reg_ckg_sram_share_18_s 0
#define reg_ckg_sram_share_18_e 1
#define reg_ckg_sram_share_19 ckgen00(0x06F8)
#define reg_ckg_sram_share_19_s 0
#define reg_ckg_sram_share_19_e 1
#define reg_ckg_sram_share_20 ckgen00(0x0700)
#define reg_ckg_sram_share_20_s 0
#define reg_ckg_sram_share_20_e 1
#define reg_ckg_sram_share_21 ckgen00(0x0708)
#define reg_ckg_sram_share_21_s 0
#define reg_ckg_sram_share_21_e 1
#define reg_ckg_sram_share_22 ckgen00(0x0710)
#define reg_ckg_sram_share_22_s 0
#define reg_ckg_sram_share_22_e 1
#define reg_ckg_sram_share_23 ckgen00(0x0718)
#define reg_ckg_sram_share_23_s 0
#define reg_ckg_sram_share_23_e 1
#define reg_ckg_sram_share_24 ckgen00(0x0720)
#define reg_ckg_sram_share_24_s 0
#define reg_ckg_sram_share_24_e 1
#define reg_ckg_sram_share_26 ckgen00(0x0728)
#define reg_ckg_sram_share_26_s 0
#define reg_ckg_sram_share_26_e 1
#define reg_ckg_sram_share_27 ckgen00(0x0730)
#define reg_ckg_sram_share_27_s 0
#define reg_ckg_sram_share_27_e 1
#define reg_ckg_sram_share_28 ckgen00(0x0738)
#define reg_ckg_sram_share_28_s 0
#define reg_ckg_sram_share_28_e 1
#define reg_ckg_sram_share_29 ckgen00(0x0740)
#define reg_ckg_sram_share_29_s 0
#define reg_ckg_sram_share_29_e 1
#define reg_ckg_sram_share_34 ckgen00(0x0748)
#define reg_ckg_sram_share_34_s 0
#define reg_ckg_sram_share_34_e 1
#define reg_ckg_sram_share_35 ckgen00(0x0750)
#define reg_ckg_sram_share_35_s 0
#define reg_ckg_sram_share_35_e 2
#define reg_ckg_sram_share_36 ckgen00(0x0758)
#define reg_ckg_sram_share_36_s 0
#define reg_ckg_sram_share_36_e 2
#define reg_ckg_sram_share_40 ckgen00(0x0760)
#define reg_ckg_sram_share_40_s 0
#define reg_ckg_sram_share_40_e 2
#define reg_ckg_sram_share_42 ckgen00(0x0768)
#define reg_ckg_sram_share_42_s 0
#define reg_ckg_sram_share_42_e 1
#define reg_ckg_sram_share_44 ckgen00(0x0770)
#define reg_ckg_sram_share_44_s 0
#define reg_ckg_sram_share_44_e 1
#define reg_ckg_sram_share_46 ckgen00(0x0778)
#define reg_ckg_sram_share_46_s 0
#define reg_ckg_sram_share_46_e 1
#define reg_ckg_sram_share_47 ckgen00(0x0780)
#define reg_ckg_sram_share_47_s 0
#define reg_ckg_sram_share_47_e 2
#define reg_ckg_sram_share_50_0 ckgen00(0x0788)
#define reg_ckg_sram_share_50_0_s 0
#define reg_ckg_sram_share_50_0_e 1
#define reg_ckg_sram_share_52_0 ckgen00(0x0790)
#define reg_ckg_sram_share_52_0_s 0
#define reg_ckg_sram_share_52_0_e 1
#define reg_ckg_sram_share_53_0 ckgen00(0x0798)
#define reg_ckg_sram_share_53_0_s 0
#define reg_ckg_sram_share_53_0_e 1
#define reg_ckg_sram_share_55_0 ckgen00(0x07A0)
#define reg_ckg_sram_share_55_0_s 0
#define reg_ckg_sram_share_55_0_e 1
#define reg_ckg_sram_share_56 ckgen00(0x07A8)
#define reg_ckg_sram_share_56_s 0
#define reg_ckg_sram_share_56_e 1
#define reg_ckg_sram_share_57 ckgen00(0x07B0)
#define reg_ckg_sram_share_57_s 0
#define reg_ckg_sram_share_57_e 1
#define reg_ckg_sram_share_58 ckgen00(0x07B8)
#define reg_ckg_sram_share_58_s 0
#define reg_ckg_sram_share_58_e 1
#define reg_ckg_sram_share_59 ckgen00(0x07C0)
#define reg_ckg_sram_share_59_s 0
#define reg_ckg_sram_share_59_e 1
#define reg_ckg_sram_share_60 ckgen00(0x07C8)
#define reg_ckg_sram_share_60_s 0
#define reg_ckg_sram_share_60_e 1
#define reg_ckg_sram_share_61 ckgen00(0x07D0)
#define reg_ckg_sram_share_61_s 0
#define reg_ckg_sram_share_61_e 1
#define reg_ckg_sram_share_62 ckgen00(0x07D8)
#define reg_ckg_sram_share_62_s 0
#define reg_ckg_sram_share_62_e 1
#define reg_ckg_sram_share_64 ckgen00(0x07E0)
#define reg_ckg_sram_share_64_s 0
#define reg_ckg_sram_share_64_e 1
#define reg_ckg_sram_share_66 ckgen00(0x07E8)
#define reg_ckg_sram_share_66_s 0
#define reg_ckg_sram_share_66_e 1
#define reg_ckg_sram_share_67 ckgen00(0x07F0)
#define reg_ckg_sram_share_67_s 0
#define reg_ckg_sram_share_67_e 1
#define reg_ckg_sram_share_68_0 ckgen00(0x07F8)
#define reg_ckg_sram_share_68_0_s 0
#define reg_ckg_sram_share_68_0_e 2
#define reg_ckg_sram_share_68_2 ckgen00(0x0800)
#define reg_ckg_sram_share_68_2_s 0
#define reg_ckg_sram_share_68_2_e 1
#define reg_ckg_sram_share_69_0 ckgen00(0x0808)
#define reg_ckg_sram_share_69_0_s 0
#define reg_ckg_sram_share_69_0_e 1
#define reg_ckg_sram_share_70 ckgen00(0x0810)
#define reg_ckg_sram_share_70_s 0
#define reg_ckg_sram_share_70_e 2
#define reg_ckg_sram_share_71 ckgen00(0x0818)
#define reg_ckg_sram_share_71_s 0
#define reg_ckg_sram_share_71_e 1
#define reg_ckg_sram_share_77 ckgen00(0x0820)
#define reg_ckg_sram_share_77_s 0
#define reg_ckg_sram_share_77_e 1
#define reg_ckg_sram_share_79 ckgen00(0x0828)
#define reg_ckg_sram_share_79_s 0
#define reg_ckg_sram_share_79_e 1
#define reg_ckg_sram_share_81 ckgen00(0x0830)
#define reg_ckg_sram_share_81_s 0
#define reg_ckg_sram_share_81_e 1
#define reg_ckg_sram_share_85 ckgen00(0x0838)
#define reg_ckg_sram_share_85_s 0
#define reg_ckg_sram_share_85_e 1
#define reg_ckg_sram_share_87 ckgen00(0x0840)
#define reg_ckg_sram_share_87_s 0
#define reg_ckg_sram_share_87_e 1
#define reg_ckg_sram_share_89 ckgen00(0x0848)
#define reg_ckg_sram_share_89_s 0
#define reg_ckg_sram_share_89_e 1
#define reg_ckg_sram_share_91 ckgen00(0x0850)
#define reg_ckg_sram_share_91_s 0
#define reg_ckg_sram_share_91_e 1
#define reg_ckg_sram_share_92 ckgen00(0x0858)
#define reg_ckg_sram_share_92_s 0
#define reg_ckg_sram_share_92_e 1
#define reg_ckg_sram_share_93 ckgen00(0x0860)
#define reg_ckg_sram_share_93_s 0
#define reg_ckg_sram_share_93_e 1
#define reg_ckg_sram_share_94 ckgen00(0x0868)
#define reg_ckg_sram_share_94_s 0
#define reg_ckg_sram_share_94_e 1
#define reg_ckg_sram_share_96 ckgen00(0x0870)
#define reg_ckg_sram_share_96_s 0
#define reg_ckg_sram_share_96_e 1
#define reg_ckg_sram_share_98 ckgen00(0x0878)
#define reg_ckg_sram_share_98_s 0
#define reg_ckg_sram_share_98_e 1
#define reg_ckg_sram_share_99 ckgen00(0x0880)
#define reg_ckg_sram_share_99_s 0
#define reg_ckg_sram_share_99_e 1
#define reg_ckg_sram_share_100 ckgen00(0x0888)
#define reg_ckg_sram_share_100_s 0
#define reg_ckg_sram_share_100_e 1
#define reg_ckg_sram_share_103 ckgen00(0x0890)
#define reg_ckg_sram_share_103_s 0
#define reg_ckg_sram_share_103_e 1
#define reg_ckg_sram_share_105 ckgen00(0x0898)
#define reg_ckg_sram_share_105_s 0
#define reg_ckg_sram_share_105_e 1
#define reg_ckg_sram_share_107 ckgen00(0x08A0)
#define reg_ckg_sram_share_107_s 0
#define reg_ckg_sram_share_107_e 1
#define reg_ckg_sram_share_109 ckgen00(0x08A8)
#define reg_ckg_sram_share_109_s 0
#define reg_ckg_sram_share_109_e 1
#define reg_ckg_sram_share_110 ckgen00(0x08B0)
#define reg_ckg_sram_share_110_s 0
#define reg_ckg_sram_share_110_e 1
#define reg_ckg_sram_share_111 ckgen00(0x08B8)
#define reg_ckg_sram_share_111_s 0
#define reg_ckg_sram_share_111_e 1
#define reg_ckg_sram_share_112 ckgen00(0x08C0)
#define reg_ckg_sram_share_112_s 0
#define reg_ckg_sram_share_112_e 1
#define reg_ckg_sram_share_124 ckgen00(0x08C8)
#define reg_ckg_sram_share_124_s 0
#define reg_ckg_sram_share_124_e 1
#define reg_ckg_sram_share_128 ckgen00(0x08D0)
#define reg_ckg_sram_share_128_s 0
#define reg_ckg_sram_share_128_e 1
#define reg_ckg_sram_share_129 ckgen00(0x08D8)
#define reg_ckg_sram_share_129_s 0
#define reg_ckg_sram_share_129_e 1
#define reg_ckg_sram_share_130 ckgen00(0x08E0)
#define reg_ckg_sram_share_130_s 0
#define reg_ckg_sram_share_130_e 1
#define reg_ckg_sram_share_131 ckgen00(0x08E8)
#define reg_ckg_sram_share_131_s 0
#define reg_ckg_sram_share_131_e 1
#define reg_ckg_sram_share_132 ckgen00(0x08F0)
#define reg_ckg_sram_share_132_s 0
#define reg_ckg_sram_share_132_e 1
#define reg_ckg_sram_share_134_r ckgen00(0x08F8)
#define reg_ckg_sram_share_134_r_s 0
#define reg_ckg_sram_share_134_r_e 1
#define reg_ckg_sram_share_134_w ckgen00(0x0900)
#define reg_ckg_sram_share_134_w_s 0
#define reg_ckg_sram_share_134_w_e 1
#define reg_ckg_sram_share_136_r ckgen00(0x0908)
#define reg_ckg_sram_share_136_r_s 0
#define reg_ckg_sram_share_136_r_e 1
#define reg_ckg_sram_share_136_w ckgen00(0x0910)
#define reg_ckg_sram_share_136_w_s 0
#define reg_ckg_sram_share_136_w_e 1
#define reg_ckg_sram_share_137_r ckgen00(0x0918)
#define reg_ckg_sram_share_137_r_s 0
#define reg_ckg_sram_share_137_r_e 1
#define reg_ckg_sram_share_137_w ckgen00(0x0920)
#define reg_ckg_sram_share_137_w_s 0
#define reg_ckg_sram_share_137_w_e 1
#define reg_ckg_sram_share_138_r ckgen00(0x0928)
#define reg_ckg_sram_share_138_r_s 0
#define reg_ckg_sram_share_138_r_e 1
#define reg_ckg_sram_share_138_w ckgen00(0x0930)
#define reg_ckg_sram_share_138_w_s 0
#define reg_ckg_sram_share_138_w_e 1
#define reg_ckg_sram_share_139_r ckgen00(0x0938)
#define reg_ckg_sram_share_139_r_s 0
#define reg_ckg_sram_share_139_r_e 1
#define reg_ckg_sram_share_139_w ckgen00(0x0940)
#define reg_ckg_sram_share_139_w_s 0
#define reg_ckg_sram_share_139_w_e 1
#define reg_ckg_sram_share_140_r ckgen00(0x0948)
#define reg_ckg_sram_share_140_r_s 0
#define reg_ckg_sram_share_140_r_e 1
#define reg_ckg_sram_share_140_w ckgen00(0x0950)
#define reg_ckg_sram_share_140_w_s 0
#define reg_ckg_sram_share_140_w_e 1
#define reg_ckg_sram_share_141_r ckgen00(0x0958)
#define reg_ckg_sram_share_141_r_s 0
#define reg_ckg_sram_share_141_r_e 1
#define reg_ckg_sram_share_141_w ckgen00(0x0960)
#define reg_ckg_sram_share_141_w_s 0
#define reg_ckg_sram_share_141_w_e 1
#define reg_ckg_sram_share_142_r ckgen00(0x0968)
#define reg_ckg_sram_share_142_r_s 0
#define reg_ckg_sram_share_142_r_e 1
#define reg_ckg_sram_share_142_w ckgen00(0x0970)
#define reg_ckg_sram_share_142_w_s 0
#define reg_ckg_sram_share_142_w_e 1
#define reg_ckg_sram_share_143_r ckgen00(0x0978)
#define reg_ckg_sram_share_143_r_s 0
#define reg_ckg_sram_share_143_r_e 1
#define reg_ckg_sram_share_143_w ckgen00(0x0980)
#define reg_ckg_sram_share_143_w_s 0
#define reg_ckg_sram_share_143_w_e 1
#define reg_ckg_sram_share_144_r ckgen00(0x0988)
#define reg_ckg_sram_share_144_r_s 0
#define reg_ckg_sram_share_144_r_e 1
#define reg_ckg_sram_share_144_w ckgen00(0x0990)
#define reg_ckg_sram_share_144_w_s 0
#define reg_ckg_sram_share_144_w_e 1
#define reg_ckg_tdp_jl_inner1x ckgen00(0x0998)
#define reg_ckg_tdp_jl_inner1x_s 0
#define reg_ckg_tdp_jl_inner1x_e 1
#define reg_ckg_tdp_jl_inner4x ckgen00(0x09A0)
#define reg_ckg_tdp_jl_inner4x_s 0
#define reg_ckg_tdp_jl_inner4x_e 1
#define reg_ckg_tdp_teq_inner1x ckgen00(0x09A8)
#define reg_ckg_tdp_teq_inner1x_s 0
#define reg_ckg_tdp_teq_inner1x_e 1
#define reg_ckg_tdp_teq_inner2x ckgen00(0x09B0)
#define reg_ckg_tdp_teq_inner2x_s 0
#define reg_ckg_tdp_teq_inner2x_e 1
#define reg_ckg_tr ckgen00(0x09B8)
#define reg_ckg_tr_s 0
#define reg_ckg_tr_e 1
#define reg_ckg_ts_in ckgen00(0x09C0)
#define reg_ckg_ts_in_s 0
#define reg_ckg_ts_in_e 1
#define reg_ckg_vifdbb_144m ckgen00(0x09C8)
#define reg_ckg_vifdbb_144m_s 0
#define reg_ckg_vifdbb_144m_e 1
#define reg_ckg_vifdbb_43m ckgen00(0x09D0)
#define reg_ckg_vifdbb_43m_s 0
#define reg_ckg_vifdbb_43m_e 1
#define reg_ckg_vifdbb_86m ckgen00(0x09D8)
#define reg_ckg_vifdbb_86m_s 0
#define reg_ckg_vifdbb_86m_e 1
#define reg_ckg_vifdbb_dac ckgen00(0x09E0)
#define reg_ckg_vifdbb_dac_s 0
#define reg_ckg_vifdbb_dac_e 1
#define reg_ckg_vifdbb_vdac ckgen00(0x09E8)
#define reg_ckg_vifdbb_vdac_s 0
#define reg_ckg_vifdbb_vdac_e 1
#define reg_ckg_vifdbb_vdac_tmp ckgen00(0x09F0)
#define reg_ckg_vifdbb_vdac_tmp_s 0
#define reg_ckg_vifdbb_vdac_tmp_e 1
#define reg_ckg_deinter ckgen00(0x09F8)
#define reg_ckg_deinter_s 0
#define reg_ckg_deinter_e 1
#define reg_ckg_dtmb_bch_demod1 ckgen00(0x0A00)
#define reg_ckg_dtmb_bch_demod1_s 0
#define reg_ckg_dtmb_bch_demod1_e 1
#define reg_ckg_dtmb_outer1x_demod1 ckgen00(0x0A08)
#define reg_ckg_dtmb_outer1x_demod1_s 0
#define reg_ckg_dtmb_outer1x_demod1_e 1
#define reg_ckg_dvbs2_demapper ckgen00(0x0A10)
#define reg_ckg_dvbs2_demapper_s 0
#define reg_ckg_dvbs2_demapper_e 1
#define reg_ckg_dvbs2_dvbt2_demapper ckgen00(0x0A18)
#define reg_ckg_dvbs2_dvbt2_demapper_s 0
#define reg_ckg_dvbs2_dvbt2_demapper_e 1
#define reg_ckg_dvbs2_outer_fifo_in ckgen00(0x0A20)
#define reg_ckg_dvbs2_outer_fifo_in_s 0
#define reg_ckg_dvbs2_outer_fifo_in_e 1
#define reg_ckg_dvbt2_demapper ckgen00(0x0A28)
#define reg_ckg_dvbt2_demapper_s 0
#define reg_ckg_dvbt2_demapper_e 1
#define reg_ckg_dvbt2_dvbs2_outer_fifo_in ckgen00(0x0A30)
#define reg_ckg_dvbt2_dvbs2_outer_fifo_in_s 0
#define reg_ckg_dvbt2_dvbs2_outer_fifo_in_e 1
#define reg_ckg_dvbt2_outer_fifo_in ckgen00(0x0A38)
#define reg_ckg_dvbt2_outer_fifo_in_s 0
#define reg_ckg_dvbt2_outer_fifo_in_e 1
#define reg_ckg_dvbt2_s2_bch ckgen00(0x0A40)
#define reg_ckg_dvbt2_s2_bch_s 0
#define reg_ckg_dvbt2_s2_bch_e 1
#define reg_ckg_dvbt2_s2_bch_out ckgen00(0x0A48)
#define reg_ckg_dvbt2_s2_bch_out_s 0
#define reg_ckg_dvbt2_s2_bch_out_e 1
#define reg_ckg_ldpc1x ckgen00(0x0A50)
#define reg_ckg_ldpc1x_s 0
#define reg_ckg_ldpc1x_e 1
#define reg_ckg_ldpc2x ckgen00(0x0A58)
#define reg_ckg_ldpc2x_s 0
#define reg_ckg_ldpc2x_e 1
#define reg_ckg_sram_dvbt2_s2_bch_me ckgen00(0x0A60)
#define reg_ckg_sram_dvbt2_s2_bch_me_s 0
#define reg_ckg_sram_dvbt2_s2_bch_me_e 1
#define reg_ckg_sram_ldpc1x_me ckgen00(0x0A68)
#define reg_ckg_sram_ldpc1x_me_s 0
#define reg_ckg_sram_ldpc1x_me_e 1
#define reg_ckg_sram_ldpc2x_me ckgen00(0x0A70)
#define reg_ckg_sram_ldpc2x_me_s 0
#define reg_ckg_sram_ldpc2x_me_e 1
#define reg_ckg_xtal_24m_demod1 ckgen00(0x0A78)
#define reg_ckg_xtal_24m_demod1_s 0
#define reg_ckg_xtal_24m_demod1_e 1
#define reg_ckg_xtal_12m_demod1 ckgen00(0x0AB8)
#define reg_ckg_xtal_12m_demod1_s 0
#define reg_ckg_xtal_12m_demod1_e 1
#define reg_ckg_aesdma ckgen00(0x0B10)
#define reg_ckg_aesdma_s 0
#define reg_ckg_aesdma_e 3
#define reg_ckg_aesdma_tsp ckgen00(0x0B10)
#define reg_ckg_aesdma_tsp_s 8
#define reg_ckg_aesdma_tsp_e 9
#define reg_ckg_parser ckgen00(0x0B18)
#define reg_ckg_parser_s 0
#define reg_ckg_parser_e 3
#define reg_ckg_viva_parser ckgen00(0x0B18)
#define reg_ckg_viva_parser_s 8
#define reg_ckg_viva_parser_e 11
#define reg_ckg_parser_tsp ckgen00(0x0B18)
#define reg_ckg_parser_tsp_s 12
#define reg_ckg_parser_tsp_e 13
#define reg_ckg_smart2 ckgen00(0x0B28)
#define reg_ckg_smart2_s 0
#define reg_ckg_smart2_e 3
#define reg_ckg_smart2_mheg5 ckgen00(0x0B28)
#define reg_ckg_smart2_mheg5_s 8
#define reg_ckg_smart2_mheg5_e 9
#define reg_ckg_smart ckgen00(0x0B30)
#define reg_ckg_smart_s 0
#define reg_ckg_smart_e 3
#define reg_ckg_smart_mheg5 ckgen00(0x0B30)
#define reg_ckg_smart_mheg5_s 8
#define reg_ckg_smart_mheg5_e 9
#define reg_ckg_tso2_out_div_mn_src ckgen00(0x0B38)
#define reg_ckg_tso2_out_div_mn_src_s 0
#define reg_ckg_tso2_out_div_mn_src_e 4
#define reg_ckg_tso_out_div_mn_src ckgen00(0x0B40)
#define reg_ckg_tso_out_div_mn_src_s 0
#define reg_ckg_tso_out_div_mn_src_e 4
#define reg_ckg_tsp ckgen00(0x0B48)
#define reg_ckg_tsp_s 0
#define reg_ckg_tsp_e 3
#define reg_ckg_tsp_tsp ckgen00(0x0B48)
#define reg_ckg_tsp_tsp_s 4
#define reg_ckg_tsp_tsp_e 5
#define reg_ckg_fiq0_27m ckgen00(0x0B50)
#define reg_ckg_fiq0_27m_s 0
#define reg_ckg_fiq0_27m_e 4
#define reg_ckg_mm0_27m ckgen00(0x0B58)
#define reg_ckg_mm0_27m_s 0
#define reg_ckg_mm0_27m_e 4
#define reg_ckg_mm1_27m ckgen00(0x0B60)
#define reg_ckg_mm1_27m_s 0
#define reg_ckg_mm1_27m_e 4
#define reg_ckg_pvr1_27m ckgen00(0x0B68)
#define reg_ckg_pvr1_27m_s 0
#define reg_ckg_pvr1_27m_e 4
#define reg_ckg_pvr2_27m ckgen00(0x0B70)
#define reg_ckg_pvr2_27m_s 0
#define reg_ckg_pvr2_27m_e 4
#define reg_ckg_pvr3_27m ckgen00(0x0B78)
#define reg_ckg_pvr3_27m_s 0
#define reg_ckg_pvr3_27m_e 4
#define reg_ckg_pvr4_27m ckgen00(0x0B80)
#define reg_ckg_pvr4_27m_s 0
#define reg_ckg_pvr4_27m_e 4
#define reg_ckg_stamp ckgen00(0x0B88)
#define reg_ckg_stamp_s 0
#define reg_ckg_stamp_e 2
#define reg_ckg_syn_stc0 ckgen00(0x0B90)
#define reg_ckg_syn_stc0_s 0
#define reg_ckg_syn_stc0_e 4
#define reg_ckg_syn_stc1 ckgen00(0x0B98)
#define reg_ckg_syn_stc1_s 0
#define reg_ckg_syn_stc1_e 4
#define reg_ckg_syn_stc2 ckgen00(0x0BA0)
#define reg_ckg_syn_stc2_s 0
#define reg_ckg_syn_stc2_e 4
#define reg_ckg_syn_stc3 ckgen00(0x0BA8)
#define reg_ckg_syn_stc3_s 0
#define reg_ckg_syn_stc3_e 4
#define reg_ckg_sys_time0_27m ckgen00(0x0BB0)
#define reg_ckg_sys_time0_27m_s 0
#define reg_ckg_sys_time0_27m_e 4
#define reg_ckg_sys_time1_27m ckgen00(0x0BB8)
#define reg_ckg_sys_time1_27m_s 0
#define reg_ckg_sys_time1_27m_e 4
#define reg_ckg_sys_time2_27m ckgen00(0x0BC0)
#define reg_ckg_sys_time2_27m_s 0
#define reg_ckg_sys_time2_27m_e 4
#define reg_ckg_sys_time3_27m ckgen00(0x0BC8)
#define reg_ckg_sys_time3_27m_s 0
#define reg_ckg_sys_time3_27m_e 4
#define reg_ckg_tlv0_27m ckgen00(0x0BD0)
#define reg_ckg_tlv0_27m_s 0
#define reg_ckg_tlv0_27m_e 4
#define reg_ckg_tlv1_27m ckgen00(0x0BD8)
#define reg_ckg_tlv1_27m_s 0
#define reg_ckg_tlv1_27m_e 4
#define reg_ckg_tlv2_27m ckgen00(0x0BE0)
#define reg_ckg_tlv2_27m_s 0
#define reg_ckg_tlv2_27m_e 4
#define reg_ckg_tsif0_27m ckgen00(0x0BE8)
#define reg_ckg_tsif0_27m_s 0
#define reg_ckg_tsif0_27m_e 4
#define reg_ckg_tso2_ch1_27m ckgen00(0x0BF0)
#define reg_ckg_tso2_ch1_27m_s 0
#define reg_ckg_tso2_ch1_27m_e 4
#define reg_ckg_tso2_ch5_27m ckgen00(0x0BF8)
#define reg_ckg_tso2_ch5_27m_s 0
#define reg_ckg_tso2_ch5_27m_e 4
#define reg_ckg_tso2_ch6_27m ckgen00(0x0C00)
#define reg_ckg_tso2_ch6_27m_s 0
#define reg_ckg_tso2_ch6_27m_e 4
#define reg_ckg_p_tso2_out ckgen00(0x0C08)
#define reg_ckg_p_tso2_out_s 0
#define reg_ckg_p_tso2_out_e 4
#define reg_ckg_tso_ch1_27m ckgen00(0x0C10)
#define reg_ckg_tso_ch1_27m_s 0
#define reg_ckg_tso_ch1_27m_e 4
#define reg_ckg_tso_ch5_27m ckgen00(0x0C18)
#define reg_ckg_tso_ch5_27m_s 0
#define reg_ckg_tso_ch5_27m_e 4
#define reg_ckg_tso_ch6_27m ckgen00(0x0C20)
#define reg_ckg_tso_ch6_27m_s 0
#define reg_ckg_tso_ch6_27m_e 4
#define reg_ckg_p_tso_out ckgen00(0x0C28)
#define reg_ckg_p_tso_out_s 0
#define reg_ckg_p_tso_out_e 4
#define reg_ckg_smart2_synth_432 ckgen00(0x0C30)
#define reg_ckg_smart2_synth_432_s 0
#define reg_ckg_smart2_synth_432_e 1
#define reg_ckg_smart2_synth_432_mheg5 ckgen00(0x0C30)
#define reg_ckg_smart2_synth_432_mheg5_s 8
#define reg_ckg_smart2_synth_432_mheg5_e 9
#define reg_ckg_smart2_synth_27 ckgen00(0x0C38)
#define reg_ckg_smart2_synth_27_s 0
#define reg_ckg_smart2_synth_27_e 1
#define reg_ckg_smart2_synth_27_mheg5 ckgen00(0x0C38)
#define reg_ckg_smart2_synth_27_mheg5_s 8
#define reg_ckg_smart2_synth_27_mheg5_e 9
#define reg_ckg_smart_synth_432 ckgen00(0x0C40)
#define reg_ckg_smart_synth_432_s 0
#define reg_ckg_smart_synth_432_e 1
#define reg_ckg_smart_synth_432_mheg5 ckgen00(0x0C40)
#define reg_ckg_smart_synth_432_mheg5_s 8
#define reg_ckg_smart_synth_432_mheg5_e 9
#define reg_ckg_smart_synth_27 ckgen00(0x0C48)
#define reg_ckg_smart_synth_27_s 0
#define reg_ckg_smart_synth_27_e 1
#define reg_ckg_smart_synth_27_mheg5 ckgen00(0x0C48)
#define reg_ckg_smart_synth_27_mheg5_s 8
#define reg_ckg_smart_synth_27_mheg5_e 9
#define reg_ckg_path0_27m ckgen00(0x0C50)
#define reg_ckg_path0_27m_s 0
#define reg_ckg_path0_27m_e 4
#define reg_ckg_path1_27m ckgen00(0x0C58)
#define reg_ckg_path1_27m_s 0
#define reg_ckg_path1_27m_e 4
#define reg_ckg_path2_27m ckgen00(0x0C60)
#define reg_ckg_path2_27m_s 0
#define reg_ckg_path2_27m_e 4
#define reg_ckg_path_fi_27m ckgen00(0x0C68)
#define reg_ckg_path_fi_27m_s 0
#define reg_ckg_path_fi_27m_e 4
#define reg_ckg_ausdm_3m ckgen00(0x0C98)
#define reg_ckg_ausdm_3m_s 0
#define reg_ckg_ausdm_3m_e 3
#define reg_ckg_bclk_i2s_encoder2 ckgen00(0x0CA0)
#define reg_ckg_bclk_i2s_encoder2_s 0
#define reg_ckg_bclk_i2s_encoder2_e 2
#define reg_ckg_bclk_i2s_encoder ckgen00(0x0CA8)
#define reg_ckg_bclk_i2s_encoder_s 0
#define reg_ckg_bclk_i2s_encoder_e 2
#define reg_ckg_earc_tx_pll_256fs_ref ckgen00(0x0CB0)
#define reg_ckg_earc_tx_pll_256fs_ref_s 0
#define reg_ckg_earc_tx_pll_256fs_ref_e 2
#define reg_ckg_viva_ab3_mac ckgen00(0x0CB8)
#define reg_ckg_viva_ab3_mac_s 0
#define reg_ckg_viva_ab3_mac_e 4
#define reg_ckg_viva_ab_mac ckgen00(0x0CC0)
#define reg_ckg_viva_ab_mac_s 0
#define reg_ckg_viva_ab_mac_e 3
#define reg_ckg_viva_adc_512fs ckgen00(0x0CC8)
#define reg_ckg_viva_adc_512fs_s 0
#define reg_ckg_viva_adc_512fs_e 3
#define reg_ckg_viva_audma_v2_r1_256fs ckgen00(0x0CD0)
#define reg_ckg_viva_audma_v2_r1_256fs_s 0
#define reg_ckg_viva_audma_v2_r1_256fs_e 2
#define reg_ckg_viva_audma_v2_r1_synth_ref ckgen00(0x0CD8)
#define reg_ckg_viva_audma_v2_r1_synth_ref_s 0
#define reg_ckg_viva_audma_v2_r1_synth_ref_e 4
#define reg_ckg_viva_audma_v2_r2_256fs ckgen00(0x0CE0)
#define reg_ckg_viva_audma_v2_r2_256fs_s 0
#define reg_ckg_viva_audma_v2_r2_256fs_e 2
#define reg_ckg_viva_audma_v2_r2_synth_ref ckgen00(0x0CE8)
#define reg_ckg_viva_audma_v2_r2_synth_ref_s 0
#define reg_ckg_viva_audma_v2_r2_synth_ref_e 4
#define reg_ckg_viva_aupll_in ckgen00(0x0CF0)
#define reg_ckg_viva_aupll_in_s 0
#define reg_ckg_viva_aupll_in_e 3
#define reg_ckg_viva_bclk_i2s_decoder2 ckgen00(0x0CF8)
#define reg_ckg_viva_bclk_i2s_decoder2_s 0
#define reg_ckg_viva_bclk_i2s_decoder2_e 3
#define reg_ckg_viva_bclk_i2s_decoder ckgen00(0x0D00)
#define reg_ckg_viva_bclk_i2s_decoder_s 0
#define reg_ckg_viva_bclk_i2s_decoder_e 3
#define reg_ckg_viva_bi2s_synth_ref2 ckgen00(0x0D08)
#define reg_ckg_viva_bi2s_synth_ref2_s 0
#define reg_ckg_viva_bi2s_synth_ref2_e 4
#define reg_ckg_viva_ch1_256fsi ckgen00(0x0D10)
#define reg_ckg_viva_ch1_256fsi_s 0
#define reg_ckg_viva_ch1_256fsi_e 2
#define reg_ckg_viva_ch2_256fsi ckgen00(0x0D18)
#define reg_ckg_viva_ch2_256fsi_s 0
#define reg_ckg_viva_ch2_256fsi_e 2
#define reg_ckg_viva_ch3_256fsi ckgen00(0x0D20)
#define reg_ckg_viva_ch3_256fsi_s 0
#define reg_ckg_viva_ch3_256fsi_e 2
#define reg_ckg_viva_ch4_256fsi ckgen00(0x0D28)
#define reg_ckg_viva_ch4_256fsi_s 0
#define reg_ckg_viva_ch4_256fsi_e 2
#define reg_ckg_viva_ch5_256fsi ckgen00(0x0D30)
#define reg_ckg_viva_ch5_256fsi_s 0
#define reg_ckg_viva_ch5_256fsi_e 2
#define reg_ckg_viva_ch6_256fsi ckgen00(0x0D38)
#define reg_ckg_viva_ch6_256fsi_s 0
#define reg_ckg_viva_ch6_256fsi_e 2
#define reg_ckg_viva_ch7_256fsi ckgen00(0x0D40)
#define reg_ckg_viva_ch7_256fsi_s 0
#define reg_ckg_viva_ch7_256fsi_e 2
#define reg_ckg_viva_ch8_256fsi ckgen00(0x0D48)
#define reg_ckg_viva_ch8_256fsi_s 0
#define reg_ckg_viva_ch8_256fsi_e 2
#define reg_ckg_viva_ch9_256fsi ckgen00(0x0D50)
#define reg_ckg_viva_ch9_256fsi_s 0
#define reg_ckg_viva_ch9_256fsi_e 2
#define reg_ckg_viva_codec_sh ckgen00(0x0D58)
#define reg_ckg_viva_codec_sh_s 0
#define reg_ckg_viva_codec_sh_e 3
#define reg_ckg_viva_dac_512fs ckgen00(0x0D60)
#define reg_ckg_viva_dac_512fs_s 0
#define reg_ckg_viva_dac_512fs_e 3
#define reg_ckg_viva_dsp ckgen00(0x0D68)
#define reg_ckg_viva_dsp_s 0
#define reg_ckg_viva_dsp_e 4
#define reg_ckg_viva_dvb1_synth_ref ckgen00(0x0D70)
#define reg_ckg_viva_dvb1_synth_ref_s 0
#define reg_ckg_viva_dvb1_synth_ref_e 3
#define reg_ckg_viva_dvb1_timing_gen_256fs ckgen00(0x0D78)
#define reg_ckg_viva_dvb1_timing_gen_256fs_s 0
#define reg_ckg_viva_dvb1_timing_gen_256fs_e 2
#define reg_ckg_viva_dvb2_synth_ref ckgen00(0x0D80)
#define reg_ckg_viva_dvb2_synth_ref_s 0
#define reg_ckg_viva_dvb2_synth_ref_e 3
#define reg_ckg_viva_dvb2_timing_gen_256fs ckgen00(0x0D88)
#define reg_ckg_viva_dvb2_timing_gen_256fs_s 0
#define reg_ckg_viva_dvb2_timing_gen_256fs_e 2
#define reg_ckg_viva_dvb3_synth_ref ckgen00(0x0D90)
#define reg_ckg_viva_dvb3_synth_ref_s 0
#define reg_ckg_viva_dvb3_synth_ref_e 3
#define reg_ckg_viva_dvb3_timing_gen_256fs ckgen00(0x0D98)
#define reg_ckg_viva_dvb3_timing_gen_256fs_s 0
#define reg_ckg_viva_dvb3_timing_gen_256fs_e 2
#define reg_ckg_viva_dvb4_synth_ref ckgen00(0x0DA0)
#define reg_ckg_viva_dvb4_synth_ref_s 0
#define reg_ckg_viva_dvb4_synth_ref_e 3
#define reg_ckg_viva_dvb4_timing_gen_256fs ckgen00(0x0DA8)
#define reg_ckg_viva_dvb4_timing_gen_256fs_s 0
#define reg_ckg_viva_dvb4_timing_gen_256fs_e 2
#define reg_ckg_viva_dvb5_timing_gen_256fs ckgen00(0x0DB0)
#define reg_ckg_viva_dvb5_timing_gen_256fs_s 0
#define reg_ckg_viva_dvb5_timing_gen_256fs_e 2
#define reg_ckg_viva_dvb6_timing_gen_256fs ckgen00(0x0DB8)
#define reg_ckg_viva_dvb6_timing_gen_256fs_s 0
#define reg_ckg_viva_dvb6_timing_gen_256fs_e 2
#define reg_ckg_viva_earc_tx_32xchxfs ckgen00(0x0DC0)
#define reg_ckg_viva_earc_tx_32xchxfs_s 0
#define reg_ckg_viva_earc_tx_32xchxfs_e 2
#define reg_ckg_viva_earc_tx_32xfs ckgen00(0x0DC8)
#define reg_ckg_viva_earc_tx_32xfs_s 0
#define reg_ckg_viva_earc_tx_32xfs_e 2
#define reg_ckg_viva_earc_tx_64xchxfs ckgen00(0x0DD0)
#define reg_ckg_viva_earc_tx_64xchxfs_s 0
#define reg_ckg_viva_earc_tx_64xchxfs_e 2
#define reg_ckg_viva_earc_tx_gpa_synth_ref ckgen00(0x0DD8)
#define reg_ckg_viva_earc_tx_gpa_synth_ref_s 0
#define reg_ckg_viva_earc_tx_gpa_synth_ref_e 2
#define reg_ckg_viva_earc_tx_pll ckgen00(0x0DE0)
#define reg_ckg_viva_earc_tx_pll_s 0
#define reg_ckg_viva_earc_tx_pll_e 2
#define reg_ckg_viva_earc_tx_source_256fs ckgen00(0x0DE8)
#define reg_ckg_viva_earc_tx_source_256fs_s 0
#define reg_ckg_viva_earc_tx_source_256fs_e 2
#define reg_ckg_viva_earc_tx_synth_iir_ref ckgen00(0x0DF0)
#define reg_ckg_viva_earc_tx_synth_iir_ref_s 0
#define reg_ckg_viva_earc_tx_synth_iir_ref_e 2
#define reg_ckg_viva_earc_tx_synth_ref ckgen00(0x0DF8)
#define reg_ckg_viva_earc_tx_synth_ref_s 0
#define reg_ckg_viva_earc_tx_synth_ref_e 3
#define reg_ckg_viva_fm_demodulator ckgen00(0x0E00)
#define reg_ckg_viva_fm_demodulator_s 0
#define reg_ckg_viva_fm_demodulator_e 4
#define reg_ckg_viva_gpa_240fso ckgen00(0x0E08)
#define reg_ckg_viva_gpa_240fso_s 0
#define reg_ckg_viva_gpa_240fso_e 2
#define reg_ckg_viva_gpa_256fso ckgen00(0x0E10)
#define reg_ckg_viva_gpa_256fso_s 0
#define reg_ckg_viva_gpa_256fso_e 2
#define reg_ckg_viva_gpa_480fso ckgen00(0x0E18)
#define reg_ckg_viva_gpa_480fso_s 0
#define reg_ckg_viva_gpa_480fso_e 2
#define reg_ckg_viva_hdmi_rx2_mpll_432 ckgen00(0x0E20)
#define reg_ckg_viva_hdmi_rx2_mpll_432_s 0
#define reg_ckg_viva_hdmi_rx2_mpll_432_e 2
#define reg_ckg_viva_hdmi_rx2_s2p_128fs ckgen00(0x0E28)
#define reg_ckg_viva_hdmi_rx2_s2p_128fs_s 0
#define reg_ckg_viva_hdmi_rx2_s2p_128fs_e 2
#define reg_ckg_viva_hdmi_rx2_s2p_256fs ckgen00(0x0E30)
#define reg_ckg_viva_hdmi_rx2_s2p_256fs_s 0
#define reg_ckg_viva_hdmi_rx2_s2p_256fs_e 2
#define reg_ckg_viva_hdmi_rx2_synth_ref ckgen00(0x0E38)
#define reg_ckg_viva_hdmi_rx2_synth_ref_s 0
#define reg_ckg_viva_hdmi_rx2_synth_ref_e 2
#define reg_ckg_viva_hdmi_rx2_v2a_time_stamp ckgen00(0x0E40)
#define reg_ckg_viva_hdmi_rx2_v2a_time_stamp_s 0
#define reg_ckg_viva_hdmi_rx2_v2a_time_stamp_e 1
#define reg_ckg_viva_hdmi_rx_mpll_432 ckgen00(0x0E48)
#define reg_ckg_viva_hdmi_rx_mpll_432_s 0
#define reg_ckg_viva_hdmi_rx_mpll_432_e 2
#define reg_ckg_viva_hdmi_rx_s2p_128fs ckgen00(0x0E50)
#define reg_ckg_viva_hdmi_rx_s2p_128fs_s 0
#define reg_ckg_viva_hdmi_rx_s2p_128fs_e 2
#define reg_ckg_viva_hdmi_rx_s2p_256fs ckgen00(0x0E58)
#define reg_ckg_viva_hdmi_rx_s2p_256fs_s 0
#define reg_ckg_viva_hdmi_rx_s2p_256fs_e 2
#define reg_ckg_viva_hdmi_rx_synth_ref ckgen00(0x0E60)
#define reg_ckg_viva_hdmi_rx_synth_ref_s 0
#define reg_ckg_viva_hdmi_rx_synth_ref_e 2
#define reg_ckg_viva_hdmi_rx_v2a_time_stamp ckgen00(0x0E68)
#define reg_ckg_viva_hdmi_rx_v2a_time_stamp_s 0
#define reg_ckg_viva_hdmi_rx_v2a_time_stamp_e 1
#define reg_ckg_viva_hdmi_tx_128fs ckgen00(0x0E70)
#define reg_ckg_viva_hdmi_tx_128fs_s 0
#define reg_ckg_viva_hdmi_tx_128fs_e 2
#define reg_ckg_viva_hdmi_tx_256fs ckgen00(0x0E78)
#define reg_ckg_viva_hdmi_tx_256fs_s 0
#define reg_ckg_viva_hdmi_tx_256fs_e 2
#define reg_ckg_viva_i2s_2_bclk_synth_ref ckgen00(0x0E80)
#define reg_ckg_viva_i2s_2_bclk_synth_ref_s 0
#define reg_ckg_viva_i2s_2_bclk_synth_ref_e 3
#define reg_ckg_viva_i2s_bclk_dg2 ckgen00(0x0E88)
#define reg_ckg_viva_i2s_bclk_dg2_s 0
#define reg_ckg_viva_i2s_bclk_dg2_e 2
#define reg_ckg_viva_i2s_bclk_dg ckgen00(0x0E90)
#define reg_ckg_viva_i2s_bclk_dg_s 0
#define reg_ckg_viva_i2s_bclk_dg_e 2
#define reg_ckg_viva_i2s_bclk_synth_ref ckgen00(0x0E98)
#define reg_ckg_viva_i2s_bclk_synth_ref_s 0
#define reg_ckg_viva_i2s_bclk_synth_ref_e 3
#define reg_ckg_viva_i2s_mclk_synth_ref ckgen00(0x0EA0)
#define reg_ckg_viva_i2s_mclk_synth_ref_s 0
#define reg_ckg_viva_i2s_mclk_synth_ref_e 2
#define reg_ckg_viva_i2s_synth_ref ckgen00(0x0EA8)
#define reg_ckg_viva_i2s_synth_ref_s 0
#define reg_ckg_viva_i2s_synth_ref_e 4
#define reg_ckg_viva_i2s_trx_bclk_timing_gen ckgen00(0x0EB0)
#define reg_ckg_viva_i2s_trx_bclk_timing_gen_s 0
#define reg_ckg_viva_i2s_trx_bclk_timing_gen_e 3
#define reg_ckg_viva_i2s_trx_synth_ref ckgen00(0x0EB8)
#define reg_ckg_viva_i2s_trx_synth_ref_s 0
#define reg_ckg_viva_i2s_trx_synth_ref_e 4
#define reg_ckg_viva_i2s_tx_fifo_256fs ckgen00(0x0EC0)
#define reg_ckg_viva_i2s_tx_fifo_256fs_s 0
#define reg_ckg_viva_i2s_tx_fifo_256fs_e 2
#define reg_ckg_viva_mclk_i2s_decoder2 ckgen00(0x0EC8)
#define reg_ckg_viva_mclk_i2s_decoder2_s 0
#define reg_ckg_viva_mclk_i2s_decoder2_e 4
#define reg_ckg_viva_mclk_i2s_decoder ckgen00(0x0ED0)
#define reg_ckg_viva_mclk_i2s_decoder_s 0
#define reg_ckg_viva_mclk_i2s_decoder_e 4
#define reg_ckg_viva_mclk_i2s_encoder2 ckgen00(0x0ED8)
#define reg_ckg_viva_mclk_i2s_encoder2_s 0
#define reg_ckg_viva_mclk_i2s_encoder2_e 4
#define reg_ckg_viva_mclk_i2s_encoder ckgen00(0x0EE0)
#define reg_ckg_viva_mclk_i2s_encoder_s 0
#define reg_ckg_viva_mclk_i2s_encoder_e 4
#define reg_ckg_viva_npcm2_synth_ref ckgen00(0x0EE8)
#define reg_ckg_viva_npcm2_synth_ref_s 0
#define reg_ckg_viva_npcm2_synth_ref_e 3
#define reg_ckg_viva_npcm3_synth_ref ckgen00(0x0EF0)
#define reg_ckg_viva_npcm3_synth_ref_s 0
#define reg_ckg_viva_npcm3_synth_ref_e 3
#define reg_ckg_viva_npcm4_256fs_timing_gen ckgen00(0x0EF8)
#define reg_ckg_viva_npcm4_256fs_timing_gen_s 0
#define reg_ckg_viva_npcm4_256fs_timing_gen_e 2
#define reg_ckg_viva_npcm4_synth_ref ckgen00(0x0F00)
#define reg_ckg_viva_npcm4_synth_ref_s 0
#define reg_ckg_viva_npcm4_synth_ref_e 3
#define reg_ckg_viva_npcm5_256fs_timing_gen ckgen00(0x0F08)
#define reg_ckg_viva_npcm5_256fs_timing_gen_s 0
#define reg_ckg_viva_npcm5_256fs_timing_gen_e 2
#define reg_ckg_viva_npcm5_synth_ref ckgen00(0x0F10)
#define reg_ckg_viva_npcm5_synth_ref_s 0
#define reg_ckg_viva_npcm5_synth_ref_e 3
#define reg_ckg_viva_npcm_synth_ref ckgen00(0x0F18)
#define reg_ckg_viva_npcm_synth_ref_s 0
#define reg_ckg_viva_npcm_synth_ref_e 3
#define reg_ckg_viva_pcm_clk_216 ckgen00(0x0F20)
#define reg_ckg_viva_pcm_clk_216_s 0
#define reg_ckg_viva_pcm_clk_216_e 2
#define reg_ckg_viva_pcm_clk_aupll ckgen00(0x0F28)
#define reg_ckg_viva_pcm_clk_aupll_s 0
#define reg_ckg_viva_pcm_clk_aupll_e 2
#define reg_ckg_r2_vivaldi9 ckgen00(0x0F2C)
#define reg_ckg_r2_vivaldi9_s 0
#define reg_ckg_r2_vivaldi9_e 1
#define reg_ckg_viva_r2_wb ckgen00(0x0F30)
#define reg_ckg_viva_r2_wb_s 0
#define reg_ckg_viva_r2_wb_e 2
#define reg_ckg_au_r2_wb ckgen00(0x0F30)
#define reg_ckg_au_r2_wb_s 8
#define reg_ckg_au_r2_wb_e 9
#define reg_ckg_mcu_wb_rv55audio ckgen00(0x0F30)
#define reg_ckg_mcu_wb_rv55audio_s 10
#define reg_ckg_mcu_wb_rv55audio_e 11
#define reg_ckg_viva_riu_brg_r2 ckgen00(0x0F38)
#define reg_ckg_viva_riu_brg_r2_s 0
#define reg_ckg_viva_riu_brg_r2_e 2
#define reg_ckg_viva_riu_r2 ckgen00(0x0F40)
#define reg_ckg_viva_riu_r2_s 0
#define reg_ckg_viva_riu_r2_e 3
#define reg_ckg_viva_sh ckgen00(0x0F48)
#define reg_ckg_viva_sh_s 0
#define reg_ckg_viva_sh_e 2
#define reg_ckg_viva_sif_adc_cic ckgen00(0x0F50)
#define reg_ckg_viva_sif_adc_cic_s 0
#define reg_ckg_viva_sif_adc_cic_e 3
#define reg_ckg_viva_sif_adc_r2b_fifo_in ckgen00(0x0F58)
#define reg_ckg_viva_sif_adc_r2b_fifo_in_s 0
#define reg_ckg_viva_sif_adc_r2b_fifo_in_e 3
#define reg_ckg_viva_sif_adc_r2b ckgen00(0x0F60)
#define reg_ckg_viva_sif_adc_r2b_s 0
#define reg_ckg_viva_sif_adc_r2b_e 3
#define reg_ckg_sif_cordic ckgen00(0x0F68)
#define reg_ckg_sif_cordic_s 0
#define reg_ckg_sif_cordic_e 4
#define reg_ckg_viva_sif_synth ckgen00(0x0F70)
#define reg_ckg_viva_sif_synth_s 0
#define reg_ckg_viva_sif_synth_e 3
#define reg_ckg_viva_sin_gen ckgen00(0x0F78)
#define reg_ckg_viva_sin_gen_s 0
#define reg_ckg_viva_sin_gen_e 2
#define reg_ckg_viva_spdif_extearc ckgen00(0x0F80)
#define reg_ckg_viva_spdif_extearc_s 0
#define reg_ckg_viva_spdif_extearc_e 2
#define reg_ckg_viva_spdif_rx_128fs ckgen00(0x0F88)
#define reg_ckg_viva_spdif_rx_128fs_s 0
#define reg_ckg_viva_spdif_rx_128fs_e 2
#define reg_ckg_viva_spdif_rx_dg ckgen00(0x0F90)
#define reg_ckg_viva_spdif_rx_dg_s 0
#define reg_ckg_viva_spdif_rx_dg_e 2
#define reg_ckg_viva_spdif_rx_synth_ref ckgen00(0x0F98)
#define reg_ckg_viva_spdif_rx_synth_ref_s 0
#define reg_ckg_viva_spdif_rx_synth_ref_e 3
#define reg_ckg_viva_spdif_tx2_128fs ckgen00(0x0FA0)
#define reg_ckg_viva_spdif_tx2_128fs_s 0
#define reg_ckg_viva_spdif_tx2_128fs_e 2
#define reg_ckg_viva_spdif_tx2_256fs ckgen00(0x0FA8)
#define reg_ckg_viva_spdif_tx2_256fs_s 0
#define reg_ckg_viva_spdif_tx2_256fs_e 2
#define reg_ckg_viva_spdif_tx_128fs ckgen00(0x0FB0)
#define reg_ckg_viva_spdif_tx_128fs_s 0
#define reg_ckg_viva_spdif_tx_128fs_e 2
#define reg_ckg_viva_spdif_tx_256fs ckgen00(0x0FB8)
#define reg_ckg_viva_spdif_tx_256fs_s 0
#define reg_ckg_viva_spdif_tx_256fs_e 2
#define reg_ckg_viva_spdif_tx_synth_ref ckgen00(0x0FC0)
#define reg_ckg_viva_spdif_tx_synth_ref_s 0
#define reg_ckg_viva_spdif_tx_synth_ref_e 2
#define reg_ckg_viva_synth_2nd_order ckgen00(0x0FC8)
#define reg_ckg_viva_synth_2nd_order_s 0
#define reg_ckg_viva_synth_2nd_order_e 3
#define reg_ckg_viva_synth_codec ckgen00(0x0FD0)
#define reg_ckg_viva_synth_codec_s 0
#define reg_ckg_viva_synth_codec_e 3
#define reg_ckg_viva_test_bus ckgen00(0x0FD8)
#define reg_ckg_viva_test_bus_s 0
#define reg_ckg_viva_test_bus_e 2
#define reg_ckg_viva_vbdma_mcu ckgen00(0x0FE0)
#define reg_ckg_viva_vbdma_mcu_s 0
#define reg_ckg_viva_vbdma_mcu_e 2
#define reg_ckg_viva_xtal_12m ckgen00(0x0FE8)
#define reg_ckg_viva_xtal_12m_s 0
#define reg_ckg_viva_xtal_12m_e 1
#define reg_ckg_viva_xtal_24m ckgen00(0x0FF0)
#define reg_ckg_viva_xtal_24m_s 0
#define reg_ckg_viva_xtal_24m_e 1
#define reg_ckg_au_r2_dfs ckgen00(0x0FF8)
#define reg_ckg_au_r2_dfs_s 0
#define reg_ckg_au_r2_dfs_e 2
#define reg_ckg_au_r2_pll ckgen00(0x1000)
#define reg_ckg_au_r2_pll_s 0
#define reg_ckg_au_r2_pll_e 2
#define reg_ckg_xtal_12m_rv55audio ckgen00(0x1008)
#define reg_ckg_xtal_12m_rv55audio_s 0
#define reg_ckg_xtal_12m_rv55audio_e 1
#define reg_ckg_xtal_24m_rv55audio ckgen00(0x100C)
#define reg_ckg_xtal_24m_rv55audio_s 0
#define reg_ckg_xtal_24m_rv55audio_e 1
#define reg_ckg_xtal_12m_audio_r2 ckgen00(0x1010)
#define reg_ckg_xtal_12m_audio_r2_s 0
#define reg_ckg_xtal_12m_audio_r2_e 1
#define reg_ckg_xtal_24m_audio_r2 ckgen00(0x1014)
#define reg_ckg_xtal_24m_audio_r2_s 0
#define reg_ckg_xtal_24m_audio_r2_e 1
#define reg_ckg_rv55audio ckgen00(0x1018)
#define reg_ckg_rv55audio_s 0
#define reg_ckg_rv55audio_e 4
#define reg_ckg_audma_v2_r1_256fs ckgen00(0x1020)
#define reg_ckg_audma_v2_r1_256fs_s 0
#define reg_ckg_audma_v2_r1_256fs_e 0
#define reg_ckg_bclk_i2s_encoder2_mux ckgen00(0x1028)
#define reg_ckg_bclk_i2s_encoder2_mux_s 0
#define reg_ckg_bclk_i2s_encoder2_mux_e 2
#define reg_ckg_bclk_i2s_encoder_mux ckgen00(0x1030)
#define reg_ckg_bclk_i2s_encoder_mux_s 0
#define reg_ckg_bclk_i2s_encoder_mux_e 2
#define reg_ckg_ch5_256fsi_mux ckgen00(0x1058)
#define reg_ckg_ch5_256fsi_mux_s 0
#define reg_ckg_ch5_256fsi_mux_e 4
#define reg_ckg_ch6_256fsi_mux ckgen00(0x1060)
#define reg_ckg_ch6_256fsi_mux_s 0
#define reg_ckg_ch6_256fsi_mux_e 4
#define reg_ckg_ch7_256fsi_mux ckgen00(0x1068)
#define reg_ckg_ch7_256fsi_mux_s 0
#define reg_ckg_ch7_256fsi_mux_e 4
#define reg_ckg_ch8_256fsi_mux ckgen00(0x1070)
#define reg_ckg_ch8_256fsi_mux_s 0
#define reg_ckg_ch8_256fsi_mux_e 4
#define reg_ckg_ch9_256fsi_mux ckgen00(0x1078)
#define reg_ckg_ch9_256fsi_mux_s 0
#define reg_ckg_ch9_256fsi_mux_e 4
#define reg_ckg_dec1_synth_hdmi_ctsn_div_mux ckgen00(0x1080)
#define reg_ckg_dec1_synth_hdmi_ctsn_div_mux_s 0
#define reg_ckg_dec1_synth_hdmi_ctsn_div_mux_e 2
#define reg_ckg_dec1_synth_spdif_cdr_div4_mux ckgen00(0x1088)
#define reg_ckg_dec1_synth_spdif_cdr_div4_mux_s 0
#define reg_ckg_dec1_synth_spdif_cdr_div4_mux_e 0
#define reg_ckg_dec2_synth_hdmi_ctsn_div_mux ckgen00(0x1090)
#define reg_ckg_dec2_synth_hdmi_ctsn_div_mux_s 0
#define reg_ckg_dec2_synth_hdmi_ctsn_div_mux_e 2
#define reg_ckg_dec2_synth_spdif_cdr_div4_mux ckgen00(0x1098)
#define reg_ckg_dec2_synth_spdif_cdr_div4_mux_s 0
#define reg_ckg_dec2_synth_spdif_cdr_div4_mux_e 0
#define reg_ckg_dec3_synth_hdmi_ctsn_div_mux ckgen00(0x10A0)
#define reg_ckg_dec3_synth_hdmi_ctsn_div_mux_s 0
#define reg_ckg_dec3_synth_hdmi_ctsn_div_mux_e 2
#define reg_ckg_dec3_synth_spdif_cdr_div4_mux ckgen00(0x10A8)
#define reg_ckg_dec3_synth_spdif_cdr_div4_mux_s 0
#define reg_ckg_dec3_synth_spdif_cdr_div4_mux_e 0
#define reg_ckg_dec4_synth_hdmi_ctsn_div_mux ckgen00(0x10B0)
#define reg_ckg_dec4_synth_hdmi_ctsn_div_mux_s 0
#define reg_ckg_dec4_synth_hdmi_ctsn_div_mux_e 2
#define reg_ckg_dec4_synth_spdif_cdr_div4_mux ckgen00(0x10B8)
#define reg_ckg_dec4_synth_spdif_cdr_div4_mux_s 0
#define reg_ckg_dec4_synth_spdif_cdr_div4_mux_e 0
#define reg_ckg_decoder1_function_mux ckgen00(0x10C0)
#define reg_ckg_decoder1_function_mux_s 0
#define reg_ckg_decoder1_function_mux_e 3
#define reg_ckg_decoder2_function_mux ckgen00(0x10C8)
#define reg_ckg_decoder2_function_mux_s 0
#define reg_ckg_decoder2_function_mux_e 3
#define reg_ckg_decoder3_function_mux ckgen00(0x10D0)
#define reg_ckg_decoder3_function_mux_s 0
#define reg_ckg_decoder3_function_mux_e 3
#define reg_ckg_decoder4_function_mux ckgen00(0x10D8)
#define reg_ckg_decoder4_function_mux_s 0
#define reg_ckg_decoder4_function_mux_e 3
#define reg_ckg_earc_tx_gpa_synth_mux ckgen00(0x10E0)
#define reg_ckg_earc_tx_gpa_synth_mux_s 0
#define reg_ckg_earc_tx_gpa_synth_mux_e 1
#define reg_ckg_earc_tx_source_mux ckgen00(0x10E8)
#define reg_ckg_earc_tx_source_mux_s 0
#define reg_ckg_earc_tx_source_mux_e 2
#define reg_ckg_hdmi2_patgen_en ckgen00(0x10F0)
#define reg_ckg_hdmi2_patgen_en_s 0
#define reg_ckg_hdmi2_patgen_en_e 0
#define reg_ckg_hdmi_patgen_en ckgen00(0x10F8)
#define reg_ckg_hdmi_patgen_en_s 0
#define reg_ckg_hdmi_patgen_en_e 0
#define reg_ckg_hdmi_rx_bypass_to_tx ckgen00(0x1100)
#define reg_ckg_hdmi_rx_bypass_to_tx_s 0
#define reg_ckg_hdmi_rx_bypass_to_tx_e 0
#define reg_ckg_hdmi_tx_256fs_mux0 ckgen00(0x1108)
#define reg_ckg_hdmi_tx_256fs_mux0_s 0
#define reg_ckg_hdmi_tx_256fs_mux0_e 0
#define reg_ckg_hdmi_tx_256fs_mux1 ckgen00(0x1110)
#define reg_ckg_hdmi_tx_256fs_mux1_s 0
#define reg_ckg_hdmi_tx_256fs_mux1_e 0
#define reg_ckg_hdmi_tx_to_i2s_tx ckgen00(0x1118)
#define reg_ckg_hdmi_tx_to_i2s_tx_s 0
#define reg_ckg_hdmi_tx_to_i2s_tx_e 0
#define reg_ckg_i2s_2_synth_ssc_mux ckgen00(0x1120)
#define reg_ckg_i2s_2_synth_ssc_mux_s 0
#define reg_ckg_i2s_2_synth_ssc_mux_e 0
#define reg_ckg_i2s_ch ckgen00(0x1128)
#define reg_ckg_i2s_ch_s 0
#define reg_ckg_i2s_ch_e 0
#define reg_ckg_i2s_synth_ssc_mux ckgen00(0x1130)
#define reg_ckg_i2s_synth_ssc_mux_s 0
#define reg_ckg_i2s_synth_ssc_mux_e 0
#define reg_ckg_pcm_mode ckgen00(0x1138)
#define reg_ckg_pcm_mode_s 0
#define reg_ckg_pcm_mode_e 0
#define reg_ckg_r2_wb_mux ckgen00(0x1140)
#define reg_ckg_r2_wb_mux_s 0
#define reg_ckg_r2_wb_mux_e 2
#define reg_ckg_spdif_extearc_128fs_mux ckgen00(0x1148)
#define reg_ckg_spdif_extearc_128fs_mux_s 0
#define reg_ckg_spdif_extearc_128fs_mux_e 2
#define reg_ckg_spdif_extearc_256fs_mux ckgen00(0x1150)
#define reg_ckg_spdif_extearc_256fs_mux_s 0
#define reg_ckg_spdif_extearc_256fs_mux_e 2
#define reg_ckg_spdif_extearc_mux ckgen00(0x1158)
#define reg_ckg_spdif_extearc_mux_s 0
#define reg_ckg_spdif_extearc_mux_e 0
#define reg_ckg_spdif_extearc_mux0 ckgen00(0x1160)
#define reg_ckg_spdif_extearc_mux0_s 0
#define reg_ckg_spdif_extearc_mux0_e 0
#define reg_ckg_spdif_tx2_gpa_synth_mux ckgen00(0x1168)
#define reg_ckg_spdif_tx2_gpa_synth_mux_s 0
#define reg_ckg_spdif_tx2_gpa_synth_mux_e 1
#define reg_ckg_spdif_tx2_mux ckgen00(0x1170)
#define reg_ckg_spdif_tx2_mux_s 0
#define reg_ckg_spdif_tx2_mux_e 2
#define reg_ckg_spdif_tx_gpa_synth_mux ckgen00(0x1178)
#define reg_ckg_spdif_tx_gpa_synth_mux_s 0
#define reg_ckg_spdif_tx_gpa_synth_mux_e 1
#define reg_ckg_spdif_tx_mux ckgen00(0x1180)
#define reg_ckg_spdif_tx_mux_s 0
#define reg_ckg_spdif_tx_mux_e 2
#define reg_ckg_viva_i2s_tx_2_fifo_256fs ckgen00(0x1184)
#define reg_ckg_viva_i2s_tx_2_fifo_256fs_s 0
#define reg_ckg_viva_i2s_tx_2_fifo_256fs_e 3
#define reg_ckg_earc_audio_earc_dmacro ckgen00(0x1188)
#define reg_ckg_earc_audio_earc_dmacro_s 0
#define reg_ckg_earc_audio_earc_dmacro_e 2
#define reg_ckg_ausdm_3m_ck ckgen00(0x1190)
#define reg_ckg_ausdm_3m_ck_s 0
#define reg_ckg_ausdm_3m_ck_e 1
#define reg_ckg_ch10_256fsi_mux ckgen00(0x1194)
#define reg_ckg_ch10_256fsi_mux_s 0
#define reg_ckg_ch10_256fsi_mux_e 4
#define reg_ckg_ch_m1_256fsi_mux ckgen00(0x1198)
#define reg_ckg_ch_m1_256fsi_mux_s 0
#define reg_ckg_ch_m1_256fsi_mux_e 3
#define reg_ckg_ch_m2_256fsi_mux ckgen00(0x119C)
#define reg_ckg_ch_m2_256fsi_mux_s 0
#define reg_ckg_ch_m2_256fsi_mux_e 3
#define reg_ckg_ch_m3_256fsi_mux ckgen00(0x11A0)
#define reg_ckg_ch_m3_256fsi_mux_s 0
#define reg_ckg_ch_m3_256fsi_mux_e 3
#define reg_ckg_ch_m4_256fsi_mux ckgen00(0x11A4)
#define reg_ckg_ch_m4_256fsi_mux_s 0
#define reg_ckg_ch_m4_256fsi_mux_e 3
#define reg_ckg_ch_m5_256fsi_mux ckgen00(0x11A8)
#define reg_ckg_ch_m5_256fsi_mux_s 0
#define reg_ckg_ch_m5_256fsi_mux_e 3
#define reg_ckg_ch_m6_256fsi_mux ckgen00(0x11AC)
#define reg_ckg_ch_m6_256fsi_mux_s 0
#define reg_ckg_ch_m6_256fsi_mux_e 3
#define reg_ckg_ch_m7_256fsi_mux ckgen00(0x11B0)
#define reg_ckg_ch_m7_256fsi_mux_s 0
#define reg_ckg_ch_m7_256fsi_mux_e 3
#define reg_ckg_ch_m8_256fsi_mux ckgen00(0x11B4)
#define reg_ckg_ch_m8_256fsi_mux_s 0
#define reg_ckg_ch_m8_256fsi_mux_e 3
#define reg_ckg_ch_m9_256fsi_mux ckgen00(0x11B8)
#define reg_ckg_ch_m9_256fsi_mux_s 0
#define reg_ckg_ch_m9_256fsi_mux_e 3
#define reg_ckg_ch_m10_256fsi_mux ckgen00(0x11BC)
#define reg_ckg_ch_m10_256fsi_mux_s 0
#define reg_ckg_ch_m10_256fsi_mux_e 3
#define reg_ckg_ch_m11_256fsi_mux ckgen00(0x11C0)
#define reg_ckg_ch_m11_256fsi_mux_s 0
#define reg_ckg_ch_m11_256fsi_mux_e 3
#define reg_ckg_ch_m12_256fsi_mux ckgen00(0x11C4)
#define reg_ckg_ch_m12_256fsi_mux_s 0
#define reg_ckg_ch_m12_256fsi_mux_e 3
#define reg_ckg_ch_m13_256fsi_mux ckgen00(0x11C8)
#define reg_ckg_ch_m13_256fsi_mux_s 0
#define reg_ckg_ch_m13_256fsi_mux_e 3
#define reg_ckg_ch_m14_256fsi_mux ckgen00(0x11CC)
#define reg_ckg_ch_m14_256fsi_mux_s 0
#define reg_ckg_ch_m14_256fsi_mux_e 3
#define reg_ckg_ch_m15_256fsi_mux ckgen00(0x11D0)
#define reg_ckg_ch_m15_256fsi_mux_s 0
#define reg_ckg_ch_m15_256fsi_mux_e 3
#define reg_ckg_ch_m16_256fsi_mux ckgen00(0x11D4)
#define reg_ckg_ch_m16_256fsi_mux_s 0
#define reg_ckg_ch_m16_256fsi_mux_e 3
#define reg_ckg_dap_tck_vivaldi9 ckgen00(0x11D8)
#define reg_ckg_dap_tck_vivaldi9_s 0
#define reg_ckg_dap_tck_vivaldi9_e 1
#define reg_ckg_dap_tck_rv55audio ckgen00(0x11D8)
#define reg_ckg_dap_tck_rv55audio_s 8
#define reg_ckg_dap_tck_rv55audio_e 9
#define reg_ckg_dap_vivaldi9 ckgen00(0x11DC)
#define reg_ckg_dap_vivaldi9_s 0
#define reg_ckg_dap_vivaldi9_e 1
#define reg_ckg_dap_rv55audio ckgen00(0x11DC)
#define reg_ckg_dap_rv55audio_s 8
#define reg_ckg_dap_rv55audio_e 9
#define reg_ckg_dec1_synth_hdmi2_ctsn_div_mux ckgen00(0x11E0)
#define reg_ckg_dec1_synth_hdmi2_ctsn_div_mux_s 0
#define reg_ckg_dec1_synth_hdmi2_ctsn_div_mux_e 2
#define reg_ckg_dec1_synth_spdif_cdr_div_mux ckgen00(0x11E4)
#define reg_ckg_dec1_synth_spdif_cdr_div_mux_s 0
#define reg_ckg_dec1_synth_spdif_cdr_div_mux_e 2
#define reg_ckg_dec2_synth_hdmi2_ctsn_div_mux ckgen00(0x11E8)
#define reg_ckg_dec2_synth_hdmi2_ctsn_div_mux_s 0
#define reg_ckg_dec2_synth_hdmi2_ctsn_div_mux_e 2
#define reg_ckg_dec2_synth_spdif_cdr_div_mux ckgen00(0x11EC)
#define reg_ckg_dec2_synth_spdif_cdr_div_mux_s 0
#define reg_ckg_dec2_synth_spdif_cdr_div_mux_e 2
#define reg_ckg_dec3_synth_hdmi2_ctsn_div_mux ckgen00(0x11F0)
#define reg_ckg_dec3_synth_hdmi2_ctsn_div_mux_s 0
#define reg_ckg_dec3_synth_hdmi2_ctsn_div_mux_e 2
#define reg_ckg_dec3_synth_spdif_cdr_div_mux ckgen00(0x11F4)
#define reg_ckg_dec3_synth_spdif_cdr_div_mux_s 0
#define reg_ckg_dec3_synth_spdif_cdr_div_mux_e 2
#define reg_ckg_dec4_synth_hdmi2_ctsn_div_mux ckgen00(0x11F8)
#define reg_ckg_dec4_synth_hdmi2_ctsn_div_mux_s 0
#define reg_ckg_dec4_synth_hdmi2_ctsn_div_mux_e 2
#define reg_ckg_dec4_synth_spdif_cdr_div_mux ckgen00(0x11FC)
#define reg_ckg_dec4_synth_spdif_cdr_div_mux_s 0
#define reg_ckg_dec4_synth_spdif_cdr_div_mux_e 2
#define reg_ckg_rv_tck_vivaldi9 ckgen00(0x1200)
#define reg_ckg_rv_tck_vivaldi9_s 0
#define reg_ckg_rv_tck_vivaldi9_e 1
#define reg_ckg_rv_tck_rv55audio ckgen00(0x1200)
#define reg_ckg_rv_tck_rv55audio_s 8
#define reg_ckg_rv_tck_rv55audio_e 9
#define reg_ckg_rv_vivaldi9 ckgen00(0x1204)
#define reg_ckg_rv_vivaldi9_s 0
#define reg_ckg_rv_vivaldi9_e 1
#define reg_ckg_viva_ch10_256fsi ckgen00(0x1208)
#define reg_ckg_viva_ch10_256fsi_s 0
#define reg_ckg_viva_ch10_256fsi_e 2
#define reg_ckg_viva_ch_m1_256fsi ckgen00(0x120C)
#define reg_ckg_viva_ch_m1_256fsi_s 0
#define reg_ckg_viva_ch_m1_256fsi_e 2
#define reg_ckg_viva_ch_m2_256fsi ckgen00(0x1210)
#define reg_ckg_viva_ch_m2_256fsi_s 0
#define reg_ckg_viva_ch_m2_256fsi_e 2
#define reg_ckg_viva_ch_m3_256fsi ckgen00(0x1214)
#define reg_ckg_viva_ch_m3_256fsi_s 0
#define reg_ckg_viva_ch_m3_256fsi_e 2
#define reg_ckg_viva_ch_m4_256fsi ckgen00(0x1218)
#define reg_ckg_viva_ch_m4_256fsi_s 0
#define reg_ckg_viva_ch_m4_256fsi_e 2
#define reg_ckg_viva_ch_m5_256fsi ckgen00(0x121C)
#define reg_ckg_viva_ch_m5_256fsi_s 0
#define reg_ckg_viva_ch_m5_256fsi_e 2
#define reg_ckg_viva_ch_m6_256fsi ckgen00(0x1220)
#define reg_ckg_viva_ch_m6_256fsi_s 0
#define reg_ckg_viva_ch_m6_256fsi_e 2
#define reg_ckg_viva_ch_m7_256fsi ckgen00(0x1224)
#define reg_ckg_viva_ch_m7_256fsi_s 0
#define reg_ckg_viva_ch_m7_256fsi_e 2
#define reg_ckg_viva_ch_m8_256fsi ckgen00(0x1228)
#define reg_ckg_viva_ch_m8_256fsi_s 0
#define reg_ckg_viva_ch_m8_256fsi_e 2
#define reg_ckg_viva_ch_m9_256fsi ckgen00(0x122C)
#define reg_ckg_viva_ch_m9_256fsi_s 0
#define reg_ckg_viva_ch_m9_256fsi_e 2
#define reg_ckg_viva_ch_m10_256fsi ckgen00(0x1230)
#define reg_ckg_viva_ch_m10_256fsi_s 0
#define reg_ckg_viva_ch_m10_256fsi_e 2
#define reg_ckg_viva_ch_m11_256fsi ckgen00(0x1234)
#define reg_ckg_viva_ch_m11_256fsi_s 0
#define reg_ckg_viva_ch_m11_256fsi_e 2
#define reg_ckg_viva_ch_m12_256fsi ckgen00(0x1238)
#define reg_ckg_viva_ch_m12_256fsi_s 0
#define reg_ckg_viva_ch_m12_256fsi_e 2
#define reg_ckg_viva_ch_m13_256fsi ckgen00(0x123C)
#define reg_ckg_viva_ch_m13_256fsi_s 0
#define reg_ckg_viva_ch_m13_256fsi_e 2
#define reg_ckg_viva_ch_m14_256fsi ckgen00(0x1240)
#define reg_ckg_viva_ch_m14_256fsi_s 0
#define reg_ckg_viva_ch_m14_256fsi_e 2
#define reg_ckg_viva_ch_m15_256fsi ckgen00(0x1244)
#define reg_ckg_viva_ch_m15_256fsi_s 0
#define reg_ckg_viva_ch_m15_256fsi_e 2
#define reg_ckg_viva_ch_m16_256fsi ckgen00(0x1248)
#define reg_ckg_viva_ch_m16_256fsi_s 0
#define reg_ckg_viva_ch_m16_256fsi_e 2
#define reg_ckg_viva_i2s_tdm_1x16tx32b_bclk ckgen00(0x124C)
#define reg_ckg_viva_i2s_tdm_1x16tx32b_bclk_s 0
#define reg_ckg_viva_i2s_tdm_1x16tx32b_bclk_e 4
#define reg_ckg_viva_i2s_tdm_1x16tx32b_bclk_to_pad ckgen00(0x1250)
#define reg_ckg_viva_i2s_tdm_1x16tx32b_bclk_to_pad_s 0
#define reg_ckg_viva_i2s_tdm_1x16tx32b_bclk_to_pad_e 2
#define reg_ckg_viva_i2s_tdm_1x16tx32b_fifo ckgen00(0x1254)
#define reg_ckg_viva_i2s_tdm_1x16tx32b_fifo_s 0
#define reg_ckg_viva_i2s_tdm_1x16tx32b_fifo_e 2
#define reg_ckg_viva_i2s_tdm_6x16tx32b_bclk ckgen00(0x1258)
#define reg_ckg_viva_i2s_tdm_6x16tx32b_bclk_s 0
#define reg_ckg_viva_i2s_tdm_6x16tx32b_bclk_e 4
#define reg_ckg_viva_i2s_tdm_6x16tx32b_bclk_to_pad ckgen00(0x125C)
#define reg_ckg_viva_i2s_tdm_6x16tx32b_bclk_to_pad_s 0
#define reg_ckg_viva_i2s_tdm_6x16tx32b_bclk_to_pad_e 2
#define reg_ckg_viva_i2s_tdm_6x16tx32b_fifo ckgen00(0x1260)
#define reg_ckg_viva_i2s_tdm_6x16tx32b_fifo_s 0
#define reg_ckg_viva_i2s_tdm_6x16tx32b_fifo_e 2
#define reg_ckg_viva_src_mac_bspline ckgen00(0x1264)
#define reg_ckg_viva_src_mac_bspline_s 0
#define reg_ckg_viva_src_mac_bspline_e 3
#define reg_ckg_disp_mfdec ckgen00(0x1268)
#define reg_ckg_disp_mfdec_s 0
#define reg_ckg_disp_mfdec_e 3
#define reg_ckg_disp_mfdec_gpu_nodie ckgen00(0x1268)
#define reg_ckg_disp_mfdec_gpu_nodie_s 8
#define reg_ckg_disp_mfdec_gpu_nodie_e 9
#define reg_ckg_disp_mfdec_scnr ckgen00(0x126C)
#define reg_ckg_disp_mfdec_scnr_s 0
#define reg_ckg_disp_mfdec_scnr_e 1
#define reg_ckg_gpd ckgen00(0x1270)
#define reg_ckg_gpd_s 0
#define reg_ckg_gpd_e 3
#define reg_ckg_gpd_mheg5 ckgen00(0x1270)
#define reg_ckg_gpd_mheg5_s 8
#define reg_ckg_gpd_mheg5_e 9
#define reg_ckg_njpd ckgen00(0x1278)
#define reg_ckg_njpd_s 0
#define reg_ckg_njpd_e 3
#define reg_ckg_njpd_tsp ckgen00(0x1278)
#define reg_ckg_njpd_tsp_s 8
#define reg_ckg_njpd_tsp_e 9
#define reg_ckg_vdec_lae ckgen00(0x1280)
#define reg_ckg_vdec_lae_s 0
#define reg_ckg_vdec_lae_e 4
#define reg_ckg_vdec_lae_slow ckgen00(0x1288)
#define reg_ckg_vdec_lae_slow_s 0
#define reg_ckg_vdec_lae_slow_e 4
#define reg_ckg_vdec_bus_vdec_soc ckgen00(0x1288)
#define reg_ckg_vdec_bus_vdec_soc_s 8
#define reg_ckg_vdec_bus_vdec_soc_e 9
#define reg_ckg_vdec_bus_vdec_core0 ckgen00(0x1288)
#define reg_ckg_vdec_bus_vdec_core0_s 10
#define reg_ckg_vdec_bus_vdec_core0_e 11
#define reg_ckg_vdec_bus_vdec_core1 ckgen00(0x1288)
#define reg_ckg_vdec_bus_vdec_core1_s 12
#define reg_ckg_vdec_bus_vdec_core1_e 13
#define reg_ckg_vdec_bus_vdec_core2 ckgen00(0x1288)
#define reg_ckg_vdec_bus_vdec_core2_s 14
#define reg_ckg_vdec_bus_vdec_core2_e 15
#define reg_ckg_vdec_sys ckgen00(0x1290)
#define reg_ckg_vdec_sys_s 0
#define reg_ckg_vdec_sys_e 4
#define reg_ckg_vdec_sys_vdec_soc ckgen00(0x1290)
#define reg_ckg_vdec_sys_vdec_soc_s 8
#define reg_ckg_vdec_sys_vdec_soc_e 9
#define reg_ckg_vdec_sys_vdec_core0 ckgen00(0x1290)
#define reg_ckg_vdec_sys_vdec_core0_s 10
#define reg_ckg_vdec_sys_vdec_core0_e 11
#define reg_ckg_vdec_sys_vdec_core1 ckgen00(0x1290)
#define reg_ckg_vdec_sys_vdec_core1_s 12
#define reg_ckg_vdec_sys_vdec_core1_e 13
#define reg_ckg_vdec_sys_vdec_core2 ckgen00(0x1290)
#define reg_ckg_vdec_sys_vdec_core2_s 14
#define reg_ckg_vdec_sys_vdec_core2_e 15
#define reg_ckg_vdec_sys_slow ckgen00(0x1298)
#define reg_ckg_vdec_sys_slow_s 0
#define reg_ckg_vdec_sys_slow_e 3
#define reg_ckg_vdec_lat0 ckgen00(0x12A0)
#define reg_ckg_vdec_lat0_s 0
#define reg_ckg_vdec_lat0_e 1
#define reg_ckg_vdec_lat1 ckgen00(0x12A8)
#define reg_ckg_vdec_lat1_s 0
#define reg_ckg_vdec_lat1_e 1
#define reg_ckg_gce_f26m ckgen00(0x12B0)
#define reg_ckg_gce_f26m_s 0
#define reg_ckg_gce_f26m_e 1
#define reg_ckg_xtal_24m_vdec_core0 ckgen00(0x12B8)
#define reg_ckg_xtal_24m_vdec_core0_s 0
#define reg_ckg_xtal_24m_vdec_core0_e 1
#define reg_ckg_xtal_24m_vdec_core1 ckgen00(0x12C0)
#define reg_ckg_xtal_24m_vdec_core1_s 0
#define reg_ckg_xtal_24m_vdec_core1_e 1
#define reg_ckg_xtal_24m_vdec_core2 ckgen00(0x12C8)
#define reg_ckg_xtal_24m_vdec_core2_s 0
#define reg_ckg_xtal_24m_vdec_core2_e 1
#define reg_sw_en_calc2calc_mcusys ckgen00(0x1400)
#define reg_sw_en_calc2calc_mcusys_s 1
#define reg_sw_en_calc2calc_mcusys_e 1
#define reg_sw_en_bridge2gpu_nodie ckgen00(0x1440)
#define reg_sw_en_bridge2gpu_nodie_s 0
#define reg_sw_en_bridge2gpu_nodie_e 0
#define reg_sw_en_gpu2gpu_die ckgen00(0x1444)
#define reg_sw_en_gpu2gpu_die_s 0
#define reg_sw_en_gpu2gpu_die_e 0
#define reg_sw_en_sc2shader ckgen00(0x1448)
#define reg_sw_en_sc2shader_s 0
#define reg_sw_en_sc2shader_e 0
#define reg_sw_en_xtal_12m2met ckgen00(0x144C)
#define reg_sw_en_xtal_12m2met_s 0
#define reg_sw_en_xtal_12m2met_e 0
#define reg_sw_en_xtal_24m2syscount ckgen00(0x1450)
#define reg_sw_en_xtal_24m2syscount_s 1
#define reg_sw_en_xtal_24m2syscount_e 1
#define reg_sw_en_xtal_24m2xtal ckgen00(0x1450)
#define reg_sw_en_xtal_24m2xtal_s 2
#define reg_sw_en_xtal_24m2xtal_e 2
#define reg_sw_en_bus_nodie2aiatop ckgen00(0x1460)
#define reg_sw_en_bus_nodie2aiatop_s 0
#define reg_sw_en_bus_nodie2aiatop_e 0
#define reg_sw_en_bus_nodie2smi ckgen00(0x1460)
#define reg_sw_en_bus_nodie2smi_s 1
#define reg_sw_en_bus_nodie2smi_e 1
#define reg_sw_en_xtal_24m2aiatop ckgen00(0x1464)
#define reg_sw_en_xtal_24m2aiatop_s 0
#define reg_sw_en_xtal_24m2aiatop_e 0
#define reg_sw_en_dramc0_cgclk_fast_cha2dramc0 ckgen00(0x1474)
#define reg_sw_en_dramc0_cgclk_fast_cha2dramc0_s 0
#define reg_sw_en_dramc0_cgclk_fast_cha2dramc0_e 0
#define reg_sw_en_dramc1_cgclk_fast_cha2dramc1 ckgen00(0x1478)
#define reg_sw_en_dramc1_cgclk_fast_cha2dramc1_s 0
#define reg_sw_en_dramc1_cgclk_fast_cha2dramc1_e 0
#define reg_sw_en_dramc2_cgclk_fast_cha2dramc2 ckgen00(0x147C)
#define reg_sw_en_dramc2_cgclk_fast_cha2dramc2_s 0
#define reg_sw_en_dramc2_cgclk_fast_cha2dramc2_e 0
#define reg_sw_en_occ_src_2162dramc0 ckgen00(0x1480)
#define reg_sw_en_occ_src_2162dramc0_s 0
#define reg_sw_en_occ_src_2162dramc0_e 0
#define reg_sw_en_occ_src_2162dramc1 ckgen00(0x1484)
#define reg_sw_en_occ_src_2162dramc1_s 0
#define reg_sw_en_occ_src_2162dramc1_e 0
#define reg_sw_en_occ_src_2162dramc2 ckgen00(0x1488)
#define reg_sw_en_occ_src_2162dramc2_s 0
#define reg_sw_en_occ_src_2162dramc2_e 0
#define reg_sw_en_xtal_24m2dramc0 ckgen00(0x148C)
#define reg_sw_en_xtal_24m2dramc0_s 0
#define reg_sw_en_xtal_24m2dramc0_e 0
#define reg_sw_en_xtal_24m2dramc1 ckgen00(0x1490)
#define reg_sw_en_xtal_24m2dramc1_s 0
#define reg_sw_en_xtal_24m2dramc1_e 0
#define reg_sw_en_xtal_24m2dramc2 ckgen00(0x1494)
#define reg_sw_en_xtal_24m2dramc2_s 0
#define reg_sw_en_xtal_24m2dramc2_e 0
#define reg_sw_en_emi0_deb2ip_wrap ckgen00(0x1498)
#define reg_sw_en_emi0_deb2ip_wrap_s 0
#define reg_sw_en_emi0_deb2ip_wrap_e 0
#define reg_sw_en_emi02ip_wrap ckgen00(0x149C)
#define reg_sw_en_emi02ip_wrap_s 0
#define reg_sw_en_emi02ip_wrap_e 0
#define reg_sw_en_emi1_deb2ip_wrap ckgen00(0x14A0)
#define reg_sw_en_emi1_deb2ip_wrap_s 0
#define reg_sw_en_emi1_deb2ip_wrap_e 0
#define reg_sw_en_emi12ip_wrap ckgen00(0x14A4)
#define reg_sw_en_emi12ip_wrap_s 0
#define reg_sw_en_emi12ip_wrap_e 0
#define reg_sw_en_emi2_deb2ip_wrap ckgen00(0x14A8)
#define reg_sw_en_emi2_deb2ip_wrap_s 0
#define reg_sw_en_emi2_deb2ip_wrap_e 0
#define reg_sw_en_emi22ip_wrap ckgen00(0x14AC)
#define reg_sw_en_emi22ip_wrap_s 0
#define reg_sw_en_emi22ip_wrap_e 0
#define reg_sw_en_emi22xpu ckgen00(0x14AC)
#define reg_sw_en_emi22xpu_s 1
#define reg_sw_en_emi22xpu_e 1
#define reg_sw_en_ip_wrap2ip_wrap ckgen00(0x14B0)
#define reg_sw_en_ip_wrap2ip_wrap_s 0
#define reg_sw_en_ip_wrap2ip_wrap_e 0
#define reg_sw_en_xtal_12m2ip_wrap ckgen00(0x14B4)
#define reg_sw_en_xtal_12m2ip_wrap_s 0
#define reg_sw_en_xtal_12m2ip_wrap_e 0
#define reg_sw_en_xtal_24m2ip_wrap ckgen00(0x14B8)
#define reg_sw_en_xtal_24m2ip_wrap_s 0
#define reg_sw_en_xtal_24m2ip_wrap_e 0
#define reg_sw_en_smi2aia_smi ckgen00(0x14E4)
#define reg_sw_en_smi2aia_smi_s 0
#define reg_sw_en_smi2aia_smi_e 0
#define reg_sw_en_smi2audio_r2 ckgen00(0x14E4)
#define reg_sw_en_smi2audio_r2_s 1
#define reg_sw_en_smi2audio_r2_e 1
#define reg_sw_en_smi2cmdq ckgen00(0x14E4)
#define reg_sw_en_smi2cmdq_s 2
#define reg_sw_en_smi2cmdq_e 2
#define reg_sw_en_smi2core0 ckgen00(0x14E4)
#define reg_sw_en_smi2core0_s 3
#define reg_sw_en_smi2core0_e 3
#define reg_sw_en_smi2core1 ckgen00(0x14E4)
#define reg_sw_en_smi2core1_s 4
#define reg_sw_en_smi2core1_e 4
#define reg_sw_en_smi2core2 ckgen00(0x14E4)
#define reg_sw_en_smi2core2_s 5
#define reg_sw_en_smi2core2_e 5
#define reg_sw_en_smi2smi_demod0 ckgen00(0x14E4)
#define reg_sw_en_smi2smi_demod0_s 6
#define reg_sw_en_smi2smi_demod0_e 6
#define reg_sw_en_smi2dscrmb ckgen00(0x14E4)
#define reg_sw_en_smi2dscrmb_s 7
#define reg_sw_en_smi2dscrmb_e 7
#define reg_sw_en_smi2frciopmrv55 ckgen00(0x14E4)
#define reg_sw_en_smi2frciopmrv55_s 9
#define reg_sw_en_smi2frciopmrv55_e 9
#define reg_sw_en_smi2frcmehalo ckgen00(0x14E4)
#define reg_sw_en_smi2frcmehalo_s 10
#define reg_sw_en_smi2frcmehalo_e 10
#define reg_sw_en_smi2ge ckgen00(0x14E4)
#define reg_sw_en_smi2ge_s 11
#define reg_sw_en_smi2ge_e 11
#define reg_sw_en_smi2gmac ckgen00(0x14E4)
#define reg_sw_en_smi2gmac_s 12
#define reg_sw_en_smi2gmac_e 12
#define reg_sw_en_smi2gpd ckgen00(0x14E4)
#define reg_sw_en_smi2gpd_s 13
#define reg_sw_en_smi2gpd_e 13
#define reg_sw_en_smi2jpd ckgen00(0x14E4)
#define reg_sw_en_smi2jpd_s 15
#define reg_sw_en_smi2jpd_e 15
#define reg_sw_en_smi2mac ckgen00(0x14E8)
#define reg_sw_en_smi2mac_s 0
#define reg_sw_en_smi2mac_e 0
#define reg_sw_en_smi2mcu_bdma ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_bdma_s 1
#define reg_sw_en_smi2mcu_bdma_e 1
#define reg_sw_en_smi2mcu_demura ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_demura_s 2
#define reg_sw_en_smi2mcu_demura_e 2
#define reg_sw_en_smi2mcu_fuart ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_fuart_s 3
#define reg_sw_en_smi2mcu_fuart_e 3
#define reg_sw_en_smi2mcu_m2mcu ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_m2mcu_s 4
#define reg_sw_en_smi2mcu_m2mcu_e 4
#define reg_sw_en_smi2mcu_miic0 ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_miic0_s 5
#define reg_sw_en_smi2mcu_miic0_e 5
#define reg_sw_en_smi2mcu_miic1 ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_miic1_s 6
#define reg_sw_en_smi2mcu_miic1_e 6
#define reg_sw_en_smi2mcu_miic2 ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_miic2_s 7
#define reg_sw_en_smi2mcu_miic2_e 7
#define reg_sw_en_smi2mcu_miic3 ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_miic3_s 8
#define reg_sw_en_smi2mcu_miic3_e 8
#define reg_sw_en_smi2mcu_xd2miu ckgen00(0x14E8)
#define reg_sw_en_smi2mcu_xd2miu_s 9
#define reg_sw_en_smi2mcu_xd2miu_e 9
#define reg_sw_en_smi2mheg5_smi ckgen00(0x14E8)
#define reg_sw_en_smi2mheg5_smi_s 10
#define reg_sw_en_smi2mheg5_smi_e 10
#define reg_sw_en_smi2rv55audio ckgen00(0x14E8)
#define reg_sw_en_smi2rv55audio_s 11
#define reg_sw_en_smi2rv55audio_e 11
#define reg_sw_en_smi2rv55frc ckgen00(0x14E8)
#define reg_sw_en_smi2rv55frc_s 12
#define reg_sw_en_smi2rv55frc_e 12
#define reg_sw_en_smi2rv55pqu ckgen00(0x14E8)
#define reg_sw_en_smi2rv55pqu_s 13
#define reg_sw_en_smi2rv55pqu_e 13
#define reg_sw_en_smi2scace ckgen00(0x14E8)
#define reg_sw_en_smi2scace_s 14
#define reg_sw_en_smi2scace_e 14
#define reg_sw_en_smi2scdv ckgen00(0x14E8)
#define reg_sw_en_smi2scdv_s 15
#define reg_sw_en_smi2scdv_e 15
#define reg_sw_en_smi2scip ckgen00(0x14EC)
#define reg_sw_en_smi2scip_s 0
#define reg_sw_en_smi2scip_e 0
#define reg_sw_en_smi2scm ckgen00(0x14EC)
#define reg_sw_en_smi2scm_s 1
#define reg_sw_en_smi2scm_e 1
#define reg_sw_en_smi2scmo ckgen00(0x14EC)
#define reg_sw_en_smi2scmo_s 2
#define reg_sw_en_smi2scmo_e 2
#define reg_sw_en_smi2scmw ckgen00(0x14EC)
#define reg_sw_en_smi2scmw_s 3
#define reg_sw_en_smi2scmw_e 3
#define reg_sw_en_smi2scnr ckgen00(0x14EC)
#define reg_sw_en_smi2scnr_s 4
#define reg_sw_en_smi2scnr_e 4
#define reg_sw_en_smi2scpq ckgen00(0x14EC)
#define reg_sw_en_smi2scpq_s 5
#define reg_sw_en_smi2scpq_e 5
#define reg_sw_en_smi2scscl ckgen00(0x14EC)
#define reg_sw_en_smi2scscl_s 6
#define reg_sw_en_smi2scscl_e 6
#define reg_sw_en_smi2scsr ckgen00(0x14EC)
#define reg_sw_en_smi2scsr_s 7
#define reg_sw_en_smi2scsr_e 7
#define reg_sw_en_smi2sctcon ckgen00(0x14EC)
#define reg_sw_en_smi2sctcon_s 8
#define reg_sw_en_smi2sctcon_e 8
#define reg_sw_en_smi2smi ckgen00(0x14EC)
#define reg_sw_en_smi2smi_s 9
#define reg_sw_en_smi2smi_e 9
#define reg_sw_en_smi2soc ckgen00(0x14EC)
#define reg_sw_en_smi2soc_s 10
#define reg_sw_en_smi2soc_e 10
#define reg_sw_en_smi2ssusb ckgen00(0x14EC)
#define reg_sw_en_smi2ssusb_s 11
#define reg_sw_en_smi2ssusb_e 11
#define reg_sw_en_smi2tso ckgen00(0x14EC)
#define reg_sw_en_smi2tso_s 12
#define reg_sw_en_smi2tso_e 12
#define reg_sw_en_smi2tso2 ckgen00(0x14EC)
#define reg_sw_en_smi2tso2_s 13
#define reg_sw_en_smi2tso2_e 13
#define reg_sw_en_smi2tsp ckgen00(0x14EC)
#define reg_sw_en_smi2tsp_s 14
#define reg_sw_en_smi2tsp_e 14
#define reg_sw_en_smi2vd ckgen00(0x14EC)
#define reg_sw_en_smi2vd_s 15
#define reg_sw_en_smi2vd_e 15
#define reg_sw_en_smi2vd_pes_parser ckgen00(0x14F0)
#define reg_sw_en_smi2vd_pes_parser_s 0
#define reg_sw_en_smi2vd_pes_parser_e 0
#define reg_sw_en_smi2smi_larb_scmw ckgen00(0x14F0)
#define reg_sw_en_smi2smi_larb_scmw_s 1
#define reg_sw_en_smi2smi_larb_scmw_e 1
#define reg_sw_en_smi2larb_tsp ckgen00(0x14F0)
#define reg_sw_en_smi2larb_tsp_s 2
#define reg_sw_en_smi2larb_tsp_e 2
#define reg_sw_en_smi_aesdma2dscrmb ckgen00(0x14F0)
#define reg_sw_en_smi_aesdma2dscrmb_s 3
#define reg_sw_en_smi_aesdma2dscrmb_e 3
#define reg_sw_en_smi_tsp2tsp ckgen00(0x14F0)
#define reg_sw_en_smi_tsp2tsp_s 4
#define reg_sw_en_smi_tsp2tsp_e 4
#define reg_sw_en_smi_fcie2fcie ckgen00(0x14F0)
#define reg_sw_en_smi_fcie2fcie_s 5
#define reg_sw_en_smi_fcie2fcie_e 5
#define reg_sw_en_smi_uhc2uhc ckgen00(0x14F0)
#define reg_sw_en_smi_uhc2uhc_s 6
#define reg_sw_en_smi_uhc2uhc_e 6
#define reg_sw_en_viva_smi2smi ckgen00(0x14F0)
#define reg_sw_en_viva_smi2smi_s 7
#define reg_sw_en_viva_smi2smi_e 7
#define reg_sw_en_smi2demod0 ckgen00(0x14F0)
#define reg_sw_en_smi2demod0_s 8
#define reg_sw_en_smi2demod0_e 8
#define reg_sw_en_smi2demod0_dvbtm ckgen00(0x14F0)
#define reg_sw_en_smi2demod0_dvbtm_s 9
#define reg_sw_en_smi2demod0_dvbtm_e 9
#define reg_sw_en_smi2demod0_isdbt ckgen00(0x14F0)
#define reg_sw_en_smi2demod0_isdbt_s 10
#define reg_sw_en_smi2demod0_isdbt_e 10
#define reg_sw_en_smi2demod0_dtmb ckgen00(0x14F0)
#define reg_sw_en_smi2demod0_dtmb_s 11
#define reg_sw_en_smi2demod0_dtmb_e 11
#define reg_sw_en_smi2demod0_adc_dump ckgen00(0x14F0)
#define reg_sw_en_smi2demod0_adc_dump_s 12
#define reg_sw_en_smi2demod0_adc_dump_e 12
#define reg_sw_en_smi2mcu_mspi0 ckgen00(0x14F0)
#define reg_sw_en_smi2mcu_mspi0_s 13
#define reg_sw_en_smi2mcu_mspi0_e 13
#define reg_sw_en_smi2mcu_mspi1 ckgen00(0x14F0)
#define reg_sw_en_smi2mcu_mspi1_s 14
#define reg_sw_en_smi2mcu_mspi1_e 14
#define reg_sw_en_smi2mcu_mspi2 ckgen00(0x14F0)
#define reg_sw_en_smi2mcu_mspi2_s 15
#define reg_sw_en_smi2mcu_mspi2_e 15
#define reg_sw_en_smi2mcu_mspi3 ckgen00(0x14F4)
#define reg_sw_en_smi2mcu_mspi3_s 0
#define reg_sw_en_smi2mcu_mspi3_e 0
#define reg_sw_en_smi2mcu_mspi4 ckgen00(0x14F4)
#define reg_sw_en_smi2mcu_mspi4_s 1
#define reg_sw_en_smi2mcu_mspi4_e 1
#define reg_sw_en_smi2mcu_mspi5 ckgen00(0x14F4)
#define reg_sw_en_smi2mcu_mspi5_s 2
#define reg_sw_en_smi2mcu_mspi5_e 2
#define reg_sw_en_smi2mcu_mspi6 ckgen00(0x14F4)
#define reg_sw_en_smi2mcu_mspi6_s 3
#define reg_sw_en_smi2mcu_mspi6_e 3
#define reg_sw_en_smi2mcu_mspi7 ckgen00(0x14F4)
#define reg_sw_en_smi2mcu_mspi7_s 4
#define reg_sw_en_smi2mcu_mspi7_e 4
#define reg_sw_en_smi2mcu_mspi_cilink ckgen00(0x14F4)
#define reg_sw_en_smi2mcu_mspi_cilink_s 5
#define reg_sw_en_smi2mcu_mspi_cilink_e 5
#define reg_sw_en_smi2pextp ckgen00(0x14F4)
#define reg_sw_en_smi2pextp_s 6
#define reg_sw_en_smi2pextp_e 6
#define reg_sw_en_smi2ufs ckgen00(0x14F4)
#define reg_sw_en_smi2ufs_s 7
#define reg_sw_en_smi2ufs_e 7
#define reg_sw_en_frc_imi2frciopm ckgen00(0x1520)
#define reg_sw_en_frc_imi2frciopm_s 0
#define reg_sw_en_frc_imi2frciopm_e 0
#define reg_sw_en_frc_imi2frciopmrv55 ckgen00(0x1520)
#define reg_sw_en_frc_imi2frciopmrv55_s 1
#define reg_sw_en_frc_imi2frciopmrv55_e 1
#define reg_sw_en_frc_imi2rv55frc ckgen00(0x1520)
#define reg_sw_en_frc_imi2rv55frc_s 2
#define reg_sw_en_frc_imi2rv55frc_e 2
#define reg_sw_en_frc_imi2rv55pqu ckgen00(0x1520)
#define reg_sw_en_frc_imi2rv55pqu_s 3
#define reg_sw_en_frc_imi2rv55pqu_e 3
#define reg_sw_en_imi2share_sram_imi ckgen00(0x1524)
#define reg_sw_en_imi2share_sram_imi_s 0
#define reg_sw_en_imi2share_sram_imi_e 0
#define reg_sw_en_imi2ufs ckgen00(0x1524)
#define reg_sw_en_imi2ufs_s 1
#define reg_sw_en_imi2ufs_e 1
#define reg_sw_en_imi2tsp ckgen00(0x1524)
#define reg_sw_en_imi2tsp_s 2
#define reg_sw_en_imi2tsp_e 2
#define reg_sw_en_xtal_12m2codec_riu_bridge_top ckgen00(0x153C)
#define reg_sw_en_xtal_12m2codec_riu_bridge_top_s 0
#define reg_sw_en_xtal_12m2codec_riu_bridge_top_e 0
#define reg_sw_en_xtal_12m2dig_dft_dummy ckgen00(0x153C)
#define reg_sw_en_xtal_12m2dig_dft_dummy_s 2
#define reg_sw_en_xtal_12m2dig_dft_dummy_e 2
#define reg_sw_en_xtal_12m2mcu_bdma ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_bdma_s 3
#define reg_sw_en_xtal_12m2mcu_bdma_e 3
#define reg_sw_en_xtal_12m2mcu_demura ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_demura_s 4
#define reg_sw_en_xtal_12m2mcu_demura_e 4
#define reg_sw_en_xtal_12m2mcu_fuart ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_fuart_s 5
#define reg_sw_en_xtal_12m2mcu_fuart_e 5
#define reg_sw_en_xtal_12m2mcu_m2mcu ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_m2mcu_s 6
#define reg_sw_en_xtal_12m2mcu_m2mcu_e 6
#define reg_sw_en_xtal_12m2mcu_m2riu ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_m2riu_s 7
#define reg_sw_en_xtal_12m2mcu_m2riu_e 7
#define reg_sw_en_xtal_12m2mcu_mcuif ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_mcuif_s 8
#define reg_sw_en_xtal_12m2mcu_mcuif_e 8
#define reg_sw_en_xtal_12m2mcu_miic0 ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_miic0_s 9
#define reg_sw_en_xtal_12m2mcu_miic0_e 9
#define reg_sw_en_xtal_12m2mcu_miic1 ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_miic1_s 10
#define reg_sw_en_xtal_12m2mcu_miic1_e 10
#define reg_sw_en_xtal_12m2mcu_miic2 ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_miic2_s 11
#define reg_sw_en_xtal_12m2mcu_miic2_e 11
#define reg_sw_en_xtal_12m2mcu_miic3 ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_miic3_s 12
#define reg_sw_en_xtal_12m2mcu_miic3_e 12
#define reg_sw_en_xtal_12m2mcu_xd2miu ckgen00(0x153C)
#define reg_sw_en_xtal_12m2mcu_xd2miu_s 13
#define reg_sw_en_xtal_12m2mcu_xd2miu_e 13
#define reg_sw_en_xtal_12m2pad_top ckgen00(0x153C)
#define reg_sw_en_xtal_12m2pad_top_s 14
#define reg_sw_en_xtal_12m2pad_top_e 14
#define reg_sw_en_xtal_12m2prearb2pmriu ckgen00(0x153C)
#define reg_sw_en_xtal_12m2prearb2pmriu_s 15
#define reg_sw_en_xtal_12m2prearb2pmriu_e 15
#define reg_sw_en_xtal_12m2riu_bridge_top ckgen00(0x1540)
#define reg_sw_en_xtal_12m2riu_bridge_top_s 0
#define reg_sw_en_xtal_12m2riu_bridge_top_e 0
#define reg_sw_en_xtal_12m2secure_top_nonpm ckgen00(0x1540)
#define reg_sw_en_xtal_12m2secure_top_nonpm_s 1
#define reg_sw_en_xtal_12m2secure_top_nonpm_e 1
#define reg_sw_en_xtal_12m2test_clk_calculate ckgen00(0x1540)
#define reg_sw_en_xtal_12m2test_clk_calculate_s 2
#define reg_sw_en_xtal_12m2test_clk_calculate_e 2
#define reg_sw_en_xtal_12m2test_ctrl ckgen00(0x1540)
#define reg_sw_en_xtal_12m2test_ctrl_s 3
#define reg_sw_en_xtal_12m2test_ctrl_e 3
#define reg_sw_en_xtal_12m2vd ckgen00(0x1540)
#define reg_sw_en_xtal_12m2vd_s 4
#define reg_sw_en_xtal_12m2vd_e 4
#define reg_sw_en_xtal_12m2mcu_mspi0 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi0_s 5
#define reg_sw_en_xtal_12m2mcu_mspi0_e 5
#define reg_sw_en_xtal_12m2mcu_mspi1 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi1_s 6
#define reg_sw_en_xtal_12m2mcu_mspi1_e 6
#define reg_sw_en_xtal_12m2mcu_mspi2 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi2_s 7
#define reg_sw_en_xtal_12m2mcu_mspi2_e 7
#define reg_sw_en_xtal_12m2mcu_mspi3 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi3_s 8
#define reg_sw_en_xtal_12m2mcu_mspi3_e 8
#define reg_sw_en_xtal_12m2mcu_mspi4 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi4_s 9
#define reg_sw_en_xtal_12m2mcu_mspi4_e 9
#define reg_sw_en_xtal_12m2mcu_mspi5 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi5_s 10
#define reg_sw_en_xtal_12m2mcu_mspi5_e 10
#define reg_sw_en_xtal_12m2mcu_mspi6 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi6_s 11
#define reg_sw_en_xtal_12m2mcu_mspi6_e 11
#define reg_sw_en_xtal_12m2mcu_mspi7 ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi7_s 12
#define reg_sw_en_xtal_12m2mcu_mspi7_e 12
#define reg_sw_en_xtal_12m2mcu_mspi_cilink ckgen00(0x1540)
#define reg_sw_en_xtal_12m2mcu_mspi_cilink_s 13
#define reg_sw_en_xtal_12m2mcu_mspi_cilink_e 13
#define reg_sw_en_xtal_24m2dmd_rst_ctrl ckgen00(0x1558)
#define reg_sw_en_xtal_24m2dmd_rst_ctrl_s 0
#define reg_sw_en_xtal_24m2dmd_rst_ctrl_e 0
#define reg_sw_en_xtal_24m2dscrmb ckgen00(0x1558)
#define reg_sw_en_xtal_24m2dscrmb_s 1
#define reg_sw_en_xtal_24m2dscrmb_e 1
#define reg_sw_en_xtal_24m2gmac ckgen00(0x1558)
#define reg_sw_en_xtal_24m2gmac_s 2
#define reg_sw_en_xtal_24m2gmac_e 2
#define reg_sw_en_xtal_24m2pextp ckgen00(0x1558)
#define reg_sw_en_xtal_24m2pextp_s 4
#define reg_sw_en_xtal_24m2pextp_e 4
#define reg_sw_en_xtal_24m2ssusb ckgen00(0x1558)
#define reg_sw_en_xtal_24m2ssusb_s 5
#define reg_sw_en_xtal_24m2ssusb_e 5
#define reg_sw_en_xtal_24m2top ckgen00(0x1558)
#define reg_sw_en_xtal_24m2top_s 6
#define reg_sw_en_xtal_24m2top_e 6
#define reg_sw_en_xtal_24m2usb20 ckgen00(0x1558)
#define reg_sw_en_xtal_24m2usb20_s 8
#define reg_sw_en_xtal_24m2usb20_e 8
#define reg_sw_en_adcd_i_in_div22dmd_ana ckgen00(0x1578)
#define reg_sw_en_adcd_i_in_div22dmd_ana_s 0
#define reg_sw_en_adcd_i_in_div22dmd_ana_e 0
#define reg_sw_en_dvbtc_adc_i_p2dmd_ana ckgen00(0x157C)
#define reg_sw_en_dvbtc_adc_i_p2dmd_ana_s 0
#define reg_sw_en_dvbtc_adc_i_p2dmd_ana_e 0
#define reg_sw_en_dvbtc_adc_q_p2dmd_ana ckgen00(0x1580)
#define reg_sw_en_dvbtc_adc_q_p2dmd_ana_s 0
#define reg_sw_en_dvbtc_adc_q_p2dmd_ana_e 0
#define reg_sw_en_acifir2demod0 ckgen00(0x1584)
#define reg_sw_en_acifir2demod0_s 0
#define reg_sw_en_acifir2demod0_e 0
#define reg_sw_en_adcd_i_in2dmd_ana ckgen00(0x1588)
#define reg_sw_en_adcd_i_in2dmd_ana_s 0
#define reg_sw_en_adcd_i_in2dmd_ana_e 0
#define reg_sw_en_adcd_i_out2dmd_ana ckgen00(0x158C)
#define reg_sw_en_adcd_i_out2dmd_ana_s 0
#define reg_sw_en_adcd_i_out2dmd_ana_e 0
#define reg_sw_en_adcd_q_in2dmd_ana ckgen00(0x1590)
#define reg_sw_en_adcd_q_in2dmd_ana_s 0
#define reg_sw_en_adcd_q_in2dmd_ana_e 0
#define reg_sw_en_adcd_q_out2dmd_ana ckgen00(0x1594)
#define reg_sw_en_adcd_q_out2dmd_ana_s 0
#define reg_sw_en_adcd_q_out2dmd_ana_e 0
#define reg_sw_en_adcd2demod0 ckgen00(0x1598)
#define reg_sw_en_adcd2demod0_s 0
#define reg_sw_en_adcd2demod0_e 0
#define reg_sw_en_atsc_adcd_sync2demod0 ckgen00(0x159C)
#define reg_sw_en_atsc_adcd_sync2demod0_s 0
#define reg_sw_en_atsc_adcd_sync2demod0_e 0
#define reg_sw_en_atsc_ce252demod0 ckgen00(0x15A0)
#define reg_sw_en_atsc_ce252demod0_s 0
#define reg_sw_en_atsc_ce252demod0_e 0
#define reg_sw_en_atsc_eq252demod0 ckgen00(0x15A4)
#define reg_sw_en_atsc_eq252demod0_s 0
#define reg_sw_en_atsc_eq252demod0_e 0
#define reg_sw_en_atsc200_ph12demod0 ckgen00(0x15A8)
#define reg_sw_en_atsc200_ph12demod0_s 0
#define reg_sw_en_atsc200_ph12demod0_e 0
#define reg_sw_en_atsc200_ph32demod0 ckgen00(0x15AC)
#define reg_sw_en_atsc200_ph32demod0_s 0
#define reg_sw_en_atsc200_ph32demod0_e 0
#define reg_sw_en_atsc252demod0 ckgen00(0x15B0)
#define reg_sw_en_atsc252demod0_s 0
#define reg_sw_en_atsc252demod0_e 0
#define reg_sw_en_atsc4002demod0 ckgen00(0x15B4)
#define reg_sw_en_atsc4002demod0_s 0
#define reg_sw_en_atsc4002demod0_e 0
#define reg_sw_en_atsc502demod0 ckgen00(0x15B8)
#define reg_sw_en_atsc502demod0_s 0
#define reg_sw_en_atsc502demod0_e 0
#define reg_sw_en_dec_xtal_i2dmd_ana ckgen00(0x15BC)
#define reg_sw_en_dec_xtal_i2dmd_ana_s 0
#define reg_sw_en_dec_xtal_i2dmd_ana_e 0
#define reg_sw_en_dec_xtal_q2dmd_ana ckgen00(0x15C0)
#define reg_sw_en_dec_xtal_q2dmd_ana_s 0
#define reg_sw_en_dec_xtal_q2dmd_ana_e 0
#define reg_sw_en_deinter2demod1 ckgen00(0x15C4)
#define reg_sw_en_deinter2demod1_s 0
#define reg_sw_en_deinter2demod1_e 0
#define reg_sw_en_demod_864m2clk_vif_ssc_div ckgen00(0x15C8)
#define reg_sw_en_demod_864m2clk_vif_ssc_div_s 0
#define reg_sw_en_demod_864m2clk_vif_ssc_div_e 0
#define reg_sw_en_demod_adc_int2dmd_rst_ctrl ckgen00(0x15CC)
#define reg_sw_en_demod_adc_int2dmd_rst_ctrl_s 0
#define reg_sw_en_demod_adc_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmd_dma2demod0 ckgen00(0x15D0)
#define reg_sw_en_dmd_dma2demod0_s 0
#define reg_sw_en_dmd_dma2demod0_e 0
#define reg_sw_en_dmplldiv10_int2dmd_rst_ctrl ckgen00(0x15D4)
#define reg_sw_en_dmplldiv10_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv10_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv17_int2dmd_rst_ctrl ckgen00(0x15D8)
#define reg_sw_en_dmplldiv17_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv17_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv2_atsc_int2dmd_rst_ctrl ckgen00(0x15DC)
#define reg_sw_en_dmplldiv2_atsc_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv2_atsc_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv2_dtmb_int2dmd_rst_ctrl ckgen00(0x15E0)
#define reg_sw_en_dmplldiv2_dtmb_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv2_dtmb_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv2_int2dmd_rst_ctrl ckgen00(0x15E4)
#define reg_sw_en_dmplldiv2_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv2_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv3_dtmb_int2dmd_rst_ctrl ckgen00(0x15E8)
#define reg_sw_en_dmplldiv3_dtmb_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv3_dtmb_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv3_dvbc_int2dmd_rst_ctrl ckgen00(0x15EC)
#define reg_sw_en_dmplldiv3_dvbc_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv3_dvbc_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv3_dvbt2_int2dmd_rst_ctrl ckgen00(0x15F0)
#define reg_sw_en_dmplldiv3_dvbt2_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv3_dvbt2_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv3_int2dmd_rst_ctrl ckgen00(0x15F4)
#define reg_sw_en_dmplldiv3_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv3_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv3_isdbt_int2dmd_rst_ctrl ckgen00(0x15F8)
#define reg_sw_en_dmplldiv3_isdbt_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv3_isdbt_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv3_isdbt_outer_rs_m_over_n_int2dmd_rst_ctrl ckgen00(0x15FC)
#define reg_sw_en_dmplldiv3_isdbt_outer_rs_m_over_n_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv3_isdbt_outer_rs_m_over_n_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv4_dvb_oppro_m_over_n_int2dmd_rst_ctrl ckgen00(0x1600)
#define reg_sw_en_dmplldiv4_dvb_oppro_m_over_n_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv4_dvb_oppro_m_over_n_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv4_dvbs2_bch_m_over_n_int2dmd_rst_ctrl ckgen00(0x1604)
#define reg_sw_en_dmplldiv4_dvbs2_bch_m_over_n_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv4_dvbs2_bch_m_over_n_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv4_dvbtc_rs_m_over_n_int2dmd_rst_ctrl ckgen00(0x1608)
#define reg_sw_en_dmplldiv4_dvbtc_rs_m_over_n_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv4_dvbtc_rs_m_over_n_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv4_int2dmd_rst_ctrl ckgen00(0x160C)
#define reg_sw_en_dmplldiv4_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv4_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dmplldiv5_int2dmd_rst_ctrl ckgen00(0x1610)
#define reg_sw_en_dmplldiv5_int2dmd_rst_ctrl_s 0
#define reg_sw_en_dmplldiv5_int2dmd_rst_ctrl_e 0
#define reg_sw_en_dtmb_adc2demod0 ckgen00(0x1614)
#define reg_sw_en_dtmb_adc2demod0_s 0
#define reg_sw_en_dtmb_adc2demod0_e 0
#define reg_sw_en_dtmb_bch2demod0 ckgen00(0x1618)
#define reg_sw_en_dtmb_bch2demod0_s 0
#define reg_sw_en_dtmb_bch2demod0_e 0
#define reg_sw_en_dtmb_bch2demod1 ckgen00(0x161C)
#define reg_sw_en_dtmb_bch2demod1_s 0
#define reg_sw_en_dtmb_bch2demod1_e 0
#define reg_sw_en_dtmb_eq0p25x2demod0 ckgen00(0x1620)
#define reg_sw_en_dtmb_eq0p25x2demod0_s 0
#define reg_sw_en_dtmb_eq0p25x2demod0_e 0
#define reg_sw_en_dtmb_eq0p5x2demod0 ckgen00(0x1624)
#define reg_sw_en_dtmb_eq0p5x2demod0_s 0
#define reg_sw_en_dtmb_eq0p5x2demod0_e 0
#define reg_sw_en_dtmb_eq1x2demod0 ckgen00(0x1628)
#define reg_sw_en_dtmb_eq1x2demod0_s 0
#define reg_sw_en_dtmb_eq1x2demod0_e 0
#define reg_sw_en_dtmb_eq2x_inner12x2demod0 ckgen00(0x162C)
#define reg_sw_en_dtmb_eq2x_inner12x2demod0_s 0
#define reg_sw_en_dtmb_eq2x_inner12x2demod0_e 0
#define reg_sw_en_dtmb_eq2x_inner2x_12x2demod0 ckgen00(0x1630)
#define reg_sw_en_dtmb_eq2x_inner2x_12x2demod0_s 0
#define reg_sw_en_dtmb_eq2x_inner2x_12x2demod0_e 0
#define reg_sw_en_dtmb_eq2x_inner4x2demod0 ckgen00(0x1634)
#define reg_sw_en_dtmb_eq2x_inner4x2demod0_s 0
#define reg_sw_en_dtmb_eq2x_inner4x2demod0_e 0
#define reg_sw_en_dtmb_eq2x2demod0 ckgen00(0x1638)
#define reg_sw_en_dtmb_eq2x2demod0_s 0
#define reg_sw_en_dtmb_eq2x2demod0_e 0
#define reg_sw_en_dtmb_inner12x_eq0p25x2demod0 ckgen00(0x163C)
#define reg_sw_en_dtmb_inner12x_eq0p25x2demod0_s 0
#define reg_sw_en_dtmb_inner12x_eq0p25x2demod0_e 0
#define reg_sw_en_dtmb_inner12x_inner4x2demod0 ckgen00(0x1640)
#define reg_sw_en_dtmb_inner12x_inner4x2demod0_s 0
#define reg_sw_en_dtmb_inner12x_inner4x2demod0_e 0
#define reg_sw_en_dtmb_inner12x_inner6x2demod0 ckgen00(0x1644)
#define reg_sw_en_dtmb_inner12x_inner6x2demod0_s 0
#define reg_sw_en_dtmb_inner12x_inner6x2demod0_e 0
#define reg_sw_en_dtmb_inner12x_inner8x_tap_com2demod0 ckgen00(0x1648)
#define reg_sw_en_dtmb_inner12x_inner8x_tap_com2demod0_s 0
#define reg_sw_en_dtmb_inner12x_inner8x_tap_com2demod0_e 0
#define reg_sw_en_dtmb_inner12x2demod0 ckgen00(0x164C)
#define reg_sw_en_dtmb_inner12x2demod0_s 0
#define reg_sw_en_dtmb_inner12x2demod0_e 0
#define reg_sw_en_dtmb_inner1x_atsc252demod0 ckgen00(0x1650)
#define reg_sw_en_dtmb_inner1x_atsc252demod0_s 0
#define reg_sw_en_dtmb_inner1x_atsc252demod0_e 0
#define reg_sw_en_dtmb_inner1x2demod0 ckgen00(0x1654)
#define reg_sw_en_dtmb_inner1x2demod0_s 0
#define reg_sw_en_dtmb_inner1x2demod0_e 0
#define reg_sw_en_dtmb_inner24x_atsc_4002demod0 ckgen00(0x1658)
#define reg_sw_en_dtmb_inner24x_atsc_4002demod0_s 0
#define reg_sw_en_dtmb_inner24x_atsc_4002demod0_e 0
#define reg_sw_en_dtmb_inner24x2demod0 ckgen00(0x165C)
#define reg_sw_en_dtmb_inner24x2demod0_s 0
#define reg_sw_en_dtmb_inner24x2demod0_e 0
#define reg_sw_en_dtmb_inner2x_4x_sr1x2demod0 ckgen00(0x1660)
#define reg_sw_en_dtmb_inner2x_4x_sr1x2demod0_s 0
#define reg_sw_en_dtmb_inner2x_4x_sr1x2demod0_e 0
#define reg_sw_en_dtmb_inner2x_sr0p5x2demod0 ckgen00(0x1664)
#define reg_sw_en_dtmb_inner2x_sr0p5x2demod0_s 0
#define reg_sw_en_dtmb_inner2x_sr0p5x2demod0_e 0
#define reg_sw_en_dtmb_inner2x2demod0 ckgen00(0x1668)
#define reg_sw_en_dtmb_inner2x2demod0_s 0
#define reg_sw_en_dtmb_inner2x2demod0_e 0
#define reg_sw_en_dtmb_inner4x_atsc502demod0 ckgen00(0x166C)
#define reg_sw_en_dtmb_inner4x_atsc502demod0_s 0
#define reg_sw_en_dtmb_inner4x_atsc502demod0_e 0
#define reg_sw_en_dtmb_inner4x_sr1x2demod0 ckgen00(0x1670)
#define reg_sw_en_dtmb_inner4x_sr1x2demod0_s 0
#define reg_sw_en_dtmb_inner4x_sr1x2demod0_e 0
#define reg_sw_en_dtmb_inner4x2demod0 ckgen00(0x1674)
#define reg_sw_en_dtmb_inner4x2demod0_s 0
#define reg_sw_en_dtmb_inner4x2demod0_e 0
#define reg_sw_en_dtmb_inner6x2demod0 ckgen00(0x1678)
#define reg_sw_en_dtmb_inner6x2demod0_s 0
#define reg_sw_en_dtmb_inner6x2demod0_e 0
#define reg_sw_en_dtmb_inner8x_tap_com2demod0 ckgen00(0x167C)
#define reg_sw_en_dtmb_inner8x_tap_com2demod0_s 0
#define reg_sw_en_dtmb_inner8x_tap_com2demod0_e 0
#define reg_sw_en_dtmb_inner8x2demod0 ckgen00(0x1680)
#define reg_sw_en_dtmb_inner8x2demod0_s 0
#define reg_sw_en_dtmb_inner8x2demod0_e 0
#define reg_sw_en_dtmb_ldpc2demod0 ckgen00(0x1684)
#define reg_sw_en_dtmb_ldpc2demod0_s 0
#define reg_sw_en_dtmb_ldpc2demod0_e 0
#define reg_sw_en_dtmb_ldpc2x2demod0 ckgen00(0x1688)
#define reg_sw_en_dtmb_ldpc2x2demod0_s 0
#define reg_sw_en_dtmb_ldpc2x2demod0_e 0
#define reg_sw_en_dtmb_outer1x2demod0 ckgen00(0x168C)
#define reg_sw_en_dtmb_outer1x2demod0_s 0
#define reg_sw_en_dtmb_outer1x2demod0_e 0
#define reg_sw_en_dtmb_outer1x2demod1 ckgen00(0x1690)
#define reg_sw_en_dtmb_outer1x2demod1_s 0
#define reg_sw_en_dtmb_outer1x2demod1_e 0
#define reg_sw_en_dtmb_outer2x2demod0 ckgen00(0x1694)
#define reg_sw_en_dtmb_outer2x2demod0_s 0
#define reg_sw_en_dtmb_outer2x2demod0_e 0
#define reg_sw_en_dtmb_outer8x2demod0 ckgen00(0x1698)
#define reg_sw_en_dtmb_outer8x2demod0_s 0
#define reg_sw_en_dtmb_outer8x2demod0_e 0
#define reg_sw_en_dtmb_sram_dump2demod0 ckgen00(0x169C)
#define reg_sw_en_dtmb_sram_dump2demod0_s 0
#define reg_sw_en_dtmb_sram_dump2demod0_e 0
#define reg_sw_en_dvbs_outer1x2demod0 ckgen00(0x16A0)
#define reg_sw_en_dvbs_outer1x2demod0_s 0
#define reg_sw_en_dvbs_outer1x2demod0_e 0
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x2demod0 ckgen00(0x16A4)
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x2demod0_s 0
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x2demod0_e 0
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x_miu2demod0 ckgen00(0x16A8)
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x_miu2demod0_s 0
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x_miu2demod0_e 0
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x2demod0 ckgen00(0x16AC)
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x2demod0_s 0
#define reg_sw_en_dvbs_outer2x_dvbt_outer2x2demod0_e 0
#define reg_sw_en_dvbs_outer2x2demod0 ckgen00(0x16B0)
#define reg_sw_en_dvbs_outer2x2demod0_s 0
#define reg_sw_en_dvbs_outer2x2demod0_e 0
#define reg_sw_en_dvbs2_bch2demod0 ckgen00(0x16B4)
#define reg_sw_en_dvbs2_bch2demod0_s 0
#define reg_sw_en_dvbs2_bch2demod0_e 0
#define reg_sw_en_dvbs2_demapper2demod1 ckgen00(0x16B8)
#define reg_sw_en_dvbs2_demapper2demod1_s 0
#define reg_sw_en_dvbs2_demapper2demod1_e 0
#define reg_sw_en_dvbs2_diseqc2demod0 ckgen00(0x16BC)
#define reg_sw_en_dvbs2_diseqc2demod0_s 0
#define reg_sw_en_dvbs2_diseqc2demod0_e 0
#define reg_sw_en_dvbs2_dvbt2_demapper2demod1 ckgen00(0x16C0)
#define reg_sw_en_dvbs2_dvbt2_demapper2demod1_s 0
#define reg_sw_en_dvbs2_dvbt2_demapper2demod1_e 0
#define reg_sw_en_dvbs2_inner2demod0 ckgen00(0x16C4)
#define reg_sw_en_dvbs2_inner2demod0_s 0
#define reg_sw_en_dvbs2_inner2demod0_e 0
#define reg_sw_en_dvbs2_oppro2demod0 ckgen00(0x16C8)
#define reg_sw_en_dvbs2_oppro2demod0_s 0
#define reg_sw_en_dvbs2_oppro2demod0_e 0
#define reg_sw_en_dvbs2_outer_fifo_in2demod1 ckgen00(0x16CC)
#define reg_sw_en_dvbs2_outer_fifo_in2demod1_s 0
#define reg_sw_en_dvbs2_outer_fifo_in2demod1_e 0
#define reg_sw_en_dvbt_inner1x2demod0 ckgen00(0x16D0)
#define reg_sw_en_dvbt_inner1x2demod0_s 0
#define reg_sw_en_dvbt_inner1x2demod0_e 0
#define reg_sw_en_dvbt_inner2x_srd0p5x2demod0 ckgen00(0x16D4)
#define reg_sw_en_dvbt_inner2x_srd0p5x2demod0_s 0
#define reg_sw_en_dvbt_inner2x_srd0p5x2demod0_e 0
#define reg_sw_en_dvbt_inner2x2demod0 ckgen00(0x16D8)
#define reg_sw_en_dvbt_inner2x2demod0_s 0
#define reg_sw_en_dvbt_inner2x2demod0_e 0
#define reg_sw_en_dvbt_inner4x2demod0 ckgen00(0x16DC)
#define reg_sw_en_dvbt_inner4x2demod0_s 0
#define reg_sw_en_dvbt_inner4x2demod0_e 0
#define reg_sw_en_dvbt_outer1x2demod0 ckgen00(0x16E0)
#define reg_sw_en_dvbt_outer1x2demod0_s 0
#define reg_sw_en_dvbt_outer1x2demod0_e 0
#define reg_sw_en_dvbt_outer2x2demod0 ckgen00(0x16E4)
#define reg_sw_en_dvbt_outer2x2demod0_s 0
#define reg_sw_en_dvbt_outer2x2demod0_e 0
#define reg_sw_en_dvbt2_demapper2demod1 ckgen00(0x16E8)
#define reg_sw_en_dvbt2_demapper2demod1_s 0
#define reg_sw_en_dvbt2_demapper2demod1_e 0
#define reg_sw_en_dvbt2_dvbs2_outer_fifo_in2demod1 ckgen00(0x16EC)
#define reg_sw_en_dvbt2_dvbs2_outer_fifo_in2demod1_s 0
#define reg_sw_en_dvbt2_dvbs2_outer_fifo_in2demod1_e 0
#define reg_sw_en_dvbt2_inner1x2demod0 ckgen00(0x16F0)
#define reg_sw_en_dvbt2_inner1x2demod0_s 0
#define reg_sw_en_dvbt2_inner1x2demod0_e 0
#define reg_sw_en_dvbt2_inner2x_srd0p5x2demod0 ckgen00(0x16F4)
#define reg_sw_en_dvbt2_inner2x_srd0p5x2demod0_s 0
#define reg_sw_en_dvbt2_inner2x_srd0p5x2demod0_e 0
#define reg_sw_en_dvbt2_inner2x2demod0 ckgen00(0x16F8)
#define reg_sw_en_dvbt2_inner2x2demod0_s 0
#define reg_sw_en_dvbt2_inner2x2demod0_e 0
#define reg_sw_en_dvbt2_inner4x_dvbtc_rs2demod0 ckgen00(0x16FC)
#define reg_sw_en_dvbt2_inner4x_dvbtc_rs2demod0_s 0
#define reg_sw_en_dvbt2_inner4x_dvbtc_rs2demod0_e 0
#define reg_sw_en_dvbt2_inner4x_s2_inner2demod0 ckgen00(0x1700)
#define reg_sw_en_dvbt2_inner4x_s2_inner2demod0_s 0
#define reg_sw_en_dvbt2_inner4x_s2_inner2demod0_e 0
#define reg_sw_en_dvbt2_inner4x2demod0 ckgen00(0x1704)
#define reg_sw_en_dvbt2_inner4x2demod0_s 0
#define reg_sw_en_dvbt2_inner4x2demod0_e 0
#define reg_sw_en_dvbt2_outer_fifo_in2demod1 ckgen00(0x1708)
#define reg_sw_en_dvbt2_outer_fifo_in2demod1_s 0
#define reg_sw_en_dvbt2_outer_fifo_in2demod1_e 0
#define reg_sw_en_dvbt2_s2_bch_out2demod1 ckgen00(0x170C)
#define reg_sw_en_dvbt2_s2_bch_out2demod1_s 0
#define reg_sw_en_dvbt2_s2_bch_out2demod1_e 0
#define reg_sw_en_dvbt2_s2_bch2demod1 ckgen00(0x1710)
#define reg_sw_en_dvbt2_s2_bch2demod1_s 0
#define reg_sw_en_dvbt2_s2_bch2demod1_e 0
#define reg_sw_en_dvbtc_adc_i2dmd_ana ckgen00(0x1718)
#define reg_sw_en_dvbtc_adc_i2dmd_ana_s 0
#define reg_sw_en_dvbtc_adc_i2dmd_ana_e 0
#define reg_sw_en_dvbtc_adc_q2dmd_ana ckgen00(0x1720)
#define reg_sw_en_dvbtc_adc_q2dmd_ana_s 0
#define reg_sw_en_dvbtc_adc_q2dmd_ana_e 0
#define reg_sw_en_dvbtc_adc2demod0 ckgen00(0x1724)
#define reg_sw_en_dvbtc_adc2demod0_s 0
#define reg_sw_en_dvbtc_adc2demod0_e 0
#define reg_sw_en_dvbtc_outer2x_isdbt_outer_rs2demod0 ckgen00(0x1728)
#define reg_sw_en_dvbtc_outer2x_isdbt_outer_rs2demod0_s 0
#define reg_sw_en_dvbtc_outer2x_isdbt_outer_rs2demod0_e 0
#define reg_sw_en_dvbtc_outer2x2demod0 ckgen00(0x172C)
#define reg_sw_en_dvbtc_outer2x2demod0_s 0
#define reg_sw_en_dvbtc_outer2x2demod0_e 0
#define reg_sw_en_dvbtc_rs2demod0 ckgen00(0x1730)
#define reg_sw_en_dvbtc_rs2demod0_s 0
#define reg_sw_en_dvbtc_rs2demod0_e 0
#define reg_sw_en_dvbtc_sram12demod0 ckgen00(0x1734)
#define reg_sw_en_dvbtc_sram12demod0_s 0
#define reg_sw_en_dvbtc_sram12demod0_e 0
#define reg_sw_en_dvbtc_sram32demod0 ckgen00(0x1738)
#define reg_sw_en_dvbtc_sram32demod0_s 0
#define reg_sw_en_dvbtc_sram32demod0_e 0
#define reg_sw_en_dvbtc_sram42demod0 ckgen00(0x173C)
#define reg_sw_en_dvbtc_sram42demod0_s 0
#define reg_sw_en_dvbtc_sram42demod0_e 0
#define reg_sw_en_dvbtc_ts2demod0 ckgen00(0x1740)
#define reg_sw_en_dvbtc_ts2demod0_s 0
#define reg_sw_en_dvbtc_ts2demod0_e 0
#define reg_sw_en_dvbtm_adc0p5x_eq0p5x2demod0 ckgen00(0x1744)
#define reg_sw_en_dvbtm_adc0p5x_eq0p5x2demod0_s 0
#define reg_sw_en_dvbtm_adc0p5x_eq0p5x2demod0_e 0
#define reg_sw_en_dvbtm_adc1x_eq1x2demod0 ckgen00(0x1748)
#define reg_sw_en_dvbtm_adc1x_eq1x2demod0_s 0
#define reg_sw_en_dvbtm_adc1x_eq1x2demod0_e 0
#define reg_sw_en_dvbtm_sram_adc_t22x_dvbtc_rs2demod0 ckgen00(0x174C)
#define reg_sw_en_dvbtm_sram_adc_t22x_dvbtc_rs2demod0_s 0
#define reg_sw_en_dvbtm_sram_adc_t22x_dvbtc_rs2demod0_e 0
#define reg_sw_en_dvbtm_sram_adc_t22x2demod0 ckgen00(0x1750)
#define reg_sw_en_dvbtm_sram_adc_t22x2demod0_s 0
#define reg_sw_en_dvbtm_sram_adc_t22x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t11x_t22x2demod0 ckgen00(0x1754)
#define reg_sw_en_dvbtm_sram_t11x_t22x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t11x_t22x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t11x_t24x2demod0 ckgen00(0x1758)
#define reg_sw_en_dvbtm_sram_t11x_t24x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t11x_t24x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t12x_t22x2demod0 ckgen00(0x175C)
#define reg_sw_en_dvbtm_sram_t12x_t22x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t12x_t22x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t12x_t24x_s2inner2demod0 ckgen00(0x1760)
#define reg_sw_en_dvbtm_sram_t12x_t24x_s2inner2demod0_s 0
#define reg_sw_en_dvbtm_sram_t12x_t24x_s2inner2demod0_e 0
#define reg_sw_en_dvbtm_sram_t12x_t24x_srd1x2demod0 ckgen00(0x1764)
#define reg_sw_en_dvbtm_sram_t12x_t24x_srd1x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t12x_t24x_srd1x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t12x_t24x2demod0 ckgen00(0x1768)
#define reg_sw_en_dvbtm_sram_t12x_t24x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t12x_t24x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t14x_t24x_s2inner2demod0 ckgen00(0x176C)
#define reg_sw_en_dvbtm_sram_t14x_t24x_s2inner2demod0_s 0
#define reg_sw_en_dvbtm_sram_t14x_t24x_s2inner2demod0_e 0
#define reg_sw_en_dvbtm_sram_t14x_t24x_srd1x_vifdac2demod0 ckgen00(0x1770)
#define reg_sw_en_dvbtm_sram_t14x_t24x_srd1x_vifdac2demod0_s 0
#define reg_sw_en_dvbtm_sram_t14x_t24x_srd1x_vifdac2demod0_e 0
#define reg_sw_en_dvbtm_sram_t14x_t24x_srd1x_vifssc2demod0 ckgen00(0x1774)
#define reg_sw_en_dvbtm_sram_t14x_t24x_srd1x_vifssc2demod0_s 0
#define reg_sw_en_dvbtm_sram_t14x_t24x_srd1x_vifssc2demod0_e 0
#define reg_sw_en_dvbtm_sram_t14x_t24x2demod0 ckgen00(0x1778)
#define reg_sw_en_dvbtm_sram_t14x_t24x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t14x_t24x2demod0_e 0
#define reg_sw_en_dvbtm_sram_t1outer1x_t24x2demod0 ckgen00(0x177C)
#define reg_sw_en_dvbtm_sram_t1outer1x_t24x2demod0_s 0
#define reg_sw_en_dvbtm_sram_t1outer1x_t24x2demod0_e 0
#define reg_sw_en_isdbt_inner1x_dvbt_inner1x2demod0 ckgen00(0x1780)
#define reg_sw_en_isdbt_inner1x_dvbt_inner1x2demod0_s 0
#define reg_sw_en_isdbt_inner1x_dvbt_inner1x2demod0_e 0
#define reg_sw_en_isdbt_inner1x2demod0 ckgen00(0x1784)
#define reg_sw_en_isdbt_inner1x2demod0_s 0
#define reg_sw_en_isdbt_inner1x2demod0_e 0
#define reg_sw_en_isdbt_inner2x_dvbt_inner2x2demod0 ckgen00(0x1788)
#define reg_sw_en_isdbt_inner2x_dvbt_inner2x2demod0_s 0
#define reg_sw_en_isdbt_inner2x_dvbt_inner2x2demod0_e 0
#define reg_sw_en_isdbt_inner2x2demod0 ckgen00(0x178C)
#define reg_sw_en_isdbt_inner2x2demod0_s 0
#define reg_sw_en_isdbt_inner2x2demod0_e 0
#define reg_sw_en_isdbt_inner4x_dvbt_inner4x_adc2demod0 ckgen00(0x1790)
#define reg_sw_en_isdbt_inner4x_dvbt_inner4x_adc2demod0_s 0
#define reg_sw_en_isdbt_inner4x_dvbt_inner4x_adc2demod0_e 0
#define reg_sw_en_isdbt_inner4x_dvbt_inner4x2demod0 ckgen00(0x1794)
#define reg_sw_en_isdbt_inner4x_dvbt_inner4x2demod0_s 0
#define reg_sw_en_isdbt_inner4x_dvbt_inner4x2demod0_e 0
#define reg_sw_en_isdbt_inner4x2demod0 ckgen00(0x1798)
#define reg_sw_en_isdbt_inner4x2demod0_s 0
#define reg_sw_en_isdbt_inner4x2demod0_e 0
#define reg_sw_en_isdbt_outer_rs2demod0 ckgen00(0x179C)
#define reg_sw_en_isdbt_outer_rs2demod0_s 0
#define reg_sw_en_isdbt_outer_rs2demod0_e 0
#define reg_sw_en_isdbt_outer12x2demod0 ckgen00(0x17A0)
#define reg_sw_en_isdbt_outer12x2demod0_s 0
#define reg_sw_en_isdbt_outer12x2demod0_e 0
#define reg_sw_en_isdbt_outer1x_dvbt_outer1x2demod0 ckgen00(0x17A4)
#define reg_sw_en_isdbt_outer1x_dvbt_outer1x2demod0_s 0
#define reg_sw_en_isdbt_outer1x_dvbt_outer1x2demod0_e 0
#define reg_sw_en_isdbt_outer1x2demod0 ckgen00(0x17A8)
#define reg_sw_en_isdbt_outer1x2demod0_s 0
#define reg_sw_en_isdbt_outer1x2demod0_e 0
#define reg_sw_en_isdbt_outer4x2demod0 ckgen00(0x17AC)
#define reg_sw_en_isdbt_outer4x2demod0_s 0
#define reg_sw_en_isdbt_outer4x2demod0_e 0
#define reg_sw_en_isdbt_outer6x_dvbt_inner1x2demod0 ckgen00(0x17B0)
#define reg_sw_en_isdbt_outer6x_dvbt_inner1x2demod0_s 0
#define reg_sw_en_isdbt_outer6x_dvbt_inner1x2demod0_e 0
#define reg_sw_en_isdbt_outer6x_dvbt_inner2x2demod0 ckgen00(0x17B4)
#define reg_sw_en_isdbt_outer6x_dvbt_inner2x2demod0_s 0
#define reg_sw_en_isdbt_outer6x_dvbt_inner2x2demod0_e 0
#define reg_sw_en_isdbt_outer6x_dvbt_outer2x_c2demod0 ckgen00(0x17B8)
#define reg_sw_en_isdbt_outer6x_dvbt_outer2x_c2demod0_s 0
#define reg_sw_en_isdbt_outer6x_dvbt_outer2x_c2demod0_e 0
#define reg_sw_en_isdbt_outer6x_dvbt_outer2x2demod0 ckgen00(0x17BC)
#define reg_sw_en_isdbt_outer6x_dvbt_outer2x2demod0_s 0
#define reg_sw_en_isdbt_outer6x_dvbt_outer2x2demod0_e 0
#define reg_sw_en_isdbt_outer6x2demod0 ckgen00(0x17C0)
#define reg_sw_en_isdbt_outer6x2demod0_s 0
#define reg_sw_en_isdbt_outer6x2demod0_e 0
#define reg_sw_en_ldpc1x2demod1 ckgen00(0x17C4)
#define reg_sw_en_ldpc1x2demod1_s 0
#define reg_sw_en_ldpc1x2demod1_e 0
#define reg_sw_en_ldpc2x2demod1 ckgen00(0x17C8)
#define reg_sw_en_ldpc2x2demod1_s 0
#define reg_sw_en_ldpc2x2demod1_e 0
#define reg_sw_en_sram_dvbt2_s2_bch_me2demod1 ckgen00(0x17E0)
#define reg_sw_en_sram_dvbt2_s2_bch_me2demod1_s 0
#define reg_sw_en_sram_dvbt2_s2_bch_me2demod1_e 0
#define reg_sw_en_sram_ldpc1x_me2demod1 ckgen00(0x17E4)
#define reg_sw_en_sram_ldpc1x_me2demod1_s 0
#define reg_sw_en_sram_ldpc1x_me2demod1_e 0
#define reg_sw_en_sram_ldpc2x_me2demod1 ckgen00(0x17E8)
#define reg_sw_en_sram_ldpc2x_me2demod1_s 0
#define reg_sw_en_sram_ldpc2x_me2demod1_e 0
#define reg_sw_en_sram_share_00_02demod0 ckgen00(0x17EC)
#define reg_sw_en_sram_share_00_02demod0_s 0
#define reg_sw_en_sram_share_00_02demod0_e 0
#define reg_sw_en_sram_share_00_12demod0 ckgen00(0x17F0)
#define reg_sw_en_sram_share_00_12demod0_s 0
#define reg_sw_en_sram_share_00_12demod0_e 0
#define reg_sw_en_sram_share_01_02demod0 ckgen00(0x17F4)
#define reg_sw_en_sram_share_01_02demod0_s 0
#define reg_sw_en_sram_share_01_02demod0_e 0
#define reg_sw_en_sram_share_02_02demod0 ckgen00(0x17F8)
#define reg_sw_en_sram_share_02_02demod0_s 0
#define reg_sw_en_sram_share_02_02demod0_e 0
#define reg_sw_en_sram_share_03_02demod0 ckgen00(0x17FC)
#define reg_sw_en_sram_share_03_02demod0_s 0
#define reg_sw_en_sram_share_03_02demod0_e 0
#define reg_sw_en_sram_share_03_12demod0 ckgen00(0x1800)
#define reg_sw_en_sram_share_03_12demod0_s 0
#define reg_sw_en_sram_share_03_12demod0_e 0
#define reg_sw_en_sram_share_04_02demod0 ckgen00(0x1804)
#define reg_sw_en_sram_share_04_02demod0_s 0
#define reg_sw_en_sram_share_04_02demod0_e 0
#define reg_sw_en_sram_share_04_12demod0 ckgen00(0x1808)
#define reg_sw_en_sram_share_04_12demod0_s 0
#define reg_sw_en_sram_share_04_12demod0_e 0
#define reg_sw_en_sram_share_052demod0 ckgen00(0x180C)
#define reg_sw_en_sram_share_052demod0_s 0
#define reg_sw_en_sram_share_052demod0_e 0
#define reg_sw_en_sram_share_062demod0 ckgen00(0x1810)
#define reg_sw_en_sram_share_062demod0_s 0
#define reg_sw_en_sram_share_062demod0_e 0
#define reg_sw_en_sram_share_072demod0 ckgen00(0x1814)
#define reg_sw_en_sram_share_072demod0_s 0
#define reg_sw_en_sram_share_072demod0_e 0
#define reg_sw_en_sram_share_082demod0 ckgen00(0x1818)
#define reg_sw_en_sram_share_082demod0_s 0
#define reg_sw_en_sram_share_082demod0_e 0
#define reg_sw_en_sram_share_092demod0 ckgen00(0x181C)
#define reg_sw_en_sram_share_092demod0_s 0
#define reg_sw_en_sram_share_092demod0_e 0
#define reg_sw_en_sram_share_102demod0 ckgen00(0x1820)
#define reg_sw_en_sram_share_102demod0_s 0
#define reg_sw_en_sram_share_102demod0_e 0
#define reg_sw_en_sram_share_112demod0 ckgen00(0x1824)
#define reg_sw_en_sram_share_112demod0_s 0
#define reg_sw_en_sram_share_112demod0_e 0
#define reg_sw_en_sram_share_122demod0 ckgen00(0x1828)
#define reg_sw_en_sram_share_122demod0_s 0
#define reg_sw_en_sram_share_122demod0_e 0
#define reg_sw_en_sram_share_132demod0 ckgen00(0x182C)
#define reg_sw_en_sram_share_132demod0_s 0
#define reg_sw_en_sram_share_132demod0_e 0
#define reg_sw_en_sram_share_14_r2demod0 ckgen00(0x1830)
#define reg_sw_en_sram_share_14_r2demod0_s 0
#define reg_sw_en_sram_share_14_r2demod0_e 0
#define reg_sw_en_sram_share_14_w2demod0 ckgen00(0x1834)
#define reg_sw_en_sram_share_14_w2demod0_s 0
#define reg_sw_en_sram_share_14_w2demod0_e 0
#define reg_sw_en_sram_share_15_r2demod0 ckgen00(0x1838)
#define reg_sw_en_sram_share_15_r2demod0_s 0
#define reg_sw_en_sram_share_15_r2demod0_e 0
#define reg_sw_en_sram_share_15_w2demod0 ckgen00(0x183C)
#define reg_sw_en_sram_share_15_w2demod0_s 0
#define reg_sw_en_sram_share_15_w2demod0_e 0
#define reg_sw_en_sram_share_162demod0 ckgen00(0x1840)
#define reg_sw_en_sram_share_162demod0_s 0
#define reg_sw_en_sram_share_162demod0_e 0
#define reg_sw_en_sram_share_182demod0 ckgen00(0x1844)
#define reg_sw_en_sram_share_182demod0_s 0
#define reg_sw_en_sram_share_182demod0_e 0
#define reg_sw_en_sram_share_192demod0 ckgen00(0x1848)
#define reg_sw_en_sram_share_192demod0_s 0
#define reg_sw_en_sram_share_192demod0_e 0
#define reg_sw_en_sram_share_202demod0 ckgen00(0x184C)
#define reg_sw_en_sram_share_202demod0_s 0
#define reg_sw_en_sram_share_202demod0_e 0
#define reg_sw_en_sram_share_212demod0 ckgen00(0x1850)
#define reg_sw_en_sram_share_212demod0_s 0
#define reg_sw_en_sram_share_212demod0_e 0
#define reg_sw_en_sram_share_222demod0 ckgen00(0x1854)
#define reg_sw_en_sram_share_222demod0_s 0
#define reg_sw_en_sram_share_222demod0_e 0
#define reg_sw_en_sram_share_232demod0 ckgen00(0x1858)
#define reg_sw_en_sram_share_232demod0_s 0
#define reg_sw_en_sram_share_232demod0_e 0
#define reg_sw_en_sram_share_242demod0 ckgen00(0x185C)
#define reg_sw_en_sram_share_242demod0_s 0
#define reg_sw_en_sram_share_242demod0_e 0
#define reg_sw_en_sram_share_262demod0 ckgen00(0x1860)
#define reg_sw_en_sram_share_262demod0_s 0
#define reg_sw_en_sram_share_262demod0_e 0
#define reg_sw_en_sram_share_272demod0 ckgen00(0x1864)
#define reg_sw_en_sram_share_272demod0_s 0
#define reg_sw_en_sram_share_272demod0_e 0
#define reg_sw_en_sram_share_282demod0 ckgen00(0x1868)
#define reg_sw_en_sram_share_282demod0_s 0
#define reg_sw_en_sram_share_282demod0_e 0
#define reg_sw_en_sram_share_292demod0 ckgen00(0x186C)
#define reg_sw_en_sram_share_292demod0_s 0
#define reg_sw_en_sram_share_292demod0_e 0
#define reg_sw_en_sram_share_342demod0 ckgen00(0x1870)
#define reg_sw_en_sram_share_342demod0_s 0
#define reg_sw_en_sram_share_342demod0_e 0
#define reg_sw_en_sram_share_352demod0 ckgen00(0x1874)
#define reg_sw_en_sram_share_352demod0_s 0
#define reg_sw_en_sram_share_352demod0_e 0
#define reg_sw_en_sram_share_362demod0 ckgen00(0x1878)
#define reg_sw_en_sram_share_362demod0_s 0
#define reg_sw_en_sram_share_362demod0_e 0
#define reg_sw_en_sram_share_402demod0 ckgen00(0x187C)
#define reg_sw_en_sram_share_402demod0_s 0
#define reg_sw_en_sram_share_402demod0_e 0
#define reg_sw_en_sram_share_422demod0 ckgen00(0x1880)
#define reg_sw_en_sram_share_422demod0_s 0
#define reg_sw_en_sram_share_422demod0_e 0
#define reg_sw_en_sram_share_442demod0 ckgen00(0x1884)
#define reg_sw_en_sram_share_442demod0_s 0
#define reg_sw_en_sram_share_442demod0_e 0
#define reg_sw_en_sram_share_462demod0 ckgen00(0x1888)
#define reg_sw_en_sram_share_462demod0_s 0
#define reg_sw_en_sram_share_462demod0_e 0
#define reg_sw_en_sram_share_472demod0 ckgen00(0x188C)
#define reg_sw_en_sram_share_472demod0_s 0
#define reg_sw_en_sram_share_472demod0_e 0
#define reg_sw_en_sram_share_50_02demod0 ckgen00(0x1890)
#define reg_sw_en_sram_share_50_02demod0_s 0
#define reg_sw_en_sram_share_50_02demod0_e 0
#define reg_sw_en_sram_share_52_02demod0 ckgen00(0x1894)
#define reg_sw_en_sram_share_52_02demod0_s 0
#define reg_sw_en_sram_share_52_02demod0_e 0
#define reg_sw_en_sram_share_53_02demod0 ckgen00(0x1898)
#define reg_sw_en_sram_share_53_02demod0_s 0
#define reg_sw_en_sram_share_53_02demod0_e 0
#define reg_sw_en_sram_share_55_02demod0 ckgen00(0x189C)
#define reg_sw_en_sram_share_55_02demod0_s 0
#define reg_sw_en_sram_share_55_02demod0_e 0
#define reg_sw_en_sram_share_562demod0 ckgen00(0x18A0)
#define reg_sw_en_sram_share_562demod0_s 0
#define reg_sw_en_sram_share_562demod0_e 0
#define reg_sw_en_sram_share_572demod0 ckgen00(0x18A4)
#define reg_sw_en_sram_share_572demod0_s 0
#define reg_sw_en_sram_share_572demod0_e 0
#define reg_sw_en_sram_share_582demod0 ckgen00(0x18A8)
#define reg_sw_en_sram_share_582demod0_s 0
#define reg_sw_en_sram_share_582demod0_e 0
#define reg_sw_en_sram_share_592demod0 ckgen00(0x18AC)
#define reg_sw_en_sram_share_592demod0_s 0
#define reg_sw_en_sram_share_592demod0_e 0
#define reg_sw_en_sram_share_602demod0 ckgen00(0x18B0)
#define reg_sw_en_sram_share_602demod0_s 0
#define reg_sw_en_sram_share_602demod0_e 0
#define reg_sw_en_sram_share_612demod0 ckgen00(0x18B4)
#define reg_sw_en_sram_share_612demod0_s 0
#define reg_sw_en_sram_share_612demod0_e 0
#define reg_sw_en_sram_share_622demod0 ckgen00(0x18B8)
#define reg_sw_en_sram_share_622demod0_s 0
#define reg_sw_en_sram_share_622demod0_e 0
#define reg_sw_en_sram_share_642demod0 ckgen00(0x18BC)
#define reg_sw_en_sram_share_642demod0_s 0
#define reg_sw_en_sram_share_642demod0_e 0
#define reg_sw_en_sram_share_662demod0 ckgen00(0x18C0)
#define reg_sw_en_sram_share_662demod0_s 0
#define reg_sw_en_sram_share_662demod0_e 0
#define reg_sw_en_sram_share_672demod0 ckgen00(0x18C4)
#define reg_sw_en_sram_share_672demod0_s 0
#define reg_sw_en_sram_share_672demod0_e 0
#define reg_sw_en_sram_share_68_02demod0 ckgen00(0x18C8)
#define reg_sw_en_sram_share_68_02demod0_s 0
#define reg_sw_en_sram_share_68_02demod0_e 0
#define reg_sw_en_sram_share_68_22demod0 ckgen00(0x18CC)
#define reg_sw_en_sram_share_68_22demod0_s 0
#define reg_sw_en_sram_share_68_22demod0_e 0
#define reg_sw_en_sram_share_69_02demod0 ckgen00(0x18D0)
#define reg_sw_en_sram_share_69_02demod0_s 0
#define reg_sw_en_sram_share_69_02demod0_e 0
#define reg_sw_en_sram_share_702demod0 ckgen00(0x18D4)
#define reg_sw_en_sram_share_702demod0_s 0
#define reg_sw_en_sram_share_702demod0_e 0
#define reg_sw_en_sram_share_712demod0 ckgen00(0x18D8)
#define reg_sw_en_sram_share_712demod0_s 0
#define reg_sw_en_sram_share_712demod0_e 0
#define reg_sw_en_sram_share_772demod0 ckgen00(0x18DC)
#define reg_sw_en_sram_share_772demod0_s 0
#define reg_sw_en_sram_share_772demod0_e 0
#define reg_sw_en_sram_share_792demod0 ckgen00(0x18E0)
#define reg_sw_en_sram_share_792demod0_s 0
#define reg_sw_en_sram_share_792demod0_e 0
#define reg_sw_en_sram_share_812demod0 ckgen00(0x18E4)
#define reg_sw_en_sram_share_812demod0_s 0
#define reg_sw_en_sram_share_812demod0_e 0
#define reg_sw_en_sram_share_852demod0 ckgen00(0x18E8)
#define reg_sw_en_sram_share_852demod0_s 0
#define reg_sw_en_sram_share_852demod0_e 0
#define reg_sw_en_sram_share_872demod0 ckgen00(0x18EC)
#define reg_sw_en_sram_share_872demod0_s 0
#define reg_sw_en_sram_share_872demod0_e 0
#define reg_sw_en_sram_share_892demod0 ckgen00(0x18F0)
#define reg_sw_en_sram_share_892demod0_s 0
#define reg_sw_en_sram_share_892demod0_e 0
#define reg_sw_en_sram_share_912demod0 ckgen00(0x18F4)
#define reg_sw_en_sram_share_912demod0_s 0
#define reg_sw_en_sram_share_912demod0_e 0
#define reg_sw_en_sram_share_922demod0 ckgen00(0x18F8)
#define reg_sw_en_sram_share_922demod0_s 0
#define reg_sw_en_sram_share_922demod0_e 0
#define reg_sw_en_sram_share_932demod0 ckgen00(0x18FC)
#define reg_sw_en_sram_share_932demod0_s 0
#define reg_sw_en_sram_share_932demod0_e 0
#define reg_sw_en_sram_share_942demod0 ckgen00(0x1900)
#define reg_sw_en_sram_share_942demod0_s 0
#define reg_sw_en_sram_share_942demod0_e 0
#define reg_sw_en_sram_share_962demod0 ckgen00(0x1904)
#define reg_sw_en_sram_share_962demod0_s 0
#define reg_sw_en_sram_share_962demod0_e 0
#define reg_sw_en_sram_share_982demod0 ckgen00(0x1908)
#define reg_sw_en_sram_share_982demod0_s 0
#define reg_sw_en_sram_share_982demod0_e 0
#define reg_sw_en_sram_share_992demod0 ckgen00(0x190C)
#define reg_sw_en_sram_share_992demod0_s 0
#define reg_sw_en_sram_share_992demod0_e 0
#define reg_sw_en_sram_share_1002demod0 ckgen00(0x1910)
#define reg_sw_en_sram_share_1002demod0_s 0
#define reg_sw_en_sram_share_1002demod0_e 0
#define reg_sw_en_sram_share_1032demod0 ckgen00(0x1914)
#define reg_sw_en_sram_share_1032demod0_s 0
#define reg_sw_en_sram_share_1032demod0_e 0
#define reg_sw_en_sram_share_1052demod0 ckgen00(0x1918)
#define reg_sw_en_sram_share_1052demod0_s 0
#define reg_sw_en_sram_share_1052demod0_e 0
#define reg_sw_en_sram_share_1072demod0 ckgen00(0x191C)
#define reg_sw_en_sram_share_1072demod0_s 0
#define reg_sw_en_sram_share_1072demod0_e 0
#define reg_sw_en_sram_share_1092demod0 ckgen00(0x1920)
#define reg_sw_en_sram_share_1092demod0_s 0
#define reg_sw_en_sram_share_1092demod0_e 0
#define reg_sw_en_sram_share_1102demod0 ckgen00(0x1924)
#define reg_sw_en_sram_share_1102demod0_s 0
#define reg_sw_en_sram_share_1102demod0_e 0
#define reg_sw_en_sram_share_1112demod0 ckgen00(0x1928)
#define reg_sw_en_sram_share_1112demod0_s 0
#define reg_sw_en_sram_share_1112demod0_e 0
#define reg_sw_en_sram_share_1122demod0 ckgen00(0x192C)
#define reg_sw_en_sram_share_1122demod0_s 0
#define reg_sw_en_sram_share_1122demod0_e 0
#define reg_sw_en_sram_share_1242demod0 ckgen00(0x1930)
#define reg_sw_en_sram_share_1242demod0_s 0
#define reg_sw_en_sram_share_1242demod0_e 0
#define reg_sw_en_sram_share_1282demod0 ckgen00(0x1934)
#define reg_sw_en_sram_share_1282demod0_s 0
#define reg_sw_en_sram_share_1282demod0_e 0
#define reg_sw_en_sram_share_1292demod0 ckgen00(0x1938)
#define reg_sw_en_sram_share_1292demod0_s 0
#define reg_sw_en_sram_share_1292demod0_e 0
#define reg_sw_en_sram_share_1302demod0 ckgen00(0x193C)
#define reg_sw_en_sram_share_1302demod0_s 0
#define reg_sw_en_sram_share_1302demod0_e 0
#define reg_sw_en_sram_share_1312demod0 ckgen00(0x1940)
#define reg_sw_en_sram_share_1312demod0_s 0
#define reg_sw_en_sram_share_1312demod0_e 0
#define reg_sw_en_sram_share_1322demod0 ckgen00(0x1944)
#define reg_sw_en_sram_share_1322demod0_s 0
#define reg_sw_en_sram_share_1322demod0_e 0
#define reg_sw_en_sram_share_134_r2demod0 ckgen00(0x1948)
#define reg_sw_en_sram_share_134_r2demod0_s 0
#define reg_sw_en_sram_share_134_r2demod0_e 0
#define reg_sw_en_sram_share_134_w2demod0 ckgen00(0x194C)
#define reg_sw_en_sram_share_134_w2demod0_s 0
#define reg_sw_en_sram_share_134_w2demod0_e 0
#define reg_sw_en_sram_share_136_r2demod0 ckgen00(0x1950)
#define reg_sw_en_sram_share_136_r2demod0_s 0
#define reg_sw_en_sram_share_136_r2demod0_e 0
#define reg_sw_en_sram_share_136_w2demod0 ckgen00(0x1954)
#define reg_sw_en_sram_share_136_w2demod0_s 0
#define reg_sw_en_sram_share_136_w2demod0_e 0
#define reg_sw_en_sram_share_137_r2demod0 ckgen00(0x1958)
#define reg_sw_en_sram_share_137_r2demod0_s 0
#define reg_sw_en_sram_share_137_r2demod0_e 0
#define reg_sw_en_sram_share_137_w2demod0 ckgen00(0x195C)
#define reg_sw_en_sram_share_137_w2demod0_s 0
#define reg_sw_en_sram_share_137_w2demod0_e 0
#define reg_sw_en_sram_share_138_r2demod0 ckgen00(0x1960)
#define reg_sw_en_sram_share_138_r2demod0_s 0
#define reg_sw_en_sram_share_138_r2demod0_e 0
#define reg_sw_en_sram_share_138_w2demod0 ckgen00(0x1964)
#define reg_sw_en_sram_share_138_w2demod0_s 0
#define reg_sw_en_sram_share_138_w2demod0_e 0
#define reg_sw_en_sram_share_139_r2demod0 ckgen00(0x1968)
#define reg_sw_en_sram_share_139_r2demod0_s 0
#define reg_sw_en_sram_share_139_r2demod0_e 0
#define reg_sw_en_sram_share_139_w2demod0 ckgen00(0x196C)
#define reg_sw_en_sram_share_139_w2demod0_s 0
#define reg_sw_en_sram_share_139_w2demod0_e 0
#define reg_sw_en_sram_share_140_r2demod0 ckgen00(0x1970)
#define reg_sw_en_sram_share_140_r2demod0_s 0
#define reg_sw_en_sram_share_140_r2demod0_e 0
#define reg_sw_en_sram_share_140_w2demod0 ckgen00(0x1974)
#define reg_sw_en_sram_share_140_w2demod0_s 0
#define reg_sw_en_sram_share_140_w2demod0_e 0
#define reg_sw_en_sram_share_141_r2demod0 ckgen00(0x1978)
#define reg_sw_en_sram_share_141_r2demod0_s 0
#define reg_sw_en_sram_share_141_r2demod0_e 0
#define reg_sw_en_sram_share_141_w2demod0 ckgen00(0x197C)
#define reg_sw_en_sram_share_141_w2demod0_s 0
#define reg_sw_en_sram_share_141_w2demod0_e 0
#define reg_sw_en_sram_share_142_r2demod0 ckgen00(0x1980)
#define reg_sw_en_sram_share_142_r2demod0_s 0
#define reg_sw_en_sram_share_142_r2demod0_e 0
#define reg_sw_en_sram_share_142_w2demod0 ckgen00(0x1984)
#define reg_sw_en_sram_share_142_w2demod0_s 0
#define reg_sw_en_sram_share_142_w2demod0_e 0
#define reg_sw_en_sram_share_143_r2demod0 ckgen00(0x1988)
#define reg_sw_en_sram_share_143_r2demod0_s 0
#define reg_sw_en_sram_share_143_r2demod0_e 0
#define reg_sw_en_sram_share_143_w2demod0 ckgen00(0x198C)
#define reg_sw_en_sram_share_143_w2demod0_s 0
#define reg_sw_en_sram_share_143_w2demod0_e 0
#define reg_sw_en_sram_share_144_r2demod0 ckgen00(0x1990)
#define reg_sw_en_sram_share_144_r2demod0_s 0
#define reg_sw_en_sram_share_144_r2demod0_e 0
#define reg_sw_en_sram_share_144_w2demod0 ckgen00(0x1994)
#define reg_sw_en_sram_share_144_w2demod0_s 0
#define reg_sw_en_sram_share_144_w2demod0_e 0
#define reg_sw_en_tdp_jl_inner1x2demod0 ckgen00(0x1998)
#define reg_sw_en_tdp_jl_inner1x2demod0_s 0
#define reg_sw_en_tdp_jl_inner1x2demod0_e 0
#define reg_sw_en_tdp_jl_inner4x2demod0 ckgen00(0x199C)
#define reg_sw_en_tdp_jl_inner4x2demod0_s 0
#define reg_sw_en_tdp_jl_inner4x2demod0_e 0
#define reg_sw_en_tdp_teq_inner1x2demod0 ckgen00(0x19A0)
#define reg_sw_en_tdp_teq_inner1x2demod0_s 0
#define reg_sw_en_tdp_teq_inner1x2demod0_e 0
#define reg_sw_en_tdp_teq_inner2x2demod0 ckgen00(0x19A4)
#define reg_sw_en_tdp_teq_inner2x2demod0_s 0
#define reg_sw_en_tdp_teq_inner2x2demod0_e 0
#define reg_sw_en_tr2demod0 ckgen00(0x19A8)
#define reg_sw_en_tr2demod0_s 0
#define reg_sw_en_tr2demod0_e 0
#define reg_sw_en_ts_in2demod0 ckgen00(0x19AC)
#define reg_sw_en_ts_in2demod0_s 0
#define reg_sw_en_ts_in2demod0_e 0
#define reg_sw_en_vifdbb_144m2demod0 ckgen00(0x19B0)
#define reg_sw_en_vifdbb_144m2demod0_s 0
#define reg_sw_en_vifdbb_144m2demod0_e 0
#define reg_sw_en_vifdbb_43m2demod0 ckgen00(0x19B4)
#define reg_sw_en_vifdbb_43m2demod0_s 0
#define reg_sw_en_vifdbb_43m2demod0_e 0
#define reg_sw_en_vifdbb_86m2demod0 ckgen00(0x19B8)
#define reg_sw_en_vifdbb_86m2demod0_s 0
#define reg_sw_en_vifdbb_86m2demod0_e 0
#define reg_sw_en_vifdbb_dac2demod0 ckgen00(0x19BC)
#define reg_sw_en_vifdbb_dac2demod0_s 0
#define reg_sw_en_vifdbb_dac2demod0_e 0
#define reg_sw_en_vifdbb_vdac_tmp2demod0 ckgen00(0x19C0)
#define reg_sw_en_vifdbb_vdac_tmp2demod0_s 0
#define reg_sw_en_vifdbb_vdac_tmp2demod0_e 0
#define reg_sw_en_vifdbb_vdac2demod0 ckgen00(0x19C4)
#define reg_sw_en_vifdbb_vdac2demod0_s 0
#define reg_sw_en_vifdbb_vdac2demod0_e 0
#define reg_sw_en_xtal_12m2demod0 ckgen00(0x19C8)
#define reg_sw_en_xtal_12m2demod0_s 0
#define reg_sw_en_xtal_12m2demod0_e 0
#define reg_sw_en_xtal_24m2demod0 ckgen00(0x19CC)
#define reg_sw_en_xtal_24m2demod0_s 0
#define reg_sw_en_xtal_24m2demod0_e 0
#define reg_sw_en_xtal_24m2demod1 ckgen00(0x19D0)
#define reg_sw_en_xtal_24m2demod1_s 0
#define reg_sw_en_xtal_24m2demod1_e 0
#define reg_sw_en_xtal_12m2demod1 ckgen00(0x19D4)
#define reg_sw_en_xtal_12m2demod1_s 0
#define reg_sw_en_xtal_12m2demod1_e 0
#define reg_sw_en_aesdma2dscrmb ckgen00(0x1A00)
#define reg_sw_en_aesdma2dscrmb_s 0
#define reg_sw_en_aesdma2dscrmb_e 0
#define reg_sw_en_cilink_2b_rx2cilink ckgen00(0x1A0C)
#define reg_sw_en_cilink_2b_rx2cilink_s 0
#define reg_sw_en_cilink_2b_rx2cilink_e 0
#define reg_sw_en_cilink_2b_tx_ext2ts_sample ckgen00(0x1A10)
#define reg_sw_en_cilink_2b_tx_ext2ts_sample_s 0
#define reg_sw_en_cilink_2b_tx_ext2ts_sample_e 0
#define reg_sw_en_cilink_2b_tx2cilink ckgen00(0x1A14)
#define reg_sw_en_cilink_2b_tx2cilink_s 0
#define reg_sw_en_cilink_2b_tx2cilink_e 0
#define reg_sw_en_cilink_if2cilink ckgen00(0x1A18)
#define reg_sw_en_cilink_if2cilink_s 0
#define reg_sw_en_cilink_if2cilink_e 0
#define reg_sw_en_smart_synth_272piu ckgen00(0x1A24)
#define reg_sw_en_smart_synth_272piu_s 0
#define reg_sw_en_smart_synth_272piu_e 0
#define reg_sw_en_smart_synth_4322piu ckgen00(0x1A28)
#define reg_sw_en_smart_synth_4322piu_s 0
#define reg_sw_en_smart_synth_4322piu_e 0
#define reg_sw_en_smart2_synth_272piu ckgen00(0x1A2C)
#define reg_sw_en_smart2_synth_272piu_s 0
#define reg_sw_en_smart2_synth_272piu_e 0
#define reg_sw_en_smart2_synth_4322piu ckgen00(0x1A30)
#define reg_sw_en_smart2_synth_4322piu_s 0
#define reg_sw_en_smart2_synth_4322piu_e 0
#define reg_sw_en_smart22piu ckgen00(0x1A34)
#define reg_sw_en_smart22piu_s 0
#define reg_sw_en_smart22piu_e 0
#define reg_sw_en_smart2piu ckgen00(0x1A38)
#define reg_sw_en_smart2piu_s 0
#define reg_sw_en_smart2piu_e 0
#define reg_sw_en_fiq0_27m2tsp ckgen00(0x1A48)
#define reg_sw_en_fiq0_27m2tsp_s 0
#define reg_sw_en_fiq0_27m2tsp_e 0
#define reg_sw_en_mm0_27m2tsp ckgen00(0x1A4C)
#define reg_sw_en_mm0_27m2tsp_s 0
#define reg_sw_en_mm0_27m2tsp_e 0
#define reg_sw_en_mm1_27m2tsp ckgen00(0x1A50)
#define reg_sw_en_mm1_27m2tsp_s 0
#define reg_sw_en_mm1_27m2tsp_e 0
#define reg_sw_en_parser2tsp ckgen00(0x1A54)
#define reg_sw_en_parser2tsp_s 0
#define reg_sw_en_parser2tsp_e 0
#define reg_sw_en_parser2vd_pes_parser ckgen00(0x1A54)
#define reg_sw_en_parser2vd_pes_parser_s 1
#define reg_sw_en_parser2vd_pes_parser_e 1
#define reg_sw_en_viva_parser2parser ckgen00(0x1A54)
#define reg_sw_en_viva_parser2parser_s 2
#define reg_sw_en_viva_parser2parser_e 2
#define reg_sw_en_pvr1_27m2tsp ckgen00(0x1A58)
#define reg_sw_en_pvr1_27m2tsp_s 0
#define reg_sw_en_pvr1_27m2tsp_e 0
#define reg_sw_en_pvr2_27m2tsp ckgen00(0x1A5C)
#define reg_sw_en_pvr2_27m2tsp_s 0
#define reg_sw_en_pvr2_27m2tsp_e 0
#define reg_sw_en_pvr3_27m2tsp ckgen00(0x1A60)
#define reg_sw_en_pvr3_27m2tsp_s 0
#define reg_sw_en_pvr3_27m2tsp_e 0
#define reg_sw_en_pvr4_27m2tsp ckgen00(0x1A64)
#define reg_sw_en_pvr4_27m2tsp_s 0
#define reg_sw_en_pvr4_27m2tsp_e 0
#define reg_sw_en_stamp2tso ckgen00(0x1A6C)
#define reg_sw_en_stamp2tso_s 0
#define reg_sw_en_stamp2tso_e 0
#define reg_sw_en_stamp2tso2 ckgen00(0x1A70)
#define reg_sw_en_stamp2tso2_s 0
#define reg_sw_en_stamp2tso2_e 0
#define reg_sw_en_stamp2tsp ckgen00(0x1A74)
#define reg_sw_en_stamp2tsp_s 0
#define reg_sw_en_stamp2tsp_e 0
#define reg_sw_en_syn_stc02ts_sample ckgen00(0x1A78)
#define reg_sw_en_syn_stc02ts_sample_s 0
#define reg_sw_en_syn_stc02ts_sample_e 0
#define reg_sw_en_syn_stc12ts_sample ckgen00(0x1A7C)
#define reg_sw_en_syn_stc12ts_sample_s 0
#define reg_sw_en_syn_stc12ts_sample_e 0
#define reg_sw_en_syn_stc22ts_sample ckgen00(0x1A80)
#define reg_sw_en_syn_stc22ts_sample_s 0
#define reg_sw_en_syn_stc22ts_sample_e 0
#define reg_sw_en_syn_stc32ts_sample ckgen00(0x1A84)
#define reg_sw_en_syn_stc32ts_sample_s 0
#define reg_sw_en_syn_stc32ts_sample_e 0
#define reg_sw_en_sys_time0_27m2tsp ckgen00(0x1A88)
#define reg_sw_en_sys_time0_27m2tsp_s 0
#define reg_sw_en_sys_time0_27m2tsp_e 0
#define reg_sw_en_sys_time1_27m2tsp ckgen00(0x1A8C)
#define reg_sw_en_sys_time1_27m2tsp_s 0
#define reg_sw_en_sys_time1_27m2tsp_e 0
#define reg_sw_en_sys_time2_27m2tsp ckgen00(0x1A90)
#define reg_sw_en_sys_time2_27m2tsp_s 0
#define reg_sw_en_sys_time2_27m2tsp_e 0
#define reg_sw_en_sys_time3_27m2tsp ckgen00(0x1A94)
#define reg_sw_en_sys_time3_27m2tsp_s 0
#define reg_sw_en_sys_time3_27m2tsp_e 0
#define reg_sw_en_tlv0_27m2tsp ckgen00(0x1A98)
#define reg_sw_en_tlv0_27m2tsp_s 0
#define reg_sw_en_tlv0_27m2tsp_e 0
#define reg_sw_en_tlv1_27m2tsp ckgen00(0x1A9C)
#define reg_sw_en_tlv1_27m2tsp_s 0
#define reg_sw_en_tlv1_27m2tsp_e 0
#define reg_sw_en_tlv2_27m2tsp ckgen00(0x1AA0)
#define reg_sw_en_tlv2_27m2tsp_s 0
#define reg_sw_en_tlv2_27m2tsp_e 0
#define reg_sw_en_ts_alp02tsp ckgen00(0x1AA8)
#define reg_sw_en_ts_alp02tsp_s 0
#define reg_sw_en_ts_alp02tsp_e 0
#define reg_sw_en_ts_alp12tsp ckgen00(0x1AAC)
#define reg_sw_en_ts_alp12tsp_s 0
#define reg_sw_en_ts_alp12tsp_e 0
#define reg_sw_en_ts_sample2ts_sample ckgen00(0x1AB4)
#define reg_sw_en_ts_sample2ts_sample_s 0
#define reg_sw_en_ts_sample2ts_sample_e 0
#define reg_sw_en_ts_tx_c12cilink ckgen00(0x1AB8)
#define reg_sw_en_ts_tx_c12cilink_s 0
#define reg_sw_en_ts_tx_c12cilink_e 0
#define reg_sw_en_ts_tx_c22cilink ckgen00(0x1ABC)
#define reg_sw_en_ts_tx_c22cilink_s 0
#define reg_sw_en_ts_tx_c22cilink_e 0
#define reg_sw_en_ts0_in_dft2ts_sample ckgen00(0x1AC0)
#define reg_sw_en_ts0_in_dft2ts_sample_s 0
#define reg_sw_en_ts0_in_dft2ts_sample_e 0
#define reg_sw_en_ts02tsp ckgen00(0x1AC4)
#define reg_sw_en_ts02tsp_s 0
#define reg_sw_en_ts02tsp_e 0
#define reg_sw_en_ts1_in_dft2ts_sample ckgen00(0x1AC8)
#define reg_sw_en_ts1_in_dft2ts_sample_s 0
#define reg_sw_en_ts1_in_dft2ts_sample_e 0
#define reg_sw_en_ts12tsp ckgen00(0x1ACC)
#define reg_sw_en_ts12tsp_s 0
#define reg_sw_en_ts12tsp_e 0
#define reg_sw_en_ts2_in_dft2ts_sample ckgen00(0x1AD0)
#define reg_sw_en_ts2_in_dft2ts_sample_s 0
#define reg_sw_en_ts2_in_dft2ts_sample_e 0
#define reg_sw_en_ts22tsp ckgen00(0x1AD4)
#define reg_sw_en_ts22tsp_s 0
#define reg_sw_en_ts22tsp_e 0
#define reg_sw_en_ts3_in_dft2ts_sample ckgen00(0x1AD8)
#define reg_sw_en_ts3_in_dft2ts_sample_s 0
#define reg_sw_en_ts3_in_dft2ts_sample_e 0
#define reg_sw_en_ts4_in_dft2ts_sample ckgen00(0x1ADC)
#define reg_sw_en_ts4_in_dft2ts_sample_s 0
#define reg_sw_en_ts4_in_dft2ts_sample_e 0
#define reg_sw_en_ts5_in_dft2ts_sample ckgen00(0x1AE0)
#define reg_sw_en_ts5_in_dft2ts_sample_s 0
#define reg_sw_en_ts5_in_dft2ts_sample_e 0
#define reg_sw_en_tsfi2tsp ckgen00(0x1AE4)
#define reg_sw_en_tsfi2tsp_s 0
#define reg_sw_en_tsfi2tsp_e 0
#define reg_sw_en_tsif0_27m2tsp ckgen00(0x1AE8)
#define reg_sw_en_tsif0_27m2tsp_s 0
#define reg_sw_en_tsif0_27m2tsp_e 0
#define reg_sw_en_tso_ch1_27m2tso ckgen00(0x1AEC)
#define reg_sw_en_tso_ch1_27m2tso_s 0
#define reg_sw_en_tso_ch1_27m2tso_e 0
#define reg_sw_en_tso_ch12tso ckgen00(0x1AF0)
#define reg_sw_en_tso_ch12tso_s 0
#define reg_sw_en_tso_ch12tso_e 0
#define reg_sw_en_tso_ch5_27m2tso ckgen00(0x1AF4)
#define reg_sw_en_tso_ch5_27m2tso_s 0
#define reg_sw_en_tso_ch5_27m2tso_e 0
#define reg_sw_en_tso_ch52tso ckgen00(0x1AF8)
#define reg_sw_en_tso_ch52tso_s 0
#define reg_sw_en_tso_ch52tso_e 0
#define reg_sw_en_tso_ch6_27m2tso ckgen00(0x1AFC)
#define reg_sw_en_tso_ch6_27m2tso_s 0
#define reg_sw_en_tso_ch6_27m2tso_e 0
#define reg_sw_en_tso_ch62tso ckgen00(0x1B00)
#define reg_sw_en_tso_ch62tso_s 0
#define reg_sw_en_tso_ch62tso_e 0
#define reg_sw_en_tso_out_div_mn_src2ts_sample ckgen00(0x1B04)
#define reg_sw_en_tso_out_div_mn_src2ts_sample_s 0
#define reg_sw_en_tso_out_div_mn_src2ts_sample_e 0
#define reg_sw_en_tso_out2tso ckgen00(0x1B08)
#define reg_sw_en_tso_out2tso_s 0
#define reg_sw_en_tso_out2tso_e 0
#define reg_sw_en_tso_s2p12tso ckgen00(0x1B0C)
#define reg_sw_en_tso_s2p12tso_s 0
#define reg_sw_en_tso_s2p12tso_e 0
#define reg_sw_en_tso_s2p2tso ckgen00(0x1B10)
#define reg_sw_en_tso_s2p2tso_s 0
#define reg_sw_en_tso_s2p2tso_e 0
#define reg_sw_en_tso_trace_in2tso ckgen00(0x1B14)
#define reg_sw_en_tso_trace_in2tso_s 0
#define reg_sw_en_tso_trace_in2tso_e 0
#define reg_sw_en_tso_trace2tso ckgen00(0x1B18)
#define reg_sw_en_tso_trace2tso_s 0
#define reg_sw_en_tso_trace2tso_e 0
#define reg_sw_en_tso2_ch1_27m2tso2 ckgen00(0x1B1C)
#define reg_sw_en_tso2_ch1_27m2tso2_s 0
#define reg_sw_en_tso2_ch1_27m2tso2_e 0
#define reg_sw_en_tso2_ch12tso2 ckgen00(0x1B20)
#define reg_sw_en_tso2_ch12tso2_s 0
#define reg_sw_en_tso2_ch12tso2_e 0
#define reg_sw_en_tso2_ch5_27m2tso2 ckgen00(0x1B24)
#define reg_sw_en_tso2_ch5_27m2tso2_s 0
#define reg_sw_en_tso2_ch5_27m2tso2_e 0
#define reg_sw_en_tso2_ch52tso2 ckgen00(0x1B28)
#define reg_sw_en_tso2_ch52tso2_s 0
#define reg_sw_en_tso2_ch52tso2_e 0
#define reg_sw_en_tso2_ch6_27m2tso2 ckgen00(0x1B2C)
#define reg_sw_en_tso2_ch6_27m2tso2_s 0
#define reg_sw_en_tso2_ch6_27m2tso2_e 0
#define reg_sw_en_tso2_ch62tso2 ckgen00(0x1B30)
#define reg_sw_en_tso2_ch62tso2_s 0
#define reg_sw_en_tso2_ch62tso2_e 0
#define reg_sw_en_tso2_out_div_mn_src2ts_sample ckgen00(0x1B34)
#define reg_sw_en_tso2_out_div_mn_src2ts_sample_s 0
#define reg_sw_en_tso2_out_div_mn_src2ts_sample_e 0
#define reg_sw_en_tso2_out2tso2 ckgen00(0x1B38)
#define reg_sw_en_tso2_out2tso2_s 0
#define reg_sw_en_tso2_out2tso2_e 0
#define reg_sw_en_tso2_s2p12tso2 ckgen00(0x1B3C)
#define reg_sw_en_tso2_s2p12tso2_s 0
#define reg_sw_en_tso2_s2p12tso2_e 0
#define reg_sw_en_tso2_s2p2tso2 ckgen00(0x1B40)
#define reg_sw_en_tso2_s2p2tso2_s 0
#define reg_sw_en_tso2_s2p2tso2_e 0
#define reg_sw_en_tso2_trace_in2tso2 ckgen00(0x1B44)
#define reg_sw_en_tso2_trace_in2tso2_s 0
#define reg_sw_en_tso2_trace_in2tso2_e 0
#define reg_sw_en_tso2_trace2tso2 ckgen00(0x1B48)
#define reg_sw_en_tso2_trace2tso2_s 0
#define reg_sw_en_tso2_trace2tso2_e 0
#define reg_sw_en_tsp2dscrmb ckgen00(0x1B4C)
#define reg_sw_en_tsp2dscrmb_s 0
#define reg_sw_en_tsp2dscrmb_e 0
#define reg_sw_en_tsp2tso ckgen00(0x1B50)
#define reg_sw_en_tsp2tso_s 0
#define reg_sw_en_tsp2tso_e 0
#define reg_sw_en_tsp2tso2 ckgen00(0x1B50)
#define reg_sw_en_tsp2tso2_s 1
#define reg_sw_en_tsp2tso2_e 1
#define reg_sw_en_tsp2tsp ckgen00(0x1B50)
#define reg_sw_en_tsp2tsp_s 2
#define reg_sw_en_tsp2tsp_e 2
#define reg_sw_en_ts_tlv02tsp ckgen00(0x1B54)
#define reg_sw_en_ts_tlv02tsp_s 0
#define reg_sw_en_ts_tlv02tsp_e 0
#define reg_sw_en_ts_tlv12tsp ckgen00(0x1B58)
#define reg_sw_en_ts_tlv12tsp_s 0
#define reg_sw_en_ts_tlv12tsp_e 0
#define reg_sw_en_ts_tlv22tsp ckgen00(0x1B5C)
#define reg_sw_en_ts_tlv22tsp_s 0
#define reg_sw_en_ts_tlv22tsp_e 0
#define reg_sw_en_path0_27m2tsp ckgen00(0x1B60)
#define reg_sw_en_path0_27m2tsp_s 0
#define reg_sw_en_path0_27m2tsp_e 0
#define reg_sw_en_path1_27m2tsp ckgen00(0x1B64)
#define reg_sw_en_path1_27m2tsp_s 0
#define reg_sw_en_path1_27m2tsp_e 0
#define reg_sw_en_path2_27m2tsp ckgen00(0x1B68)
#define reg_sw_en_path2_27m2tsp_s 0
#define reg_sw_en_path2_27m2tsp_e 0
#define reg_sw_en_path_fi_27m2tsp ckgen00(0x1B6C)
#define reg_sw_en_path_fi_27m2tsp_s 0
#define reg_sw_en_path_fi_27m2tsp_e 0
#define reg_sw_en_au_r2_dfs2audio_r2 ckgen00(0x1B84)
#define reg_sw_en_au_r2_dfs2audio_r2_s 0
#define reg_sw_en_au_r2_dfs2audio_r2_e 0
#define reg_sw_en_au_r2_pll2audio_r2 ckgen00(0x1B88)
#define reg_sw_en_au_r2_pll2audio_r2_s 0
#define reg_sw_en_au_r2_pll2audio_r2_e 0
#define reg_sw_en_au_r2_wb2audio_r2 ckgen00(0x1B8C)
#define reg_sw_en_au_r2_wb2audio_r2_s 0
#define reg_sw_en_au_r2_wb2audio_r2_e 0
#define reg_sw_en_ausdm_3m2ausdm_dmacro ckgen00(0x1B90)
#define reg_sw_en_ausdm_3m2ausdm_dmacro_s 0
#define reg_sw_en_ausdm_3m2ausdm_dmacro_e 0
#define reg_sw_en_bclk_i2s_encoder22bclk_i2s_encoder2 ckgen00(0x1B94)
#define reg_sw_en_bclk_i2s_encoder22bclk_i2s_encoder2_s 0
#define reg_sw_en_bclk_i2s_encoder22bclk_i2s_encoder2_e 0
#define reg_sw_en_bclk_i2s_encoder2bclk_i2s_encoder ckgen00(0x1B98)
#define reg_sw_en_bclk_i2s_encoder2bclk_i2s_encoder_s 0
#define reg_sw_en_bclk_i2s_encoder2bclk_i2s_encoder_e 0
#define reg_sw_en_earc_audio2earc_dmacro ckgen00(0x1B9C)
#define reg_sw_en_earc_audio2earc_dmacro_s 0
#define reg_sw_en_earc_audio2earc_dmacro_e 0
#define reg_sw_en_viva_ab_mac2ab_mac ckgen00(0x1BA0)
#define reg_sw_en_viva_ab_mac2ab_mac_s 0
#define reg_sw_en_viva_ab_mac2ab_mac_e 0
#define reg_sw_en_viva_ab3_mac2ab3_mac ckgen00(0x1BA4)
#define reg_sw_en_viva_ab3_mac2ab3_mac_s 0
#define reg_sw_en_viva_ab3_mac2ab3_mac_e 0
#define reg_sw_en_viva_adc_512fs2adc_512_fs ckgen00(0x1BA8)
#define reg_sw_en_viva_adc_512fs2adc_512_fs_s 0
#define reg_sw_en_viva_adc_512fs2adc_512_fs_e 0
#define reg_sw_en_viva_au_mcu2au_mcu ckgen00(0x1BAC)
#define reg_sw_en_viva_au_mcu2au_mcu_s 0
#define reg_sw_en_viva_au_mcu2au_mcu_e 0
#define reg_sw_en_viva_audma_v2_r1_256fs2audma_v2_r1_256fs ckgen00(0x1BB0)
#define reg_sw_en_viva_audma_v2_r1_256fs2audma_v2_r1_256fs_s 0
#define reg_sw_en_viva_audma_v2_r1_256fs2audma_v2_r1_256fs_e 0
#define reg_sw_en_viva_audma_v2_r1_256fs2audma_v2_r1_timing_gen ckgen00(0x1BB4)
#define reg_sw_en_viva_audma_v2_r1_256fs2audma_v2_r1_timing_gen_s 0
#define reg_sw_en_viva_audma_v2_r1_256fs2audma_v2_r1_timing_gen_e 0
#define reg_sw_en_viva_audma_v2_r1_synth_ref2audma_v2_r1_synth_ref ckgen00(0x1BB8)
#define reg_sw_en_viva_audma_v2_r1_synth_ref2audma_v2_r1_synth_ref_s 0
#define reg_sw_en_viva_audma_v2_r1_synth_ref2audma_v2_r1_synth_ref_e 0
#define reg_sw_en_viva_audma_v2_r2_256fs2audma_v2_r2_256fs ckgen00(0x1BBC)
#define reg_sw_en_viva_audma_v2_r2_256fs2audma_v2_r2_256fs_s 0
#define reg_sw_en_viva_audma_v2_r2_256fs2audma_v2_r2_256fs_e 0
#define reg_sw_en_viva_audma_v2_r2_256fs2audma_v2_r2_timing_gen ckgen00(0x1BC0)
#define reg_sw_en_viva_audma_v2_r2_256fs2audma_v2_r2_timing_gen_s 0
#define reg_sw_en_viva_audma_v2_r2_256fs2audma_v2_r2_timing_gen_e 0
#define reg_sw_en_viva_audma_v2_r2_synth_ref2audma_v2_r2_synth_ref ckgen00(0x1BC4)
#define reg_sw_en_viva_audma_v2_r2_synth_ref2audma_v2_r2_synth_ref_s 0
#define reg_sw_en_viva_audma_v2_r2_synth_ref2audma_v2_r2_synth_ref_e 0
#define reg_sw_en_viva_bclk_i2s_decoder22bclk_i2s_decoder2 ckgen00(0x1BC8)
#define reg_sw_en_viva_bclk_i2s_decoder22bclk_i2s_decoder2_s 0
#define reg_sw_en_viva_bclk_i2s_decoder22bclk_i2s_decoder2_e 0
#define reg_sw_en_viva_bclk_i2s_decoder2bclk_i2s_decoder ckgen00(0x1BCC)
#define reg_sw_en_viva_bclk_i2s_decoder2bclk_i2s_decoder_s 0
#define reg_sw_en_viva_bclk_i2s_decoder2bclk_i2s_decoder_e 0
#define reg_sw_en_viva_bi2s_synth_ref22i2s_synth_ref2 ckgen00(0x1BD0)
#define reg_sw_en_viva_bi2s_synth_ref22i2s_synth_ref2_s 0
#define reg_sw_en_viva_bi2s_synth_ref22i2s_synth_ref2_e 0
#define reg_sw_en_viva_ch1_256fsi2ch1_256fsi ckgen00(0x1BD4)
#define reg_sw_en_viva_ch1_256fsi2ch1_256fsi_s 0
#define reg_sw_en_viva_ch1_256fsi2ch1_256fsi_e 0
#define reg_sw_en_viva_ch2_256fsi2ch2_256fsi ckgen00(0x1BD8)
#define reg_sw_en_viva_ch2_256fsi2ch2_256fsi_s 0
#define reg_sw_en_viva_ch2_256fsi2ch2_256fsi_e 0
#define reg_sw_en_viva_ch3_256fsi2ch3_256fsi ckgen00(0x1BDC)
#define reg_sw_en_viva_ch3_256fsi2ch3_256fsi_s 0
#define reg_sw_en_viva_ch3_256fsi2ch3_256fsi_e 0
#define reg_sw_en_viva_ch4_256fsi2ch4_256fsi ckgen00(0x1BE0)
#define reg_sw_en_viva_ch4_256fsi2ch4_256fsi_s 0
#define reg_sw_en_viva_ch4_256fsi2ch4_256fsi_e 0
#define reg_sw_en_viva_ch5_256fsi2ch5_256fsi ckgen00(0x1BE4)
#define reg_sw_en_viva_ch5_256fsi2ch5_256fsi_s 0
#define reg_sw_en_viva_ch5_256fsi2ch5_256fsi_e 0
#define reg_sw_en_viva_ch6_256fsi2ch6_256fsi ckgen00(0x1BE8)
#define reg_sw_en_viva_ch6_256fsi2ch6_256fsi_s 0
#define reg_sw_en_viva_ch6_256fsi2ch6_256fsi_e 0
#define reg_sw_en_viva_ch7_256fsi2ch7_256fsi ckgen00(0x1BEC)
#define reg_sw_en_viva_ch7_256fsi2ch7_256fsi_s 0
#define reg_sw_en_viva_ch7_256fsi2ch7_256fsi_e 0
#define reg_sw_en_viva_ch8_256fsi2ch8_256fsi ckgen00(0x1BF0)
#define reg_sw_en_viva_ch8_256fsi2ch8_256fsi_s 0
#define reg_sw_en_viva_ch8_256fsi2ch8_256fsi_e 0
#define reg_sw_en_viva_ch9_256fsi2ch9_256fsi ckgen00(0x1BF4)
#define reg_sw_en_viva_ch9_256fsi2ch9_256fsi_s 0
#define reg_sw_en_viva_ch9_256fsi2ch9_256fsi_e 0
#define reg_sw_en_viva_codec_sh2codec_sh ckgen00(0x1BF8)
#define reg_sw_en_viva_codec_sh2codec_sh_s 0
#define reg_sw_en_viva_codec_sh2codec_sh_e 0
#define reg_sw_en_viva_dac_512fs2dac_512_fs ckgen00(0x1BFC)
#define reg_sw_en_viva_dac_512fs2dac_512_fs_s 0
#define reg_sw_en_viva_dac_512fs2dac_512_fs_e 0
#define reg_sw_en_viva_dsp2dsp_230 ckgen00(0x1C00)
#define reg_sw_en_viva_dsp2dsp_230_s 0
#define reg_sw_en_viva_dsp2dsp_230_e 0
#define reg_sw_en_viva_dsp2dsp_230_1 ckgen00(0x1C04)
#define reg_sw_en_viva_dsp2dsp_230_1_s 0
#define reg_sw_en_viva_dsp2dsp_230_1_e 0
#define reg_sw_en_viva_dsp2dsp_230_2 ckgen00(0x1C08)
#define reg_sw_en_viva_dsp2dsp_230_2_s 0
#define reg_sw_en_viva_dsp2dsp_230_2_e 0
#define reg_sw_en_viva_dsp2dsp_230_3 ckgen00(0x1C0C)
#define reg_sw_en_viva_dsp2dsp_230_3_s 0
#define reg_sw_en_viva_dsp2dsp_230_3_e 0
#define reg_sw_en_viva_dsp2dsp_230_dfs_ref ckgen00(0x1C10)
#define reg_sw_en_viva_dsp2dsp_230_dfs_ref_s 0
#define reg_sw_en_viva_dsp2dsp_230_dfs_ref_e 0
#define reg_sw_en_viva_dsp2dsp_230_tm ckgen00(0x1C14)
#define reg_sw_en_viva_dsp2dsp_230_tm_s 0
#define reg_sw_en_viva_dsp2dsp_230_tm_e 0
#define reg_sw_en_viva_dvb1_synth_ref2dvb1_synth_ref ckgen00(0x1C18)
#define reg_sw_en_viva_dvb1_synth_ref2dvb1_synth_ref_s 0
#define reg_sw_en_viva_dvb1_synth_ref2dvb1_synth_ref_e 0
#define reg_sw_en_viva_dvb1_timing_gen_256fs2dvb1_timing_gen_256fs ckgen00(0x1C1C)
#define reg_sw_en_viva_dvb1_timing_gen_256fs2dvb1_timing_gen_256fs_s 0
#define reg_sw_en_viva_dvb1_timing_gen_256fs2dvb1_timing_gen_256fs_e 0
#define reg_sw_en_viva_dvb2_synth_ref2dvb2_synth_ref ckgen00(0x1C20)
#define reg_sw_en_viva_dvb2_synth_ref2dvb2_synth_ref_s 0
#define reg_sw_en_viva_dvb2_synth_ref2dvb2_synth_ref_e 0
#define reg_sw_en_viva_dvb2_timing_gen_256fs2dvb2_timing_gen_256fs ckgen00(0x1C24)
#define reg_sw_en_viva_dvb2_timing_gen_256fs2dvb2_timing_gen_256fs_s 0
#define reg_sw_en_viva_dvb2_timing_gen_256fs2dvb2_timing_gen_256fs_e 0
#define reg_sw_en_viva_dvb3_synth_ref2dvb3_synth_ref ckgen00(0x1C28)
#define reg_sw_en_viva_dvb3_synth_ref2dvb3_synth_ref_s 0
#define reg_sw_en_viva_dvb3_synth_ref2dvb3_synth_ref_e 0
#define reg_sw_en_viva_dvb3_timing_gen_256fs2dvb3_timing_gen_256fs ckgen00(0x1C2C)
#define reg_sw_en_viva_dvb3_timing_gen_256fs2dvb3_timing_gen_256fs_s 0
#define reg_sw_en_viva_dvb3_timing_gen_256fs2dvb3_timing_gen_256fs_e 0
#define reg_sw_en_viva_dvb4_synth_ref2dvb4_synth_ref ckgen00(0x1C30)
#define reg_sw_en_viva_dvb4_synth_ref2dvb4_synth_ref_s 0
#define reg_sw_en_viva_dvb4_synth_ref2dvb4_synth_ref_e 0
#define reg_sw_en_viva_dvb4_timing_gen_256fs2dvb4_timing_gen_256fs ckgen00(0x1C34)
#define reg_sw_en_viva_dvb4_timing_gen_256fs2dvb4_timing_gen_256fs_s 0
#define reg_sw_en_viva_dvb4_timing_gen_256fs2dvb4_timing_gen_256fs_e 0
#define reg_sw_en_viva_dvb5_timing_gen_256fs2dvb5_timing_gen_256fs ckgen00(0x1C38)
#define reg_sw_en_viva_dvb5_timing_gen_256fs2dvb5_timing_gen_256fs_s 0
#define reg_sw_en_viva_dvb5_timing_gen_256fs2dvb5_timing_gen_256fs_e 0
#define reg_sw_en_viva_dvb6_timing_gen_256fs2dvb6_timing_gen_256fs ckgen00(0x1C3C)
#define reg_sw_en_viva_dvb6_timing_gen_256fs2dvb6_timing_gen_256fs_s 0
#define reg_sw_en_viva_dvb6_timing_gen_256fs2dvb6_timing_gen_256fs_e 0
#define reg_sw_en_viva_earc_tx_32xchxfs2earc_tx_32xchxfs ckgen00(0x1C40)
#define reg_sw_en_viva_earc_tx_32xchxfs2earc_tx_32xchxfs_s 0
#define reg_sw_en_viva_earc_tx_32xchxfs2earc_tx_32xchxfs_e 0
#define reg_sw_en_viva_earc_tx_32xfs2earc_tx_32xfs ckgen00(0x1C44)
#define reg_sw_en_viva_earc_tx_32xfs2earc_tx_32xfs_s 0
#define reg_sw_en_viva_earc_tx_32xfs2earc_tx_32xfs_e 0
#define reg_sw_en_viva_earc_tx_64xchxfs2earc_tx_64xchxfs ckgen00(0x1C48)
#define reg_sw_en_viva_earc_tx_64xchxfs2earc_tx_64xchxfs_s 0
#define reg_sw_en_viva_earc_tx_64xchxfs2earc_tx_64xchxfs_e 0
#define reg_sw_en_viva_earc_tx_gpa_synth_ref2earc_tx_gpa_synth_ref ckgen00(0x1C4C)
#define reg_sw_en_viva_earc_tx_gpa_synth_ref2earc_tx_gpa_synth_ref_s 0
#define reg_sw_en_viva_earc_tx_gpa_synth_ref2earc_tx_gpa_synth_ref_e 0
#define reg_sw_en_viva_earc_tx_pll2earc_tx_pll ckgen00(0x1C50)
#define reg_sw_en_viva_earc_tx_pll2earc_tx_pll_s 0
#define reg_sw_en_viva_earc_tx_pll2earc_tx_pll_e 0
#define reg_sw_en_viva_earc_tx_source_256fs2earc_tx_source_256fs ckgen00(0x1C54)
#define reg_sw_en_viva_earc_tx_source_256fs2earc_tx_source_256fs_s 0
#define reg_sw_en_viva_earc_tx_source_256fs2earc_tx_source_256fs_e 0
#define reg_sw_en_viva_earc_tx_synth_iir_ref2earc_tx_synth_iir_ref ckgen00(0x1C58)
#define reg_sw_en_viva_earc_tx_synth_iir_ref2earc_tx_synth_iir_ref_s 0
#define reg_sw_en_viva_earc_tx_synth_iir_ref2earc_tx_synth_iir_ref_e 0
#define reg_sw_en_viva_earc_tx_synth_ref2earc_tx_synth_ref ckgen00(0x1C5C)
#define reg_sw_en_viva_earc_tx_synth_ref2earc_tx_synth_ref_s 0
#define reg_sw_en_viva_earc_tx_synth_ref2earc_tx_synth_ref_e 0
#define reg_sw_en_viva_fm_demodulator2fm_demodulator ckgen00(0x1C60)
#define reg_sw_en_viva_fm_demodulator2fm_demodulator_s 0
#define reg_sw_en_viva_fm_demodulator2fm_demodulator_e 0
#define reg_sw_en_viva_gpa_240fso2gpa_240fso ckgen00(0x1C64)
#define reg_sw_en_viva_gpa_240fso2gpa_240fso_s 0
#define reg_sw_en_viva_gpa_240fso2gpa_240fso_e 0
#define reg_sw_en_viva_gpa_256fso2gpa_256fso ckgen00(0x1C68)
#define reg_sw_en_viva_gpa_256fso2gpa_256fso_s 0
#define reg_sw_en_viva_gpa_256fso2gpa_256fso_e 0
#define reg_sw_en_viva_gpa_480fso2gpa_480fso ckgen00(0x1C6C)
#define reg_sw_en_viva_gpa_480fso2gpa_480fso_s 0
#define reg_sw_en_viva_gpa_480fso2gpa_480fso_e 0
#define reg_sw_en_viva_hdmi_rx_mpll_4322hdmi_rx_mpll_432 ckgen00(0x1C70)
#define reg_sw_en_viva_hdmi_rx_mpll_4322hdmi_rx_mpll_432_s 0
#define reg_sw_en_viva_hdmi_rx_mpll_4322hdmi_rx_mpll_432_e 0
#define reg_sw_en_viva_hdmi_rx_s2p_128fs2hdmi_rx_s2p_128fs ckgen00(0x1C74)
#define reg_sw_en_viva_hdmi_rx_s2p_128fs2hdmi_rx_s2p_128fs_s 0
#define reg_sw_en_viva_hdmi_rx_s2p_128fs2hdmi_rx_s2p_128fs_e 0
#define reg_sw_en_viva_hdmi_rx_s2p_256fs2hdmi_rx_s2p_256fs ckgen00(0x1C78)
#define reg_sw_en_viva_hdmi_rx_s2p_256fs2hdmi_rx_s2p_256fs_s 0
#define reg_sw_en_viva_hdmi_rx_s2p_256fs2hdmi_rx_s2p_256fs_e 0
#define reg_sw_en_viva_hdmi_rx_synth_ref2hdmi_rx_synth_ref ckgen00(0x1C7C)
#define reg_sw_en_viva_hdmi_rx_synth_ref2hdmi_rx_synth_ref_s 0
#define reg_sw_en_viva_hdmi_rx_synth_ref2hdmi_rx_synth_ref_e 0
#define reg_sw_en_viva_hdmi_rx_v2a_time_stamp2hdmi_rx_v2a_time_stamp ckgen00(0x1C80)
#define reg_sw_en_viva_hdmi_rx_v2a_time_stamp2hdmi_rx_v2a_time_stamp_s 0
#define reg_sw_en_viva_hdmi_rx_v2a_time_stamp2hdmi_rx_v2a_time_stamp_e 0
#define reg_sw_en_viva_hdmi_rx2_mpll_4322hdmi_rx2_mpll_432 ckgen00(0x1C84)
#define reg_sw_en_viva_hdmi_rx2_mpll_4322hdmi_rx2_mpll_432_s 0
#define reg_sw_en_viva_hdmi_rx2_mpll_4322hdmi_rx2_mpll_432_e 0
#define reg_sw_en_viva_hdmi_rx2_s2p_128fs2hdmi_rx2_s2p_128fs ckgen00(0x1C88)
#define reg_sw_en_viva_hdmi_rx2_s2p_128fs2hdmi_rx2_s2p_128fs_s 0
#define reg_sw_en_viva_hdmi_rx2_s2p_128fs2hdmi_rx2_s2p_128fs_e 0
#define reg_sw_en_viva_hdmi_rx2_s2p_256fs2hdmi_rx2_s2p_256fs ckgen00(0x1C8C)
#define reg_sw_en_viva_hdmi_rx2_s2p_256fs2hdmi_rx2_s2p_256fs_s 0
#define reg_sw_en_viva_hdmi_rx2_s2p_256fs2hdmi_rx2_s2p_256fs_e 0
#define reg_sw_en_viva_hdmi_rx2_synth_ref2hdmi_rx2_synth_ref ckgen00(0x1C90)
#define reg_sw_en_viva_hdmi_rx2_synth_ref2hdmi_rx2_synth_ref_s 0
#define reg_sw_en_viva_hdmi_rx2_synth_ref2hdmi_rx2_synth_ref_e 0
#define reg_sw_en_viva_hdmi_rx2_v2a_time_stamp2hdmi_rx2_v2a_time_stamp ckgen00(0x1C94)
#define reg_sw_en_viva_hdmi_rx2_v2a_time_stamp2hdmi_rx2_v2a_time_stamp_s 0
#define reg_sw_en_viva_hdmi_rx2_v2a_time_stamp2hdmi_rx2_v2a_time_stamp_e 0
#define reg_sw_en_viva_hdmi_tx_128fs2hdmi_tx_128fs ckgen00(0x1C98)
#define reg_sw_en_viva_hdmi_tx_128fs2hdmi_tx_128fs_s 0
#define reg_sw_en_viva_hdmi_tx_128fs2hdmi_tx_128fs_e 0
#define reg_sw_en_viva_hdmi_tx_256fs2hdmi_tx_256fs ckgen00(0x1C9C)
#define reg_sw_en_viva_hdmi_tx_256fs2hdmi_tx_256fs_s 0
#define reg_sw_en_viva_hdmi_tx_256fs2hdmi_tx_256fs_e 0
#define reg_sw_en_viva_i2s_2_bclk_synth_ref2i2s_2_bclk_synth_ref ckgen00(0x1CA0)
#define reg_sw_en_viva_i2s_2_bclk_synth_ref2i2s_2_bclk_synth_ref_s 0
#define reg_sw_en_viva_i2s_2_bclk_synth_ref2i2s_2_bclk_synth_ref_e 0
#define reg_sw_en_viva_i2s_bclk_dg22i2s_bclk_dg2 ckgen00(0x1CA4)
#define reg_sw_en_viva_i2s_bclk_dg22i2s_bclk_dg2_s 0
#define reg_sw_en_viva_i2s_bclk_dg22i2s_bclk_dg2_e 0
#define reg_sw_en_viva_i2s_bclk_dg2i2s_bclk_dg ckgen00(0x1CA8)
#define reg_sw_en_viva_i2s_bclk_dg2i2s_bclk_dg_s 0
#define reg_sw_en_viva_i2s_bclk_dg2i2s_bclk_dg_e 0
#define reg_sw_en_viva_i2s_bclk_synth_ref2i2s_bclk_synth_ref ckgen00(0x1CAC)
#define reg_sw_en_viva_i2s_bclk_synth_ref2i2s_bclk_synth_ref_s 0
#define reg_sw_en_viva_i2s_bclk_synth_ref2i2s_bclk_synth_ref_e 0
#define reg_sw_en_viva_i2s_mclk_synth_ref2i2s_mclk_synth_ref ckgen00(0x1CB0)
#define reg_sw_en_viva_i2s_mclk_synth_ref2i2s_mclk_synth_ref_s 0
#define reg_sw_en_viva_i2s_mclk_synth_ref2i2s_mclk_synth_ref_e 0
#define reg_sw_en_viva_i2s_synth_ref2i2s_synth_ref ckgen00(0x1CB4)
#define reg_sw_en_viva_i2s_synth_ref2i2s_synth_ref_s 0
#define reg_sw_en_viva_i2s_synth_ref2i2s_synth_ref_e 0
#define reg_sw_en_viva_i2s_trx_bclk_timing_gen2i2s_trx_bclk_timing_gen ckgen00(0x1CB8)
#define reg_sw_en_viva_i2s_trx_bclk_timing_gen2i2s_trx_bclk_timing_gen_s 0
#define reg_sw_en_viva_i2s_trx_bclk_timing_gen2i2s_trx_bclk_timing_gen_e 0
#define reg_sw_en_viva_i2s_trx_synth_ref2i2s_trx_synth_ref ckgen00(0x1CBC)
#define reg_sw_en_viva_i2s_trx_synth_ref2i2s_trx_synth_ref_s 0
#define reg_sw_en_viva_i2s_trx_synth_ref2i2s_trx_synth_ref_e 0
#define reg_sw_en_viva_i2s_tx_fifo_256fs2i2s_tx_fifo_256fs ckgen00(0x1CC0)
#define reg_sw_en_viva_i2s_tx_fifo_256fs2i2s_tx_fifo_256fs_s 0
#define reg_sw_en_viva_i2s_tx_fifo_256fs2i2s_tx_fifo_256fs_e 0
#define reg_sw_en_viva_mclk_i2s_decoder22mclk_i2s_decoder2 ckgen00(0x1CC4)
#define reg_sw_en_viva_mclk_i2s_decoder22mclk_i2s_decoder2_s 0
#define reg_sw_en_viva_mclk_i2s_decoder22mclk_i2s_decoder2_e 0
#define reg_sw_en_viva_mclk_i2s_decoder2mclk_i2s_decoder ckgen00(0x1CC8)
#define reg_sw_en_viva_mclk_i2s_decoder2mclk_i2s_decoder_s 0
#define reg_sw_en_viva_mclk_i2s_decoder2mclk_i2s_decoder_e 0
#define reg_sw_en_viva_npcm_synth_ref2npcm_synth_ref ckgen00(0x1CCC)
#define reg_sw_en_viva_npcm_synth_ref2npcm_synth_ref_s 0
#define reg_sw_en_viva_npcm_synth_ref2npcm_synth_ref_e 0
#define reg_sw_en_viva_npcm2_synth_ref2npcm2_synth_ref ckgen00(0x1CD0)
#define reg_sw_en_viva_npcm2_synth_ref2npcm2_synth_ref_s 0
#define reg_sw_en_viva_npcm2_synth_ref2npcm2_synth_ref_e 0
#define reg_sw_en_viva_npcm3_synth_ref2npcm3_synth_ref ckgen00(0x1CD4)
#define reg_sw_en_viva_npcm3_synth_ref2npcm3_synth_ref_s 0
#define reg_sw_en_viva_npcm3_synth_ref2npcm3_synth_ref_e 0
#define reg_sw_en_viva_npcm4_256fs_timing_gen2npcm4_256fs_timing_gen ckgen00(0x1CD8)
#define reg_sw_en_viva_npcm4_256fs_timing_gen2npcm4_256fs_timing_gen_s 0
#define reg_sw_en_viva_npcm4_256fs_timing_gen2npcm4_256fs_timing_gen_e 0
#define reg_sw_en_viva_npcm4_synth_ref2npcm4_synth_ref ckgen00(0x1CDC)
#define reg_sw_en_viva_npcm4_synth_ref2npcm4_synth_ref_s 0
#define reg_sw_en_viva_npcm4_synth_ref2npcm4_synth_ref_e 0
#define reg_sw_en_viva_npcm5_256fs_timing_gen2npcm5_256fs_timing_gen ckgen00(0x1CE0)
#define reg_sw_en_viva_npcm5_256fs_timing_gen2npcm5_256fs_timing_gen_s 0
#define reg_sw_en_viva_npcm5_256fs_timing_gen2npcm5_256fs_timing_gen_e 0
#define reg_sw_en_viva_npcm5_synth_ref2npcm5_synth_ref ckgen00(0x1CE4)
#define reg_sw_en_viva_npcm5_synth_ref2npcm5_synth_ref_s 0
#define reg_sw_en_viva_npcm5_synth_ref2npcm5_synth_ref_e 0
#define reg_sw_en_viva_pcm_clk_2162pcm_clk_216 ckgen00(0x1CE8)
#define reg_sw_en_viva_pcm_clk_2162pcm_clk_216_s 0
#define reg_sw_en_viva_pcm_clk_2162pcm_clk_216_e 0
#define reg_sw_en_viva_pcm_clk_aupll2pcm_clk_aupll ckgen00(0x1CEC)
#define reg_sw_en_viva_pcm_clk_aupll2pcm_clk_aupll_s 0
#define reg_sw_en_viva_pcm_clk_aupll2pcm_clk_aupll_e 0
#define reg_sw_en_viva_r2_wb2r2_wb ckgen00(0x1CF0)
#define reg_sw_en_viva_r2_wb2r2_wb_s 0
#define reg_sw_en_viva_r2_wb2r2_wb_e 0
#define reg_sw_en_viva_riu_brg_r22r2_riu_brg ckgen00(0x1CF4)
#define reg_sw_en_viva_riu_brg_r22r2_riu_brg_s 0
#define reg_sw_en_viva_riu_brg_r22r2_riu_brg_e 0
#define reg_sw_en_viva_riu_r22riu_r2 ckgen00(0x1CF8)
#define reg_sw_en_viva_riu_r22riu_r2_s 0
#define reg_sw_en_viva_riu_r22riu_r2_e 0
#define reg_sw_en_viva_sh2ch1_sh ckgen00(0x1CFC)
#define reg_sw_en_viva_sh2ch1_sh_s 0
#define reg_sw_en_viva_sh2ch1_sh_e 0
#define reg_sw_en_viva_sh2ch2_sh ckgen00(0x1D00)
#define reg_sw_en_viva_sh2ch2_sh_s 0
#define reg_sw_en_viva_sh2ch2_sh_e 0
#define reg_sw_en_viva_sh2ch3_sh ckgen00(0x1D04)
#define reg_sw_en_viva_sh2ch3_sh_s 0
#define reg_sw_en_viva_sh2ch3_sh_e 0
#define reg_sw_en_viva_sh2ch4_sh ckgen00(0x1D08)
#define reg_sw_en_viva_sh2ch4_sh_s 0
#define reg_sw_en_viva_sh2ch4_sh_e 0
#define reg_sw_en_viva_sh2ch5_sh ckgen00(0x1D0C)
#define reg_sw_en_viva_sh2ch5_sh_s 0
#define reg_sw_en_viva_sh2ch5_sh_e 0
#define reg_sw_en_viva_sh2ch6_sh ckgen00(0x1D10)
#define reg_sw_en_viva_sh2ch6_sh_s 0
#define reg_sw_en_viva_sh2ch6_sh_e 0
#define reg_sw_en_viva_sh2ch7_sh ckgen00(0x1D14)
#define reg_sw_en_viva_sh2ch7_sh_s 0
#define reg_sw_en_viva_sh2ch7_sh_e 0
#define reg_sw_en_viva_sh2ch8_sh ckgen00(0x1D18)
#define reg_sw_en_viva_sh2ch8_sh_s 0
#define reg_sw_en_viva_sh2ch8_sh_e 0
#define reg_sw_en_viva_sh2ch9_sh ckgen00(0x1D1C)
#define reg_sw_en_viva_sh2ch9_sh_s 0
#define reg_sw_en_viva_sh2ch9_sh_e 0
#define reg_sw_en_viva_sif_adc_cic2sif_adc_cic ckgen00(0x1D20)
#define reg_sw_en_viva_sif_adc_cic2sif_adc_cic_s 0
#define reg_sw_en_viva_sif_adc_cic2sif_adc_cic_e 0
#define reg_sw_en_viva_sif_adc_r2b_fifo_in2sif_adc_r2b_fifo_in ckgen00(0x1D24)
#define reg_sw_en_viva_sif_adc_r2b_fifo_in2sif_adc_r2b_fifo_in_s 0
#define reg_sw_en_viva_sif_adc_r2b_fifo_in2sif_adc_r2b_fifo_in_e 0
#define reg_sw_en_viva_sif_adc_r2b2sif_adc_r2b ckgen00(0x1D28)
#define reg_sw_en_viva_sif_adc_r2b2sif_adc_r2b_s 0
#define reg_sw_en_viva_sif_adc_r2b2sif_adc_r2b_e 0
#define reg_sw_en_viva_sif_cordic2sif_cordic ckgen00(0x1D2C)
#define reg_sw_en_viva_sif_cordic2sif_cordic_s 0
#define reg_sw_en_viva_sif_cordic2sif_cordic_e 0
#define reg_sw_en_viva_sif_synth2sif_synth ckgen00(0x1D30)
#define reg_sw_en_viva_sif_synth2sif_synth_s 0
#define reg_sw_en_viva_sif_synth2sif_synth_e 0
#define reg_sw_en_viva_sin_gen2sin_gen ckgen00(0x1D34)
#define reg_sw_en_viva_sin_gen2sin_gen_s 0
#define reg_sw_en_viva_sin_gen2sin_gen_e 0
#define reg_sw_en_viva_spdif_rx_128fs2spdif_rx_128fs ckgen00(0x1D38)
#define reg_sw_en_viva_spdif_rx_128fs2spdif_rx_128fs_s 0
#define reg_sw_en_viva_spdif_rx_128fs2spdif_rx_128fs_e 0
#define reg_sw_en_viva_spdif_rx_dg2spdif_rx_dg ckgen00(0x1D3C)
#define reg_sw_en_viva_spdif_rx_dg2spdif_rx_dg_s 0
#define reg_sw_en_viva_spdif_rx_dg2spdif_rx_dg_e 0
#define reg_sw_en_viva_spdif_rx_synth_ref2spdif_rx_synth_ref ckgen00(0x1D40)
#define reg_sw_en_viva_spdif_rx_synth_ref2spdif_rx_synth_ref_s 0
#define reg_sw_en_viva_spdif_rx_synth_ref2spdif_rx_synth_ref_e 0
#define reg_sw_en_viva_spdif_tx_128fs2spdif_tx_128fs ckgen00(0x1D44)
#define reg_sw_en_viva_spdif_tx_128fs2spdif_tx_128fs_s 0
#define reg_sw_en_viva_spdif_tx_128fs2spdif_tx_128fs_e 0
#define reg_sw_en_viva_spdif_tx_256fs2spdif_tx_256fs ckgen00(0x1D48)
#define reg_sw_en_viva_spdif_tx_256fs2spdif_tx_256fs_s 0
#define reg_sw_en_viva_spdif_tx_256fs2spdif_tx_256fs_e 0
#define reg_sw_en_viva_spdif_tx_synth_ref2spdif_tx_synth_ref ckgen00(0x1D4C)
#define reg_sw_en_viva_spdif_tx_synth_ref2spdif_tx_synth_ref_s 0
#define reg_sw_en_viva_spdif_tx_synth_ref2spdif_tx_synth_ref_e 0
#define reg_sw_en_viva_spdif_tx2_128fs2spdif_tx2_128fs ckgen00(0x1D50)
#define reg_sw_en_viva_spdif_tx2_128fs2spdif_tx2_128fs_s 0
#define reg_sw_en_viva_spdif_tx2_128fs2spdif_tx2_128fs_e 0
#define reg_sw_en_viva_spdif_tx2_256fs2spdif_tx2_256fs ckgen00(0x1D54)
#define reg_sw_en_viva_spdif_tx2_256fs2spdif_tx2_256fs_s 0
#define reg_sw_en_viva_spdif_tx2_256fs2spdif_tx2_256fs_e 0
#define reg_sw_en_viva_synth_2nd_order2synth_2nd_order ckgen00(0x1D58)
#define reg_sw_en_viva_synth_2nd_order2synth_2nd_order_s 0
#define reg_sw_en_viva_synth_2nd_order2synth_2nd_order_e 0
#define reg_sw_en_viva_synth_codec2synth_codec ckgen00(0x1D5C)
#define reg_sw_en_viva_synth_codec2synth_codec_s 0
#define reg_sw_en_viva_synth_codec2synth_codec_e 0
#define reg_sw_en_viva_test_bus2test_bus ckgen00(0x1D60)
#define reg_sw_en_viva_test_bus2test_bus_s 0
#define reg_sw_en_viva_test_bus2test_bus_e 0
#define reg_sw_en_viva_vbdma_mcu2vbdma_mcu ckgen00(0x1D64)
#define reg_sw_en_viva_vbdma_mcu2vbdma_mcu_s 0
#define reg_sw_en_viva_vbdma_mcu2vbdma_mcu_e 0
#define reg_sw_en_viva_xtal_12m2xtal ckgen00(0x1D68)
#define reg_sw_en_viva_xtal_12m2xtal_s 0
#define reg_sw_en_viva_xtal_12m2xtal_e 0
#define reg_sw_en_xtal_12m2audio_r2 ckgen00(0x1D68)
#define reg_sw_en_xtal_12m2audio_r2_s 1
#define reg_sw_en_xtal_12m2audio_r2_e 1
#define reg_sw_en_viva_xtal_24m2xtal ckgen00(0x1D6C)
#define reg_sw_en_viva_xtal_24m2xtal_s 0
#define reg_sw_en_viva_xtal_24m2xtal_e 0
#define reg_sw_en_rv_tck2rv55audio ckgen00(0x1D70)
#define reg_sw_en_rv_tck2rv55audio_s 0
#define reg_sw_en_rv_tck2rv55audio_e 0
#define reg_sw_en_rv55audio2rv55audio ckgen00(0x1D74)
#define reg_sw_en_rv55audio2rv55audio_s 0
#define reg_sw_en_rv55audio2rv55audio_e 0
#define reg_sw_en_rv55audio2rv55dfs ckgen00(0x1D74)
#define reg_sw_en_rv55audio2rv55dfs_s 1
#define reg_sw_en_rv55audio2rv55dfs_e 1
#define reg_sw_en_mcu_wb2rv55audio ckgen00(0x1D78)
#define reg_sw_en_mcu_wb2rv55audio_s 0
#define reg_sw_en_mcu_wb2rv55audio_e 0
#define reg_sw_en_viva_i2s_tx_2_fifo_256fs2i2s_tx_2_fifo_256fs ckgen00(0x1D7C)
#define reg_sw_en_viva_i2s_tx_2_fifo_256fs2i2s_tx_2_fifo_256fs_s 0
#define reg_sw_en_viva_i2s_tx_2_fifo_256fs2i2s_tx_2_fifo_256fs_e 0
#define reg_sw_en_gpd2gpd ckgen00(0x1D90)
#define reg_sw_en_gpd2gpd_s 0
#define reg_sw_en_gpd2gpd_e 0
#define reg_sw_en_njpd2jpd ckgen00(0x1D98)
#define reg_sw_en_njpd2jpd_s 0
#define reg_sw_en_njpd2jpd_e 0
#define reg_sw_en_vdec_bus2core0 ckgen00(0x1DA0)
#define reg_sw_en_vdec_bus2core0_s 0
#define reg_sw_en_vdec_bus2core0_e 0
#define reg_sw_en_vdec_bus2core1 ckgen00(0x1DA0)
#define reg_sw_en_vdec_bus2core1_s 1
#define reg_sw_en_vdec_bus2core1_e 1
#define reg_sw_en_vdec_bus2core2 ckgen00(0x1DA0)
#define reg_sw_en_vdec_bus2core2_s 2
#define reg_sw_en_vdec_bus2core2_e 2
#define reg_sw_en_gce_f26m2gce_biu ckgen00(0x1DA0)
#define reg_sw_en_gce_f26m2gce_biu_s 3
#define reg_sw_en_gce_f26m2gce_biu_e 3
#define reg_sw_en_vdec_bus2soc ckgen00(0x1DA4)
#define reg_sw_en_vdec_bus2soc_s 0
#define reg_sw_en_vdec_bus2soc_e 0
#define reg_sw_en_vdec_lat02soc ckgen00(0x1DA8)
#define reg_sw_en_vdec_lat02soc_s 0
#define reg_sw_en_vdec_lat02soc_e 0
#define reg_sw_en_vdec_lat12soc ckgen00(0x1DAC)
#define reg_sw_en_vdec_lat12soc_s 0
#define reg_sw_en_vdec_lat12soc_e 0
#define reg_sw_en_vdec_sys2core0 ckgen00(0x1DAC)
#define reg_sw_en_vdec_sys2core0_s 1
#define reg_sw_en_vdec_sys2core0_e 1
#define reg_sw_en_vdec_sys2core1 ckgen00(0x1DAC)
#define reg_sw_en_vdec_sys2core1_s 3
#define reg_sw_en_vdec_sys2core1_e 3
#define reg_sw_en_vdec_sys2core2 ckgen00(0x1DAC)
#define reg_sw_en_vdec_sys2core2_s 4
#define reg_sw_en_vdec_sys2core2_e 4
#define reg_sw_en_vdec_sys2soc ckgen00(0x1DB0)
#define reg_sw_en_vdec_sys2soc_s 0
#define reg_sw_en_vdec_sys2soc_e 0
#define reg_sw_en_xtal_24m2core0 ckgen00(0x1DB0)
#define reg_sw_en_xtal_24m2core0_s 1
#define reg_sw_en_xtal_24m2core0_e 1
#define reg_sw_en_xtal_24m2core1 ckgen00(0x1DB0)
#define reg_sw_en_xtal_24m2core1_s 2
#define reg_sw_en_xtal_24m2core1_e 2
#define reg_sw_en_xtal_24m2core2 ckgen00(0x1DB4)
#define reg_sw_en_xtal_24m2core2_s 3
#define reg_sw_en_xtal_24m2core2_e 3
#define reg_sw_en_viva_ch10_256fsi2ch10_256fsi ckgen00(0x1E00)
#define reg_sw_en_viva_ch10_256fsi2ch10_256fsi_s 0
#define reg_sw_en_viva_ch10_256fsi2ch10_256fsi_e 0
#define reg_sw_en_viva_ch_m1_256fsi2ch_m1_256fsi ckgen00(0x1E04)
#define reg_sw_en_viva_ch_m1_256fsi2ch_m1_256fsi_s 0
#define reg_sw_en_viva_ch_m1_256fsi2ch_m1_256fsi_e 0
#define reg_sw_en_viva_ch_m2_256fsi2ch_m2_256fsi ckgen00(0x1E08)
#define reg_sw_en_viva_ch_m2_256fsi2ch_m2_256fsi_s 0
#define reg_sw_en_viva_ch_m2_256fsi2ch_m2_256fsi_e 0
#define reg_sw_en_viva_ch_m3_256fsi2ch_m3_256fsi ckgen00(0x1E0C)
#define reg_sw_en_viva_ch_m3_256fsi2ch_m3_256fsi_s 0
#define reg_sw_en_viva_ch_m3_256fsi2ch_m3_256fsi_e 0
#define reg_sw_en_viva_ch_m4_256fsi2ch_m4_256fsi ckgen00(0x1E10)
#define reg_sw_en_viva_ch_m4_256fsi2ch_m4_256fsi_s 0
#define reg_sw_en_viva_ch_m4_256fsi2ch_m4_256fsi_e 0
#define reg_sw_en_viva_ch_m5_256fsi2ch_m5_256fsi ckgen00(0x1E14)
#define reg_sw_en_viva_ch_m5_256fsi2ch_m5_256fsi_s 0
#define reg_sw_en_viva_ch_m5_256fsi2ch_m5_256fsi_e 0
#define reg_sw_en_viva_ch_m6_256fsi2ch_m6_256fsi ckgen00(0x1E18)
#define reg_sw_en_viva_ch_m6_256fsi2ch_m6_256fsi_s 0
#define reg_sw_en_viva_ch_m6_256fsi2ch_m6_256fsi_e 0
#define reg_sw_en_viva_ch_m7_256fsi2ch_m7_256fsi ckgen00(0x1E1C)
#define reg_sw_en_viva_ch_m7_256fsi2ch_m7_256fsi_s 0
#define reg_sw_en_viva_ch_m7_256fsi2ch_m7_256fsi_e 0
#define reg_sw_en_viva_ch_m8_256fsi2ch_m8_256fsi ckgen00(0x1E20)
#define reg_sw_en_viva_ch_m8_256fsi2ch_m8_256fsi_s 0
#define reg_sw_en_viva_ch_m8_256fsi2ch_m8_256fsi_e 0
#define reg_sw_en_viva_ch_m9_256fsi2ch_m9_256fsi ckgen00(0x1E24)
#define reg_sw_en_viva_ch_m9_256fsi2ch_m9_256fsi_s 0
#define reg_sw_en_viva_ch_m9_256fsi2ch_m9_256fsi_e 0
#define reg_sw_en_viva_ch_m10_256fsi2ch_m10_256fsi ckgen00(0x1E28)
#define reg_sw_en_viva_ch_m10_256fsi2ch_m10_256fsi_s 0
#define reg_sw_en_viva_ch_m10_256fsi2ch_m10_256fsi_e 0
#define reg_sw_en_viva_ch_m11_256fsi2ch_m11_256fsi ckgen00(0x1E2C)
#define reg_sw_en_viva_ch_m11_256fsi2ch_m11_256fsi_s 0
#define reg_sw_en_viva_ch_m11_256fsi2ch_m11_256fsi_e 0
#define reg_sw_en_viva_ch_m12_256fsi2ch_m12_256fsi ckgen00(0x1E30)
#define reg_sw_en_viva_ch_m12_256fsi2ch_m12_256fsi_s 0
#define reg_sw_en_viva_ch_m12_256fsi2ch_m12_256fsi_e 0
#define reg_sw_en_viva_ch_m13_256fsi2ch_m13_256fsi ckgen00(0x1E34)
#define reg_sw_en_viva_ch_m13_256fsi2ch_m13_256fsi_s 0
#define reg_sw_en_viva_ch_m13_256fsi2ch_m13_256fsi_e 0
#define reg_sw_en_viva_ch_m14_256fsi2ch_m14_256fsi ckgen00(0x1E38)
#define reg_sw_en_viva_ch_m14_256fsi2ch_m14_256fsi_s 0
#define reg_sw_en_viva_ch_m14_256fsi2ch_m14_256fsi_e 0
#define reg_sw_en_viva_ch_m15_256fsi2ch_m15_256fsi ckgen00(0x1E3C)
#define reg_sw_en_viva_ch_m15_256fsi2ch_m15_256fsi_s 0
#define reg_sw_en_viva_ch_m15_256fsi2ch_m15_256fsi_e 0
#define reg_sw_en_viva_ch_m16_256fsi2ch_m16_256fsi ckgen00(0x1E40)
#define reg_sw_en_viva_ch_m16_256fsi2ch_m16_256fsi_s 0
#define reg_sw_en_viva_ch_m16_256fsi2ch_m16_256fsi_e 0
#define reg_sw_en_viva_i2s_tdm_1x16tx32b_bclk2viva_i2s_tdm_1x16tx32b_bclk ckgen00(0x1E44)
#define reg_sw_en_viva_i2s_tdm_1x16tx32b_bclk2viva_i2s_tdm_1x16tx32b_bclk_s 0
#define reg_sw_en_viva_i2s_tdm_1x16tx32b_bclk2viva_i2s_tdm_1x16tx32b_bclk_e 0
#define reg_sw_en_viva_i2s_tdm_1x16tx32b_fifo2viva_i2s_tdm_1x16tx32b_fifo ckgen00(0x1E48)
#define reg_sw_en_viva_i2s_tdm_1x16tx32b_fifo2viva_i2s_tdm_1x16tx32b_fifo_s 0
#define reg_sw_en_viva_i2s_tdm_1x16tx32b_fifo2viva_i2s_tdm_1x16tx32b_fifo_e 0
#define reg_sw_en_viva_i2s_tdm_6x16tx32b_bclk2i2s_tdm_6x16tx32b_bclk ckgen00(0x1E4C)
#define reg_sw_en_viva_i2s_tdm_6x16tx32b_bclk2i2s_tdm_6x16tx32b_bclk_s 0
#define reg_sw_en_viva_i2s_tdm_6x16tx32b_bclk2i2s_tdm_6x16tx32b_bclk_e 0
#define reg_sw_en_viva_i2s_tdm_6x16tx32b_fifo2viva_i2s_tdm_6x16tx32b_fifo ckgen00(0x1E50)
#define reg_sw_en_viva_i2s_tdm_6x16tx32b_fifo2viva_i2s_tdm_6x16tx32b_fifo_s 0
#define reg_sw_en_viva_i2s_tdm_6x16tx32b_fifo2viva_i2s_tdm_6x16tx32b_fifo_e 0
#define reg_sw_en_viva_sh2ch10_sh ckgen00(0x1E54)
#define reg_sw_en_viva_sh2ch10_sh_s 0
#define reg_sw_en_viva_sh2ch10_sh_e 0
#define reg_sw_en_viva_sh2ch_m1_sh ckgen00(0x1E58)
#define reg_sw_en_viva_sh2ch_m1_sh_s 0
#define reg_sw_en_viva_sh2ch_m1_sh_e 0
#define reg_sw_en_viva_sh2ch_m2_sh ckgen00(0x1E5C)
#define reg_sw_en_viva_sh2ch_m2_sh_s 0
#define reg_sw_en_viva_sh2ch_m2_sh_e 0
#define reg_sw_en_viva_sh2ch_m3_sh ckgen00(0x1E60)
#define reg_sw_en_viva_sh2ch_m3_sh_s 0
#define reg_sw_en_viva_sh2ch_m3_sh_e 0
#define reg_sw_en_viva_sh2ch_m4_sh ckgen00(0x1E64)
#define reg_sw_en_viva_sh2ch_m4_sh_s 0
#define reg_sw_en_viva_sh2ch_m4_sh_e 0
#define reg_sw_en_viva_sh2ch_m5_sh ckgen00(0x1E68)
#define reg_sw_en_viva_sh2ch_m5_sh_s 0
#define reg_sw_en_viva_sh2ch_m5_sh_e 0
#define reg_sw_en_viva_sh2ch_m6_sh ckgen00(0x1E6C)
#define reg_sw_en_viva_sh2ch_m6_sh_s 0
#define reg_sw_en_viva_sh2ch_m6_sh_e 0
#define reg_sw_en_viva_sh2ch_m7_sh ckgen00(0x1E70)
#define reg_sw_en_viva_sh2ch_m7_sh_s 0
#define reg_sw_en_viva_sh2ch_m7_sh_e 0
#define reg_sw_en_viva_sh2ch_m8_sh ckgen00(0x1E74)
#define reg_sw_en_viva_sh2ch_m8_sh_s 0
#define reg_sw_en_viva_sh2ch_m8_sh_e 0
#define reg_sw_en_viva_sh2ch_m9_sh ckgen00(0x1E78)
#define reg_sw_en_viva_sh2ch_m9_sh_s 0
#define reg_sw_en_viva_sh2ch_m9_sh_e 0
#define reg_sw_en_viva_sh2ch_m10_sh ckgen00(0x1E7C)
#define reg_sw_en_viva_sh2ch_m10_sh_s 0
#define reg_sw_en_viva_sh2ch_m10_sh_e 0
#define reg_sw_en_viva_sh2ch_m11_sh ckgen00(0x1E80)
#define reg_sw_en_viva_sh2ch_m11_sh_s 0
#define reg_sw_en_viva_sh2ch_m11_sh_e 0
#define reg_sw_en_viva_sh2ch_m12_sh ckgen00(0x1E84)
#define reg_sw_en_viva_sh2ch_m12_sh_s 0
#define reg_sw_en_viva_sh2ch_m12_sh_e 0
#define reg_sw_en_viva_sh2ch_m13_sh ckgen00(0x1E88)
#define reg_sw_en_viva_sh2ch_m13_sh_s 0
#define reg_sw_en_viva_sh2ch_m13_sh_e 0
#define reg_sw_en_viva_sh2ch_m14_sh ckgen00(0x1E8C)
#define reg_sw_en_viva_sh2ch_m14_sh_s 0
#define reg_sw_en_viva_sh2ch_m14_sh_e 0
#define reg_sw_en_viva_sh2ch_m15_sh ckgen00(0x1E90)
#define reg_sw_en_viva_sh2ch_m15_sh_s 0
#define reg_sw_en_viva_sh2ch_m15_sh_e 0
#define reg_sw_en_viva_sh2ch_m16_sh ckgen00(0x1E94)
#define reg_sw_en_viva_sh2ch_m16_sh_s 0
#define reg_sw_en_viva_sh2ch_m16_sh_e 0
#define reg_sw_en_viva_src_mac_bspline2src_mac_bspline ckgen00(0x1E98)
#define reg_sw_en_viva_src_mac_bspline2src_mac_bspline_s 0
#define reg_sw_en_viva_src_mac_bspline2src_mac_bspline_e 0
#define reg_pd_sys3pll ckgen00(0x1EC0)
#define reg_pd_sys3pll_s 0
#define reg_pd_sys3pll_e 0
#define reg_pd_sys3pll_clk_div2p5 ckgen00(0x1EC0)
#define reg_pd_sys3pll_clk_div2p5_s 4
#define reg_pd_sys3pll_clk_div2p5_e 4
#define reg_pd_sys3pll_clk_div2 ckgen00(0x1EC0)
#define reg_pd_sys3pll_clk_div2_s 8
#define reg_pd_sys3pll_clk_div2_e 8
#define reg_pd_sys3pll_clk_div3 ckgen00(0x1EC0)
#define reg_pd_sys3pll_clk_div3_s 12
#define reg_pd_sys3pll_clk_div3_e 12
#define reg_pd_sys3pll_clk_div5 ckgen00(0x1EC4)
#define reg_pd_sys3pll_clk_div5_s 0
#define reg_pd_sys3pll_clk_div5_e 0
#define reg_pd_sys3pll_postdiv ckgen00(0x1EC4)
#define reg_pd_sys3pll_postdiv_s 4
#define reg_pd_sys3pll_postdiv_e 4
#define reg_pd_sys3pll_clk_div30 ckgen00(0x1EC4)
#define reg_pd_sys3pll_clk_div30_s 8
#define reg_pd_sys3pll_clk_div30_e 8
#define reg_en_sys3pll_vco_div3 ckgen00(0x1EC8)
#define reg_en_sys3pll_vco_div3_s 0
#define reg_en_sys3pll_vco_div3_e 0
#define reg_en_sys3pll_occ_div128 ckgen00(0x1EC8)
#define reg_en_sys3pll_occ_div128_s 4
#define reg_en_sys3pll_occ_div128_e 4
#define reg_en_sys3pll_xtal ckgen00(0x1EC8)
#define reg_en_sys3pll_xtal_s 8
#define reg_en_sys3pll_xtal_e 8
#define reg_en_sys3pll_test ckgen00(0x1EC8)
#define reg_en_sys3pll_test_s 12
#define reg_en_sys3pll_test_e 12
#define reg_en_sys3pll_prdt ckgen00(0x1ECC)
#define reg_en_sys3pll_prdt_s 0
#define reg_en_sys3pll_prdt_e 0
#define reg_en_sys3pll_rst ckgen00(0x1ECC)
#define reg_en_sys3pll_rst_s 4
#define reg_en_sys3pll_rst_e 4
#define reg_gc_sys3pll_input_div ckgen00(0x1ED0)
#define reg_gc_sys3pll_input_div_s 0
#define reg_gc_sys3pll_input_div_e 1
#define reg_gc_sys3pll_cp_sw ckgen00(0x1ED4)
#define reg_gc_sys3pll_cp_sw_s 0
#define reg_gc_sys3pll_cp_sw_e 1
#define reg_gc_sys3pll_ictrl ckgen00(0x1ED4)
#define reg_gc_sys3pll_ictrl_s 8
#define reg_gc_sys3pll_ictrl_e 10
#define reg_gc_sys3pll_output_div_first ckgen00(0x1ED8)
#define reg_gc_sys3pll_output_div_first_s 0
#define reg_gc_sys3pll_output_div_first_e 1
#define reg_gc_sys3pll_output_div ckgen00(0x1ED8)
#define reg_gc_sys3pll_output_div_s 8
#define reg_gc_sys3pll_output_div_e 10
#define reg_gc_sys3pll_loopdiv_first ckgen00(0x1EDC)
#define reg_gc_sys3pll_loopdiv_first_s 0
#define reg_gc_sys3pll_loopdiv_first_e 1
#define reg_gc_sys3pll_loopdiv_second ckgen00(0x1EE0)
#define reg_gc_sys3pll_loopdiv_second_s 0
#define reg_gc_sys3pll_loopdiv_second_e 7
#define reg_ro_sys3pll_lock ckgen00(0x1EE8)
#define reg_ro_sys3pll_lock_s 0
#define reg_ro_sys3pll_lock_e 0
#define reg_test_sys3pll ckgen00(0x1EF8)
#define reg_test_sys3pll_s 0
#define reg_test_sys3pll_e 15
#define reg_pd_gpubrdgpll ckgen00(0x1F00)
#define reg_pd_gpubrdgpll_s 0
#define reg_pd_gpubrdgpll_e 0
#define reg_pd_gpubrdgpll_clk_div2p5 ckgen00(0x1F00)
#define reg_pd_gpubrdgpll_clk_div2p5_s 4
#define reg_pd_gpubrdgpll_clk_div2p5_e 4
#define reg_pd_gpubrdgpll_clk_div2 ckgen00(0x1F00)
#define reg_pd_gpubrdgpll_clk_div2_s 8
#define reg_pd_gpubrdgpll_clk_div2_e 8
#define reg_pd_gpubrdgpll_clk_div3 ckgen00(0x1F00)
#define reg_pd_gpubrdgpll_clk_div3_s 12
#define reg_pd_gpubrdgpll_clk_div3_e 12
#define reg_pd_gpubrdgpll_clk_div5 ckgen00(0x1F04)
#define reg_pd_gpubrdgpll_clk_div5_s 0
#define reg_pd_gpubrdgpll_clk_div5_e 0
#define reg_pd_gpubrdgpll_postdiv ckgen00(0x1F04)
#define reg_pd_gpubrdgpll_postdiv_s 4
#define reg_pd_gpubrdgpll_postdiv_e 4
#define reg_pd_gpubrdgpll_clk_div30 ckgen00(0x1F04)
#define reg_pd_gpubrdgpll_clk_div30_s 8
#define reg_pd_gpubrdgpll_clk_div30_e 8
#define reg_en_gpubrdgpll_vco_div3 ckgen00(0x1F08)
#define reg_en_gpubrdgpll_vco_div3_s 0
#define reg_en_gpubrdgpll_vco_div3_e 0
#define reg_en_gpubrdgpll_occ_div128 ckgen00(0x1F08)
#define reg_en_gpubrdgpll_occ_div128_s 4
#define reg_en_gpubrdgpll_occ_div128_e 4
#define reg_en_gpubrdgpll_xtal ckgen00(0x1F08)
#define reg_en_gpubrdgpll_xtal_s 8
#define reg_en_gpubrdgpll_xtal_e 8
#define reg_en_gpubrdgpll_test ckgen00(0x1F08)
#define reg_en_gpubrdgpll_test_s 12
#define reg_en_gpubrdgpll_test_e 12
#define reg_en_gpubrdgpll_prdt ckgen00(0x1F0C)
#define reg_en_gpubrdgpll_prdt_s 0
#define reg_en_gpubrdgpll_prdt_e 0
#define reg_en_gpubrdgpll_rst ckgen00(0x1F0C)
#define reg_en_gpubrdgpll_rst_s 4
#define reg_en_gpubrdgpll_rst_e 4
#define reg_gc_gpubrdgpll_input_div ckgen00(0x1F10)
#define reg_gc_gpubrdgpll_input_div_s 0
#define reg_gc_gpubrdgpll_input_div_e 1
#define reg_gc_gpubrdgpll_cp_sw ckgen00(0x1F14)
#define reg_gc_gpubrdgpll_cp_sw_s 0
#define reg_gc_gpubrdgpll_cp_sw_e 1
#define reg_gc_gpubrdgpll_ictrl ckgen00(0x1F14)
#define reg_gc_gpubrdgpll_ictrl_s 8
#define reg_gc_gpubrdgpll_ictrl_e 10
#define reg_gc_gpubrdgpll_output_div_first ckgen00(0x1F18)
#define reg_gc_gpubrdgpll_output_div_first_s 0
#define reg_gc_gpubrdgpll_output_div_first_e 1
#define reg_gc_gpubrdgpll_output_div ckgen00(0x1F18)
#define reg_gc_gpubrdgpll_output_div_s 8
#define reg_gc_gpubrdgpll_output_div_e 10
#define reg_gc_gpubrdgpll_loopdiv_first ckgen00(0x1F1C)
#define reg_gc_gpubrdgpll_loopdiv_first_s 0
#define reg_gc_gpubrdgpll_loopdiv_first_e 1
#define reg_gc_gpubrdgpll_loopdiv_second ckgen00(0x1F20)
#define reg_gc_gpubrdgpll_loopdiv_second_s 0
#define reg_gc_gpubrdgpll_loopdiv_second_e 7
#define reg_ro_gpubrdgpll_lock ckgen00(0x1F28)
#define reg_ro_gpubrdgpll_lock_s 0
#define reg_ro_gpubrdgpll_lock_e 0
#define reg_test_gpubrdgpll ckgen00(0x1F38)
#define reg_test_gpubrdgpll_s 0
#define reg_test_gpubrdgpll_e 15
#define reg_pd_apubuspll ckgen00(0x1F40)
#define reg_pd_apubuspll_s 0
#define reg_pd_apubuspll_e 0
#define reg_pd_apubuspll_clk_div2p5 ckgen00(0x1F40)
#define reg_pd_apubuspll_clk_div2p5_s 4
#define reg_pd_apubuspll_clk_div2p5_e 4
#define reg_pd_apubuspll_clk_div2 ckgen00(0x1F40)
#define reg_pd_apubuspll_clk_div2_s 8
#define reg_pd_apubuspll_clk_div2_e 8
#define reg_pd_apubuspll_clk_div3 ckgen00(0x1F40)
#define reg_pd_apubuspll_clk_div3_s 12
#define reg_pd_apubuspll_clk_div3_e 12
#define reg_pd_apubuspll_clk_div5 ckgen00(0x1F44)
#define reg_pd_apubuspll_clk_div5_s 0
#define reg_pd_apubuspll_clk_div5_e 0
#define reg_pd_apubuspll_postdiv ckgen00(0x1F44)
#define reg_pd_apubuspll_postdiv_s 4
#define reg_pd_apubuspll_postdiv_e 4
#define reg_pd_apubuspll_clk_div30 ckgen00(0x1F44)
#define reg_pd_apubuspll_clk_div30_s 8
#define reg_pd_apubuspll_clk_div30_e 8
#define reg_en_apubuspll_vco_div3 ckgen00(0x1F48)
#define reg_en_apubuspll_vco_div3_s 0
#define reg_en_apubuspll_vco_div3_e 0
#define reg_en_apubuspll_occ_div128 ckgen00(0x1F48)
#define reg_en_apubuspll_occ_div128_s 4
#define reg_en_apubuspll_occ_div128_e 4
#define reg_en_apubuspll_xtal ckgen00(0x1F48)
#define reg_en_apubuspll_xtal_s 8
#define reg_en_apubuspll_xtal_e 8
#define reg_en_apubuspll_test ckgen00(0x1F48)
#define reg_en_apubuspll_test_s 12
#define reg_en_apubuspll_test_e 12
#define reg_en_apubuspll_prdt ckgen00(0x1F4C)
#define reg_en_apubuspll_prdt_s 0
#define reg_en_apubuspll_prdt_e 0
#define reg_en_apubuspll_rst ckgen00(0x1F4C)
#define reg_en_apubuspll_rst_s 4
#define reg_en_apubuspll_rst_e 4
#define reg_gc_apubuspll_input_div ckgen00(0x1F50)
#define reg_gc_apubuspll_input_div_s 0
#define reg_gc_apubuspll_input_div_e 1
#define reg_gc_apubuspll_cp_sw ckgen00(0x1F54)
#define reg_gc_apubuspll_cp_sw_s 0
#define reg_gc_apubuspll_cp_sw_e 1
#define reg_gc_apubuspll_ictrl ckgen00(0x1F54)
#define reg_gc_apubuspll_ictrl_s 8
#define reg_gc_apubuspll_ictrl_e 10
#define reg_gc_apubuspll_output_div_first ckgen00(0x1F58)
#define reg_gc_apubuspll_output_div_first_s 0
#define reg_gc_apubuspll_output_div_first_e 1
#define reg_gc_apubuspll_output_div ckgen00(0x1F58)
#define reg_gc_apubuspll_output_div_s 8
#define reg_gc_apubuspll_output_div_e 10
#define reg_gc_apubuspll_loopdiv_first ckgen00(0x1F5C)
#define reg_gc_apubuspll_loopdiv_first_s 0
#define reg_gc_apubuspll_loopdiv_first_e 1
#define reg_gc_apubuspll_loopdiv_second ckgen00(0x1F60)
#define reg_gc_apubuspll_loopdiv_second_s 0
#define reg_gc_apubuspll_loopdiv_second_e 7
#define reg_ro_apubuspll_lock ckgen00(0x1F68)
#define reg_ro_apubuspll_lock_s 0
#define reg_ro_apubuspll_lock_e 0
#define reg_test_apubuspll ckgen00(0x1F78)
#define reg_test_apubuspll_s 0
#define reg_test_apubuspll_e 15
#define reg_ckg_dvbtm_ts_divnum ckgen00(0x1F80)
#define reg_ckg_dvbtm_ts_divnum_s 0
#define reg_ckg_dvbtm_ts_divnum_e 7
#define reg_ckg_atsc_dvb_div_sel ckgen00(0x1F80)
#define reg_ckg_atsc_dvb_div_sel_s 8
#define reg_ckg_atsc_dvb_div_sel_e 10
#define reg_ckg_atsc_dvbtc_ts_inv ckgen00(0x1F80)
#define reg_ckg_atsc_dvbtc_ts_inv_s 11
#define reg_ckg_atsc_dvbtc_ts_inv_e 11
#define reg_ckg_dvbtm_ts_out_mode ckgen00(0x1F80)
#define reg_ckg_dvbtm_ts_out_mode_s 12
#define reg_ckg_dvbtm_ts_out_mode_e 12
#define reg_ckg_demod_test_in_en ckgen00(0x1F80)
#define reg_ckg_demod_test_in_en_s 13
#define reg_ckg_demod_test_in_en_e 13
#define reg_ckg_tsout_ph_tun_en ckgen00(0x1F80)
#define reg_ckg_tsout_ph_tun_en_s 14
#define reg_ckg_tsout_ph_tun_en_e 14
#define reg_atsc_dvb_div_reset ckgen00(0x1F84)
#define reg_atsc_dvb_div_reset_s 0
#define reg_atsc_dvb_div_reset_e 0
#define reg_ckg_atsc_ts ckgen00(0x1F88)
#define reg_ckg_atsc_ts_s 0
#define reg_ckg_atsc_ts_e 3
#define reg_ckg_dvbtc_ts_top ckgen00(0x1F8C)
#define reg_ckg_dvbtc_ts_top_s 8
#define reg_ckg_dvbtc_ts_top_e 11
#define reg_ckg_tsout_ph_tun_num ckgen00(0x1F90)
#define reg_ckg_tsout_ph_tun_num_s 8
#define reg_ckg_tsout_ph_tun_num_e 12
#define reg_ckg_vifdbb_dac_top ckgen00(0x1F94)
#define reg_ckg_vifdbb_dac_top_s 0
#define reg_ckg_vifdbb_dac_top_e 3
#define reg_ckg_daca2 ckgen00(0x1F98)
#define reg_ckg_daca2_s 0
#define reg_ckg_daca2_e 4
#define reg_ckg_dacb2 ckgen00(0x1F98)
#define reg_ckg_dacb2_s 8
#define reg_ckg_dacb2_e 11
#define reg_ckg_vd_sel ckgen00(0x1FA0)
#define reg_ckg_vd_sel_s 0
#define reg_ckg_vd_sel_e 0
#define reg_ckg_vd_buf_sel ckgen00(0x1FA0)
#define reg_ckg_vd_buf_sel_s 4
#define reg_ckg_vd_buf_sel_e 4
#define reg_ckgen00_dummy0 ckgen00(0x1FF0)
#define reg_ckgen00_dummy0_s 0
#define reg_ckgen00_dummy0_e 15
#define reg_ckgen00_dummy1 ckgen00(0x1FF4)
#define reg_ckgen00_dummy1_s 0
#define reg_ckgen00_dummy1_e 15
#define reg_ckgen00_dummy2 ckgen00(0x1FF8)
#define reg_ckgen00_dummy2_s 0
#define reg_ckgen00_dummy2_e 15
#define reg_ckgen00_dummy3 ckgen00(0x1FFC)
#define reg_ckgen00_dummy3_s 0
#define reg_ckgen00_dummy3_e 15

#endif
