#ifndef _TGEN_MAIN_BK_H
#define _TGEN_MAIN_BK_H

#define TGEN_MAIN_BKA3A0 0x01474000

//Page TGEN_MAIN_BKA3A0
#define REG_0004_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x004)
    #define REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_NP_MD Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_TS_MD Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_REGEN_CNT_SRC_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_CNT_SW_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_XTALI Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_ODCLK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x008)
    #define REG_0008_TGEN_MAIN_BKA3A0_REG_TGEN_VIDEO_EN Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x00C)
    #define REG_000C_TGEN_MAIN_BKA3A0_REG_TGEN_TESTBUS_SEL Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_000C_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_000C_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_SEL_V2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_000C_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0010_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x010)
    #define REG_0010_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x014)
    #define REG_0014_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0018_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x018)
    #define REG_0018_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x01C)
    #define REG_001C_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x020)
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_VDE_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_CLR_RPFP_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_STR_RPFP_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_CLR_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_STR_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0020_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_SRC_SEL Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0024_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x024)
    #define REG_0024_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_VALUE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x028)
    #define REG_0028_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x02C)
    #define REG_002C_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_VDE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0030_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x030)
    #define REG_0030_TGEN_MAIN_BKA3A0_REG_TGEN_CHK_SUM_VDE_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x034)
    #define REG_0034_TGEN_MAIN_BKA3A0_REG_TGEN_INTR_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0038_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x038)
    #define REG_0038_TGEN_MAIN_BKA3A0_REG_TGEN_DB_OFF Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0038_TGEN_MAIN_BKA3A0_REG_TGEN_DB_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0038_TGEN_MAIN_BKA3A0_REG_TGEN_DB_FLAG Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0038_TGEN_MAIN_BKA3A0_REG_TGEN_SETTING_DONE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_003C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x03C)
    #define REG_003C_TGEN_MAIN_BKA3A0_REG_TGEN_DB_REF_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x040)
    #define REG_0040_TGEN_MAIN_BKA3A0_REG_HCNT_INI_VAL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x044)
    #define REG_0044_TGEN_MAIN_BKA3A0_REG_HCNT_OF_KEEP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0044_TGEN_MAIN_BKA3A0_REG_HCNT_REGEN_CLR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0044_TGEN_MAIN_BKA3A0_REG_HCNT_REGEN_CLR_PULSE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0044_TGEN_MAIN_BKA3A0_REG_HCNT_REGEN_CLR_EN_DB_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0044_TGEN_MAIN_BKA3A0_REG_HCNT_REGEN_CLR_EN_DB_OFF Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0044_TGEN_MAIN_BKA3A0_REG_HCNT_REPORT_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_004C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x04C)
    #define REG_004C_TGEN_MAIN_BKA3A0_REG_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x050)
    #define REG_0050_TGEN_MAIN_BKA3A0_REG_HSYNC_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x054)
    #define REG_0054_TGEN_MAIN_BKA3A0_REG_HSYNC_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0058_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x058)
    #define REG_0058_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_005C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x05C)
    #define REG_005C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x060)
    #define REG_0060_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x064)
    #define REG_0064_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x068)
    #define REG_0068_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_006C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x06C)
    #define REG_006C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x070)
    #define REG_0070_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_TCON_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x074)
    #define REG_0074_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_TCON_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_007C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x07C)
    #define REG_007C_TGEN_MAIN_BKA3A0_REG_REGEN_CNT_CLR_HCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0080_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x080)
    #define REG_0080_TGEN_MAIN_BKA3A0_REG_VCNT_INI_VAL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0084_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x084)
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_OF_KEEP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_EQ_VTT_STOP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_EVEN_VTT_VCNT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_REGEN_CLR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_REGEN_CLR_PULSE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_REGEN_CLR_EN_DB_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_REGEN_CLR_EN_DB_OFF Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0084_TGEN_MAIN_BKA3A0_REG_VCNT_REPORT_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0088_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x088)
    #define REG_0088_TGEN_MAIN_BKA3A0_REG_FRAMELOCK_VCNT_EN_DB Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0088_TGEN_MAIN_BKA3A0_REG_FRAMELOCK_VCNT_EN_DB_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0088_TGEN_MAIN_BKA3A0_REG_FRAMELOCK_VCNT_EN_DB_OFF Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0088_TGEN_MAIN_BKA3A0_REG_FRAMELOCK_VCNT_MODE Fld(1,3,AC_MSKB0)//[3:3]
#define REG_008C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x08C)
    #define REG_008C_TGEN_MAIN_BKA3A0_REG_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x090)
    #define REG_0090_TGEN_MAIN_BKA3A0_REG_VSYNC_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0094_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x094)
    #define REG_0094_TGEN_MAIN_BKA3A0_REG_VSYNC_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0098_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x098)
    #define REG_0098_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_009C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x09C)
    #define REG_009C_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0A0)
    #define REG_00A0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0A4)
    #define REG_00A4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0A8)
    #define REG_00A8_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00AC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0AC)
    #define REG_00AC_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0B0)
    #define REG_00B0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_TCON_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0B4)
    #define REG_00B4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_TCON_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0BC)
    #define REG_00BC_TGEN_MAIN_BKA3A0_REG_REGEN_CNT_CLR_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0C0)
    #define REG_00C0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0C4)
    #define REG_00C4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0C8)
    #define REG_00C8_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO1_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0CC)
    #define REG_00CC_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO1_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0D0)
    #define REG_00D0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO2_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0D4)
    #define REG_00D4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO2_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0D8)
    #define REG_00D8_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO3_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0DC)
    #define REG_00DC_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO3_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0E0)
    #define REG_00E0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO4_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0E4)
    #define REG_00E4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO4_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0E8)
    #define REG_00E8_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO5_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0EC)
    #define REG_00EC_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO5_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0F0)
    #define REG_00F0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO6_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0F4)
    #define REG_00F4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO6_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0F8)
    #define REG_00F8_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO7_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00FC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x0FC)
    #define REG_00FC_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO7_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x100)
    #define REG_0100_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0104_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x104)
    #define REG_0104_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0108_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x108)
    #define REG_0108_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO1_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_010C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x10C)
    #define REG_010C_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO1_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0110_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x110)
    #define REG_0110_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO2_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0114_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x114)
    #define REG_0114_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO2_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0118_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x118)
    #define REG_0118_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO3_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_011C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x11C)
    #define REG_011C_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO3_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0120_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x120)
    #define REG_0120_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO4_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0124_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x124)
    #define REG_0124_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO4_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0128_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x128)
    #define REG_0128_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO5_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_012C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x12C)
    #define REG_012C_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO5_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0130_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x130)
    #define REG_0130_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO6_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0134_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x134)
    #define REG_0134_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO6_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0138_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x138)
    #define REG_0138_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO7_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_013C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x13C)
    #define REG_013C_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO7_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0140_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x140)
    #define REG_0140_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO8_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0144_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x144)
    #define REG_0144_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO8_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0148_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x148)
    #define REG_0148_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO9_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_014C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x14C)
    #define REG_014C_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO9_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0150_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x150)
    #define REG_0150_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO10_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0154_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x154)
    #define REG_0154_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO10_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0158_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x158)
    #define REG_0158_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO11_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_015C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x15C)
    #define REG_015C_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO11_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0160_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x160)
    #define REG_0160_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO12_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0164_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x164)
    #define REG_0164_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO12_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0168_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x168)
    #define REG_0168_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO13_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_016C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x16C)
    #define REG_016C_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO13_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0170_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x170)
    #define REG_0170_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO14_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0174_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x174)
    #define REG_0174_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO14_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0178_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x178)
    #define REG_0178_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO15_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_017C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x17C)
    #define REG_017C_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO15_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0180_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x180)
    #define REG_0180_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO8_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0184_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x184)
    #define REG_0184_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO8_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x188)
    #define REG_0188_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO9_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_018C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x18C)
    #define REG_018C_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO9_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x190)
    #define REG_0190_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO10_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x194)
    #define REG_0194_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO10_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0198_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x198)
    #define REG_0198_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO11_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x19C)
    #define REG_019C_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO11_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1A0)
    #define REG_01A0_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO12_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1A4)
    #define REG_01A4_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO12_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1A8)
    #define REG_01A8_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO13_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01AC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1AC)
    #define REG_01AC_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO13_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1B0)
    #define REG_01B0_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO14_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1B4)
    #define REG_01B4_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO14_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1B8)
    #define REG_01B8_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO15_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01BC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1BC)
    #define REG_01BC_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO15_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1C0)
    #define REG_01C0_TGEN_MAIN_BKA3A0_REG_PIX_SFT_V0_CTRL Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01C0_TGEN_MAIN_BKA3A0_REG_PIX_SFT_V0_FRAME_COLOR_ALPHA Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01C0_TGEN_MAIN_BKA3A0_REG_PIX_SFT_V0_FRAME_COLOR_DE_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01C0_TGEN_MAIN_BKA3A0_REG_PIX_SFT_V0_FRAME_COLOR_BYPASS Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01C0_TGEN_MAIN_BKA3A0_REG_PIX_SFT_V0_EN Fld(1,7,AC_MSKB0)//[7:7]
#define REG_01C4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1C4)
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G0_CTRL Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G0_FRAME_COLOR_ALPHA Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G0_FRAME_COLOR_DE_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G0_FRAME_COLOR_BYPASS Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G0_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G1_CTRL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G1_FRAME_COLOR_ALPHA Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G1_FRAME_COLOR_DE_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G1_FRAME_COLOR_BYPASS Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01C4_TGEN_MAIN_BKA3A0_REG_PIX_SFT_G1_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01C8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1C8)
    #define REG_01C8_TGEN_MAIN_BKA3A0_REG_FRAME_R Fld(10,0,AC_MSKW10)//[9:0]
#define REG_01CC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1CC)
    #define REG_01CC_TGEN_MAIN_BKA3A0_REG_FRAME_G Fld(10,0,AC_MSKW10)//[9:0]
#define REG_01D0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1D0)
    #define REG_01D0_TGEN_MAIN_BKA3A0_REG_FRAME_B Fld(10,0,AC_MSKW10)//[9:0]
#define REG_01D4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1D4)
    #define REG_01D4_TGEN_MAIN_BKA3A0_REG_FRAME_ALPHA Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01D4_TGEN_MAIN_BKA3A0_REG_FRAME_COLOR_DE_SEL Fld(2,13,AC_MSKB1)//[14:13]
    #define REG_01D4_TGEN_MAIN_BKA3A0_REG_FRAME_COLOR_BYPASS Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E0_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1E0)
    #define REG_01E0_TGEN_MAIN_BKA3A0_REG_TGEN_REF_HCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1E4)
    #define REG_01E4_TGEN_MAIN_BKA3A0_REG_TGEN_REF_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1E8)
    #define REG_01E8_TGEN_MAIN_BKA3A0_REG_VSYNC_TCON_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01EC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1EC)
    #define REG_01EC_TGEN_MAIN_BKA3A0_REG_VSYNC_TCON_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1F4)
    #define REG_01F4_TGEN_MAIN_BKA3A0_REG_M_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F8_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1F8)
    #define REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_TGEN_MAIN_BKA3A0 (TGEN_MAIN_BKA3A0 + 0x1FC)
    #define REG_01FC_TGEN_MAIN_BKA3A0_REG_PANEL_UPPER_BOUND Fld(16,0,AC_FULLW10)//[15:0]

#endif
