/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

/* PM clock mux */
#define CLK_PMGEN_MIIC0_PM_INT_CK		1
#define CLK_PMGEN_MIIC1_PM_INT_CK		2
#define CLK_PMGEN_MIIC_MUX_GATE_NR		3

/* PM sw_en */
#define CLK_MIIC_PM_EN_MIIC0_PM2PM		1
#define CLK_MIIC_PM_EN_MIIC1_PM2PM		2
#define CLK_MIIC_PM_EN_NR			3

/* clock mux for mheg5 */
#define CLK_MHEG5GEN_MIIC0_INT_CK		1
#define CLK_MHEG5GEN_MIIC1_INT_CK		2
#define CLK_MHEG5GEN_MIIC2_INT_CK		3
#define CLK_MHEG5GEN_MIIC3_INT_CK		4
#define CLK_MHEG5GEN_MIIC_MUX_GATE_NR		5

/* sw_en */
#define CLK_MIIC_NONPM_EN_SMI2MCU_MIIC0		1
#define CLK_MIIC_NONPM_EN_SMI2MCU_MIIC1		2
#define CLK_MIIC_NONPM_EN_SMI2MCU_MIIC2		3
#define CLK_MIIC_NONPM_EN_SMI2MCU_MIIC3		4

#define CLK_MIIC_NONPM_EN_XTAL_12M2MCU_MIIC0	5
#define CLK_MIIC_NONPM_EN_XTAL_12M2MCU_MIIC1	6
#define CLK_MIIC_NONPM_EN_XTAL_12M2MCU_MIIC2	7
#define CLK_MIIC_NONPM_EN_XTAL_12M2MCU_MIIC3	8

#define CLK_MIIC_NONPM_EN_MCU_NONPM2MCU_MIIC0	9
#define CLK_MIIC_NONPM_EN_MCU_NONPM2MCU_MIIC1	10
#define CLK_MIIC_NONPM_EN_MCU_NONPM2MCU_MIIC2	11
#define CLK_MIIC_NONPM_EN_MCU_NONPM2MCU_MIIC3	12

#define CLK_MIIC_NONPM_EN_MIIC02MCU_MIIC0	13
#define CLK_MIIC_NONPM_EN_MIIC12MCU_MIIC1	14
#define CLK_MIIC_NONPM_EN_MIIC22MCU_MIIC2	15
#define CLK_MIIC_NONPM_EN_MIIC32MCU_MIIC3	16

#define CLK_MIIC_NONPM_EN_NR			17
