#ifndef _MODA2_H
#define _MODA2_H

#define moda2 0x00484800

//Page MODA2
#define REG_0008_MODA2 (moda2 + 0x008)
    #define REG_0008_MODA2_REG_GCR_DS_POL_CH_39_20_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_MODA2 (moda2 + 0x00C)
    #define REG_000C_MODA2_REG_GCR_DS_POL_CH_39_20_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0010_MODA2 (moda2 + 0x010)
    #define REG_0010_MODA2_REG_GCR_PE_EN_CH_39_20_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_MODA2 (moda2 + 0x014)
    #define REG_0014_MODA2_REG_GCR_PE_EN_CH_39_20_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0018_MODA2 (moda2 + 0x018)
    #define REG_0018_MODA2_REG_GCR_EN_RINT_CH_39_20_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_MODA2 (moda2 + 0x01C)
    #define REG_001C_MODA2_REG_GCR_EN_RINT_CH_39_20_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0020_MODA2 (moda2 + 0x020)
    #define REG_0020_MODA2_REG_GCR_EN_VBY1_CH_39_20_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_MODA2 (moda2 + 0x024)
    #define REG_0024_MODA2_REG_GCR_EN_VBY1_CH_39_20_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0028_MODA2 (moda2 + 0x028)
    #define REG_0028_MODA2_REG_GCR_TTL_LPM_EN_CH_39_20_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_MODA2 (moda2 + 0x02C)
    #define REG_002C_MODA2_REG_GCR_TTL_LPM_EN_CH_39_20_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0030_MODA2 (moda2 + 0x030)
    #define REG_0030_MODA2_REG_GCR_EN_XSWING_CH_39_20_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_MODA2 (moda2 + 0x034)
    #define REG_0034_MODA2_REG_GCR_EN_XSWING_CH_39_20_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0060_MODA2 (moda2 + 0x060)
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH20 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH21 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH22 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH23 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH24 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH25 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH26 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0060_MODA2_REG_OUTPUT_CONF_CH27 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0064_MODA2 (moda2 + 0x064)
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH28 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH29 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH30 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH31 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH32 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH33 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH34 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0064_MODA2_REG_OUTPUT_CONF_CH35 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0068_MODA2 (moda2 + 0x068)
    #define REG_0068_MODA2_REG_OUTPUT_CONF_CH36 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0068_MODA2_REG_OUTPUT_CONF_CH37 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0068_MODA2_REG_OUTPUT_CONF_CH38 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0068_MODA2_REG_OUTPUT_CONF_CH39 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0070_MODA2 (moda2 + 0x070)
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH20 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH21 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH22 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH23 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH24 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH25 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH26 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0070_MODA2_REG_FTUNE_SKEW_CH27 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0074_MODA2 (moda2 + 0x074)
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH28 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH29 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH30 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH31 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH32 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH33 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH34 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0074_MODA2_REG_FTUNE_SKEW_CH35 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0078_MODA2 (moda2 + 0x078)
    #define REG_0078_MODA2_REG_FTUNE_SKEW_CH36 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0078_MODA2_REG_FTUNE_SKEW_CH37 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0078_MODA2_REG_FTUNE_SKEW_CH38 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0078_MODA2_REG_FTUNE_SKEW_CH39 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0080_MODA2 (moda2 + 0x080)
    #define REG_0080_MODA2_REG_GCR_PE_ADJ_CH20 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0080_MODA2_REG_GCR_PE_ADJ_CH21 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0084_MODA2 (moda2 + 0x084)
    #define REG_0084_MODA2_REG_GCR_PE_ADJ_CH22 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0084_MODA2_REG_GCR_PE_ADJ_CH23 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0088_MODA2 (moda2 + 0x088)
    #define REG_0088_MODA2_REG_GCR_PE_ADJ_CH24 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0088_MODA2_REG_GCR_PE_ADJ_CH25 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_008C_MODA2 (moda2 + 0x08C)
    #define REG_008C_MODA2_REG_GCR_PE_ADJ_CH26 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_008C_MODA2_REG_GCR_PE_ADJ_CH27 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0090_MODA2 (moda2 + 0x090)
    #define REG_0090_MODA2_REG_GCR_PE_ADJ_CH28 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0090_MODA2_REG_GCR_PE_ADJ_CH29 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0094_MODA2 (moda2 + 0x094)
    #define REG_0094_MODA2_REG_GCR_PE_ADJ_CH30 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0094_MODA2_REG_GCR_PE_ADJ_CH31 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0098_MODA2 (moda2 + 0x098)
    #define REG_0098_MODA2_REG_GCR_PE_ADJ_CH32 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0098_MODA2_REG_GCR_PE_ADJ_CH33 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_009C_MODA2 (moda2 + 0x09C)
    #define REG_009C_MODA2_REG_GCR_PE_ADJ_CH34 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_009C_MODA2_REG_GCR_PE_ADJ_CH35 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A0_MODA2 (moda2 + 0x0A0)
    #define REG_00A0_MODA2_REG_GCR_PE_ADJ_CH36 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00A0_MODA2_REG_GCR_PE_ADJ_CH37 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A4_MODA2 (moda2 + 0x0A4)
    #define REG_00A4_MODA2_REG_GCR_PE_ADJ_CH38 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00A4_MODA2_REG_GCR_PE_ADJ_CH39 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00B0_MODA2 (moda2 + 0x0B0)
    #define REG_00B0_MODA2_REG_GCR_ICON_CH20 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B0_MODA2_REG_GCR_ICON_CH21 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B4_MODA2 (moda2 + 0x0B4)
    #define REG_00B4_MODA2_REG_GCR_ICON_CH22 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B4_MODA2_REG_GCR_ICON_CH23 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B8_MODA2 (moda2 + 0x0B8)
    #define REG_00B8_MODA2_REG_GCR_ICON_CH24 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B8_MODA2_REG_GCR_ICON_CH25 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00BC_MODA2 (moda2 + 0x0BC)
    #define REG_00BC_MODA2_REG_GCR_ICON_CH26 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00BC_MODA2_REG_GCR_ICON_CH27 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C0_MODA2 (moda2 + 0x0C0)
    #define REG_00C0_MODA2_REG_GCR_ICON_CH28 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C0_MODA2_REG_GCR_ICON_CH29 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_MODA2 (moda2 + 0x0C4)
    #define REG_00C4_MODA2_REG_GCR_ICON_CH30 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C4_MODA2_REG_GCR_ICON_CH31 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C8_MODA2 (moda2 + 0x0C8)
    #define REG_00C8_MODA2_REG_GCR_ICON_CH32 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C8_MODA2_REG_GCR_ICON_CH33 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_MODA2 (moda2 + 0x0CC)
    #define REG_00CC_MODA2_REG_GCR_ICON_CH34 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00CC_MODA2_REG_GCR_ICON_CH35 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D0_MODA2 (moda2 + 0x0D0)
    #define REG_00D0_MODA2_REG_GCR_ICON_CH36 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D0_MODA2_REG_GCR_ICON_CH37 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D4_MODA2 (moda2 + 0x0D4)
    #define REG_00D4_MODA2_REG_GCR_ICON_CH38 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D4_MODA2_REG_GCR_ICON_CH39 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00E0_MODA2 (moda2 + 0x0E0)
    #define REG_00E0_MODA2_REG_GCR_RCON_CH20 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E0_MODA2_REG_GCR_RCON_CH21 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00E4_MODA2 (moda2 + 0x0E4)
    #define REG_00E4_MODA2_REG_GCR_RCON_CH22 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E4_MODA2_REG_GCR_RCON_CH23 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00E8_MODA2 (moda2 + 0x0E8)
    #define REG_00E8_MODA2_REG_GCR_RCON_CH24 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E8_MODA2_REG_GCR_RCON_CH25 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00EC_MODA2 (moda2 + 0x0EC)
    #define REG_00EC_MODA2_REG_GCR_RCON_CH26 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00EC_MODA2_REG_GCR_RCON_CH27 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F0_MODA2 (moda2 + 0x0F0)
    #define REG_00F0_MODA2_REG_GCR_RCON_CH28 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F0_MODA2_REG_GCR_RCON_CH29 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F4_MODA2 (moda2 + 0x0F4)
    #define REG_00F4_MODA2_REG_GCR_RCON_CH30 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F4_MODA2_REG_GCR_RCON_CH31 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F8_MODA2 (moda2 + 0x0F8)
    #define REG_00F8_MODA2_REG_GCR_RCON_CH32 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F8_MODA2_REG_GCR_RCON_CH33 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00FC_MODA2 (moda2 + 0x0FC)
    #define REG_00FC_MODA2_REG_GCR_RCON_CH34 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00FC_MODA2_REG_GCR_RCON_CH35 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0100_MODA2 (moda2 + 0x100)
    #define REG_0100_MODA2_REG_GCR_RCON_CH36 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0100_MODA2_REG_GCR_RCON_CH37 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0104_MODA2 (moda2 + 0x104)
    #define REG_0104_MODA2_REG_GCR_RCON_CH38 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0104_MODA2_REG_GCR_RCON_CH39 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0110_MODA2 (moda2 + 0x110)
    #define REG_0110_MODA2_REG_RINT_SEL_CH20 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0110_MODA2_REG_RINT_SEL_CH21 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0110_MODA2_REG_RINT_SEL_CH22 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0110_MODA2_REG_RINT_SEL_CH23 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0114_MODA2 (moda2 + 0x114)
    #define REG_0114_MODA2_REG_RINT_SEL_CH24 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0114_MODA2_REG_RINT_SEL_CH25 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0114_MODA2_REG_RINT_SEL_CH26 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0114_MODA2_REG_RINT_SEL_CH27 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0118_MODA2 (moda2 + 0x118)
    #define REG_0118_MODA2_REG_RINT_SEL_CH28 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0118_MODA2_REG_RINT_SEL_CH29 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0118_MODA2_REG_RINT_SEL_CH30 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0118_MODA2_REG_RINT_SEL_CH31 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_011C_MODA2 (moda2 + 0x11C)
    #define REG_011C_MODA2_REG_RINT_SEL_CH32 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_011C_MODA2_REG_RINT_SEL_CH33 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_011C_MODA2_REG_RINT_SEL_CH34 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_011C_MODA2_REG_RINT_SEL_CH35 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0120_MODA2 (moda2 + 0x120)
    #define REG_0120_MODA2_REG_RINT_SEL_CH36 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0120_MODA2_REG_RINT_SEL_CH37 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0120_MODA2_REG_RINT_SEL_CH38 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0120_MODA2_REG_RINT_SEL_CH39 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0124_MODA2 (moda2 + 0x124)
    #define REG_0124_MODA2_REG_GCR_TEST_PRE_LDO_CH20 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0124_MODA2_REG_GCR_TEST_PRE_LDO_CH21 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0124_MODA2_REG_GCR_TEST_PRE_LDO_CH22 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0124_MODA2_REG_GCR_TEST_PRE_LDO_CH23 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0128_MODA2 (moda2 + 0x128)
    #define REG_0128_MODA2_REG_GCR_TEST_PRE_LDO_CH24 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0128_MODA2_REG_GCR_TEST_PRE_LDO_CH25 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0128_MODA2_REG_GCR_TEST_PRE_LDO_CH26 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0128_MODA2_REG_GCR_TEST_PRE_LDO_CH27 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_012C_MODA2 (moda2 + 0x12C)
    #define REG_012C_MODA2_REG_GCR_TEST_PRE_LDO_CH28 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_012C_MODA2_REG_GCR_TEST_PRE_LDO_CH29 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_012C_MODA2_REG_GCR_TEST_PRE_LDO_CH30 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_012C_MODA2_REG_GCR_TEST_PRE_LDO_CH31 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0130_MODA2 (moda2 + 0x130)
    #define REG_0130_MODA2_REG_GCR_TEST_PRE_LDO_CH32 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0130_MODA2_REG_GCR_TEST_PRE_LDO_CH33 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0130_MODA2_REG_GCR_TEST_PRE_LDO_CH34 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0130_MODA2_REG_GCR_TEST_PRE_LDO_CH35 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0134_MODA2 (moda2 + 0x134)
    #define REG_0134_MODA2_REG_GCR_TEST_PRE_LDO_CH36 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0134_MODA2_REG_GCR_TEST_PRE_LDO_CH37 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0134_MODA2_REG_GCR_TEST_PRE_LDO_CH38 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0134_MODA2_REG_GCR_TEST_PRE_LDO_CH39 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0140_MODA2 (moda2 + 0x140)
    #define REG_0140_MODA2_REG_GCR_VBY1_VREG_CH20 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0140_MODA2_REG_GCR_VBY1_VREG_CH21 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0140_MODA2_REG_GCR_VBY1_VREG_CH22 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0140_MODA2_REG_GCR_VBY1_VREG_CH23 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0144_MODA2 (moda2 + 0x144)
    #define REG_0144_MODA2_REG_GCR_VBY1_VREG_CH24 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0144_MODA2_REG_GCR_VBY1_VREG_CH25 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0144_MODA2_REG_GCR_VBY1_VREG_CH26 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0144_MODA2_REG_GCR_VBY1_VREG_CH27 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0148_MODA2 (moda2 + 0x148)
    #define REG_0148_MODA2_REG_GCR_VBY1_VREG_CH28 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0148_MODA2_REG_GCR_VBY1_VREG_CH29 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0148_MODA2_REG_GCR_VBY1_VREG_CH30 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0148_MODA2_REG_GCR_VBY1_VREG_CH31 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_014C_MODA2 (moda2 + 0x14C)
    #define REG_014C_MODA2_REG_GCR_VBY1_VREG_CH32 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_014C_MODA2_REG_GCR_VBY1_VREG_CH33 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_014C_MODA2_REG_GCR_VBY1_VREG_CH34 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_014C_MODA2_REG_GCR_VBY1_VREG_CH35 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0150_MODA2 (moda2 + 0x150)
    #define REG_0150_MODA2_REG_GCR_VBY1_VREG_CH36 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0150_MODA2_REG_GCR_VBY1_VREG_CH37 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0150_MODA2_REG_GCR_VBY1_VREG_CH38 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0150_MODA2_REG_GCR_VBY1_VREG_CH39 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0154_MODA2 (moda2 + 0x154)
    #define REG_0154_MODA2_REG_DRV_MODE_CH20 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0154_MODA2_REG_DRV_MODE_CH21 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0154_MODA2_REG_DRV_MODE_CH22 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0154_MODA2_REG_DRV_MODE_CH23 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0154_MODA2_REG_DRV_MODE_CH24 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0154_MODA2_REG_DRV_MODE_CH25 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0154_MODA2_REG_DRV_MODE_CH26 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0154_MODA2_REG_DRV_MODE_CH27 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0158_MODA2 (moda2 + 0x158)
    #define REG_0158_MODA2_REG_DRV_MODE_CH28 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0158_MODA2_REG_DRV_MODE_CH29 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0158_MODA2_REG_DRV_MODE_CH30 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0158_MODA2_REG_DRV_MODE_CH31 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0158_MODA2_REG_DRV_MODE_CH32 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0158_MODA2_REG_DRV_MODE_CH33 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0158_MODA2_REG_DRV_MODE_CH34 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0158_MODA2_REG_DRV_MODE_CH35 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_015C_MODA2 (moda2 + 0x15C)
    #define REG_015C_MODA2_REG_DRV_MODE_CH36 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_015C_MODA2_REG_DRV_MODE_CH37 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_015C_MODA2_REG_DRV_MODE_CH38 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_015C_MODA2_REG_DRV_MODE_CH39 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0168_MODA2 (moda2 + 0x168)
    #define REG_0168_MODA2_REG_BIAS_CON_OFFSET_CH20 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0168_MODA2_REG_BIAS_CON_OFFSET_CH21 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0168_MODA2_REG_BIAS_CON_OFFSET_CH22 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0168_MODA2_REG_BIAS_CON_OFFSET_CH23 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_016C_MODA2 (moda2 + 0x16C)
    #define REG_016C_MODA2_REG_BIAS_CON_OFFSET_CH24 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_016C_MODA2_REG_BIAS_CON_OFFSET_CH25 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_016C_MODA2_REG_BIAS_CON_OFFSET_CH26 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_016C_MODA2_REG_BIAS_CON_OFFSET_CH27 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0170_MODA2 (moda2 + 0x170)
    #define REG_0170_MODA2_REG_BIAS_CON_OFFSET_CH28 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0170_MODA2_REG_BIAS_CON_OFFSET_CH29 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0170_MODA2_REG_BIAS_CON_OFFSET_CH30 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0170_MODA2_REG_BIAS_CON_OFFSET_CH31 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0174_MODA2 (moda2 + 0x174)
    #define REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH32 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH33 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH34 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH35 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0178_MODA2 (moda2 + 0x178)
    #define REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH36 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH37 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH38 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH39 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0180_MODA2 (moda2 + 0x180)
    #define REG_0180_MODA2_REG_GPO_OEZ_79_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0184_MODA2 (moda2 + 0x184)
    #define REG_0184_MODA2_REG_GPO_OEZ_79_40_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_MODA2 (moda2 + 0x188)
    #define REG_0188_MODA2_REG_GPO_OEZ_79_40_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_018C_MODA2 (moda2 + 0x18C)
    #define REG_018C_MODA2_REG_GPO_DATA_79_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_MODA2 (moda2 + 0x190)
    #define REG_0190_MODA2_REG_GPO_DATA_79_40_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_MODA2 (moda2 + 0x194)
    #define REG_0194_MODA2_REG_GPO_DATA_79_40_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0198_MODA2 (moda2 + 0x198)
    #define REG_0198_MODA2_REG_GPI_DATA_79_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_MODA2 (moda2 + 0x19C)
    #define REG_019C_MODA2_REG_GPI_DATA_79_40_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_MODA2 (moda2 + 0x1A0)
    #define REG_01A0_MODA2_REG_GPI_DATA_79_40_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01A4_MODA2 (moda2 + 0x1A4)
    #define REG_01A4_MODA2_REG_EXT_EN_79_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A8_MODA2 (moda2 + 0x1A8)
    #define REG_01A8_MODA2_REG_EXT_EN_79_40_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01AC_MODA2 (moda2 + 0x1AC)
    #define REG_01AC_MODA2_REG_EXT_EN_79_40_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01B0_MODA2 (moda2 + 0x1B0)
    #define REG_01B0_MODA2_REG_TTL_EN_79_40_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B4_MODA2 (moda2 + 0x1B4)
    #define REG_01B4_MODA2_REG_TTL_EN_79_40_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B8_MODA2 (moda2 + 0x1B8)
    #define REG_01B8_MODA2_REG_TTL_EN_79_40_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01EC_MODA2 (moda2 + 0x1EC)
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_20 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_21 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_22 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_23 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_24 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_25 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_26 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01EC_MODA2_REG_TEST_DATA_SEL_27 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F0_MODA2 (moda2 + 0x1F0)
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_28 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_29 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_30 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_31 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_32 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_33 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_34 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01F0_MODA2_REG_TEST_DATA_SEL_35 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F4_MODA2 (moda2 + 0x1F4)
    #define REG_01F4_MODA2_REG_TEST_DATA_SEL_36 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01F4_MODA2_REG_TEST_DATA_SEL_37 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01F4_MODA2_REG_TEST_DATA_SEL_38 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F4_MODA2_REG_TEST_DATA_SEL_39 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_01F8_MODA2 (moda2 + 0x1F8)
    #define REG_01F8_MODA2_REG_FORCE_DATA1_31_16 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_MODA2 (moda2 + 0x1FC)
    #define REG_01FC_MODA2_REG_FORCE_DATA2_31_16 Fld(16,0,AC_FULLW10)//[15:0]

#endif
