/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_REG01_PM_H
#define _DT_BINDINGS_CLK_MT5896_REG01_PM_H

#define ckgen01_pm(Offset) (Offset+0x200)

#define reg_sw_en_smi2pm_ssusb ckgen01_pm(0x0000)
#define reg_sw_en_smi2pm_ssusb_s 0
#define reg_sw_en_smi2pm_ssusb_e 0
#define reg_sw_en_smi2pm_smi ckgen01_pm(0x0000)
#define reg_sw_en_smi2pm_smi_s 1
#define reg_sw_en_smi2pm_smi_e 1
#define reg_sw_en_smi2pm_pextp ckgen01_pm(0x0000)
#define reg_sw_en_smi2pm_pextp_s 2
#define reg_sw_en_smi2pm_pextp_e 2
#define reg_sw_en_cm4_core2cm4_core ckgen01_pm(0x0004)
#define reg_sw_en_cm4_core2cm4_core_s 0
#define reg_sw_en_cm4_core2cm4_core_e 0
#define reg_sw_en_cm4_dfs_ref2cm4 ckgen01_pm(0x0008)
#define reg_sw_en_cm4_dfs_ref2cm4_s 0
#define reg_sw_en_cm4_dfs_ref2cm4_e 0
#define reg_sw_en_cm4_systick2cm4_systick ckgen01_pm(0x000C)
#define reg_sw_en_cm4_systick2cm4_systick_s 0
#define reg_sw_en_cm4_systick2cm4_systick_e 0
#define reg_sw_en_cm4_tck2tck_int ckgen01_pm(0x0010)
#define reg_sw_en_cm4_tck2tck_int_s 0
#define reg_sw_en_cm4_tck2tck_int_e 0
#define reg_sw_en_cm4_tsvalueb2cm4_tsvalueb ckgen01_pm(0x0014)
#define reg_sw_en_cm4_tsvalueb2cm4_tsvalueb_s 0
#define reg_sw_en_cm4_tsvalueb2cm4_tsvalueb_e 0
#define reg_sw_en_cm42cm4 ckgen01_pm(0x0018)
#define reg_sw_en_cm42cm4_s 0
#define reg_sw_en_cm42cm4_e 0
#define reg_sw_en_codec_i2s_mck2codec_i2s_mck ckgen01_pm(0x001C)
#define reg_sw_en_codec_i2s_mck2codec_i2s_mck_s 0
#define reg_sw_en_codec_i2s_mck2codec_i2s_mck_e 0
#define reg_sw_en_codec_i2s_rx_bck2codec_i2s_rx_bck ckgen01_pm(0x0020)
#define reg_sw_en_codec_i2s_rx_bck2codec_i2s_rx_bck_s 0
#define reg_sw_en_codec_i2s_rx_bck2codec_i2s_rx_bck_e 0
#define reg_sw_en_codec_i2s_rx_ms_bck_p2codec_i2s_rx_ms_bck_p ckgen01_pm(0x0024)
#define reg_sw_en_codec_i2s_rx_ms_bck_p2codec_i2s_rx_ms_bck_p_s 0
#define reg_sw_en_codec_i2s_rx_ms_bck_p2codec_i2s_rx_ms_bck_p_e 0
#define reg_sw_en_dig_mic2dig_mic ckgen01_pm(0x0028)
#define reg_sw_en_dig_mic2dig_mic_s 0
#define reg_sw_en_dig_mic2dig_mic_e 0
#define reg_sw_en_i2s_rx_bck_dg2i2s_rx_bck_dg ckgen01_pm(0x002C)
#define reg_sw_en_i2s_rx_bck_dg2i2s_rx_bck_dg_s 0
#define reg_sw_en_i2s_rx_bck_dg2i2s_rx_bck_dg_e 0
#define reg_sw_en_i2s_test_txi2i2s_test_txi_dg ckgen01_pm(0x0030)
#define reg_sw_en_i2s_test_txi2i2s_test_txi_dg_s 0
#define reg_sw_en_i2s_test_txi2i2s_test_txi_dg_e 0
#define reg_sw_en_i2s_test_txo2i2s_test_txo_dg ckgen01_pm(0x0034)
#define reg_sw_en_i2s_test_txo2i2s_test_txo_dg_s 0
#define reg_sw_en_i2s_test_txo2i2s_test_txo_dg_e 0
#define reg_sw_en_imi_dfs_ref2paganini_imi_ref ckgen01_pm(0x0038)
#define reg_sw_en_imi_dfs_ref2paganini_imi_ref_s 0
#define reg_sw_en_imi_dfs_ref2paganini_imi_ref_e 0
#define reg_sw_en_imi2paganini_imi ckgen01_pm(0x003C)
#define reg_sw_en_imi2paganini_imi_s 0
#define reg_sw_en_imi2paganini_imi_e 0
#define reg_sw_en_nf_synth_ref2nf_synth_ref ckgen01_pm(0x0040)
#define reg_sw_en_nf_synth_ref2nf_synth_ref_s 0
#define reg_sw_en_nf_synth_ref2nf_synth_ref_e 0
#define reg_sw_en_pll2pagadiv2plldiv ckgen01_pm(0x0044)
#define reg_sw_en_pll2pagadiv2plldiv_s 0
#define reg_sw_en_pll2pagadiv2plldiv_e 0
#define reg_sw_en_src_a1_256fsi2src_a1_256fsi ckgen01_pm(0x0048)
#define reg_sw_en_src_a1_256fsi2src_a1_256fsi_s 0
#define reg_sw_en_src_a1_256fsi2src_a1_256fsi_e 0
#define reg_sw_en_paga_pll_sel2paga_pll_sel ckgen01_pm(0x004C)
#define reg_sw_en_paga_pll_sel2paga_pll_sel_s 0
#define reg_sw_en_paga_pll_sel2paga_pll_sel_e 0
#define reg_sw_en_vrec_mac2vrec_mac ckgen01_pm(0x0050)
#define reg_sw_en_vrec_mac2vrec_mac_s 0
#define reg_sw_en_vrec_mac2vrec_mac_e 0
#define reg_sw_en_xtal_24m2cm4 ckgen01_pm(0x0054)
#define reg_sw_en_xtal_24m2cm4_s 0
#define reg_sw_en_xtal_24m2cm4_e 0
#define reg_sw_en_xtal_paganini_testbus2xtal_paganini_testbus ckgen01_pm(0x0058)
#define reg_sw_en_xtal_paganini_testbus2xtal_paganini_testbus_s 0
#define reg_sw_en_xtal_paganini_testbus2xtal_paganini_testbus_e 0
#define reg_sw_en_imi_div22paganini_imi ckgen01_pm(0x005C)
#define reg_sw_en_imi_div22paganini_imi_s 0
#define reg_sw_en_imi_div22paganini_imi_e 0
#define reg_sw_en_smi_div22pm_smi ckgen01_pm(0x0060)
#define reg_sw_en_smi_div22pm_smi_s 0
#define reg_sw_en_smi_div22pm_smi_e 0
#define reg_sw_en_cec12pm ckgen01_pm(0x0064)
#define reg_sw_en_cec12pm_s 0
#define reg_sw_en_cec12pm_e 0
#define reg_sw_en_cec22pm ckgen01_pm(0x0068)
#define reg_sw_en_cec22pm_s 0
#define reg_sw_en_cec22pm_e 0
#define reg_sw_en_cec2pm ckgen01_pm(0x006C)
#define reg_sw_en_cec2pm_s 0
#define reg_sw_en_cec2pm_e 0
#define reg_sw_en_cec32pm ckgen01_pm(0x0070)
#define reg_sw_en_cec32pm_s 0
#define reg_sw_en_cec32pm_e 0
#define reg_sw_en_ddc2pm ckgen01_pm(0x0074)
#define reg_sw_en_ddc2pm_s 0
#define reg_sw_en_ddc2pm_e 0
#define reg_sw_en_dvi_raw02pm ckgen01_pm(0x0078)
#define reg_sw_en_dvi_raw02pm_s 0
#define reg_sw_en_dvi_raw02pm_e 0
#define reg_sw_en_dvi_raw12pm ckgen01_pm(0x007C)
#define reg_sw_en_dvi_raw12pm_s 0
#define reg_sw_en_dvi_raw12pm_e 0
#define reg_sw_en_dvi_raw22pm ckgen01_pm(0x0080)
#define reg_sw_en_dvi_raw22pm_s 0
#define reg_sw_en_dvi_raw22pm_e 0
#define reg_sw_en_dvi_raw32pm ckgen01_pm(0x0084)
#define reg_sw_en_dvi_raw32pm_s 0
#define reg_sw_en_dvi_raw32pm_e 0
#define reg_sw_en_hotplug2pm ckgen01_pm(0x0088)
#define reg_sw_en_hotplug2pm_s 0
#define reg_sw_en_hotplug2pm_e 0
#define reg_sw_en_scdc_p02pm ckgen01_pm(0x008C)
#define reg_sw_en_scdc_p02pm_s 0
#define reg_sw_en_scdc_p02pm_e 0
#define reg_sw_en_scdc_p12pm ckgen01_pm(0x0090)
#define reg_sw_en_scdc_p12pm_s 0
#define reg_sw_en_scdc_p12pm_e 0
#define reg_sw_en_scdc_p22pm ckgen01_pm(0x0094)
#define reg_sw_en_scdc_p22pm_s 0
#define reg_sw_en_scdc_p22pm_e 0
#define reg_sw_en_scdc_p32pm ckgen01_pm(0x0098)
#define reg_sw_en_scdc_p32pm_s 0
#define reg_sw_en_scdc_p32pm_e 0
#define reg_sw_en_sd2pm ckgen01_pm(0x00A4)
#define reg_sw_en_sd2pm_s 0
#define reg_sw_en_sd2pm_e 0
#define reg_sw_en_adcpll_test2ephy ckgen01_pm(0x00A8)
#define reg_sw_en_adcpll_test2ephy_s 0
#define reg_sw_en_adcpll_test2ephy_e 0
#define reg_sw_en_emac_testrx1252pm ckgen01_pm(0x00B4)
#define reg_sw_en_emac_testrx1252pm_s 0
#define reg_sw_en_emac_testrx1252pm_e 0
#define reg_sw_en_gmac_rx2eth ckgen01_pm(0x00B8)
#define reg_sw_en_gmac_rx2eth_s 0
#define reg_sw_en_gmac_rx2eth_e 0
#define reg_sw_en_gmac_tx2eth ckgen01_pm(0x00BC)
#define reg_sw_en_gmac_tx2eth_s 0
#define reg_sw_en_gmac_tx2eth_e 0
#define reg_sw_en_gmac_tx_pad2eth ckgen01_pm(0x00C0)
#define reg_sw_en_gmac_tx_pad2eth_s 0
#define reg_sw_en_gmac_tx_pad2eth_e 0
#define reg_sw_en_clk_125m_tx_eee2ephy ckgen01_pm(0x00C4)
#define reg_sw_en_clk_125m_tx_eee2ephy_s 0
#define reg_sw_en_clk_125m_tx_eee2ephy_e 0
#define reg_sw_en_clk_25m_rx2ephy ckgen01_pm(0x00C8)
#define reg_sw_en_clk_25m_rx2ephy_s 0
#define reg_sw_en_clk_25m_rx2ephy_e 0
#define reg_sw_en_clk_25m_tx2ephy ckgen01_pm(0x00CC)
#define reg_sw_en_clk_25m_tx2ephy_s 0
#define reg_sw_en_clk_25m_tx2ephy_e 0
#define reg_sw_en_clk_2p5m_rx2ephy ckgen01_pm(0x00D0)
#define reg_sw_en_clk_2p5m_rx2ephy_s 0
#define reg_sw_en_clk_2p5m_rx2ephy_e 0
#define reg_sw_en_clk_2p5m_tx2ephy ckgen01_pm(0x00D4)
#define reg_sw_en_clk_2p5m_tx2ephy_s 0
#define reg_sw_en_clk_2p5m_tx2ephy_e 0
#define reg_sw_en_dac1x2ephy ckgen01_pm(0x00D8)
#define reg_sw_en_dac1x2ephy_s 0
#define reg_sw_en_dac1x2ephy_e 0
#define reg_sw_en_dac2x2ephy ckgen01_pm(0x00DC)
#define reg_sw_en_dac2x2ephy_s 0
#define reg_sw_en_dac2x2ephy_e 0
#define reg_sw_en_dactx2ephy ckgen01_pm(0x00E0)
#define reg_sw_en_dactx2ephy_s 0
#define reg_sw_en_dactx2ephy_e 0
#define reg_sw_en_ethpll_250m2ephy ckgen01_pm(0x00E4)
#define reg_sw_en_ethpll_250m2ephy_s 0
#define reg_sw_en_ethpll_250m2ephy_e 0
#define reg_sw_en_ls2ephy ckgen01_pm(0x00E8)
#define reg_sw_en_ls2ephy_s 0
#define reg_sw_en_ls2ephy_e 0
#define reg_sw_en_mcu_62p52ephy ckgen01_pm(0x00EC)
#define reg_sw_en_mcu_62p52ephy_s 0
#define reg_sw_en_mcu_62p52ephy_e 0
#define reg_sw_en_mii_rx_free2ephy ckgen01_pm(0x00F0)
#define reg_sw_en_mii_rx_free2ephy_s 0
#define reg_sw_en_mii_rx_free2ephy_e 0
#define reg_sw_en_mii_rx2ephy ckgen01_pm(0x00F4)
#define reg_sw_en_mii_rx2ephy_s 0
#define reg_sw_en_mii_rx2ephy_e 0
#define reg_sw_en_mii_tx2ephy ckgen01_pm(0x00F8)
#define reg_sw_en_mii_tx2ephy_s 0
#define reg_sw_en_mii_tx2ephy_e 0
#define reg_sw_en_rx_22ephy ckgen01_pm(0x00FC)
#define reg_sw_en_rx_22ephy_s 0
#define reg_sw_en_rx_22ephy_e 0
#define reg_sw_en_rx_gat1002ephy ckgen01_pm(0x0100)
#define reg_sw_en_rx_gat1002ephy_s 0
#define reg_sw_en_rx_gat1002ephy_e 0
#define reg_sw_en_rx2ephy ckgen01_pm(0x0104)
#define reg_sw_en_rx2ephy_s 0
#define reg_sw_en_rx2ephy_e 0
#define reg_sw_en_rx_lpi2ephy ckgen01_pm(0x0108)
#define reg_sw_en_rx_lpi2ephy_s 0
#define reg_sw_en_rx_lpi2ephy_e 0
#define reg_sw_en_xin_free2ephy ckgen01_pm(0x010C)
#define reg_sw_en_xin_free2ephy_s 0
#define reg_sw_en_xin_free2ephy_e 0
#define reg_sw_en_xin2ephy ckgen01_pm(0x0110)
#define reg_sw_en_xin2ephy_s 0
#define reg_sw_en_xin2ephy_e 0
#define reg_sw_en_mcu_bus_pm2pm ckgen01_pm(0x011C)
#define reg_sw_en_mcu_bus_pm2pm_s 0
#define reg_sw_en_mcu_bus_pm2pm_e 0
#define reg_sw_en_mcu_pm2pm ckgen01_pm(0x0120)
#define reg_sw_en_mcu_pm2pm_s 0
#define reg_sw_en_mcu_pm2pm_e 0
#define reg_sw_en_mcu_pm2cm4 ckgen01_pm(0x0120)
#define reg_sw_en_mcu_pm2cm4_s 1
#define reg_sw_en_mcu_pm2cm4_e 1
#define reg_sw_en_mcu_pm2pm51 ckgen01_pm(0x0120)
#define reg_sw_en_mcu_pm2pm51_s 2
#define reg_sw_en_mcu_pm2pm51_e 2
#define reg_sw_en_miic0_pm2pm ckgen01_pm(0x0124)
#define reg_sw_en_miic0_pm2pm_s 0
#define reg_sw_en_miic0_pm2pm_e 0
#define reg_sw_en_miic1_pm2pm ckgen01_pm(0x0128)
#define reg_sw_en_miic1_pm2pm_s 0
#define reg_sw_en_miic1_pm2pm_e 0
#define reg_sw_en_spi_pm2pm ckgen01_pm(0x012C)
#define reg_sw_en_spi_pm2pm_s 0
#define reg_sw_en_spi_pm2pm_e 0
#define reg_sw_en_uart0_pm2pm ckgen01_pm(0x0130)
#define reg_sw_en_uart0_pm2pm_s 0
#define reg_sw_en_uart0_pm2pm_e 0
#define reg_sw_en_uart0_pm_synth2pm ckgen01_pm(0x0134)
#define reg_sw_en_uart0_pm_synth2pm_s 0
#define reg_sw_en_uart0_pm_synth2pm_e 0
#define reg_sw_en_uart1_pm2pm ckgen01_pm(0x0138)
#define reg_sw_en_uart1_pm2pm_s 0
#define reg_sw_en_uart1_pm2pm_e 0
#define reg_sw_en_uart1_pm_synth2pm ckgen01_pm(0x013C)
#define reg_sw_en_uart1_pm_synth2pm_s 0
#define reg_sw_en_uart1_pm_synth2pm_e 0
#define reg_sw_en_fuart0_pm2pm ckgen01_pm(0x0140)
#define reg_sw_en_fuart0_pm2pm_s 0
#define reg_sw_en_fuart0_pm2pm_e 0
#define reg_sw_en_fuart0_pm_synth2pm ckgen01_pm(0x0144)
#define reg_sw_en_fuart0_pm_synth2pm_s 0
#define reg_sw_en_fuart0_pm_synth2pm_e 0
#define reg_sw_en_xiu_rx2pm ckgen01_pm(0x0148)
#define reg_sw_en_xiu_rx2pm_s 0
#define reg_sw_en_xiu_rx2pm_e 0
#define reg_sw_en_mcu_nonpm2pm ckgen01_pm(0x0150)
#define reg_sw_en_mcu_nonpm2pm_s 0
#define reg_sw_en_mcu_nonpm2pm_e 0
#define reg_sw_en_ir2pm ckgen01_pm(0x0164)
#define reg_sw_en_ir2pm_s 0
#define reg_sw_en_ir2pm_e 0
#define reg_sw_en_kref2pm ckgen01_pm(0x0168)
#define reg_sw_en_kref2pm_s 0
#define reg_sw_en_kref2pm_e 0
#define reg_sw_en_pm_sleep2pm ckgen01_pm(0x016C)
#define reg_sw_en_pm_sleep2pm_s 0
#define reg_sw_en_pm_sleep2pm_e 0
#define reg_sw_en_rtc22pm ckgen01_pm(0x0170)
#define reg_sw_en_rtc22pm_s 0
#define reg_sw_en_rtc22pm_e 0
#define reg_sw_en_rtc2pm ckgen01_pm(0x0174)
#define reg_sw_en_rtc2pm_s 0
#define reg_sw_en_rtc2pm_e 0
#define reg_sw_en_sar2pm ckgen01_pm(0x0178)
#define reg_sw_en_sar2pm_s 0
#define reg_sw_en_sar2pm_e 0
#define reg_sw_en_pwm_pm2pm ckgen01_pm(0x0184)
#define reg_sw_en_pwm_pm2pm_s 0
#define reg_sw_en_pwm_pm2pm_e 0
#define reg_sw_en_ahb2pm_ssusb ckgen01_pm(0x018C)
#define reg_sw_en_ahb2pm_ssusb_s 0
#define reg_sw_en_ahb2pm_ssusb_e 0
#define reg_sw_en_ahb2pm_ssusb_u3phy ckgen01_pm(0x018C)
#define reg_sw_en_ahb2pm_ssusb_u3phy_s 1
#define reg_sw_en_ahb2pm_ssusb_u3phy_e 1
#define reg_sw_en_ahb2ssusb_u2phy ckgen01_pm(0x018C)
#define reg_sw_en_ahb2ssusb_u2phy_s 2
#define reg_sw_en_ahb2ssusb_u2phy_e 2
#define reg_sw_en_ahb2pm_pextp ckgen01_pm(0x018C)
#define reg_sw_en_ahb2pm_pextp_s 3
#define reg_sw_en_ahb2pm_pextp_e 3
#define reg_sw_en_axi2pm_ssusb ckgen01_pm(0x0190)
#define reg_sw_en_axi2pm_ssusb_s 0
#define reg_sw_en_axi2pm_ssusb_e 0
#define reg_sw_en_axi2pm_pextp ckgen01_pm(0x0190)
#define reg_sw_en_axi2pm_pextp_s 1
#define reg_sw_en_axi2pm_pextp_e 1
#define reg_sw_en_mcu_pm2pm_ssusb ckgen01_pm(0x0194)
#define reg_sw_en_mcu_pm2pm_ssusb_s 0
#define reg_sw_en_mcu_pm2pm_ssusb_e 0
#define reg_sw_en_mcu_pm2pm_ssusb_u3phy ckgen01_pm(0x0194)
#define reg_sw_en_mcu_pm2pm_ssusb_u3phy_s 1
#define reg_sw_en_mcu_pm2pm_ssusb_u3phy_e 1
#define reg_sw_en_mcu_pm2ssusb_u2phy ckgen01_pm(0x0194)
#define reg_sw_en_mcu_pm2ssusb_u2phy_s 2
#define reg_sw_en_mcu_pm2ssusb_u2phy_e 2
#define reg_sw_en_mcu_pm2pm_pextp ckgen01_pm(0x0194)
#define reg_sw_en_mcu_pm2pm_pextp_s 3
#define reg_sw_en_mcu_pm2pm_pextp_e 3
#define reg_sw_en_ssusb_dma2pm_ssusb ckgen01_pm(0x0198)
#define reg_sw_en_ssusb_dma2pm_ssusb_s 0
#define reg_sw_en_ssusb_dma2pm_ssusb_e 0
#define reg_sw_en_ssusb_frmcnt2pm_ssusb ckgen01_pm(0x019C)
#define reg_sw_en_ssusb_frmcnt2pm_ssusb_s 0
#define reg_sw_en_ssusb_frmcnt2pm_ssusb_e 0
#define reg_sw_en_ssusb_pclk2pm_ssusb ckgen01_pm(0x01A0)
#define reg_sw_en_ssusb_pclk2pm_ssusb_s 0
#define reg_sw_en_ssusb_pclk2pm_ssusb_e 0
#define reg_sw_en_ssusb_scl2pm_ssusb ckgen01_pm(0x01A4)
#define reg_sw_en_ssusb_scl2pm_ssusb_s 0
#define reg_sw_en_ssusb_scl2pm_ssusb_e 0
#define reg_sw_en_ssusb_sdin2pm_ssusb ckgen01_pm(0x01A8)
#define reg_sw_en_ssusb_sdin2pm_ssusb_s 0
#define reg_sw_en_ssusb_sdin2pm_ssusb_e 0
#define reg_sw_en_ssusb_sys2pm_ssusb ckgen01_pm(0x01AC)
#define reg_sw_en_ssusb_sys2pm_ssusb_s 0
#define reg_sw_en_ssusb_sys2pm_ssusb_e 0
#define reg_sw_en_ssusb_utmi2pm_ssusb ckgen01_pm(0x01B0)
#define reg_sw_en_ssusb_utmi2pm_ssusb_s 0
#define reg_sw_en_ssusb_utmi2pm_ssusb_e 0
#define reg_sw_en_ssusb_xhci2pm_ssusb ckgen01_pm(0x01B4)
#define reg_sw_en_ssusb_xhci2pm_ssusb_s 0
#define reg_sw_en_ssusb_xhci2pm_ssusb_e 0
#define reg_sw_en_xtal_24m_pm2pm_ssusb ckgen01_pm(0x01B8)
#define reg_sw_en_xtal_24m_pm2pm_ssusb_s 0
#define reg_sw_en_xtal_24m_pm2pm_ssusb_e 0
#define reg_sw_en_xtal_24m_pm2pm_ssusb_u3phy ckgen01_pm(0x01B8)
#define reg_sw_en_xtal_24m_pm2pm_ssusb_u3phy_s 1
#define reg_sw_en_xtal_24m_pm2pm_ssusb_u3phy_e 1
#define reg_sw_en_xtal_24m_pm2ssusb_u2phy ckgen01_pm(0x01B8)
#define reg_sw_en_xtal_24m_pm2ssusb_u2phy_s 2
#define reg_sw_en_xtal_24m_pm2ssusb_u2phy_e 2
#define reg_sw_en_xtal_24m_pm2pm_pextp ckgen01_pm(0x01B8)
#define reg_sw_en_xtal_24m_pm2pm_pextp_s 3
#define reg_sw_en_xtal_24m_pm2pm_pextp_e 3
#define reg_sw_en_pextp_tl2pm_pextp ckgen01_pm(0x01BC)
#define reg_sw_en_pextp_tl2pm_pextp_s 3
#define reg_sw_en_pextp_tl2pm_pextp_e 3
#define reg_sw_en_xtal_12m_pm2pm_pad_top ckgen01_pm(0x01CC)
#define reg_sw_en_xtal_12m_pm2pm_pad_top_s 0
#define reg_sw_en_xtal_12m_pm2pm_pad_top_e 0
#define reg_sw_en_xtal_24m_pm2pm_mbist ckgen01_pm(0x01DC)
#define reg_sw_en_xtal_24m_pm2pm_mbist_s 0
#define reg_sw_en_xtal_24m_pm2pm_mbist_e 0
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_pm ckgen01_pm(0x01E0)
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_pm_s 0
#define reg_sw_en_riu_nonpm2riu_dft_nonpm_pm_e 0
#define reg_ckgen01_pm_dummy0 ckgen01_pm(0x01F8)
#define reg_ckgen01_pm_dummy0_s 0
#define reg_ckgen01_pm_dummy0_e 15
#define reg_ckgen01_pm_dummy1 ckgen01_pm(0x01FC)
#define reg_ckgen01_pm_dummy1_s 0
#define reg_ckgen01_pm_dummy1_e 15

#endif
