#ifndef _TGEN_REGEN_BK_H
#define _TGEN_REGEN_BK_H

#define TGEN_REGEN_BKA39C 0x01473800

//Page TGEN_REGEN_BKA39C
#define REG_0004_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x004)
    #define REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_NP_MD Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_REGEN_CNT_SRC_SEL_V3 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_CNT_SW_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_SW_RST_XTALI Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_SW_RST_ODCLK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_000C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x00C)
    #define REG_000C_TGEN_REGEN_BKA39C_REG_TGEN_TESTBUS_SEL Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_000C_TGEN_REGEN_BKA39C_REG_TGEN_DEBUG_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_000C_TGEN_REGEN_BKA39C_REG_TGEN_DEBUG_READBACK_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0010_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x010)
    #define REG_0010_TGEN_REGEN_BKA39C_REG_TGEN_DEBUG_READBACK_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x014)
    #define REG_0014_TGEN_REGEN_BKA39C_REG_TGEN_DEBUG_READBACK_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0018_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x018)
    #define REG_0018_TGEN_REGEN_BKA39C_REG_TGEN_DEBUG_READBACK_2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x01C)
    #define REG_001C_TGEN_REGEN_BKA39C_REG_TGEN_DEBUG_READBACK_3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x020)
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_VDE_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_IN_OUT_SEL_V3 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_CLR_RPFP_SEL_V3 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_STR_RPFP_SEL_V3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_CLR_SEL_V3 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_STR_SEL_V3 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0020_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_SRC_SEL Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0024_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x024)
    #define REG_0024_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_VALUE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x028)
    #define REG_0028_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x02C)
    #define REG_002C_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_VDE_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0030_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x030)
    #define REG_0030_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_VDE_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x034)
    #define REG_0034_TGEN_REGEN_BKA39C_REG_TGEN_INTR_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0038_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x038)
    #define REG_0038_TGEN_REGEN_BKA39C_REG_TGEN_DB_OFF Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_TGEN_DB_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_VDE_DB_OFF_V3 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_TGEN_CHK_SUM_VDE_DB_SEL_V3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_REGEN_CNT_CLR_DB_OFF_V3 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_REGEN_CNT_CLR_DB_SEL_V3 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_TGEN_DB_FLAG Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0038_TGEN_REGEN_BKA39C_REG_TGEN_SETTING_DONE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_003C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x03C)
    #define REG_003C_TGEN_REGEN_BKA39C_REG_TGEN_DB_REF_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x040)
    #define REG_0040_TGEN_REGEN_BKA39C_REG_HCNT_INI_VAL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x044)
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_OF_KEEP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REGEN_CLR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REGEN_CLR_LEVEL_V3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REGEN_CLR_PULSE_V3 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REGEN_CLR_EN_DB_SEL_V3 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REGEN_CLR_EN_DB_OFF_V3 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REPORT_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_004C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x04C)
    #define REG_004C_TGEN_REGEN_BKA39C_REG_HTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x050)
    #define REG_0050_TGEN_REGEN_BKA39C_REG_HSYNC_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x054)
    #define REG_0054_TGEN_REGEN_BKA39C_REG_HSYNC_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0058_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x058)
    #define REG_0058_TGEN_REGEN_BKA39C_REG_HDE_FRAME_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_005C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x05C)
    #define REG_005C_TGEN_REGEN_BKA39C_REG_HDE_FRAME_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x070)
	#define REG_0070_TGEN_REGEN_BKA39C_REG_HDE_FRAME_TCON_ST_V3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x074)
	#define REG_0074_TGEN_REGEN_BKA39C_REG_HDE_FRAME_TCON_END_V3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_007C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x07C)
    #define REG_007C_TGEN_REGEN_BKA39C_REG_REGEN_CNT_CLR_HCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0080_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x080)
    #define REG_0080_TGEN_REGEN_BKA39C_REG_VCNT_INI_VAL Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0084_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x084)
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_OF_KEEP_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_EQ_VTT_STOP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_EVEN_VTT_VCNT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REGEN_CLR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REGEN_CLR_LEVEL_V3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REGEN_CLR_PULSE_V3 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REGEN_CLR_EN_DB_SEL_V3 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REGEN_CLR_EN_DB_OFF_V3 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REPORT_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_008C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x08C)
    #define REG_008C_TGEN_REGEN_BKA39C_REG_VTT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x090)
    #define REG_0090_TGEN_REGEN_BKA39C_REG_VSYNC_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0094_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x094)
    #define REG_0094_TGEN_REGEN_BKA39C_REG_VSYNC_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0098_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x098)
    #define REG_0098_TGEN_REGEN_BKA39C_REG_VDE_FRAME_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_009C_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x09C)
    #define REG_009C_TGEN_REGEN_BKA39C_REG_VDE_FRAME_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B0_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x0B0)
	#define REG_00B0_TGEN_REGEN_BKA39C_REG_VDE_FRAME_TCON_ST_V3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B4_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x0B4)
	#define REG_00B4_TGEN_REGEN_BKA39C_REG_VDE_FRAME_TCON_END_V3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_TGEN_REGEN_BKA39C (TGEN_REGEN_BKA39C + 0x0BC)
    #define REG_00BC_TGEN_REGEN_BKA39C_REG_REGEN_CNT_CLR_VCNT Fld(16,0,AC_FULLW10)//[15:0]

#endif
