#define PADJ_TOP_BKA4D6 0x0149AC00

//Page PADJ_TOP_BKA4D6_1
#define REG_0004_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x004)
    #define REG_0004_PADJ_TOP_BKA4D6_REG_PA_BYPASS_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_PADJ_TOP_BKA4D6_REG_PA_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0004_PADJ_TOP_BKA4D6_REG_PA_HW_CLK_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0004_PADJ_TOP_BKA4D6_REG_PA_11BITS_MODE_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0004_PADJ_TOP_BKA4D6_REG_PA_DB_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0004_PADJ_TOP_BKA4D6_REG_PA_SW_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x008)
    #define REG_0008_PADJ_TOP_BKA4D6_REG_HORI_START Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x00C)
    #define REG_000C_PADJ_TOP_BKA4D6_REG_HORI_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0010_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x010)
    #define REG_0010_PADJ_TOP_BKA4D6_REG_VERT_START Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x014)
    #define REG_0014_PADJ_TOP_BKA4D6_REG_VERT_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0018_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x018)
    #define REG_0018_PADJ_TOP_BKA4D6_REG_PA_ACCU_PROTECT_HSIZE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x01C)
    #define REG_001C_PADJ_TOP_BKA4D6_REG_B2P_ADL_PRELOAD_LINE Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_001C_PADJ_TOP_BKA4D6_REG_B2P_ADL_SW_TRIG Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_001C_PADJ_TOP_BKA4D6_REG_B2P_ADL_SW_TRIG_MODE_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_001C_PADJ_TOP_BKA4D6_REG_B2P_ADL_TRIG_MASK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0020_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x020)
    #define REG_0020_PADJ_TOP_BKA4D6_REG_PA_ED_MODE Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_0020_PADJ_TOP_BKA4D6_REG_PA_PATGEN_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0020_PADJ_TOP_BKA4D6_REG_PA_CURSOR_WIDTH Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0020_PADJ_TOP_BKA4D6_REG_PA_HIST_UP_PERMISSION Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0024_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x024)
    #define REG_0024_PADJ_TOP_BKA4D6_REG_PA_CURSOR_X Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x028)
    #define REG_0028_PADJ_TOP_BKA4D6_REG_PA_CURSOR_Y Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x02C)
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_DEBUG_MODE_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_DEBUG_MODE_SEL Fld(4,1,AC_MSKB0)//[4:1]
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_DEBUG_MODE_B_MUX Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_DEBUG_OUT_SHIFT Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_NOISE_DITHER_PSE_RST_NUM Fld(2,9,AC_MSKB1)//[10:9]
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_NOISE_DITHER_RST_E_4_FRAME Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_002C_PADJ_TOP_BKA4D6_REG_PA_DITHER_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0030_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x030)
    #define REG_0030_PADJ_TOP_BKA4D6_REG_PA_SIN_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x034)
    #define REG_0034_PADJ_TOP_BKA4D6_REG_PA_VIN_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0038_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x038)
    #define REG_0038_PADJ_TOP_BKA4D6_REG_PA_SOUT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define REG_003C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x03C)
    #define REG_003C_PADJ_TOP_BKA4D6_REG_PA_VOUT_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x060)
    #define REG_0060_PADJ_TOP_BKA4D6_REG_PA_REFER_OSD_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0060_PADJ_TOP_BKA4D6_REG_PA_REFER_MCG_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0060_PADJ_TOP_BKA4D6_REG_PA_REFER_PURE_COLOR_BOOST_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0060_PADJ_TOP_BKA4D6_REG_PA_OSD_ALPHA_INV_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0060_PADJ_TOP_BKA4D6_REG_PA_PQ_BOOST_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0060_PADJ_TOP_BKA4D6_REG_RGB_CH_MODE Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0060_PADJ_TOP_BKA4D6_REG_PA_AWB_MODE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0064_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x064)
    #define REG_0064_PADJ_TOP_BKA4D6_REG_PA_OSD_ALPHA_THRD Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0068_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x068)
    #define REG_0068_PADJ_TOP_BKA4D6_REG_PA_OSD_ALPHA_SLOPE Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0068_PADJ_TOP_BKA4D6_REG_PA_OSD_ALPHA_SLOPE_SHIFT Fld(3,12,AC_MSKB1)//[14:12]
#define REG_006C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x06C)
    #define REG_006C_PADJ_TOP_BKA4D6_REG_PA_MCG_WEIGHT_THRD Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_006C_PADJ_TOP_BKA4D6_REG_PA_MCG_WEIGHT_SLOPE Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0070_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x070)
    #define REG_0070_PADJ_TOP_BKA4D6_REG_PA_PURE_COLOR_BOOST_WEIGHT_THRD Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0070_PADJ_TOP_BKA4D6_REG_PA_PURE_COLOR_BOOST_WEIGHT_SLOPE Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_0070_PADJ_TOP_BKA4D6_REG_PA_PQGAIN_SHIFT6_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0074_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x074)
    #define REG_0074_PADJ_TOP_BKA4D6_REG_PA_MIN_CH_GAIN Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0078_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x078)
    #define REG_0078_PADJ_TOP_BKA4D6_REG_PA_MED_CH_GAIN Fld(12,0,AC_MSKW10)//[11:0]
#define REG_007C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x07C)
    #define REG_007C_PADJ_TOP_BKA4D6_REG_PA_MAX_CH_GAIN Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0080_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x080)
    #define REG_0080_PADJ_TOP_BKA4D6_REG_PA_APL_X_START Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0084_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x084)
    #define REG_0084_PADJ_TOP_BKA4D6_REG_PA_APL_X_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x088)
    #define REG_0088_PADJ_TOP_BKA4D6_REG_PA_APL_Y_START Fld(16,0,AC_FULLW10)//[15:0]
#define REG_008C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x08C)
    #define REG_008C_PADJ_TOP_BKA4D6_REG_PA_APL_Y_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x090)
    #define REG_0090_PADJ_TOP_BKA4D6_REG_PA_APL_WB_GAIN_R Fld(11,0,AC_MSKW10)//[10:0]
    #define REG_0090_PADJ_TOP_BKA4D6_REG_PA_APL_DEGAMMA_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0090_PADJ_TOP_BKA4D6_REG_PA_APL_GAMMA_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0090_PADJ_TOP_BKA4D6_REG_PA_APL_DITHER_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0094_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x094)
    #define REG_0094_PADJ_TOP_BKA4D6_REG_PA_APL_WB_GAIN_G Fld(11,0,AC_MSKW10)//[10:0]
    #define REG_0094_PADJ_TOP_BKA4D6_REG_PA_APL_DIV_SHIFT Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0098_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x098)
    #define REG_0098_PADJ_TOP_BKA4D6_REG_PA_APL_WB_GAIN_B Fld(11,0,AC_MSKW10)//[10:0]
#define REG_009C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x09C)
    #define REG_009C_PADJ_TOP_BKA4D6_REG_PA_APL_DIV_VAL Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0A0)
    #define REG_00A0_PADJ_TOP_BKA4D6_REG_ADL_RAM_RIU_MODE_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_00A4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0A4)
    #define REG_00A4_PADJ_TOP_BKA4D6_REG_ADL_RAM_ADDR Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00A4_PADJ_TOP_BKA4D6_REG_ADL_RAM_R_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00A4_PADJ_TOP_BKA4D6_REG_ADL_RAM_W_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00A8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0A8)
    #define REG_00A8_PADJ_TOP_BKA4D6_REG_ADL_RAM_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00B0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0B0)
    #define REG_00B0_PADJ_TOP_BKA4D6_REG_ADL_RAM_DAT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0B4)
    #define REG_00B4_PADJ_TOP_BKA4D6_REG_ADL_RAM_DAT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0B8)
    #define REG_00B8_PADJ_TOP_BKA4D6_REG_ADL_RAM_DAT_2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0BC)
    #define REG_00BC_PADJ_TOP_BKA4D6_REG_ADL_RAM_DAT_3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0C0)
    #define REG_00C0_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0C4)
    #define REG_00C4_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0C8)
    #define REG_00C8_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0CC)
    #define REG_00CC_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0D0)
    #define REG_00D0_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0D4)
    #define REG_00D4_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_5 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0D8)
    #define REG_00D8_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_6 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0DC)
    #define REG_00DC_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_7 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0E0)
    #define REG_00E0_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0E4)
    #define REG_00E4_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_9 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0E8)
    #define REG_00E8_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_10 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0EC)
    #define REG_00EC_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_11 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0F0)
    #define REG_00F0_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_12 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0F4)
    #define REG_00F4_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_13 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0F8)
    #define REG_00F8_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_14 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00FC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x0FC)
    #define REG_00FC_PADJ_TOP_BKA4D6_REG_ADL_RAM_WD_15 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x100)
    #define REG_0100_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_START_00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0100_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_END_00 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0104_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x104)
    #define REG_0104_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_START_00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0104_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_END_00 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0108_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x108)
    #define REG_0108_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_START_00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0108_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_END_00 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_010C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x10C)
    #define REG_010C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_START_00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_010C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_END_00 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0110_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x110)
    #define REG_0110_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_START_01 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0110_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_END_01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0114_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x114)
    #define REG_0114_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_START_01 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0114_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_END_01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0118_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x118)
    #define REG_0118_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_START_01 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0118_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_END_01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_011C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x11C)
    #define REG_011C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_START_01 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_011C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_END_01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0120_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x120)
    #define REG_0120_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_START_02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0120_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_END_02 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0124_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x124)
    #define REG_0124_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_START_02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0124_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_END_02 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0128_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x128)
    #define REG_0128_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_START_02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0128_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_END_02 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_012C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x12C)
    #define REG_012C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_START_02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_012C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_END_02 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0130_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x130)
    #define REG_0130_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_START_03 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0130_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_HUE_END_03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0134_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x134)
    #define REG_0134_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_START_03 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0134_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SAT_END_03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0138_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x138)
    #define REG_0138_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_START_03 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0138_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_VAL_END_03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_013C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x13C)
    #define REG_013C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_START_03 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_013C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_ALPHA_END_03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0140_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x140)
    #define REG_0140_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_BLK_NUM_H Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0140_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_BLK_NUM_V Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0144_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x144)
    #define REG_0144_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_BLK_RATIO_W_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0148_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x148)
    #define REG_0148_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_BLK_RATIO_W_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_014C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x14C)
    #define REG_014C_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_BLK_RATIO_H_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0150_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x150)
    #define REG_0150_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_BLK_RATIO_H_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0154_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x154)
    #define REG_0154_PADJ_TOP_BKA4D6_REG_PA_COLOR_AREA_HIST_SHIFT Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0154_PADJ_TOP_BKA4D6_REG_PA_COLOR_HIST_AUL_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0154_PADJ_TOP_BKA4D6_REG_PA_ACCU_H_PROTECT_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0154_PADJ_TOP_BKA4D6_REG_PA_ACCU_H_PROTECT_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0154_PADJ_TOP_BKA4D6_REG_PA_ACCU_COLOR Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0158_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x158)
    #define REG_0158_PADJ_TOP_BKA4D6_REG_PA_COLOR_AUL_TRIG_DLY Fld(15,0,AC_MSKW10)//[14:0]
    #define REG_0158_PADJ_TOP_BKA4D6_REG_AUL_FF_SWRST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_015C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x15C)
    #define REG_015C_PADJ_TOP_BKA4D6_REG_AUL_NUM Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_015C_PADJ_TOP_BKA4D6_REG_AUL_TRIG_MUX Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0160_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x160)
    #define REG_0160_PADJ_TOP_BKA4D6_REG_PA_APL_USR Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0160_PADJ_TOP_BKA4D6_REG_PA_APL_USR_MODE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0164_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x164)
    #define REG_0164_PADJ_TOP_BKA4D6_REG_PA_APL_OUT_RPT Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0164_PADJ_TOP_BKA4D6_REG_PA_APL_UP_PERMISSION Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0168_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x168)
    #define REG_0168_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_RPT Fld(10,0,AC_MSKW10)//[9:0]
#define REG_016C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x16C)
    #define REG_016C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_USR Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_016C_PADJ_TOP_BKA4D6_REG_PA_APL_OUT_RE_ALIGN Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_016C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_USR_MODE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0170_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x170)
    #define REG_0170_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RPT Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0174_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x174)
    #define REG_0174_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_TAP Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0174_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0178_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x178)
    #define REG_0178_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_HW_RESET_THRD Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0178_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_RESET_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0178_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_SW_RESET_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0178_PADJ_TOP_BKA4D6_REG_PA_APL_FIR_HW_RESET_EN Fld(1,13,AC_MSKB1)//[13:13]
#define REG_017C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x17C)
    #define REG_017C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_HW_RESET_THRD Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_017C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RESET_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_017C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_SW_RESET_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_017C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_HW_RESET_EN Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0180_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x180)
    #define REG_0180_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RESET_PRV_IIR_VAL Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0180_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RESET_PRV_IIR_VAL_SW_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0180_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RESET_CTRL_RATIO_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0180_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x184)
    #define REG_0184_PADJ_TOP_BKA4D6_REG_PA_OLED_BOOST_FINAL_GAIN Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0184_PADJ_TOP_BKA4D6_REG_PA_APL_AUTO_CTRL_GAIN_INPUT_MUX Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0184_PADJ_TOP_BKA4D6_REG_PA_APL_AUTO_CTRL_GAIN_RPT Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_0184_PADJ_TOP_BKA4D6_REG_PA_APL_AUTO_CTRL_GAIN_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_018C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x18C)
    #define REG_018C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_TARGET_GAMMA_OFFSET Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_018C_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_TARGET_GAMMA_STEP Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0190_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x190)
    #define REG_0190_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RATIO_OFFSET Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0190_PADJ_TOP_BKA4D6_REG_PA_APL_IIR_RATIO_STEP Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0194_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x194)
    #define REG_0194_PADJ_TOP_BKA4D6_REG_PA_APL_AUTO_CTRL_GAIN_OFFSET Fld(10,0,AC_MSKW10)//[9:0]
    #define REG_0194_PADJ_TOP_BKA4D6_REG_PA_APL_AUTO_CTRL_GAIN_STEP Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0198_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x198)
    #define REG_0198_PADJ_TOP_BKA4D6_REG_PA_APL_OUTPUT_MIN Fld(10,0,AC_MSKW10)//[9:0]
#define REG_019C_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x19C)
    #define REG_019C_PADJ_TOP_BKA4D6_REG_PA_APL_OUTPUT_MAX Fld(10,0,AC_MSKW10)//[9:0]
#define REG_01A0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1A0)
    #define REG_01A0_PADJ_TOP_BKA4D6_REG_B2P_LBX_HST Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01A0_PADJ_TOP_BKA4D6_REG_B2P_LBX_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01A4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1A4)
    #define REG_01A4_PADJ_TOP_BKA4D6_REG_B2P_LBX_HEND Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01A4_PADJ_TOP_BKA4D6_REG_B2P_ADL_WRITE_DONE_SW Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01A8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1A8)
    #define REG_01A8_PADJ_TOP_BKA4D6_REG_B2P_LBX_VST Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01A8_PADJ_TOP_BKA4D6_REG_B2P_V_FLIP_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01AC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1AC)
    #define REG_01AC_PADJ_TOP_BKA4D6_REG_B2P_LBX_VEND Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01AC_PADJ_TOP_BKA4D6_REG_B2P_H_MIRROR_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01B0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1B0)
    #define REG_01B0_PADJ_TOP_BKA4D6_REG_B2P_WIDTH Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01B4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1B4)
    #define REG_01B4_PADJ_TOP_BKA4D6_REG_B2P_HEIGHT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01B8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1B8)
    #define REG_01B8_PADJ_TOP_BKA4D6_REG_B2P_ADL_CNT_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01BC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1BC)
    #define REG_01BC_PADJ_TOP_BKA4D6_REG_B2P_ADL_CNT_V Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01C0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1C0)
    #define REG_01C0_PADJ_TOP_BKA4D6_REG_INI_FACTOR_HO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1C4)
    #define REG_01C4_PADJ_TOP_BKA4D6_REG_INI_FACTOR_HO_1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01C8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1C8)
    #define REG_01C8_PADJ_TOP_BKA4D6_REG_INI_FACTOR_VE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1CC)
    #define REG_01CC_PADJ_TOP_BKA4D6_REG_INI_FACTOR_VE_1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01D0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1D0)
    #define REG_01D0_PADJ_TOP_BKA4D6_REG_SCALE_FACTOR_HO_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1D4)
    #define REG_01D4_PADJ_TOP_BKA4D6_REG_SCALE_FACTOR_HO_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_01D4_PADJ_TOP_BKA4D6_REG_SCALE_FACTOR_HO_MSB Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_01D4_PADJ_TOP_BKA4D6_REG_SCALE_HO_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01D4_PADJ_TOP_BKA4D6_REG_H_SHIFT_MODE_EN Fld(1,9,AC_MSKB1)//[9:9]
#define REG_01D8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1D8)
    #define REG_01D8_PADJ_TOP_BKA4D6_REG_SCALE_FACTOR_VE_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01DC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1DC)
    #define REG_01DC_PADJ_TOP_BKA4D6_REG_SCALE_FACTOR_VE_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_01DC_PADJ_TOP_BKA4D6_REG_SCALE_VE_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01DC_PADJ_TOP_BKA4D6_REG_V_SHIFT_MODE_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01DC_PADJ_TOP_BKA4D6_REG_SCALE_FACTOR_VE_MSB Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01E0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1E0)
    #define REG_01E0_PADJ_TOP_BKA4D6_REG_H_SIZE Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01E0_PADJ_TOP_BKA4D6_REG_H_SIZE_USR_MD Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1E4)
    #define REG_01E4_PADJ_TOP_BKA4D6_REG_V_SIZE Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01E4_PADJ_TOP_BKA4D6_REG_V_SIZE_USR_MD Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01E4_PADJ_TOP_BKA4D6_REG_DEBUG_CLR Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01E8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1E8)
    #define REG_01E8_PADJ_TOP_BKA4D6_REG_SCL_H_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01EC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1EC)
    #define REG_01EC_PADJ_TOP_BKA4D6_REG_SCL_V_SIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01F0_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1F0)
    #define REG_01F0_PADJ_TOP_BKA4D6_REG_H_SIZE_RPT Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01F0_PADJ_TOP_BKA4D6_REG_MODE_Y_HO Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01F4_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1F4)
    #define REG_01F4_PADJ_TOP_BKA4D6_REG_V_SIZE_RPT Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01F4_PADJ_TOP_BKA4D6_REG_MODE_Y_VE Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01F4_PADJ_TOP_BKA4D6_REG_3D_TOP_BOT_EN Fld(1,14,AC_MSKB1)//[14:14]

//Page PADJ_TOP_BKA4D6_2
#define REG_01F8_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1F8)
    #define REG_01F8_PADJ_TOP_BKA4D6_REG_SCL_H_SIZE_RPT Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01F8_PADJ_TOP_BKA4D6_REG_3D_SBS_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01FC_PADJ_TOP_BKA4D6 (PADJ_TOP_BKA4D6 + 0x1FC)
    #define REG_01FC_PADJ_TOP_BKA4D6_REG_SCL_V_SIZE_RPT Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_01FC_PADJ_TOP_BKA4D6_REG_HVSP_BYPASS Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01FC_PADJ_TOP_BKA4D6_REG_HVSP_BUFFER_MD Fld(1,14,AC_MSKB1)//[14:14]

