#define SCAID_BIND_BKA3AE 0x01475C00

//Page SCAID_BIND_BKA3AE
#define REG_0004_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x004)
    #define REG_0004_SCAID_BIND_BKA3AE_REG_SEC_EN_TEE_0004 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0008_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x008)
    #define REG_0008_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DMA_USR_EN_TEE_0008 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0008_SCAID_BIND_BKA3AE_REG_SEC_AID_VS_PROTECT_FORCE_OFF_TEE_0008 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0008_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_CAP_PROTECT_OFF_TEE_0008 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_0020_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x020)
    #define REG_0020_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SCIP_WRITE_THR_TEE_0020 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x024)
    #define REG_0024_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SCNR_WRITE_THR_TEE_0024 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0028_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x028)
    #define REG_0028_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SCMW_WRITE_THR_TEE_0028 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0030_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x030)
    #define REG_0030_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SCTCON_WRITE_THR_TEE_0030 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0040_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x040)
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_1_0 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_3_2 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_5_4 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_7_6 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_9_8 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_11_10 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_13_12 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0040_SCAID_BIND_BKA3AE_REG_AID_SEL_SRC_TEE_0040_15_14 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0044_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x044)
    #define REG_0044_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SRC_REE_0044 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0048_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x048)
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DV5PR_R_REE_0048 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DV5PR_W_REE_0048 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DVDMA0_W_REE_0048 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DVDMA1_W_REE_0048 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DVDMA_R_REE_0048 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_EMPM_REE_0048 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_EMPS_REE_0048 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0048_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_IPDMA0_W_REE_0048 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_004C_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x04C)
    #define REG_004C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_IPDMA1_W_REE_004C Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_004C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_IPDMA_R_REE_004C Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_004C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UFOD_REE_004C Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_004C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UFODL_REE_004C Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_004C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UFODL_HDR_REE_004C Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_004C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_VE_REE_004C Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0050_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x050)
    #define REG_0050_SCAID_BIND_BKA3AE_REG_AID_SEL_SCIP_DMA_READBACK_0_0050 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x054)
    #define REG_0054_SCAID_BIND_BKA3AE_REG_AID_SEL_SCIP_DMA_READBACK_1_0054 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0058_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x058)
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DV5PR_R_USR_TEE_0058 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DV5PR_W_USR_TEE_0058 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DVDMA0_W_USR_TEE_0058 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DVDMA1_W_USR_TEE_0058 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DVDMA_R_USR_TEE_0058 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_EMPM_USR_TEE_0058 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_EMPS_USR_TEE_0058 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0058_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_IPDMA0_W_USR_TEE_0058 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_005C_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x05C)
    #define REG_005C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_IPDMA1_W_USR_TEE_005C Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_005C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_IPDMA_R_USR_TEE_005C Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_005C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UFOD_USR_TEE_005C Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_005C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UFODL_USR_TEE_005C Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_005C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UFODL_HDR_USR_TEE_005C Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_005C_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_VE_USR_TEE_005C Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0078_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x078)
    #define REG_0078_SCAID_BIND_BKA3AE_REG_SECURE_CAP_FORCE_OFF_IPDMA0_TEE_0078 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0078_SCAID_BIND_BKA3AE_REG_SECURE_CAP_FORCE_OFF_IPDMA1_TEE_0078 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0078_SCAID_BIND_BKA3AE_REG_SECURE_CAP_FORCE_OFF_IP2_TEE_0078 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_007C_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x07C)
    #define REG_007C_SCAID_BIND_BKA3AE_REG_SEC_AID_IPDMA_R_MD_REE_007C Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_007C_SCAID_BIND_BKA3AE_REG_SEC_AID_DVDMA_R_MD_REE_007C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0088_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x088)
    #define REG_0088_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SCM_REE_0088 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0088_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UCM_REE_0088 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0090_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x090)
    #define REG_0090_SCAID_BIND_BKA3AE_REG_AID_SEL_SCNR_DMA_READBACK_0090 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0098_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x098)
    #define REG_0098_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_SCM_USR_TEE_0098 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0098_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_UCM_USR_TEE_0098 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_00C0_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0C0)
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_01_00 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_03_02 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_05_04 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_07_06 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_09_08 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_11_10 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_13_12 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_00C0_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_0_00C0_15_14 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_00C4_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0C4)
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_17_16 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_19_18 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_21_20 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_23_22 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_25_24 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_27_26 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_29_28 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_00C4_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MW_REE_1_00C4_31_30 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_00C8_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0C8)
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MDW_REE_00C8 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MGW_REE_00C8 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_VGS0_REE_00C8 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_VGS1_REE_00C8 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIP0_REE_00C8 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIP1_REE_00C8 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIP2_REE_00C8 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_00C8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIPR_REE_00C8 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_00CC_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0CC)
    #define REG_00CC_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DDI_REE_00CC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00D0_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0D0)
    #define REG_00D0_SCAID_BIND_BKA3AE_REG_AID_SEL_SCMW_DMA_READBACK_0_00D0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0D4)
    #define REG_00D4_SCAID_BIND_BKA3AE_REG_AID_SEL_SCMW_DMA_READBACK_1_00D4 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00D8_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0D8)
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MDW_USR_TEE_00D8 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_MGW_USR_TEE_00D8 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_VGS0_USR_TEE_00D8 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_VGS1_USR_TEE_00D8 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIP0_USR_TEE_00D8 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIP1_USR_TEE_00D8 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIP2_USR_TEE_00D8 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_00D8_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DIPR_USR_TEE_00D8 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_00DC_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0DC)
    #define REG_00DC_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_DDI_USR_TEE_00DC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00FC_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x0FC)
    #define REG_00FC_SCAID_BIND_BKA3AE_REG_SEC_AID_MGW_MD_REE_00FC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00FC_SCAID_BIND_BKA3AE_REG_SEC_AID_VGS_MD_REE_00FC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0140_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x140)
    #define REG_0140_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP0_REE_0140 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0140_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP1_REE_0140 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0140_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP2_REE_0140 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0140_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP3_REE_0140 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0140_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOPC_REE_0140 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0150_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x150)
    #define REG_0150_SCAID_BIND_BKA3AE_REG_AID_SEL_SCTCON_DMA_READBACK_0150 Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0158_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x158)
    #define REG_0158_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP0_USR_TEE_0158 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0158_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP1_USR_TEE_0158 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0158_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP2_USR_TEE_0158 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0158_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOP3_USR_TEE_0158 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0158_SCAID_BIND_BKA3AE_REG_SEC_AID_SEL_GOPC_USR_TEE_0158 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_017C_SCAID_BIND_BKA3AE (SCAID_BIND_BKA3AE + 0x17C)
    #define REG_017C_SCAID_BIND_BKA3AE_REG_SEC_AID_GOP_MD_REE_017C Fld(1,0,AC_MSKB0)//[0:0]

