#ifndef _DEMURA_BKA377_H
#define _DEMURA_BKA377_H

#define DEMURA_BKA377 0x0146EE00

//---------------- AC_FULL/MSK ----------------
//  B3[31:24] | B2[23:16] | B1[15:8] | B0[7:0]
//  W32[31:16] | W21[23:8] | W10 [15:0]
//  DW[31:0]
//---------------------------------------------

#define AC_FULLB0           1
#define AC_FULLB1           2
#define AC_FULLB2           3
#define AC_FULLB3           4
#define AC_FULLW10          5
#define AC_FULLW21          6
#define AC_FULLW32          7
#define AC_FULLDW           8
#define AC_MSKB0            9
#define AC_MSKB1            10
#define AC_MSKB2            11
#define AC_MSKB3            12
#define AC_MSKW10           13
#define AC_MSKW21           14
#define AC_MSKW32           15
#define AC_MSKDW            16

//-------------------- Fld --------------------
//    wid[31:16] | shift[15:8] | ac[7:0]
//---------------------------------------------

#define Fld(wid, shft, ac)    (((MS_U32)wid<<16)|(shft<<8)|ac)
#define Fld_wid(fld)        (MS_U8)((fld)>>16)
#define Fld_shift(fld)       (MS_U8)((fld)>>8)
#define Fld_ac(fld)         (MS_U8)((fld))

//Page DEMURA_BKA377
#define REG_0040_DEMURA_BKA377 (DEMURA_BKA377 + 0x040)
    #define REG_0040_DEMURA_BKA377_REG_DMC_BLACK_LIMIT Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0044_DEMURA_BKA377 (DEMURA_BKA377 + 0x044)
    #define REG_0044_DEMURA_BKA377_REG_DMC_PLANE_LEVEL1 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0048_DEMURA_BKA377 (DEMURA_BKA377 + 0x048)
    #define REG_0048_DEMURA_BKA377_REG_DMC_PLANE_LEVEL2 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_004C_DEMURA_BKA377 (DEMURA_BKA377 + 0x04C)
    #define REG_004C_DEMURA_BKA377_REG_DMC_PLANE_LEVEL3 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0050_DEMURA_BKA377 (DEMURA_BKA377 + 0x050)
    #define REG_0050_DEMURA_BKA377_REG_DMC_PLANE_LEVEL4 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0054_DEMURA_BKA377 (DEMURA_BKA377 + 0x054)
    #define REG_0054_DEMURA_BKA377_REG_DMC_PLANE_LEVEL5 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0058_DEMURA_BKA377 (DEMURA_BKA377 + 0x058)
    #define REG_0058_DEMURA_BKA377_REG_DMC_PLANE_LEVEL6 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_005C_DEMURA_BKA377 (DEMURA_BKA377 + 0x05C)
    #define REG_005C_DEMURA_BKA377_REG_DMC_PLANE_LEVEL7 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0060_DEMURA_BKA377 (DEMURA_BKA377 + 0x060)
    #define REG_0060_DEMURA_BKA377_REG_DMC_PLANE_LEVEL8 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0064_DEMURA_BKA377 (DEMURA_BKA377 + 0x064)
    #define REG_0064_DEMURA_BKA377_REG_DMC_WHITE_LIMIT Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0068_DEMURA_BKA377 (DEMURA_BKA377 + 0x068)
    #define REG_0068_DEMURA_BKA377_REG_DMC_DATA_R_MAG4 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0068_DEMURA_BKA377_REG_DMC_DATA_R_MAG3 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0068_DEMURA_BKA377_REG_DMC_DATA_R_MAG2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0068_DEMURA_BKA377_REG_DMC_DATA_R_MAG1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_006C_DEMURA_BKA377 (DEMURA_BKA377 + 0x06C)
    #define REG_006C_DEMURA_BKA377_REG_DMC_DATA_R_MAG8 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_006C_DEMURA_BKA377_REG_DMC_DATA_R_MAG7 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_006C_DEMURA_BKA377_REG_DMC_DATA_R_MAG6 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_006C_DEMURA_BKA377_REG_DMC_DATA_R_MAG5 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0070_DEMURA_BKA377 (DEMURA_BKA377 + 0x070)
    #define REG_0070_DEMURA_BKA377_REG_DMC_DATA_G_MAG4 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0070_DEMURA_BKA377_REG_DMC_DATA_G_MAG3 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0070_DEMURA_BKA377_REG_DMC_DATA_G_MAG2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0070_DEMURA_BKA377_REG_DMC_DATA_G_MAG1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0074_DEMURA_BKA377 (DEMURA_BKA377 + 0x074)
    #define REG_0074_DEMURA_BKA377_REG_DMC_DATA_G_MAG8 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0074_DEMURA_BKA377_REG_DMC_DATA_G_MAG7 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0074_DEMURA_BKA377_REG_DMC_DATA_G_MAG6 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0074_DEMURA_BKA377_REG_DMC_DATA_G_MAG5 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0078_DEMURA_BKA377 (DEMURA_BKA377 + 0x078)
    #define REG_0078_DEMURA_BKA377_REG_DMC_DATA_B_MAG4 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0078_DEMURA_BKA377_REG_DMC_DATA_B_MAG3 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0078_DEMURA_BKA377_REG_DMC_DATA_B_MAG2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0078_DEMURA_BKA377_REG_DMC_DATA_B_MAG1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_007C_DEMURA_BKA377 (DEMURA_BKA377 + 0x07C)
    #define REG_007C_DEMURA_BKA377_REG_DMC_DATA_B_MAG8 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_007C_DEMURA_BKA377_REG_DMC_DATA_B_MAG7 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_007C_DEMURA_BKA377_REG_DMC_DATA_B_MAG6 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_007C_DEMURA_BKA377_REG_DMC_DATA_B_MAG5 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0080_DEMURA_BKA377 (DEMURA_BKA377 + 0x080)
    #define REG_0080_DEMURA_BKA377_REG_DMC_PLANE_B1_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0084_DEMURA_BKA377 (DEMURA_BKA377 + 0x084)
    #define REG_0084_DEMURA_BKA377_REG_DMC_PLANE_12_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0088_DEMURA_BKA377 (DEMURA_BKA377 + 0x088)
    #define REG_0088_DEMURA_BKA377_REG_DMC_PLANE_23_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_008C_DEMURA_BKA377 (DEMURA_BKA377 + 0x08C)
    #define REG_008C_DEMURA_BKA377_REG_DMC_PLANE_34_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0090_DEMURA_BKA377 (DEMURA_BKA377 + 0x090)
    #define REG_0090_DEMURA_BKA377_REG_DMC_PLANE_45_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0094_DEMURA_BKA377 (DEMURA_BKA377 + 0x094)
    #define REG_0094_DEMURA_BKA377_REG_DMC_PLANE_56_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0098_DEMURA_BKA377 (DEMURA_BKA377 + 0x098)
    #define REG_0098_DEMURA_BKA377_REG_DMC_PLANE_67_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_009C_DEMURA_BKA377 (DEMURA_BKA377 + 0x09C)
    #define REG_009C_DEMURA_BKA377_REG_DMC_PLANE_78_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A0_DEMURA_BKA377 (DEMURA_BKA377 + 0x0A0)
    #define REG_00A0_DEMURA_BKA377_REG_DMC_PLANE_9W_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A4_DEMURA_BKA377 (DEMURA_BKA377 + 0x0A4)
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_9W_KS22 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_89_KS22 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_78_KS22 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_67_KS22 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_56_KS22 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_45_KS22 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_34_KS22 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_23_KS22 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_12_KS22 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00A4_DEMURA_BKA377_REG_DMC_PLANE_B1_KS22 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_00A8_DEMURA_BKA377 (DEMURA_BKA377 + 0x0A8)
    #define REG_00A8_DEMURA_BKA377_REG_DMC_H_BLOCK Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_00A8_DEMURA_BKA377_REG_DMC_V_BLOCK Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_00A8_DEMURA_BKA377_REG_DMC_RGB_MODE Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_00A8_DEMURA_BKA377_REG_DMC_BLOCK_SIZE Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00A8_DEMURA_BKA377_REG_DMC_PLANE_NUM Fld(4,0,AC_MSKB0)//[3:0]
#define REG_00AC_DEMURA_BKA377 (DEMURA_BKA377 + 0x0AC)
    #define REG_00AC_DEMURA_BKA377_REG_DMC_H_LUT_NUM Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B0_DEMURA_BKA377 (DEMURA_BKA377 + 0x0B0)
    #define REG_00B0_DEMURA_BKA377_REG_DMC_V_LUT_NUM Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00B4_DEMURA_BKA377 (DEMURA_BKA377 + 0x0B4)
    #define REG_00B4_DEMURA_BKA377_REG_DMC_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B8_DEMURA_BKA377 (DEMURA_BKA377 + 0x0B8)
    #define REG_00B8_DEMURA_BKA377_REG_DMC_DUMMY2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_DEMURA_BKA377 (DEMURA_BKA377 + 0x0BC)
    #define REG_00BC_DEMURA_BKA377_REG_DMC_DITHER_RST_E_4_FRAME Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_DITHER_PSE_RST_NUM Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_POS_AF_GAMMA Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_BYPASS Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_DITHER_EN Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_DB_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_R_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_G_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00BC_DEMURA_BKA377_REG_DMC_B_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_00C0_DEMURA_BKA377 (DEMURA_BKA377 + 0x0C0)
    #define REG_00C0_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_DEMURA_BKA377 (DEMURA_BKA377 + 0x0C4)
    #define REG_00C4_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_DEMURA_BKA377 (DEMURA_BKA377 + 0x0C8)
    #define REG_00C8_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_DEMURA_BKA377 (DEMURA_BKA377 + 0x0CC)
    #define REG_00CC_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_DEMURA_BKA377 (DEMURA_BKA377 + 0x0D0)
    #define REG_00D0_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET5 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_DEMURA_BKA377 (DEMURA_BKA377 + 0x0D4)
    #define REG_00D4_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET6 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_DEMURA_BKA377 (DEMURA_BKA377 + 0x0D8)
    #define REG_00D8_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET7 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_DEMURA_BKA377 (DEMURA_BKA377 + 0x0DC)
    #define REG_00DC_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_DEMURA_BKA377 (DEMURA_BKA377 + 0x0E0)
    #define REG_00E0_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_DEMURA_BKA377 (DEMURA_BKA377 + 0x0E4)
    #define REG_00E4_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_DEMURA_BKA377 (DEMURA_BKA377 + 0x0E8)
    #define REG_00E8_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_DEMURA_BKA377 (DEMURA_BKA377 + 0x0EC)
    #define REG_00EC_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_DEMURA_BKA377 (DEMURA_BKA377 + 0x0F0)
    #define REG_00F0_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET5 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_DEMURA_BKA377 (DEMURA_BKA377 + 0x0F4)
    #define REG_00F4_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET6 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_DEMURA_BKA377 (DEMURA_BKA377 + 0x0F8)
    #define REG_00F8_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET7 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00FC_DEMURA_BKA377 (DEMURA_BKA377 + 0x0FC)
    #define REG_00FC_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_DEMURA_BKA377 (DEMURA_BKA377 + 0x100)
    #define REG_0100_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0104_DEMURA_BKA377 (DEMURA_BKA377 + 0x104)
    #define REG_0104_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0108_DEMURA_BKA377 (DEMURA_BKA377 + 0x108)
    #define REG_0108_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET3 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_010C_DEMURA_BKA377 (DEMURA_BKA377 + 0x10C)
    #define REG_010C_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0110_DEMURA_BKA377 (DEMURA_BKA377 + 0x110)
    #define REG_0110_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET5 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0114_DEMURA_BKA377 (DEMURA_BKA377 + 0x114)
    #define REG_0114_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET6 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0118_DEMURA_BKA377 (DEMURA_BKA377 + 0x118)
    #define REG_0118_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET7 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_011C_DEMURA_BKA377 (DEMURA_BKA377 + 0x11C)
    #define REG_011C_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0120_DEMURA_BKA377 (DEMURA_BKA377 + 0x120)
    #define REG_0120_DEMURA_BKA377_REG_DMC_PANEL_H_SIZE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0124_DEMURA_BKA377 (DEMURA_BKA377 + 0x124)
    #define REG_0124_DEMURA_BKA377_REG_DMC_PRELOAD_LINE Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0128_DEMURA_BKA377 (DEMURA_BKA377 + 0x128)
    #define REG_0128_DEMURA_BKA377_REG_DMC_R_H_R Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_0128_DEMURA_BKA377_REG_DMC_Q_H_R Fld(8,0,AC_FULLB0)//[7:0]
#define REG_012C_DEMURA_BKA377 (DEMURA_BKA377 + 0x12C)
    #define REG_012C_DEMURA_BKA377_REG_DMC_GRID_LINE_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_012C_DEMURA_BKA377_REG_DMC_GRID_LINE_SIZE Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_012C_DEMURA_BKA377_REG_DMC_GRID_LINE_COLOR Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0130_DEMURA_BKA377 (DEMURA_BKA377 + 0x130)
    #define REG_0130_DEMURA_BKA377_REG_DMC_FLOW_CTRL_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0130_DEMURA_BKA377_REG_DMC_FLOW_LEN Fld(11,0,AC_MSKW10)//[10:0]
#define REG_013C_DEMURA_BKA377 (DEMURA_BKA377 + 0x13C)
    #define REG_013C_DEMURA_BKA377_REG_ADL_CHECKSUM_XP Fld(3,13,AC_MSKB1)//[15:13]
    #define REG_013C_DEMURA_BKA377_REG_ADL_CHECKSUM_LR Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_013C_DEMURA_BKA377_REG_ADL_CHECKSUM_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_013C_DEMURA_BKA377_REG_DMC_GUARD_BAND_SIZE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0180_DEMURA_BKA377 (DEMURA_BKA377 + 0x180)
    #define REG_0180_DEMURA_BKA377_REG_DMC_PLANE_LEVEL9 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0184_DEMURA_BKA377 (DEMURA_BKA377 + 0x184)
    #define REG_0184_DEMURA_BKA377_REG_DMC_DATA_R_MAG9 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0184_DEMURA_BKA377_REG_DMC_DATA_G_MAG9 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0184_DEMURA_BKA377_REG_DMC_DATA_B_MAG9 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0188_DEMURA_BKA377 (DEMURA_BKA377 + 0x188)
    #define REG_0188_DEMURA_BKA377_REG_DMC_PLANE_89_COEF Fld(14,0,AC_MSKW10)//[13:0]
#define REG_018C_DEMURA_BKA377 (DEMURA_BKA377 + 0x18C)
    #define REG_018C_DEMURA_BKA377_REG_DMC_DATA_R_OFFSET9 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_DEMURA_BKA377 (DEMURA_BKA377 + 0x190)
    #define REG_0190_DEMURA_BKA377_REG_DMC_DATA_G_OFFSET9 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_DEMURA_BKA377 (DEMURA_BKA377 + 0x194)
    #define REG_0194_DEMURA_BKA377_REG_DMC_DATA_B_OFFSET9 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0198_DEMURA_BKA377 (DEMURA_BKA377 + 0x198)
    #define REG_0198_DEMURA_BKA377_REG_DMC_DELTA_LOW_LIMIT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_DEMURA_BKA377 (DEMURA_BKA377 + 0x19C)
    #define REG_019C_DEMURA_BKA377_REG_DMC_DELTA_HIGH_LIMIT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_DEMURA_BKA377 (DEMURA_BKA377 + 0x1A0)
    #define REG_01A0_DEMURA_BKA377_REG_DMC_POS_V_OFFSET Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_01A0_DEMURA_BKA377_REG_DMC_POS_H_OFFSET Fld(4,0,AC_MSKB0)//[3:0]
#define REG_01A4_DEMURA_BKA377 (DEMURA_BKA377 + 0x1A4)
    #define REG_01A4_DEMURA_BKA377_REG_DMC_L1_EQ_0_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01A4_DEMURA_BKA377_REG_DMC_FLOW_REST Fld(11,0,AC_MSKW10)//[10:0]
#define REG_01B4_DEMURA_BKA377 (DEMURA_BKA377 + 0x1B4)
    #define REG_01B4_DEMURA_BKA377_REG_DMC_BIST_FAIL_0 Fld(7,0,AC_MSKB0)//[6:0]
#define REG_01B8_DEMURA_BKA377 (DEMURA_BKA377 + 0x1B8)
    #define REG_01B8_DEMURA_BKA377_REG_DMC_BIST_FAIL_1 Fld(7,0,AC_MSKB0)//[6:0]
#define REG_01BC_DEMURA_BKA377 (DEMURA_BKA377 + 0x1BC)
    #define REG_01BC_DEMURA_BKA377_REG_DMC_BIST_FAIL_2 Fld(7,0,AC_MSKB0)//[6:0]

#endif /*#ifndef _DEMURA_BKA377_H*/
