#ifndef _LDC_BKA3EF_H
#define _LDC_BKA3EF_H
#include "hwreg_common.h"

#define LDC_BKA3EF 0x0147DE00

//Page LDC_BKA3EF
#define REG_0004_LDC_BKA3EF (LDC_BKA3EF + 0x004)
    #define REG_0004_LDC_BKA3EF_REG_LDC_BYPASS Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_LDC_BKA3EF_REG_LDC_PATH_SEL Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0008_LDC_BKA3EF (LDC_BKA3EF + 0x008)
    #define REG_0008_LDC_BKA3EF_REG_LDC_CLK_SW_MD_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0008_LDC_BKA3EF_REG_LDC_CLK_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0008_LDC_BKA3EF_REG_LDC_CLK_DB_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0020_LDC_BKA3EF (LDC_BKA3EF + 0x020)
    #define REG_0020_LDC_BKA3EF_REG_LDC_XIU2AHB_SEL0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0020_LDC_BKA3EF_REG_LDC_XIU2AHB_SEL1 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0040_LDC_BKA3EF (LDC_BKA3EF + 0x040)
    #define REG_0040_LDC_BKA3EF_REG_LDC_RST_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0040_LDC_BKA3EF_REG_LDC_MRST_SW_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0040_LDC_BKA3EF_REG_LDC_AHB_SW_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0040_LDC_BKA3EF_REG_LDC_AHB_WP_SW_RST Fld(1,3,AC_MSKB0)//[3:3]
#define REG_0080_LDC_BKA3EF (LDC_BKA3EF + 0x080)
    #define REG_0080_LDC_BKA3EF_REG_LDC_HFDE_GEN_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0080_LDC_BKA3EF_REG_LDC_HFDE_GEN_SW_MODE Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0084_LDC_BKA3EF (LDC_BKA3EF + 0x084)
    #define REG_0084_LDC_BKA3EF_REG_LDC_HFDE_GEN_START Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_LDC_BKA3EF (LDC_BKA3EF + 0x088)
    #define REG_0088_LDC_BKA3EF_REG_LDC_HFDE_GEN_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0180_LDC_BKA3EF (LDC_BKA3EF + 0x180)
    #define REG_0180_LDC_BKA3EF_REG_AHB_CRC_EN_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0180_LDC_BKA3EF_REG_AHB_CRC_AUTO_MODE_0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0180_LDC_BKA3EF_REG_AHB_CRC_CLR_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0180_LDC_BKA3EF_REG_AHB_CRC_DONE_0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_LDC_BKA3EF (LDC_BKA3EF + 0x184)
    #define REG_0184_LDC_BKA3EF_REG_AHB_CRC_ST_TRIG_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0184_LDC_BKA3EF_REG_AHB_CRC_END_TRIG_0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0188_LDC_BKA3EF (LDC_BKA3EF + 0x188)
    #define REG_0188_LDC_BKA3EF_REG_AHB_CRC_OUT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_LDC_BKA3EF (LDC_BKA3EF + 0x190)
    #define REG_0190_LDC_BKA3EF_REG_AHB_CRC_ST_ADDR_0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_LDC_BKA3EF (LDC_BKA3EF + 0x194)
    #define REG_0194_LDC_BKA3EF_REG_AHB_CRC_ST_ADDR_0_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0198_LDC_BKA3EF (LDC_BKA3EF + 0x198)
    #define REG_0198_LDC_BKA3EF_REG_AHB_CRC_END_ADDR_0_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_LDC_BKA3EF (LDC_BKA3EF + 0x19C)
    #define REG_019C_LDC_BKA3EF_REG_AHB_CRC_END_ADDR_0_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_LDC_BKA3EF (LDC_BKA3EF + 0x1A0)
    #define REG_01A0_LDC_BKA3EF_REG_AHB_CRC_EN_1 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01A0_LDC_BKA3EF_REG_AHB_CRC_AUTO_MODE_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01A0_LDC_BKA3EF_REG_AHB_CRC_CLR_1 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01A0_LDC_BKA3EF_REG_AHB_CRC_DONE_1 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01A4_LDC_BKA3EF (LDC_BKA3EF + 0x1A4)
    #define REG_01A4_LDC_BKA3EF_REG_AHB_CRC_ST_TRIG_1 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01A4_LDC_BKA3EF_REG_AHB_CRC_END_TRIG_1 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01A8_LDC_BKA3EF (LDC_BKA3EF + 0x1A8)
    #define REG_01A8_LDC_BKA3EF_REG_AHB_CRC_OUT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B0_LDC_BKA3EF (LDC_BKA3EF + 0x1B0)
    #define REG_01B0_LDC_BKA3EF_REG_AHB_CRC_ST_ADDR_1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B4_LDC_BKA3EF (LDC_BKA3EF + 0x1B4)
    #define REG_01B4_LDC_BKA3EF_REG_AHB_CRC_ST_ADDR_1_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B8_LDC_BKA3EF (LDC_BKA3EF + 0x1B8)
    #define REG_01B8_LDC_BKA3EF_REG_AHB_CRC_END_ADDR_1_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01BC_LDC_BKA3EF (LDC_BKA3EF + 0x1BC)
    #define REG_01BC_LDC_BKA3EF_REG_AHB_CRC_END_ADDR_1_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C0_LDC_BKA3EF (LDC_BKA3EF + 0x1C0)
    #define REG_01C0_LDC_BKA3EF_REG_AHB_DEBUG_CLR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01C0_LDC_BKA3EF_REG_AHB_DEBUG_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01C0_LDC_BKA3EF_REG_AHB_DEBUG_CNT_LIVE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01C0_LDC_BKA3EF_REG_AHB_DEBUG_SEL0 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_01C4_LDC_BKA3EF (LDC_BKA3EF + 0x1C4)
    #define REG_01C4_LDC_BKA3EF_REG_AHB_DEBUG_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E0_LDC_BKA3EF (LDC_BKA3EF + 0x1E0)
    #define REG_01E0_LDC_BKA3EF_REG_REPORT_AHB_ADDR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E4_LDC_BKA3EF (LDC_BKA3EF + 0x1E4)
    #define REG_01E4_LDC_BKA3EF_REG_REPORT_AHB_ADDR_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E8_LDC_BKA3EF (LDC_BKA3EF + 0x1E8)
    #define REG_01E8_LDC_BKA3EF_REG_REPORT_AHB_WDATA_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01EC_LDC_BKA3EF (LDC_BKA3EF + 0x1EC)
    #define REG_01EC_LDC_BKA3EF_REG_REPORT_AHB_WDATA_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F0_LDC_BKA3EF (LDC_BKA3EF + 0x1F0)
    #define REG_01F0_LDC_BKA3EF_REG_REPORT_AHB_CNT0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_LDC_BKA3EF (LDC_BKA3EF + 0x1F4)
    #define REG_01F4_LDC_BKA3EF_REG_REPORT_AHB_CNT1 Fld(16,0,AC_FULLW10)//[15:0]

#endif
