#ifndef _XCPLL_REG_V005_H_
#define _XCPLL_REG_V005_H_

/* ----------------- Internal Register Definitions ------------------- */
#define XCPLL_BASE 0x201A00
#define REG_0000_XCPLL					(XCPLL_BASE + 0x00000000)
	#define REG_0000_XCPLL_REG_XCPLL_TEST_0000	Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0004_XCPLL					(XCPLL_BASE + 0x00000004)
	#define REG_0004_XCPLL_REG_XCPLL_PD_0004	Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0004_XCPLL_REG_XCPLL_PD_CLK_DIV1_0004	Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0004_XCPLL_REG_XCPLL_PD_CLK_DIV2_0004	Fld(1,8,AC_MSKB1)//[8:8]
#define REG_0008_XCPLL					(XCPLL_BASE + 0x00000008)
	#define REG_0008_XCPLL_REG_XCPLL_RST_0008	Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0008_XCPLL_REG_XCPLL_INPUT_DIV_FIRST_0008	Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_0008_XCPLL_REG_XCPLL_LOOP_DIV_FIRST_0008	Fld(2,8,AC_MSKB1)//[9:8]
#define REG_000C_XCPLL					(XCPLL_BASE + 0x0000000c)
	#define REG_000C_XCPLL_REG_XCPLL_LOOP_DIV_SECOND_000C	Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_000C_XCPLL_REG_XCPLL_OUTPUT_DIV_000C	Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_000C_XCPLL_REG_XCPLL_OUTPUT_DIV_FIRST_000C	Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0010_XCPLL					(XCPLL_BASE + 0x00000010)
	#define REG_0010_XCPLL_REG_XCPLL_TEST_EN_0010	Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0010_XCPLL_REG_XCPLL_VCO_DIV3_EN_0010	Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0010_XCPLL_REG_XCPLL_CP_SW_0010	Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0010_XCPLL_REG_XCPLL_ICP_ICTRL_0010	Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0010_XCPLL_REG_XCPLL_XTAL_0010	Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0010_XCPLL_REG_XCPLL_OV_CP_SW_EN_0010	Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0010_XCPLL_REG_XCPLL_PRDT3_EN_0010	Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0010_XCPLL_REG_XCPLL_PRDT2_EN_0010	Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0010_XCPLL_REG_XCPLL_PRDT_EN_0010	Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0014_XCPLL					(XCPLL_BASE + 0x00000014)
	#define REG_0014_XCPLL_REG_XCPLL_SET_0_0014	Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0018_XCPLL					(XCPLL_BASE + 0x00000018)
	#define REG_0018_XCPLL_REG_XCPLL_SET_1_0018	Fld(8,0,AC_FULLB0)//[7:0]
#define REG_001C_XCPLL					(XCPLL_BASE + 0x0000001c)
	#define REG_001C_XCPLL_REG_XCPLL_STEP_0_001C	Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_XCPLL					(XCPLL_BASE + 0x00000020)
	#define REG_0020_XCPLL_REG_XCPLL_STEP_1_0020	Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0024_XCPLL					(XCPLL_BASE + 0x00000024)
	#define REG_0024_XCPLL_REG_XCPLL_SPAN_0_0024	Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_XCPLL					(XCPLL_BASE + 0x00000028)
	#define REG_0028_XCPLL_REG_XCPLL_SPAN_1_0028	Fld(8,0,AC_FULLB0)//[7:0]
#define REG_002C_XCPLL					(XCPLL_BASE + 0x0000002c)
	#define REG_002C_XCPLL_REG_XCPLL_TESTD_002C	Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0034_XCPLL					(XCPLL_BASE + 0x00000034)
	#define REG_0034_XCPLL_REG_XCPLL_SSC_SYNC_0034	Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0034_XCPLL_REG_XCPLL_SSC_MODE_0034	Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0038_XCPLL					(XCPLL_BASE + 0x00000038)
	#define REG_0038_XCPLL_REG_XCPLL_SPAN_CNT_0_0038	Fld(16,0,AC_FULLW10)//[15:0]
#define REG_003C_XCPLL					(XCPLL_BASE + 0x0000003c)
	#define REG_003C_XCPLL_REG_XCPLL_SPAN_CNT_1_003C	Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0040_XCPLL					(XCPLL_BASE + 0x00000040)
	#define REG_0040_XCPLL_REG_XCPLL_SEGMENT_0040	Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0040_XCPLL_REG_XCPLL_STOP_FLAG_0040	Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0040_XCPLL_REG_XCPLL_REVERSE_FLAG_0040	Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0040_XCPLL_REG_XCPLL_SSC_OFF_0040	Fld(1,4,AC_MSKB0)//[4:4]
#define REG_0044_XCPLL					(XCPLL_BASE + 0x00000044)
	#define REG_0044_XCPLL_REG_XCPLL_SSC_OFFSET_0_0044	Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_XCPLL					(XCPLL_BASE + 0x00000048)
	#define REG_0048_XCPLL_REG_XCPLL_SSC_OFFSET_1_0048	Fld(8,0,AC_FULLB0)//[7:0]
#define REG_004C_XCPLL					(XCPLL_BASE + 0x0000004c)
	#define REG_004C_XCPLL_REG_XCPLL_DIV_004C	Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0050_XCPLL					(XCPLL_BASE + 0x00000050)
	#define REG_0050_XCPLL_REG_XCPLL_SLD_0050	Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0054_XCPLL					(XCPLL_BASE + 0x00000054)
	#define REG_0054_XCPLL_REG_XCPLL_PORST_0054	Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0058_XCPLL					(XCPLL_BASE + 0x00000058)
	#define REG_0058_XCPLL_REG_XCPLL_LOCK_0058	Fld(1,0,AC_MSKB0)//[0:0]
#define REG_005C_XCPLL					(XCPLL_BASE + 0x0000005c)
	#define REG_005C_XCPLL_REG_CKG_SC_SYN_005C	Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0060_XCPLL					(XCPLL_BASE + 0x00000060)
	#define REG_0060_XCPLL_REG_XCPLL_DIE_PWR_GOOD_0060	Fld(1,0,AC_MSKB0)//[0:0]

#endif
