/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_SCIP_H
#define _DT_BINDINGS_CLK_MT5896_SCIP_H

#define CLK_SCIP_XTAL_12M_INT_CK	1
#define CLK_SCIP_XTAL_24M_INT_CK	2
#define CLK_SCIP_XTAL_IP1_INT_CK	5
#define CLK_SCIP_SIDCLK_HD0_INT_CK	6
#define CLK_SCIP_SIDCLK_HD1_INT_CK	7
#define CLK_SCIP_SIDCLK_HD2_INT_CK	8
#define CLK_SCIP_SIDCLK_HD3_INT_CK	9
#define CLK_SCIP_MCU_NONPM_INT_CK	10
#define CLK_SCIP_RIU_NONPM_INT_CK	11
#define CLK_SCIP_SMI_INT_CK	12
#define CLK_SCIP_MCU_XC_INT_CK	13
#define CLK_SCIP_RIU_XC_INT_CK	14
#define CLK_SCIP_XC_DC0_INT_CK	15
#define CLK_SCIP_XC_SUB_DC0_INT_CK	16
#define CLK_SCIP_XC_SUB1_DC0_INT_CK	17
#define CLK_SCIP_XC_ADC_INT_CK	18
#define CLK_SCIP_XC_HDMI0_INT_CK	19
#define CLK_SCIP_XC_HDMI1_INT_CK	20
#define CLK_SCIP_XC_HDMI2_INT_CK	21
#define CLK_SCIP_XC_HDMI3_INT_CK	22
#define CLK_SCIP_XC_VD_INT_CK	23
#define CLK_SCIP_XC_ID0_INT_CK	24
#define CLK_SCIP_XC_ID1_INT_CK	25
#define CLK_SCIP_XC_ED_LIVE_INT_CK	26
#define CLK_SCIP_XC_ED0_INT_CK	27
#define CLK_SCIP_XC_ED1_INT_CK	28
#define CLK_SCIP_XC_FN_INT_CK	29
#define CLK_SCIP_XC_FS_INT_CK	30
#define CLK_SCIP_XC_FD_INT_CK	31
#define CLK_SCIP_XC_OD_INT_CK	32
#define CLK_SCIP_XC_OD_DELTA_INT_CK	33
#define CLK_SCIP_FRC_FCLK_2XPLUS_INT_CK	34
#define CLK_SCIP_XC_DISP_MFDEC_INT_CK	35
#define CLK_SCIP_XC_DBG2MIU_INT_CK	36
#define CLK_SCIP_XC_HD2MIU_M_INT_CK	37
#define CLK_SCIP_XC_HD2MIU_S_INT_CK	38
#define CLK_SCIP_XC_VEIN_INT_CK	39
#define CLK_SCIP_XC_SLOW_INT_CK	40
#define CLK_SCIP_XC_VE_INT_CK	41
#define CLK_SCIP_XC_VEDAC_INT_CK	42
#define CLK_SCIP_XC_IP2_SRC_INT_CK	43
#define CLK_SCIP_XC_TGEN_WIN_INT_CK	44
#define CLK_SCIP_XC_UCD_STAT_INT_CK	45
#define CLK_SCIP_DC0_SRAM_INT_CK	46
#define CLK_SCIP_UCD_ST_SRAM_INT_CK	47
#define CLK_SCIP_XC_DIP0_INT_CK	48
#define CLK_SCIP_XC_DIP1_INT_CK	49
#define CLK_SCIP_XC_DIP2_INT_CK	50
#define CLK_SCIP_XC_SC2FPLL_INT_CK	51
#define CLK_SCIP_NR	52

#endif
