/*
 * Realtek Semiconductor Corp.
 *
 * bsp/bspinit.h:
 *
 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
 */
#ifndef __BSPINIT_H_
#define __BSPINIT_H_

#include <asm/asm.h>
#include <bspcpu.h>

.macro  kernel_entry_setup
/*
 * If UCRdNPWr is set to 1, uncacheable read will be not be sent to system bus
 * until previous writes are all responded. When UCRdNPWr is set to 0,
 * an uncacheable read can be sent to system bus without waiting the response
 * of the previous write.
 * This bit is presented in AXI BIU only, the default setting is 0
 */
mfc0    t0, LXCP0_CCTL, 2
or      t0, CCTL_UCRDNPWR
mtc0    t0, LXCP0_CCTL, 2
.endm

.macro  smp_slave_setup
.endm

#endif
