/*
 * This header provides constants for the reset controller
 * present in the RTS39xx SoC
 */

#ifndef _RTS_RESETS_H
#define _RTS_RESETS_H

#define FORCE_RESET_VIDEO		0
#define FORCE_RESET_H264		1
#define FORCE_RESET_JPG			2
#define FORCE_RESET_MIPI		3
#define FORCE_RESET_MCU			4
#define FORCE_RESET_ISP			7
#define FORCE_RESET_CIPHER		8
#define FORCE_RESET_SDIO0		9
#define FORCE_RESET_SDIO1		10
#define FORCE_RESET_CODEC		11
#define FORCE_RESET_I2S			12
#define FORCE_RESET_SPDIF		13
#define FORCE_RESET_I2C			14
#define FORCE_RESET_U2DEV		15
#define FORCE_RESET_U2HOST		16
#define FORCE_RESET_UART		17
#define FORCE_RESET_ETHERNET		18
#define FORCE_RESET_H265_AXI		19
#define FORCE_RESET_H265_BPU		20
#define FORCE_RESET_H265_CORE		21
#define FORCE_RESET_H265		22
#define FORCE_RESET_GE			23
#define FORCE_RESET_RSA			24
#define FORCE_RESET_SHA256		25
#define FORCE_RESET_TRNG		26
#define FORCE_RESET_DRAM_LCDC		27
#define FORCE_RESET_FEPHY		28
#define FORCE_RESET_EFUSE		29
#define FORCE_RESET_NN			30
#define FORCE_RESET_MIPI_TX		31
#define FORCE_RESET_MAX			32

#endif
