// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Copyright (c) 2022 MediaTek Inc.
 */

#ifndef MTK_DMX_MEDIACTRL_INC
#define MTK_DMX_MEDIACTRL_INC

#include "mtk_dmx_regs.h"

#define CI_SERIAL_MODE_SUPPORT	0

struct mtk_tso_ck_settings {
	u32 rateKHz;
	u16 out_clk_sel;
	u16 div_src;
	u16 div_num;
};
/*
 * suppot output clk
 * 6.75Mhz for < 54Mbps
 * 8Mhz for 54 ~ 64Mbps
 * 9Mhz for 64 ~ 72Mbps
 * 12Mhz for 72 ~ 96Mbps
 * 14.4Mhz for 96 ~ 115Mbps
 * rateKHz = 288/(2*(div_num+1))
 * Formula:
 *  out_clk_sel = 2N,
 *  rateKHz = div_src / (2 * (div_num + 1))
 */

const struct mtk_tso_ck_settings tso_ck_ci14_tbl [] = {
	{6850, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 20},
	{8000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 17},
	{9000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 15},
	{9600, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 14},
	{10285, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 13},
	{11000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 12},
	{12000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 11},
	{13000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 10},
	{14400, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 9},
#if (CI_SERIAL_MODE_SUPPORT)
	{72000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 1},
#endif
};

const struct mtk_tso_ck_settings tso_ck_ci20_tbl [] = {
	{8600, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_172MHZ, 9},
	{12000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 11},
	{14400, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 9},
	{72000, TSO_OUT_CLK_DIV_2N, TSO_OUT_DIV_SEL_SRC_288MHZ, 1},
};
#endif
