/* SPDX-License-Identifier: BSD-2-Clause */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

/* [File] : wf_hif_dmashdl_top.h */
/* [Revision time] : Mon Apr 29 11:37:41 2019 */
/* [Description] : This file is auto generated by CODA */
/* reserved. */

#ifndef __WF_HIF_DMASHDL_TOP_REGS_H__
#define __WF_HIF_DMASHDL_TOP_REGS_H__

#ifdef __cplusplus
extern "C" {
#endif

/* ************************************************************************** */
/* */
/* WF_HIF_DMASHDL_TOP CR Definitions */
/* */
/* ************************************************************************** */

#define WF_HIF_DMASHDL_TOP_BASE 0x7C026000

#define WF_HIF_DMASHDL_TOP_PAGE_SETTING_ADDR                                   \
	(WF_HIF_DMASHDL_TOP_BASE + 0x0C) /* 600C */
#define WF_HIF_DMASHDL_TOP_PAGE_SETTING_GROUP_SEQUENCE_ORDER_TYPE_MASK         \
	0x00010000 /* GROUP_SEQUENCE_ORDER_TYPE[16] */

#define WF_HIF_DMASHDL_TOP_REFILL_CONTROL_ADDR                                 \
	(WF_HIF_DMASHDL_TOP_BASE + 0x10) /* 6010 */
#define WF_HIF_DMASHDL_TOP_REFILL_CONTROL_GROUP0_REFILL_DISABLE_MASK           \
	0x00010000 /* GROUP0_REFILL_DISABLE[16] */

#define WF_HIF_DMASHDL_TOP_PACKET_MAX_SIZE_ADDR                                \
	(WF_HIF_DMASHDL_TOP_BASE + 0x1c) /* 601C */
#define WF_HIF_DMASHDL_TOP_PACKET_MAX_SIZE_PSE_PACKET_MAX_SIZE_MASK            \
	0x0FFF0000 /* PSE_PACKET_MAX_SIZE[27..16] */
#define WF_HIF_DMASHDL_TOP_PACKET_MAX_SIZE_PSE_PACKET_MAX_SIZE_SHFT 16
#define WF_HIF_DMASHDL_TOP_PACKET_MAX_SIZE_PLE_PACKET_MAX_SIZE_MASK            \
	0x00000FFF /* PLE_PACKET_MAX_SIZE[11..0] */
#define WF_HIF_DMASHDL_TOP_PACKET_MAX_SIZE_PLE_PACKET_MAX_SIZE_SHFT 0

#define WF_HIF_DMASHDL_TOP_GROUP0_CONTROL_ADDR                                 \
	(WF_HIF_DMASHDL_TOP_BASE + 0x20) /* 6020 */
#define WF_HIF_DMASHDL_TOP_GROUP0_CONTROL_GROUP0_MAX_QUOTA_MASK                \
	0x0FFF0000 /* GROUP0_MAX_QUOTA[27..16] */
#define WF_HIF_DMASHDL_TOP_GROUP0_CONTROL_GROUP0_MAX_QUOTA_SHFT 16
#define WF_HIF_DMASHDL_TOP_GROUP0_CONTROL_GROUP0_MIN_QUOTA_MASK                \
	0x00000FFF /* GROUP0_MIN_QUOTA[11..0] */
#define WF_HIF_DMASHDL_TOP_GROUP0_CONTROL_GROUP0_MIN_QUOTA_SHFT 0

#define WF_HIF_DMASHDL_TOP_QUEUE_MAPPING0_ADDR                                 \
	(WF_HIF_DMASHDL_TOP_BASE + 0x60) /* 6060 */
#define WF_HIF_DMASHDL_TOP_QUEUE_MAPPING0_QUEUE0_MAPPING_MASK                  \
	0x0000000F /* QUEUE0_MAPPING[3..0] */

#define WF_HIF_DMASHDL_TOP_HIF_SCHEDULER_SETTING0_ADDR                         \
	(WF_HIF_DMASHDL_TOP_BASE + 0x70) /* 6070 */
#define WF_HIF_DMASHDL_TOP_HIF_SCHEDULER_SETTING0_PRIORITY0_GROUP_MASK         \
	0x0000000F /* PRIORITY0_GROUP[3..0] */

#ifdef __cplusplus
}
#endif

#endif /* __WF_HIF_DMASHDL_TOP_REGS_H__ */
