/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TSP4_TEST
#define REG_0000_TSP4 (0x000)
	#define TSP4_REG_OVERFLOW0_0000_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_OVERFLOW0_0000_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_OVERFLOW0_0000_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_OVERFLOW0_0000_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_OVERFLOW0_0000_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_OVERFLOW0_0000_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_OVERFLOW0_0000_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP4_REG_OVERFLOW0_0000_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP4_REG_OVERFLOW0_0000_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_OVERFLOW0_0000_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_OVERFLOW0_0000_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_OVERFLOW0_0000_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_OVERFLOW0_0000_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_OVERFLOW0_0000_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP4_REG_OVERFLOW0_0000_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP4_REG_OVERFLOW0_0000_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0004_TSP4 (0x004)
	#define TSP4_REG_OVERFLOW1_0004_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_OVERFLOW1_0004_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_OVERFLOW1_0004_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_OVERFLOW1_0004_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_OVERFLOW1_0004_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_OVERFLOW1_0004_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_OVERFLOW1_0004_15_6 Fld(10, 6, AC_MSKW10)//[15:6]
#define REG_0008_TSP4 (0x008)
	#define TSP4_REG_AV_FIFO_STATUS_0008 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_000C_TSP4 (0x00C)
	#define TSP4_REG_PVR_FIFO_STATUS_000C_3_0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP4_REG_PVR_FIFO_STATUS_000C_7_4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP4_REG_PVR_FIFO_STATUS_000C_11_8 Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_0010_TSP4 (0x010)
	#define TSP4_REG_VQ_TX_FIFO_STATUS_0010_3_0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP4_REG_VQ_TX_FIFO_STATUS_0010_7_4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP4_REG_VQ_TX_FIFO_STATUS_0010_11_8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP4_REG_VQ_TX_FIFO_STATUS_0010_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0014_TSP4 (0x014)
	#define TSP4_REG_PKT_CNT_V_0014 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0018_TSP4 (0x018)
	#define TSP4_REG_PKT_CNT_V3D_0018 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_001C_TSP4 (0x01C)
	#define TSP4_REG_PKT_CNT_A_001C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0020_TSP4 (0x020)
	#define TSP4_REG_PKT_CNT_AD_0020 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0024_TSP4 (0x024)
	#define TSP4_REG_PKT_CNT_ADC_0024 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0028_TSP4 (0x028)
	#define TSP4_REG_PKT_CNT_ADD_0028 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0034_TSP4 (0x034)
	#define TSP4_REG_LOCKED_PKT_CNT_0034 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0038_TSP4 (0x038)
	#define TSP4_REG_AV_PKT_CNT_0038 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_003C_TSP4 (0x03C)
	#define TSP4_REG_PKT_ERR_STATUS_003C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_PKT_ERR_STATUS_003C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_PKT_ERR_STATUS_003C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_PKT_ERR_STATUS_003C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_PKT_ERR_STATUS_003C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_PKT_ERR_STATUS_003C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_PKT_ERR_STATUS_003C_15 Fld(1, 15, AC_MSKB1)//[15:15]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP4_REG_PKT_ERR_STATUS_003C_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_0040_TSP4 (0x040)
	#define TSP4_REG_PID_MATCHED0_0040 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP4_REG_PID_CHANGE0_0040 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_0044_TSP4 (0x044)
	#define TSP4_REG_PID_MATCHED1_0044 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP4_REG_PID_CHANGE1_0044 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_0048_TSP4 (0x048)
	#define TSP4_REG_PID_MATCHED2_0048 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP4_REG_PID_CHANGE2_0048 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_004C_TSP4 (0x04C)
	#define TSP4_REG_PID_MATCHED3_004C Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP4_REG_PID_CHANGE3_004C Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_0058_TSP4 (0x058)
	#define TSP4_REG_SRAM2P_COLLISION_0058_11_0 Fld(12, 0, AC_MSKW10)//[11:0]
	#define TSP4_REG_SRAM2P_COLLISION_0058_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_SRAM2P_COLLISION_0058_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP4_REG_SRAM2P_COLLISION_0058_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP4_REG_SRAM2P_COLLISION_0058_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_005C_TSP4 (0x05C)
	#define TSP4_REG_AV_PKT_CNT1_005C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0060_TSP4 (0x060)
	#define TSP4_REG_ERR_PKT_CNT_0060 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0064_TSP4 (0x064)
	#define TSP4_REG_AV_PKT_CNT2_0064 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_TSP4 (0x068)
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_EVER_UNLOCK_STATUS_0068_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_006C_TSP4 (0x06C)
	#define TSP4_REG_OVERFLOW2_006C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_OVERFLOW2_006C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_OVERFLOW2_006C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_OVERFLOW2_006C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_OVERFLOW2_006C_15_4 Fld(12, 4, AC_MSKW10)//[15:4]
#define REG_0070_TSP4 (0x070)
	#define TSP4_REG_PVR_FLUSH_INFO_0070_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_PVR_FLUSH_INFO_0070_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_PVR_FLUSH_INFO_0070_15_2 Fld(14, 2, AC_MSKW10)//[15:2]
#define REG_00C0_TSP4 (0x0C0)
	#define TSP4_REG_PKT_MEET_SIZE_PVR_L_00C0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C4_TSP4 (0x0C4)
	#define TSP4_REG_PKT_MEET_SIZE_PVR_H_00C4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP4_REG_STR2MI_CNT_CLEAR_PVR_00C4 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_CNT_INT_MODE_PVR_00C4 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_SYNC_INT_MODE_PVR_00C4 Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_00C8_TSP4 (0x0C8)
	#define TSP4_REG_MEET_SIZE_CNT_R_PVR_00C8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP4_REG_TIME_STAMP_SRC_SEL_00C8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_BYPASS_TIMESTAMP_SEL_00C8 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_BURST_PKT_MODE_00C8 Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_00CC_TSP4 (0x0CC)
	#define TSP4_REG_PAUSE_TIME_0_00CC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00D0_TSP4 (0x0D0)
	#define TSP4_REG_PAUSE_TIME_1_00D0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00D4_TSP4 (0x0D4)
	#define TSP4_REG_FORCE_SYNC_BYTE_VAL_00D4 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0100_TSP4 (0x100)
	#define TSP4_REG_PKT_MEET_SIZE_PVR4_L_0100 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0104_TSP4 (0x104)
	#define TSP4_REG_PKT_MEET_SIZE_PVR4_H_0104 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP4_REG_STR2MI_CNT_CLEAR_PVR4_0104 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_CNT_INT_MODE_PVR4_0104 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_SYNC_INT_MODE_PVR4_0104 Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0108_TSP4 (0x108)
	#define TSP4_REG_MEET_SIZE_CNT_R_PVR4_0108 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP4_REG_TIME_STAMP_SRC_SEL_PVR4_0108 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_BYPASS_TIMESTAMP_SEL_PVR4_0108 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_BURST_PKT_MODE_PVR4_0108 Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_010C_TSP4 (0x10C)
	#define TSP4_REG_PAUSE_TIME_PVR4_0_010C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0110_TSP4 (0x110)
	#define TSP4_REG_PAUSE_TIME_PVR4_1_0110 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0114_TSP4 (0x114)
	#define TSP4_REG_FORCE_SYNC_BYTE_VAL_PVR4_0114 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_01C0_TSP4 (0x1C0)
	#define TSP4_REG_ERR_PKT_SRC_SEL_01C0 Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_01C4_TSP4 (0x1C4)
	#define TSP4_REG_ERR_PKT_CNT_0_LOAD_01C4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_ERR_PKT_CNT_FILE_LOAD_01C4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_ERR_PKT_CNT_1_LOAD_01C4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_ERR_PKT_CNT_2_LOAD_01C4 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_ERR_PKT_CNT_MMFI0_LOAD_01C4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_ERR_PKT_CNT_MMFI1_LOAD_01C4 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_01C8_TSP4 (0x1C8)
	#define TSP4_REG_ERR_PKT_CNT_0_CLR_01C8 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_ERR_PKT_CNT_FILE_CLR_01C8 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_ERR_PKT_CNT_1_CLR_01C8 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_ERR_PKT_CNT_2_CLR_01C8 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_ERR_PKT_CNT_MMFI0_CLR_01C8 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_ERR_PKT_CNT_MMFI1_CLR_01C8 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_01E0_TSP4 (0x1E0)
	#define TSP4_REG_AUDC_SRC_01E0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define TSP4_REG_AUDD_SRC_01E0 Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_01E4_TSP4 (0x1E4)
	#define TSP4_REG_SCRMB_PKT_CNT_V_CLR_01E4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_SCRMB_PKT_CNT_V3D_CLR_01E4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_SCRMB_PKT_CNT_A_CLR_01E4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_SCRMB_PKT_CNT_AD_CLR_01E4 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_SCRMB_PKT_CNT_ADC_CLR_01E4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_SCRMB_PKT_CNT_ADD_CLR_01E4 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_01E8_TSP4 (0x1E8)
	#define TSP4_REG_LOCKED_PKT_CNT_0_LOAD_01E8 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_LOCKED_PKT_CNT_1_LOAD_01E8 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_LOCKED_PKT_CNT_2_LOAD_01E8 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_LOCKED_PKT_CNT_FI_LOAD_01E8 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_LOCKED_PKT_CNT_FILEIN_LOAD_01E8 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_LOCKED_PKT_CNT_MM0_LOAD_01E8 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP4_REG_LOCKED_PKT_CNT_MM1_LOAD_01E8 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP4_REG_V_PKT_CNT_LOAD_01E8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_V3D_PKT_CNT_LOAD_01E8 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_A_PKT_CNT_LOAD_01E8 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_AD_PKT_CNT_LOAD_01E8 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_ADC_PKT_CNT_LOAD_01E8 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_ADD_PKT_CNT_LOAD_01E8 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_01EC_TSP4 (0x1EC)
	#define TSP4_REG_DROP_PKT_CNT_V_LOAD_01EC Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_DROP_PKT_CNT_V3D_LOAD_01EC Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_DROP_PKT_CNT_A_LOAD_01EC Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_DROP_PKT_CNT_AD_LOAD_01EC Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_DROP_PKT_CNT_ADC_LOAD_01EC Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_DROP_PKT_CNT_ADD_LOAD_01EC Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_DIS_CNTR_V_LOAD_01EC Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_DIS_CNTR_V3D_LOAD_01EC Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_DIS_CNTR_A_LOAD_01EC Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_DIS_CNTR_AD_LOAD_01EC Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_DIS_CNTR_ADC_LOAD_01EC Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_DIS_CNTR_ADD_LOAD_01EC Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_01F0_TSP4 (0x1F0)
	#define TSP4_REG_LOCKED_PKT_CNT_0_CLR_01F0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_LOCKED_PKT_CNT_1_CLR_01F0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_LOCKED_PKT_CNT_2_CLR_01F0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_LOCKED_PKT_CNT_FI_CLR_01F0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_LOCKED_PKT_CNT_FILEIN_CLR_01F0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_LOCKED_PKT_CNT_MM0_CLR_01F0 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP4_REG_LOCKED_PKT_CNT_MM1_CLR_01F0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP4_REG_V_PKT_CNT_CLR_01F0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_V3D_PKT_CNT_CLR_01F0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_A_PKT_CNT_CLR_01F0 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_AD_PKT_CNT_CLR_01F0 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_ADC_PKT_CNT_CLR_01F0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_ADD_PKT_CNT_CLR_01F0 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_01F4_TSP4 (0x1F4)
	#define TSP4_REG_DROP_PKT_CNT_V_CLR_01F4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_DROP_PKT_CNT_V3D_CLR_01F4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_DROP_PKT_CNT_A_CLR_01F4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP4_REG_DROP_PKT_CNT_AD_CLR_01F4 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP4_REG_DROP_PKT_CNT_ADC_CLR_01F4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP4_REG_DROP_PKT_CNT_ADD_CLR_01F4 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP4_REG_DIS_CNTR_V_CLR_01F4 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_DIS_CNTR_V3D_CLR_01F4 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP4_REG_DIS_CNTR_A_CLR_01F4 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP4_REG_DIS_CNTR_AD_CLR_01F4 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP4_REG_DIS_CNTR_ADC_CLR_01F4 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP4_REG_DIS_CNTR_ADD_CLR_01F4 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_01F8_TSP4 (0x1F8)
	#define TSP4_REG_VID_SRC_01F8 Fld(3, 0, AC_MSKB0)//[2:0]
	#define TSP4_REG_VID_3D_SRC_01F8 Fld(3, 3, AC_MSKB0)//[5:3]
	#define TSP4_REG_AUDA_SRC_01F8 Fld(3, 6, AC_MSKW10)//[8:6]
	#define TSP4_REG_AUDB_SRC_01F8 Fld(3, 9, AC_MSKB1)//[11:9]
#define REG_01FC_TSP4 (0x1FC)
	#define TSP4_REG_SRC_SEL_01FC Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP4_REG_DROP_PKT_MODE_01FC Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP4_REG_PIDFLT_SRC_SEL_01FC Fld(3, 2, AC_MSKB0)//[4:2]
	#define TSP4_REG_TSIF_SRC_SEL_01FC Fld(3, 5, AC_MSKB0)//[7:5]
	#define TSP4_REG_AV_PKT_SRC_SEL_01FC Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP4_REG_CLR_SRC_01FC Fld(4, 9, AC_MSKB1)//[12:9]
	#define TSP4_REG_TSIF_SRC_SEL_EXT_01FC Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP4_REG_SCRMB_PKT_MODE_01FC Fld(1, 14, AC_MSKB1)//[14:14]

