// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#include <linux/module.h>
#include <linux/fs.h>
#include <linux/timer.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/timer.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/debugfs.h>
#include <asm/uaccess.h>
#include <asm/siginfo.h>
#include <linux/sched.h>
#include <asm/uaccess.h>
#include <linux/device.h>
#include <linux/videodev2.h>
#include <linux/errno.h>
#include <linux/compat.h>
#include <linux/of_address.h>
#include <linux/delay.h>

#include "mtk_mod.h"
#include "mtk_tv_drm_video_panel.h"

#include <linux/clk-provider.h>

static const char *mod_v1_clks[E_MOD_V1_EN_NUM] = {
	[E_MOD_V1_EN_DELTA_B2P2_SRAM2SCACE] = "MOD_EN_DELTA_B2P2_SRAM2SCACE",
	[E_MOD_V1_EN_GUCD_18_LUT2_SRAM2SCACE] = "MOD_EN_GUCD_18_LUT2_SRAM2SCACE",
	[E_MOD_V1_EN_GUCD_256_LUT2_SRAM2SCACE] = "MOD_EN_GUCD_256_LUT2_SRAM2SCACE",
	[E_MOD_V1_EN_HSY_8P3_SRAM2SCACE] = "MOD_EN_HSY_8P3_SRAM2SCACE",
	[E_MOD_V1_EN_HSY_8P_SRAM2SCACE] = "MOD_EN_HSY_8P_SRAM2SCACE",
	[E_MOD_V1_EN_LCE_ACE_SRAM2SCACE] = "MOD_EN_LCE_ACE_SRAM2SCACE",
	[E_MOD_V1_EN_VIP_ACE_SRAM2SCACE] = "MOD_EN_VIP_ACE_SRAM2SCACE",
	[E_MOD_V1_EN_XC_FS2SCACE_HSY] = "MOD_EN_XC_FS2SCACE_HSY",
	[E_MOD_V1_EN_XC_FS2SCACE_VIP] = "MOD_EN_XC_FS2SCACE_VIP",
	[E_MOD_V1_EN_XTAL_12M2SCACE] = "MOD_EN_XTAL_12M2SCACE",
	[E_MOD_V1_EN_XTAL_24M2SCACE] = "MOD_EN_XTAL_24M2SCACE",
	[E_MOD_V1_EN_DV_HW5_SRAM2SCDV] = "MOD_EN_DV_HW5_SRAM2SCDV",
	[E_MOD_V1_EN_XC_FN_22SCDV] = "MOD_EN_XC_FN_22SCDV",
	[E_MOD_V1_EN_XC_FN2SCDV] = "MOD_EN_XC_FN2SCDV",
	[E_MOD_V1_EN_XTAL_12M2SCDV] = "MOD_EN_XTAL_12M2SCDV",
	[E_MOD_V1_EN_XTAL_24M2SCDV] = "MOD_EN_XTAL_24M2SCDV",
	[E_MOD_V1_EN_SIDCLK_HD02SCIP] = "MOD_EN_SIDCLK_HD02SCIP",
	[E_MOD_V1_EN_SIDCLK_HD12SCIP] = "MOD_EN_SIDCLK_HD12SCIP",
	[E_MOD_V1_EN_SIDCLK_HD22SCIP] = "MOD_EN_SIDCLK_HD22SCIP",
	[E_MOD_V1_EN_SIDCLK_HD32SCIP] = "MOD_EN_SIDCLK_HD32SCIP",
	[E_MOD_V1_EN_UCD_ST_SRAM2SCIP] = "MOD_EN_UCD_ST_SRAM2SCIP",
	[E_MOD_V1_EN_XC_ADC2SCIP] = "MOD_EN_XC_ADC2SCIP",
	[E_MOD_V1_EN_XC_DBG2MIU2SCIP] = "MOD_EN_XC_DBG2MIU2SCIP",
	[E_MOD_V1_EN_XC_DIP02SCIP] = "MOD_EN_XC_DIP02SCIP",
	[E_MOD_V1_EN_XC_DIP12SCIP] = "MOD_EN_XC_DIP12SCIP",
	[E_MOD_V1_EN_XC_DIP22SCIP] = "MOD_EN_XC_DIP22SCIP",
	[E_MOD_V1_EN_XC_DISP_MFDEC2SCIP] = "MOD_EN_XC_DISP_MFDEC2SCIP",
	[E_MOD_V1_EN_XC_ED02SCIP] = "MOD_EN_XC_ED02SCIP",
	[E_MOD_V1_EN_XC_ED12SCIP] = "MOD_EN_XC_ED12SCIP",
	[E_MOD_V1_EN_XC_FD2SCIP] = "MOD_EN_XC_FD2SCIP",
	[E_MOD_V1_EN_XC_FN2SCIP] = "MOD_EN_XC_FN2SCIP",
	[E_MOD_V1_EN_XC_FS2SCIP] = "MOD_EN_XC_FS2SCIP",
	[E_MOD_V1_EN_XC_HD2MIU_M2SCIP] = "MOD_EN_XC_HD2MIU_M2SCIP",
	[E_MOD_V1_EN_XC_HD2MIU_S2SCIP] = "MOD_EN_XC_HD2MIU_S2SCIP",
	[E_MOD_V1_EN_XC_HDMI02SCIP] = "MOD_EN_XC_HDMI02SCIP",
	[E_MOD_V1_EN_XC_HDMI12SCIP] = "MOD_EN_XC_HDMI12SCIP",
	[E_MOD_V1_EN_XC_HDMI22SCIP] = "MOD_EN_XC_HDMI22SCIP",
	[E_MOD_V1_EN_XC_HDMI32SCIP] = "MOD_EN_XC_HDMI32SCIP",
	[E_MOD_V1_EN_XC_ID02SCIP] = "MOD_EN_XC_ID02SCIP",
	[E_MOD_V1_EN_XC_ID12SCIP] = "MOD_EN_XC_ID12SCIP",
	[E_MOD_V1_EN_XC_IP2_SRC2SCIP] = "MOD_EN_XC_IP2_SRC2SCIP",
	[E_MOD_V1_EN_XC_OD_DELTA2SCIP] = "MOD_EN_XC_OD_DELTA2SCIP",
	[E_MOD_V1_EN_XC_OD2SCIP] = "MOD_EN_XC_OD2SCIP",
	[E_MOD_V1_EN_XC_SLOW2SCIP] = "MOD_EN_XC_SLOW2SCIP",
	[E_MOD_V1_EN_XC_UCD_STAT2SCIP] = "MOD_EN_XC_UCD_STAT2SCIP",
	[E_MOD_V1_EN_XC_VD2SCIP] = "MOD_EN_XC_VD2SCIP",
	[E_MOD_V1_EN_XC_VE2SCIP] = "MOD_EN_XC_VE2SCIP",
	[E_MOD_V1_EN_XC_VEIN2SCIP] = "MOD_EN_XC_VEIN2SCIP",
	[E_MOD_V1_EN_XTAL_12M2SCIP] = "MOD_EN_XTAL_12M2SCIP",
	[E_MOD_V1_EN_XTAL_24M2SCIP] = "MOD_EN_XTAL_24M2SCIP",
	[E_MOD_V1_EN_XTAL_IP12SCIP] = "MOD_EN_XTAL_IP12SCIP",
	[E_MOD_V1_EN_DIP1_HVSP_SRAM2SCMW] = "MOD_EN_DIP1_HVSP_SRAM2SCMW",
	[E_MOD_V1_EN_DIP1_XVYCC_SRAM2SCMW] = "MOD_EN_DIP1_XVYCC_SRAM2SCMW",
	[E_MOD_V1_EN_HSY_8P3_SRAM2SCMW] = "MOD_EN_HSY_8P3_SRAM2SCMW",
	[E_MOD_V1_EN_HSY_8P_SRAM2SCMW] = "MOD_EN_HSY_8P_SRAM2SCMW",
	[E_MOD_V1_EN_RGB_3DLUT_SRAM2SCMW] = "MOD_EN_RGB_3DLUT_SRAM2SCMW",
	[E_MOD_V1_EN_XC_FD2SCMW] = "MOD_EN_XC_FD2SCMW",
	[E_MOD_V1_EN_XC_FN2SCMW] = "MOD_EN_XC_FN2SCMW",
	[E_MOD_V1_EN_XC_FS2SCMW] = "MOD_EN_XC_FS2SCMW",
	[E_MOD_V1_EN_XC_OD2SCMW] = "MOD_EN_XC_OD2SCMW",
	[E_MOD_V1_EN_XTAL_24M2SCMW] = "MOD_EN_XTAL_24M2SCMW",
	[E_MOD_V1_EN_XVYCC_SRAM2SCMW] = "MOD_EN_XVYCC_SRAM2SCMW",
	[E_MOD_V1_EN_DISP_MFDEC2SCNR] = "MOD_EN_DISP_MFDEC2SCNR",
	[E_MOD_V1_EN_XC_FN2SCNR] = "MOD_EN_XC_FN2SCNR",
	[E_MOD_V1_EN_XTAL_24M2SCNR] = "MOD_EN_XTAL_24M2SCNR",
	[E_MOD_V1_EN_DBK_HW_SRAM2SCPQ] = "MOD_EN_DBK_HW_SRAM2SCPQ",
	[E_MOD_V1_EN_SCNR_HDR_SRAM2SCPQ] = "MOD_EN_SCNR_HDR_SRAM2SCPQ",
	[E_MOD_V1_EN_SPF_HDBK_SRAM2SCPQ] = "MOD_EN_SPF_HDBK_SRAM2SCPQ",
	[E_MOD_V1_EN_VDBK_SRAM2SCPQ] = "MOD_EN_VDBK_SRAM2SCPQ",
	[E_MOD_V1_EN_XC_FN2SCPQ_SPF] = "MOD_EN_XC_FN2SCPQ_SPF",
	[E_MOD_V1_EN_XC_FN2SCPQ_DOLBY] = "MOD_EN_XC_FN2SCPQ_DOLBY",
	[E_MOD_V1_EN_XTAL_24M2SCPQ] = "MOD_EN_XTAL_24M2SCPQ",
	[E_MOD_V1_EN_DELTA_B2P_SRAM2SCSCL] = "MOD_EN_DELTA_B2P_SRAM2SCSCL",
	[E_MOD_V1_EN_GUCD_18_SRAM2SCSCL] = "MOD_EN_GUCD_18_SRAM2SCSCL",
	[E_MOD_V1_EN_GUCD_256_SRAM2SCSCL] = "MOD_EN_GUCD_256_SRAM2SCSCL",
	[E_MOD_V1_EN_HSY_SP3_SRAM2SCSCL] = "MOD_EN_HSY_SP3_SRAM2SCSCL",
	[E_MOD_V1_EN_HSY_SP_SRAM2SCSCL] = "MOD_EN_HSY_SP_SRAM2SCSCL",
	[E_MOD_V1_EN_HVSP_STP1_SRAM2SCSCL] = "MOD_EN_HVSP_STP1_SRAM2SCSCL",
	[E_MOD_V1_EN_HVSP_STP2_SRAM2SCSCL] = "MOD_EN_HVSP_STP2_SRAM2SCSCL",
	[E_MOD_V1_EN_LCE_SCL_SRAM2SCSCL] = "MOD_EN_LCE_SCL_SRAM2SCSCL",
	[E_MOD_V1_EN_VIP_PQ_SRAM2SCSCL] = "MOD_EN_VIP_PQ_SRAM2SCSCL",
	[E_MOD_V1_EN_XC_FD2SCSCL] = "MOD_EN_XC_FD2SCSCL",
	[E_MOD_V1_EN_XC_FN2SCSCL] = "MOD_EN_XC_FN2SCSCL",
	[E_MOD_V1_EN_XC_FS2SCSCL] = "MOD_EN_XC_FS2SCSCL",
	[E_MOD_V1_EN_XC_OD_DELTA2SCSCL] = "MOD_EN_XC_OD_DELTA2SCSCL",
	[E_MOD_V1_EN_XC_OD2SCSCL] = "MOD_EN_XC_OD2SCSCL",
	[E_MOD_V1_EN_XTAL_12M2SCSCL] = "MOD_EN_XTAL_12M2SCSCL",
	[E_MOD_V1_EN_XTAL_24M2SCSCL] = "MOD_EN_XTAL_24M2SCSCL",
	[E_MOD_V1_EN_AISR_HVSP_SRAM2SCSR] = "MOD_EN_AISR_HVSP_SRAM2SCSR",
	[E_MOD_V1_EN_AISR_SRAM2SCSR] = "MOD_EN_AISR_SRAM2SCSR",
	[E_MOD_V1_EN_AISR_SRAM_PH_12SCSR] = "MOD_EN_AISR_SRAM_PH_12SCSR",
	[E_MOD_V1_EN_XC_AISR2SCSR] = "MOD_EN_XC_AISR2SCSR",
	[E_MOD_V1_EN_XC_FN2SCSR] = "MOD_EN_XC_FN2SCSR",
	[E_MOD_V1_EN_XC_FS2SCSR] = "MOD_EN_XC_FS2SCSR",
	[E_MOD_V1_EN_XC_SR_ALAI2SCSR] = "MOD_EN_XC_SR_ALAI2SCSR",
	[E_MOD_V1_EN_XC_SR_SRAM_SHARE2SCSR] = "MOD_EN_XC_SR_SRAM_SHARE2SCSR",
	[E_MOD_V1_EN_XC_SRS2SCSR] = "MOD_EN_XC_SRS2SCSR",
	[E_MOD_V1_EN_XTAL_12M2SCSR] = "MOD_EN_XTAL_12M2SCSR",
	[E_MOD_V1_EN_XTAL_24M2SCSR] = "MOD_EN_XTAL_24M2SCSR",
	[E_MOD_V1_EN_DEMURA_SRAM2SCTCON] = "MOD_EN_DEMURA_SRAM2SCTCON",
	[E_MOD_V1_EN_GOP0_SRAM2SCTCON] = "MOD_EN_GOP0_SRAM2SCTCON",
	[E_MOD_V1_EN_GOP1_SRAM2SCTCON] = "MOD_EN_GOP1_SRAM2SCTCON",
	[E_MOD_V1_EN_GOP2_SRAM2SCTCON] = "MOD_EN_GOP2_SRAM2SCTCON",
	[E_MOD_V1_EN_GOP3_SRAM2SCTCON] = "MOD_EN_GOP3_SRAM2SCTCON",
	[E_MOD_V1_EN_LD_EDGE2D_SRAM2SCTCON] = "MOD_EN_LD_EDGE2D_SRAM2SCTCON",
	[E_MOD_V1_EN_LDCOMP_SRAM2SCTCON] = "MOD_EN_LDCOMP_SRAM2SCTCON",
	[E_MOD_V1_EN_LDM_GA_SRAM2SCTCON] = "MOD_EN_LDM_GA_SRAM2SCTCON",
	[E_MOD_V1_EN_LDMCG_SRAM2SCTCON] = "MOD_EN_LDMCG_SRAM2SCTCON",
	[E_MOD_V1_EN_LPQ_PA_SRAM2SCTCON] = "MOD_EN_LPQ_PA_SRAM2SCTCON",
	[E_MOD_V1_EN_OSD_DV_HW5_SRAM2SCTCON] = "MOD_EN_OSD_DV_HW5_SRAM2SCTCON",
	[E_MOD_V1_EN_PADJ_SRAM2SCTCON] = "MOD_EN_PADJ_SRAM2SCTCON",
	[E_MOD_V1_EN_PANEL_GA_SRAM2SCTCON] = "MOD_EN_PANEL_GA_SRAM2SCTCON",
	[E_MOD_V1_EN_XC_AFBC2SCTCON] = "MOD_EN_XC_AFBC2SCTCON",
	[E_MOD_V1_EN_XC_FD_ABF2SCTCON] = "MOD_EN_XC_FD_ABF2SCTCON",
	[E_MOD_V1_EN_XC_FD_DV2SCTCON] = "MOD_EN_XC_FD_DV2SCTCON",
	[E_MOD_V1_EN_XC_FD_GOP02SCTCON] = "MOD_EN_XC_FD_GOP02SCTCON",
	[E_MOD_V1_EN_XC_FD2SCTCON] = "MOD_EN_XC_FD2SCTCON",
	[E_MOD_V1_EN_XC_FN2SCTCON] = "MOD_EN_XC_FN2SCTCON",
	[E_MOD_V1_EN_XC_FS2SCTCON] = "MOD_EN_XC_FS2SCTCON",
	[E_MOD_V1_EN_XC_GOP0_DST2SCTCON] = "MOD_EN_XC_GOP0_DST2SCTCON",
	[E_MOD_V1_EN_XC_GOP2SCTCON] = "MOD_EN_XC_GOP2SCTCON",
	[E_MOD_V1_EN_XC_GOP_SCL2SCTCON] = "MOD_EN_XC_GOP_SCL2SCTCON",
	[E_MOD_V1_EN_XC_GOPC_DST2SCTCON] = "MOD_EN_XC_GOPC_DST2SCTCON",
	[E_MOD_V1_EN_XC_GOPG_DST2SCTCON] = "MOD_EN_XC_GOPG_DST2SCTCON",
	[E_MOD_V1_EN_XC_OD_DELTA2SCTCON] = "MOD_EN_XC_OD_DELTA2SCTCON",
	[E_MOD_V1_EN_XC_OD_DELTA_META2SCTCON] = "MOD_EN_XC_OD_DELTA_META2SCTCON",
	[E_MOD_V1_EN_XC_OD_DIV22SCTCON] = "MOD_EN_XC_OD_DIV22SCTCON",
	[E_MOD_V1_EN_XC_OD_DIV42SCTCON] = "MOD_EN_XC_OD_DIV42SCTCON",
	[E_MOD_V1_EN_XC_OD_EDGE2SCTCON] = "MOD_EN_XC_OD_EDGE2SCTCON",
	[E_MOD_V1_EN_XC_OD2SCTCON] = "MOD_EN_XC_OD2SCTCON",
	[E_MOD_V1_EN_XC_OD_META2SCTCON] = "MOD_EN_XC_OD_META2SCTCON",
	[E_MOD_V1_EN_XC_OD_OSD2SCTCON] = "MOD_EN_XC_OD_OSD2SCTCON",
	[E_MOD_V1_EN_XC_OD_OSD_META2SCTCON] = "MOD_EN_XC_OD_OSD_META2SCTCON",
	[E_MOD_V1_EN_XTAL_12M2SCTCON] = "MOD_EN_XTAL_12M2SCTCON",
	[E_MOD_V1_EN_XTAL_24M2SCTCON] = "MOD_EN_XTAL_24M2SCTCON",
	[E_MOD_V1_EN_SMI2SCACE] = "MOD_EN_SMI2SCACE",
	[E_MOD_V1_EN_SMI2SCDV] = "MOD_EN_SMI2SCDV",
	[E_MOD_V1_EN_SMI2SCMW] = "MOD_EN_SMI2SCMW",
	[E_MOD_V1_EN_SMI2SCPQ] = "MOD_EN_SMI2SCPQ",
	[E_MOD_V1_EN_SMI2SCSCL] = "MOD_EN_SMI2SCSCL",
	[E_MOD_V1_EN_SMI2SCSR] = "MOD_EN_SMI2SCSR",
	[E_MOD_V1_EN_DAP2FRCIOPM] = "MOD_EN_DAP2FRCIOPM",
	[E_MOD_V1_EN_RV55DAP_JTAG_TCK2FRCIOPM] = "MOD_EN_RV55DAP_JTAG_TCK2FRCIOPM",
	[E_MOD_V1_EN_XTAL_12M2FRCIOPM] = "MOD_EN_XTAL_12M2FRCIOPM",
	[E_MOD_V1_EN_FRC_FUART02FRCIOPM] = "MOD_EN_FRC_FUART02FRCIOPM",
	[E_MOD_V1_EN_FRC_MSPI02FRCIOPM] = "MOD_EN_FRC_MSPI02FRCIOPM",
	[E_MOD_V1_EN_FRC_UART02FRCIOPM] = "MOD_EN_FRC_UART02FRCIOPM",
	[E_MOD_V1_EN_FRC_UART12FRCIOPM] = "MOD_EN_FRC_UART12FRCIOPM",
	[E_MOD_V1_EN_MOD_A_ODCLK2MOD_A] = "MOD_EN_MOD_A_ODCLK2MOD_A",
	[E_MOD_V1_EN_XTAL_12M2MOD_A] = "MOD_EN_XTAL_12M2MOD_A",
	[E_MOD_V1_EN_LPLL_SYN_8642FPLL] = "MOD_EN_LPLL_SYN_8642FPLL",
	[E_MOD_V1_EN_MOD_D_ODCLK2MOD_D] = "MOD_EN_MOD_D_ODCLK2MOD_D",
	[E_MOD_V1_EN_MOD_D_ODCLK2LVDS] = "MOD_EN_MOD_D_ODCLK2LVDS",
	[E_MOD_V1_EN_V1_ODCLK2V1] = "MOD_EN_V1_ODCLK2V1",
	[E_MOD_V1_EN_V1_ODCLK_STG12V1] = "MOD_EN_V1_ODCLK_STG12V1",
	[E_MOD_V1_EN_V1_ODCLK_STG22V1] = "MOD_EN_V1_ODCLK_STG22V1",
	[E_MOD_V1_EN_V1_ODCLK_STG32V1] = "MOD_EN_V1_ODCLK_STG32V1",
	[E_MOD_V1_EN_V1_ODCLK_STG42V1] = "MOD_EN_V1_ODCLK_STG42V1",
	[E_MOD_V1_EN_V1_ODCLK_STG52V1] = "MOD_EN_V1_ODCLK_STG52V1",
	[E_MOD_V1_EN_V1_ODCLK_STG62V1] = "MOD_EN_V1_ODCLK_STG62V1",
	[E_MOD_V1_EN_V1_ODCLK_STG72V1] = "MOD_EN_V1_ODCLK_STG72V1",
	[E_MOD_V1_EN_MOD_V1_SR_WCLK2V1] = "MOD_EN_MOD_V1_SR_WCLK2V1",
	[E_MOD_V1_EN_V1_MOD_SR_RCLK2V1] = "MOD_EN_V1_MOD_SR_RCLK2V1",
	[E_MOD_V1_EN_V1_MOD_SR_RCLK_PRE02V1] = "MOD_EN_V1_MOD_SR_RCLK_PRE02V1",
	[E_MOD_V1_EN_V1_MOD_SR_RCLK_PRE12V1] = "MOD_EN_V1_MOD_SR_RCLK_PRE12V1",
	[E_MOD_V1_EN_V1_MOD_SR_RCLK_FINIAL2V1] = "MOD_EN_V1_MOD_SR_RCLK_FINIAL2V1",
	[E_MOD_V1_EN_V1_ODCLK_STG82V1] = "MOD_EN_V1_ODCLK_STG82V1",
	[E_MOD_V1_EN_V1_ODCLK_STG92V1] = "MOD_EN_V1_ODCLK_STG92V1",
	[E_MOD_V1_EN_MOD_V1_SR_WCLK2VBY1_V1] = "MOD_EN_MOD_V1_SR_WCLK2VBY1_V1",
	[E_MOD_V1_EN_V2_ODCLK_STG32V2] = "MOD_EN_V2_ODCLK_STG32V2",
	[E_MOD_V1_EN_MOD_V2_SR_WCLK2V2] = "MOD_EN_MOD_V2_SR_WCLK2V2",
	[E_MOD_V1_EN_V2_MOD_SR_RCLK2V2] = "MOD_EN_V2_MOD_SR_RCLK2V2",
	[E_MOD_V1_EN_V2_MOD_SR_RCLK_PRE02V2] = "MOD_EN_V2_MOD_SR_RCLK_PRE02V2",
	[E_MOD_V1_EN_V2_MOD_SR_RCLK_PRE12V2] = "MOD_EN_V2_MOD_SR_RCLK_PRE12V2",
	[E_MOD_V1_EN_LPLL_SYN_4322FPLL] = "MOD_EN_LPLL_SYN_4322FPLL",
	[E_MOD_V1_EN_XTAL_24M2FPLL] = "MOD_EN_XTAL_24M2FPLL",
	[E_MOD_V1_EN_XC_SUB_DC02SCIP] = "MOD_EN_XC_SUB_DC02SCIP",
	[E_MOD_V1_EN_XC_TGEN_WIN2SCIP] = "MOD_EN_XC_TGEN_WIN2SCIP",
	[E_MOD_V1_EN_SMI2SCM] = "MOD_EN_SMI2SCM",
	[E_MOD_V1_EN_SMI2SCMO] = "MOD_EN_SMI2SCMO",
	[E_MOD_V1_EN_XC_VEDAC2SCIP] = "MOD_EN_XC_VEDAC2SCIP",
	[E_MOD_V1_EN_LPLL_SYN_864_PIPE2FPLL] = "MOD_EN_LPLL_SYN_864_PIPE2FPLL",
	[E_B2R_V1_EN_DC0_SRAM2SCIP] = "B2R_EN_DC0_SRAM2SCIP",
	[E_B2R_V1_EN_XC_DC02SCIP] = "B2R_EN_XC_DC02SCIP",
};

static const char *mod_v2_clks[E_MOD_V2_EN_NUM] = {
	[E_MOD_V2_EN_LPLL_SYN_4322FPLL] = "MOD_CLK_V2_EN_LPLL_SYN_4322FPLL",
	[E_MOD_V2_EN_MOD_A_ODCLK2MOD_A] = "MOD_CLK_V2_EN_MOD_A_ODCLK2MOD_A",
	[E_MOD_V2_EN_MOD_D_ODCLK2MOD_D] = "MOD_CLK_V2_EN_MOD_D_ODCLK2MOD_D",
	[E_MOD_V2_EN_MOD_D_ODCLK2LVDS] = "MOD_CLK_V2_EN_MOD_D_ODCLK2LVDS",
	[E_MOD_V2_EN_MOD_V1_SR_WCLK2V1] = "MOD_CLK_V2_EN_MOD_V1_SR_WCLK2V1",
	[E_MOD_V2_EN_MOD_V1_SR_WCLK2VBY1_V1] = "MOD_CLK_V2_EN_MOD_V1_SR_WCLK2VBY1_V1",
	[E_MOD_V2_EN_MOD_V2_SR_WCLK2V2] = "MOD_CLK_V2_EN_MOD_V2_SR_WCLK2V2",
	[E_MOD_V2_EN_V1_MOD_SR_RCLK2V1] = "MOD_CLK_V2_EN_V1_MOD_SR_RCLK2V1",
	[E_MOD_V2_EN_V1_ODCLK2V1] = "MOD_CLK_V2_EN_V1_ODCLK2V1",
	[E_MOD_V2_EN_V1_ODCLK_STG12V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG12V1",
	[E_MOD_V2_EN_V1_ODCLK_STG22V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG22V1",
	[E_MOD_V2_EN_V1_ODCLK_STG32V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG32V1",
	[E_MOD_V2_EN_V1_ODCLK_STG42V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG42V1",
	[E_MOD_V2_EN_V1_ODCLK_STG52V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG52V1",
	[E_MOD_V2_EN_V1_ODCLK_STG62V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG62V1",
	[E_MOD_V2_EN_V1_ODCLK_STG72V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG72V1",
	[E_MOD_V2_EN_V1_ODCLK_STG82V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG82V1",
	[E_MOD_V2_EN_V1_ODCLK_STG92V1] = "MOD_CLK_V2_EN_V1_ODCLK_STG92V1",
	[E_MOD_V2_EN_V2_MOD_SR_RCLK2V2] = "MOD_CLK_V2_EN_V2_MOD_SR_RCLK2V2",
	[E_MOD_V2_EN_V2_ODCLK_STG32V2] = "MOD_CLK_V2_EN_V2_ODCLK_STG32V2",
	[E_MOD_V2_EN_XTAL_12M2MOD_A] = "MOD_CLK_V2_EN_XTAL_12M2MOD_A",
	[E_MOD_V2_EN_XTAL_24M2FPLL] = "MOD_CLK_V2_EN_XTAL_24M2FPLL",
	[E_MOD_V2_EN_V1_MOD_SR_RCLK_FINIAL2V1] = "MOD_CLK_V2_EN_V1_MOD_SR_RCLK_FINIAL2V1",
	[E_MOD_V2_EN_V1_MOD_SR_RCLK_PRE02V1] = "MOD_CLK_V2_EN_V1_MOD_SR_RCLK_PRE02V1",
	[E_MOD_V2_EN_V1_MOD_SR_RCLK_PRE12V1] = "MOD_CLK_V2_EN_V1_MOD_SR_RCLK_PRE12V1",
	[E_MOD_V2_EN_V2_MOD_SR_RCLK_PRE02V2] = "MOD_CLK_V2_EN_V2_MOD_SR_RCLK_PRE02V2",
	[E_MOD_V2_EN_V2_MOD_SR_RCLK_PRE12V2] = "MOD_CLK_V2_EN_V2_MOD_SR_RCLK_PRE12V2",
	[E_MOD_V2_EN_DELTA_B2P2_SRAM2SCACE] = "MOD_CLK_V2_EN_DELTA_B2P2_SRAM2SCACE",
	[E_MOD_V2_EN_GUCD_18_LUT2_SRAM2SCACE] = "MOD_CLK_V2_EN_GUCD_18_LUT2_SRAM2SCACE",
	[E_MOD_V2_EN_GUCD_256_LUT2_SRAM2SCACE] = "MOD_CLK_V2_EN_GUCD_256_LUT2_SRAM2SCACE",
	[E_MOD_V2_EN_HSY_8P3_SRAM2SCACE] = "MOD_CLK_V2_EN_HSY_8P3_SRAM2SCACE",
	[E_MOD_V2_EN_HSY_8P_SRAM2SCACE] = "MOD_CLK_V2_EN_HSY_8P_SRAM2SCACE",
	[E_MOD_V2_EN_LCE_ACE_SRAM2SCACE] = "MOD_CLK_V2_EN_LCE_ACE_SRAM2SCACE",
	[E_MOD_V2_EN_SMI2SCACE] = "MOD_CLK_V2_EN_SMI2SCACE",
	[E_MOD_V2_EN_VIP_ACE_SRAM2SCACE] = "MOD_CLK_V2_EN_VIP_ACE_SRAM2SCACE",
	[E_MOD_V2_EN_XC_FS2SCACE_HSY] = "MOD_CLK_V2_EN_XC_FS2SCACE_HSY",
	[E_MOD_V2_EN_XC_FS2SCACE_VIP] = "MOD_CLK_V2_EN_XC_FS2SCACE_VIP",
	[E_MOD_V2_EN_XTAL_12M2SCACE] = "MOD_CLK_V2_EN_XTAL_12M2SCACE",
	[E_MOD_V2_EN_XTAL_24M2SCACE] = "MOD_CLK_V2_EN_XTAL_24M2SCACE",
	[E_MOD_V2_EN_DV_HW5_SRAM2SCDV] = "MOD_CLK_V2_EN_DV_HW5_SRAM2SCDV",
	[E_MOD_V2_EN_SMI2SCDV] = "MOD_CLK_V2_EN_SMI2SCDV",
	[E_MOD_V2_EN_XC_FN_22SCDV] = "MOD_CLK_V2_EN_XC_FN_22SCDV",
	[E_MOD_V2_EN_XC_FN2SCDV] = "MOD_CLK_V2_EN_XC_FN2SCDV",
	[E_MOD_V2_EN_XTAL_12M2SCDV] = "MOD_CLK_V2_EN_XTAL_12M2SCDV",
	[E_MOD_V2_EN_XTAL_24M2SCDV] = "MOD_CLK_V2_EN_XTAL_24M2SCDV",
	[E_MOD_V2_EN_SIDCLK_HD02SCIP] = "MOD_CLK_V2_EN_SIDCLK_HD02SCIP",
	[E_MOD_V2_EN_SIDCLK_HD12SCIP] = "MOD_CLK_V2_EN_SIDCLK_HD12SCIP",
	[E_MOD_V2_EN_SIDCLK_HD22SCIP] = "MOD_CLK_V2_EN_SIDCLK_HD22SCIP",
	[E_MOD_V2_EN_SIDCLK_HD32SCIP] = "MOD_CLK_V2_EN_SIDCLK_HD32SCIP",
	[E_MOD_V2_EN_UCD_ST_SRAM2SCIP] = "MOD_CLK_V2_EN_UCD_ST_SRAM2SCIP",
	[E_MOD_V2_EN_XC_ADC2SCIP] = "MOD_CLK_V2_EN_XC_ADC2SCIP",
	[E_MOD_V2_EN_XC_DBG2MIU2SCIP] = "MOD_CLK_V2_EN_XC_DBG2MIU2SCIP",
	[E_MOD_V2_EN_XC_DIP02SCIP] = "MOD_CLK_V2_EN_XC_DIP02SCIP",
	[E_MOD_V2_EN_XC_DIP12SCIP] = "MOD_CLK_V2_EN_XC_DIP12SCIP",
	[E_MOD_V2_EN_XC_DIP22SCIP] = "MOD_CLK_V2_EN_XC_DIP22SCIP",
	[E_MOD_V2_EN_XC_DISP_MFDEC2SCIP] = "MOD_CLK_V2_EN_XC_DISP_MFDEC2SCIP",
	[E_MOD_V2_EN_XC_ED02SCIP] = "MOD_CLK_V2_EN_XC_ED02SCIP",
	[E_MOD_V2_EN_XC_ED12SCIP] = "MOD_CLK_V2_EN_XC_ED12SCIP",
	[E_MOD_V2_EN_XC_FD2SCIP] = "MOD_CLK_V2_EN_XC_FD2SCIP",
	[E_MOD_V2_EN_XC_FN2SCIP] = "MOD_CLK_V2_EN_XC_FN2SCIP",
	[E_MOD_V2_EN_XC_FS2SCIP] = "MOD_CLK_V2_EN_XC_FS2SCIP",
	[E_MOD_V2_EN_XC_HD2MIU_M2SCIP] = "MOD_CLK_V2_EN_XC_HD2MIU_M2SCIP",
	[E_MOD_V2_EN_XC_HD2MIU_S2SCIP] = "MOD_CLK_V2_EN_XC_HD2MIU_S2SCIP",
	[E_MOD_V2_EN_XC_HDMI02SCIP] = "MOD_CLK_V2_EN_XC_HDMI02SCIP",
	[E_MOD_V2_EN_XC_HDMI12SCIP] = "MOD_CLK_V2_EN_XC_HDMI12SCIP",
	[E_MOD_V2_EN_XC_HDMI22SCIP] = "MOD_CLK_V2_EN_XC_HDMI22SCIP",
	[E_MOD_V2_EN_XC_HDMI32SCIP] = "MOD_CLK_V2_EN_XC_HDMI32SCIP",
	[E_MOD_V2_EN_XC_ID02SCIP] = "MOD_CLK_V2_EN_XC_ID02SCIP",
	[E_MOD_V2_EN_XC_ID12SCIP] = "MOD_CLK_V2_EN_XC_ID12SCIP",
	[E_MOD_V2_EN_XC_IP2_SRC2SCIP] = "MOD_CLK_V2_EN_XC_IP2_SRC2SCIP",
	[E_MOD_V2_EN_XC_OD_DELTA2SCIP] = "MOD_CLK_V2_EN_XC_OD_DELTA2SCIP",
	[E_MOD_V2_EN_XC_OD2SCIP] = "MOD_CLK_V2_EN_XC_OD2SCIP",
	[E_MOD_V2_EN_XC_SLOW2SCIP] = "MOD_CLK_V2_EN_XC_SLOW2SCIP",
	[E_MOD_V2_EN_XC_SUB_DC02SCIP] = "MOD_CLK_V2_EN_XC_SUB_DC02SCIP",
	[E_MOD_V2_EN_XC_TGEN_WIN2SCIP] = "MOD_CLK_V2_EN_XC_TGEN_WIN2SCIP",
	[E_MOD_V2_EN_XC_UCD_STAT2SCIP] = "MOD_CLK_V2_EN_XC_UCD_STAT2SCIP",
	[E_MOD_V2_EN_XC_VD2SCIP] = "MOD_CLK_V2_EN_XC_VD2SCIP",
	[E_MOD_V2_EN_XC_VE2SCIP] = "MOD_CLK_V2_EN_XC_VE2SCIP",
	[E_MOD_V2_EN_XC_VEDAC2SCIP] = "MOD_CLK_V2_EN_XC_VEDAC2SCIP",
	[E_MOD_V2_EN_XC_VEIN2SCIP] = "MOD_CLK_V2_EN_XC_VEIN2SCIP",
	[E_MOD_V2_EN_XTAL_12M2SCIP] = "MOD_CLK_V2_EN_XTAL_12M2SCIP",
	[E_MOD_V2_EN_XTAL_24M2SCIP] = "MOD_CLK_V2_EN_XTAL_24M2SCIP",
	[E_MOD_V2_EN_XTAL_IP12SCIP] = "MOD_CLK_V2_EN_XTAL_IP12SCIP",
	[E_MOD_V2_EN_DIP1_HVSP_SRAM2SCMW] = "MOD_CLK_V2_EN_DIP1_HVSP_SRAM2SCMW",
	[E_MOD_V2_EN_DIP1_XVYCC_SRAM2SCMW] = "MOD_CLK_V2_EN_DIP1_XVYCC_SRAM2SCMW",
	[E_MOD_V2_EN_HSY_8P3_SRAM2SCMW] = "MOD_CLK_V2_EN_HSY_8P3_SRAM2SCMW",
	[E_MOD_V2_EN_HSY_8P_SRAM2SCMW] = "MOD_CLK_V2_EN_HSY_8P_SRAM2SCMW",
	[E_MOD_V2_EN_PQ_GAMMA_SRAM2SCMW] = "MOD_CLK_V2_EN_RGB_3DLUT_SRAM2SCMW",
	[E_MOD_V2_EN_RGB_3DLUT_SRAM2SCMW] = "MOD_CLK_V2_EN_RGB_3DLUT_SRAM2SCMW",
	[E_MOD_V2_EN_SMI2SCMW] = "MOD_CLK_V2_EN_SMI2SCMW",
	[E_MOD_V2_EN_XC_FD2SCMW] = "MOD_CLK_V2_EN_XC_FD2SCMW",
	[E_MOD_V2_EN_XC_FN2SCMW] = "MOD_CLK_V2_EN_XC_FN2SCMW",
	[E_MOD_V2_EN_XC_FS2SCMW] = "MOD_CLK_V2_EN_XC_FS2SCMW",
	[E_MOD_V2_EN_XC_OD2SCMW] = "MOD_CLK_V2_EN_XC_OD2SCMW",
	[E_MOD_V2_EN_XTAL_24M2SCMW] = "MOD_CLK_V2_EN_XTAL_24M2SCMW",
	[E_MOD_V2_EN_XVYCC_SRAM2SCMW] = "MOD_CLK_V2_EN_XVYCC_SRAM2SCMW",
	[E_MOD_V2_EN_DISP_MFDEC2SCNR] = "MOD_CLK_V2_EN_DISP_MFDEC2SCNR",
	[E_MOD_V2_EN_XC_FN2SCNR] = "MOD_CLK_V2_EN_XC_FN2SCNR",
	[E_MOD_V2_EN_XTAL_24M2SCNR] = "MOD_CLK_V2_EN_XTAL_24M2SCNR",
	[E_MOD_V2_EN_DBK_HW_SRAM2SCPQ] = "MOD_CLK_V2_EN_DBK_HW_SRAM2SCPQ",
	[E_MOD_V2_EN_SCNR_HDR_SRAM2SCPQ] = "MOD_CLK_V2_EN_SCNR_HDR_SRAM2SCPQ",
	[E_MOD_V2_EN_SMI2SCPQ] = "MOD_CLK_V2_EN_SMI2SCPQ",
	[E_MOD_V2_EN_SPF_HDBK_SRAM2SCPQ] = "MOD_CLK_V2_EN_SPF_HDBK_SRAM2SCPQ",
	[E_MOD_V2_EN_VDBK_SRAM2SCPQ] = "MOD_CLK_V2_EN_VDBK_SRAM2SCPQ",
	[E_MOD_V2_EN_XC_FN2SCPQ_SPF] = "MOD_CLK_V2_EN_XC_FN2SCPQ_SPF",
	[E_MOD_V2_EN_XC_FN2SCPQ_DOLBY] = "MOD_CLK_V2_EN_XC_FN2SCPQ_DOLBY",
	[E_MOD_V2_EN_XTAL_24M2SCPQ] = "MOD_CLK_V2_EN_XTAL_24M2SCPQ",
	[E_MOD_V2_EN_DELTA_B2P_SRAM2SCSCL] = "MOD_CLK_V2_EN_DELTA_B2P_SRAM2SCSCL",
	[E_MOD_V2_EN_GUCD_18_SRAM2SCSCL] = "MOD_CLK_V2_EN_GUCD_18_SRAM2SCSCL",
	[E_MOD_V2_EN_GUCD_256_SRAM2SCSCL] = "MOD_CLK_V2_EN_GUCD_256_SRAM2SCSCL",
	[E_MOD_V2_EN_HSY_SP3_SRAM2SCSCL] = "MOD_CLK_V2_EN_HSY_SP3_SRAM2SCSCL",
	[E_MOD_V2_EN_HSY_SP_SRAM2SCSCL] = "MOD_CLK_V2_EN_HSY_SP_SRAM2SCSCL",
	[E_MOD_V2_EN_HVSP_STP1_SRAM2SCSCL] = "MOD_CLK_V2_EN_HVSP_STP1_SRAM2SCSCL",
	[E_MOD_V2_EN_HVSP_STP2_SRAM2SCSCL] = "MOD_CLK_V2_EN_HVSP_STP2_SRAM2SCSCL",
	[E_MOD_V2_EN_LCE_SCL_SRAM2SCSCL] = "MOD_CLK_V2_EN_LCE_SCL_SRAM2SCSCL",
	[E_MOD_V2_EN_SMI2SCSCL] = "MOD_CLK_V2_EN_SMI2SCSCL",
	[E_MOD_V2_EN_VIP_PQ_SRAM2SCSCL] = "MOD_CLK_V2_EN_VIP_PQ_SRAM2SCSCL",
	[E_MOD_V2_EN_XC_FD2SCSCL] = "MOD_CLK_V2_EN_XC_FD2SCSCL",
	[E_MOD_V2_EN_XC_FN2SCSCL] = "MOD_CLK_V2_EN_XC_FN2SCSCL",
	[E_MOD_V2_EN_XC_FS2SCSCL] = "MOD_CLK_V2_EN_XC_FS2SCSCL",
	[E_MOD_V2_EN_XC_OD_DELTA2SCSCL] = "MOD_CLK_V2_EN_XC_OD_DELTA2SCSCL",
	[E_MOD_V2_EN_XC_OD2SCSCL] = "MOD_CLK_V2_EN_XC_OD2SCSCL",
	[E_MOD_V2_EN_XTAL_12M2SCSCL] = "MOD_CLK_V2_EN_XTAL_12M2SCSCL",
	[E_MOD_V2_EN_XTAL_24M2SCSCL] = "MOD_CLK_V2_EN_XTAL_24M2SCSCL",
	[E_MOD_V2_EN_AISR_HVSP_SRAM2SCSR] = "MOD_CLK_V2_EN_AISR_HVSP_SRAM2SCSR",
	[E_MOD_V2_EN_AISR_SRAM2SCSR] = "MOD_CLK_V2_EN_AISR_SRAM2SCSR",
	[E_MOD_V2_EN_AISR_SRAM_PH_12SCSR] = "MOD_CLK_V2_EN_AISR_SRAM_PH_12SCSR",
	[E_MOD_V2_EN_SMI2SCSR] = "MOD_CLK_V2_EN_SMI2SCSR",
	[E_MOD_V2_EN_XC_AISR2SCSR] = "MOD_CLK_V2_EN_XC_AISR2SCSR",
	[E_MOD_V2_EN_XC_FS2SCSR] = "MOD_CLK_V2_EN_XC_FS2SCSR",
	[E_MOD_V2_EN_XC_SR_ALAI2SCSR] = "MOD_CLK_V2_EN_XC_SR_ALAI2SCSR",
	[E_MOD_V2_EN_XC_SR_SRAM_SHARE2SCSR] = "MOD_CLK_V2_EN_XC_SR_SRAM_SHARE2SCSR",
	[E_MOD_V2_EN_XC_SRS2SCSR] = "MOD_CLK_V2_EN_XC_SRS2SCSR",
	[E_MOD_V2_EN_XTAL_12M2SCSR] = "MOD_CLK_V2_EN_XTAL_12M2SCSR",
	[E_MOD_V2_EN_XTAL_24M2SCSR] = "MOD_CLK_V2_EN_XTAL_24M2SCSR",
	[E_MOD_V2_EN_GOP0_SRAM2SCTCON] = "MOD_CLK_V2_EN_GOP0_SRAM2SCTCON",
	[E_MOD_V2_EN_GOP1_SRAM2SCTCON] = "MOD_CLK_V2_EN_GOP1_SRAM2SCTCON",
	[E_MOD_V2_EN_GOP2_SRAM2SCTCON] = "MOD_CLK_V2_EN_GOP2_SRAM2SCTCON",
	[E_MOD_V2_EN_GOP3_SRAM2SCTCON] = "MOD_CLK_V2_EN_GOP3_SRAM2SCTCON",
	[E_MOD_V2_EN_PADJ_SRAM2SCTCON] = "MOD_CLK_V2_EN_PADJ_SRAM2SCTCON",
	[E_MOD_V2_EN_PANEL_GA_SRAM2SCTCON] = "MOD_CLK_V2_EN_PANEL_GA_SRAM2SCTCON",
	[E_MOD_V2_EN_XC_FD2SCTCON] = "MOD_CLK_V2_EN_XC_FD2SCTCON",
	[E_MOD_V2_EN_XC_FN2SCTCON] = "MOD_CLK_V2_EN_XC_FN2SCTCON",
	[E_MOD_V2_EN_XC_FS2SCTCON] = "MOD_CLK_V2_EN_XC_FS2SCTCON",
	[E_MOD_V2_EN_XC_GOP2SCTCON] = "MOD_CLK_V2_EN_XC_GOP2SCTCON",
	[E_MOD_V2_EN_XC_GOP_SCL2SCTCON] = "MOD_CLK_V2_EN_XC_GOP_SCL2SCTCON",
	[E_MOD_V2_EN_XC_OD_DELTA2SCTCON] = "MOD_CLK_V2_EN_XC_OD_DELTA2SCTCON",
	[E_MOD_V2_EN_XC_OD_DELTA_META2SCTCON] = "MOD_CLK_V2_EN_XC_OD_DELTA_META2SCTCON",
	[E_MOD_V2_EN_XC_OD2SCTCON] = "MOD_CLK_V2_EN_XC_OD2SCTCON",
	[E_MOD_V2_EN_XC_OD_META2SCTCON] = "MOD_CLK_V2_EN_XC_OD_META2SCTCON",
	[E_MOD_V2_EN_XC_OD_OSD2SCTCON] = "MOD_CLK_V2_EN_XC_OD_OSD2SCTCON",
	[E_MOD_V2_EN_XC_OD_OSD_META2SCTCON] = "MOD_CLK_V2_EN_XC_OD_OSD_META2SCTCON",
	[E_MOD_V2_EN_XTAL_12M2SCTCON] = "MOD_CLK_V2_EN_XTAL_12M2SCTCON",
	[E_MOD_V2_EN_XTAL_24M2SCTCON] = "MOD_CLK_V2_EN_XTAL_24M2SCTCON"
};

static const char *mod_v3_clks[E_MOD_V3_EN_NUM] = {
	[E_MOD_V3_EN_DAP2FRCIOPMRV55] = "MOD_CLK_V3_EN_DAP2FRCIOPMRV55",
	[E_MOD_V3_EN_FRC_FUART02FRCIOPMRV55] = "MOD_CLK_V3_EN_FRC_FUART02FRCIOPMRV55",
	[E_MOD_V3_EN_FRC_MSPI02FRCIOPMRV55] = "MOD_CLK_V3_EN_FRC_MSPI02FRCIOPMRV55",
	[E_MOD_V3_EN_FRC_UART02FRCIOPMRV55] = "MOD_CLK_V3_EN_FRC_UART02FRCIOPMRV55",
	[E_MOD_V3_EN_FRC_UART12FRCIOPMRV55] = "MOD_CLK_V3_EN_FRC_UART12FRCIOPMRV55",
	[E_MOD_V3_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55] = "MOD_CLK_V3_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55",
	[E_MOD_V3_EN_XTAL_12M2FRCIOPMRV55] = "MOD_CLK_V3_EN_XTAL_12M2FRCIOPMRV55",
	[E_MOD_V3_EN_LPLL_SYN_864_PIPE2FPLL] = "MOD_CLK_V3_EN_LPLL_SYN_864_PIPE2FPLL",
	[E_MOD_V3_EN_LPLL_SYN_4322FPLL] = "MOD_CLK_V3_EN_LPLL_SYN_4322FPLL",
	[E_MOD_V3_EN_MOD_A_ODCLK2MOD_A] = "MOD_CLK_V3_EN_MOD_A_ODCLK2MOD_A",
	[E_MOD_V3_EN_MOD_D_ODCLK2MOD_D] = "MOD_CLK_V3_EN_MOD_D_ODCLK2MOD_D",
	[E_MOD_V3_EN_MOD_D_ODCLK2LVDS] = "MOD_CLK_V3_EN_MOD_D_ODCLK2LVDS",
	[E_MOD_V3_EN_MOD_V1_SR_WCLK2V1] = "MOD_CLK_V3_EN_MOD_V1_SR_WCLK2V1",
	[E_MOD_V3_EN_MOD_V1_SR_WCLK2VBY1_V1] = "MOD_CLK_V3_EN_MOD_V1_SR_WCLK2VBY1_V1",
	[E_MOD_V3_EN_MOD_V2_SR_WCLK2V2] = "MOD_CLK_V3_EN_MOD_V2_SR_WCLK2V2",
	[E_MOD_V3_EN_V1_MOD_SR_RCLK2V1] = "MOD_CLK_V3_EN_V1_MOD_SR_RCLK2V1",
	[E_MOD_V3_EN_V1_ODCLK2V1] = "MOD_CLK_V3_EN_V1_ODCLK2V1",
	[E_MOD_V3_EN_V1_ODCLK_STG12V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG12V1",
	[E_MOD_V3_EN_V1_ODCLK_STG22V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG22V1",
	[E_MOD_V3_EN_V1_ODCLK_STG32V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG32V1",
	[E_MOD_V3_EN_V1_ODCLK_STG42V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG42V1",
	[E_MOD_V3_EN_V1_ODCLK_STG52V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG52V1",
	[E_MOD_V3_EN_V1_ODCLK_STG62V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG62V1",
	[E_MOD_V3_EN_V1_ODCLK_STG72V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG72V1",
	[E_MOD_V3_EN_V1_ODCLK_STG82V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG82V1",
	[E_MOD_V3_EN_V1_ODCLK_STG92V1] = "MOD_CLK_V3_EN_V1_ODCLK_STG92V1",
	[E_MOD_V3_EN_V2_MOD_SR_RCLK2V2] = "MOD_CLK_V3_EN_V2_MOD_SR_RCLK2V2",
	[E_MOD_V3_EN_V2_ODCLK_STG32V2] = "MOD_CLK_V3_EN_V2_ODCLK_STG32V2",
	[E_MOD_V3_EN_XTAL_12M2MOD_A] = "MOD_CLK_V3_EN_XTAL_12M2MOD_A",
	[E_MOD_V3_EN_XTAL_24M2FPLL] = "MOD_CLK_V3_EN_XTAL_24M2FPLL",
	[E_MOD_V3_EN_V1_MOD_SR_RCLK_FINIAL2V1] = "MOD_CLK_V3_EN_V1_MOD_SR_RCLK_FINIAL2V1",
	[E_MOD_V3_EN_V1_MOD_SR_RCLK_PRE02V1] = "MOD_CLK_V3_EN_V1_MOD_SR_RCLK_PRE02V1",
	[E_MOD_V3_EN_V1_MOD_SR_RCLK_PRE12V1] = "MOD_CLK_V3_EN_V1_MOD_SR_RCLK_PRE12V1",
	[E_MOD_V3_EN_V2_MOD_SR_RCLK_PRE02V2] = "MOD_CLK_V3_EN_V2_MOD_SR_RCLK_PRE02V2",
	[E_MOD_V3_EN_V2_MOD_SR_RCLK_PRE12V2] = "MOD_CLK_V3_EN_V2_MOD_SR_RCLK_PRE12V2",
	[E_MOD_V3_EN_SMI2SCACE] = "MOD_CLK_V3_EN_SMI2SCACE",
	[E_MOD_V3_EN_SMI2SCDV] = "MOD_CLK_V3_EN_SMI2SCDV",
	[E_MOD_V3_EN_SMI2SCMW] = "MOD_CLK_V3_EN_SMI2SCMW",
	[E_MOD_V3_EN_SMI2SCPQ] = "MOD_CLK_V3_EN_SMI2SCPQ",
	[E_MOD_V3_EN_SMI2SCSCL] = "MOD_CLK_V3_EN_SMI2SCSCL",
	[E_MOD_V3_EN_SMI2SCSR] = "MOD_CLK_V3_EN_SMI2SCSR",
	[E_B2R_V3_EN_DC0_SRAM2SCIP] = "B2R_EN_DC0_SRAM2SCIP",
	[E_B2R_V3_EN_XC_DC02SCIP] = "B2R_EN_XC_DC02SCIP",
};

static const char *mod_v4_clks[E_MOD_V4_EN_NUM] = {
	[E_MOD_V4_EN_SMI2SCBE] = "MOD_CLK_V4_EN_SMI2SCBE",
	[E_MOD_V4_EN_SMI2SCIP] = "MOD_CLK_V4_EN_SMI2SCIP",
	[E_MOD_V4_EN_SMI2SCTC] = "MOD_CLK_V4_EN_SMI2SCTC",
};

static const char *mod_v5_clks[E_MOD_V5_EN_NUM] = {
	[E_MOD_V5_EN_SMI2SCIP] = "MOD_CLK_V5_EN_SMI2SCIP",
	[E_MOD_V5_EN_SMI2SCBE] = "MOD_CLK_V5_EN_SMI2SCBE",
	[E_MOD_V5_EN_SMI2SCTC] = "MOD_CLK_V5_EN_SMI2SCTC",
	[E_MOD_V5_EN_SMI2SCFE_EMI] = "MOD_CLK_V5_EN_SMI2SCFE_EMI",
	[E_MOD_V5_EN_SMI2SCFE_SMI_IP] = "MOD_CLK_V5_EN_SMI2SCFE_SMI_IP",
	[E_MOD_V5_EN_DAP2FRCMISC] = "MOD_CLK_V5_EN_DAP2FRCMISC",
	[E_MOD_V5_EN_R2_FRC2FRCMISC] = "MOD_CLK_V5_EN_R2_FRC2FRCMISC",
	[E_MOD_V5_EN_XTAL_12M2FRCMISC] = "MOD_CLK_V5_EN_XTAL_12M2FRCMISC",
};

static const char *mod_v6_clks[E_MOD_V6_EN_NUM] = {
	[E_MOD_V6_EN_SMI2SCBE] = "MOD_CLK_V6_EN_SMI2SCBE",
	[E_MOD_V6_EN_XC_DIP02SCBE] = "MOD_CLK_V6_EN_XC_DIP02SCBE",
	[E_MOD_V6_EN_XC_DIP12SCBE] = "MOD_CLK_V6_EN_XC_DIP12SCBE",
	[E_MOD_V6_EN_SMI2SCIP] = "MOD_CLK_V6_EN_SMI2SCIP",
	[E_MOD_V6_EN_EN_XC_FN2XC_DC0_CG_SCIP] = "MOD_CLK_V6_EN_EN_XC_FN2XC_DC0_CG_SCIP",
	[E_MOD_V6_EN_SMI2SCTC] = "MOD_CLK_V6_EN_SMI2SCTC",
};

static const char *mod_v7_clks[E_MOD_V7_EN_NUM] = {
	[E_MOD_V7_EN_SMI2SCACE] = "MOD_CLK_V7_EN_SMI2SCACE",
	[E_MOD_V7_EN_SMI2SCACE_GALS] = "MOD_CLK_V7_EN_SMI2SCACE_GALS",
	//[E_MOD_V7_EN_XC_FN2SCACE] = "MOD_CLK_V7_EN_XC_FN2SCACE",
	[E_MOD_V7_EN_XC_IP_AUL_CLK_MERGE2SCACE_TMP] = "MOD_CLK_V7_EN_XC_IP_AUL_CLK_MERGE2SCACE_TMP",
	[E_MOD_V7_EN_XTAL_24M2SCACE] = "MOD_CLK_V7_EN_XTAL_24M2SCACE",
	[E_MOD_V7_EN_XTAL_24M2SCACE_MBIST] = "MOD_CLK_V7_EN_XTAL_24M2SCACE_MBIST",
	[E_MOD_V7_EN_SIDCLK_DP02SCIP] = "MOD_CLK_V7_EN_SIDCLK_DP02SCIP",
	[E_MOD_V7_EN_SIDCLK_DP12SCIP] = "MOD_CLK_V7_EN_SIDCLK_DP12SCIP",
	[E_MOD_V7_EN_SIDCLK_DSC2SCIP] = "MOD_CLK_V7_EN_SIDCLK_DSC2SCIP",
	[E_MOD_V7_EN_SIDCLK_HD02SCIP] = "MOD_CLK_V7_EN_SIDCLK_HD02SCIP",
	[E_MOD_V7_EN_SIDCLK_HD12SCIP] = "MOD_CLK_V7_EN_SIDCLK_HD12SCIP",
	[E_MOD_V7_EN_SIDCLK_HD22SCIP] = "MOD_CLK_V7_EN_SIDCLK_HD22SCIP",
	[E_MOD_V7_EN_SIDCLK_HD32SCIP] = "MOD_CLK_V7_EN_SIDCLK_HD32SCIP",
	[E_MOD_V7_EN_XC_ADC2SCIP] = "MOD_CLK_V7_EN_XC_ADC2SCIP",
	[E_MOD_V7_EN_XC_DBG2MIU_M2SCIP] = "MOD_CLK_V7_EN_XC_DBG2MIU_M2SCIP",
	[E_MOD_V7_EN_XC_DBG2MIU_S2SCIP] = "MOD_CLK_V7_EN_XC_DBG2MIU_S2SCIP",
	[E_MOD_V7_EN_XC_DP02SCIP] = "MOD_CLK_V7_EN_XC_DP02SCIP",
	[E_MOD_V7_EN_XC_DP12SCIP] = "MOD_CLK_V7_EN_XC_DP12SCIP",
	[E_MOD_V7_EN_XC_DSC2SCIP] = "MOD_CLK_V7_EN_XC_DSC2SCIP",
	//[E_MOD_V7_EN_XC_FN2SCIP] = "MOD_CLK_V7_EN_XC_FN2SCIP",
	[E_MOD_V7_EN_XC_FN2XC_DC0_CG_SCIP] = "MOD_CLK_V7_EN_XC_FN2XC_DC0_CG_SCIP",
	[E_MOD_V7_EN_XC_FN2XC_SUB_DC0_CG_SCIP] = "MOD_CLK_V7_EN_XC_FN2XC_SUB_DC0_CG_SCIP",
	[E_MOD_V7_EN_XC_FN2XC_SUB1_DC0_CG_SCIP] = "MOD_CLK_V7_EN_XC_FN2XC_SUB1_DC0_CG_SCIP",
	[E_MOD_V7_EN_XC_FN2XC_MFDEC_CG_SCIP] = "MOD_CLK_V7_EN_XC_FN2XC_MFDEC_CG_SCIP",
	[E_MOD_V7_EN_XC_GPU_MFDEC2SCIP] = "MOD_CLK_V7_EN_XC_GPU_MFDEC2SCIP",
	[E_MOD_V7_EN_XC_HDMI02SCIP] = "MOD_CLK_V7_EN_XC_HDMI02SCIP",
	[E_MOD_V7_EN_XC_HDMI12SCIP] = "MOD_CLK_V7_EN_XC_HDMI12SCIP",
	[E_MOD_V7_EN_XC_HDMI22SCIP] = "MOD_CLK_V7_EN_XC_HDMI22SCIP",
	[E_MOD_V7_EN_XC_HDMI32SCIP] = "MOD_CLK_V7_EN_XC_HDMI32SCIP",
	[E_MOD_V7_EN_XC_ID02SCIP] = "MOD_CLK_V7_EN_XC_ID02SCIP",
	[E_MOD_V7_EN_XC_ID12SCIP] = "MOD_CLK_V7_EN_XC_ID12SCIP",
	[E_MOD_V7_EN_XC_SC2FPLL2SCIP] = "MOD_CLK_V7_EN_XC_SC2FPLL2SCIP",
	[E_MOD_V7_EN_XC_SLOW2SCIP] = "MOD_CLK_V7_EN_XC_SLOW2SCIP",
	[E_MOD_V7_EN_XC_TGEN_WIN2SCIP] = "MOD_CLK_V7_EN_XC_TGEN_WIN2SCIP",
	[E_MOD_V7_EN_XC_VD2SCIP] = "MOD_CLK_V7_EN_XC_VD2SCIP",
	[E_MOD_V7_EN_XTAL_12M2SCIP] = "MOD_CLK_V7_EN_XTAL_12M2SCIP",
	[E_MOD_V7_EN_XTAL_24M2SCIP] = "MOD_CLK_V7_EN_XTAL_24M2SCIP",
	[E_MOD_V7_EN_XTAL_24M2SCIP_MBIST] = "MOD_CLK_V7_EN_XTAL_24M2SCIP_MBIST",
	[E_MOD_V7_EN_XTAL_IP12SCIP] = "MOD_CLK_V7_EN_XTAL_IP12SCIP",
	[E_MOD_V7_EN_FRC_FCLK_2XPLUS2SCMW] = "MOD_CLK_V7_EN_FRC_FCLK_2XPLUS2SCMW",
	[E_MOD_V7_EN_SMI2SCMW] = "MOD_CLK_V7_EN_SMI2SCMW",
	//[E_MOD_V7_EN_SMI2SCMW_GALS] = "MOD_CLK_V7_EN_SMI2SCMW_GALS",
	[E_MOD_V7_EN_XC_DIP02SCMW] = "MOD_CLK_V7_EN_XC_DIP02SCMW",
	[E_MOD_V7_EN_XC_DIP12SCMW] = "MOD_CLK_V7_EN_XC_DIP12SCMW",
	[E_MOD_V7_EN_XC_DIP22SCMW] = "MOD_CLK_V7_EN_XC_DIP22SCMW",
	//[E_MOD_V7_EN_XC_FN2SCMW] = "MOD_CLK_V7_EN_XC_FN2SCMW",
	[E_MOD_V7_EN_XC_OD_1P2SCMW] = "MOD_CLK_V7_EN_XC_OD_1P2SCMW",
	[E_MOD_V7_EN_XC_OD_B2P2SCMW] = "MOD_CLK_V7_EN_XC_OD_B2P2SCMW",
	[E_MOD_V7_EN_XTAL_12M2SCMW] = "MOD_CLK_V7_EN_XTAL_12M2SCMW",
	[E_MOD_V7_EN_XTAL_24M2SCMW] = "MOD_CLK_V7_EN_XTAL_24M2SCMW",
	[E_MOD_V7_EN_XTAL_24M2SCMW_MBIST] = "MOD_CLK_V7_EN_XTAL_24M2SCMW_MBIST",
	//[E_MOD_V7_EN_XC_FN2SCNR] = "MOD_CLK_V7_EN_XC_FN2SCNR",
	[E_MOD_V7_EN_XTAL_24M2SCNR] = "MOD_CLK_V7_EN_XTAL_24M2SCNR",
	[E_MOD_V7_EN_XTAL_24M2SCNR_MBIST] = "MOD_CLK_V7_EN_XTAL_24M2SCNR_MBIST",
	[E_MOD_V7_EN_MCU_NONPM2SCSR] = "MOD_CLK_V7_EN_MCU_NONPM2SCSR",
	[E_MOD_V7_EN_SMI2SCSR] = "MOD_CLK_V7_EN_SMI2SCSR",
	[E_MOD_V7_EN_XC_FN2SCSR] = "MOD_CLK_V7_EN_XC_FN2SCSR",
	[E_MOD_V7_EN_XTAL_24M2SCSR] = "MOD_CLK_V7_EN_XTAL_24M2SCSR",
	[E_MOD_V7_EN_XTAL_24M2SCSR_MBIST] = "MOD_CLK_V7_EN_XTAL_24M2SCSR_MBIST",
	[E_MOD_V7_EN_MCU_NONPM2SCTCON] = "MOD_CLK_V7_EN_MCU_NONPM2SCTCON",
	[E_MOD_V7_EN_SMI2SCTCON] = "MOD_CLK_V7_EN_SMI2SCTCON",
	[E_MOD_V7_EN_XC_FN2SCTCON] = "MOD_CLK_V7_EN_XC_FN2SCTCON",
	//[E_MOD_V7_EN_XC_GOP2SCTCON] = "MOD_CLK_V7_EN_XC_GOP2SCTCON",
	[E_MOD_V7_EN_XC_OD_1P2SCTCON] = "MOD_CLK_V7_EN_XC_OD_1P2SCTCON",
	//[E_MOD_V7_EN_XC_OD_B2P2SCTCON] = "MOD_CLK_V7_EN_XC_OD_B2P2SCTCON",
	[E_MOD_V7_EN_XC_OD2SCTCON] = "MOD_CLK_V7_EN_XC_OD2SCTCON",
	[E_MOD_V7_EN_XC_OD_META2SCTCON] = "MOD_CLK_V7_EN_XC_OD_META2SCTCON",
	[E_MOD_V7_EN_XC_OD_OSD_META2SCTCON] = "MOD_CLK_V7_EN_XC_OD_OSD_META2SCTCON",
	[E_MOD_V7_EN_XC_OD_OSD2SCTCON] = "MOD_CLK_V7_EN_XC_OD_OSD2SCTCON",
	[E_MOD_V7_EN_XTAL_24M2SCTCON] = "MOD_CLK_V7_EN_XTAL_24M2SCTCON",
	[E_MOD_V7_EN_XTAL_24M2SCTCON_MBIST] = "MOD_CLK_V7_EN_XTAL_24M2SCTCON_MBIST",
	[E_MOD_V7_EN_FRC_FCLK_2XPLUS2SCACE] = "MOD_CLK_V7_EN_FRC_FCLK_2XPLUS2SCACE",
};

struct clk *st_mod_clk_V1_en[E_MOD_V1_EN_NUM] = {0};
struct clk *st_mod_clk_V2_en[E_MOD_V2_EN_NUM] = {0};
struct clk *st_mod_clk_V3_en[E_MOD_V3_EN_NUM] = {0};
struct clk *st_mod_clk_V4_en[E_MOD_V4_EN_NUM] = {0};
struct clk *st_mod_clk_V5_en[E_MOD_V5_EN_NUM] = {0};
struct clk *st_mod_clk_V6_en[E_MOD_V6_EN_NUM] = {0};
struct clk *st_mod_clk_V7_en[E_MOD_V7_EN_NUM] = {0};

int mtk_mod_clk_initV1(struct device *dev)
{
	struct clk *clkv1 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V1_EN_NUM; u16modclkcount++) {
		clkv1 = devm_clk_get(dev, mod_v1_clks[u16modclkcount]);
		if (IS_ERR(clkv1)) {
			DRM_ERROR("[%s, %d]: mod init clk V1 unable to retrieve %s\n",
			__func__, __LINE__, mod_v1_clks[u16modclkcount]);
			//return -EINVAL;
		}
		st_mod_clk_V1_en[u16modclkcount] = clkv1;
		mtk_video_mod_enable_clkV1(true, u16modclkcount);
	}
	return 0;
}

int mtk_mod_clk_initV2(struct device *dev)
{
	struct clk *clkv2 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V2_EN_NUM; u16modclkcount++) {
		clkv2 = devm_clk_get(dev, mod_v2_clks[u16modclkcount]);
		if (IS_ERR(clkv2)) {
			DRM_ERROR("[%s, %d]: mod init clk V2 unable to retrieve %s\n",
			__func__, __LINE__, mod_v2_clks[u16modclkcount]);
			return -EINVAL;
		}
		st_mod_clk_V2_en[u16modclkcount] = clkv2;
		mtk_video_mod_enable_clkV2(true, u16modclkcount);
	}

	return 0;
}

int mtk_mod_clk_initV3(struct device *dev)
{
	struct clk *clkv3 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V3_EN_NUM; u16modclkcount++) {
		clkv3 = devm_clk_get(dev, mod_v3_clks[u16modclkcount]);
		if (IS_ERR(clkv3)) {
			DRM_ERROR("[%s, %d]: mod init clk V3 unable to retrieve %s\n",
			__func__, __LINE__, mod_v3_clks[u16modclkcount]);
			//return -EINVAL;
		}
		st_mod_clk_V3_en[u16modclkcount] = clkv3;
		mtk_video_mod_enable_clkV3(true, u16modclkcount);
	}

	return 0;
}

int mtk_mod_clk_initV4(struct device *dev)
{
	struct clk *clkv4 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V4_EN_NUM; u16modclkcount++) {
		clkv4 = devm_clk_get(dev, mod_v4_clks[u16modclkcount]);
		if (IS_ERR(clkv4)) {
			DRM_ERROR("[%s, %d]: mod init clk V4 unable to retrieve %s\n",
			__func__, __LINE__, mod_v4_clks[u16modclkcount]);
			return -EINVAL;
		}
		st_mod_clk_V4_en[u16modclkcount] = clkv4;
		mtk_video_mod_enable_clkV4(true, u16modclkcount);
	}

	return 0;
}

int mtk_mod_clk_initV5(struct device *dev)
{
	struct clk *clkv5 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V5_EN_NUM; u16modclkcount++) {
		clkv5 = devm_clk_get(dev, mod_v5_clks[u16modclkcount]);
		if (IS_ERR(clkv5)) {
			DRM_ERROR("[%s, %d]: mod init clk V5 unable to retrieve %s\n",
			__func__, __LINE__, mod_v5_clks[u16modclkcount]);
			return -EINVAL;
		}
		st_mod_clk_V5_en[u16modclkcount] = clkv5;
		mtk_video_mod_enable_clkV5(true, u16modclkcount);
	}

	return 0;
}

int mtk_mod_clk_initV6(struct device *dev)
{
	struct clk *clkv6 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V6_EN_NUM; u16modclkcount++) {
		clkv6 = devm_clk_get(dev, mod_v6_clks[u16modclkcount]);
		if (IS_ERR(clkv6)) {
			DRM_ERROR("[%s, %d]: mod init clk V6 unable to retrieve %s\n",
			__func__, __LINE__, mod_v6_clks[u16modclkcount]);
			return -EINVAL;
		}
		st_mod_clk_V6_en[u16modclkcount] = clkv6;
		mtk_video_mod_enable_clkV6(true, u16modclkcount);
	}

	return 0;
}

int mtk_mod_clk_initV7(struct device *dev)
{
	struct clk *clkv7 = NULL;
	__u16 u16modclkcount = 0;

	if (dev == NULL) {
		MOD_MSG_POINTER_CHECK();
		return -ENXIO;
	}

	for (u16modclkcount = 0; u16modclkcount < E_MOD_V7_EN_NUM; u16modclkcount++) {
		clkv7 = devm_clk_get(dev, mod_v7_clks[u16modclkcount]);
		if (IS_ERR(clkv7)) {
			DRM_ERROR("[%s, %d]: mod init clk V7 unable to retrieve %s\n",
			__func__, __LINE__, mod_v7_clks[u16modclkcount]);
			return -EINVAL;
		}
		st_mod_clk_V7_en[u16modclkcount] = clkv7;
		mtk_video_mod_enable_clkV7(true, u16modclkcount);
	}

	return 0;
}

int mtk_video_mod_enable_clkV1(bool bEn, EN_MOD_CLK_V1_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V1_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V1_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V1_en[enClkSel]);

	return ret;
}

int mtk_video_mod_enable_clkV2(bool bEn, EN_MOD_CLK_V2_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V2_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V2_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V2_en[enClkSel]);

	return ret;
}

int mtk_video_mod_enable_clkV3(bool bEn, EN_MOD_CLK_V3_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V3_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V3_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V3_en[enClkSel]);

	return ret;
}

int mtk_video_mod_enable_clkV4(bool bEn, EN_MOD_CLK_V4_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V4_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V4_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V4_en[enClkSel]);

	return ret;
}

int mtk_video_mod_enable_clkV5(bool bEn, EN_MOD_CLK_V5_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V5_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V5_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V5_en[enClkSel]);

	return ret;
}

int mtk_video_mod_enable_clkV6(bool bEn, EN_MOD_CLK_V6_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V6_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V6_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V6_en[enClkSel]);

	return ret;
}

int mtk_video_mod_enable_clkV7(bool bEn, enum EN_MOD_CLK_V7_EN enClkSel)
{
	int ret = 0;

	if ((enClkSel >= E_MOD_V7_EN_NUM) || (enClkSel < 0))
		return 0;

	if (bEn == true)
		ret = mtk_mod_enable_clock(st_mod_clk_V7_en[enClkSel]);
	else
		ret = mtk_mod_disable_clock(st_mod_clk_V7_en[enClkSel]);

	return ret;
}

int mtk_mod_enable_clock(struct clk *st_mod_clk_en)
{
	struct clk *clk = NULL;
	int res = 0;

	clk = st_mod_clk_en;
	res = clk_prepare_enable(clk);
	if (res)
		return -EINVAL;

	return 0;
}

int mtk_mod_disable_clock(struct clk *st_mod_clk_disable)
{
	struct clk *clk = NULL;

	clk = st_mod_clk_disable;
	clk_disable_unprepare(clk);

	return 0;
}
