/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 * Author Owen Tseng <Owen.Tseng@mediatek.com>
 */
#ifndef _SPI_MT5896_CODA_H_
#define _SPI_MT5896_CODA_H_

//Page MSPI0_1
#define SPI_REG_0000_MSPI0 (0x0000)
#define REG_MSPI_WD8 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD9 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0004_MSPI0 (0x0004)
#define REG_MSPI_WD10 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD11 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0008_MSPI0 (0x0008)
#define REG_MSPI_WD12 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD13 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_000C_MSPI0 (0x000C)
#define REG_MSPI_WD14 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD15 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0010_MSPI0 (0x0010)
#define REG_MSPI_WD16 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD17 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0014_MSPI0 (0x0014)
#define REG_MSPI_WD18 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD19 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0018_MSPI0 (0x0018)
#define REG_MSPI_WD20 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD21 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_001C_MSPI0 (0x001C)
#define REG_MSPI_WD22 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD23 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0020_MSPI0 (0x0020)
#define REG_MSPI_WD24 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD25 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0024_MSPI0 (0x0024)
#define REG_MSPI_WD26 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD27 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0028_MSPI0 (0x0028)
#define REG_MSPI_WD28 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD29 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_002C_MSPI0 (0x002C)
#define REG_MSPI_WD30 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD31 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0040_MSPI0 (0x0040)
#define REG_MSPI_RD8 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD9 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0044_MSPI0 (0x0044)
#define REG_MSPI_RD10 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD11 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0048_MSPI0 (0x0048)
#define REG_MSPI_RD12 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD13 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_004C_MSPI0 (0x004C)
#define REG_MSPI_RD14 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD15 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0050_MSPI0 (0x0050)
#define REG_MSPI_RD16 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD17 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0054_MSPI0 (0x0054)
#define REG_MSPI_RD18 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD19 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0058_MSPI0 (0x0058)
#define REG_MSPI_RD20 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD21 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_005C_MSPI0 (0x005C)
#define REG_MSPI_RD22 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD23 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0060_MSPI0 (0x0060)
#define REG_MSPI_RD24 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD25 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0064_MSPI0 (0x0064)
#define REG_MSPI_RD26 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD27 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0068_MSPI0 (0x0068)
#define REG_MSPI_RD28 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD29 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_006C_MSPI0 (0x006C)
#define REG_MSPI_RD30 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD31 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0080_MSPI0 (0x0080)
#define REG_MSPI_WD8_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD9_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD10_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD11_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0084_MSPI0 (0x0084)
#define REG_MSPI_WD12_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD13_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD14_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD15_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0088_MSPI0 (0x0088)
#define REG_MSPI_WD16_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD17_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD18_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD19_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_008C_MSPI0 (0x008C)
#define REG_MSPI_WD20_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD21_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD22_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD23_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0090_MSPI0 (0x0090)
#define REG_MSPI_WD24_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD25_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD26_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD27_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0094_MSPI0 (0x0094)
#define REG_MSPI_WD28_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD29_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD30_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD31_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00A0_MSPI0 (0x00A0)
#define REG_MSPI_RD8_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD9_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD10_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD11_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00A4_MSPI0 (0x00A4)
#define REG_MSPI_RD12_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD13_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD14_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD15_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00A8_MSPI0 (0x00A8)
#define REG_MSPI_RD16_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD17_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD18_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD19_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00AC_MSPI0 (0x00AC)
#define REG_MSPI_RD20_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD21_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD22_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD23_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00B0_MSPI0 (0x00B0)
#define REG_MSPI_RD24_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD25_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD26_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD27_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00B4_MSPI0 (0x00B4)
#define REG_MSPI_RD28_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD29_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD30_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD31_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_00C0_MSPI0 (0x00C0)
#define REG_DEV2MSPI_RDY Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_DEV2MSPI_RW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_MSPI2DEV_ACK Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_MSPI2DEV_RD_LAT Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_MSPI_STATE Fld(9, 7, AC_MSKW10)//[15:7]
#define SPI_REG_00C4_MSPI0 (0x00C4)
#define REG_DEV2MSPI_WD Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI2DEV_RD Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_00C8_MSPI0 (0x00C8)
#define REG_DMA_DEBUG_INFO_0 Fld(10, 0, AC_MSKW10)//[9:0]
#define SPI_REG_00CC_MSPI0 (0x00CC)
#define REG_DMA_DEBUG_INFO_1 Fld(10, 0, AC_MSKW10)//[9:0]
#define SPI_REG_00D0_MSPI0 (0x00D0)
#define REG_DMA_DEBUG_INFO_2 Fld(10, 0, AC_MSKW10)//[9:0]
#define SPI_REG_00D4_MSPI0 (0x00D4)
#define REG_DMA_DEBUG_INFO_3 Fld(10, 0, AC_MSKW10)//[9:0]
#define SPI_REG_00E0_MSPI0 (0x00E0)
#define REG_MSPI_CTRL2 Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_00E8_MSPI0 (0x00E8)
#define REG_DMA_BYTE_CNT_L Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_00EC_MSPI0 (0x00EC)
#define REG_DMA_BYTE_CNT_H Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_00F0_MSPI0 (0x00F0)
#define REG_DMA_TIMEOUT_EN Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_DMA_DBG_INFO_EN Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_MSPI_XTAL_RSTZ Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_DMA_TIMEOUT_FLAG Fld(1, 8, AC_MSKB1)//[8:8]
#define SPI_REG_00F4_MSPI0 (0x00F4)
#define REG_DMA_TARGET_TIMEOT_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_00F8_MSPI0 (0x00F8)
#define REG_DMA_CURRENT_TIMEOUT_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_0100_MSPI0 (0x0100)
#define REG_MSPI_WD0 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD1 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0104_MSPI0 (0x0104)
#define REG_MSPI_WD2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD3 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0108_MSPI0 (0x0108)
#define REG_MSPI_WD4 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD5 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_010C_MSPI0 (0x010C)
#define REG_MSPI_WD6 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_WD7 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0110_MSPI0 (0x0110)
#define REG_MSPI_RD0 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD1 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0114_MSPI0 (0x0114)
#define REG_MSPI_RD2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD3 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0118_MSPI0 (0x0118)
#define REG_MSPI_RD4 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD5 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_011C_MSPI0 (0x011C)
#define REG_MSPI_RD6 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_RD7 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0120_MSPI0 (0x0120)
#define REG_MSPI_WBF_SIZE Fld(6, 0, AC_MSKB0)//[5:0]
#define REG_MSPI_RBF_SIZE Fld(6, 8, AC_MSKB1)//[13:8]
#define SPI_REG_0124_MSPI0 (0x0124)
#define REG_MSPI_CTRL Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_CLOCK_RATE Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0128_MSPI0 (0x0128)
#define REG_TR_START_TIME Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_TR_END_TIME Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_012C_MSPI0 (0x012C)
#define REG_TBYTE_INTERVAL_TIME Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_RW_TURN_AROUND_TIME Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0130_MSPI0 (0x0130)
#define REG_MSPI_WD0_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD1_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD2_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD3_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0134_MSPI0 (0x0134)
#define REG_MSPI_WD4_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_WD5_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_WD6_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_WD7_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0138_MSPI0 (0x0138)
#define REG_MSPI_RD0_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD1_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD2_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD3_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_013C_MSPI0 (0x013C)
#define REG_MSPI_RD4_BIT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD5_BIT_SEL Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_MSPI_RD6_BIT_SEL Fld(3, 6, AC_MSKW10)//[8:6]
#define REG_MSPI_RD7_BIT_SEL Fld(3, 9, AC_MSKB1)//[11:9]
#define SPI_REG_0140_MSPI0 (0x0140)
#define REG_MSPI_DMA_TX_EN Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_MSPI_DMA_RX_EN Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_DMA_CS_SW_MODE Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_MSPI_ABORT_EN Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_MSPI_DMA_RSTZ Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_MSPI_DMA_TX_MULTI_BIT_SEL_EN Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_MSPI_DMA_RX_MULTI_BIT_SEL_EN Fld(1, 9, AC_MSKB1)//[9:9]
#define SPI_REG_0144_MSPI0 (0x0144)
#define REG_MSPI_WD_BIT_SEL_DMA Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_MSPI_RD_BIT_SEL_DMA Fld(3, 3, AC_MSKB0)//[5:3]
#define SPI_REG_0148_MSPI0 (0x0148)
#define REG_MSPI_DMA_TX_SIZE_L Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_014C_MSPI0 (0x014C)
#define REG_MSPI_DMA_TX_SIZE_H Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_0150_MSPI0 (0x0150)
#define REG_MSPI_DMA_RX_SIZE_L Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_0154_MSPI0 (0x0954)
#define REG_MSPI_DMA_RX_SIZE_H Fld(16, 0, AC_FULLW10)//[15:0]
#define SPI_REG_0168_MSPI0 (0x0168)
#define REG_MSPI_TRIGGER Fld(1, 0, AC_MSKB0)//[0:0]
#define SPI_REG_016C_MSPI0 (0x016C)
#define REG_MSPI_DONE_FLAG Fld(1, 0, AC_MSKB0)//[0:0]
#define SPI_REG_0170_MSPI0 (0x0170)
#define REG_MSPI_CLEAR_DONE_FLAG Fld(1, 0, AC_MSKB0)//[0:0]
#define SPI_REG_0174_MSPI0 (0x0174)
#define REG_SPI_WP_I Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_SPI_WP_OEN Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_SPI_WP_C Fld(1, 2, AC_MSKB0)//[2:2]
#define SPI_REG_0178_MSPI0 (0x0178)
#define REG_SPI_HOLD_I Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_SPI_HOLD_OEN Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_SPI_HOLD_C Fld(1, 2, AC_MSKB0)//[2:2]
#define SPI_REG_017C_MSPI0 (0x017C)
#define REG_CHIP_SELECT1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_CHIP_SELECT2 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_CHIP_SELECT3 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_CHIP_SELECT4 Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_CHIP_SELECT5 Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_CHIP_SELECT6 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_CHIP_SELECT7 Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_CHIP_SELECT8 Fld(1, 7, AC_MSKB0)//[7:7]
#define SPI_REG_0180_MSPI0 (0x0180)
#define REG_AUTO_CLR_DONE_FLAG1 Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_AUTO_CLR_DONE_FLAG2 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_GDMA_MODE Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_IN_DIFF_CLK_DOMAIN Fld(1, 7, AC_MSKB0)//[7:7]
#define SPI_REG_0190_MSPI0 (0x0190)
#define REG_CTRLER_CMD2_END_STATUS Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_CTRLER_CMD2_END_STATUS_MASK Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0194_MSPI0 (0x0194)
#define REG_CTRLER_CMD_LENGTH0 Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_CTRLER_CMD_LENGTH1 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_0198_MSPI0 (0x0198)
#define REG_CTRLER_CMD_LENGTH2 Fld(4, 0, AC_MSKB0)//[3:0]
#define SPI_REG_019C_MSPI0 (0x019C)
#define REG_CTRLER_CMD_ADDR_ADD_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_01A0_MSPI0 (0x01A0)
#define REG_CTRLER_CFG_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_CTRLER_CFG_1 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01A4_MSPI0 (0x01A4)
#define REG_CS_TIME_CNT_LENGTH_0_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_01C0_MSPI0 (0x01C0)
#define REG_CS_TIME_CNT_LENGTH_1_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_01C4_MSPI0 (0x01C4)
#define REG_CS_TIME_CNT_LENGTH_2_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_01C8_MSPI0 (0x01C8)
#define REG_CTRLER_ERROR_STATUS Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_CTRLER_ERROR_STATUS_MASK Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01CC_MSPI0 (0x01CC)
#define REG_DUMMY0 Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_01D0_MSPI0 (0x01D0)
#define REG_DBG_SIG_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_DBG_SIG_1 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01D8_MSPI0 (0x01D8)
#define REG_MSPI_CS_SPECIAL_MODE Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_CLK_NOT_GATED Fld(1, 8, AC_MSKB1)//[8:8]
#define SPI_REG_01DC_MSPI0 (0x01DC)
#define REG_MSPI_FULL_DEPLUX_RD_CNT Fld(8, 0, AC_FULLB0)//[7:0]
#define SPI_REG_01E0_MSPI0 (0x01E0)
#define REG_MSPI_FULL_DEPLUX_RD00 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD01 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01E4_MSPI0 (0x01E4)
#define REG_MSPI_FULL_DEPLUX_RD02 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD03 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01E8_MSPI0 (0x01E8)
#define REG_MSPI_FULL_DEPLUX_RD04 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD05 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01EC_MSPI0 (0x01EC)
#define REG_MSPI_FULL_DEPLUX_RD06 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD07 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01F0_MSPI0 (0x01F0)
#define REG_MSPI_FULL_DEPLUX_RD08 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD09 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01F4_MSPI0 (0x01F4)
#define REG_MSPI_FULL_DEPLUX_RD10 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD11 Fld(8, 8, AC_FULLB1)//[15:8]

//Page MSPI0_2
#define SPI_REG_01F8_MSPI0 (0x01F8)
#define REG_MSPI_FULL_DEPLUX_RD12 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD13 Fld(8, 8, AC_FULLB1)//[15:8]
#define SPI_REG_01FC_MSPI0 (0x01FC)
#define REG_MSPI_FULL_DEPLUX_RD14 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_MSPI_FULL_DEPLUX_RD15 Fld(8, 8, AC_FULLB1)//[15:8]

#endif
