/* SPDX-License-Identifier: BSD-2-Clause */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

/* [File]            : wf_wfdma_host_dma0.h */
/* [Revision time]   : Sun Jul  4 21:03:12 2021 */
/* [Description]     : This file is auto generated by CODA */
/*                     reserved. */

#ifndef __WF_WFDMA_HOST_DMA0_REGS_H__
#define __WF_WFDMA_HOST_DMA0_REGS_H__

#ifdef __cplusplus
extern "C" {
#endif


/* ************************************************************************** */
/*  */
/* WF_WFDMA_HOST_DMA0 CR Definitions */
/*  */
/* ************************************************************************** */

#define WF_WFDMA_HOST_DMA0_BASE   (0x18024000 + CONN_INFRA_REMAPPING_OFFSET)

#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x000) /* 4000 */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x004) /* 4004 */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x008) /* 4008 */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x00C) /* 400C */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_4_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x010) /* 4010 */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_5_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x014) /* 4014 */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_6_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x018) /* 4018 */
#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_START_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0B0) /* 40B0 */
#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_END_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0B8) /* 40B8 */
#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_START_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0C0) /* 40C0 */
#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_END_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0C8) /* 40C8 */
#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_START_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0D0) /* 40D0 */
#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_END_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0D8) /* 40D8 */
#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_START_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0E0) /* 40E0 */
#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_END_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x0E8) /* 40E8 */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x100) /* 4100 */
#define WF_WFDMA_HOST_DMA0_HOST2MCU_SW_INT_SET_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0X108) /* 4108 */
#define WF_WFDMA_HOST_DMA0_MCU2HOST_SW_INT_SET_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x10C) /* 410C */
#define WF_WFDMA_HOST_DMA0_MCU_INT_STA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0X110) /* 4110 */
#define WF_WFDMA_HOST_DMA0_MCU_INT_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0X114) /* 4114 */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x118) /* 4118 */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_EXT_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x11C) /* 411C */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DUMMY_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x120) /* 4120 */
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x124) /* 4124 */
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_PROBE_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x128) /* 4128 */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DBG_IDX_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x12C) /* 412C */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DBG_PROBE_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x130) /* 4130 */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DMASHDL_DBG_PROBE_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x134) /* 4134 */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_BUSY_STATUS_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x138) /* 4138 */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_BUSY_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x13c) /* 413C */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_FIFO_TEST_MOD_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x140) /* 4140 */
#define WF_WFDMA_HOST_DMA0_WPDMA2HOST_ERR_INT_STA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x1E8) /* 41E8 */
#define WF_WFDMA_HOST_DMA0_WPDMA2HOST_ERR_INT_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x1EC) /* 41EC */
#define WF_WFDMA_HOST_DMA0_MCU2HOST_SW_INT_STA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x1F0) /* 41F0 */
#define WF_WFDMA_HOST_DMA0_MCU2HOST_SW_INT_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x1F4) /* 41F4 */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x1F8) /* 41F8 */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x1FC) /* 41FC */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RST_DTX_PTR_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x20C) /* 420C */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_SET_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0X228) /* 4228 */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_CLR_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0X22C) /* 422C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TIMEOUT_CFG_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x230) /* 4230 */
#define WF_WFDMA_HOST_DMA0_WPDMA_MISC_CFG_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x234) /* 4234 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_WRR_ARB_GBF0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x240) /* 4240 */
#define WF_WFDMA_HOST_DMA0_MD_INT_STA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x250) /* 4250 */
#define WF_WFDMA_HOST_DMA0_MD_INT_ENA_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x254) /* 4254 */
#define WF_WFDMA_HOST_DMA0_MCU2MD_SW_INT_SET_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x258) /* 4258 */
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x25C) /* 425C */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RX_Q_TH10_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x260) /* 4260 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RX_Q_TH32_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x264) /* 4264 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RX_Q_TH54_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x268) /* 4268 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RX_Q_TH76_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x26C) /* 426C */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RX_Q_TH98_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x270) /* 4270 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RX_Q_TH1110_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x274) /* 4274 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PAUSE_RRO_Q_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x27C) /* 427C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RST_DRX_PTR_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x280) /* 4280 */
#define WF_WFDMA_HOST_DMA0_WPDMA_INFO_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x284) /* 4284 */
#define WF_WFDMA_HOST_DMA0_WPDMA_INFO_EXT_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x288) /* 4288 */
#define WF_WFDMA_HOST_DMA0_WPDMA_INT_RX_PRI_SEL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x298) /* 4298 */
#define WF_WFDMA_HOST_DMA0_WPDMA_INT_TX_PRI_SEL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x29C) /* 429C */
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_EXT0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2B0) /* 42B0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_EXT1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2B4) /* 42B4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_EXT2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2B8) /* 42B8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_CTXD_CFG_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2BC) /* 42BC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_QOS_QTM_CFG0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2D0) /* 42D0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_QOS_QTM_CFG1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2D4) /* 42D4 */
#define WF_WFDMA_HOST_DMA0_HOST_PER_DLY_INT_CFG_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2E8) /* 42E8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PRI_DLY_INT_CFG0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2F0) /* 42F0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PRI_DLY_INT_CFG1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2F4) /* 42F4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_PRI_DLY_INT_CFG2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x2F8) /* 42F8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING8_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x380) /* 4380 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING8_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x384) /* 4384 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING8_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x388) /* 4388 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING8_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x38c) /* 438C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING9_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x390) /* 4390 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING9_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x394) /* 4394 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING9_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x398) /* 4398 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING9_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x39c) /* 439C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING10_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3a0) /* 43A0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING10_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3a4) /* 43A4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING10_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3a8) /* 43A8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING10_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3ac) /* 43AC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING11_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3b0) /* 43B0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING11_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3b4) /* 43B4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING11_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3b8) /* 43B8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING11_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3bc) /* 43BC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING12_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3c0) /* 43C0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING12_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3c4) /* 43C4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING12_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3c8) /* 43C8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING12_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3cc) /* 43CC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING13_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3d0) /* 43D0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING13_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3d4) /* 43D4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING13_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3d8) /* 43D8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING13_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3dc) /* 43DC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING14_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3e0) /* 43E0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING14_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3e4) /* 43E4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING14_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3e8) /* 43E8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING14_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3ec) /* 43EC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING15_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3f0) /* 43F0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING15_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3f4) /* 43F4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING15_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3f8) /* 43F8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING15_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x3fc) /* 43FC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5a0) /* 45A0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5a4) /* 45A4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5a8) /* 45A8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5ac) /* 45AC */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5b0) /* 45B0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5b4) /* 45B4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5b8) /* 45B8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL3_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x5bc) /* 45BC */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x600) /* 4600 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x604) /* 4604 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x608) /* 4608 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x60C) /* 460C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x610) /* 4610 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x614) /* 4614 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x618) /* 4618 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING8_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x620) /* 4620 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING9_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x624) /* 4624 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING10_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x628) /* 4628 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING11_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x62C) /* 462C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING12_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x630) /* 4630 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING13_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x634) /* 4634 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING14_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x638) /* 4638 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING15_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x63C) /* 463C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x640) /* 4640 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x644) /* 4644 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x648) /* 4648 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x64C) /* 464C */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x650) /* 4650 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x654) /* 4654 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x680) /* 4680 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x684) /* 4684 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x688) /* 4688 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x68C) /* 468C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x690) /* 4690 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x694) /* 4694 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x698) /* 4698 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x69C) /* 469C */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x6A0) /* 46A0 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x6A4) /* 46A4 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x6A8) /* 46A8 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_EXT_CTRL_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x6AC) /* 46AC */
#define WF_WFDMA_HOST_DMA0_BN0_CTXD_RNG0_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x940) /* 4940 */
#define WF_WFDMA_HOST_DMA0_BN0_CTXD_RNG1_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x944) /* 4944 */
#define WF_WFDMA_HOST_DMA0_BN0_CTXD_RNG2_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x948) /* 4948 */
#define WF_WFDMA_HOST_DMA0_BN0_CTXD_RNG3_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x94C) /* 494C */
#define WF_WFDMA_HOST_DMA0_BN1_CTXD_RNG0_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x950) /* 4950 */
#define WF_WFDMA_HOST_DMA0_BN1_CTXD_RNG1_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x954) /* 4954 */
#define WF_WFDMA_HOST_DMA0_BN1_CTXD_RNG2_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x958) /* 4958 */
#define WF_WFDMA_HOST_DMA0_BN1_CTXD_RNG3_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x95C) /* 495C */
#define WF_WFDMA_HOST_DMA0_BN2_CTXD_RNG0_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x960) /* 4960 */
#define WF_WFDMA_HOST_DMA0_BN2_CTXD_RNG1_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x964) /* 4964 */
#define WF_WFDMA_HOST_DMA0_BN2_CTXD_RNG2_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x968) /* 4968 */
#define WF_WFDMA_HOST_DMA0_BN2_CTXD_RNG3_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x96C) /* 496C */
#define WF_WFDMA_HOST_DMA0_WPDMA_CTXD_PAD_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0x980) /* 4980 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB00) /* 4B00 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB04) /* 4B04 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB08) /* 4B08 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB10) /* 4B10 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB14) /* 4B14 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB18) /* 4B18 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB20) /* 4B20 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB24) /* 4B24 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB28) /* 4B28 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB30) /* 4B30 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB34) /* 4B34 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB38) /* 4B38 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB40) /* 4B40 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB44) /* 4B44 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB48) /* 4B48 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB50) /* 4B50 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB54) /* 4B54 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xB58) /* 4B58 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC00) /* 4C00 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC04) /* 4C04 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC08) /* 4C08 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC10) /* 4C10 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC14) /* 4C14 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC18) /* 4C18 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC20) /* 4C20 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC24) /* 4C24 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC28) /* 4C28 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC30) /* 4C30 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC34) /* 4C34 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC38) /* 4C38 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC40) /* 4C40 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC44) /* 4C44 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC48) /* 4C48 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC50) /* 4C50 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC54) /* 4C54 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC58) /* 4C58 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC60) /* 4C60 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC64) /* 4C64 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC68) /* 4C68 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_BKRS_CTRL0_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC70) /* 4C70 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_BKRS_CTRL1_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC74) /* 4C74 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_BKRS_CTRL2_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xC78) /* 4C78 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD00) /* 4D00 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD04) /* 4D04 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD10) /* 4D10 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD14) /* 4D14 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD20) /* 4D20 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD24) /* 4D24 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD30) /* 4D30 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD34) /* 4D34 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD40) /* 4D40 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD44) /* 4D44 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD50) /* 4D50 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD54) /* 4D54 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD60) /* 4D60 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xD64) /* 4D64 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE00) /* 4E00 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE04) /* 4E04 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE10) /* 4E10 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE14) /* 4E14 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE20) /* 4E20 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE24) /* 4E24 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE30) /* 4E30 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE34) /* 4E34 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE40) /* 4E40 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE44) /* 4E44 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE50) /* 4E50 */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xE54) /* 4E54 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF00) /* 4F00 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF04) /* 4F04 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF10) /* 4F10 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF14) /* 4F14 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF20) /* 4F20 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF24) /* 4F24 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF30) /* 4F30 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF34) /* 4F34 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF40) /* 4F40 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF44) /* 4F44 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF50) /* 4F50 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF54) /* 4F54 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF60) /* 4F60 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF64) /* 4F64 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_DMAD_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF70) /* 4F70 */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_PKT_MIB_ADDR \
	(WF_WFDMA_HOST_DMA0_BASE + 0xF74) /* 4F74 */





#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_0_TX_PAYLOAD_LEN0_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_0_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_0_TX_PAYLOAD_LEN0_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN0[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_0_TX_PAYLOAD_LEN0_SHFT 0


#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_1_TX_PAYLOAD_LEN1_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_1_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_1_TX_PAYLOAD_LEN1_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN1[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_1_TX_PAYLOAD_LEN1_SHFT 0


#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_2_TX_PAYLOAD_LEN2_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_2_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_2_TX_PAYLOAD_LEN2_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN2[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_2_TX_PAYLOAD_LEN2_SHFT 0


#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_3_TX_PAYLOAD_LEN3_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_3_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_3_TX_PAYLOAD_LEN3_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN3[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_3_TX_PAYLOAD_LEN3_SHFT 0


#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_4_TX_PAYLOAD_LEN4_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_4_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_4_TX_PAYLOAD_LEN4_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN4[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_4_TX_PAYLOAD_LEN4_SHFT 0


#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_5_TX_PAYLOAD_LEN5_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_5_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_5_TX_PAYLOAD_LEN5_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN5[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_5_TX_PAYLOAD_LEN5_SHFT 0


#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_6_TX_PAYLOAD_LEN6_ADDR \
	WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_6_ADDR
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_6_TX_PAYLOAD_LEN6_MASK 0xFFFFFFFF
	/* TX_PAYLOAD_LEN6[31..0] */
#define WF_WFDMA_HOST_DMA0_CBTOP_TXDMAD_6_TX_PAYLOAD_LEN6_SHFT 0


#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_START_tx_dmad_rng_start_ADDR \
	WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_START_ADDR
#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_START_tx_dmad_rng_start_MASK 0xFFFFFFFF
	/* tx_dmad_rng_start[31..0] */
#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_START_tx_dmad_rng_start_SHFT 0


#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_END_tx_dmad_rng_end_ADDR \
	WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_END_ADDR
#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_END_tx_dmad_rng_end_MASK 0xFFFFFFFF
	/* tx_dmad_rng_end[31..0] */
#define WF_WFDMA_HOST_DMA0_TX_DMAD_RNG_END_tx_dmad_rng_end_SHFT 0


#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_START_rx_dmad_rng_start_ADDR \
	WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_START_ADDR
#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_START_rx_dmad_rng_start_MASK 0xFFFFFFFF
	/* rx_dmad_rng_start[31..0] */
#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_START_rx_dmad_rng_start_SHFT 0


#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_END_rx_dmad_rng_end_ADDR \
	WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_END_ADDR
#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_END_rx_dmad_rng_end_MASK 0xFFFFFFFF
	/* rx_dmad_rng_end[31..0] */
#define WF_WFDMA_HOST_DMA0_RX_DMAD_RNG_END_rx_dmad_rng_end_SHFT 0


#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_START_tx_pld_rng_start_ADDR \
	WF_WFDMA_HOST_DMA0_TX_PLD_RNG_START_ADDR
#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_START_tx_pld_rng_start_MASK 0xFFFFFFFF
	/* tx_pld_rng_start[31..0] */
#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_START_tx_pld_rng_start_SHFT 0


#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_END_tx_pld_rng_end_ADDR \
	WF_WFDMA_HOST_DMA0_TX_PLD_RNG_END_ADDR
#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_END_tx_pld_rng_end_MASK  0xFFFFFFFF
	/* tx_pld_rng_end[31..0] */
#define WF_WFDMA_HOST_DMA0_TX_PLD_RNG_END_tx_pld_rng_end_SHFT  0


#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_START_rx_pld_rng_start_ADDR \
	WF_WFDMA_HOST_DMA0_RX_PLD_RNG_START_ADDR
#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_START_rx_pld_rng_start_MASK 0xFFFFFFFF
	/* rx_pld_rng_start[31..0] */
#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_START_rx_pld_rng_start_SHFT 0


#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_END_rx_pld_rng_end_ADDR \
	WF_WFDMA_HOST_DMA0_RX_PLD_RNG_END_ADDR
#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_END_rx_pld_rng_end_MASK  0xFFFFFFFF
	/* rx_pld_rng_end[31..0] */
#define WF_WFDMA_HOST_DMA0_RX_PLD_RNG_END_rx_pld_rng_end_SHFT  0


#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_dmashdl_all_rst_n_ADDR \
	WF_WFDMA_HOST_DMA0_CONN_HIF_RST_ADDR
#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_dmashdl_all_rst_n_MASK 0x00000020
	/* dmashdl_all_rst_n[5] */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_dmashdl_all_rst_n_SHFT 5
#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_conn_hif_logic_rst_n_ADDR \
	WF_WFDMA_HOST_DMA0_CONN_HIF_RST_ADDR
#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_conn_hif_logic_rst_n_MASK 0x00000010
	/* conn_hif_logic_rst_n[4] */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_RST_conn_hif_logic_rst_n_SHFT 4


#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_19_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_19_MASK 0x00002000
	/* tx_done_int_sts_19[13] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_19_SHFT 13
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_11_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_11_MASK 0x00000800
	/* rx_done_int_sts_11[11] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_11_SHFT 11
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_10_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_10_MASK 0x00000400
	/* rx_done_int_sts_10[10] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_10_SHFT 10
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_9_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_9_MASK 0x00000200
	/* rx_done_int_sts_9[9] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_9_SHFT 9
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_8_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_8_MASK 0x00000100
	/* rx_done_int_sts_8[8] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_rx_done_int_sts_8_SHFT 8
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_14_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_14_MASK 0x00000080
	/* tx_done_int_sts_14[7] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_14_SHFT 7
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_13_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_13_MASK 0x00000040
	/* tx_done_int_sts_13[6] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_13_SHFT 6
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_12_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_12_MASK 0x00000020
	/* tx_done_int_sts_12[5] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_12_SHFT 5
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_11_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_11_MASK 0x00000010
	/* tx_done_int_sts_11[4] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_11_SHFT 4
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_10_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_10_MASK 0x00000008
	/* tx_done_int_sts_10[3] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_10_SHFT 3
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_9_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_9_MASK 0x00000004
	/* tx_done_int_sts_9[2] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_9_SHFT 2
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_8_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_8_MASK 0x00000002
	/* tx_done_int_sts_8[1] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_8_SHFT 1
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_7_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_7_MASK 0x00000001
	/* tx_done_int_sts_7[0] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_EXT_tx_done_int_sts_7_SHFT 0


#define WF_WFDMA_HOST_DMA0_CONN_HIF_DUMMY_CONN_HIF_DUMMY_ADDR \
	WF_WFDMA_HOST_DMA0_CONN_HIF_DUMMY_ADDR
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DUMMY_CONN_HIF_DUMMY_MASK  0xFFFFFFFF
	/* CONN_HIF_DUMMY[31..0] */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DUMMY_CONN_HIF_DUMMY_SHFT  0


#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_PDMA_DBG_Enable_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_PDMA_DBG_Enable_MASK  0x00000100
	/* PDMA_DBG_Enable[8] */
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_PDMA_DBG_Enable_SHFT  8
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_PDMA_DBG_IDX_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_PDMA_DBG_IDX_MASK     0x000000FF
	/* PDMA_DBG_IDX[7..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_IDX_PDMA_DBG_IDX_SHFT     0


#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_PROBE_PDMA_DBG_PROBE_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_DBG_PROBE_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_PROBE_PDMA_DBG_PROBE_MASK 0xFFFFFFFF
	/* PDMA_DBG_PROBE[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_DBG_PROBE_PDMA_DBG_PROBE_SHFT 0

#define WF_WFDMA_HOST_DMA0_CONN_HIF_DBG_PROBE_conn_hif_dbg_probe_ADDR \
	WF_WFDMA_HOST_DMA0_CONN_HIF_DBG_PROBE_ADDR
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DBG_PROBE_conn_hif_dbg_probe_MASK 0xFFFFFFFF
	/* conn_hif_dbg_probe[31..0] */
#define WF_WFDMA_HOST_DMA0_CONN_HIF_DBG_PROBE_conn_hif_dbg_probe_SHFT 0


#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_wf_rro_irq_sts_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_wf_rro_irq_sts_MASK 0x00200000
	/* wf_rro_irq_sts[21] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_wf_rro_irq_sts_SHFT 21
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_9_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_9_MASK 0x00008000
	/* mac_int_sts_9[15] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_9_SHFT 15
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_8_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_8_MASK 0x00004000
	/* mac_int_sts_8[14] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_8_SHFT 14
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_7_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_7_MASK 0x00002000
	/* mac_int_sts_7[13] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_7_SHFT 13
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_6_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_6_MASK 0x00001000
	/* mac_int_sts_6[12] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_6_SHFT 12
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_5_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_5_MASK 0x00000800
	/* mac_int_sts_5[11] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_5_SHFT 11
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_dmashdl_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_dmashdl_int_sts_MASK 0x00000400
	/* dmashdl_int_sts[10] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_dmashdl_int_sts_SHFT 10
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_conn2ap_sw_irq_sts_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_conn2ap_sw_irq_sts_MASK \
	0x00000200 /* conn2ap_sw_irq_sts[9] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_conn2ap_sw_irq_sts_SHFT 9
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_conn_hif_on_host_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_conn_hif_on_host_int_sts_MASK \
	0x00000100 /* conn_hif_on_host_int_sts[8] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_conn_hif_on_host_int_sts_SHFT 8
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_4_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_4_MASK 0x00000010
	/* mac_int_sts_4[4] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_4_SHFT 4
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_3_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_3_MASK 0x00000008
	/* mac_int_sts_3[3] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_3_SHFT 3
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_2_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_2_MASK 0x00000004
	/* mac_int_sts_2[2] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_2_SHFT 2
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_1_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_1_MASK 0x00000002
	/* mac_int_sts_1[1] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_1_SHFT 1
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_0_ADDR \
	WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_0_MASK 0x00000001
	/* mac_int_sts_0[0] */
#define WF_WFDMA_HOST_DMA0_SUBSYS2HOST_INT_STA_mac_int_sts_0_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_PKT_MIB_PKT_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_DMAD_MIB_DMAD_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_DMAD_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_DMAD_MIB_DMAD_MIB_MASK 0xFFFFFFFF
	/* DMAD_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_DMAD_MIB_DMAD_MIB_SHFT 0


#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_PKT_MIB_PKT_MIB_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_PKT_MIB_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_PKT_MIB_PKT_MIB_MASK 0xFFFFFFFF
	/* PKT_MIB[31..0] */
#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_PKT_MIB_PKT_MIB_SHFT 0

#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA11_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA11_MASK 0x00080000
	/* HOST_RX_DONE_INT_ENA11[19] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA11_SHFT 19
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA10_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA10_MASK 0x00040000
	/* HOST_RX_DONE_INT_ENA10[18] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA10_SHFT 18
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA9_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA9_MASK 0x00020000
	/* HOST_RX_DONE_INT_ENA9[17] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA9_SHFT 17
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA8_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA8_MASK 0x00010000
	/* HOST_RX_DONE_INT_ENA8[16] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA8_SHFT 16
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA7_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA7_MASK 0x00008000
	/* HOST_RX_DONE_INT_ENA7[15] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA7_SHFT 15
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA6_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA6_MASK 0x00004000
	/* HOST_RX_DONE_INT_ENA6[14] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA6_SHFT 14
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA5_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA5_MASK 0x00002000
	/* HOST_RX_DONE_INT_ENA5[13] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA5_SHFT 13
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA4_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA4_MASK 0x00001000
	/* HOST_RX_DONE_INT_ENA4[12] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA4_SHFT 12
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA5_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA5_MASK 0x00000200
	/* HOST_TX_DONE_INT_ENA5[9] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA5_SHFT 9
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA4_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA4_MASK 0x00000100
	/* HOST_TX_DONE_INT_ENA4[8] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA4_SHFT 8
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA3_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA3_MASK 0x00000080
	/* HOST_TX_DONE_INT_ENA3[7] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA3_SHFT 7
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA2_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA2_MASK 0x00000040
	/* HOST_TX_DONE_INT_ENA2[6] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA2_SHFT 6
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA1_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA1_MASK 0x00000020
	/* HOST_TX_DONE_INT_ENA1[5] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA1_SHFT 5
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA0_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA0_MASK 0x00000010
	/* HOST_TX_DONE_INT_ENA0[4] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA0_SHFT 4
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA3_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA3_MASK 0x00000008
	/* HOST_RX_DONE_INT_ENA3[3] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA3_SHFT 3
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA2_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA2_MASK 0x00000004
	/* HOST_RX_DONE_INT_ENA2[2] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA2_SHFT 2
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA1_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA1_MASK 0x00000002
	/* HOST_RX_DONE_INT_ENA1[1] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA1_SHFT 1
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA0_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA0_MASK 0x00000001
	/* HOST_RX_DONE_INT_ENA0[0] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA0_SHFT 0

#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA19_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA19_MASK 0x80000000
	/* HOST_TX_DONE_INT_ENA19[31] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA19_SHFT 31
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA18_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA18_MASK 0x40000000
	/* HOST_TX_DONE_INT_ENA18[30] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA18_SHFT 30
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_mcu2host_sw_int_ena_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_mcu2host_sw_int_ena_MASK 0x20000000
	/* mcu2host_sw_int_ena[29] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_mcu2host_sw_int_ena_SHFT 29
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_subsys_int_ena_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_subsys_int_ena_MASK    0x10000000
	/* subsys_int_ena[28] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_subsys_int_ena_SHFT    28
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA17_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA17_MASK 0x08000000
	/* HOST_TX_DONE_INT_ENA17[27] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA17_SHFT 27
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA16_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA16_MASK 0x04000000
	/* HOST_TX_DONE_INT_ENA16[26] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA16_SHFT 26
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA15_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA15_MASK 0x02000000
	/* HOST_TX_DONE_INT_ENA15[25] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA15_SHFT 25
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_wpdma2host_err_int_ena_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_wpdma2host_err_int_ena_MASK 0x01000000
	/* wpdma2host_err_int_ena[24] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_wpdma2host_err_int_ena_SHFT 24
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_COHERENT_EN_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_COHERENT_EN_MASK 0x00200000
	/* HOST_TX_COHERENT_EN[21] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_COHERENT_EN_SHFT 21
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_COHERENT_EN_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_COHERENT_EN_MASK 0x00100000
	/* HOST_RX_COHERENT_EN[20] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_COHERENT_EN_SHFT 20
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA11_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA11_MASK 0x00080000
	/* HOST_RX_DONE_INT_ENA11[19] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA11_SHFT 19
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA10_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA10_MASK 0x00040000
	/* HOST_RX_DONE_INT_ENA10[18] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA10_SHFT 18
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA9_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA9_MASK 0x00020000
	/* HOST_RX_DONE_INT_ENA9[17] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA9_SHFT 17
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA8_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA8_MASK 0x00010000
	/* HOST_RX_DONE_INT_ENA8[16] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA8_SHFT 16
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA7_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA7_MASK 0x00008000
	/* HOST_RX_DONE_INT_ENA7[15] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA7_SHFT 15
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA6_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA6_MASK 0x00004000
	/* HOST_RX_DONE_INT_ENA6[14] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA6_SHFT 14
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA5_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA5_MASK 0x00002000
	/* HOST_RX_DONE_INT_ENA5[13] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA5_SHFT 13
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA4_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA4_MASK 0x00001000
	/* HOST_RX_DONE_INT_ENA4[12] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA4_SHFT 12
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA5_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA5_MASK 0x00000200
	/* HOST_TX_DONE_INT_ENA5[9] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA5_SHFT 9
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA4_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA4_MASK 0x00000100
	/* HOST_TX_DONE_INT_ENA4[8] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA4_SHFT 8
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA3_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA3_MASK 0x00000080
	/* HOST_TX_DONE_INT_ENA3[7] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA3_SHFT 7
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA2_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA2_MASK 0x00000040
	/* HOST_TX_DONE_INT_ENA2[6] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA2_SHFT 6
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA1_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA1_MASK 0x00000020
	/* HOST_TX_DONE_INT_ENA1[5] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA1_SHFT 5
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA0_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA0_MASK 0x00000010
	/* HOST_TX_DONE_INT_ENA0[4] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_TX_DONE_INT_ENA0_SHFT 4
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA3_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA3_MASK 0x00000008
	/* HOST_RX_DONE_INT_ENA3[3] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA3_SHFT 3
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA2_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA2_MASK 0x00000004
	/* HOST_RX_DONE_INT_ENA2[2] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA2_SHFT 2
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA1_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA1_MASK 0x00000002
	/* HOST_RX_DONE_INT_ENA1[1] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA1_SHFT 1
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA0_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA0_MASK 0x00000001
	/* HOST_RX_DONE_INT_ENA0[0] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_HOST_RX_DONE_INT_ENA0_SHFT 0

#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_19_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_19_MASK 0x80000000
	/* tx_done_int_sts_19[31] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_19_SHFT 31
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_18_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_18_MASK 0x40000000
	/* tx_done_int_sts_18[30] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_18_SHFT 30
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_mcu2host_sw_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_mcu2host_sw_int_sts_MASK 0x20000000
	/* mcu2host_sw_int_sts[29] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_mcu2host_sw_int_sts_SHFT 29
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_subsys_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_subsys_int_sts_MASK    0x10000000
	/* subsys_int_sts[28] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_subsys_int_sts_SHFT    28
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_17_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_17_MASK 0x08000000
	/* tx_done_int_sts_17[27] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_17_SHFT 27
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_16_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_16_MASK 0x04000000
	/* tx_done_int_sts_16[26] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_16_SHFT 26
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_15_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_15_MASK 0x02000000
	/* tx_done_int_sts_15[25] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_15_SHFT 25
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_wpdma2host_err_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_wpdma2host_err_int_sts_MASK 0x01000000
	/* wpdma2host_err_int_sts[24] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_wpdma2host_err_int_sts_SHFT 24
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_coherent_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_coherent_int_sts_MASK 0x00200000
	/* tx_coherent_int_sts[21] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_coherent_int_sts_SHFT 21
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_coherent_int_sts_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_coherent_int_sts_MASK 0x00100000
	/* rx_coherent_int_sts[20] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_coherent_int_sts_SHFT 20
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_11_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_11_MASK 0x00080000
	/* rx_done_int_sts_11[19] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_11_SHFT 19
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_10_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_10_MASK 0x00040000
	/* rx_done_int_sts_10[18] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_10_SHFT 18
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_9_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_9_MASK 0x00020000
	/* rx_done_int_sts_9[17] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_9_SHFT 17
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_8_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_8_MASK 0x00010000
	/* rx_done_int_sts_8[16] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_8_SHFT 16
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_7_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_7_MASK 0x00008000
	/* rx_done_int_sts_7[15] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_7_SHFT 15
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_6_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_6_MASK 0x00004000
	/* rx_done_int_sts_6[14] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_6_SHFT 14
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_5_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_5_MASK 0x00002000
	/* rx_done_int_sts_5[13] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_5_SHFT 13
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_4_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_4_MASK 0x00001000
	/* rx_done_int_sts_4[12] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_4_SHFT 12
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_5_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_5_MASK 0x00000200
	/* tx_done_int_sts_5[9] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_5_SHFT 9
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_4_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_4_MASK 0x00000100
	/* tx_done_int_sts_4[8] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_4_SHFT 8
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_3_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_3_MASK 0x00000080
	/* tx_done_int_sts_3[7] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_3_SHFT 7
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_2_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_2_MASK 0x00000040
	/* tx_done_int_sts_2[6] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_2_SHFT 6
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_1_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_1_MASK 0x00000020
	/* tx_done_int_sts_1[5] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_1_SHFT 5
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_0_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_0_MASK 0x00000010
	/* tx_done_int_sts_0[4] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_tx_done_int_sts_0_SHFT 4
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_3_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_3_MASK 0x00000008
	/* rx_done_int_sts_3[3] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_3_SHFT 3
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_2_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_2_MASK 0x00000004
	/* rx_done_int_sts_2[2] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_2_SHFT 2
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_1_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_1_MASK 0x00000002
	/* rx_done_int_sts_1[1] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_1_SHFT 1
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_0_ADDR \
	WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_0_MASK 0x00000001
	/* rx_done_int_sts_0[0] */
#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_rx_done_int_sts_0_SHFT 0

#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN_ADDR \
	WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN_MASK \
	0x00008000 /* CSR_DISP_BASE_PTR_CHAIN_EN[15] */
#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN_SHFT 15

#ifdef __cplusplus
}
#endif

#endif
	/* __WF_WFDMA_HOST_DMA0_REGS_H__ */
