// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
 *
 * Copyright(C) 2023 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


#include "mali_kbase_platform_mtk_dtv.h"

#ifdef MTK_DTV_DEVICE_TREE_PROBE
extern ptrdiff_t pm_top_vaddr;
extern ptrdiff_t X32_GPU_DIE_vaddr;
extern ptrdiff_t X32_IOMMU_BYPASS_TABLE0_GPU_vaddr;
extern ptrdiff_t X32_IOMMU_BYPASS_TABLE1_GPU_vaddr;
extern ptrdiff_t gpu2miu_mask_vaddr;
extern ptrdiff_t X32_IOMMU_LOCAL_GPU_vaddr;
extern ptrdiff_t X32_GPU_vaddr;
extern ptrdiff_t gpu_ror_w_vaddr;
extern ptrdiff_t gpu_ror_r_vaddr;
extern ptrdiff_t armpll_vaddr;
extern ptrdiff_t CKGEN00_vaddr;
extern ptrdiff_t CKGEN01_vaddr;
extern ptrdiff_t SRAM_PD_vaddr;
extern ptrdiff_t IOMMU_GLOBAL_vaddr;
extern ptrdiff_t MFDEC_BKA415_vaddr;
#if defined(CONFIG_MALI_DEBUG)
extern ptrdiff_t cpu_vaddr;
#endif
extern ptrdiff_t X32_MIU_vaddr;
extern ptrdiff_t efuse0_vaddr;
#ifdef MTK_DTV_GPU_THERMAL
extern ptrdiff_t pm_misc_vaddr;
#endif
extern ptrdiff_t GPU_GALS_vaddr;
#endif

/* Marcos to convert Mali frequency to register value */
#define MHZ_TO_REG(MHZ) (0x143fffc28/(MHZ))

/* Registers */
DEFINE_REG_BANK(pm_top, 0x10800);
DEFINE_REG_BANK(tzpc_aid_0, 0x120300);
DEFINE_REG_BANK(GPUBRDGPLL, 0x100700); // Added for m6e3
DEFINE_REG_BANK(armpll, 0x100e00);
DEFINE_REG_BANK(CKGEN00, 0x102000);
DEFINE_REG_BANK(CKGEN01, 0x103000);
DEFINE_REG_BANK(gpu2miu_mask, 0x2ee300);
DEFINE_REG_BANK(SRAM_PD, 0x110000);
DEFINE_REG_BANK(X32_GPU_DIE, 0x2ee000);
DEFINE_REG_BANK(X32_GPU, 0x2ee900);
DEFINE_REG_BANK(gpu_ror_w, 0x2eeb00);
DEFINE_REG_BANK(gpu_ror_r, 0x2eec00);
DEFINE_REG_BANK(efuse0, 0x012900);

#ifdef MTK_DTV_GPU_THERMAL
/* All software reset */
DEFINE_REG_BANK(pm_misc, 0x10900);
DEFINE_REG(pm_misc, all_reset, 0x2e, 0, 15);
#endif

DEFINE_REG_BANK(GPU_GALS, 0x19f000);

DEFINE_REG(GPU_GALS, slpprot_en_gpu02ip_MST, 0xe, 9, 9);
DEFINE_REG(GPU_GALS, slpprot_en_gpu02ip_SLV, 0xe, 11, 11);
DEFINE_REG(GPU_GALS, slpprot_en_gpu12ip_MST, 0xe, 13, 13);
DEFINE_REG(GPU_GALS, slpprot_en_gpu12ip_SLV, 0xe, 15, 15);
DEFINE_REG(GPU_GALS, slpprot_en_gpu22ip_MST, 0xf, 1, 1);
DEFINE_REG(GPU_GALS, slpprot_en_gpu22ip_SLV, 0xf, 3, 3);
DEFINE_REG(GPU_GALS, slpprot_en_gpu2ssc7_MST, 0xf, 5, 5);
DEFINE_REG(GPU_GALS, slpprot_en_gpu2ssc7_SLV, 0xf, 7, 7);

DEFINE_REG(GPU_GALS, slpprot_rdy_gpu02ip_MST, 0x14, 10, 10);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu02ip_SLV, 0x14, 11, 11);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu12ip_MST, 0x14, 12, 12);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu12ip_SLV, 0x14, 13, 13);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu22ip_MST, 0x14, 14, 14);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu22ip_SLV, 0x14, 15, 15);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu2ssc7_MST, 0x15, 0, 0);
DEFINE_REG(GPU_GALS, slpprot_rdy_gpu2ssc7_SLV, 0x15, 1, 1);

DEFINE_REG(pm_top, chip_id, 0x0, 0, 15); // Chip ID: 0x0101
DEFINE_REG(pm_top, chip_version, 0x1, 0, 7);
DEFINE_REG(pm_top, chip_revision, 0x1, 8, 15); //0: U01(E1), 1: U02(E2), 2: U03(E3)

DEFINE_REG(efuse0, outb_overwrite_en, 0x5c, 0, 0); // for test only
DEFINE_REG(efuse0, outb_overwrite_35, 0x52, 3, 3); // 1: disable shader_core1
DEFINE_REG(efuse0, outb_overwrite_36, 0x52, 4, 4); // 1: disable shader_core2

DEFINE_REG(tzpc_aid_0, tzpc_page_table_walk_aid, 0x0, 0, 5);
DEFINE_REG(tzpc_aid_0, tzpc_gpu_aid, 0x35, 8, 13);
DEFINE_REG(tzpc_aid_0, tzpc_gpu_protected_aid, 0x36, 0, 5);

DEFINE_REG(CKGEN00, clkgen_sel, 0x36, 0, 15);
DEFINE_REG(armpll, clk_lo, 0x30, 0, 15);
DEFINE_REG(armpll, clk_hi, 0x31, 0, 15);
DEFINE_REG(armpll, sld, 0x32, 0, 0);
DEFINE_REG(armpll, armpll_ictrl, 0x04, 4, 5);
DEFINE_REG(armpll, armpll_loop_div_1st, 0x02, 8, 9);
DEFINE_REG(armpll, armpll_loop_div_2nd, 0x03, 0, 7);
DEFINE_REG(armpll, armpll_en_occ_div128, 0x05, 0, 0);
DEFINE_REG(armpll, armpll_pd_droop_bypass, 0x07, 5, 5);
DEFINE_REG(armpll, armpll_pd_vringcmp, 0x09, 0, 0);
DEFINE_REG(armpll, armpll_en_cpuclk, 0x01, 7, 7);
DEFINE_REG(armpll, armpll_en_occclk2, 0x01, 9, 9);
DEFINE_REG(armpll, armpll_pd, 0x01, 8, 8);

DEFINE_REG(CKGEN00, gc_gpubrdpll_output_div, 0x7c6, 8, 10);
DEFINE_REG(CKGEN00, gc_gpubrdpll_input_div, 0x7c4, 0, 1);
DEFINE_REG(CKGEN00, gc_gpubrdpll_loopdiv_first, 0x7c7, 0, 1);
DEFINE_REG(CKGEN00, gc_gpubrdpll_loopdiv_second, 0x7c8, 0, 7);
DEFINE_REG(CKGEN00, pd_gpubrdpll_postdiv, 0x7c1, 4, 4);
DEFINE_REG(CKGEN00, pd_gpubrdpll, 0x7c0, 0, 0);
DEFINE_REG(CKGEN00, pd_gpubrdpll_clk_div2p5, 0x7c0, 4, 4);
DEFINE_REG(CKGEN00, pd_gpubrdpll_clk_div2, 0x7c0, 8, 8);

// Start of Added for m6e3
DEFINE_REG(GPUBRDGPLL, gc_gpubrdpll_output_div, 0x6, 8, 10);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdpll_input_div, 0x4, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdpll_loopdiv_first, 0x7, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdpll_loopdiv_second, 0x8, 0, 7);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll_postdiv, 0x1, 4, 4);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll_clk_div30, 0x1, 8, 8);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll, 0x0, 0, 0);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll_clk_div5, 0x1, 0, 0);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll_clk_div1, 0x0, 4, 4);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll_clk_div2, 0x0, 8, 8);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdpll_clk_div3, 0x0, 12, 12);
// End of Added for m6e3

DEFINE_REG(X32_GPU_DIE, riu_apb_en, 0x66, 0, 0);
DEFINE_REG(X32_GPU_DIE, miu0_start, 0x50, 0, 15);
DEFINE_REG(X32_GPU_DIE, miu0_end, 0x51, 0, 15);

DEFINE_REG(CKGEN00, ckg_bridge_gpu_nodie, 0x30, 0, 0);
DEFINE_REG(CKGEN00, ckg_gpu_gpu_die, 0x32, 0, 0);
DEFINE_REG(CKGEN00, ckg_shader_core, 0x34, 0, 0);
DEFINE_REG(CKGEN00, ckg_xtal_24m_gpu_die, 0xa0, 10, 10);
DEFINE_REG(CKGEN00, ckg_xtal_24m_gpu_nodie, 0xa0, 12, 12);
DEFINE_REG(CKGEN00, ckg_xtal_24m_gpu_shader, 0xa0, 14, 14);
DEFINE_REG(CKGEN00, ckg_xtal_12m_gpu_die, 0x9e, 10, 10);

DEFINE_REG(CKGEN00, ckg_disp_mfdec_gpu_nodie, 0x49a, 8, 8);
DEFINE_REG(CKGEN00, sw_en_bridge2gpu_nodie, 0x510, 0, 0);
DEFINE_REG(CKGEN00, sw_en_gpu2_gpudie, 0x511, 0, 0);
DEFINE_REG(CKGEN00, sw_en_sc2shader, 0x512, 0, 0);
DEFINE_REG(CKGEN00, sw_en_xtal_12m2met, 0x513, 0, 0);
DEFINE_REG(CKGEN00, sw_en_xtal_24m2syscount, 0x514, 1, 1);
DEFINE_REG(CKGEN00, sw_en_xtal_24m2xtal, 0x514, 2, 2);
DEFINE_REG(CKGEN01, ckg_mcu_nonpm_gpu_die, 0x414, 12, 12);
DEFINE_REG(CKGEN01, ckg_mcu_nonpm_gpu_nodie, 0x414, 14, 14);
DEFINE_REG(CKGEN01, sw_en_disp_mfdec2gpu_nodie, 0x559, 0, 0);
DEFINE_REG(CKGEN01, sw_en_mcu_nonpm2_gpu_die, 0x6dd, 11, 11);
DEFINE_REG(CKGEN01, sw_en_mcu_nonpm2_gpu_nodie, 0x6dd, 12, 12);
DEFINE_REG(CKGEN01, sw_en_riu_nonpm2riu_dft_gpu_nodie, 0x7f0, 12, 12);

DEFINE_REG(X32_GPU, soft_reset, 0x00, 0, 0);
DEFINE_REG(X32_GPU, secure_sw_reset, 0x00, 1, 1);
DEFINE_REG(X32_GPU, gpu_protect_mode, 0x5b, 0, 0);
DEFINE_REG(X32_GPU, gpu_bridge_idle, 0x5E, 1, 1);
DEFINE_REG(X32_GPU, riu_legacy_mode, 0x7f, 0, 0);
DEFINE_REG(X32_GPU_DIE, riu_die_legacy_mode, 0x7f, 1, 1);

//dummy register
DEFINE_REG(X32_GPU, spare0, 0x49, 0, 15);
DEFINE_REG(X32_GPU, spare1, 0x4a, 0, 15);

DEFINE_REG(gpu_ror_w, wror_miu_hw_arb_update, 0x1f, 8, 8);
DEFINE_REG(gpu_ror_r, rror_miu_hw_arb_update, 0x1f, 8, 8);

DEFINE_REG(SRAM_PD, glb_sram_pd_reg_gpu, 0x100, 0, 0);
DEFINE_REG(SRAM_PD, glb_sram_pd_reg_gpu_die, 0x110, 0, 0);

DEFINE_REG(SRAM_PD, glb_sram_pd_reg_shader_core0, 0x111, 0, 0);
DEFINE_REG(SRAM_PD, glb_sram_pd_reg_shader_core1, 0x112, 0, 0);
DEFINE_REG(SRAM_PD, glb_sram_pd_reg_shader_core2, 0x113, 0, 0);


// Add for debug
DEFINE_REG(X32_GPU, force_clkgate_off, 0x42, 11, 11);

//ToDo: Check the following list
DEFINE_REG_BANK(X32_MIU,       0x1bf400);
DEFINE_REG(X32_MIU, out_of_area_start,           0xc, 0, 15);
DEFINE_REG(X32_MIU, out_of_area_start_20_16,     0xd, 0, 4);
DEFINE_REG(X32_MIU, out_of_area_end,             0xe, 0, 15);
DEFINE_REG(X32_MIU, out_of_area_end_20_16,       0xf, 0, 4);

//bank for mpu
DEFINE_REG_BANK(IOMMU_GLOBAL,       0x120e00);
DEFINE_REG_BANK(X32_IOMMU_LOCAL_GPU,       0x2ee700);
DEFINE_REG_BANK(X32_IOMMU_BYPASS_TABLE0_GPU,       0x2ee100);
DEFINE_REG_BANK(X32_IOMMU_BYPASS_TABLE1_GPU,       0x2ee200);

//reg for mpu
//6. Update MPU Base Address
DEFINE_REG(IOMMU_GLOBAL, mpu_table_base_low, 0x2, 0, 15);
DEFINE_REG(IOMMU_GLOBAL, mpu_table_base_high, 0x3, 0, 3);
DEFINE_REG(IOMMU_GLOBAL, mpu_area0_start, 0x4, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_area0_end, 0x5, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_area1_start, 0x6, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_area1_end, 0x7, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_table_update, 0x8, 0, 0);

DEFINE_REG(IOMMU_GLOBAL, mpu_enable, 0x9, 0, 0);

//7. MPU invalidate by range@IOMMU_GLOBAL
//8. MPU invalidate all@IOMMU_GLOBAL
DEFINE_REG(IOMMU_GLOBAL, mpu_table_invalid_mode, 0xd, 0, 0);// default 0: by range
DEFINE_REG(IOMMU_GLOBAL, mpu_cache_invalidate_ref_idle, 0x10, 8, 8); // 0:mpu idle, 1: bridge idle
DEFINE_REG(IOMMU_GLOBAL, mpu_tlb_invalid_start, 0xe, 0, 15);
DEFINE_REG(IOMMU_GLOBAL, mpu_tlb_invalid_end, 0xf, 0, 15);
DEFINE_REG(IOMMU_GLOBAL, iommu_mpu_tlb_invalid_fire, 0x10, 0, 0);
DEFINE_REG(IOMMU_GLOBAL, iommu_mpu_tlb_invalid_status, 0x11, 2, 2);  //[2] stand for GPU. mpu flush flag, 1: invalidating cache, 0: invalidating cache done. ReadOnly

//9. Read MPU fault information@IOMMU_LOCAL
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_debug_client_sel_rw_path, 0x65, 8, 8);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_fault_info_valid, 0x70, 0, 0); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_fault_phy_address_low, 0x71, 0, 15); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_fault_phy_address_high, 0x72, 0, 5); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_fault_info_sr, 0x73, 8, 12); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_fault_info_en_status, 0x74, 0, 0); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_fault_info_clean, 0x74, 2, 2);

//10. MPU Hit rate calculations@IOMMU_LOCAL
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_en_hitrate_calculation, 0x6d, 8, 8);

DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_hit_low, 0x68, 0, 15); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_hit_high, 0x69, 0, 4); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_miss_low, 0x6a, 0, 15); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_miss_high, 0x6b, 0, 4); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_total_low, 0x6c, 0, 15); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_total_high, 0x6d, 0, 4); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_bypass_low, 0x6e, 0, 15); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_bypass_high, 0x6f, 0, 4); //ReadOnly
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_index, 0x6d, 12, 15); //ReadOnly

//11. Bypass Table Debug Mode
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_info, 0x31, 5, 7);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_table_enable, 0x30, 1, 1);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_table_debug_enable, 0x30, 2, 2);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_table_entry_size, 0x30, 4, 5); // default 0: 1bit means 256KB bytes
DEFINE_REG(X32_IOMMU_BYPASS_TABLE0_GPU, mpu_bypass_table_content, 0x00, 0, 3); // check bypass table default content setting
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_enable_local, 0x61, 0, 15); //bit[0]  for ACPU_MPU_LOCAL, GPU_MPU_LOCAL enable

#if defined(CONFIG_MALI_DEBUG)
DEFINE_REG_BANK(cpu, 0x200200);
DEFINE_REG(cpu, cpu_axi_stop, 0x41, 0, 0);
#endif

#if MTK_DTV_GPU_MFDEC
DEFINE_REG(CKGEN00, ckg_g_disp_mfdec, 0x49a, 0, 0);
DEFINE_REG(CKGEN00, ckg_g_disp_mfdec_gpu, 0x49a, 10, 10); // Added for m6e3
DEFINE_REG(CKGEN00, sw_en_smi2scip, 0x53B, 0 , 0); //Added for m6e3. Shared by B2R/B2R lite1/B2R lite2/GPU
DEFINE_REG(X32_GPU, mfdec_rreq_rd_len, 0x41, 0, 2);
DEFINE_REG(X32_GPU, mfdec_divider_en, 0x42, 14, 14);
DEFINE_REG(X32_GPU, mfdec_linear_mode, 0x43, 0, 0);
DEFINE_REG(X32_GPU_DIE, mfdec_adr_idx, 0x3a, 0, 3);
DEFINE_REG(X32_GPU_DIE, video_pitch, 0x53, 0, 14);

DEFINE_REG(X32_GPU_DIE, mfdec_y_start, 0x18, 0, 15);
DEFINE_REG(X32_GPU_DIE, mfdec_y_start_21_16, 0x19, 0, 5);
DEFINE_REG(X32_GPU_DIE, mfdec_y_end, 0x1a, 0, 15);
DEFINE_REG(X32_GPU_DIE, mfdec_y_end_21_16, 0x1b, 0, 5);

DEFINE_REG(X32_GPU_DIE, mfdec_uv_start, 0x1c, 0, 15);
DEFINE_REG(X32_GPU_DIE, mfdec_uv_start_21_16, 0x1d, 0, 5);
DEFINE_REG(X32_GPU_DIE, mfdec_uv_end, 0x1e, 0, 15);
DEFINE_REG(X32_GPU_DIE, mfdec_uv_end_21_16, 0x1f, 0, 5);

DEFINE_REG(X32_GPU_DIE, mfdec_adr_update, 0x3a, 4, 4);
DEFINE_REG(X32_GPU_DIE, mfdec_valid, 0x52, 0, 15);

DEFINE_REG_BANK(MFDEC_BKA415, 0xA41500);

//DEFINE_REG(mfdec_clock, CKG_DC_SRAM0_MFDEC_USE, 0x4f, 0, 3);
//DEFINE_REG(mfdec_clock, CKG_DC_SRAM1_MFDEC_USE, 0x4f, 4, 7);

DEFINE_REG(CKGEN01, sw_en_xc_disp_mfdec2scip, 0x661, 0, 0);
DEFINE_REG(CKGEN01, ckg_xc_disp_mfdec_scip, 0x330, 0, 0);
DEFINE_REG(CKGEN01, sw_en_xc_dc02scip, 0x65f, 0, 0);
DEFINE_REG(CKGEN01, ckg_xc_dc0_scip, 0x2c4, 0, 0);

//DEFINE_REG(X32_GPU_DIE, mfdec_16b_mode,          0x44, 0, 15); // 0: 32 bytes mode (not support in M6)
DEFINE_REG(X32_GPU_DIE, mfdec_off,               0x66, 1, 1);

DEFINE_REG(MFDEC_BKA415, disp_mfdec_clk_gate,     0x0, 12, 12);
DEFINE_REG(MFDEC_BKA415, mfdec_reset,                   0x0, 0, 0);
DEFINE_REG(MFDEC_BKA415, vde_xpu_sel,                   0x0, 6, 6);
DEFINE_REG(MFDEC_BKA415, dec_frame_start_xpu,     0x0, 8, 8);
DEFINE_REG(MFDEC_BKA415, dec_frame_end_xpu,       0x0, 9, 9);
DEFINE_REG(MFDEC_BKA415, gpu_aid_rst,     0x2, 1, 1); // Added for m6e3

DEFINE_REG(MFDEC_BKA415, mfdec_xpu_sel,                 0x1,  0,  0);
DEFINE_REG(MFDEC_BKA415, gpu_mfdec_map,               0x1,  4,  4);
DEFINE_REG(MFDEC_BKA415, gpu_dec_sw_rst,               0x1,  10,  10);
DEFINE_REG(MFDEC_BKA415, disp_mfdec_int_mask,          0x6, 0, 7);
DEFINE_REG(MFDEC_BKA415, disp_mfdec_int_en,               0x6, 8, 8);

DEFINE_REG(MFDEC_BKA415, fb_ufo_jump_mode,                 0xd0, 0, 0);// 0: non-jump mode, 1: jump mode
DEFINE_REG(MFDEC_BKA415, fb_ufo_lsb_tile,                  0xd0, 2, 2);// 0: raster mode, 1: tile mode
DEFINE_REG(MFDEC_BKA415, fb_ufo_jump_mode_m6e3,            0xd0, 3, 3);// 0: non-jump mode, 1: jump mode
DEFINE_REG(MFDEC_BKA415, fb_ufo_lsb_tile_m6e3,             0xd0, 5, 5);// 0: raster mode, 1: tile mode
DEFINE_REG(MFDEC_BKA415, gpu_main_ctrl_mode,               0xd0, 6, 7);// 0: gpu_sw_frame_start, 1: auto_start

DEFINE_REG(MFDEC_BKA415, prg_fb_type,                  0x8,  0,  2);
DEFINE_REG(MFDEC_BKA415, prg_fb_idx,                    0x8,  4,  7);
DEFINE_REG(MFDEC_BKA415, fb_para_data_0,              0x9,  0,  15); // 64Byte unit
DEFINE_REG(MFDEC_BKA415, fb_para_data_1,             0xa,  0,  15); // 64Byte unit
DEFINE_REG(MFDEC_BKA415, tagram_inv,                    0xe,  0,  0); //SW force mfdec cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, rt_tagram_inv,                 0xe,  1,  1); //SW run-time force cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, tagram_inv_2nd,                 0xe,  2,  2); //SW force mfdec2 cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, tagram_inv_gpu,                 0xe,  3,  3); //SW force mfdec cache tag ram invalidate for gpu path
DEFINE_REG(MFDEC_BKA415, vd_iommu_tagram_inv,           0xe,  4,  4); //SW force codec_iommu cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, mfd_l_cache_flush_timeout_lb,  0x12, 0,  5);
DEFINE_REG(MFDEC_BKA415, mfd_l_cache_flush_timeout_ub,  0x12, 8,  13);
DEFINE_REG(MFDEC_BKA415, mfd_ofs_cache,                 0x16, 15, 15); //Offset DMA cache time-out enable
DEFINE_REG(MFDEC_BKA415, mfd_cpx_pf_en,                 0x50, 12, 12); //Enable mfdec engine cpx data pre-fetch

// gpu bridge debug register
DEFINE_REG(X32_GPU, mfdec_bri_status_sel_1, 0x40, 4, 6);
DEFINE_REG(X32_GPU, mfdec_status_1, 0x69, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_1_31_16, 0x6a, 0, 15);
DEFINE_REG(X32_GPU, bridge_idle, 0x5e, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_sel, 0x6f, 0, 2);
DEFINE_REG(X32_GPU, g3d_bri_status_0, 0x6b, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_0_31_16, 0x6c, 0, 15);

DEFINE_REG(X32_GPU_DIE, mfdec_bri_status_sel_0, 0x40, 1, 3);
DEFINE_REG(X32_GPU_DIE, mfdec_status_0, 0x67, 0, 15);
DEFINE_REG(X32_GPU_DIE, mfdec_status_0_31_16, 0x68, 0, 15);

// mfdec debug register
DEFINE_REG(MFDEC_BKA415, mfdec_dbus_l,               0x66, 0, 15);
DEFINE_REG(MFDEC_BKA415, mfdec_dbus_h,               0x67, 0, 7);
DEFINE_REG(MFDEC_BKA415, mfdec_dbus_sel,             0x67, 8, 15);

#endif
