/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _MTK_TV_LPLL_TBL_H_
#define _MTK_TV_LPLL_TBL_H_

#define LPLL_REG_NUM         (44)
#define PNL_NUM_VER1         (35)

//======version2 start======
#define LPLL_REG_NUM_VER0200    (37)
#define MODA_REG_NUM_VER0200    (29)
#define MPLL_REG_NUM_VER0200    (7)
#define PNL_NUM_VER0200         (21)


//======version3 start======

#define LPLL_REG_NUM_VER0300    (53)
#define MODA_REG_NUM_VER0300    (74)
#define MPLL_REG_NUM_VER0300    (7)
#define PNL_NUM_VER0300         (21)

//======version0203 start======

#define LPLL_REG_NUM_VER0203    (37)
#define MODA_REG_NUM_VER0203    (29)
#define MPLL_REG_NUM_VER0203    (7)
#define PNL_NUM_VER0203         (21)

//======version004 start======
#define LPLL_REG_NUM_VER004    (34)
#define MODA_REG_NUM_VER004    (11)
#define MPLL_REG_NUM_VER004    (8)
#define PNL_NUM_VER004         (177)

//======version005 start======
#define LPLL_REG_NUM_VER005    (36)
#define MODA_REG_NUM_VER005    (11)
#define MPLL_REG_NUM_VER005    (8)
#define PNL_NUM_VER005         (236)

//======version006 start======
#define LPLL_REG_NUM_VER006    (35)
#define MODA_REG_NUM_VER006    (10)
#define MPLL_REG_NUM_VER006    (8)
#define PNL_NUM_VER006         (200)

//======version007 start======
#define LPLL_REG_NUM_VER007    (31)
#define Master_PLL_REG_NUM_VER007    (55)
#define Slave_PLL_REG_NUM_VER007    (19)
#define Slave_SDM_PCW_REG_NUM_VER007    (2)
#define OSD_PLL_REG_NUM_VER007    (41)
#define OSD_SDM_PCW_REG_NUM_VER007    (3)
#define MODA_REG_NUM_VER007    (99)
#define MOD_D_REG_NUM_VER007    (1)
#define PNL_NUM_VER007         (241)

typedef enum {

	//======version0100 start======
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz,                           // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz,                           // 1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz,                           // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz,                           // 3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz,                           // 4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz,                           // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz,                        // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz,                        // 7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz,                        // 8
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz,                        // 9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz,                        // 10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz,                        // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_400to600MHz,          // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to400MHz,          // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to300MHz,          // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_400to600MHz,          // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to400MHz,          // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to300MHz,          // 17
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz,          // 18
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz,          // 19
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to300MHz,          // 20
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_400to600MHz,          // 21
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to400MHz,          // 22
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to300MHz,          // 23
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to600MHz,          // 24
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to300MHz,          // 25
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz,          // 26
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz,          // 27
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz,          // 28
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz,          // 29
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to300MHz,          // 30
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz,          // 31
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to300MHz,          // 32
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz,          // 33
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to300MHz,          // 34
	//======version0100 end======

	//======version0200 start======
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2,                           // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2,                           // 1
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2,                           // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2,                           // 3
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2,                        // 4
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2,                        // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2,                        // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2,                        // 7
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2,          // 8
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2,          // 9
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2,          // 10
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2,          // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2,          // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2,          // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2,          // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2,          // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2,          // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2,          // 17
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2,          // 18
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2,              // 19
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2,// 20
	//======version0200 end======

	//======version0300 start=====
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER0300,                          // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER0300,                          // 1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER0300,                          // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER0300,                          // 3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER0300,                          // 4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER0300,                          // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER0300,                       // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER0300,                       // 7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER0300,                       // 8
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER0300,                       // 9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER0300,                       // 10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER0300,                       // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER0300,         // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER0300,         // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER0300,   // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER0300,   // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER0300,   // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER0300,   // 17
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER0300,               // 18
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER0300,// 19
	E_PNL_SUPPORTED_LPLL_CEDS_TEST_0to600MHz_VER0300,                           // 20
	//======version0300 end=====

	//======version0203 start=====
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER0203,                             // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER0203,                             // 1
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER0203,                             // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER0203,                             // 3
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER0203,                          // 4
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER0203,                          // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER0203,                          // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER0203,                          // 7
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER0203,            // 8
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER0203,            // 9
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER0203,            // 10
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER0203,            // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER0203,            // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER0203,            // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER0203,            // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER0203,            // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER0203,            // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER0203,            // 17
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER0203,            // 18
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER0203,                // 19
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER0203,  // 20
	//======version0203 end=====

	//======version004 start====
	E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004,          //0
	E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004,          //1
	E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004,          //2
	E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004,          //3
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004,          //4
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004,          //5
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004,          //6
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004,          //7
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004,          //8
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004,          //9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004,          //10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004,          //11
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004,          //12
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004,          //13
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004,          //14
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004,          //15
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004,          //16
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004,          //17
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004,          //18
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004,          //19
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004,          //20
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004,          //21
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004,          //22
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004,          //23
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004,          //24
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004,          //25
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004,          //26
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004,          //27
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004,          //28
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004,          //29
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004,          //30
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004,          //31
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004,          //32
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004,          //33
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004,          //34
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004,          //35
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004,          //36
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004,          //37
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004,          //38
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004,          //39
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004,          //40
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004,          //41
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004,          //42
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004,          //43
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004,          //44
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004,          //45
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004,          //46
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004,          //47
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004,          //48
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004,          //49
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004,          //50
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004,          //51
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004,          //52
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004,          //53
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004,          //54
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004,          //55
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004,          //56
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004,          //57
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004,          //58
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004,          //59
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004,          //60
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004,          //61
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004,          //62
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004,          //63
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004,          //64
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004,          //65
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004,          //66
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004,          //67
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004,          //68
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004,          //69
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004,          //70
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004,          //71
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004,          //72
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004,          //73
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004,          //74
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004,          //75
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004,          //76
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004,          //77
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004,          //78
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004,          //79
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004,          //80
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004,          //81
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004,          //82
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004,          //83
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004,          //84
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004,          //85
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004,          //86
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004,          //87
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004,          //88
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004,          //89
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004,          //90
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004,          //91
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004,          //92
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004,          //93
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004,          //94
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004,          //95
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004,          //96
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004,          //97
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004,          //98
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004,          //99
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004,          //100
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004,          //101
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004,          //102
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004,          //103
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004,          //104
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004,          //105
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004,          //106
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004,          //107
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004,          //108
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004,          //109
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004,          //110
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004,          //111
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004,          //112
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004,          //113
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004,          //114
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004,          //115
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004,          //116
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004,          //117
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004,          //118
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004,          //119
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004,          //120
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004,          //121
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004,          //122
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004,          //123
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004,          //124
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004,          //125
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004,          //126
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004,          //127
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004,          //128
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004,          //129
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004,          //130
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004,          //131
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004,          //132
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004,          //133
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004,          //134
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004,          //135
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004,          //136
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004,          //137
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004,          //138
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004,          //139
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004,          //140
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004,          //141
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004,          //142
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004,          //143
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004,          //144
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004,          //145
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004,          //146
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004,          //147
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004,          //148
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004,          //149
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004,          //150
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004,          //151
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004,          //152
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004,          //153
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004,          //154
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004,          //155
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004,          //156
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004,          //157
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004,          //158
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004,          //159
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004,          //160
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004,          //161
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004,          //162
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004,          //163
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004,          //164
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004,          //165
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004,          //166
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004,          //167
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004,          //168
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004,          //169
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004,          //170
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004,          //171
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004,          //172
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004,          //173
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004,          //174
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004,          //175
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004,          //176
	//======version004 end======
	//======version005 start====
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005,          //0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005,          //1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005,          //2

	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005,          //3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005,          //4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005,          //5

	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005,          //6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005,          //7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005,          //8

	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005,          //9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005,          //10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005,          //11

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_360to600MHz_VER005,          //12
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to360MHz_VER005,          //13
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to300MHz_VER005,          //14

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_450to600MHz_VER005,          //15
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to450MHz_VER005,          //16
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to300MHz_VER005,          //17

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to600MHz_VER005,          //18
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to300MHz_VER005,          //19

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_360to600MHz_VER005,          //20
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to360MHz_VER005,          //21
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to300MHz_VER005,          //22

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_450to600MHz_VER005,          //23
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to450MHz_VER005,          //24
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to300MHz_VER005,          //25

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to720MHz_VER005,          //26
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to360MHz_VER005,          //27

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_480to720MHz_VER005,          //28
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to480MHz_VER005,          //29
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to360MHz_VER005,          //30

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to600MHz_VER005,          //31
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to300MHz_VER005,          //32

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to600MHz_VER005,          //33
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to300MHz_VER005,          //34

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to600MHz_VER005,          //35
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to300MHz_VER005,          //36

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_400to600MHz_VER005,          //37
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to400MHz_VER005,          //38
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to300MHz_VER005,          //39

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_360to600MHz_VER005,          //40
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to360MHz_VER005,          //41
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to300MHz_VER005,          //42

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_450to600MHz_VER005,          //43
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to450MHz_VER005,          //44
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to300MHz_VER005,          //45

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to600MHz_VER005,          //46
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to300MHz_VER005,          //47

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_360to600MHz_VER005,          //48
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to360MHz_VER005,          //49
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to300MHz_VER005,          //50

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_450to600MHz_VER005,          //51
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to450MHz_VER005,          //52
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to300MHz_VER005,          //53

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to720MHz_VER005,          //54
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to360MHz_VER005,          //55

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_480to720MHz_VER005,          //56
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to480MHz_VER005,          //57
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to360MHz_VER005,          //58

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to600MHz_VER005,          //59
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to300MHz_VER005,          //60

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to600MHz_VER005,          //61
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to300MHz_VER005,          //62

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to600MHz_VER005,          //63
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to300MHz_VER005,          //64

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_400to600MHz_VER005,          //65
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to400MHz_VER005,          //66
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to300MHz_VER005,          //67

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_400to600MHz_VER005,          //68
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to400MHz_VER005,          //69
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to300MHz_VER005,          //70

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_450to600MHz_VER005,          //71
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to450MHz_VER005,          //72
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to300MHz_VER005,          //73

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to600MHz_VER005,          //74
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to300MHz_VER005,          //75

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_450to600MHz_VER005,          //76
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to450MHz_VER005,          //77
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to300MHz_VER005,          //78

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_400to600MHz_VER005,          //79
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to400MHz_VER005,          //80
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to300MHz_VER005,          //81

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to720MHz_VER005,          //82
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to360MHz_VER005,          //83

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to600MHz_VER005,          //84
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to300MHz_VER005,          //85

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_540to720MHz_VER005,          //86
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to540MHz_VER005,          //87
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to360MHz_VER005,          //88

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to600MHz_VER005,          //89
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to300MHz_VER005,          //90

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to600MHz_VER005,          //91
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to300MHz_VER005,          //92

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to600MHz_VER005,          //93
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to300MHz_VER005,          //94

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_400to600MHz_VER005,          //95
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to400MHz_VER005,          //96
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to300MHz_VER005,          //97

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_400to600MHz_VER005,          //98
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to400MHz_VER005,          //99
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to300MHz_VER005,          //100

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_450to600MHz_VER005,          //101
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to450MHz_VER005,          //102
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to300MHz_VER005,          //103

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to600MHz_VER005,          //104
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to300MHz_VER005,          //105

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_400to600MHz_VER005,          //106
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to400MHz_VER005,          //107
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to300MHz_VER005,          //108

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to720MHz_VER005,          //109
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to360MHz_VER005,          //110

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to600MHz_VER005,          //111
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to300MHz_VER005,          //112

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to600MHz_VER005,          //113
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to300MHz_VER005,          //114

	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_400to600MHz_VER005,          //115
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to400MHz_VER005,          //116
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to300MHz_VER005,          //117

	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to600MHz_VER005,          //118
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to300MHz_VER005,          //119

	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_450to600MHz_VER005,          //120
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to450MHz_VER005,          //121
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to300MHz_VER005,          //122

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to600MHz_VER005,          //123
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to300MHz_VER005,          //124

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_400to600MHz_VER005,          //125
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to400MHz_VER005,          //126
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to300MHz_VER005,          //127

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to720MHz_VER005,          //128
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to360MHz_VER005,          //129

	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to600MHz_VER005,          //130
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to300MHz_VER005,          //131

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to600MHz_VER005,          //132
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to300MHz_VER005,          //133

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to600MHz_VER005,          //134
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to300MHz_VER005,          //135

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to720MHz_VER005,          //136
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to360MHz_VER005,          //137

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to600MHz_VER005,          //138
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to300MHz_VER005,          //139

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to600MHz_VER005,          //140
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to300MHz_VER005,          //141

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_450to600MHz_VER005,          //142
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to450MHz_VER005,          //143
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to300MHz_VER005,          //144

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to600MHz_VER005,          //145
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to300MHz_VER005,          //146

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to600MHz_VER005,          //147
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to300MHz_VER005,          //148

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to720MHz_VER005,          //149
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to360MHz_VER005,          //150

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_360to600MHz_VER005,          //151
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to360MHz_VER005,          //152
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to300MHz_VER005,          //153

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to600MHz_VER005,          //154
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to300MHz_VER005,          //155

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to600MHz_VER005,          //156
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to300MHz_VER005,          //157

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to600MHz_VER005,          //158
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to300MHz_VER005,          //159

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to600MHz_VER005,          //160
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to300MHz_VER005,          //161

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to600MHz_VER005,          //162
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to300MHz_VER005,          //163

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to600MHz_VER005,          //164
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to300MHz_VER005,          //165

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to720MHz_VER005,          //166
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to360MHz_VER005,          //167

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_450to600MHz_VER005,          //168
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to450MHz_VER005,          //169
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to300MHz_VER005,          //170

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_450to600MHz_VER005,          //171
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to450MHz_VER005,          //172
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to300MHz_VER005,          //173

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_450to600MHz_VER005,          //174
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to450MHz_VER005,          //175
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to300MHz_VER005,          //176

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_450to600MHz_VER005,          //177
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to450MHz_VER005,          //178
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to300MHz_VER005,          //179

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_480to720MHz_VER005,          //180
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to480MHz_VER005,          //181
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to360MHz_VER005,          //182

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to405MHz_VER005,          //183
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to202MHz_VER005,          //184

	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to700MHz_VER005,          //185
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER005,          //186

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER005,          //187
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER005,          //188

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_270to360MHz_VER005,          //189
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to270MHz_VER005,          //190
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER005,          //191

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to360MHz_VER005,          //192
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to180MHz_VER005,          //193

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER005,          //194
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER005,          //195

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_270to360MHz_VER005,          //196
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to270MHz_VER005,          //197
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER005,          //198

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to360MHz_VER005,          //199
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to180MHz_VER005,          //200

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER005,          //201
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER005,          //202

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_270to360MHz_VER005,          //203
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to270MHz_VER005,          //204
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to180MHz_VER005,          //205

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to360MHz_VER005,          //206
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER005,          //207

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to360MHz_VER005,          //208
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to180MHz_VER005,          //209

	E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to360MHz_VER005,          //210
	E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to180MHz_VER005,          //211

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_270to360MHz_VER005,          //212
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to270MHz_VER005,          //213
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER005,          //214

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER005,          //215
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER005,          //216

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_270to360MHz_VER005,          //217
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to270MHz_VER005,          //218
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER005,          //219

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER005,          //220
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER005,          //221

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_270to360MHz_VER005,          //222
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to270MHz_VER005,          //223
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER005,          //224

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to360MHz_VER005,          //225
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to180MHz_VER005,          //226

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_240to360MHz_VER005,          //227
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to240MHz_VER005,          //228
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to180MHz_VER005,          //229

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to405MHz_VER005,          //230
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to202MHz_VER005,          //231

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_CML_300to600MHz_VER005,		   //232
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_CML_300to300MHz_VER005,		   //233

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_CML_360to720MHz_VER005,		   //234
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_CML_360to360MHz_VER005,		   //235
	//======version005 end======
	//======version006 start======
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_HD60_225to300MHz_VER006,          //0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_HD60_150to225MHz_VER006,          // 1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_HD60_150to150MHz_VER006,          // 2

	E_PNL_SUPPORTED_LPLL_LVDS_2ch_2K60_225to300MHz_VER006,          //3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_2K60_150to225MHz_VER006,          //4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_2K60_150to150MHz_VER006,          //5

	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_2K60_225to300MHz_VER006,          //6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_2K60_150to225MHz_VER006,          //7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_2K60_150to150MHz_VER006,          //8

	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_4K2K30_225to300MHz_VER006,          //9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_4K2K30_150to225MHz_VER006,          //10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_4K2K30_150to150MHz_VER006,          //11

	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_HD60_150to300MHz_VER006,          //12
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_HD60_150to150MHz_VER006,          //13

	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_HD60_150to300MHz_VER006,          //14
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_HD60_150to150MHz_VER006,          //15

	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_2K60_150to300MHz_VER006,          //16
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_2K60_150to150MHz_VER006,          //17

	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_2K60_150to300MHz_VER006,          //18
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_2K60_150to150MHz_VER006,          //19

	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_HD60_150to300MHz_VER006,          //20
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_HD60_150to150MHz_VER006,          //21

	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_HD60_150to300MHz_VER006,          //22
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_HD60_150to150MHz_VER006,          //23

	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_2K60_150to300MHz_VER006,          //24
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_2K60_150to150MHz_VER006,          //25

	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_2K60_150to300MHz_VER006,          //26
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_2K60_150to150MHz_VER006,          //27

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K60_CML_225to300MHz_VER006,          //28
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K60_CML_150to225MHz_VER006,          //29
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K60_CML_150to150MHz_VER006,          //30

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K60_CML_225to300MHz_VER006,          //31
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K60_CML_150to225MHz_VER006,          //32
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K60_CML_150to150MHz_VER006,          //33

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K120_CML_300to600MHz_VER006,          //34
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K120_CML_300to300MHz_VER006,          //35

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K120_CML_450to600MHz_VER006,          //36
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K120_CML_300to450MHz_VER006,          //37
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K120_CML_300to300MHz_VER006,          //38

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4x2_4K2K60_CML_450to600MHz_VER006,          //39
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4x2_4K2K60_CML_300to450MHz_VER006,          //40
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4x2_4K2K60_CML_300to300MHz_VER006,          //41

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K2K60_CML_350to600MHz_VER006,          //42
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K2K60_CML_300to350MHz_VER006,          //43
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K2K60_CML_300to300MHz_VER006,          //44

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K2K60_CML_450to600MHz_VER006,          //45
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K2K60_CML_300to450MHz_VER006,          //46
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K2K60_CML_300to300MHz_VER006,          //47

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K2K60_CML_300to600MHz_VER006,          //48
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K2K60_CML_300to300MHz_VER006,          //49

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER006,          //50
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER006,          //51

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K2K60_CML_450to600MHz_VER006,          //52
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K2K60_CML_300to450MHz_VER006,          //53
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K2K60_CML_300to300MHz_VER006,          //54

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K2K60_CML_300to600MHz_VER006,          //55
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K2K60_CML_300to300MHz_VER006,          //56

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_4x2_4K2K60_CML_350to600MHz_VER006,          //57
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_4x2_4K2K60_CML_300to350MHz_VER006,          //58
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_4x2_4K2K60_CML_300to300MHz_VER006,          //59

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K2K60_CML_300to600MHz_VER006,          //60
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K2K60_CML_300to300MHz_VER006,          //61

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_280to360MHz_VER006,          //62
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to280MHz_VER006,          //63
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER006,          //64

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K60_LVDS_225to300MHz_VER006,          //65
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K60_LVDS_150to225MHz_VER006,          //66
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K60_LVDS_150to150MHz_VER006,          //67

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K60_LVDS_225to300MHz_VER006,          //68
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K60_LVDS_150to225MHz_VER006,          //69
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K60_LVDS_150to150MHz_VER006,          //70

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K120_LVDS_300to600MHz_VER006,          //71
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K120_LVDS_300to300MHz_VER006,          //72

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K120_LVDS_450to600MHz_VER006,          //73
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K120_LVDS_300to450MHz_VER006,          //74
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K120_LVDS_300to300MHz_VER006,          //75

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4x2_4K2K60_LVDS_450to600MHz_VER006,          //76
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4x2_4K2K60_LVDS_300to450MHz_VER006,          //77
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4x2_4K2K60_LVDS_300to300MHz_VER006,          //78

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K2K60_LVDS_350to600MHz_VER006,          //79
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K2K60_LVDS_300to350MHz_VER006,          //80
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K2K60_LVDS_300to300MHz_VER006,          //81

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K2K60_LVDS_450to600MHz_VER006,          //82
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K2K60_LVDS_300to450MHz_VER006,          //83
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K2K60_LVDS_300to300MHz_VER006,          //84

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K2K60_LVDS_300to600MHz_VER006,          //85
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K2K60_LVDS_300to300MHz_VER006,          //86

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER006,          //87
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER006,          //88

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K_450to600MHz_VER006,          //89
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K_300to450MHz_VER006,          //90
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K_300to300MHz_VER006,          //91

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K2K60_LVDS_300to600MHz_VER006,          //92
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K2K60_LVDS_300to300MHz_VER006,          //93

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_4x2_4K2K60_LVDS_350to600MHz_VER006,          //94
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_4x2_4K2K60_LVDS_300to350MHz_VER006,          //95
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_4x2_4K2K60_LVDS_300to300MHz_VER006,          //96

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K2K60_LVDS_300to600MHz_VER006,          //97
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K2K60_LVDS_300to300MHz_VER006,          //98

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_280to360MHz_VER006,          //99
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to280MHz_VER006,          //100
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER006,          //101

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_4x2_4K2K60_450to600MHz_VER006,          //102
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_4x2_4K2K60_300to450MHz_VER006,          //103
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_4x2_4K2K60_300to300MHz_VER006,          //104

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K2K60_350to600MHz_VER006,          //105
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K2K60_300to350MHz_VER006,          //106
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K2K60_300to300MHz_VER006,          //107

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K2K60_450to600MHz_VER006,          //108
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K2K60_300to450MHz_VER006,          //109
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K2K60_300to300MHz_VER006,          //110

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K2K60_300to600MHz_VER006,          //111
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K2K60_300to300MHz_VER006,          //112

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER006,          //113
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER006,          //114

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_4x2_4K2K60_350to600MHz_VER006,          //115
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_4x2_4K2K60_300to350MHz_VER006,          //116
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_4x2_4K2K60_300to300MHz_VER006,          //117

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_4K2K60_350to600MHz_VER006,          //118
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_4K2K60_300to350MHz_VER006,          //119
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_4K2K60_300to300MHz_VER006,          //120

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K2K60_300to600MHz_VER006,          //121
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K2K60_300to300MHz_VER006,          //122

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_280to360MHz_VER006,          //123
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to280MHz_VER006,          //124
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER006,          //125

	E_PNL_SUPPORTED_LPLL_ISP_8bit_4x2_4K2K60_450to600MHz_VER006,          //126
	E_PNL_SUPPORTED_LPLL_ISP_8bit_4x2_4K2K60_300to450MHz_VER006,          //127
	E_PNL_SUPPORTED_LPLL_ISP_8bit_4x2_4K2K60_300to300MHz_VER006,          //128

	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K2K60_350to600MHz_VER006,          //129
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K2K60_300to350MHz_VER006,          //130
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K2K60_300to300MHz_VER006,          //131

	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K2K60_300to600MHz_VER006,          //132
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K2K60_300to300MHz_VER006,          //133

	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K2K60_450to600MHz_VER006,          //134
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K2K60_300to450MHz_VER006,          //135
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K2K60_300to300MHz_VER006,          //136

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K2K60_300to600MHz_VER006,          //137
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K2K60_300to300MHz_VER006,          //138

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER006,          //139
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER006,          //140

	E_PNL_SUPPORTED_LPLL_ISP_10bit_4x2_4K2K60_400to600MHz_VER006,          //141
	E_PNL_SUPPORTED_LPLL_ISP_10bit_4x2_4K2K60_300to400MHz_VER006,          //142
	E_PNL_SUPPORTED_LPLL_ISP_10bit_4x2_4K2K60_300to300MHz_VER006,          //143

	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K2K60_300to600MHz_VER006,          //144
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K2K60_300to300MHz_VER006,          //145

	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_4K2K60_400to600MHz_VER006,          //146
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_4K2K60_300to400MHz_VER006,          //147
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_4K2K60_300to300MHz_VER006,          //148

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K2K60_300to600MHz_VER006,          //149
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K2K60_300to300MHz_VER006,          //150

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER006,          //151
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER006,          //152
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER006,          //153

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_4x2_4K2K60_450to600MHz_VER006,          //154
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_4x2_4K2K60_300to450MHz_VER006,          //155
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_4x2_4K2K60_300to300MHz_VER006,          //156

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K2K60_300to600MHz_VER006,          //157
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K2K60_300to300MHz_VER006,          //158

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K2K60_300to600MHz_VER006,          //159
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K2K60_300to300MHz_VER006,          //160

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K2K60_450to600MHz_VER006,          //161
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K2K60_300to450MHz_VER006,          //162
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K2K60_300to300MHz_VER006,          //163

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K2K60_300to600MHz_VER006,          //164
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K2K60_300to300MHz_VER006,          //165

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER006,          //166
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER006,          //167

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_4x2_4K2K60_350to600MHz_VER006,          //168
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_4x2_4K2K60_300to350MHz_VER006,          //169
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_4x2_4K2K60_300to300MHz_VER006,          //170

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K2K60_350to600MHz_VER006,          //171
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K2K60_300to350MHz_VER006,          //172
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K2K60_300to300MHz_VER006,          //173

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K2K60_500to600MHz_VER006,          //174
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K2K60_300to500MHz_VER006,          //175
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K2K60_300to300MHz_VER006,          //176

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_280to360MHz_VER006,          //177
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to280MHz_VER006,          //178
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER006,          //179

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_150to300MHz_VER006,          //180
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_150to150MHz_VER006,          //181

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K2K30_300to600MHz_VER006,          //182
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K2K30_300to300MHz_VER006,          //183

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K2K60_300to600MHz_VER006,          //184
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K2K60_300to300MHz_VER006,          //185

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER006,          //186
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER006,          //187

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_225to300MHz_VER006,          //188
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_150to225MHz_VER006,          //189
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_150to150MHz_VER006,          //190

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K2K30_450to600MHz_VER006,          //191
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K2K30_300to450MHz_VER006,          //192
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K2K30_300to300MHz_VER006,          //193

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K2K60_450to600MHz_VER006,          //194
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K2K60_300to450MHz_VER006,          //195
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K2K60_300to300MHz_VER006,          //196

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_225to360MHz_VER006,          //197
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to225MHz_VER006,          //198
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER006,          //199
	//======version006 end======

	//======version007stard======
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4X2_4K60_CML_300TO600MHZ_VER007,			//0
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4X2_4K60_CML_300TO300MHZ_VER007,			//1

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6X1_4K60_CML_300TO600MHZ_VER007,			//2
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6X1_4K60_CML_300TO300MHZ_VER007,			//3

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8X1_4K60_CML_300TO600MHZ_VER007,			//4
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8X1_4K60_CML_300TO300MHZ_VER007,			//5

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K60_CML_300TO600MHZ_VER007,			//6
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K60_CML_300TO300MHZ_VER007,			//7

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K1K144_CML_270TO360MHZ_VER007,			//8
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K1K144_CML_180TO270MHZ_VER007,			//9
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K1K144_CML_180TO180MHZ_VER007,			//10

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K120_CML_300TO600MHZ_VER007,			//11
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K120_CML_300TO300MHZ_VER007,			//12

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K144_CML_540TO720MHZ_VER007,			//13
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K144_CML_360TO540MHZ_VER007,			//14
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K144_CML_360TO360MHZ_VER007,			//15

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K165_CML_413TO825MHZ_VER007,		//16
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K165_CML_413TO413MHZ_VER007,		//17

	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K60_CML_300TO600MHZ_VER007,		//18
	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K60_CML_300TO300MHZ_VER007,		//19

	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K120_CML_300TO600MHZ_VER007,		//20
	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K120_CML_300TO300MHZ_VER007,		//21

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4X2_4K60_LVDS_300TO600MHZ_VER007,			//22
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4X2_4K60_LVDS_300TO300MHZ_VER007,			//23

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6X1_4K60_LVDS_300TO600MHZ_VER007,			//24
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6X1_4K60_LVDS_300TO300MHZ_VER007,			//25

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8X1_4K60_LVDS_300TO600MHZ_VER007,			//26
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8X1_4K60_LVDS_300TO300MHZ_VER007,			//27

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K60_LVDS_300TO600MHZ_VER007,			//28
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K60_LVDS_300TO300MHZ_VER007,			//29

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K1K144_LVDS_270TO360MHZ_VER007,		//30
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K1K144_LVDS_180TO270MHZ_VER007,		//31
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K1K144_LVDS_180TO180MHZ_VER007,		//32

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K120_LVDS_300TO600MHZ_VER007,		//33
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K120_LVDS_300TO300MHZ_VER007,		//34

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K144_LVDS_540TO720MHZ_VER007,		//35
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K144_LVDS_360TO540MHZ_VER007,		//36
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K144_LVDS_360TO360MHZ_VER007,		//37

	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K165_LVDS_413TO825MHZ_VER007,		//38
	E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12X1_4K165_LVDS_413TO413MHZ_VER007,		//39

	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K60_LVDS_300TO600MHZ_VER007,		//40
	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K60_LVDS_300TO300MHZ_VER007,		//41

	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K120_LVDS_300TO600MHZ_VER007,			//42
	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12X1_4K120_LVDS_300TO300MHZ_VER007,			//43

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K60_300TO600MHZ_VER007,			//44
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K60_300TO300MHZ_VER007,			//45

	E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12X1_4K60_450TO600MHZ_VER007,			//46
	E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12X1_4K60_300TO450MHZ_VER007,			//47
	E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12X1_4K60_300TO300MHZ_VER007,			//48

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_4X2_4K60_300TO600MHZ_VER007,			//49
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_4X2_4K60_300TO300MHZ_VER007,			//50

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_6X1_4K60_300TO600MHZ_VER007,			//51
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_6X1_4K60_300TO300MHZ_VER007,			//52

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_8X1_4K60_300TO600MHZ_VER007,			//53
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_8X1_4K60_300TO300MHZ_VER007,			//54

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K60_300TO600MHZ_VER007,		//55
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K60_300TO300MHZ_VER007,		//56

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K1K144_270TO360MHZ_VER007,			//57
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K1K144_180TO270MHZ_VER007,			//58
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K1K144_180TO180MHZ_VER007,			//59

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K120_300TO600MHZ_VER007,		//60
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K120_300TO300MHZ_VER007,		//61

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K144_540TO720MHZ_VER007,		//62
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K144_360TO540MHZ_VER007,		//63
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K144_360TO360MHZ_VER007,		//64

	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K165_413TO825MHZ_VER007,		//65
	E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12X1_4K165_413TO413MHZ_VER007,		//66

	E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12X1_4K60_300TO600MHZ_VER007,		//67
	E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12X1_4K60_300TO300MHZ_VER007,		//68

	E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12X1_4K120_300TO600MHZ_VER007,			//69
	E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12X1_4K120_300TO300MHZ_VER007,			//70

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_4X2_4K60_300TO600MHZ_VER007,		//71
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_4X2_4K60_300TO300MHZ_VER007,		//72

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_6X1_4K60_300TO600MHZ_VER007,		//73
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_6X1_4K60_300TO300MHZ_VER007,		//74

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_6X2_4K60_300TO600MHZ_VER007,		//75
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_6X2_4K60_300TO300MHZ_VER007,		//76

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_8X1_4K60_300TO600MHZ_VER007,		//77
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_8X1_4K60_300TO300MHZ_VER007,		//78

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K60_300TO600MHZ_VER007,		//79
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K60_300TO300MHZ_VER007,		//80

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K1K144_270TO360MHZ_VER007,		//81
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K1K144_180TO270MHZ_VER007,		//82
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K1K144_180TO180MHZ_VER007,		//83

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K120_300TO600MHZ_VER007,			//84
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K120_300TO300MHZ_VER007,			//85

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K144_540TO720MHZ_VER007,			//86
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K144_360TO540MHZ_VER007,			//87
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K144_360TO360MHZ_VER007,			//88

	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K165_413TO825MHZ_VER007,			//89
	E_PNL_SUPPORTED_LPLL_CHPI_8BIT_12X1_4K165_413TO413MHZ_VER007,			//90

	E_PNL_SUPPORTED_LPLL_CHPI_10BIT_8X1_4K60_300TO600MHZ_VER007,		//91
	E_PNL_SUPPORTED_LPLL_CHPI_10BIT_8X1_4K60_300TO300MHZ_VER007,		//92

	E_PNL_SUPPORTED_LPLL_CHPI_10BIT_12X1_4K60_300TO600MHZ_VER007,			//93
	E_PNL_SUPPORTED_LPLL_CHPI_10BIT_12X1_4K60_300TO300MHZ_VER007,			//94

	E_PNL_SUPPORTED_LPLL_CHPI_10BIT_12X1_4K120_300TO600MHZ_VER007,			//95
	E_PNL_SUPPORTED_LPLL_CHPI_10BIT_12X1_4K120_300TO300MHZ_VER007,			//96

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_2_LANE_2K60_150TO300MHZ_VER007,			//97
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_2_LANE_2K60_150TO150MHZ_VER007,			//98

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_4_LANE_4K30_300TO600MHZ_VER007,			//99
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_4_LANE_4K30_300TO300MHZ_VER007,			//100

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8_LANE_4K60_300TO600MHZ_VER007,			//101
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8_LANE_4K60_300TO300MHZ_VER007,			//102

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8_LANE_4K1K144_180TO360MHZ_VER007,		//103
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8_LANE_4K1K144_180TO180MHZ_VER007,		//104

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K120_300TO600MHZ_VER007,		//105
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K120_300TO300MHZ_VER007,		//106

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K144_540TO720MHZ_VER007,		//107
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K144_360TO540MHZ_VER007,		//108
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K144_360TO360MHZ_VER007,		//109

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K165_413TO825MHZ_VER007,		//110
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_16_LANE_4K165_413TO413MHZ_VER007,		//111

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_2_LANE_2K60_150TO300MHZ_VER007,			//112
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_2_LANE_2K60_150TO150MHZ_VER007,			//113

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_4_LANE_4K30_300TO600MHZ_VER007,			//114
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_4_LANE_4K30_300TO300MHZ_VER007,			//115

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8_LANE_4K60_300TO600MHZ_VER007,			//116
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8_LANE_4K60_300TO300MHZ_VER007,			//117

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8_LANE_4K1K144_270TO360MHZ_VER007,		//118
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8_LANE_4K1K144_180TO270MHZ_VER007,		//119
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8_LANE_4K1K144_180TO180MHZ_VER007,		//120

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K120_300TO600MHZ_VER007,		//121
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K120_300TO300MHZ_VER007,		//122

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K144_540TO720MHZ_VER007,		//123
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K144_360TO540MHZ_VER007,		//124
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K144_360TO360MHZ_VER007,		//125

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K165_619TO825MHZ_VER007,		//126
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K165_413TO619MHZ_VER007,		//127
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_16_LANE_4K165_413TO413MHZ_VER007,		//128

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_2_LANE_2K60_150TO300MHZ_VER007,			//129
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_2_LANE_2K60_150TO150MHZ_VER007,			//130

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_4_LANE_4K30_300TO600MHZ_VER007,			//131
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_4_LANE_4K30_300TO300MHZ_VER007,			//132

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8_LANE_4K60_300TO600MHZ_VER007,			//133
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8_LANE_4K60_300TO300MHZ_VER007,			//134

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_16_LANE_4K120_300TO600MHZ_VER007,		//135
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_16_LANE_4K120_300TO300MHZ_VER007,		//136

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8V_8BIT_4O_300TO600MHZ_VER007,		//137
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8V_8BIT_4O_300TO300MHZ_VER007,		//138

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8V_10BIT_4O_300TO600MHZ_VER007,			//139
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8V_10BIT_4O_300TO300MHZ_VER007,			//140

	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8V_12BIT_4O_300TO600MHZ_VER007,			//141
	E_PNL_SUPPORTED_LPLL_VX1_8BIT_8V_12BIT_4O_300TO300MHZ_VER007,			//142

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8V_8BIT_4O_300TO600MHZ_VER007,			//143
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8V_8BIT_4O_300TO300MHZ_VER007,			//144

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8V_10BIT_4O_300TO600MHZ_VER007,			//145
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8V_10BIT_4O_300TO300MHZ_VER007,			//146

	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8V_12BIT_4O_300TO600MHZ_VER007,			//147
	E_PNL_SUPPORTED_LPLL_VX1_10BIT_8V_12BIT_4O_300TO300MHZ_VER007,			//148

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8V_8BIT_4O_300TO600MHZ_VER007,			//149
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8V_8BIT_4O_300TO300MHZ_VER007,			//150

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8V_10BIT_4O_300TO600MHZ_VER007,			//151
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8V_10BIT_4O_300TO300MHZ_VER007,			//152

	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8V_12BIT_4O_300TO600MHZ_VER007,			//153
	E_PNL_SUPPORTED_LPLL_VX1_12BIT_8V_12BIT_4O_300TO300MHZ_VER007,			//154

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_4X2_4K60_300TO600MHZ_VER007,		//155
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_4X2_4K60_300TO300MHZ_VER007,		//156

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_6X1_4K60_300TO600MHZ_VER007,		//157
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_6X1_4K60_300TO300MHZ_VER007,		//158

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_8X1_4K60_300TO600MHZ_VER007,		//159
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_8X1_4K60_300TO300MHZ_VER007,		//160

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K1K144_270TO360MHZ_VER007,		//161
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K1K144_180TO270MHZ_VER007,		//162
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K1K144_180TO180MHZ_VER007,		//163

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K120_300TO600MHZ_VER007,			//164
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K120_300TO300MHZ_VER007,			//165

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K144_540TO720MHZ_VER007,			//166
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K144_360TO540MHZ_VER007,			//167
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K144_360TO360MHZ_VER007,			//168

	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K165_413TO825MHZ_VER007,			//169
	E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12X1_4K165_413TO413MHZ_VER007,			//170

	E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12X1_4K120_300TO600MHZ_VER007,		//171
	E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12X1_4K120_300TO300MHZ_VER007,		//172

	E_PNL_SUPPORTED_LPLL_LVDS_1CH_150TO300MHZ_VER007,			//173
	E_PNL_SUPPORTED_LPLL_LVDS_1CH_150TO150MHZ_VER007,			//174

	E_PNL_SUPPORTED_LPLL_LVDS_2CH_150TO300MHZ_VER007,			//175
	E_PNL_SUPPORTED_LPLL_LVDS_2CH_150TO150MHZ_VER007,			//176

	E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_150TO300MHZ_VER007,		//177
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_150TO150MHZ_VER007,		//178

	E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_150TO300MHZ_VER007,		//179
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_150TO150MHZ_VER007,		//180

	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_150TO300MHZ_VER007,		//181
	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_150TO150MHZ_VER007,		//182

	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_150TO300MHZ_VER007,		//183
	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_150TO150MHZ_VER007,		//184

	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_150TO300MHZ_VER007,		//185
	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_150TO150MHZ_VER007,		//186

	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_150TO300MHZ_VER007,		//187
	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_150TO150MHZ_VER007,		//188

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_4X2_4K60_300TO600MHZ_VER007,			//189
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_4X2_4K60_300TO300MHZ_VER007,			//190

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_6X1_4K60_300TO600MHZ_VER007,			//191
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_6X1_4K60_300TO300MHZ_VER007,			//192

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_6X2_4K60_300TO600MHZ_VER007,			//193
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_6X2_4K60_300TO300MHZ_VER007,			//194

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_8X1_4K60_300TO600MHZ_VER007,			//195
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_8X1_4K60_300TO300MHZ_VER007,			//196

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K60_300TO600MHZ_VER007,		//197
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K60_300TO300MHZ_VER007,		//198

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K1K144_270TO360MHZ_VER007,			//199
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K1K144_180TO270MHZ_VER007,			//200
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K1K144_180TO180MHZ_VER007,			//201

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K120_300TO600MHZ_VER007,		//202
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K120_300TO300MHZ_VER007,		//203

	E_PNL_SUPPORTED_LPLL_ISP_10BIT_6X2_4K60_300TO600MHZ_VER007,		//204
	E_PNL_SUPPORTED_LPLL_ISP_10BIT_6X2_4K60_300TO300MHZ_VER007,		//205

	E_PNL_SUPPORTED_LPLL_ISP_10BIT_12X1_4K60_300TO600MHZ_VER007,		//206
	E_PNL_SUPPORTED_LPLL_ISP_10BIT_12X1_4K60_300TO300MHZ_VER007,		//207

	E_PNL_SUPPORTED_LPLL_EDP_4LANE_2K60_150TO300MHZ_VER007,		//208
	E_PNL_SUPPORTED_LPLL_EDP_4LANE_2K60_150TO150MHZ_VER007,		//209

	E_PNL_SUPPORTED_LPLL_EDP_4LANE_4K30_300TO600MHZ_VER007,		//210
	E_PNL_SUPPORTED_LPLL_EDP_4LANE_4K30_300TO300MHZ_VER007,		//211

	E_PNL_SUPPORTED_LPLL_EDP_4LANE_4K60_300TO600MHZ_VER007,		//212
	E_PNL_SUPPORTED_LPLL_EDP_4LANE_4K60_300TO300MHZ_VER007,		//213

	E_PNL_SUPPORTED_LPLL_EDP_8LANE_4K120_300TO600MHZ_VER007,		//214
	E_PNL_SUPPORTED_LPLL_EDP_8LANE_4K120_300TO300MHZ_VER007,		//215

	E_PNL_SUPPORTED_LPLL_EDP_16LANE_4K144_540TO720MHZ_VER007,			//216
	E_PNL_SUPPORTED_LPLL_EDP_16LANE_4K144_360TO540MHZ_VER007,			//217
	E_PNL_SUPPORTED_LPLL_EDP_16LANE_4K144_360TO360MHZ_VER007,			//218

	E_PNL_SUPPORTED_LPLL_EDP_16LANE_4K165_412TO825MHZ_VER007,			//219
	E_PNL_SUPPORTED_LPLL_EDP_16LANE_4K165_412TO412MHZ_VER007,			//220

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K144_540TO720MHZ_VER007,		//221
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K144_360TO540MHZ_VER007,		//222
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K144_360TO360MHZ_VER007,		//223

	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K165_619TO825MHZ_VER007,		//224
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K165_413TO619MHZ_VER007,		//225
	E_PNL_SUPPORTED_LPLL_ISP_8BIT_12X1_4K165_413TO413MHZ_VER007,		//226

	E_PNL_SUPPORTED_LPLL_ISP_10BIT_12X1_4K120_300TO600MHZ_VER007,			//227
	E_PNL_SUPPORTED_LPLL_ISP_10BIT_12X1_4K120_300TO300MHZ_VER007,			//228

	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_4X2_4K60_CML_300TO600MHZ_VER007,		//229
	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_4X2_4K60_CML_300TO300MHZ_VER007,		//230

	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_4X2_4K60_LVDS_300TO600MHZ_VER007,		//231
	E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_4X2_4K60_LVDS_300TO300MHZ_VER007,		//232

	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_6PAIR_6BIT_150TO300MHZ_VER007,		//233
	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_6PAIR_6BIT_150TO150MHZ_VER007,		//234

	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_150TO300MHZ_VER007,		//235
	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_150TO150MHZ_VER007,		//236

	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_6PAIR_8BIT_150TO300MHZ_VER007,		//237
	E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_6PAIR_8BIT_150TO150MHZ_VER007,		//238

	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_150TO300MHZ_VER007,		//239
	E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_150TO150MHZ_VER007,		//240
	E_PNL_SUPPORTED_LPLL_MAX,//Add for the max
	//======version007 end======
} E_PNL_SUPPORTED_LPLL_TYPE;

#endif				//_LPLL_TBL_H_
