/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TSP3_TEST_1
#define REG_0040_TSP3 (0x040)
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_2_0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_11_7 Fld(5, 7, AC_MSKW10)//[11:7]
	#define TSP3_REG_PKT_CONVERTER0_CONFIG_0040_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0044_TSP3 (0x044)
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_2_0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_11_7 Fld(5, 7, AC_MSKW10)//[11:7]
	#define TSP3_REG_PKT_CONVERTER_FILE_CONFIG_0044_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0048_TSP3 (0x048)
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_2_0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_11_7 Fld(5, 7, AC_MSKW10)//[11:7]
	#define TSP3_REG_PKT_CONVERTER1_CONFIG_0048_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_004C_TSP3 (0x04C)
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_2_0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_11_7 Fld(5, 7, AC_MSKW10)//[11:7]
	#define TSP3_REG_PKT_CONVERTER2_CONFIG_004C_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0050_TSP3 (0x050)
	#define TSP3_REG_HW3_CONFIG0_0050_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_HW3_CONFIG0_0050_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0054_TSP3 (0x054)
	#define TSP3_REG_HW3_CONFIG1_0054_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_HW3_CONFIG1_0054_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_HW3_CONFIG1_0054_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_HW3_CONFIG1_0054_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_HW3_CONFIG1_0054_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_HW3_CONFIG1_0054_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_HW3_CONFIG1_0054_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_HW3_CONFIG1_0054_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_HW3_CONFIG1_0054_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_HW3_CONFIG1_0054_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_HW3_CONFIG1_0054_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_HW3_CONFIG1_0054_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_HW3_CONFIG1_0054_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_HW3_CONFIG1_0054_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_HW3_CONFIG1_0054_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_HW3_CONFIG1_0054_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0058_TSP3 (0x058)
	#define TSP3_REG_PAUSE_TIME0_0_0058 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_005C_TSP3 (0x05C)
	#define TSP3_REG_PAUSE_TIME0_1_005C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0060_TSP3 (0x060)
	#define TSP3_REG_PAUSE_TIME1_0_0060 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0064_TSP3 (0x064)
	#define TSP3_REG_PAUSE_TIME1_1_0064 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_TSP3 (0x068)
	#define TSP3_REG_PIDFLT_PCR0_0_0068_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP3_REG_PIDFLT_PCR0_0_0068_14_13 Fld(2, 13, AC_MSKB1)//[14:13]
	#define TSP3_REG_PIDFLT_PCR0_0_0068_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_006C_TSP3 (0x06C)
	#define TSP3_REG_PIDFLT_PCR0_1_006C_21_16 Fld(6, 16, AC_MSKB2)//[21:16]
	#define TSP3_REG_PIDFLT_PCR0_1_006C_RESERVED_22 Fld(1, 22, AC_MSKB2)//[22:22]
	#define TSP3_REG_PIDFLT_PCR0_1_006C_RESERVED_23 Fld(1, 23, AC_MSKB2)//[23:23]
#define REG_0070_TSP3 (0x070)
	#define TSP3_REG_PIDFLT_PCR1_0_0070_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP3_REG_PIDFLT_PCR1_0_0070_14_13 Fld(2, 13, AC_MSKB1)//[14:13]
	#define TSP3_REG_PIDFLT_PCR1_0_0070_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0074_TSP3 (0x074)
	#define TSP3_REG_PIDFLT_PCR1_1_0074_21_16 Fld(6, 16, AC_MSKB2)//[21:16]
	#define TSP3_REG_PIDFLT_PCR1_1_0074_RESERVED_22 Fld(1, 22, AC_MSKB2)//[22:22]
	#define TSP3_REG_PIDFLT_PCR1_1_0074_RESERVED_23 Fld(1, 23, AC_MSKB2)//[23:23]
#define REG_0078_TSP3 (0x078)
	#define TSP3_REG_HW3_CONFIG2_0078_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_HW3_CONFIG2_0078_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_HW3_CONFIG2_0078_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_HW3_CONFIG2_0078_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_HW3_CONFIG2_0078_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_HW3_CONFIG2_0078_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_HW3_CONFIG2_0078_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_HW3_CONFIG2_0078_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_HW3_CONFIG2_0078_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_HW3_CONFIG2_0078_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_HW3_CONFIG2_0078_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_HW3_CONFIG2_0078_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_HW3_CONFIG2_0078_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_007C_TSP3 (0x07C)
	#define TSP3_REG_HW3_CONFIG3_007C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0080_TSP3 (0x080)
	#define TSP3_REG_HW_SEMAPHORE0_0080 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0084_TSP3 (0x084)
	#define TSP3_REG_HW_SEMAPHORE1_0084 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0088_TSP3 (0x088)
	#define TSP3_REG_HW_SEMAPHORE2_0088 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_008C_TSP3 (0x08C)
	#define TSP3_REG_ECO0_008C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_ECO0_008C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_ECO0_008C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_ECO0_008C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_ECO0_008C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_ECO0_008C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_ECO0_008C_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP3_REG_ECO0_008C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_ECO0_008C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_ECO0_008C_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_ECO0_008C_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_ECO0_008C_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_ECO0_008C_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_ECO0_008C_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_ECO0_008C_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0090_TSP3 (0x090)
	#define TSP3_REG_ECO1_0090 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0094_TSP3 (0x094)
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_3WIRE_SERIAL_MODE_0094_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_NEW_OVERFLOW_MODE_0094 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_NON_188_CNT_MODE_0094 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_DISABLE_STREAM_ID_CHK_FOR_NAGRA_DONGLE_0094 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_FILTER_STREAM_ID_0_TO_1F_FOR_NAGRA_DONGLE_0094 \
			Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_0098_TSP3 (0x098)
	#define TSP3_REG_NAGRA_DONGLE_SYNC_BYTE_F0_0098 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_NAGRA_DONGLE_SYNC_BYTE_F1_0098 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A0_TSP3 (0x0A0)
	#define TSP3_REG_SYNC_BYTE00_00A0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE01_00A0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A4_TSP3 (0x0A4)
	#define TSP3_REG_SYNC_BYTE02_00A4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE03_00A4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A8_TSP3 (0x0A8)
	#define TSP3_REG_SYNC_BYTE04_00A8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE05_00A8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00AC_TSP3 (0x0AC)
	#define TSP3_REG_SYNC_BYTE06_00AC Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE07_00AC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00B0_TSP3 (0x0B0)
	#define TSP3_REG_SOURCE_ID00_00B0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID01_00B0 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID02_00B0 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID03_00B0 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00B4_TSP3 (0x0B4)
	#define TSP3_REG_SOURCE_ID04_00B4 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID05_00B4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID06_00B4 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID07_00B4 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00B8_TSP3 (0x0B8)
	#define TSP3_REG_SYNC_BYTE_F0_00B8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE_F1_00B8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00BC_TSP3 (0x0BC)
	#define TSP3_REG_SYNC_BYTE_F2_00BC Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE_F3_00BC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C0_TSP3 (0x0C0)
	#define TSP3_REG_SYNC_BYTE_F4_00C0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE_F5_00C0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C4_TSP3 (0x0C4)
	#define TSP3_REG_SYNC_BYTE_F6_00C4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE_F7_00C4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C8_TSP3 (0x0C8)
	#define TSP3_REG_SOURCE_ID_F0_00C8 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID_F1_00C8 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID_F2_00C8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID_F3_00C8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00CC_TSP3 (0x0CC)
	#define TSP3_REG_SOURCE_ID_F4_00CC Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID_F5_00CC Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID_F6_00CC Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID_F7_00CC Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00D0_TSP3 (0x0D0)
	#define TSP3_REG_SYNC_BYTE10_00D0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE11_00D0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00D4_TSP3 (0x0D4)
	#define TSP3_REG_SYNC_BYTE12_00D4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE13_00D4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00D8_TSP3 (0x0D8)
	#define TSP3_REG_SYNC_BYTE14_00D8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE15_00D8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00DC_TSP3 (0x0DC)
	#define TSP3_REG_SYNC_BYTE16_00DC Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE17_00DC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00E0_TSP3 (0x0E0)
	#define TSP3_REG_SOURCE_ID10_00E0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID11_00E0 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID12_00E0 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID13_00E0 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00E4_TSP3 (0x0E4)
	#define TSP3_REG_SOURCE_ID14_00E4 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID15_00E4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID16_00E4 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID17_00E4 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00E8_TSP3 (0x0E8)
	#define TSP3_REG_SYNC_BYTE20_00E8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE21_00E8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00EC_TSP3 (0x0EC)
	#define TSP3_REG_SYNC_BYTE22_00EC Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE23_00EC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00F0_TSP3 (0x0F0)
	#define TSP3_REG_SYNC_BYTE24_00F0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE25_00F0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00F4_TSP3 (0x0F4)
	#define TSP3_REG_SYNC_BYTE26_00F4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_SYNC_BYTE27_00F4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00F8_TSP3 (0x0F8)
	#define TSP3_REG_SOURCE_ID20_00F8 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID21_00F8 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID22_00F8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID23_00F8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00FC_TSP3 (0x0FC)
	#define TSP3_REG_SOURCE_ID24_00FC Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_SOURCE_ID25_00FC Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_SOURCE_ID26_00FC Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_SOURCE_ID27_00FC Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0100_TSP3 (0x100)
	#define TSP3_REG_FIQ0_CONFIG0_0100_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_FIQ0_CONFIG0_0100_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_FIQ0_CONFIG0_0100_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_FIQ0_CONFIG0_0100_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_FIQ0_CONFIG0_0100_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_FIQ0_CONFIG0_0100_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_FIQ0_CONFIG0_0100_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_FIQ0_CONFIG0_0100_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_FIQ0_CONFIG0_0100_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_FIQ0_CONFIG0_0100_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_FIQ0_CONFIG0_0100_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_FIQ0_CONFIG0_0100_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_FIQ0_CONFIG0_0100_13_12 Fld(2, 12, AC_MSKB1)//[13:12]
	#define TSP3_REG_FIQ0_CONFIG0_0100_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_FIQ0_CONFIG0_0100_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0104_TSP3 (0x104)
	#define TSP3_REG_FIQ02MI_HEAD_0_0104 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0108_TSP3 (0x108)
	#define TSP3_REG_FIQ02MI_HEAD_1_0108 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_010C_TSP3 (0x10C)
	#define TSP3_REG_FIQ02MI_TAIL_0_010C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0110_TSP3 (0x110)
	#define TSP3_REG_FIQ02MI_TAIL_1_0110 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0114_TSP3 (0x114)
	#define TSP3_REG_FIQ02MI_MID_0_0114 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0118_TSP3 (0x118)
	#define TSP3_REG_FIQ02MI_MID_1_0118 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_011C_TSP3 (0x11C)
	#define TSP3_REG_FIQ0_RUSH_ADDR_0_011C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0120_TSP3 (0x120)
	#define TSP3_REG_FIQ0_RUSH_ADDR_1_0120 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0124_TSP3 (0x124)
	#define TSP3_REG_FIQ0_CUR_PKT_START_WADR_OFFSET_0_0124 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0128_TSP3 (0x128)
	#define TSP3_REG_FIQ0_CUR_PKT_START_WADR_OFFSET_1_0128 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_012C_TSP3 (0x12C)
	#define TSP3_REG_FIQ0_CONFIG1_012C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_FIQ0_CONFIG1_012C_2_1 Fld(2, 1, AC_MSKB0)//[2:1]
	#define TSP3_REG_FIQ0_CONFIG1_012C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_FIQ0_CONFIG1_012C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_FIQ0_CONFIG1_012C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_FIQ0_CONFIG1_012C_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_FIQ0_CONFIG1_012C_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_FIQ0_CONFIG1_012C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_FIQ0_CONFIG1_012C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_FIQ0_CONFIG1_012C_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_FIQ0_CONFIG1_012C_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_FIQ0_CONFIG1_012C_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_FIQ0_CONFIG1_012C_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_FIQ0_CONFIG1_012C_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_FIQ0_CONFIG1_012C_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0130_TSP3 (0x130)
	#define TSP3_REG_FIQ0_PKT_ADDR_OFFSET_0_0130 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0134_TSP3 (0x134)
	#define TSP3_REG_FIQ0_PKT_ADDR_OFFSET_1_0134 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0138_TSP3 (0x138)
	#define TSP3_REG_FIQ0_CONFIG2_0138_1_0 Fld(2, 0, AC_MSKB0)//[1:0]
	#define TSP3_REG_FIQ0_CONFIG2_0138_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_FIQ0_CONFIG2_0138_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_FIQ0_CONFIG2_0138_5_4 Fld(2, 4, AC_MSKB0)//[5:4]
	#define TSP3_REG_FIQ0_CONFIG2_0138_15_6 Fld(10, 6, AC_MSKW10)//[15:6]
#define REG_013C_TSP3 (0x13C)
	#define TSP3_REG_FIQ0_CONFIG3_013C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0144_TSP3 (0x144)
	#define TSP3_REG_FIQ02MI_WADR_R_0_0144 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0148_TSP3 (0x148)
	#define TSP3_REG_FIQ02MI_WADR_R_1_0148 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_014C_TSP3 (0x14C)
	#define TSP3_REG_FIQ02MI_RADR_R_0_014C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0150_TSP3 (0x150)
	#define TSP3_REG_FIQ02MI_RADR_R_1_0150 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0154_TSP3 (0x154)
	#define TSP3_REG_FIQ0_STATUS_0154_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_FIQ0_STATUS_0154_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_FIQ0_STATUS_0154_4_2 Fld(3, 2, AC_MSKB0)//[4:2]
	#define TSP3_REG_FIQ0_STATUS_0154_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_FIQ0_STATUS_0154_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_FIQ0_STATUS_0154_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0158_TSP3 (0x158)
#define REG_015C_TSP3 (0x15C)

//Page TSP3_TEST_2
#define REG_0164_TSP3 (0x164)
	#define TSP3_REG_CLR_MATCH_SCR_START_CODE_BANK_SEL_0164 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TSP3_REG_MATCH_SCR_START_CODE_SCR_EN_0164 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_CLR_MATCH_SCR_START_CODE_BY_PID_EN_0164 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_CLR_MATCH_SCR_START_CODE_0164 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0168_TSP3 (0x168)
	#define TSP3_REG_CLR_MATCH_SCR_START_CODE_BIT_SEL_0_0168 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_016C_TSP3 (0x16C)
	#define TSP3_REG_CLR_MATCH_SCR_START_CODE_BIT_SEL_1_016C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0180_TSP3 (0x180)
	#define TSP3_REG_FIQ1_CONFIG0_0180_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_FIQ1_CONFIG0_0180_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_FIQ1_CONFIG0_0180_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_FIQ1_CONFIG0_0180_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_FIQ1_CONFIG0_0180_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_FIQ1_CONFIG0_0180_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_FIQ1_CONFIG0_0180_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_FIQ1_CONFIG0_0180_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_FIQ1_CONFIG0_0180_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_FIQ1_CONFIG0_0180_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_FIQ1_CONFIG0_0180_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_FIQ1_CONFIG0_0180_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_FIQ1_CONFIG0_0180_13_12 Fld(2, 12, AC_MSKB1)//[13:12]
	#define TSP3_REG_FIQ1_CONFIG0_0180_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_FIQ1_CONFIG0_0180_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0184_TSP3 (0x184)
	#define TSP3_REG_FIQ12MI_HEAD_0_0184 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0188_TSP3 (0x188)
	#define TSP3_REG_FIQ12MI_HEAD_1_0188 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_018C_TSP3 (0x18C)
	#define TSP3_REG_FIQ12MI_TAIL_0_018C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0190_TSP3 (0x190)
	#define TSP3_REG_FIQ12MI_TAIL_1_0190 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0194_TSP3 (0x194)
	#define TSP3_REG_FIQ12MI_MID_0_0194 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0198_TSP3 (0x198)
	#define TSP3_REG_FIQ12MI_MID_1_0198 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_019C_TSP3 (0x19C)
	#define TSP3_REG_FIQ1_RUSH_ADDR_0_019C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A0_TSP3 (0x1A0)
	#define TSP3_REG_FIQ1_RUSH_ADDR_1_01A0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A4_TSP3 (0x1A4)
	#define TSP3_REG_FIQ1_CUR_PKT_START_WADR_OFFSET_0_01A4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A8_TSP3 (0x1A8)
	#define TSP3_REG_FIQ1_CUR_PKT_START_WADR_OFFSET_1_01A8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01AC_TSP3 (0x1AC)
	#define TSP3_REG_FIQ1_CONFIG1_01AC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_2_1 Fld(2, 1, AC_MSKB0)//[2:1]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_FIQ1_CONFIG1_01AC_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01B0_TSP3 (0x1B0)
	#define TSP3_REG_FIQ1_PKT_ADDR_OFFSET_0_01B0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01B4_TSP3 (0x1B4)
	#define TSP3_REG_FIQ1_PKT_ADDR_OFFSET_1_01B4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01B8_TSP3 (0x1B8)
	#define TSP3_REG_FIQ1_CONFIG2_01B8_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01BC_TSP3 (0x1BC)
	#define TSP3_REG_FIQ1_CONFIG3_01BC_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C4_TSP3 (0x1C4)
	#define TSP3_REG_FIQ12MI_WADR_R_0_01C4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C8_TSP3 (0x1C8)
	#define TSP3_REG_FIQ12MI_WADR_R_1_01C8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01CC_TSP3 (0x1CC)
	#define TSP3_REG_FIQ12MI_RADR_R_0_01CC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D0_TSP3 (0x1D0)
	#define TSP3_REG_FIQ12MI_RADR_R_1_01D0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D4_TSP3 (0x1D4)
	#define TSP3_REG_FIQ1_STATUS_01D4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_FIQ1_STATUS_01D4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_FIQ1_STATUS_01D4_3_2 Fld(2, 2, AC_MSKB0)//[3:2]
	#define TSP3_REG_FIQ1_STATUS_01D4_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_FIQ1_STATUS_01D4_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_FIQ1_STATUS_01D4_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_FIQ1_STATUS_01D4_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_01E4_TSP3 (0x1E4)
	#define TSP3_REG_INTERRUPT_AV_SCRMB_01E4_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP3_REG_INTERRUPT_AV_SCRMB_01E4_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01E8_TSP3 (0x1E8)
	#define TSP3_REG_PATH_PC0_MUX_01E8 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP3_REG_PATH_PCFI_MUX_01E8 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP3_REG_PATH_PC1_MUX_01E8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP3_REG_PATH_PC2_MUX_01E8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01EC_TSP3 (0x1EC)
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_0_01EC_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_0_01EC_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01F0_TSP3 (0x1F0)
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_FI_01F0_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_FI_01F0_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01F4_TSP3 (0x1F4)
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_1_01F4_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_1_01F4_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01F8_TSP3 (0x1F8)
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP3_REG_ALP_PKT_TYPE_IP_FILTER_2_01F8_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP3_REG_ALP_PKT_TYPE_TS_FILTER_2_01F8_15 Fld(1, 15, AC_MSKB1)//[15:15]

