/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
#ifndef _MTK_TV_DRM_DELTA_EDP_H_
#define _MTK_TV_DRM_DELTA_EDP_H_

//-------------------------------------------------------------------------------------------------
// Define & Macro
//-------------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Enum
//------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
// Structure
//-------------------------------------------------------------------------------------------------
#include <video/videomode.h>
// Same values as used by the DP Spec for MISC0 bits 1 and 2
enum mtk_edp_color_format {
	MTK_DP_COLOR_FORMAT_RGB_444     = 0,
	MTK_DP_COLOR_FORMAT_YUV_422     = 1,
	MTK_DP_COLOR_FORMAT_YUV_444     = 2,
	MTK_DP_COLOR_FORMAT_YUV_420     = 3,
	MTK_DP_COLOR_FORMAT_YONLY       = 4,
	MTK_DP_COLOR_FORMAT_RAW         = 5,
	MTK_DP_COLOR_FORMAT_RESERVED    = 6,
	MTK_DP_COLOR_FORMAT_DEFAULT     = MTK_DP_COLOR_FORMAT_RGB_444,
	MTK_DP_COLOR_FORMAT_UNKNOWN     = 15,
};

// Same values as used for DP Spec MISC0 bits 5,6,7
enum mtk_edp_color_depth {
	MTK_DP_COLOR_DEPTH_6BIT       = 0,
	MTK_DP_COLOR_DEPTH_8BIT       = 1,
	MTK_DP_COLOR_DEPTH_10BIT      = 2,
	MTK_DP_COLOR_DEPTH_12BIT      = 3,
	MTK_DP_COLOR_DEPTH_16BIT      = 4,
	MTK_DP_COLOR_DEPTH_UNKNOWN    = 5,
};

// Multiple of 0.27Gbps
enum mtk_edp_linkrate {
	MTK_DP_LINKRATE_RBR	=  0x6,
	MTK_DP_LINKRATE_HBR	=  0xA,
	MTK_DP_LINKRATE_HBR2	= 0x14,
	MTK_DP_LINKRATE_HBR25	= 0x19,
	MTK_DP_LINKRATE_HBR3	= 0x1E,
};

struct mtk_edp_timings {
	struct videomode vm;

	u16 htotal;
	u16 vtotal;
	u8 frame_rate;
	u32 pix_rate_khz;
};

struct mtk_edp_info {
	enum mtk_edp_color_depth depth;
	enum mtk_edp_color_format format;
	struct mtk_edp_timings timings;
	u8 port_num;
	enum mtk_edp_linkrate link_rate;
	u8 sc_clk_div;
};

extern struct platform_driver mtk_edp_driver;
//-------------------------------------------------------------------------------------------------
// Function
//-------------------------------------------------------------------------------------------------
extern int mtk_edp_poweron_all(void);
extern void mtk_edp_poweroff_all(void);
extern int mtk_edp_train_all(void);
extern void mtk_edp_disable_all(void);
extern void sml_change_RX_irq_status(int status);
extern void mtk_edp_change_train_forcepass_status(int status);
extern void mtk_edp_parse_timings(struct mtk_edp_info *edp_info_in);

#endif
