/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_E3_CKGEN00_PM_H
#define _DT_BINDINGS_CLK_MT5896_E3_CKGEN00_PM_H

#define REG_CKG_CM4 0x0
#define REG_CKG_CM4_S 0
#define REG_CKG_CM4_E 3
#define REG_CKG_CM4_CORE 0x4
#define REG_CKG_CM4_CORE_S 0
#define REG_CKG_CM4_CORE_E 3
#define REG_CKG_CM4_DFS 0x8
#define REG_CKG_CM4_DFS_S 0
#define REG_CKG_CM4_DFS_E 3
#define REG_CKG_CM4_SYSTICK 0xc
#define REG_CKG_CM4_SYSTICK_S 0
#define REG_CKG_CM4_SYSTICK_E 2
#define REG_CKG_CM4_TCK 0x10
#define REG_CKG_CM4_TCK_S 0
#define REG_CKG_CM4_TCK_E 2
#define REG_CKG_CM4_TSVALUEB 0x14
#define REG_CKG_CM4_TSVALUEB_S 0
#define REG_CKG_CM4_TSVALUEB_E 2
#define REG_CKG_CODEC_I2S_MCK 0x18
#define REG_CKG_CODEC_I2S_MCK_S 0
#define REG_CKG_CODEC_I2S_MCK_E 3
#define REG_CKG_CODEC_I2S_RX_BCK 0x1c
#define REG_CKG_CODEC_I2S_RX_BCK_S 0
#define REG_CKG_CODEC_I2S_RX_BCK_E 4
#define REG_CKG_CODEC_I2S_RX_MS_BCK_P 0x20
#define REG_CKG_CODEC_I2S_RX_MS_BCK_P_S 0
#define REG_CKG_CODEC_I2S_RX_MS_BCK_P_E 4
#define REG_CKG_DIG_MIC 0x24
#define REG_CKG_DIG_MIC_S 0
#define REG_CKG_DIG_MIC_E 3
#define REG_CKG_I2S_RX_BCK_DG 0x28
#define REG_CKG_I2S_RX_BCK_DG_S 0
#define REG_CKG_I2S_RX_BCK_DG_E 4
#define REG_CKG_NF_SYNTH_REF 0x2c
#define REG_CKG_NF_SYNTH_REF_S 0
#define REG_CKG_NF_SYNTH_REF_E 4
#define REG_CKG_PAGANINI_IMI 0x30
#define REG_CKG_PAGANINI_IMI_S 0
#define REG_CKG_PAGANINI_IMI_E 3
#define REG_CKG_PAGANINI_IMI_DFS 0x34
#define REG_CKG_PAGANINI_IMI_DFS_S 0
#define REG_CKG_PAGANINI_IMI_DFS_E 3
#define REG_CKG_PLL2PAGADIV 0x38
#define REG_CKG_PLL2PAGADIV_S 0
#define REG_CKG_PLL2PAGADIV_E 2
#define REG_CKG_SRC_A1_256FSI 0x3c
#define REG_CKG_SRC_A1_256FSI_S 0
#define REG_CKG_SRC_A1_256FSI_E 3
#define REG_CKG_PAGA_PLL_SEL 0x40
#define REG_CKG_PAGA_PLL_SEL_S 0
#define REG_CKG_PAGA_PLL_SEL_E 4
#define REG_CKG_VREC_MAC 0x44
#define REG_CKG_VREC_MAC_S 0
#define REG_CKG_VREC_MAC_E 4
#define REG_CKG_XTAL_24M_PAGANINI 0x48
#define REG_CKG_XTAL_24M_PAGANINI_S 0
#define REG_CKG_XTAL_24M_PAGANINI_E 1
#define REG_CKG_PAGANINI_IMI_DIV2 0x4c
#define REG_CKG_PAGANINI_IMI_DIV2_S 0
#define REG_CKG_PAGANINI_IMI_DIV2_E 2
#define REG_CKG_SMI_PM 0x58
#define REG_CKG_SMI_PM_S 0
#define REG_CKG_SMI_PM_E 1
#define REG_CKG_SMI_PM_USB_PCIE 0x58
#define REG_CKG_SMI_PM_USB_PCIE_S 8
#define REG_CKG_SMI_PM_USB_PCIE_E 9
#define REG_CKG_SMI_DIV2_PM 0x5c
#define REG_CKG_SMI_DIV2_PM_S 0
#define REG_CKG_SMI_DIV2_PM_E 1
#define REG_CKG_CEC 0x70
#define REG_CKG_CEC_S 0
#define REG_CKG_CEC_E 3
#define REG_CKG_CEC1 0x74
#define REG_CKG_CEC1_S 0
#define REG_CKG_CEC1_E 3
#define REG_CKG_CEC2 0x78
#define REG_CKG_CEC2_S 0
#define REG_CKG_CEC2_E 3
#define REG_CKG_CEC3 0x7c
#define REG_CKG_CEC3_S 0
#define REG_CKG_CEC3_E 3
#define REG_CKG_DDC 0x80
#define REG_CKG_DDC_S 0
#define REG_CKG_DDC_E 4
#define REG_CKG_DVI_RAW0 0x84
#define REG_CKG_DVI_RAW0_S 0
#define REG_CKG_DVI_RAW0_E 2
#define REG_CKG_DVI_RAW1 0x88
#define REG_CKG_DVI_RAW1_S 0
#define REG_CKG_DVI_RAW1_E 2
#define REG_CKG_DVI_RAW2 0x8c
#define REG_CKG_DVI_RAW2_S 0
#define REG_CKG_DVI_RAW2_E 2
#define REG_CKG_DVI_RAW3 0x90
#define REG_CKG_DVI_RAW3_S 0
#define REG_CKG_DVI_RAW3_E 2
#define REG_CKG_HOTPLUG 0x94
#define REG_CKG_HOTPLUG_S 0
#define REG_CKG_HOTPLUG_E 3
#define REG_CKG_SCDC_P0 0x98
#define REG_CKG_SCDC_P0_S 0
#define REG_CKG_SCDC_P0_E 1
#define REG_CKG_SCDC_P1 0x9c
#define REG_CKG_SCDC_P1_S 0
#define REG_CKG_SCDC_P1_E 1
#define REG_CKG_SCDC_P2 0xa0
#define REG_CKG_SCDC_P2_S 0
#define REG_CKG_SCDC_P2_E 1
#define REG_CKG_SCDC_P3 0xa4
#define REG_CKG_SCDC_P3_S 0
#define REG_CKG_SCDC_P3_E 1
#define REG_CKG_SD 0xc8
#define REG_CKG_SD_S 0
#define REG_CKG_SD_E 4
#define REG_CKG_GMAC_RX 0xd4
#define REG_CKG_GMAC_RX_S 0
#define REG_CKG_GMAC_RX_E 3
#define REG_CKG_GMAC_TX 0xd8
#define REG_CKG_GMAC_TX_S 0
#define REG_CKG_GMAC_TX_E 3
#define REG_CKG_GMAC_TX_PAD 0xdc
#define REG_CKG_GMAC_TX_PAD_S 0
#define REG_CKG_GMAC_TX_PAD_E 2
#define REG_CKG_MCU_BUS_PM 0xe8
#define REG_CKG_MCU_BUS_PM_S 0
#define REG_CKG_MCU_BUS_PM_E 4
#define REG_CKG_MCU_PM 0xec
#define REG_CKG_MCU_PM_S 0
#define REG_CKG_MCU_PM_E 4
#define REG_CKG_MCU_PM_PAGANINI 0xec
#define REG_CKG_MCU_PM_PAGANINI_S 8
#define REG_CKG_MCU_PM_PAGANINI_E 9
#define REG_CKG_MCU_PM_PM_USB_PCIE 0xec
#define REG_CKG_MCU_PM_PM_USB_PCIE_S 10
#define REG_CKG_MCU_PM_PM_USB_PCIE_E 11
#define REG_CKG_MIIC0_PM 0xf0
#define REG_CKG_MIIC0_PM_S 0
#define REG_CKG_MIIC0_PM_E 3
#define REG_CKG_MIIC1_PM 0xf4
#define REG_CKG_MIIC1_PM_S 0
#define REG_CKG_MIIC1_PM_E 3
#define REG_CKG_SPI_PM 0xf8
#define REG_CKG_SPI_PM_S 0
#define REG_CKG_SPI_PM_E 4
#define REG_CKG_UART0_PM 0xfc
#define REG_CKG_UART0_PM_S 0
#define REG_CKG_UART0_PM_E 3
#define REG_CKG_UART0_PM_SYNTH 0x100
#define REG_CKG_UART0_PM_SYNTH_S 0
#define REG_CKG_UART0_PM_SYNTH_E 3
#define REG_CKG_UART1_PM 0x104
#define REG_CKG_UART1_PM_S 0
#define REG_CKG_UART1_PM_E 3
#define REG_CKG_UART1_PM_SYNTH 0x108
#define REG_CKG_UART1_PM_SYNTH_S 0
#define REG_CKG_UART1_PM_SYNTH_E 3
#define REG_CKG_FUART0_PM 0x10c
#define REG_CKG_FUART0_PM_S 0
#define REG_CKG_FUART0_PM_E 3
#define REG_CKG_FUART0_PM_SYNTH 0x110
#define REG_CKG_FUART0_PM_SYNTH_S 0
#define REG_CKG_FUART0_PM_SYNTH_E 3
#define REG_CKG_XIU2SRAM 0x114
#define REG_CKG_XIU2SRAM_S 0
#define REG_CKG_XIU2SRAM_E 2
#define REG_CKG_125M_TX_EEE 0x128
#define REG_CKG_125M_TX_EEE_S 0
#define REG_CKG_125M_TX_EEE_E 0
#define REG_CKG_CLK_25M_RX 0x128
#define REG_CKG_CLK_25M_RX_S 1
#define REG_CKG_CLK_25M_RX_E 1
#define REG_CKG_CLK_2P5M_RX 0x128
#define REG_CKG_CLK_2P5M_RX_S 2
#define REG_CKG_CLK_2P5M_RX_E 2
#define REG_CKG_DACTX 0x128
#define REG_CKG_DACTX_S 3
#define REG_CKG_DACTX_E 3
#define REG_CKG_EPHY_RX 0x128
#define REG_CKG_EPHY_RX_S 4
#define REG_CKG_EPHY_RX_E 4
#define REG_CKG_LPI 0x128
#define REG_CKG_LPI_S 5
#define REG_CKG_LPI_E 5
#define REG_CKG_LS 0x128
#define REG_CKG_LS_S 6
#define REG_CKG_LS_E 6
#define REG_CKG_MII_RX 0x128
#define REG_CKG_MII_RX_S 7
#define REG_CKG_MII_RX_E 7
#define REG_CKG_MII_RX_FREE 0x128
#define REG_CKG_MII_RX_FREE_S 8
#define REG_CKG_MII_RX_FREE_E 8
#define REG_CKG_MII_TX 0x128
#define REG_CKG_MII_TX_S 9
#define REG_CKG_MII_TX_E 9
#define REG_CKG_RX 0x128
#define REG_CKG_RX_S 10
#define REG_CKG_RX_E 10
#define REG_CKG_DAC1X 0x128
#define REG_CKG_DAC1X_S 11
#define REG_CKG_DAC1X_E 11
#define REG_CKG_DAC2X 0x128
#define REG_CKG_DAC2X_S 12
#define REG_CKG_DAC2X_E 12
#define REG_CKG_25M_TX 0x12c
#define REG_CKG_25M_TX_S 0
#define REG_CKG_25M_TX_E 0
#define REG_CKG_2P5M_TX 0x12c
#define REG_CKG_2P5M_TX_S 1
#define REG_CKG_2P5M_TX_E 1
#define REG_CKG_ADCPLL_TEST 0x12c
#define REG_CKG_ADCPLL_TEST_S 2
#define REG_CKG_ADCPLL_TEST_E 2
#define REG_CKG_RX_2 0x12c
#define REG_CKG_RX_2_S 3
#define REG_CKG_RX_2_E 3
#define REG_CKG_XIN 0x12c
#define REG_CKG_XIN_S 4
#define REG_CKG_XIN_E 4
#define REG_CKG_IR 0x148
#define REG_CKG_IR_S 0
#define REG_CKG_IR_E 4
#define REG_CKG_KREF 0x158
#define REG_CKG_KREF_S 0
#define REG_CKG_KREF_E 3
#define REG_CKG_RTC2 0x15c
#define REG_CKG_RTC2_S 0
#define REG_CKG_RTC2_E 1
#define REG_CKG_RTC 0x160
#define REG_CKG_RTC_S 0
#define REG_CKG_RTC_E 4
#define REG_CKG_SAR 0x164
#define REG_CKG_SAR_S 0
#define REG_CKG_SAR_E 4
#define REG_CKG_PM_SLEEP 0x168
#define REG_CKG_PM_SLEEP_S 0
#define REG_CKG_PM_SLEEP_E 4
#define REG_CKG_PWM_PM 0x184
#define REG_CKG_PWM_PM_S 0
#define REG_CKG_PWM_PM_E 2
#define REG_CKG_PM_SSUSB_DMA_CTL 0x190
#define REG_CKG_PM_SSUSB_DMA_CTL_S 0
#define REG_CKG_PM_SSUSB_DMA_CTL_E 1
#define REG_CKG_PM_SSUSB_FRMCNT_CTL 0x194
#define REG_CKG_PM_SSUSB_FRMCNT_CTL_S 0
#define REG_CKG_PM_SSUSB_FRMCNT_CTL_E 2
#define REG_CKG_PM_SSUSB_PCLK_CTL 0x198
#define REG_CKG_PM_SSUSB_PCLK_CTL_S 0
#define REG_CKG_PM_SSUSB_PCLK_CTL_E 2
#define REG_CKG_PM_SSUSB_SCL_CTL 0x19c
#define REG_CKG_PM_SSUSB_SCL_CTL_S 0
#define REG_CKG_PM_SSUSB_SCL_CTL_E 2
#define REG_CKG_PM_SSUSB_SDIN_CTL 0x1a0
#define REG_CKG_PM_SSUSB_SDIN_CTL_S 0
#define REG_CKG_PM_SSUSB_SDIN_CTL_E 2
#define REG_CKG_PM_SSUSB_SYS_CTL 0x1a4
#define REG_CKG_PM_SSUSB_SYS_CTL_S 0
#define REG_CKG_PM_SSUSB_SYS_CTL_E 1
#define REG_CKG_PM_SSUSB_UTMI_CTL 0x1a8
#define REG_CKG_PM_SSUSB_UTMI_CTL_S 0
#define REG_CKG_PM_SSUSB_UTMI_CTL_E 2
#define REG_CKG_PM_SSUSB_XHCI_CTL 0x1ac
#define REG_CKG_PM_SSUSB_XHCI_CTL_S 0
#define REG_CKG_PM_SSUSB_XHCI_CTL_E 1
#define REG_CKG_PM_PEXTP 0x1b0
#define REG_CKG_PM_PEXTP_S 0
#define REG_CKG_PM_PEXTP_E 3
#define REG_PM_TEST_ENABLE 0x1c0
#define REG_PM_TEST_ENABLE_S 0
#define REG_PM_TEST_ENABLE_E 0
#define REG_PM_TEST_DIV_SEL 0x1c0
#define REG_PM_TEST_DIV_SEL_S 4
#define REG_PM_TEST_DIV_SEL_E 6
#define REG_PM_TEST_SRC_SEL 0x1c0
#define REG_PM_TEST_SRC_SEL_S 8
#define REG_PM_TEST_SRC_SEL_E 15
#define REG_PM_USB_PCIE_TEST_ENABLE 0x1c4
#define REG_PM_USB_PCIE_TEST_ENABLE_S 0
#define REG_PM_USB_PCIE_TEST_ENABLE_E 0
#define REG_PM_USB_PCIE_TEST_DIV_SEL 0x1c4
#define REG_PM_USB_PCIE_TEST_DIV_SEL_S 4
#define REG_PM_USB_PCIE_TEST_DIV_SEL_E 6
#define REG_PM_USB_PCIE_TEST_SRC_SEL 0x1c4
#define REG_PM_USB_PCIE_TEST_SRC_SEL_S 8
#define REG_PM_USB_PCIE_TEST_SRC_SEL_E 15
#define REG_PM_ETH_TEST_ENABLE 0x1c8
#define REG_PM_ETH_TEST_ENABLE_S 0
#define REG_PM_ETH_TEST_ENABLE_E 0
#define REG_PM_ETH_TEST_DIV_SEL 0x1c8
#define REG_PM_ETH_TEST_DIV_SEL_S 4
#define REG_PM_ETH_TEST_DIV_SEL_E 6
#define REG_PM_ETH_TEST_SRC_SEL 0x1c8
#define REG_PM_ETH_TEST_SRC_SEL_S 8
#define REG_PM_ETH_TEST_SRC_SEL_E 15
#define REG_PM_EPHY_TEST_ENABLE 0x1cc
#define REG_PM_EPHY_TEST_ENABLE_S 0
#define REG_PM_EPHY_TEST_ENABLE_E 0
#define REG_PM_EPHY_TEST_DIV_SEL 0x1cc
#define REG_PM_EPHY_TEST_DIV_SEL_S 4
#define REG_PM_EPHY_TEST_DIV_SEL_E 6
#define REG_PM_EPHY_TEST_SRC_SEL 0x1cc
#define REG_PM_EPHY_TEST_SRC_SEL_S 8
#define REG_PM_EPHY_TEST_SRC_SEL_E 15
#define REG_PAGANINI_TEST_ENABLE 0x1d0
#define REG_PAGANINI_TEST_ENABLE_S 0
#define REG_PAGANINI_TEST_ENABLE_E 0
#define REG_PAGANINI_TEST_DIV_SEL 0x1d0
#define REG_PAGANINI_TEST_DIV_SEL_S 4
#define REG_PAGANINI_TEST_DIV_SEL_E 6
#define REG_PAGANINI_TEST_SRC_SEL 0x1d0
#define REG_PAGANINI_TEST_SRC_SEL_S 8
#define REG_PAGANINI_TEST_SRC_SEL_E 15
#define REG_CKGEN00_PM_DUMMY0 0x1f8
#define REG_CKGEN00_PM_DUMMY0_S 0
#define REG_CKGEN00_PM_DUMMY0_E 15
#define REG_CKGEN00_PM_DUMMY1 0x1fc
#define REG_CKGEN00_PM_DUMMY1_S 0
#define REG_CKGEN00_PM_DUMMY1_E 15
#endif
