/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TSP7_TEST
#define REG_0000_TSP7 (0x000)
	#define TSP7_REG_PVR_REG_PINGPONG_EN_0000 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP7_REG_PVR_STR2MI_EN_0000 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP7_REG_PVR_STR2MI_RST_WADR_0000 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP7_REG_PVR_STR2MI_PAUSE_0000 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP7_REG_PVR_LPCR1_RLD_0000 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP7_REG_PVR_BURST_LEN_0000 Fld(2, 5, AC_MSKB0)//[6:5]
	#define TSP7_REG_PVR_LPCR1_WLD_0000 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP7_REG_PVR_ALIGN_EN_0000 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP7_REG_PVR_STR2MI_DSWAP_0000 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP7_REG_PVR_STR2MI_BT_ORDER_0000 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP7_REG_REC_DATA_INV_EN_0000 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP7_REG_PVR_BLOCK_DIS_0000 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP7_REG_PVR_PKT192_EN_0000 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP7_REG_CLK_27M_90K_0000 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0004_TSP7 (0x004)
	#define TSP7_REG_PVR_STR2MI_HEAD1_0_0004_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0008_TSP7 (0x008)
	#define TSP7_REG_PVR_STR2MI_HEAD1_1_0008_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_000C_TSP7 (0x00C)
	#define TSP7_REG_PVR_STR2MI_MID1_0_000C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0010_TSP7 (0x010)
	#define TSP7_REG_PVR_STR2MI_MID1_1_0010_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_0014_TSP7 (0x014)
	#define TSP7_REG_PVR_STR2MI_TAIL1_0_0014_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0018_TSP7 (0x018)
	#define TSP7_REG_PVR_STR2MI_TAIL1_1_0018_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_001C_TSP7 (0x01C)
	#define TSP7_REG_PVR_STR2MI_HEAD2_0_001C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0020_TSP7 (0x020)
	#define TSP7_REG_PVR_STR2MI_HEAD2_1_0020_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_0024_TSP7 (0x024)
	#define TSP7_REG_PVR_STR2MI_MID2_0_0024_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0028_TSP7 (0x028)
	#define TSP7_REG_PVR_STR2MI_MID2_1_0028_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_002C_TSP7 (0x02C)
	#define TSP7_REG_PVR_STR2MI_TAIL2_0_002C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0030_TSP7 (0x030)
	#define TSP7_REG_PVR_STR2MI_TAIL2_1_0030_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_0034_TSP7 (0x034)
	#define TSP7_REG_PVR_SRAM_SD_EN_0034 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP7_REG_PVR_FLUSH_DATA_0034 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP7_REG_PVR_STR2MI_WP_LD_0034 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP7_REG_PVR_CLR_0034 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP7_REG_PVR_DMA_FLUSH_EN_0034 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP7_REG_PVR_DMAW_PROTECT_EN_0034 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP7_REG_PVR_RECORD_DIS_SYNC_EN_0034 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP7_REG_PVR_MIU_HIGHPRI_0034 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP7_REG_PVR_RECORD_ALL_OLD_0034 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP7_REG_PVR_WRITE_POINTER_TO_NEXT_ADDR_EN_0034 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP7_REG_MIU_SEL_PVR_0034 Fld(2, 13, AC_MSKB1)//[14:13]
	#define TSP7_REG_RD_ADDR_ALIGN_EN_0034 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0038_TSP7 (0x038)
	#define TSP7_REG_PVR_DMAW_LBND_0_0038 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_003C_TSP7 (0x03C)
	#define TSP7_REG_PVR_DMAW_LBND_1_003C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0040_TSP7 (0x040)
	#define TSP7_REG_PVR_DMAW_UBND_0_0040 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0044_TSP7 (0x044)
	#define TSP7_REG_PVR_DMAW_UBND_1_0044 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0048_TSP7 (0x048)
	#define TSP7_REG_PVR_LPCR1_0_0048 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_004C_TSP7 (0x04C)
	#define TSP7_REG_PVR_LPCR1_1_004C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0054_TSP7 (0x054)
	#define TSP7_REG_PVR_DMAW_WADDR_ERR_0_0054 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0058_TSP7 (0x058)
	#define TSP7_REG_PVR_DMAW_WADDR_ERR_1_0058 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_005C_TSP7 (0x05C)
	#define TSP7_REG_PVR2MI_MOBF_INDEX0_005C Fld(5, 0, AC_MSKB0)//[4:0]
	#define TSP7_REG_PVR2MI_MOBF_INDEX1_005C Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0060_TSP7 (0x060)
	#define TSP7_REG_PVR_STR2MI_WADR_R_0_0060 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0064_TSP7 (0x064)
	#define TSP7_REG_PVR_STR2MI_WADR_R_1_0064 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_TSP7 (0x068)
	#define TSP7_REG_FLUSH_DATA_PVR_STATUS_0068 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP7_REG_PVR_FIFO_STATUS_0068_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP7_REG_PVR_FIFO_STATUS_0068_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP7_REG_PVR_FIFO_STATUS_0068_4_3 Fld(2, 3, AC_MSKB0)//[4:3]
	#define TSP7_REG_PVR_EVER_OVERFLOW_0068 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_0078_TSP7 (0x078)
	#define TSP7_REG_PVR_LPCR1_R_0_0078 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_007C_TSP7 (0x07C)
	#define TSP7_REG_PVR_LPCR1_R_1_007C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0080_TSP7 (0x080)
	#define TSP7_REG_PVR4_REG_PINGPONG_EN_0080 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP7_REG_PVR4_STR2MI_EN_0080 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP7_REG_PVR4_STR2MI_RST_WADR_0080 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP7_REG_PVR4_STR2MI_PAUSE_0080 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP7_REG_PVR4_LPCR1_RLD_0080 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP7_REG_PVR4_BURST_LEN_0080 Fld(2, 5, AC_MSKB0)//[6:5]
	#define TSP7_REG_PVR4_LPCR1_WLD_0080 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP7_REG_PVR4_ALIGN_EN_0080 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP7_REG_PVR4_STR2MI_DSWAP_0080 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP7_REG_PVR4_STR2MI_BT_ORDER_0080 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP7_REG_REC_DATA_INV_EN_PVR4_0080 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP7_REG_PVR4_BLOCK_DIS_0080 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP7_REG_PVR4_PKT192_EN_0080 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP7_REG_CLK_27M_90K_PVR4_0080 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0084_TSP7 (0x084)
	#define TSP7_REG_PVR4_STR2MI_HEAD1_0_0084_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0088_TSP7 (0x088)
	#define TSP7_REG_PVR4_STR2MI_HEAD1_1_0088_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_008C_TSP7 (0x08C)
	#define TSP7_REG_PVR4_STR2MI_MID1_0_008C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0090_TSP7 (0x090)
	#define TSP7_REG_PVR4_STR2MI_MID1_1_0090_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_0094_TSP7 (0x094)
	#define TSP7_REG_PVR4_STR2MI_TAIL1_0_0094_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0098_TSP7 (0x098)
	#define TSP7_REG_PVR4_STR2MI_TAIL1_1_0098_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_009C_TSP7 (0x09C)
	#define TSP7_REG_PVR4_STR2MI_HEAD2_0_009C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A0_TSP7 (0x0A0)
	#define TSP7_REG_PVR4_STR2MI_HEAD2_1_00A0_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_00A4_TSP7 (0x0A4)
	#define TSP7_REG_PVR4_STR2MI_MID2_0_00A4_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A8_TSP7 (0x0A8)
	#define TSP7_REG_PVR4_STR2MI_MID2_1_00A8_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_00AC_TSP7 (0x0AC)
	#define TSP7_REG_PVR4_STR2MI_TAIL2_0_00AC_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B0_TSP7 (0x0B0)
	#define TSP7_REG_PVR4_STR2MI_TAIL2_1_00B0_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_00B4_TSP7 (0x0B4)
	#define TSP7_REG_PVR4_SRAM_SD_EN_00B4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP7_REG_PVR4_FLUSH_DATA_00B4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP7_REG_PVR4_STR2MI_WP_LD_00B4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP7_REG_PVR4_CLR_00B4 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP7_REG_PVR4_DMA_FLUSH_EN_00B4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP7_REG_PVR4_DMAW_PROTECT_EN_00B4 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP7_REG_PVR4_RECORD_DIS_SYNC_EN_00B4 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP7_REG_PVR4_MIU_HIGHPRI_00B4 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP7_REG_PVR4_RECORD_ALL_OLD_00B4 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP7_REG_PVR4_WRITE_POINTER_TO_NEXT_ADDR_EN_00B4 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP7_REG_MIU_SEL_PVR4_00B4 Fld(2, 13, AC_MSKB1)//[14:13]
	#define TSP7_REG_RD_ADDR_ALIGN_EN_PVR4_00B4 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00B8_TSP7 (0x0B8)
	#define TSP7_REG_PVR4_DMAW_LBND_0_00B8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00BC_TSP7 (0x0BC)
	#define TSP7_REG_PVR4_DMAW_LBND_1_00BC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C0_TSP7 (0x0C0)
	#define TSP7_REG_PVR4_DMAW_UBND_0_00C0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C4_TSP7 (0x0C4)
	#define TSP7_REG_PVR4_DMAW_UBND_1_00C4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C8_TSP7 (0x0C8)
	#define TSP7_REG_PVR4_LPCR1_0_00C8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00CC_TSP7 (0x0CC)
	#define TSP7_REG_PVR4_LPCR1_1_00CC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00D4_TSP7 (0x0D4)
	#define TSP7_REG_PVR4_DMAW_WADDR_ERR_0_00D4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00D8_TSP7 (0x0D8)
	#define TSP7_REG_PVR4_DMAW_WADDR_ERR_1_00D8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00DC_TSP7 (0x0DC)
	#define TSP7_REG_PVR42MI_MOBF_INDEX0_00DC Fld(5, 0, AC_MSKB0)//[4:0]
	#define TSP7_REG_PVR42MI_MOBF_INDEX1_00DC Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_00E0_TSP7 (0x0E0)
	#define TSP7_REG_PVR4_STR2MI_WADR_R_0_00E0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E4_TSP7 (0x0E4)
	#define TSP7_REG_PVR4_STR2MI_WADR_R_1_00E4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E8_TSP7 (0x0E8)
	#define TSP7_REG_FLUSH_DATA_PVR4_STATUS_00E8 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP7_REG_PVR4_FIFO_STATUS_00E8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP7_REG_PVR4_FIFO_STATUS_00E8_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP7_REG_PVR4_FIFO_STATUS_00E8_4_3 Fld(2, 3, AC_MSKB0)//[4:3]
	#define TSP7_REG_PVR4_EVER_OVERFLOW_00E8 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_00F8_TSP7 (0x0F8)
	#define TSP7_REG_PVR4_LPCR1_R_0_00F8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00FC_TSP7 (0x0FC)
	#define TSP7_REG_PVR4_LPCR1_R_1_00FC Fld(16, 0, AC_FULLW10)//[15:0]

