/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2022 MediaTek Inc.
 */

#ifndef __MDLA_PLAT_HW_REG_H__
#define __MDLA_PLAT_HW_REG_H__
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/time.h>

extern u32 x32_aia_top_base;
extern u32 apu_conn_base;
extern u32 apu_sctrl_base;
extern u32 apu_edma2_base;
extern u32 apu_vcore_base;
extern u32 apu_mdla0_base;
extern u32 mdla_cmde_base;

#define APMCU_RIUBASE 0x1C000000
#define RIU_ADDR(bank, offset)		(APMCU_RIUBASE + ((bank<<8)<<1) + (offset<<2))
#define REG_OFFSET_SHIFT_BITS		2

#define CKGEN00	0x1020
#define TZPC_AID_0 0x1203
#define TZPC_AID_1 0x1204
#define IOMMU_LOCAL_SSC3 0x153b
#define IOMMU_LOCAL_SSC4 0x153c
#define IOMMU_GLOBAL 0x120e
#define MCUSYS_XIU_BRIDGE 0x2009
#define X32_APUSYS (0x2800)
#define X32_APUSYS_BASE (X32_APUSYS<<9)

#define APU_CONN_BASE (APMCU_RIUBASE + X32_APUSYS_BASE + apu_conn_base)
#define APU_CONN_CG_CON	((phys_addr_t)(APU_CONN_BASE+0x000))
#define APU_CONN_CG_SET	((phys_addr_t)(APU_CONN_BASE+0x004))
#define APU_CONN_CG_CLR	((phys_addr_t)(APU_CONN_BASE+0x008))
#define APU_CONN_SW_RST	((phys_addr_t)(APU_CONN_BASE+0x00C))
#define APU_CONN_MBIST_DEFAULT_DELSEL	((phys_addr_t)(APU_CONN_BASE+0x2D0))

#define APU_SCTRL_BASE (APMCU_RIUBASE + X32_APUSYS_BASE + apu_sctrl_base)
#define APU_SCTRL_PGRMP_SCTRL_SECUREFW	((phys_addr_t)(APU_SCTRL_BASE+0x000))
#define APU_SCTRL_PGRMP_SCTRL_MDLA_CORE0_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x308))
#define APU_SCTRL_PGRMP_SCTRL_MDLA_CORE1_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x30C))
#define APU_SCTRL_PGRMP_SCTRL_VP6_CORE0_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x310))
#define APU_SCTRL_PGRMP_SCTRL_VP6_CORE1_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x314))
#define APU_SCTRL_PGRMP_SCTRL_VP6_CORE2_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x318))
#define APU_SCTRL_PGRMP_SCTRL_EDMA0_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x31C))
#define APU_SCTRL_PGRMP_SCTRL_EDMA1_CTXT	((phys_addr_t)(APU_SCTRL_BASE+0x320))

#define APU_EDMA_0_BASE (APMCU_RIUBASE + X32_APUSYS_BASE + apu_edma2_base)
#define APU_EDMA_0_APU_EDMA2_CTL_0	((phys_addr_t)(APU_EDMA_0_BASE+0x000))
#define APU_EDMA_0_APU_EDMA2_CFG_0	((phys_addr_t)(APU_EDMA_0_BASE+0x004))
#define APU_EDMA_0_APU_EDMA2_INTR_MASK	((phys_addr_t)(APU_EDMA_0_BASE+0x008))
#define APU_EDMA_0_APU_EDMA2_ERR_INTR_MASK	((phys_addr_t)(APU_EDMA_0_BASE+0x00C))
#define APU_EDMA_0_APU_EDMA2_INTR_STATUS	((phys_addr_t)(APU_EDMA_0_BASE+0x010))
#define APU_EDMA_0_APU_EDMA2_ERR_STATUS	((phys_addr_t)(APU_EDMA_0_BASE+0x014))
#define APU_EDMA_0_APU_EDMA2_FILL_VALUE	((phys_addr_t)(APU_EDMA_0_BASE+0x018))
#define APU_EDMA_0_APU_EDMA2_UFBC_CFG_0	((phys_addr_t)(APU_EDMA_0_BASE+0x020))
#define APU_EDMA_0_APU_EDMA2_UFBC_CFG_1	((phys_addr_t)(APU_EDMA_0_BASE+0x024))
#define APU_EDMA_0_APU_EDMA2_UFBC_INFO_0	((phys_addr_t)(APU_EDMA_0_BASE+0x028))
#define APU_EDMA_0_APU_EDMA2_UFBC_INFO_1	((phys_addr_t)(APU_EDMA_0_BASE+0x02C))
#define APU_EDMA_0_APU_EDMA2_UFBDC_CFG_0	((phys_addr_t)(APU_EDMA_0_BASE+0x030))
#define APU_EDMA_0_APU_EDMA2_UFBDC_CFG_1	((phys_addr_t)(APU_EDMA_0_BASE+0x034))
#define APU_EDMA_0_APU_EDMA2_UFBDC_INFO_0	((phys_addr_t)(APU_EDMA_0_BASE+0x038))
#define APU_EDMA_0_APU_EDMA2_CMPR_DBG_SEL	((phys_addr_t)(APU_EDMA_0_BASE+0x080))
#define APU_EDMA_0_APU_EDMA2_DECMPR_DBG_INFO	((phys_addr_t)(APU_EDMA_0_BASE+0x084))
#define APU_EDMA_0_APU_EDMA2_CMPR_DBG_INFO	((phys_addr_t)(APU_EDMA_0_BASE+0x088))
#define APU_EDMA_0_APU_EDMA2_UFBDC_VCODE_0	((phys_addr_t)(APU_EDMA_0_BASE+0x090))
#define APU_EDMA_0_APU_EDMA2_UFBDC_VCODE_1	((phys_addr_t)(APU_EDMA_0_BASE+0x094))
#define APU_EDMA_0_APU_EDMA2_UFBDC_VCODE_2	((phys_addr_t)(APU_EDMA_0_BASE+0x098))
#define APU_EDMA_0_APU_EDMA2_UFBDC_VCODE_3	((phys_addr_t)(APU_EDMA_0_BASE+0x09C))
#define APU_EDMA_0_APU_EDMA2_EXT_DESP_CFG_0	((phys_addr_t)(APU_EDMA_0_BASE+0x0A0))
#define APU_EDMA_0_APU_EDMA2_EXT_DESP_CFG_1	((phys_addr_t)(APU_EDMA_0_BASE+0x0A4))

#define APUSYS_VCORE_BASE (APMCU_RIUBASE + X32_APUSYS_BASE + apu_vcore_base)
#define APUSYS_VCORE_CG_CON	((phys_addr_t)(APUSYS_VCORE_BASE+0x000))
#define APUSYS_VCORE_CG_SET	((phys_addr_t)(APUSYS_VCORE_BASE+0x004))
#define APUSYS_VCORE_CG_CLR	((phys_addr_t)(APUSYS_VCORE_BASE+0x008))
#define APUSYS_VCORE_SW_RST	((phys_addr_t)(APUSYS_VCORE_BASE+0x00C))

#define APU_MDLA0_BASE (APMCU_RIUBASE + X32_APUSYS_BASE + apu_mdla0_base)
#define APU_MDLA0_APU_MDLA_CG_CON	((phys_addr_t)(APU_MDLA0_BASE+0x000))
#define APU_MDLA0_APU_MDLA_CG_SET	((phys_addr_t)(APU_MDLA0_BASE+0x004))
#define APU_MDLA0_APU_MDLA_CG_CLR	((phys_addr_t)(APU_MDLA0_BASE+0x008))
#define APU_MDLA0_APU_MDLA_SW_RST	((phys_addr_t)(APU_MDLA0_BASE+0x00C))
#define APU_MDLA0_APU_MDLA_MBIST_DELSEL	((phys_addr_t)(APU_MDLA0_BASE+0x024))

// APB Module apu_cmde
#define APU_MDLA0_CMDE_BASE (APMCU_RIUBASE + X32_APUSYS_BASE + mdla_cmde_base)
#define APU_MDLA0_CMDE_INT_STATUS ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x504))
#define APU_MDLA0_CMDE_INT_ENABLE ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x508))
#define APU_MDLA0_CMDE_INT_MASK   ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x50c))
#define APU_MDLA0_CMDE_510        ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x510))
#define APU_MDLA0_CMDE_514        ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x514))
#define APU_MDLA0_CMDE_518        ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x518))
#define APU_MDLA0_CMDE_51c        ((phys_addr_t)(APU_MDLA0_CMDE_BASE + 0x51c))

#endif
