/* SPDX-License-Identifier: BSD-2-Clause */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

/* [File] : wf_wfdma_ext_wrap_csr.h */
/* [Revision time] : Sat Nov 23 20:45:02 2019 */
/* [Description] : This file is auto generated by CODA */

#ifndef __WF_WFDMA_EXT_WRAP_CSR_REGS_H__
#define __WF_WFDMA_EXT_WRAP_CSR_REGS_H__

/* ************************************************************************** */
/* */
/* WF_WFDMA_EXT_WRAP_CSR CR Definitions */
/* */
/* ************************************************************************** */

#if defined(_HIF_AXI)
#define WF_WFDMA_EXT_WRAP_CSR_BASE (0x18027000 + CONN_INFRA_REMAPPING_OFFSET)
#endif

#if defined(_HIF_PCIE)
#define WF_WFDMA_EXT_WRAP_CSR_BASE 0x7C027000
#endif

#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_CTRL_CR_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x00) /* 7000 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN0_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x20) /* 7020 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN1_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x24) /* 7024 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN2_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x28) /* 7028 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN3_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x2C) /* 702C */
#define WF_WFDMA_EXT_WRAP_CSR_DLY_INT_TICK_THRES_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x38) /* 7038 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_SW_RST_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x3C) /* 703C */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DBG_SEL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x40) /* 7040 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HIF_MISC_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x44) /* 7044 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x50) /* 7050 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_VIO_ADDR_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x54) /* 7054 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x74) /* 7074 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x94) /* 7094 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x98) /* 7098 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB_2TO1_DEBUG_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x9C) /* 709C */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0xA0) /* 70A0 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0xA4) /* 70A4 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_DOWNSIZER_DBG_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0xA8) /* 70A8 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI1_DOWNSIZER_DBG_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0xAC) /* 70AC */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x500) /* 7500 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x504) /* 7504 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x508) /* 7508 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x50C) /* 750C */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMAWR_PROBE_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x510) /* 7510 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMARD_PROBE_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x514) /* 7514 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x518) /* 7518 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x51C) /* 751C */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x520) /* 7520 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x524) /* 7524 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x528) /* 7528 */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_CMD_ST_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x52C) /* 752C */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_DAT_ST_ADDR \
	(WF_WFDMA_EXT_WRAP_CSR_BASE + 0x530) /* 7530 */




/*
* ---WFDMA_TOP_CTRL_CR (0x18027000 + 0x00)---
* CONN_HIF_WRAP_CSR_OUT[15..0] - (RW) conn_hif_wrap_csr_out for top_ctrl if
* needed in the future
* RESERVED16[31..16] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_CTRL_CR_CONN_HIF_WRAP_CSR_OUT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_CTRL_CR_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_CTRL_CR_CONN_HIF_WRAP_CSR_OUT_MASK \
	0x0000FFFF /* CONN_HIF_WRAP_CSR_OUT[15..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_CTRL_CR_CONN_HIF_WRAP_CSR_OUT_SHFT 0

/*
* ---WFDMA_TOP_DBG_IN0 (0x18027000 + 0x20)---
* DBG_IN_31_0[31..0] - (RO) DBG_IN_31_0
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN0_DBG_IN_31_0_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN0_DBG_IN_31_0_MASK \
	0xFFFFFFFF /* DBG_IN_31_0[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN0_DBG_IN_31_0_SHFT 0

/*
* ---WFDMA_TOP_DBG_IN1 (0x18027000 + 0x24)---
* DBG_IN_63_32[31..0] - (RO) DBG_IN_63_32
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN1_DBG_IN_63_32_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN1_DBG_IN_63_32_MASK \
	0xFFFFFFFF /* DBG_IN_63_32[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN1_DBG_IN_63_32_SHFT 0

/*
* ---WFDMA_TOP_DBG_IN2 (0x18027000 + 0x28)---
* DBG_IN_95_64[31..0] - (RO) DBG_IN_95_64
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN2_DBG_IN_95_64_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN2_DBG_IN_95_64_MASK \
	0xFFFFFFFF /* DBG_IN_95_64[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN2_DBG_IN_95_64_SHFT 0

/*
* ---WFDMA_TOP_DBG_IN3 (0x18027000 + 0x2C)---
* DBG_IN_127_96[31..0] - (RO) DBG_IN_127_96
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN3_DBG_IN_127_96_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN3_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN3_DBG_IN_127_96_MASK \
	0xFFFFFFFF /* DBG_IN_127_96[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_TOP_DBG_IN3_DBG_IN_127_96_SHFT 0

/*
* ---DLY_INT_TICK_THRES (0x18027000 + 0x38)---
* delay_int_tick_threshold[15..0] - (RW) 1us tick generation: slow clock period
* = 2*(delay_int_tick_threshold)*fast_clock_cycle_time
* RESERVED16[31..16] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_DLY_INT_TICK_THRES_delay_int_tick_threshold_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_DLY_INT_TICK_THRES_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_DLY_INT_TICK_THRES_delay_int_tick_threshold_MASK \
	0x0000FFFF /* delay_int_tick_threshold[15..0] */
#define WF_WFDMA_EXT_WRAP_CSR_DLY_INT_TICK_THRES_delay_int_tick_threshold_SHFT 0

/*
* ---WFDMA_SW_RST (0x18027000 + 0x3C)---
* HIF_SW_RST[0] - (RW) HIF side S/W reset , write 1 to trigger reset pulse then
* auto clear
* RESERVED1[31..1] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_SW_RST_HIF_SW_RST_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_SW_RST_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_SW_RST_HIF_SW_RST_MASK \
	0x00000001 /* HIF_SW_RST[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_SW_RST_HIF_SW_RST_SHFT     0

/*
* ---WFDMA_DBG_SEL (0x18027000 + 0x40)---
* DEBUG_SEL[1..0] - (RW) debug select among PDMA
* RESERVED2[31..2] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DBG_SEL_DEBUG_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DBG_SEL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DBG_SEL_DEBUG_SEL_MASK \
	0x00000003 /* DEBUG_SEL[1..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DBG_SEL_DEBUG_SEL_SHFT     0

/*
* ---WFDMA_HIF_MISC (0x18027000 + 0x44)---
* HIF_BUSY[0] - (RO) Inverse of idle indicator
* RESERVED1[31..1] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HIF_MISC_HIF_BUSY_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_HIF_MISC_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HIF_MISC_HIF_BUSY_MASK \
	0x00000001 /* HIF_BUSY[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HIF_MISC_HIF_BUSY_SHFT     0

/*
* ---WFDMA_AXI_SLPPROT_CTRL (0x18027000 + 0x50)---
* AXI0_SLPPROT_EN[0] - (RW) AXI0 sleep protect enable
* AXI0_SLPPROT_RDY[1] - (RO) AXI0 sleep protect ready
* AXI0_SLPPROT_IDLE[2] - (RO) AXI0 sleep protect idle
* AXI0_SLPPROT_ERR[3] - (RO) AXI0 sleep protect error
* AXI0_SLPPROT_VIO_RD[4] - (RO) AXI0 sleep protect violated transaction is read
type
* AXI0_SLPPROT_VIO_WR[5] - (RO) AXI0 sleep protect violated transaction is write
type
* RESERVED6[7..6] - (RO) Reserved bits
* AXI0_SLPPROT_VIO_ADDR_EXT[11..8] - (RO) AXI0 sleep protect violated address
[35:32]
* AXI0_FORCE_RREADY_HIGH[12] - (RW) Force AXI0 rready high.
* Debug purpose register.It could drop all coming axi rdata to finish read
transaction.
* AXI0_FORCE_WVALID_HIGH[13] - (RW) Force AXI0 wvalid high.
* Debug purpose register. It could send dummy wdata to finish write transaction.
* AXI0_FORCE_WLAST_HIGH[14] - (RW) Force AXI0 wlast high.
* Debug purpose register. It could send dummy wdata last to finish write
transaction.
* RESERVED15[15] - (RO) Reserved bits
* AXI1_SLPPROT_EN[16] - (RW) AXI1 sleep protect enable
* AXI1_SLPPROT_RDY[17] - (RO) AXI1 sleep protect ready
* AXI1_SLPPROT_IDLE[18] - (RO) AXI1 sleep protect idle
* AXI1_SLPPROT_ERR[19] - (RO) AXI1 sleep protect error
* AXI1_SLPPROT_VIO_RD[20] - (RO) AXI1 sleep protect violated transaction is read
type
* AXI1_SLPPROT_VIO_WR[21] - (RO) AXI1 sleep protect violated transaction is
* write type
* RESERVED22[23..22] - (RO) Reserved bits
* AXI1_SLPPROT_VIO_ADDR_EXT[27..24] - (RO) AXI1 sleep protect violated address
[35:32]
* AXI1_FORCE_RREADY_HIGH[28] - (RW) Force AXI1 rready high.
* Debug purpose register.It could drop all coming axi rdata to finish read
transaction.
* AXI1_FORCE_WVALID_HIGH[29] - (RW) Force AXI1 wvalid high.
* Debug purpose register. It could send dummy wdata to finish write transaction.
* AXI1_FORCE_WLAST_HIGH[30] - (RW) Force AXI1 wlast high.
* Debug purpose register. It could send dummy wdata last to finish write
transaction.
* RESERVED31[31] - (RO) Reserved bits
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_WLAST_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_WLAST_HIGH_MASK \
	0x40000000 /* AXI1_FORCE_WLAST_HIGH[30] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_WLAST_HIGH_SHFT \
	30
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_WVALID_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_WVALID_HIGH_MASK \
	0x20000000 /* AXI1_FORCE_WVALID_HIGH[29] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_WVALID_HIGH_SHFT \
	29
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_RREADY_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_RREADY_HIGH_MASK \
	0x10000000 /* AXI1_FORCE_RREADY_HIGH[28] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_FORCE_RREADY_HIGH_SHFT \
	28
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_ADDR_EXT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_ADDR_EXT_MASK \
	0x0F000000 /* AXI1_SLPPROT_VIO_ADDR_EXT[27..24] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_ADDR_EXT_SHFT \
	24
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_WR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_WR_MASK \
	0x00200000 /* AXI1_SLPPROT_VIO_WR[21] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_WR_SHFT 21
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_RD_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_RD_MASK \
	0x00100000 /* AXI1_SLPPROT_VIO_RD[20] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_VIO_RD_SHFT 20
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_ERR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_ERR_MASK \
	0x00080000 /* AXI1_SLPPROT_ERR[19] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_ERR_SHFT 19
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_IDLE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_IDLE_MASK \
	0x00040000 /* AXI1_SLPPROT_IDLE[18] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_IDLE_SHFT 18
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_RDY_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_RDY_MASK \
	0x00020000 /* AXI1_SLPPROT_RDY[17] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_RDY_SHFT 17
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_EN_MASK \
	0x00010000 /* AXI1_SLPPROT_EN[16] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI1_SLPPROT_EN_SHFT 16
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_WLAST_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_WLAST_HIGH_MASK \
	0x00004000 /* AXI0_FORCE_WLAST_HIGH[14] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_WLAST_HIGH_SHFT \
	14
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_WVALID_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_WVALID_HIGH_MASK \
	0x00002000 /* AXI0_FORCE_WVALID_HIGH[13] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_WVALID_HIGH_SHFT \
	13
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_RREADY_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_RREADY_HIGH_MASK \
	0x00001000 /* AXI0_FORCE_RREADY_HIGH[12] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_FORCE_RREADY_HIGH_SHFT \
	12
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_ADDR_EXT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_ADDR_EXT_MASK \
	0x00000F00 /* AXI0_SLPPROT_VIO_ADDR_EXT[11..8] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_ADDR_EXT_SHFT \
	8
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_WR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_WR_MASK \
	0x00000020 /* AXI0_SLPPROT_VIO_WR[5] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_WR_SHFT 5
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_RD_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_RD_MASK \
	0x00000010 /* AXI0_SLPPROT_VIO_RD[4] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_VIO_RD_SHFT 4
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_ERR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_ERR_MASK \
	0x00000008 /* AXI0_SLPPROT_ERR[3] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_ERR_SHFT 3
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_IDLE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_IDLE_MASK \
	0x00000004 /* AXI0_SLPPROT_IDLE[2] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_IDLE_SHFT 2
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_RDY_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_RDY_MASK \
	0x00000002 /* AXI0_SLPPROT_RDY[1] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_RDY_SHFT 1
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_EN_MASK \
	0x00000001 /* AXI0_SLPPROT_EN[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_CTRL_AXI0_SLPPROT_EN_SHFT 0

/*
* ---WFDMA_AXI_SLPPROT_VIO_ADDR (0x18027000 + 0x54)---
* AXI0_SLPPROT_VIO_ADDR[31..0] - (RO) AXI0 sleep protect violated address [31:0]
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_VIO_ADDR_AXI0_SLPPROT_VIO_ADDR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_VIO_ADDR_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_VIO_ADDR_AXI0_SLPPROT_VIO_ADDR_MASK \
	0xFFFFFFFF /* AXI0_SLPPROT_VIO_ADDR[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_SLPPROT_VIO_ADDR_AXI0_SLPPROT_VIO_ADDR_SHFT \
	0

/*
* ---WFDMA_DCM_CTRL (0x18027000 + 0x74)---
* DCM_CTRL_CR[0] - (RW) DCM enable for CR module
* RESERVED1[2..1] - (RO) Reserved bits
* DCM_CTRL_BUS[3] - (RW) DCM enable for RBUS to AXI module
* RESERVED4[4] - (RO) Reserved bits
* PSEL_BUSY_CNT[12..5] - (RW) APB PSEL timer to extend DCM high speed duration
* RESERVED13[14..13] - (RO) Reserved bits
* TXP_SAF_MODE[15] - (RW) 1'b0: CT mode 1'b1: Store & Forward mode
* UMAC_BUSY_CNT[21..16] - (RW) UMAC busy timer to extend DCM high speed duration
* UMAC_CK_DCM_ALWAYS_HIGH[22] - (RW) UMAC DCM control by CR
* 1: UMAC DCM clock is always high speed . 0: HW control.
* UMAC_CK_DCM_BUSY[23] - (RO) WFDMA request UMAC clock is high speed
* AXI_HIF_BUSY_CNT[29..24] - (RW) HIF AXI busy timer to extend clock exist
duration
* AXI_HIF_CK_ALWAYS_EXIST[30] - (RW) HIF AXI clock request control by CR
* 1: HIF AXI clock always exist. 0: HW control.
* AXI_HIF_CK_IDLE[31] - (RO) WFDMA is request AXI host clock gated (not busy)
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_CK_IDLE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_CK_IDLE_MASK \
	0x80000000 /* AXI_HIF_CK_IDLE[31] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_CK_IDLE_SHFT 31
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_CK_ALWAYS_EXIST_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_CK_ALWAYS_EXIST_MASK \
	0x40000000 /* AXI_HIF_CK_ALWAYS_EXIST[30] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_CK_ALWAYS_EXIST_SHFT 30
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_BUSY_CNT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_BUSY_CNT_MASK \
	0x3F000000 /* AXI_HIF_BUSY_CNT[29..24] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_AXI_HIF_BUSY_CNT_SHFT 24
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_CK_DCM_BUSY_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_CK_DCM_BUSY_MASK \
	0x00800000 /* UMAC_CK_DCM_BUSY[23] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_CK_DCM_BUSY_SHFT 23
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_CK_DCM_ALWAYS_HIGH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_CK_DCM_ALWAYS_HIGH_MASK \
	0x00400000 /* UMAC_CK_DCM_ALWAYS_HIGH[22] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_CK_DCM_ALWAYS_HIGH_SHFT 22
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_BUSY_CNT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_BUSY_CNT_MASK \
	0x003F0000 /* UMAC_BUSY_CNT[21..16] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_UMAC_BUSY_CNT_SHFT 16
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_TXP_SAF_MODE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_TXP_SAF_MODE_MASK \
	0x00008000 /* TXP_SAF_MODE[15] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_TXP_SAF_MODE_SHFT 15
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_PSEL_BUSY_CNT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_PSEL_BUSY_CNT_MASK \
	0x00001FE0 /* PSEL_BUSY_CNT[12..5] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_PSEL_BUSY_CNT_SHFT 5
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_DCM_CTRL_BUS_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_DCM_CTRL_BUS_MASK \
	0x00000008 /* DCM_CTRL_BUS[3] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_DCM_CTRL_BUS_SHFT 3
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_DCM_CTRL_CR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_DCM_CTRL_CR_MASK \
	0x00000001 /* DCM_CTRL_CR[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_DCM_CTRL_DCM_CTRL_CR_SHFT  0

/*
* ---WFDMA_APB0_SYNC_CTRL (0x18027000 + 0x94)---
* APB0_VIO_ADDR[15..0] - (RO) APB0 p2p slice violated address [15:0]
* APB0_VIO_RD[16] - (RO) APB0 p2p slice violated transaction is read type
* APB0_VIO_WR[17] - (RO) APB0 p2p slice violated transaction is write type
* APB0_VIO_TIMEOUT[18] - (RO) APB0 p2p slice timeout
* APB0_TX_IDLE[19] - (RO) APB0 p2p slice is idle
* APB0_ERR_FLAG_EN[20] - (RW) Enable APB0 p2p slice show timeout information
* RESERVED21[31..21] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_ERR_FLAG_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_ERR_FLAG_EN_MASK \
	0x00100000 /* APB0_ERR_FLAG_EN[20] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_ERR_FLAG_EN_SHFT 20
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_TX_IDLE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_TX_IDLE_MASK \
	0x00080000 /* APB0_TX_IDLE[19] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_TX_IDLE_SHFT 19
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_TIMEOUT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_TIMEOUT_MASK \
	0x00040000 /* APB0_VIO_TIMEOUT[18] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_TIMEOUT_SHFT 18
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_WR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_WR_MASK \
	0x00020000 /* APB0_VIO_WR[17] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_WR_SHFT 17
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_RD_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_RD_MASK \
	0x00010000 /* APB0_VIO_RD[16] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_RD_SHFT 16
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_ADDR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_ADDR_MASK \
	0x0000FFFF /* APB0_VIO_ADDR[15..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB0_SYNC_CTRL_APB0_VIO_ADDR_SHFT 0

/*
* ---WFDMA_APB1_SYNC_CTRL (0x18027000 + 0x98)---
* APB1_VIO_ADDR[15..0] - (RO) APB1 p2p slice violated address [15:0]
* APB1_VIO_RD[16] - (RO) APB1 p2p slice violated transaction is read type
* APB1_VIO_WR[17] - (RO) APB1 p2p slice violated transaction is write type
* APB1_VIO_TIMEOUT[18] - (RO) APB1 p2p slice timeout
* APB1_TX_IDLE[19] - (RO) APB1 p2p slice is idle
* APB1_ERR_FLAG_EN[20] - (RW) Enable APB1 p2p slice show timeout information
* RESERVED21[31..21] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_ERR_FLAG_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_ERR_FLAG_EN_MASK \
	0x00100000 /* APB1_ERR_FLAG_EN[20] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_ERR_FLAG_EN_SHFT 20
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_TX_IDLE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_TX_IDLE_MASK \
	0x00080000 /* APB1_TX_IDLE[19] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_TX_IDLE_SHFT 19
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_TIMEOUT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_TIMEOUT_MASK \
	0x00040000 /* APB1_VIO_TIMEOUT[18] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_TIMEOUT_SHFT 18
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_WR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_WR_MASK \
	0x00020000 /* APB1_VIO_WR[17] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_WR_SHFT 17
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_RD_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_RD_MASK \
	0x00010000 /* APB1_VIO_RD[16] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_RD_SHFT 16
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_ADDR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_ADDR_MASK \
	0x0000FFFF /* APB1_VIO_ADDR[15..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB1_SYNC_CTRL_APB1_VIO_ADDR_SHFT 0

/*
* ---WFDMA_APB_2TO1_DEBUG (0x18027000 + 0x9C)---
* APB_2TO1_DEBUG[31..0] - (RO) debug information for APB 2to1 slice
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB_2TO1_DEBUG_APB_2TO1_DEBUG_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB_2TO1_DEBUG_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB_2TO1_DEBUG_APB_2TO1_DEBUG_MASK \
	0xFFFFFFFF /* APB_2TO1_DEBUG[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_APB_2TO1_DEBUG_APB_2TO1_DEBUG_SHFT 0

/*
* ---WFDMA_AXI_IF_DISP_CTRL (0x18027000 + 0xA0)---
* AXI_W_FORCE_TO_MCU[0] - (RW) Force Write transaction to MCU side
* (low priority then force to HIF)
* Debug purpose register
* AXI_W_FORCE_TO_HIF[1] - (RW) Force Write transaction to HIF side
* (high priority then force to MCU)
* Debug purpose register
* AXI_R_FORCE_TO_MCU[2] - (RW) Force Read transaction to MCU side
* (low priority then force to HIF)
* Debug purpose register
* AXI_R_FORCE_TO_HIF[3] - (RW) Frorce Read transaction to HIF side (higher
* priority then force to MCU)
* Debug purpose register.
* AXI_DISP_W_SRC[4] - (RO) AXI W Channel transaction target
* 1 : to HIF
* 0: to MCU
* AXI_DISP_AW_SRC[5] - (RO) AXI AW Channel transaction target
* 1 : to HIF
* 0: to MCU
* AXI_DISP_AR_SRC[6] - (RO) AXI AR Channel transaction target
* 1 : to HIF
* 0: to MCU
* RESERVED7[15..7] - (RO) Reserved bits
* AXI_R_INTERLEAVED_EN[16] - (RW) Enable axi dispatcher support read interleaved
* 1: support interleaved
* 0: not support
* RESERVED17[31..17] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_INTERLEAVED_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_INTERLEAVED_EN_MASK \
	0x00010000 /* AXI_R_INTERLEAVED_EN[16] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_INTERLEAVED_EN_SHFT \
	16
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_AR_SRC_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_AR_SRC_MASK \
	0x00000040 /* AXI_DISP_AR_SRC[6] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_AR_SRC_SHFT 6
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_AW_SRC_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_AW_SRC_MASK \
	0x00000020 /* AXI_DISP_AW_SRC[5] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_AW_SRC_SHFT 5
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_W_SRC_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_W_SRC_MASK \
	0x00000010 /* AXI_DISP_W_SRC[4] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_DISP_W_SRC_SHFT 4
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_FORCE_TO_HIF_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_FORCE_TO_HIF_MASK \
	0x00000008 /* AXI_R_FORCE_TO_HIF[3] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_FORCE_TO_HIF_SHFT 3
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_FORCE_TO_MCU_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_FORCE_TO_MCU_MASK \
	0x00000004 /* AXI_R_FORCE_TO_MCU[2] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_R_FORCE_TO_MCU_SHFT 2
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_W_FORCE_TO_HIF_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_W_FORCE_TO_HIF_MASK \
	0x00000002 /* AXI_W_FORCE_TO_HIF[1] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_W_FORCE_TO_HIF_SHFT 1
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_W_FORCE_TO_MCU_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_W_FORCE_TO_MCU_MASK \
	0x00000001 /* AXI_W_FORCE_TO_MCU[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_DISP_CTRL_AXI_W_FORCE_TO_MCU_SHFT 0

/*
* ---WFDMA_AXI_IF_FRQBDG_CTRL (0x18027000 + 0xA4)---
* AXI0_FRQBDG_MST_SYNC_SEL[1..0] - (RW) AXI0 Master frequency bridge master sync
select
* AXI0_FRQBDG_SLV_SYNC_SEL[3..2] - (RW) AXI0 Master frequency bridge slave sync
select
* AXI0_FRQBDG_SAMPLE_SEL[4] - (RW) AXI0 Master frequency bridge sample select
* RESERVED5[7..5] - (RO) Reserved bits
* AXI1_FRQBDG_MST_SYNC_SEL[9..8] - (RW) AXI1 Master frequency bridge master sync
select
* AXI1_FRQBDG_SLV_SYNC_SEL[11..10] - (RW) AXI1 Maste frequency bridge slave sync
select
* AXI1_FRQBDG_SAMPLE_SEL[12] - (RW) AXI1 Master frequency bridge sample select
* RESERVED13[31..13] - (RO) Reserved bits
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_SAMPLE_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_SAMPLE_SEL_MASK \
	0x00001000 /* AXI1_FRQBDG_SAMPLE_SEL[12] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_SAMPLE_SEL_SHFT \
	12
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_SLV_SYNC_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_SLV_SYNC_SEL_MASK \
	0x00000C00 /* AXI1_FRQBDG_SLV_SYNC_SEL[11..10] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_SLV_SYNC_SEL_SHFT \
	10
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_MST_SYNC_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_MST_SYNC_SEL_MASK \
	0x00000300 /* AXI1_FRQBDG_MST_SYNC_SEL[9..8] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI1_FRQBDG_MST_SYNC_SEL_SHFT \
	8
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_SAMPLE_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_SAMPLE_SEL_MASK \
	0x00000010 /* AXI0_FRQBDG_SAMPLE_SEL[4] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_SAMPLE_SEL_SHFT \
	4
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_SLV_SYNC_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_SLV_SYNC_SEL_MASK \
	0x0000000C /* AXI0_FRQBDG_SLV_SYNC_SEL[3..2] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_SLV_SYNC_SEL_SHFT \
	2
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_MST_SYNC_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_MST_SYNC_SEL_MASK \
	0x00000003 /* AXI0_FRQBDG_MST_SYNC_SEL[1..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI_IF_FRQBDG_CTRL_AXI0_FRQBDG_MST_SYNC_SEL_SHFT \
	0

/*
* ---WFDMA_AXI0_DOWNSIZER_DBG (0x18027000 + 0xA8)---
* AXI0_DOWNSIZER_DBG[31..0] - (RO) debug information for AXI0 Downsizer
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_DOWNSIZER_DBG_AXI0_DOWNSIZER_DBG_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_DOWNSIZER_DBG_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_DOWNSIZER_DBG_AXI0_DOWNSIZER_DBG_MASK \
	0xFFFFFFFF /* AXI0_DOWNSIZER_DBG[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_DOWNSIZER_DBG_AXI0_DOWNSIZER_DBG_SHFT 0

/*
* ---WFDMA_AXI1_DOWNSIZER_DBG (0x18027000 + 0xAC)---
* AXI1_DOWNSIZER_DBG[31..0] - (RO) debug information for AXI1 Downsizer
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI1_DOWNSIZER_DBG_AXI1_DOWNSIZER_DBG_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI1_DOWNSIZER_DBG_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI1_DOWNSIZER_DBG_AXI1_DOWNSIZER_DBG_MASK \
	0xFFFFFFFF /* AXI1_DOWNSIZER_DBG[31..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI1_DOWNSIZER_DBG_AXI1_DOWNSIZER_DBG_SHFT 0

/*
* ---WFDMA_AXI0_R2A_CTRL_0 (0x18027000 + 0x500)---
* RD_OUTSTAND_NUM[3..0] - (RW) AXI read outstanding number
* LAST_NONBUF[4] - (RW) Last nonbuf
* BUFFERABLE[5] - (RW) Bufferable
* BURST_SIZE[7..6] - (RW) AXI burst size
* SLEEP_MODE[9..8] - (RW) Sleep mode
* BRESP_ERR_CHK_BYP[10] - (RW) BRESP error check bypass enable
* BID_CHK_BYP[11] - (RW) BID check bypass enable
* BUFRDY_BYP[12] - (RW) Buffer ready bypass enable
* CLKGATE_BYP[13] - (RW) Clock gating bypass enable
* RX_ERR_EN[14] - (RW) RX error detect enable
* TX_ERR_EN[15] - (RW) TX error detect enable
* TX_ERR_TH[23..16] - (RW) TX error timer threshold
* RX_ERR_TH[31..24] - (RW) RX error timer threshold
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RX_ERR_TH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RX_ERR_TH_MASK \
	0xFF000000 /* RX_ERR_TH[31..24] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RX_ERR_TH_SHFT 24
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_TX_ERR_TH_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_TX_ERR_TH_MASK \
	0x00FF0000 /* TX_ERR_TH[23..16] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_TX_ERR_TH_SHFT 16
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_TX_ERR_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_TX_ERR_EN_MASK \
	0x00008000 /* TX_ERR_EN[15] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_TX_ERR_EN_SHFT 15
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RX_ERR_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RX_ERR_EN_MASK \
	0x00004000 /* RX_ERR_EN[14] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RX_ERR_EN_SHFT 14
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_CLKGATE_BYP_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_CLKGATE_BYP_MASK \
	0x00002000 /* CLKGATE_BYP[13] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_CLKGATE_BYP_SHFT 13
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BUFRDY_BYP_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BUFRDY_BYP_MASK \
	0x00001000 /* BUFRDY_BYP[12] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BUFRDY_BYP_SHFT 12
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BID_CHK_BYP_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BID_CHK_BYP_MASK \
	0x00000800 /* BID_CHK_BYP[11] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BID_CHK_BYP_SHFT 11
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BRESP_ERR_CHK_BYP_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BRESP_ERR_CHK_BYP_MASK \
	0x00000400 /* BRESP_ERR_CHK_BYP[10] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BRESP_ERR_CHK_BYP_SHFT 10
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_SLEEP_MODE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_SLEEP_MODE_MASK \
	0x00000300 /* SLEEP_MODE[9..8] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_SLEEP_MODE_SHFT 8
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BURST_SIZE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BURST_SIZE_MASK \
	0x000000C0 /* BURST_SIZE[7..6] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BURST_SIZE_SHFT 6
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BUFFERABLE_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BUFFERABLE_MASK \
	0x00000020 /* BUFFERABLE[5] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_BUFFERABLE_SHFT 5
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_LAST_NONBUF_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_LAST_NONBUF_MASK \
	0x00000010 /* LAST_NONBUF[4] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_LAST_NONBUF_SHFT 4
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RD_OUTSTAND_NUM_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RD_OUTSTAND_NUM_MASK \
	0x0000000F /* RD_OUTSTAND_NUM[3..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_0_RD_OUTSTAND_NUM_SHFT 0

/*
* ---WFDMA_AXI0_R2A_CTRL_1 (0x18027000 + 0x504)---
* LIMITER_SEL[0] - (RW) LIMITER_SEL
* LIMITER_RX_RD_EN[2..1] - (RW) LIMITER_RX_RD_EN
* LIMITER_RX_RD_1[8..3] - (RW) LIMITER_RX_RD_1
* LIMITER_RX_RD_0[14..9] - (RW) LIMITER_RX_RD_0
* LIMITER_RX_WR_EN[16..15] - (RW) LIMITER_RX_WR_EN
* LIMITER_RX_WR_1[22..17] - (RW) LIMITER_RX_WR_1
* LIMITER_RX_WR_0[28..23] - (RW) LIMITER_RX_WR_0
* RESERVED29[31..29] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_0_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_0_MASK \
	0x1F800000 /* LIMITER_RX_WR_0[28..23] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_0_SHFT 23
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_1_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_1_MASK \
	0x007E0000 /* LIMITER_RX_WR_1[22..17] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_1_SHFT 17
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_EN_MASK \
	0x00018000 /* LIMITER_RX_WR_EN[16..15] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_WR_EN_SHFT 15
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_0_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_0_MASK \
	0x00007E00 /* LIMITER_RX_RD_0[14..9] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_0_SHFT 9
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_1_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_1_MASK \
	0x000001F8 /* LIMITER_RX_RD_1[8..3] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_1_SHFT 3
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_EN_MASK \
	0x00000006 /* LIMITER_RX_RD_EN[2..1] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_RX_RD_EN_SHFT 1
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_SEL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_SEL_MASK \
	0x00000001 /* LIMITER_SEL[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_1_LIMITER_SEL_SHFT 0

/*
* ---WFDMA_AXI0_R2A_CTRL_2 (0x18027000 + 0x508)---
* LOCK_MAX_CNT[4..0] - (RW) LOCK_MAX_CNT
* LOCK_MAX_CNT_EN[5] - (RW) LOCK_MAX_CNT_EN
* ERR_FLAGS_CLR[6] - (RW) ERR_FLAGS_CLR
* WFIFO_LAST_SW_CTL[7] - (RW) WFIFO_LAST_SW_CTL
* LOCK_RLS_CNT[23..8] - (RW) LOCK_RLS_CNT
* LOCK_RLS_EN[24] - (RW) LOCK_RLS_EN
* AXI_RD_OUT_OF_ORDER[25] - (RW) AXI read supports out-of-order response data
* AXI_WR_OUT_OF_ORDER[26] - (RW) AXI write supports out-of-order response data
* RESERVED27[27] - (RO) Reserved bits
* WR_OUTSTAND_NUM[31..28] - (RW) AXI write outstanding number
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_WR_OUTSTAND_NUM_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_WR_OUTSTAND_NUM_MASK \
	0xF0000000 /* WR_OUTSTAND_NUM[31..28] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_WR_OUTSTAND_NUM_SHFT 28
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_AXI_WR_OUT_OF_ORDER_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_AXI_WR_OUT_OF_ORDER_MASK \
	0x04000000 /* AXI_WR_OUT_OF_ORDER[26] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_AXI_WR_OUT_OF_ORDER_SHFT 26
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_AXI_RD_OUT_OF_ORDER_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_AXI_RD_OUT_OF_ORDER_MASK \
	0x02000000 /* AXI_RD_OUT_OF_ORDER[25] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_AXI_RD_OUT_OF_ORDER_SHFT 25
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_RLS_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_RLS_EN_MASK \
	0x01000000 /* LOCK_RLS_EN[24] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_RLS_EN_SHFT 24
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_RLS_CNT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_RLS_CNT_MASK \
	0x00FFFF00 /* LOCK_RLS_CNT[23..8] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_RLS_CNT_SHFT 8
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_WFIFO_LAST_SW_CTL_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_WFIFO_LAST_SW_CTL_MASK \
	0x00000080 /* WFIFO_LAST_SW_CTL[7] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_WFIFO_LAST_SW_CTL_SHFT 7
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ERR_FLAGS_CLR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ERR_FLAGS_CLR_MASK \
	0x00000040 /* ERR_FLAGS_CLR[6] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ERR_FLAGS_CLR_SHFT 6
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_MAX_CNT_EN_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_MAX_CNT_EN_MASK \
	0x00000020 /* LOCK_MAX_CNT_EN[5] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_MAX_CNT_EN_SHFT 5
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_MAX_CNT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_MAX_CNT_MASK \
	0x0000001F /* LOCK_MAX_CNT[4..0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_CTRL_2_LOCK_MAX_CNT_SHFT 0

/*
* ---WFDMA_AXI0_R2A_STS (0x18027000 + 0x50C)---
* RD_AXI_ERR_DET_INT[0] - (RO) RD_AXI_ERR_DET_INT
* WR_AXI_ERR_DET_INT[1] - (RO) WR_AXI_ERR_DET_INT
* ERR_PORT_RD_DAT_RID[2] - (RO) ERR_PORT_RD_DAT_RID
* RRESP_ERR_STS[10..3] - (RO) RRESP_ERR_STS
* RRESP_ERR[11] - (RO) RRESP_ERR
* BRESP_ERR_STS[19..12] - (RO) BRESP_ERR_STS
* BRESP_ERR[20] - (RO) BRESP_ERR
* RESERVED21[31..21] - (RO) Reserved bits
*/
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_BRESP_ERR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_BRESP_ERR_MASK \
	0x00100000 /* BRESP_ERR[20] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_BRESP_ERR_SHFT 20
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_BRESP_ERR_STS_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_BRESP_ERR_STS_MASK \
	0x000FF000 /* BRESP_ERR_STS[19..12] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_BRESP_ERR_STS_SHFT 12
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RRESP_ERR_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RRESP_ERR_MASK \
	0x00000800 /* RRESP_ERR[11] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RRESP_ERR_SHFT 11
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RRESP_ERR_STS_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RRESP_ERR_STS_MASK \
	0x000007F8 /* RRESP_ERR_STS[10..3] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RRESP_ERR_STS_SHFT 3
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ERR_PORT_RD_DAT_RID_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ERR_PORT_RD_DAT_RID_MASK \
	0x00000004 /* ERR_PORT_RD_DAT_RID[2] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ERR_PORT_RD_DAT_RID_SHFT 2
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_WR_AXI_ERR_DET_INT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_WR_AXI_ERR_DET_INT_MASK \
	0x00000002 /* WR_AXI_ERR_DET_INT[1] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_WR_AXI_ERR_DET_INT_SHFT 1
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RD_AXI_ERR_DET_INT_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_ADDR
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RD_AXI_ERR_DET_INT_MASK \
	0x00000001 /* RD_AXI_ERR_DET_INT[0] */
#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_STS_RD_AXI_ERR_DET_INT_SHFT 0

/*
* ---WFDMA_AXI0_R2A_DMAWR_PROBE (0x18027000 + 0x510)---
* WFDMA_AXI0_R2A_DMAWR_PROBE[31..0] - (RO) WFDMA_AXI0_R2A_DMAWR_PROBE
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMAWR_PROBE_WFDMA_AXI0_R2A_DMAWR_PROBE_ADD\
R \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMAWR_PROBE_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMAWR_PROBE_WFDMA_AXI0_R2A_DMAWR_PROBE_MAS\
K \
0xFFFFFFFF /* WFDMA_AXI0_R2A_DMAWR_PROBE[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMAWR_PROBE_WFDMA_AXI0_R2A_DMAWR_PROBE_SHF\
T \
0

/*
* ---WFDMA_AXI0_R2A_DMARD_PROBE (0x18027000 + 0x514)---
* WFDMA_AXI0_R2A_DMARD_PROBE[31..0] - (RO) WFDMA_AXI0_R2A_DMARD_PROBE
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMARD_PROBE_WFDMA_AXI0_R2A_DMARD_PROBE_ADD\
R \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMARD_PROBE_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMARD_PROBE_WFDMA_AXI0_R2A_DMARD_PROBE_MAS\
K \
0xFFFFFFFF /* WFDMA_AXI0_R2A_DMARD_PROBE[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_DMARD_PROBE_WFDMA_AXI0_R2A_DMARD_PROBE_SHF\
T \
0

/*
* ---WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0 (0x18027000 + 0x518)---
* WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0[31..0] - (RO) WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0_WFDMA_AXI0_R2A_WR_DBG_AXI\
M_OUT0_ADDR \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0_WFDMA_AXI0_R2A_WR_DBG_AXI\
M_OUT0_MASK \
0xFFFFFFFF /* WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT0_WFDMA_AXI0_R2A_WR_DBG_AXI\
M_OUT0_SHFT \
0

/*
* ---WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1 (0x18027000 + 0x51C)---
* WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1[31..0] - (RO) WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1_WFDMA_AXI0_R2A_WR_DBG_AXI\
M_OUT1_ADDR \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1_WFDMA_AXI0_R2A_WR_DBG_AXI\
M_OUT1_MASK \
0xFFFFFFFF /* WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_WR_DBG_AXIM_OUT1_WFDMA_AXI0_R2A_WR_DBG_AXI\
M_OUT1_SHFT \
0

/*
* ---WFDMA_AXI0_R2A_AXI_SLP_STS (0x18027000 + 0x520)---
* WFDMA_AXI0_R2A_AXI_RD_SLP_STS[15..0] - (RO) WFDMA_AXI0_R2A_AXI_RD_SLP_STS
* WFDMA_AXI0_R2A_AXI_WR_SLP_STS[31..16] - (RO) WFDMA_AXI0_R2A_AXI_WR_SLP_STS
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_WFDMA_AXI0_R2A_AXI_WR_SLP_STS_\
ADDR \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_WFDMA_AXI0_R2A_AXI_WR_SLP_STS_\
MASK \
0xFFFF0000 /* WFDMA_AXI0_R2A_AXI_WR_SLP_STS[31..16] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_WFDMA_AXI0_R2A_AXI_WR_SLP_STS_\
SHFT \
16
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_WFDMA_AXI0_R2A_AXI_RD_SLP_STS_\
ADDR \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_WFDMA_AXI0_R2A_AXI_RD_SLP_STS_\
MASK \
0x0000FFFF /* WFDMA_AXI0_R2A_AXI_RD_SLP_STS[15..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_AXI_SLP_STS_WFDMA_AXI0_R2A_AXI_RD_SLP_STS_\
SHFT \
0

/*
* ---WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0 (0x18027000 + 0x524)---
* WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0[31..0] - (RO) WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0_WFDMA_AXI0_R2A_RD_DBG_AXI\
M_OUT0_ADDR \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0_WFDMA_AXI0_R2A_RD_DBG_AXI\
M_OUT0_MASK \
0xFFFFFFFF /* WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT0_WFDMA_AXI0_R2A_RD_DBG_AXI\
M_OUT0_SHFT \
0

/*
* ---WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1 (0x18027000 + 0x528)---
* WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1[31..0] - (RO) WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1_WFDMA_AXI0_R2A_RD_DBG_AXI\
M_OUT1_ADDR \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1_WFDMA_AXI0_R2A_RD_DBG_AXI\
M_OUT1_MASK \
0xFFFFFFFF /* WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_RD_DBG_AXIM_OUT1_WFDMA_AXI0_R2A_RD_DBG_AXI\
M_OUT1_SHFT \
0

/*
* ---WFDMA_AXI0_R2A_FSM_CMD_ST (0x18027000 + 0x52C)---
* WFDMA_AXI0_R2A_FSM_CMD_ST[31..0] - (RO) WFDMA_AXI0_R2A_FSM_CMD_ST
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_CMD_ST_WFDMA_AXI0_R2A_FSM_CMD_ST_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_CMD_ST_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_CMD_ST_WFDMA_AXI0_R2A_FSM_CMD_ST_MASK \
	0xFFFFFFFF /* WFDMA_AXI0_R2A_FSM_CMD_ST[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_CMD_ST_WFDMA_AXI0_R2A_FSM_CMD_ST_SHFT \
	0

/*
* ---WFDMA_AXI0_R2A_FSM_DAT_ST (0x18027000 + 0x530)---
* WFDMA_AXI0_R2A_FSM_DAT_ST[31..0] - (RO) WFDMA_AXI0_R2A_FSM_DAT_ST
*/
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_DAT_ST_WFDMA_AXI0_R2A_FSM_DAT_ST_ADDR \
	WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_DAT_ST_ADDR
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_DAT_ST_WFDMA_AXI0_R2A_FSM_DAT_ST_MASK \
	0xFFFFFFFF /* WFDMA_AXI0_R2A_FSM_DAT_ST[31..0] */
#define \
WF_WFDMA_EXT_WRAP_CSR_WFDMA_AXI0_R2A_FSM_DAT_ST_WFDMA_AXI0_R2A_FSM_DAT_ST_SHFT \
	0

#ifdef __cplusplus
}
#endif

#endif /* __WF_WFDMA_EXT_WRAP_CSR_REGS_H__ */
