/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2022 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5873_CKGEN00_H
#define _DT_BINDINGS_CLK_MT5873_CKGEN00_H
#define REG_CKG_S_CALC 0x0
#define REG_CKG_S_CALC_S 2
#define REG_CKG_S_CALC_E 4
#define REG_CKG_S_CORECLK 0x8
#define REG_CKG_S_CORECLK_S 2
#define REG_CKG_S_CORECLK_E 2
#define REG_CKG_S_CORECLK_MID 0x10
#define REG_CKG_S_CORECLK_MID_S 2
#define REG_CKG_S_CORECLK_MID_E 2
#define REG_CKG_S_SCLK 0x18
#define REG_CKG_S_SCLK_S 2
#define REG_CKG_S_SCLK_E 2
#define REG_CKG_S_SCLK_MID 0x20
#define REG_CKG_S_SCLK_MID_S 2
#define REG_CKG_S_SCLK_MID_E 2
#define REG_CKG_S_BIU 0x28
#define REG_CKG_S_BIU_S 2
#define REG_CKG_S_BIU_E 3
#define REG_CKG_S_CALC_MCUSYS 0x30
#define REG_CKG_S_CALC_MCUSYS_S 2
#define REG_CKG_S_CALC_MCUSYS_E 4
#define REG_CKG_S_EMI0_MCUSYS 0x38
#define REG_CKG_S_EMI0_MCUSYS_S 2
#define REG_CKG_S_EMI0_MCUSYS_E 2
#define REG_CKG_S_EMI1_MCUSYS 0x40
#define REG_CKG_S_EMI1_MCUSYS_S 2
#define REG_CKG_S_EMI1_MCUSYS_E 2
#define REG_CKG_S_MIPS_SYN_ARMPLL 0x50
#define REG_CKG_S_MIPS_SYN_ARMPLL_S 0
#define REG_CKG_S_MIPS_SYN_ARMPLL_E 1
#define REG_CKG_S_XTAL_MPLL 0x58
#define REG_CKG_S_XTAL_MPLL_S 2
#define REG_CKG_S_XTAL_MPLL_E 2
#define REG_CKG_PTP 0x60
#define REG_CKG_PTP_S 0
#define REG_CKG_PTP_E 3
#define REG_CKG_S_LZMA_MCUSYS 0x68
#define REG_CKG_S_LZMA_MCUSYS_S 2
#define REG_CKG_S_LZMA_MCUSYS_E 2
#define REG_CKG_S_MPU_MCUSYS 0x70
#define REG_CKG_S_MPU_MCUSYS_S 2
#define REG_CKG_S_MPU_MCUSYS_E 2
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP 0xcc
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_S 0
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_E 4
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD 0xcc
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD_S 12
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD_E 12
#define REG_CKG_S_ZDEC_LZD 0x118
#define REG_CKG_S_ZDEC_LZD_S 2
#define REG_CKG_S_ZDEC_LZD_E 3
#define REG_CKG_S_ZDEC_VLD 0x118
#define REG_CKG_S_ZDEC_VLD_S 10
#define REG_CKG_S_ZDEC_VLD_E 11
#define REG_CKG_S_DRAMC_CH0 0x120
#define REG_CKG_S_DRAMC_CH0_S 2
#define REG_CKG_S_DRAMC_CH0_E 3
#define REG_CKG_S_DRAMC_CH2 0x128
#define REG_CKG_S_DRAMC_CH2_S 2
#define REG_CKG_S_DRAMC_CH2_E 3
#define REG_CKG_DRAMC_CH4 0x130
#define REG_CKG_DRAMC_CH4_S 0
#define REG_CKG_DRAMC_CH4_E 3
#define REG_CKG_S_DRAMC0_CGCLK_FAST_CHA 0x138
#define REG_CKG_S_DRAMC0_CGCLK_FAST_CHA_S 2
#define REG_CKG_S_DRAMC0_CGCLK_FAST_CHA_E 2
#define REG_CKG_S_DRAMC0_CGCLK_FAST_CHB 0x138
#define REG_CKG_S_DRAMC0_CGCLK_FAST_CHB_S 6
#define REG_CKG_S_DRAMC0_CGCLK_FAST_CHB_E 6
#define REG_CKG_S_MCU_NONPM_DRAMC0 0x13c
#define REG_CKG_S_MCU_NONPM_DRAMC0_S 2
#define REG_CKG_S_MCU_NONPM_DRAMC0_E 2
#define REG_CKG_S_SMI 0x1d8
#define REG_CKG_S_SMI_S 2
#define REG_CKG_S_SMI_E 2
#define REG_CKG_VIVA_SMI_BRG 0x1f4
#define REG_CKG_VIVA_SMI_BRG_S 0
#define REG_CKG_VIVA_SMI_BRG_E 1
#define REG_CKG_FRC_IMI 0x260
#define REG_CKG_FRC_IMI_S 0
#define REG_CKG_FRC_IMI_E 3
#define REG_CKG_S_IMI 0x268
#define REG_CKG_S_IMI_S 2
#define REG_CKG_S_IMI_E 3
#define REG_CKG_S_LZMA 0x270
#define REG_CKG_S_LZMA_S 2
#define REG_CKG_S_LZMA_E 3
#define REG_CKG_S_SRAM_SHARE_35 0x750
#define REG_CKG_S_SRAM_SHARE_35_S 2
#define REG_CKG_S_SRAM_SHARE_35_E 2
#define REG_CKG_S_SRAM_SHARE_36 0x758
#define REG_CKG_S_SRAM_SHARE_36_S 2
#define REG_CKG_S_SRAM_SHARE_36_E 2
#define REG_CKG_S_SRAM_SHARE_40 0x760
#define REG_CKG_S_SRAM_SHARE_40_S 2
#define REG_CKG_S_SRAM_SHARE_40_E 2
#define REG_CKG_S_SRAM_SHARE_47 0x780
#define REG_CKG_S_SRAM_SHARE_47_S 2
#define REG_CKG_S_SRAM_SHARE_47_E 2
#define REG_CKG_S_SRAM_SHARE_68_0 0x7f8
#define REG_CKG_S_SRAM_SHARE_68_0_S 2
#define REG_CKG_S_SRAM_SHARE_68_0_E 2
#define REG_CKG_S_SRAM_SHARE_70 0x810
#define REG_CKG_S_SRAM_SHARE_70_S 2
#define REG_CKG_S_SRAM_SHARE_70_E 2
#define REG_CKG_S_IRS 0xb08
#define REG_CKG_S_IRS_S 2
#define REG_CKG_S_IRS_E 4
#define REG_CKG_S_AESDMA 0xb10
#define REG_CKG_S_AESDMA_S 2
#define REG_CKG_S_AESDMA_E 3
#define REG_CKG_S_PARSER 0xb18
#define REG_CKG_S_PARSER_S 2
#define REG_CKG_S_PARSER_E 3
#define REG_CKG_S_VIVA_PARSER 0xb18
#define REG_CKG_S_VIVA_PARSER_S 10
#define REG_CKG_S_VIVA_PARSER_E 11
#define REG_CKG_S_SMART2 0xb28
#define REG_CKG_S_SMART2_S 2
#define REG_CKG_S_SMART2_E 3
#define REG_CKG_S_SMART 0xb30
#define REG_CKG_S_SMART_S 2
#define REG_CKG_S_SMART_E 3
#define REG_CKG_S_TSO2_OUT_DIV_MN_SRC 0xb38
#define REG_CKG_S_TSO2_OUT_DIV_MN_SRC_S 2
#define REG_CKG_S_TSO2_OUT_DIV_MN_SRC_E 4
#define REG_CKG_S_TSO_OUT_DIV_MN_SRC 0xb40
#define REG_CKG_S_TSO_OUT_DIV_MN_SRC_S 2
#define REG_CKG_S_TSO_OUT_DIV_MN_SRC_E 4
#define REG_CKG_S_TSP 0xb48
#define REG_CKG_S_TSP_S 2
#define REG_CKG_S_TSP_E 3
#define REG_CKG_S_FIQ0_27M 0xb50
#define REG_CKG_S_FIQ0_27M_S 2
#define REG_CKG_S_FIQ0_27M_E 4
#define REG_CKG_S_MM0_27M 0xb58
#define REG_CKG_S_MM0_27M_S 2
#define REG_CKG_S_MM0_27M_E 4
#define REG_CKG_S_MM1_27M 0xb60
#define REG_CKG_S_MM1_27M_S 2
#define REG_CKG_S_MM1_27M_E 4
#define REG_CKG_S_PVR1_27M 0xb68
#define REG_CKG_S_PVR1_27M_S 2
#define REG_CKG_S_PVR1_27M_E 4
#define REG_CKG_S_PVR2_27M 0xb70
#define REG_CKG_S_PVR2_27M_S 2
#define REG_CKG_S_PVR2_27M_E 4
#define REG_CKG_S_PVR3_27M 0xb78
#define REG_CKG_S_PVR3_27M_S 2
#define REG_CKG_S_PVR3_27M_E 4
#define REG_CKG_S_PVR4_27M 0xb80
#define REG_CKG_S_PVR4_27M_S 2
#define REG_CKG_S_PVR4_27M_E 4
#define REG_CKG_S_STAMP 0xb88
#define REG_CKG_S_STAMP_S 2
#define REG_CKG_S_STAMP_E 2
#define REG_CKG_S_SYN_STC0 0xb90
#define REG_CKG_S_SYN_STC0_S 2
#define REG_CKG_S_SYN_STC0_E 4
#define REG_CKG_S_SYN_STC1 0xb98
#define REG_CKG_S_SYN_STC1_S 2
#define REG_CKG_S_SYN_STC1_E 4
#define REG_CKG_S_SYN_STC2 0xba0
#define REG_CKG_S_SYN_STC2_S 2
#define REG_CKG_S_SYN_STC2_E 4
#define REG_CKG_S_SYN_STC3 0xba8
#define REG_CKG_S_SYN_STC3_S 2
#define REG_CKG_S_SYN_STC3_E 4
#define REG_CKG_S_SYS_TIME0_27M 0xbb0
#define REG_CKG_S_SYS_TIME0_27M_S 2
#define REG_CKG_S_SYS_TIME0_27M_E 4
#define REG_CKG_S_SYS_TIME1_27M 0xbb8
#define REG_CKG_S_SYS_TIME1_27M_S 2
#define REG_CKG_S_SYS_TIME1_27M_E 4
#define REG_CKG_S_SYS_TIME2_27M 0xbc0
#define REG_CKG_S_SYS_TIME2_27M_S 2
#define REG_CKG_S_SYS_TIME2_27M_E 4
#define REG_CKG_S_SYS_TIME3_27M 0xbc8
#define REG_CKG_S_SYS_TIME3_27M_S 2
#define REG_CKG_S_SYS_TIME3_27M_E 4
#define REG_CKG_S_TLV0_27M 0xbd0
#define REG_CKG_S_TLV0_27M_S 2
#define REG_CKG_S_TLV0_27M_E 4
#define REG_CKG_S_TLV1_27M 0xbd8
#define REG_CKG_S_TLV1_27M_S 2
#define REG_CKG_S_TLV1_27M_E 4
#define REG_CKG_S_TLV2_27M 0xbe0
#define REG_CKG_S_TLV2_27M_S 2
#define REG_CKG_S_TLV2_27M_E 4
#define REG_CKG_S_TSIF0_27M 0xbe8
#define REG_CKG_S_TSIF0_27M_S 2
#define REG_CKG_S_TSIF0_27M_E 4
#define REG_CKG_S_TSO2_CH1_27M 0xbf0
#define REG_CKG_S_TSO2_CH1_27M_S 2
#define REG_CKG_S_TSO2_CH1_27M_E 4
#define REG_CKG_S_TSO2_CH5_27M 0xbf8
#define REG_CKG_S_TSO2_CH5_27M_S 2
#define REG_CKG_S_TSO2_CH5_27M_E 4
#define REG_CKG_S_TSO2_CH6_27M 0xc00
#define REG_CKG_S_TSO2_CH6_27M_S 2
#define REG_CKG_S_TSO2_CH6_27M_E 4
#define REG_CKG_S_P_TSO2_OUT 0xc08
#define REG_CKG_S_P_TSO2_OUT_S 2
#define REG_CKG_S_P_TSO2_OUT_E 4
#define REG_CKG_S_TSO_CH1_27M 0xc10
#define REG_CKG_S_TSO_CH1_27M_S 2
#define REG_CKG_S_TSO_CH1_27M_E 4
#define REG_CKG_S_TSO_CH5_27M 0xc18
#define REG_CKG_S_TSO_CH5_27M_S 2
#define REG_CKG_S_TSO_CH5_27M_E 4
#define REG_CKG_S_TSO_CH6_27M 0xc20
#define REG_CKG_S_TSO_CH6_27M_S 2
#define REG_CKG_S_TSO_CH6_27M_E 4
#define REG_CKG_S_P_TSO_OUT 0xc28
#define REG_CKG_S_P_TSO_OUT_S 2
#define REG_CKG_S_P_TSO_OUT_E 4
#define REG_CKG_S_PATH0_27M 0xc50
#define REG_CKG_S_PATH0_27M_S 2
#define REG_CKG_S_PATH0_27M_E 4
#define REG_CKG_S_PATH1_27M 0xc58
#define REG_CKG_S_PATH1_27M_S 2
#define REG_CKG_S_PATH1_27M_E 4
#define REG_CKG_S_PATH2_27M 0xc60
#define REG_CKG_S_PATH2_27M_S 2
#define REG_CKG_S_PATH2_27M_E 4
#define REG_CKG_S_PATH_FI_27M 0xc68
#define REG_CKG_S_PATH_FI_27M_S 2
#define REG_CKG_S_PATH_FI_27M_E 4
#define REG_CKG_S_VIVA_AB_MAC_10CH 0xc90
#define REG_CKG_S_VIVA_AB_MAC_10CH_S 2
#define REG_CKG_S_VIVA_AB_MAC_10CH_E 4
#define REG_CKG_S_SYNTH_PCM_TRX_256FS_VIVALDI9 0xc94
#define REG_CKG_S_SYNTH_PCM_TRX_256FS_VIVALDI9_S 2
#define REG_CKG_S_SYNTH_PCM_TRX_256FS_VIVALDI9_E 2
#define REG_CKG_S_AUSDM_3M 0xc98
#define REG_CKG_S_AUSDM_3M_S 2
#define REG_CKG_S_AUSDM_3M_E 3
#define REG_CKG_S_BCLK_I2S_ENCODER2 0xca0
#define REG_CKG_S_BCLK_I2S_ENCODER2_S 2
#define REG_CKG_S_BCLK_I2S_ENCODER2_E 2
#define REG_CKG_S_BCLK_I2S_ENCODER 0xca8
#define REG_CKG_S_BCLK_I2S_ENCODER_S 2
#define REG_CKG_S_BCLK_I2S_ENCODER_E 2
#define REG_CKG_S_EARC_TX_PLL_SYNTH_NPCM_256FS_REF 0xcac
#define REG_CKG_S_EARC_TX_PLL_SYNTH_NPCM_256FS_REF_S 2
#define REG_CKG_S_EARC_TX_PLL_SYNTH_NPCM_256FS_REF_E 2
#define REG_CKG_S_EARC_TX_PLL_256FS_REF 0xcb0
#define REG_CKG_S_EARC_TX_PLL_256FS_REF_S 2
#define REG_CKG_S_EARC_TX_PLL_256FS_REF_E 2
#define REG_CKG_S_EARC_TX_PLL_256FS_MUX 0xcb4
#define REG_CKG_S_EARC_TX_PLL_256FS_MUX_S 0
#define REG_CKG_S_EARC_TX_PLL_256FS_MUX_E 2
#define REG_CKG_S_VIVA_AB3_MAC 0xcb8
#define REG_CKG_S_VIVA_AB3_MAC_S 2
#define REG_CKG_S_VIVA_AB3_MAC_E 4
#define REG_CKG_S_VIVA_AB_MAC 0xcc0
#define REG_CKG_S_VIVA_AB_MAC_S 2
#define REG_CKG_S_VIVA_AB_MAC_E 3
#define REG_CKG_S_VIVA_ADC_512FS 0xcc8
#define REG_CKG_S_VIVA_ADC_512FS_S 2
#define REG_CKG_S_VIVA_ADC_512FS_E 3
#define REG_CKG_S_VIVA_AUDMA_V2_R1_256FS 0xcd0
#define REG_CKG_S_VIVA_AUDMA_V2_R1_256FS_S 2
#define REG_CKG_S_VIVA_AUDMA_V2_R1_256FS_E 2
#define REG_CKG_S_VIVA_AUDMA_V2_R1_SYNTH_REF 0xcd8
#define REG_CKG_S_VIVA_AUDMA_V2_R1_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_AUDMA_V2_R1_SYNTH_REF_E 4
#define REG_CKG_S_VIVA_AUDMA_V2_R2_256FS 0xce0
#define REG_CKG_S_VIVA_AUDMA_V2_R2_256FS_S 2
#define REG_CKG_S_VIVA_AUDMA_V2_R2_256FS_E 2
#define REG_CKG_S_VIVA_AUDMA_V2_R2_SYNTH_REF 0xce8
#define REG_CKG_S_VIVA_AUDMA_V2_R2_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_AUDMA_V2_R2_SYNTH_REF_E 4
#define REG_CKG_S_VIVA_AUPLL_IN 0xcf0
#define REG_CKG_S_VIVA_AUPLL_IN_S 2
#define REG_CKG_S_VIVA_AUPLL_IN_E 3
#define REG_CKG_S_VIVA_BCLK_I2S_DECODER2 0xcf8
#define REG_CKG_S_VIVA_BCLK_I2S_DECODER2_S 2
#define REG_CKG_S_VIVA_BCLK_I2S_DECODER2_E 3
#define REG_CKG_S_VIVA_BI2S_SYNTH_REF2 0xd08
#define REG_CKG_S_VIVA_BI2S_SYNTH_REF2_S 2
#define REG_CKG_S_VIVA_BI2S_SYNTH_REF2_E 4
#define REG_CKG_VIVA_CH1_256FSI 0xd10
#define REG_CKG_VIVA_CH1_256FSI_S 0
#define REG_CKG_VIVA_CH1_256FSI_E 2
#define REG_CKG_VIVA_CH2_256FSI 0xd18
#define REG_CKG_VIVA_CH2_256FSI_S 0
#define REG_CKG_VIVA_CH2_256FSI_E 2
#define REG_CKG_VIVA_CH3_256FSI 0xd20
#define REG_CKG_VIVA_CH3_256FSI_S 0
#define REG_CKG_VIVA_CH3_256FSI_E 2
#define REG_CKG_VIVA_CH4_256FSI 0xd28
#define REG_CKG_VIVA_CH4_256FSI_S 0
#define REG_CKG_VIVA_CH4_256FSI_E 2
#define REG_CKG_S_VIVA_CH5_256FSI 0xd30
#define REG_CKG_S_VIVA_CH5_256FSI_S 2
#define REG_CKG_S_VIVA_CH5_256FSI_E 2
#define REG_CKG_S_VIVA_CH6_256FSI 0xd38
#define REG_CKG_S_VIVA_CH6_256FSI_S 2
#define REG_CKG_S_VIVA_CH6_256FSI_E 2
#define REG_CKG_S_VIVA_CH7_256FSI 0xd40
#define REG_CKG_S_VIVA_CH7_256FSI_S 2
#define REG_CKG_S_VIVA_CH7_256FSI_E 2
#define REG_CKG_S_VIVA_CH8_256FSI 0xd48
#define REG_CKG_S_VIVA_CH8_256FSI_S 2
#define REG_CKG_S_VIVA_CH8_256FSI_E 2
#define REG_CKG_S_VIVA_CH9_256FSI 0xd50
#define REG_CKG_S_VIVA_CH9_256FSI_S 2
#define REG_CKG_S_VIVA_CH9_256FSI_E 2
#define REG_CKG_S_VIVA_CODEC_SH 0xd58
#define REG_CKG_S_VIVA_CODEC_SH_S 2
#define REG_CKG_S_VIVA_CODEC_SH_E 3
#define REG_CKG_S_VIVA_DAC_512FS 0xd60
#define REG_CKG_S_VIVA_DAC_512FS_S 2
#define REG_CKG_S_VIVA_DAC_512FS_E 3
#define REG_CKG_S_VIVA_DSP 0xd68
#define REG_CKG_S_VIVA_DSP_S 2
#define REG_CKG_S_VIVA_DSP_E 4
#define REG_CKG_S_VIVA_DVB1_SYNTH_REF 0xd70
#define REG_CKG_S_VIVA_DVB1_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_DVB1_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_DVB1_TIMING_GEN_256FS 0xd78
#define REG_CKG_S_VIVA_DVB1_TIMING_GEN_256FS_S 2
#define REG_CKG_S_VIVA_DVB1_TIMING_GEN_256FS_E 2
#define REG_CKG_S_VIVA_DVB2_SYNTH_REF 0xd80
#define REG_CKG_S_VIVA_DVB2_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_DVB2_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_DVB2_TIMING_GEN_256FS 0xd88
#define REG_CKG_S_VIVA_DVB2_TIMING_GEN_256FS_S 2
#define REG_CKG_S_VIVA_DVB2_TIMING_GEN_256FS_E 2
#define REG_CKG_S_VIVA_DVB3_SYNTH_REF 0xd90
#define REG_CKG_S_VIVA_DVB3_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_DVB3_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_DVB3_TIMING_GEN_256FS 0xd98
#define REG_CKG_S_VIVA_DVB3_TIMING_GEN_256FS_S 2
#define REG_CKG_S_VIVA_DVB3_TIMING_GEN_256FS_E 2
#define REG_CKG_S_VIVA_DVB4_SYNTH_REF 0xda0
#define REG_CKG_S_VIVA_DVB4_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_DVB4_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_DVB4_TIMING_GEN_256FS 0xda8
#define REG_CKG_S_VIVA_DVB4_TIMING_GEN_256FS_S 2
#define REG_CKG_S_VIVA_DVB4_TIMING_GEN_256FS_E 2
#define REG_CKG_S_VIVA_DVB5_TIMING_GEN_256FS 0xdb0
#define REG_CKG_S_VIVA_DVB5_TIMING_GEN_256FS_S 2
#define REG_CKG_S_VIVA_DVB5_TIMING_GEN_256FS_E 2
#define REG_CKG_S_VIVA_DVB6_TIMING_GEN_256FS 0xdb8
#define REG_CKG_S_VIVA_DVB6_TIMING_GEN_256FS_S 2
#define REG_CKG_S_VIVA_DVB6_TIMING_GEN_256FS_E 2
#define REG_CKG_S_VIVA_EARC_TX_32XCHXFS 0xdc0
#define REG_CKG_S_VIVA_EARC_TX_32XCHXFS_S 2
#define REG_CKG_S_VIVA_EARC_TX_32XCHXFS_E 2
#define REG_CKG_S_VIVA_EARC_TX_32XFS 0xdc8
#define REG_CKG_S_VIVA_EARC_TX_32XFS_S 2
#define REG_CKG_S_VIVA_EARC_TX_32XFS_E 2
#define REG_CKG_S_VIVA_EARC_TX_64XCHXFS 0xdd0
#define REG_CKG_S_VIVA_EARC_TX_64XCHXFS_S 2
#define REG_CKG_S_VIVA_EARC_TX_64XCHXFS_E 2
#define REG_CKG_S_VIVA_EARC_TX_GPA_SYNTH_REF 0xdd8
#define REG_CKG_S_VIVA_EARC_TX_GPA_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_EARC_TX_GPA_SYNTH_REF_E 2
#define REG_CKG_S_VIVA_EARC_TX_PLL 0xde0
#define REG_CKG_S_VIVA_EARC_TX_PLL_S 2
#define REG_CKG_S_VIVA_EARC_TX_PLL_E 2
#define REG_CKG_S_VIVA_EARC_TX_SOURCE_256FS 0xde8
#define REG_CKG_S_VIVA_EARC_TX_SOURCE_256FS_S 2
#define REG_CKG_S_VIVA_EARC_TX_SOURCE_256FS_E 2
#define REG_CKG_S_VIVA_EARC_TX_SYNTH_IIR_REF 0xdf0
#define REG_CKG_S_VIVA_EARC_TX_SYNTH_IIR_REF_S 2
#define REG_CKG_S_VIVA_EARC_TX_SYNTH_IIR_REF_E 2
#define REG_CKG_S_VIVA_EARC_TX_SYNTH_REF 0xdf8
#define REG_CKG_S_VIVA_EARC_TX_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_EARC_TX_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_FM_DEMODULATOR 0xe00
#define REG_CKG_S_VIVA_FM_DEMODULATOR_S 2
#define REG_CKG_S_VIVA_FM_DEMODULATOR_E 4
#define REG_CKG_S_VIVA_GPA_240FSO 0xe08
#define REG_CKG_S_VIVA_GPA_240FSO_S 2
#define REG_CKG_S_VIVA_GPA_240FSO_E 2
#define REG_CKG_S_VIVA_GPA_256FSO 0xe10
#define REG_CKG_S_VIVA_GPA_256FSO_S 2
#define REG_CKG_S_VIVA_GPA_256FSO_E 2
#define REG_CKG_S_VIVA_GPA_480FSO 0xe18
#define REG_CKG_S_VIVA_GPA_480FSO_S 2
#define REG_CKG_S_VIVA_GPA_480FSO_E 2
#define REG_CKG_S_VIVA_HDMI_RX2_MPLL_432 0xe20
#define REG_CKG_S_VIVA_HDMI_RX2_MPLL_432_S 2
#define REG_CKG_S_VIVA_HDMI_RX2_MPLL_432_E 2
#define REG_CKG_S_VIVA_HDMI_RX2_S2P_128FS 0xe28
#define REG_CKG_S_VIVA_HDMI_RX2_S2P_128FS_S 2
#define REG_CKG_S_VIVA_HDMI_RX2_S2P_128FS_E 2
#define REG_CKG_S_VIVA_HDMI_RX2_S2P_256FS 0xe30
#define REG_CKG_S_VIVA_HDMI_RX2_S2P_256FS_S 2
#define REG_CKG_S_VIVA_HDMI_RX2_S2P_256FS_E 2
#define REG_CKG_S_VIVA_HDMI_RX2_SYNTH_REF 0xe38
#define REG_CKG_S_VIVA_HDMI_RX2_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_HDMI_RX2_SYNTH_REF_E 2
#define REG_CKG_S_VIVA_HDMI_RX_MPLL_432 0xe48
#define REG_CKG_S_VIVA_HDMI_RX_MPLL_432_S 2
#define REG_CKG_S_VIVA_HDMI_RX_MPLL_432_E 2
#define REG_CKG_S_VIVA_HDMI_RX_S2P_128FS 0xe50
#define REG_CKG_S_VIVA_HDMI_RX_S2P_128FS_S 2
#define REG_CKG_S_VIVA_HDMI_RX_S2P_128FS_E 2
#define REG_CKG_S_VIVA_HDMI_RX_S2P_256FS 0xe58
#define REG_CKG_S_VIVA_HDMI_RX_S2P_256FS_S 2
#define REG_CKG_S_VIVA_HDMI_RX_S2P_256FS_E 2
#define REG_CKG_S_VIVA_HDMI_RX_SYNTH_REF 0xe60
#define REG_CKG_S_VIVA_HDMI_RX_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_HDMI_RX_SYNTH_REF_E 2
#define REG_CKG_S_VIVA_HDMI_TX_128FS 0xe70
#define REG_CKG_S_VIVA_HDMI_TX_128FS_S 2
#define REG_CKG_S_VIVA_HDMI_TX_128FS_E 2
#define REG_CKG_S_VIVA_HDMI_TX_256FS 0xe78
#define REG_CKG_S_VIVA_HDMI_TX_256FS_S 2
#define REG_CKG_S_VIVA_HDMI_TX_256FS_E 2
#define REG_CKG_S_VIVA_I2S_2_BCLK_SYNTH_REF 0xe80
#define REG_CKG_S_VIVA_I2S_2_BCLK_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_I2S_2_BCLK_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_I2S_BCLK_DG2 0xe88
#define REG_CKG_S_VIVA_I2S_BCLK_DG2_S 2
#define REG_CKG_S_VIVA_I2S_BCLK_DG2_E 2
#define REG_CKG_S_VIVA_I2S_BCLK_DG 0xe90
#define REG_CKG_S_VIVA_I2S_BCLK_DG_S 2
#define REG_CKG_S_VIVA_I2S_BCLK_DG_E 2
#define REG_CKG_S_VIVA_I2S_BCLK_SYNTH_REF 0xe98
#define REG_CKG_S_VIVA_I2S_BCLK_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_I2S_BCLK_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_I2S_MCLK_SYNTH_REF 0xea0
#define REG_CKG_S_VIVA_I2S_MCLK_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_I2S_MCLK_SYNTH_REF_E 2
#define REG_CKG_S_VIVA_I2S_SYNTH_REF 0xea8
#define REG_CKG_S_VIVA_I2S_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_I2S_SYNTH_REF_E 4
#define REG_CKG_S_VIVA_I2S_TRX_BCLK_TIMING_GEN 0xeb0
#define REG_CKG_S_VIVA_I2S_TRX_BCLK_TIMING_GEN_S 2
#define REG_CKG_S_VIVA_I2S_TRX_BCLK_TIMING_GEN_E 3
#define REG_CKG_S_VIVA_I2S_TRX_SYNTH_REF 0xeb8
#define REG_CKG_S_VIVA_I2S_TRX_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_I2S_TRX_SYNTH_REF_E 4
#define REG_CKG_S_VIVA_I2S_TX_FIFO_256FS 0xec0
#define REG_CKG_S_VIVA_I2S_TX_FIFO_256FS_S 2
#define REG_CKG_S_VIVA_I2S_TX_FIFO_256FS_E 2
#define REG_CKG_S_VIVA_MCLK_I2S_DECODER2 0xec8
#define REG_CKG_S_VIVA_MCLK_I2S_DECODER2_S 2
#define REG_CKG_S_VIVA_MCLK_I2S_DECODER2_E 4
#define REG_CKG_S_VIVA_MCLK_I2S_DECODER 0xed0
#define REG_CKG_S_VIVA_MCLK_I2S_DECODER_S 2
#define REG_CKG_S_VIVA_MCLK_I2S_DECODER_E 4
#define REG_CKG_S_VIVA_MCLK_I2S_ENCODER2 0xed8
#define REG_CKG_S_VIVA_MCLK_I2S_ENCODER2_S 2
#define REG_CKG_S_VIVA_MCLK_I2S_ENCODER2_E 4
#define REG_CKG_S_VIVA_MCLK_I2S_ENCODER 0xee0
#define REG_CKG_S_VIVA_MCLK_I2S_ENCODER_S 2
#define REG_CKG_S_VIVA_MCLK_I2S_ENCODER_E 4
#define REG_CKG_S_VIVA_NPCM2_SYNTH_REF 0xee8
#define REG_CKG_S_VIVA_NPCM2_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_NPCM2_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_NPCM3_SYNTH_REF 0xef0
#define REG_CKG_S_VIVA_NPCM3_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_NPCM3_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_NPCM4_256FS_TIMING_GEN 0xef8
#define REG_CKG_S_VIVA_NPCM4_256FS_TIMING_GEN_S 2
#define REG_CKG_S_VIVA_NPCM4_256FS_TIMING_GEN_E 2
#define REG_CKG_S_VIVA_NPCM4_SYNTH_REF 0xf00
#define REG_CKG_S_VIVA_NPCM4_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_NPCM4_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_NPCM5_256FS_TIMING_GEN 0xf08
#define REG_CKG_S_VIVA_NPCM5_256FS_TIMING_GEN_S 2
#define REG_CKG_S_VIVA_NPCM5_256FS_TIMING_GEN_E 2
#define REG_CKG_S_VIVA_NPCM5_SYNTH_REF 0xf10
#define REG_CKG_S_VIVA_NPCM5_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_NPCM5_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_NPCM_SYNTH_REF 0xf18
#define REG_CKG_S_VIVA_NPCM_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_NPCM_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_PCM_CLK_216 0xf20
#define REG_CKG_S_VIVA_PCM_CLK_216_S 2
#define REG_CKG_S_VIVA_PCM_CLK_216_E 2
#define REG_CKG_S_VIVA_PCM_CLK_AUPLL 0xf28
#define REG_CKG_S_VIVA_PCM_CLK_AUPLL_S 2
#define REG_CKG_S_VIVA_PCM_CLK_AUPLL_E 2
#define REG_CKG_S_VIVA_R2_WB 0xf30
#define REG_CKG_S_VIVA_R2_WB_S 2
#define REG_CKG_S_VIVA_R2_WB_E 2
#define REG_CKG_S_VIVA_RIU_BRG_R2 0xf38
#define REG_CKG_S_VIVA_RIU_BRG_R2_S 2
#define REG_CKG_S_VIVA_RIU_BRG_R2_E 2
#define REG_CKG_S_VIVA_RIU_R2 0xf40
#define REG_CKG_S_VIVA_RIU_R2_S 2
#define REG_CKG_S_VIVA_RIU_R2_E 3
#define REG_CKG_S_VIVA_SH 0xf48
#define REG_CKG_S_VIVA_SH_S 2
#define REG_CKG_S_VIVA_SH_E 2
#define REG_CKG_S_VIVA_SIF_ADC_CIC 0xf50
#define REG_CKG_S_VIVA_SIF_ADC_CIC_S 2
#define REG_CKG_S_VIVA_SIF_ADC_CIC_E 3
#define REG_CKG_S_VIVA_SIF_ADC_R2B_FIFO_IN 0xf58
#define REG_CKG_S_VIVA_SIF_ADC_R2B_FIFO_IN_S 2
#define REG_CKG_S_VIVA_SIF_ADC_R2B_FIFO_IN_E 3
#define REG_CKG_S_VIVA_SIF_ADC_R2B 0xf60
#define REG_CKG_S_VIVA_SIF_ADC_R2B_S 2
#define REG_CKG_S_VIVA_SIF_ADC_R2B_E 3
#define REG_CKG_S_SIF_CORDIC 0xf68
#define REG_CKG_S_SIF_CORDIC_S 2
#define REG_CKG_S_SIF_CORDIC_E 4
#define REG_CKG_S_VIVA_SIF_SYNTH 0xf70
#define REG_CKG_S_VIVA_SIF_SYNTH_S 2
#define REG_CKG_S_VIVA_SIF_SYNTH_E 3
#define REG_CKG_S_VIVA_SIN_GEN 0xf78
#define REG_CKG_S_VIVA_SIN_GEN_S 2
#define REG_CKG_S_VIVA_SIN_GEN_E 2
#define REG_CKG_S_VIVA_SPDIF_EXTEARC 0xf80
#define REG_CKG_S_VIVA_SPDIF_EXTEARC_S 2
#define REG_CKG_S_VIVA_SPDIF_EXTEARC_E 2
#define REG_CKG_S_VIVA_SPDIF_RX_128FS 0xf88
#define REG_CKG_S_VIVA_SPDIF_RX_128FS_S 2
#define REG_CKG_S_VIVA_SPDIF_RX_128FS_E 2
#define REG_CKG_S_VIVA_SPDIF_RX_DG 0xf90
#define REG_CKG_S_VIVA_SPDIF_RX_DG_S 2
#define REG_CKG_S_VIVA_SPDIF_RX_DG_E 2
#define REG_CKG_S_VIVA_SPDIF_RX_SYNTH_REF 0xf98
#define REG_CKG_S_VIVA_SPDIF_RX_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_SPDIF_RX_SYNTH_REF_E 3
#define REG_CKG_S_VIVA_SPDIF_TX2_128FS 0xfa0
#define REG_CKG_S_VIVA_SPDIF_TX2_128FS_S 2
#define REG_CKG_S_VIVA_SPDIF_TX2_128FS_E 2
#define REG_CKG_S_VIVA_SPDIF_TX2_256FS 0xfa8
#define REG_CKG_S_VIVA_SPDIF_TX2_256FS_S 2
#define REG_CKG_S_VIVA_SPDIF_TX2_256FS_E 2
#define REG_CKG_S_VIVA_SPDIF_TX_128FS 0xfb0
#define REG_CKG_S_VIVA_SPDIF_TX_128FS_S 2
#define REG_CKG_S_VIVA_SPDIF_TX_128FS_E 2
#define REG_CKG_S_VIVA_SPDIF_TX_256FS 0xfb8
#define REG_CKG_S_VIVA_SPDIF_TX_256FS_S 2
#define REG_CKG_S_VIVA_SPDIF_TX_256FS_E 2
#define REG_CKG_S_VIVA_SPDIF_TX_SYNTH_REF 0xfc0
#define REG_CKG_S_VIVA_SPDIF_TX_SYNTH_REF_S 2
#define REG_CKG_S_VIVA_SPDIF_TX_SYNTH_REF_E 2
#define REG_CKG_S_VIVA_SYNTH_2ND_ORDER 0xfc8
#define REG_CKG_S_VIVA_SYNTH_2ND_ORDER_S 2
#define REG_CKG_S_VIVA_SYNTH_2ND_ORDER_E 3
#define REG_CKG_S_VIVA_SYNTH_CODEC 0xfd0
#define REG_CKG_S_VIVA_SYNTH_CODEC_S 2
#define REG_CKG_S_VIVA_SYNTH_CODEC_E 3
#define REG_CKG_S_VIVA_TEST_BUS 0xfd8
#define REG_CKG_S_VIVA_TEST_BUS_S 2
#define REG_CKG_S_VIVA_TEST_BUS_E 2
#define REG_CKG_VIVA_VBDMA_MCU 0xfe0
#define REG_CKG_VIVA_VBDMA_MCU_S 0
#define REG_CKG_VIVA_VBDMA_MCU_E 2
#define REG_CKG_S_AUDMA_V2_R1_256FS 0x1020
#define REG_CKG_S_AUDMA_V2_R1_256FS_S 0
#define REG_CKG_S_AUDMA_V2_R1_256FS_E 0
#define REG_CKG_S_BCLK_I2S_ENCODER2_MUX 0x1028
#define REG_CKG_S_BCLK_I2S_ENCODER2_MUX_S 0
#define REG_CKG_S_BCLK_I2S_ENCODER2_MUX_E 2
#define REG_CKG_S_RV_AUDEC 0x102c
#define REG_CKG_S_RV_AUDEC_S 2
#define REG_CKG_S_RV_AUDEC_E 4
#define REG_CKG_S_BCLK_I2S_ENCODER_MUX 0x1030
#define REG_CKG_S_BCLK_I2S_ENCODER_MUX_S 0
#define REG_CKG_S_BCLK_I2S_ENCODER_MUX_E 2
#define REG_CKG_S_RV_AUSND 0x1034
#define REG_CKG_S_RV_AUSND_S 2
#define REG_CKG_S_RV_AUSND_E 4
#define REG_CKG_S_CH5_256FSI_MUX 0x1058
#define REG_CKG_S_CH5_256FSI_MUX_S 0
#define REG_CKG_S_CH5_256FSI_MUX_E 4
#define REG_CKG_S_CH6_256FSI_MUX 0x1060
#define REG_CKG_S_CH6_256FSI_MUX_S 0
#define REG_CKG_S_CH6_256FSI_MUX_E 4
#define REG_CKG_S_CH7_256FSI_MUX 0x1068
#define REG_CKG_S_CH7_256FSI_MUX_S 0
#define REG_CKG_S_CH7_256FSI_MUX_E 4
#define REG_CKG_S_CH8_256FSI_MUX 0x1070
#define REG_CKG_S_CH8_256FSI_MUX_S 0
#define REG_CKG_S_CH8_256FSI_MUX_E 4
#define REG_CKG_S_CH9_256FSI_MUX 0x1078
#define REG_CKG_S_CH9_256FSI_MUX_S 0
#define REG_CKG_S_CH9_256FSI_MUX_E 4
#define REG_CKG_S_DEC1_SYNTH_HDMI_CTSN_DIV_MUX 0x1080
#define REG_CKG_S_DEC1_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC1_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX 0x1088
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_S_DEC2_SYNTH_HDMI_CTSN_DIV_MUX 0x1090
#define REG_CKG_S_DEC2_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC2_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX 0x1098
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_S_DEC3_SYNTH_HDMI_CTSN_DIV_MUX 0x10a0
#define REG_CKG_S_DEC3_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC3_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX 0x10a8
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_S_DEC4_SYNTH_HDMI_CTSN_DIV_MUX 0x10b0
#define REG_CKG_S_DEC4_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC4_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX 0x10b8
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_S_DECODER1_FUNCTION_MUX 0x10c0
#define REG_CKG_S_DECODER1_FUNCTION_MUX_S 0
#define REG_CKG_S_DECODER1_FUNCTION_MUX_E 3
#define REG_CKG_S_DECODER2_FUNCTION_MUX 0x10c8
#define REG_CKG_S_DECODER2_FUNCTION_MUX_S 0
#define REG_CKG_S_DECODER2_FUNCTION_MUX_E 3
#define REG_CKG_S_DECODER3_FUNCTION_MUX 0x10d0
#define REG_CKG_S_DECODER3_FUNCTION_MUX_S 0
#define REG_CKG_S_DECODER3_FUNCTION_MUX_E 3
#define REG_CKG_S_DECODER4_FUNCTION_MUX 0x10d8
#define REG_CKG_S_DECODER4_FUNCTION_MUX_S 0
#define REG_CKG_S_DECODER4_FUNCTION_MUX_E 3
#define REG_CKG_S_EARC_TX_GPA_SYNTH_MUX 0x10e0
#define REG_CKG_S_EARC_TX_GPA_SYNTH_MUX_S 0
#define REG_CKG_S_EARC_TX_GPA_SYNTH_MUX_E 1
#define REG_CKG_S_EARC_TX_SOURCE_MUX 0x10e8
#define REG_CKG_S_EARC_TX_SOURCE_MUX_S 0
#define REG_CKG_S_EARC_TX_SOURCE_MUX_E 2
#define REG_CKG_S_HDMI2_PATGEN_EN 0x10f0
#define REG_CKG_S_HDMI2_PATGEN_EN_S 0
#define REG_CKG_S_HDMI2_PATGEN_EN_E 0
#define REG_CKG_S_HDMI_PATGEN_EN 0x10f8
#define REG_CKG_S_HDMI_PATGEN_EN_S 0
#define REG_CKG_S_HDMI_PATGEN_EN_E 0
#define REG_CKG_S_HDMI_RX_BYPASS_TO_TX 0x1100
#define REG_CKG_S_HDMI_RX_BYPASS_TO_TX_S 0
#define REG_CKG_S_HDMI_RX_BYPASS_TO_TX_E 0
#define REG_CKG_S_HDMI_TX_256FS_MUX0 0x1108
#define REG_CKG_S_HDMI_TX_256FS_MUX0_S 0
#define REG_CKG_S_HDMI_TX_256FS_MUX0_E 0
#define REG_CKG_S_HDMI_TX_256FS_MUX1 0x1110
#define REG_CKG_S_HDMI_TX_256FS_MUX1_S 0
#define REG_CKG_S_HDMI_TX_256FS_MUX1_E 0
#define REG_CKG_S_HDMI_TX_TO_I2S_TX 0x1118
#define REG_CKG_S_HDMI_TX_TO_I2S_TX_S 0
#define REG_CKG_S_HDMI_TX_TO_I2S_TX_E 0
#define REG_CKG_S_I2S_2_SYNTH_SSC_MUX 0x1120
#define REG_CKG_S_I2S_2_SYNTH_SSC_MUX_S 0
#define REG_CKG_S_I2S_2_SYNTH_SSC_MUX_E 0
#define REG_CKG_S_I2S_CH 0x1128
#define REG_CKG_S_I2S_CH_S 0
#define REG_CKG_S_I2S_CH_E 0
#define REG_CKG_S_I2S_SYNTH_SSC_MUX 0x1130
#define REG_CKG_S_I2S_SYNTH_SSC_MUX_S 0
#define REG_CKG_S_I2S_SYNTH_SSC_MUX_E 0
#define REG_CKG_S_PCM_MODE 0x1138
#define REG_CKG_S_PCM_MODE_S 0
#define REG_CKG_S_PCM_MODE_E 0
#define REG_CKG_S_R2_WB_MUX 0x1140
#define REG_CKG_S_R2_WB_MUX_S 0
#define REG_CKG_S_R2_WB_MUX_E 2
#define REG_CKG_S_SPDIF_EXTEARC_128FS_MUX 0x1148
#define REG_CKG_S_SPDIF_EXTEARC_128FS_MUX_S 0
#define REG_CKG_S_SPDIF_EXTEARC_128FS_MUX_E 2
#define REG_CKG_S_SPDIF_EXTEARC_256FS_MUX 0x1150
#define REG_CKG_S_SPDIF_EXTEARC_256FS_MUX_S 0
#define REG_CKG_S_SPDIF_EXTEARC_256FS_MUX_E 2
#define REG_CKG_S_SPDIF_EXTEARC_MUX 0x1158
#define REG_CKG_S_SPDIF_EXTEARC_MUX_S 0
#define REG_CKG_S_SPDIF_EXTEARC_MUX_E 0
#define REG_CKG_S_SPDIF_EXTEARC_MUX0 0x1160
#define REG_CKG_S_SPDIF_EXTEARC_MUX0_S 0
#define REG_CKG_S_SPDIF_EXTEARC_MUX0_E 0
#define REG_CKG_S_SPDIF_TX2_GPA_SYNTH_MUX 0x1168
#define REG_CKG_S_SPDIF_TX2_GPA_SYNTH_MUX_S 0
#define REG_CKG_S_SPDIF_TX2_GPA_SYNTH_MUX_E 1
#define REG_CKG_S_SPDIF_TX2_MUX 0x1170
#define REG_CKG_S_SPDIF_TX2_MUX_S 0
#define REG_CKG_S_SPDIF_TX2_MUX_E 2
#define REG_CKG_S_SPDIF_TX_GPA_SYNTH_MUX 0x1178
#define REG_CKG_S_SPDIF_TX_GPA_SYNTH_MUX_S 0
#define REG_CKG_S_SPDIF_TX_GPA_SYNTH_MUX_E 1
#define REG_CKG_S_SPDIF_TX_MUX 0x1180
#define REG_CKG_S_SPDIF_TX_MUX_S 0
#define REG_CKG_S_SPDIF_TX_MUX_E 2
#define REG_CKG_S_VIVA_I2S_TX_2_FIFO_256FS 0x1184
#define REG_CKG_S_VIVA_I2S_TX_2_FIFO_256FS_S 2
#define REG_CKG_S_VIVA_I2S_TX_2_FIFO_256FS_E 3
#define REG_CKG_S_EARC_AUDIO_EARC_DMACRO 0x1188
#define REG_CKG_S_EARC_AUDIO_EARC_DMACRO_S 2
#define REG_CKG_S_EARC_AUDIO_EARC_DMACRO_E 2
#define REG_CKG_S_CH10_256FSI_MUX 0x1194
#define REG_CKG_S_CH10_256FSI_MUX_S 0
#define REG_CKG_S_CH10_256FSI_MUX_E 4
#define REG_CKG_S_CH_M1_256FSI_MUX 0x1198
#define REG_CKG_S_CH_M1_256FSI_MUX_S 0
#define REG_CKG_S_CH_M1_256FSI_MUX_E 4
#define REG_CKG_S_CH_M2_256FSI_MUX 0x119c
#define REG_CKG_S_CH_M2_256FSI_MUX_S 0
#define REG_CKG_S_CH_M2_256FSI_MUX_E 4
#define REG_CKG_S_CH_M3_256FSI_MUX 0x11a0
#define REG_CKG_S_CH_M3_256FSI_MUX_S 0
#define REG_CKG_S_CH_M3_256FSI_MUX_E 4
#define REG_CKG_S_CH_M4_256FSI_MUX 0x11a4
#define REG_CKG_S_CH_M4_256FSI_MUX_S 0
#define REG_CKG_S_CH_M4_256FSI_MUX_E 4
#define REG_CKG_S_CH_M5_256FSI_MUX 0x11a8
#define REG_CKG_S_CH_M5_256FSI_MUX_S 0
#define REG_CKG_S_CH_M5_256FSI_MUX_E 4
#define REG_CKG_S_CH_M6_256FSI_MUX 0x11ac
#define REG_CKG_S_CH_M6_256FSI_MUX_S 0
#define REG_CKG_S_CH_M6_256FSI_MUX_E 3
#define REG_CKG_S_CH_M7_256FSI_MUX 0x11b0
#define REG_CKG_S_CH_M7_256FSI_MUX_S 0
#define REG_CKG_S_CH_M7_256FSI_MUX_E 3
#define REG_CKG_S_CH_M8_256FSI_MUX 0x11b4
#define REG_CKG_S_CH_M8_256FSI_MUX_S 0
#define REG_CKG_S_CH_M8_256FSI_MUX_E 3
#define REG_CKG_S_CH_M9_256FSI_MUX 0x11b8
#define REG_CKG_S_CH_M9_256FSI_MUX_S 0
#define REG_CKG_S_CH_M9_256FSI_MUX_E 3
#define REG_CKG_S_CH_M10_256FSI_MUX 0x11bc
#define REG_CKG_S_CH_M10_256FSI_MUX_S 0
#define REG_CKG_S_CH_M10_256FSI_MUX_E 3
#define REG_CKG_S_CH_M11_256FSI_MUX 0x11c0
#define REG_CKG_S_CH_M11_256FSI_MUX_S 0
#define REG_CKG_S_CH_M11_256FSI_MUX_E 3
#define REG_CKG_S_CH_M12_256FSI_MUX 0x11c4
#define REG_CKG_S_CH_M12_256FSI_MUX_S 0
#define REG_CKG_S_CH_M12_256FSI_MUX_E 3
#define REG_CKG_S_CH_M13_256FSI_MUX 0x11c8
#define REG_CKG_S_CH_M13_256FSI_MUX_S 0
#define REG_CKG_S_CH_M13_256FSI_MUX_E 3
#define REG_CKG_S_CH_M14_256FSI_MUX 0x11cc
#define REG_CKG_S_CH_M14_256FSI_MUX_S 0
#define REG_CKG_S_CH_M14_256FSI_MUX_E 3
#define REG_CKG_S_CH_M15_256FSI_MUX 0x11d0
#define REG_CKG_S_CH_M15_256FSI_MUX_S 0
#define REG_CKG_S_CH_M15_256FSI_MUX_E 3
#define REG_CKG_S_CH_M16_256FSI_MUX 0x11d4
#define REG_CKG_S_CH_M16_256FSI_MUX_S 0
#define REG_CKG_S_CH_M16_256FSI_MUX_E 3
#define REG_CKG_S_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX 0x11e0
#define REG_CKG_S_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_S_DEC1_SYNTH_SPDIF_CDR_DIV_MUX 0x11e4
#define REG_CKG_S_DEC1_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_S_DEC1_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_S_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX 0x11e8
#define REG_CKG_S_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_S_DEC2_SYNTH_SPDIF_CDR_DIV_MUX 0x11ec
#define REG_CKG_S_DEC2_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_S_DEC2_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_S_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX 0x11f0
#define REG_CKG_S_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_S_DEC3_SYNTH_SPDIF_CDR_DIV_MUX 0x11f4
#define REG_CKG_S_DEC3_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_S_DEC3_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_S_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX 0x11f8
#define REG_CKG_S_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_S_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_S_DEC4_SYNTH_SPDIF_CDR_DIV_MUX 0x11fc
#define REG_CKG_S_DEC4_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_S_DEC4_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_S_VIVA_CH10_256FSI 0x1208
#define REG_CKG_S_VIVA_CH10_256FSI_S 2
#define REG_CKG_S_VIVA_CH10_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M1_256FSI 0x120c
#define REG_CKG_S_VIVA_CH_M1_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M1_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M2_256FSI 0x1210
#define REG_CKG_S_VIVA_CH_M2_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M2_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M3_256FSI 0x1214
#define REG_CKG_S_VIVA_CH_M3_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M3_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M4_256FSI 0x1218
#define REG_CKG_S_VIVA_CH_M4_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M4_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M5_256FSI 0x121c
#define REG_CKG_S_VIVA_CH_M5_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M5_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M6_256FSI 0x1220
#define REG_CKG_S_VIVA_CH_M6_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M6_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M7_256FSI 0x1224
#define REG_CKG_S_VIVA_CH_M7_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M7_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M8_256FSI 0x1228
#define REG_CKG_S_VIVA_CH_M8_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M8_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M9_256FSI 0x122c
#define REG_CKG_S_VIVA_CH_M9_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M9_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M10_256FSI 0x1230
#define REG_CKG_S_VIVA_CH_M10_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M10_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M11_256FSI 0x1234
#define REG_CKG_S_VIVA_CH_M11_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M11_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M12_256FSI 0x1238
#define REG_CKG_S_VIVA_CH_M12_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M12_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M13_256FSI 0x123c
#define REG_CKG_S_VIVA_CH_M13_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M13_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M14_256FSI 0x1240
#define REG_CKG_S_VIVA_CH_M14_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M14_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M15_256FSI 0x1244
#define REG_CKG_S_VIVA_CH_M15_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M15_256FSI_E 2
#define REG_CKG_S_VIVA_CH_M16_256FSI 0x1248
#define REG_CKG_S_VIVA_CH_M16_256FSI_S 2
#define REG_CKG_S_VIVA_CH_M16_256FSI_E 2
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK 0x124c
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_S 2
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_E 4
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD 0x1250
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_S 2
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_E 2
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_FIFO 0x1254
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_FIFO_S 2
#define REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_FIFO_E 2
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK 0x1258
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_S 2
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_E 4
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD 0x125c
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_S 2
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_E 2
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_FIFO 0x1260
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_FIFO_S 2
#define REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_FIFO_E 2
#define REG_CKG_S_VIVA_SRC_MAC_BSPLINE 0x1264
#define REG_CKG_S_VIVA_SRC_MAC_BSPLINE_S 2
#define REG_CKG_S_VIVA_SRC_MAC_BSPLINE_E 3
#define REG_CKG_S_DISP_MFDEC 0x1268
#define REG_CKG_S_DISP_MFDEC_S 2
#define REG_CKG_S_DISP_MFDEC_E 3
#define REG_CKG_S_DISP_MFDEC_GPU_PAR_GP 0x1268
#define REG_CKG_S_DISP_MFDEC_GPU_PAR_GP_S 10
#define REG_CKG_S_DISP_MFDEC_GPU_PAR_GP_E 11
#define REG_CKG_S_GPD 0x1270
#define REG_CKG_S_GPD_S 2
#define REG_CKG_S_GPD_E 3
#define REG_CKG_S_NJPD 0x1278
#define REG_CKG_S_NJPD_S 2
#define REG_CKG_S_NJPD_E 3
#define REG_CKG_S_VDEC_LAE_SLOW 0x1288
#define REG_CKG_S_VDEC_LAE_SLOW_S 2
#define REG_CKG_S_VDEC_LAE_SLOW_E 4
#define REG_CKG_S_VDEC_SYS 0x1290
#define REG_CKG_S_VDEC_SYS_S 2
#define REG_CKG_S_VDEC_SYS_E 3
#define REG_CKG_S_VDEC_SYS_SLOW 0x1298
#define REG_CKG_S_VDEC_SYS_SLOW_S 2
#define REG_CKG_S_VDEC_SYS_SLOW_E 3
#define REG_CKG_S_ZDEC_LZD_TSP 0x1300
#define REG_CKG_S_ZDEC_LZD_TSP_S 2
#define REG_CKG_S_ZDEC_LZD_TSP_E 2
#define REG_CKG_S_BIST_SCBE 0x1340
#define REG_CKG_S_BIST_SCBE_S 2
#define REG_CKG_S_BIST_SCBE_E 4
#define REG_CKG_S_BIST_SCFE 0x1340
#define REG_CKG_S_BIST_SCFE_S 10
#define REG_CKG_S_BIST_SCFE_E 12
#define REG_CKG_S_BIST_SCTC 0x1348
#define REG_CKG_S_BIST_SCTC_S 2
#define REG_CKG_S_BIST_SCTC_E 4
#define REG_CKG_S_BIST_FRC 0x1348
#define REG_CKG_S_BIST_FRC_S 10
#define REG_CKG_S_BIST_FRC_E 12
#define REG_CKG_S_BIST_DEMOD0 0x1350
#define REG_CKG_S_BIST_DEMOD0_S 2
#define REG_CKG_S_BIST_DEMOD0_E 4
#define REG_CKG_S_BIST_DEMOD1 0x1350
#define REG_CKG_S_BIST_DEMOD1_S 10
#define REG_CKG_S_BIST_DEMOD1_E 12
#define REG_CKG_S_BIST_MOD 0x1358
#define REG_CKG_S_BIST_MOD_S 2
#define REG_CKG_S_BIST_MOD_E 4
#define REG_CKG_S_BIST_GPU_PAR_GP 0x1358
#define REG_CKG_S_BIST_GPU_PAR_GP_S 10
#define REG_CKG_S_BIST_GPU_PAR_GP_E 12
#define REG_CKG_S_BIST_DRAMC0 0x1360
#define REG_CKG_S_BIST_DRAMC0_S 2
#define REG_CKG_S_BIST_DRAMC0_E 4
#define REG_CKG_S_BIST_IP 0x1368
#define REG_CKG_S_BIST_IP_S 2
#define REG_CKG_S_BIST_IP_E 4
#define REG_CKG_S_BIST_HDMIRX 0x1368
#define REG_CKG_S_BIST_HDMIRX_S 10
#define REG_CKG_S_BIST_HDMIRX_E 12
#define REG_CKG_S_BIST_MCUSYS 0x1370
#define REG_CKG_S_BIST_MCUSYS_S 2
#define REG_CKG_S_BIST_MCUSYS_E 4
#define REG_CKG_S_BIST_MHEG5 0x1370
#define REG_CKG_S_BIST_MHEG5_S 10
#define REG_CKG_S_BIST_MHEG5_E 12
#define REG_CKG_S_BIST_TSP 0x1378
#define REG_CKG_S_BIST_TSP_S 2
#define REG_CKG_S_BIST_TSP_E 4
#define REG_CKG_S_BIST_VIVA 0x1378
#define REG_CKG_S_BIST_VIVA_S 10
#define REG_CKG_S_BIST_VIVA_E 12
#define REG_CKG_S_BIST_VDEC_CORE0 0x1380
#define REG_CKG_S_BIST_VDEC_CORE0_S 2
#define REG_CKG_S_BIST_VDEC_CORE0_E 4
#define REG_CKG_S_BIST_VDEC_CORE0_MERGE 0x1380
#define REG_CKG_S_BIST_VDEC_CORE0_MERGE_S 10
#define REG_CKG_S_BIST_VDEC_CORE0_MERGE_E 12
#define REG_CKG_S_BIST_TOP 0x1388
#define REG_CKG_S_BIST_TOP_S 2
#define REG_CKG_S_BIST_TOP_E 4
#define REG_CKG_S_BIST_AURV55 0x1388
#define REG_CKG_S_BIST_AURV55_S 10
#define REG_CKG_S_BIST_AURV55_E 12
#define REG_CKG_S_BIST2_AURV55 0x1390
#define REG_CKG_S_BIST2_AURV55_S 2
#define REG_CKG_S_BIST2_AURV55_E 4
#define REG_SW_EN_CALC2CALC_MCUSYS 0x1400
#define REG_SW_EN_CALC2CALC_MCUSYS_S 1
#define REG_SW_EN_CALC2CALC_MCUSYS_E 1
#define REG_SW_EN_GPU2GPU_PAR_GP 0x1444
#define REG_SW_EN_GPU2GPU_PAR_GP_S 0
#define REG_SW_EN_GPU2GPU_PAR_GP_E 0
#define REG_SW_EN_GPU_DFS2GPU_PAR_GP 0x1444
#define REG_SW_EN_GPU_DFS2GPU_PAR_GP_S 1
#define REG_SW_EN_GPU_DFS2GPU_PAR_GP_E 1
#define REG_SW_EN_XTAL_12M2MET 0x144c
#define REG_SW_EN_XTAL_12M2MET_S 0
#define REG_SW_EN_XTAL_12M2MET_E 0
#define REG_SW_EN_XTAL_24M2SYSCOUNT 0x1450
#define REG_SW_EN_XTAL_24M2SYSCOUNT_S 1
#define REG_SW_EN_XTAL_24M2SYSCOUNT_E 1
#define REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP 0x1454
#define REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP_S 0
#define REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP_E 0
#define REG_SW_EN_RIU_NONPM2SSUSB_U2_PHY_TOP 0x1454
#define REG_SW_EN_RIU_NONPM2SSUSB_U2_PHY_TOP_S 1
#define REG_SW_EN_RIU_NONPM2SSUSB_U2_PHY_TOP_E 1
#define REG_SW_EN_XTAL_24M_NONPM2SSUSB_U2_PHY_TOP 0x1454
#define REG_SW_EN_XTAL_24M_NONPM2SSUSB_U2_PHY_TOP_S 2
#define REG_SW_EN_XTAL_24M_NONPM2SSUSB_U2_PHY_TOP_E 2
#define REG_SW_EN_MCU_NONPM2DRAMC0 0x1468
#define REG_SW_EN_MCU_NONPM2DRAMC0_S 0
#define REG_SW_EN_MCU_NONPM2DRAMC0_E 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHB2DRAMC0 0x146c
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHB2DRAMC0_S 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHB2DRAMC0_E 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0 0x1474
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0_S 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0_E 0
#define REG_SW_EN_MPLL_208M_CHA2DRAMC0 0x147c
#define REG_SW_EN_MPLL_208M_CHA2DRAMC0_S 0
#define REG_SW_EN_MPLL_208M_CHA2DRAMC0_E 0
#define REG_SW_EN_MPLL_208M_CHB2DRAMC0 0x1484
#define REG_SW_EN_MPLL_208M_CHB2DRAMC0_S 0
#define REG_SW_EN_MPLL_208M_CHB2DRAMC0_E 0
#define REG_SW_EN_XTAL_24M2DRAMC0 0x148c
#define REG_SW_EN_XTAL_24M2DRAMC0_S 0
#define REG_SW_EN_XTAL_24M2DRAMC0_E 0
#define REG_SW_EN_EMI0_DEB2IP_WRAP 0x1498
#define REG_SW_EN_EMI0_DEB2IP_WRAP_S 0
#define REG_SW_EN_EMI0_DEB2IP_WRAP_E 0
#define REG_SW_EN_EMI02IP_WRAP 0x149c
#define REG_SW_EN_EMI02IP_WRAP_S 0
#define REG_SW_EN_EMI02IP_WRAP_E 0
#define REG_SW_EN_IP_WRAP2IP_WRAP 0x14b0
#define REG_SW_EN_IP_WRAP2IP_WRAP_S 0
#define REG_SW_EN_IP_WRAP2IP_WRAP_E 0
#define REG_SW_EN_XTAL_12M2IP_WRAP 0x14b4
#define REG_SW_EN_XTAL_12M2IP_WRAP_S 0
#define REG_SW_EN_XTAL_12M2IP_WRAP_E 0
#define REG_SW_EN_XTAL_24M2IP_WRAP 0x14b8
#define REG_SW_EN_XTAL_24M2IP_WRAP_S 0
#define REG_SW_EN_XTAL_24M2IP_WRAP_E 0
#define REG_SW_EN_RIU_NONPM2IP_WRAP 0x14b8
#define REG_SW_EN_RIU_NONPM2IP_WRAP_S 1
#define REG_SW_EN_RIU_NONPM2IP_WRAP_E 1
#define REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0 0x14bc
#define REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0_S 0
#define REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0_E 0
#define REG_SW_EN_MPLL_208M_MD322DRAMC0 0x14c4
#define REG_SW_EN_MPLL_208M_MD322DRAMC0_S 0
#define REG_SW_EN_MPLL_208M_MD322DRAMC0_E 0
#define REG_SW_EN_MPLL_432M2DRAMC0 0x14cc
#define REG_SW_EN_MPLL_432M2DRAMC0_S 0
#define REG_SW_EN_MPLL_432M2DRAMC0_E 0
#define REG_SW_EN_RC2DRAMC0 0x14d4
#define REG_SW_EN_RC2DRAMC0_S 0
#define REG_SW_EN_RC2DRAMC0_E 0
#define REG_SW_EN_SMI2CMDQ 0x14e4
#define REG_SW_EN_SMI2CMDQ_S 2
#define REG_SW_EN_SMI2CMDQ_E 2
#define REG_SW_EN_SMI2CORE0 0x14e4
#define REG_SW_EN_SMI2CORE0_S 3
#define REG_SW_EN_SMI2CORE0_E 3
#define REG_SW_EN_SMI2SMI_DEMOD0 0x14e4
#define REG_SW_EN_SMI2SMI_DEMOD0_S 6
#define REG_SW_EN_SMI2SMI_DEMOD0_E 6
#define REG_SW_EN_SMI2DSCRMB 0x14e4
#define REG_SW_EN_SMI2DSCRMB_S 7
#define REG_SW_EN_SMI2DSCRMB_E 7
#define REG_SW_EN_SMI2GE 0x14e4
#define REG_SW_EN_SMI2GE_S 11
#define REG_SW_EN_SMI2GE_E 11
#define REG_SW_EN_SMI2GMAC 0x14e4
#define REG_SW_EN_SMI2GMAC_S 12
#define REG_SW_EN_SMI2GMAC_E 12
#define REG_SW_EN_SMI2GPD 0x14e4
#define REG_SW_EN_SMI2GPD_S 13
#define REG_SW_EN_SMI2GPD_E 13
#define REG_SW_EN_SMI2JPD 0x14e4
#define REG_SW_EN_SMI2JPD_S 15
#define REG_SW_EN_SMI2JPD_E 15
#define REG_SW_EN_SMI2MAC 0x14e8
#define REG_SW_EN_SMI2MAC_S 0
#define REG_SW_EN_SMI2MAC_E 0
#define REG_SW_EN_SMI2MCU_BDMA 0x14e8
#define REG_SW_EN_SMI2MCU_BDMA_S 1
#define REG_SW_EN_SMI2MCU_BDMA_E 1
#define REG_SW_EN_SMI2MCU_DEMURA 0x14e8
#define REG_SW_EN_SMI2MCU_DEMURA_S 2
#define REG_SW_EN_SMI2MCU_DEMURA_E 2
#define REG_SW_EN_SMI2MCU_FUART 0x14e8
#define REG_SW_EN_SMI2MCU_FUART_S 3
#define REG_SW_EN_SMI2MCU_FUART_E 3
#define REG_SW_EN_SMI2MCU_M2MCU 0x14e8
#define REG_SW_EN_SMI2MCU_M2MCU_S 4
#define REG_SW_EN_SMI2MCU_M2MCU_E 4
#define REG_SW_EN_SMI2MCU_MIIC0 0x14e8
#define REG_SW_EN_SMI2MCU_MIIC0_S 5
#define REG_SW_EN_SMI2MCU_MIIC0_E 5
#define REG_SW_EN_SMI2MCU_MIIC1 0x14e8
#define REG_SW_EN_SMI2MCU_MIIC1_S 6
#define REG_SW_EN_SMI2MCU_MIIC1_E 6
#define REG_SW_EN_SMI2MCU_MIIC2 0x14e8
#define REG_SW_EN_SMI2MCU_MIIC2_S 7
#define REG_SW_EN_SMI2MCU_MIIC2_E 7
#define REG_SW_EN_SMI2MCU_MIIC3 0x14e8
#define REG_SW_EN_SMI2MCU_MIIC3_S 8
#define REG_SW_EN_SMI2MCU_MIIC3_E 8
#define REG_SW_EN_SMI2MCU_XD2MIU 0x14e8
#define REG_SW_EN_SMI2MCU_XD2MIU_S 9
#define REG_SW_EN_SMI2MCU_XD2MIU_E 9
#define REG_SW_EN_SMI2MHEG5_SMI 0x14e8
#define REG_SW_EN_SMI2MHEG5_SMI_S 10
#define REG_SW_EN_SMI2MHEG5_SMI_E 10
#define REG_SW_EN_SMI2SCIP 0x14ec
#define REG_SW_EN_SMI2SCIP_S 0
#define REG_SW_EN_SMI2SCIP_E 0
#define REG_SW_EN_SMI2SCM 0x14ec
#define REG_SW_EN_SMI2SCM_S 1
#define REG_SW_EN_SMI2SCM_E 1
#define REG_SW_EN_SMI2SCMO 0x14ec
#define REG_SW_EN_SMI2SCMO_S 2
#define REG_SW_EN_SMI2SCMO_E 2
#define REG_SW_EN_SMI2SCNR 0x14ec
#define REG_SW_EN_SMI2SCNR_S 4
#define REG_SW_EN_SMI2SCNR_E 4
#define REG_SW_EN_SMI2SCBE 0x14ec
#define REG_SW_EN_SMI2SCBE_S 5
#define REG_SW_EN_SMI2SCBE_E 5
#define REG_SW_EN_SMI2SCTC 0x14ec
#define REG_SW_EN_SMI2SCTC_S 8
#define REG_SW_EN_SMI2SCTC_E 8
#define REG_SW_EN_SMI2SMI 0x14ec
#define REG_SW_EN_SMI2SMI_S 9
#define REG_SW_EN_SMI2SMI_E 9
#define REG_SW_EN_SMI2SSUSB 0x14ec
#define REG_SW_EN_SMI2SSUSB_S 11
#define REG_SW_EN_SMI2SSUSB_E 11
#define REG_SW_EN_SMI2TSO 0x14ec
#define REG_SW_EN_SMI2TSO_S 12
#define REG_SW_EN_SMI2TSO_E 12
#define REG_SW_EN_SMI2TSO2 0x14ec
#define REG_SW_EN_SMI2TSO2_S 13
#define REG_SW_EN_SMI2TSO2_E 13
#define REG_SW_EN_SMI2TSP 0x14ec
#define REG_SW_EN_SMI2TSP_S 14
#define REG_SW_EN_SMI2TSP_E 14
#define REG_SW_EN_SMI2VD 0x14ec
#define REG_SW_EN_SMI2VD_S 15
#define REG_SW_EN_SMI2VD_E 15
#define REG_SW_EN_SMI2VD_PES_PARSER 0x14f0
#define REG_SW_EN_SMI2VD_PES_PARSER_S 0
#define REG_SW_EN_SMI2VD_PES_PARSER_E 0
#define REG_SW_EN_SMI2LARB_TSP 0x14f0
#define REG_SW_EN_SMI2LARB_TSP_S 2
#define REG_SW_EN_SMI2LARB_TSP_E 2
#define REG_SW_EN_SMI_AESDMA2DSCRMB 0x14f0
#define REG_SW_EN_SMI_AESDMA2DSCRMB_S 3
#define REG_SW_EN_SMI_AESDMA2DSCRMB_E 3
#define REG_SW_EN_SMI_TSP2TSP 0x14f0
#define REG_SW_EN_SMI_TSP2TSP_S 4
#define REG_SW_EN_SMI_TSP2TSP_E 4
#define REG_SW_EN_SMI_FCIE2FCIE 0x14f0
#define REG_SW_EN_SMI_FCIE2FCIE_S 5
#define REG_SW_EN_SMI_FCIE2FCIE_E 5
#define REG_SW_EN_SMI_UHC2UHC 0x14f0
#define REG_SW_EN_SMI_UHC2UHC_S 6
#define REG_SW_EN_SMI_UHC2UHC_E 6
#define REG_SW_EN_VIVA_SMI2SMI 0x14f0
#define REG_SW_EN_VIVA_SMI2SMI_S 7
#define REG_SW_EN_VIVA_SMI2SMI_E 7
#define REG_SW_EN_SMI2DEMOD0 0x14f0
#define REG_SW_EN_SMI2DEMOD0_S 8
#define REG_SW_EN_SMI2DEMOD0_E 8
#define REG_SW_EN_SMI2DEMOD0_DVBTM 0x14f0
#define REG_SW_EN_SMI2DEMOD0_DVBTM_S 9
#define REG_SW_EN_SMI2DEMOD0_DVBTM_E 9
#define REG_SW_EN_SMI2DEMOD0_ISDBT 0x14f0
#define REG_SW_EN_SMI2DEMOD0_ISDBT_S 10
#define REG_SW_EN_SMI2DEMOD0_ISDBT_E 10
#define REG_SW_EN_SMI2DEMOD0_DTMB 0x14f0
#define REG_SW_EN_SMI2DEMOD0_DTMB_S 11
#define REG_SW_EN_SMI2DEMOD0_DTMB_E 11
#define REG_SW_EN_SMI2DEMOD0_ADC_DUMP 0x14f0
#define REG_SW_EN_SMI2DEMOD0_ADC_DUMP_S 12
#define REG_SW_EN_SMI2DEMOD0_ADC_DUMP_E 12
#define REG_SW_EN_SMI2MCU_MSPI0 0x14f0
#define REG_SW_EN_SMI2MCU_MSPI0_S 13
#define REG_SW_EN_SMI2MCU_MSPI0_E 13
#define REG_SW_EN_SMI2MCU_MSPI1 0x14f0
#define REG_SW_EN_SMI2MCU_MSPI1_S 14
#define REG_SW_EN_SMI2MCU_MSPI1_E 14
#define REG_SW_EN_SMI2MCU_MSPI2 0x14f0
#define REG_SW_EN_SMI2MCU_MSPI2_S 15
#define REG_SW_EN_SMI2MCU_MSPI2_E 15
#define REG_SW_EN_SMI2MCU_MSPI3 0x14f4
#define REG_SW_EN_SMI2MCU_MSPI3_S 0
#define REG_SW_EN_SMI2MCU_MSPI3_E 0
#define REG_SW_EN_SMI2MCU_MSPI4 0x14f4
#define REG_SW_EN_SMI2MCU_MSPI4_S 1
#define REG_SW_EN_SMI2MCU_MSPI4_E 1
#define REG_SW_EN_SMI2MCU_MSPI5 0x14f4
#define REG_SW_EN_SMI2MCU_MSPI5_S 2
#define REG_SW_EN_SMI2MCU_MSPI5_E 2
#define REG_SW_EN_SMI2MCU_MSPI6 0x14f4
#define REG_SW_EN_SMI2MCU_MSPI6_S 3
#define REG_SW_EN_SMI2MCU_MSPI6_E 3
#define REG_SW_EN_SMI2MCU_MSPI7 0x14f4
#define REG_SW_EN_SMI2MCU_MSPI7_S 4
#define REG_SW_EN_SMI2MCU_MSPI7_E 4
#define REG_SW_EN_SMI2MCU_MSPI_CILINK 0x14f4
#define REG_SW_EN_SMI2MCU_MSPI_CILINK_S 5
#define REG_SW_EN_SMI2MCU_MSPI_CILINK_E 5
#define REG_SW_EN_SMI2PEXTP 0x14f4
#define REG_SW_EN_SMI2PEXTP_S 6
#define REG_SW_EN_SMI2PEXTP_E 6
#define REG_SW_EN_SMI2UFS 0x14f4
#define REG_SW_EN_SMI2UFS_S 7
#define REG_SW_EN_SMI2UFS_E 7
#define REG_SW_EN_VIVA_SMI2SMI_BRG 0x14f4
#define REG_SW_EN_VIVA_SMI2SMI_BRG_S 9
#define REG_SW_EN_VIVA_SMI2SMI_BRG_E 9
#define REG_SW_EN_SMI2FRCCORE1 0x14f4
#define REG_SW_EN_SMI2FRCCORE1_S 10
#define REG_SW_EN_SMI2FRCCORE1_E 10
#define REG_SW_EN_SMI2FRCMISC 0x14f4
#define REG_SW_EN_SMI2FRCMISC_S 13
#define REG_SW_EN_SMI2FRCMISC_E 13
#define REG_SW_EN_SMI_SSUSB2SSUSB 0x14f4
#define REG_SW_EN_SMI_SSUSB2SSUSB_S 14
#define REG_SW_EN_SMI_SSUSB2SSUSB_E 14
#define REG_SW_EN_SMI2SMI_FRCCORE1 0x14f8
#define REG_SW_EN_SMI2SMI_FRCCORE1_S 0
#define REG_SW_EN_SMI2SMI_FRCCORE1_E 0
#define REG_SW_EN_SMI2AUDEC 0x14fc
#define REG_SW_EN_SMI2AUDEC_S 0
#define REG_SW_EN_SMI2AUDEC_E 0
#define REG_SW_EN_SMI2AUSND 0x14fc
#define REG_SW_EN_SMI2AUSND_S 1
#define REG_SW_EN_SMI2AUSND_E 1
#define REG_SW_EN_SMI2AURV55SMI 0x14fc
#define REG_SW_EN_SMI2AURV55SMI_S 2
#define REG_SW_EN_SMI2AURV55SMI_E 2
#define REG_SW_EN_SMI2AUDMA 0x14fc
#define REG_SW_EN_SMI2AUDMA_S 3
#define REG_SW_EN_SMI2AUDMA_E 3
#define REG_SW_EN_SMI2FRC_GALS 0x1504
#define REG_SW_EN_SMI2FRC_GALS_S 0
#define REG_SW_EN_SMI2FRC_GALS_E 0
#define REG_SW_EN_SMI2SCBE_GALS 0x1504
#define REG_SW_EN_SMI2SCBE_GALS_S 1
#define REG_SW_EN_SMI2SCBE_GALS_E 1
#define REG_SW_EN_SMI2SCFE_GALS 0x1504
#define REG_SW_EN_SMI2SCFE_GALS_S 2
#define REG_SW_EN_SMI2SCFE_GALS_E 2
#define REG_SW_EN_SMI2SCTC_GALS 0x1504
#define REG_SW_EN_SMI2SCTC_GALS_S 3
#define REG_SW_EN_SMI2SCTC_GALS_E 3
#define REG_SW_EN_SMI2SCFE_EMI 0x1508
#define REG_SW_EN_SMI2SCFE_EMI_S 0
#define REG_SW_EN_SMI2SCFE_EMI_E 0
#define REG_SW_EN_SMI2SCFE_SMI_IP 0x1508
#define REG_SW_EN_SMI2SCFE_SMI_IP_S 1
#define REG_SW_EN_SMI2SCFE_SMI_IP_E 1
#define REG_SW_EN_SMI2FRC_EMI 0x1508
#define REG_SW_EN_SMI2FRC_EMI_S 2
#define REG_SW_EN_SMI2FRC_EMI_E 2
#define REG_SW_EN_SMI2FRC_R2 0x1508
#define REG_SW_EN_SMI2FRC_R2_S 3
#define REG_SW_EN_SMI2FRC_R2_E 3
#define REG_SW_EN_IMI2SHARE_SRAM_IMI 0x1524
#define REG_SW_EN_IMI2SHARE_SRAM_IMI_S 0
#define REG_SW_EN_IMI2SHARE_SRAM_IMI_E 0
#define REG_SW_EN_IMI2UFS 0x1524
#define REG_SW_EN_IMI2UFS_S 1
#define REG_SW_EN_IMI2UFS_E 1
#define REG_SW_EN_IMI2TSP 0x1524
#define REG_SW_EN_IMI2TSP_S 2
#define REG_SW_EN_IMI2TSP_E 2
#define REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP 0x153c
#define REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP_S 0
#define REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP_E 0
#define REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY 0x153c
#define REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY_S 2
#define REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY_E 2
#define REG_SW_EN_XTAL_12M2MCU_BDMA 0x153c
#define REG_SW_EN_XTAL_12M2MCU_BDMA_S 3
#define REG_SW_EN_XTAL_12M2MCU_BDMA_E 3
#define REG_SW_EN_XTAL_12M2MCU_DEMURA 0x153c
#define REG_SW_EN_XTAL_12M2MCU_DEMURA_S 4
#define REG_SW_EN_XTAL_12M2MCU_DEMURA_E 4
#define REG_SW_EN_XTAL_12M2MCU_FUART 0x153c
#define REG_SW_EN_XTAL_12M2MCU_FUART_S 5
#define REG_SW_EN_XTAL_12M2MCU_FUART_E 5
#define REG_SW_EN_XTAL_12M2MCU_M2MCU 0x153c
#define REG_SW_EN_XTAL_12M2MCU_M2MCU_S 6
#define REG_SW_EN_XTAL_12M2MCU_M2MCU_E 6
#define REG_SW_EN_XTAL_12M2MCU_M2RIU 0x153c
#define REG_SW_EN_XTAL_12M2MCU_M2RIU_S 7
#define REG_SW_EN_XTAL_12M2MCU_M2RIU_E 7
#define REG_SW_EN_XTAL_12M2MCU_MCUIF 0x153c
#define REG_SW_EN_XTAL_12M2MCU_MCUIF_S 8
#define REG_SW_EN_XTAL_12M2MCU_MCUIF_E 8
#define REG_SW_EN_XTAL_12M2MCU_MIIC0 0x153c
#define REG_SW_EN_XTAL_12M2MCU_MIIC0_S 9
#define REG_SW_EN_XTAL_12M2MCU_MIIC0_E 9
#define REG_SW_EN_XTAL_12M2MCU_MIIC1 0x153c
#define REG_SW_EN_XTAL_12M2MCU_MIIC1_S 10
#define REG_SW_EN_XTAL_12M2MCU_MIIC1_E 10
#define REG_SW_EN_XTAL_12M2MCU_MIIC2 0x153c
#define REG_SW_EN_XTAL_12M2MCU_MIIC2_S 11
#define REG_SW_EN_XTAL_12M2MCU_MIIC2_E 11
#define REG_SW_EN_XTAL_12M2MCU_MIIC3 0x153c
#define REG_SW_EN_XTAL_12M2MCU_MIIC3_S 12
#define REG_SW_EN_XTAL_12M2MCU_MIIC3_E 12
#define REG_SW_EN_XTAL_12M2MCU_XD2MIU 0x153c
#define REG_SW_EN_XTAL_12M2MCU_XD2MIU_S 13
#define REG_SW_EN_XTAL_12M2MCU_XD2MIU_E 13
#define REG_SW_EN_XTAL_12M2PAD_TOP 0x153c
#define REG_SW_EN_XTAL_12M2PAD_TOP_S 14
#define REG_SW_EN_XTAL_12M2PAD_TOP_E 14
#define REG_SW_EN_XTAL_12M2PREARB2PMRIU 0x153c
#define REG_SW_EN_XTAL_12M2PREARB2PMRIU_S 15
#define REG_SW_EN_XTAL_12M2PREARB2PMRIU_E 15
#define REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP 0x1540
#define REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP_S 0
#define REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP_E 0
#define REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM 0x1540
#define REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM_S 1
#define REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM_E 1
#define REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE 0x1540
#define REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE_S 2
#define REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE_E 2
#define REG_SW_EN_XTAL_12M2TEST_CTRL 0x1540
#define REG_SW_EN_XTAL_12M2TEST_CTRL_S 3
#define REG_SW_EN_XTAL_12M2TEST_CTRL_E 3
#define REG_SW_EN_XTAL_12M2VD 0x1540
#define REG_SW_EN_XTAL_12M2VD_S 4
#define REG_SW_EN_XTAL_12M2VD_E 4
#define REG_SW_EN_XTAL_12M2MCU_MSPI0 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI0_S 5
#define REG_SW_EN_XTAL_12M2MCU_MSPI0_E 5
#define REG_SW_EN_XTAL_12M2MCU_MSPI1 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI1_S 6
#define REG_SW_EN_XTAL_12M2MCU_MSPI1_E 6
#define REG_SW_EN_XTAL_12M2MCU_MSPI2 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI2_S 7
#define REG_SW_EN_XTAL_12M2MCU_MSPI2_E 7
#define REG_SW_EN_XTAL_12M2MCU_MSPI3 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI3_S 8
#define REG_SW_EN_XTAL_12M2MCU_MSPI3_E 8
#define REG_SW_EN_XTAL_12M2MCU_MSPI4 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI4_S 9
#define REG_SW_EN_XTAL_12M2MCU_MSPI4_E 9
#define REG_SW_EN_XTAL_12M2MCU_MSPI5 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI5_S 10
#define REG_SW_EN_XTAL_12M2MCU_MSPI5_E 10
#define REG_SW_EN_XTAL_12M2MCU_MSPI6 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI6_S 11
#define REG_SW_EN_XTAL_12M2MCU_MSPI6_E 11
#define REG_SW_EN_XTAL_12M2MCU_MSPI7 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI7_S 12
#define REG_SW_EN_XTAL_12M2MCU_MSPI7_E 12
#define REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK 0x1540
#define REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK_S 13
#define REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK_E 13
#define REG_SW_EN_XTAL_24M2DMD_RST_CTRL 0x1558
#define REG_SW_EN_XTAL_24M2DMD_RST_CTRL_S 0
#define REG_SW_EN_XTAL_24M2DMD_RST_CTRL_E 0
#define REG_SW_EN_XTAL_24M2DSCRMB 0x1558
#define REG_SW_EN_XTAL_24M2DSCRMB_S 1
#define REG_SW_EN_XTAL_24M2DSCRMB_E 1
#define REG_SW_EN_XTAL_24M2GMAC 0x1558
#define REG_SW_EN_XTAL_24M2GMAC_S 2
#define REG_SW_EN_XTAL_24M2GMAC_E 2
#define REG_SW_EN_XTAL_24M2PEXTP 0x1558
#define REG_SW_EN_XTAL_24M2PEXTP_S 4
#define REG_SW_EN_XTAL_24M2PEXTP_E 4
#define REG_SW_EN_XTAL_24M2SSUSB 0x1558
#define REG_SW_EN_XTAL_24M2SSUSB_S 5
#define REG_SW_EN_XTAL_24M2SSUSB_E 5
#define REG_SW_EN_XTAL_24M2TOP 0x1558
#define REG_SW_EN_XTAL_24M2TOP_S 6
#define REG_SW_EN_XTAL_24M2TOP_E 6
#define REG_SW_EN_XTAL_24M2USB20 0x1558
#define REG_SW_EN_XTAL_24M2USB20_S 8
#define REG_SW_EN_XTAL_24M2USB20_E 8
#define REG_SW_EN_ICLAMP2DMD_ANA 0x1574
#define REG_SW_EN_ICLAMP2DMD_ANA_S 0
#define REG_SW_EN_ICLAMP2DMD_ANA_E 0
#define REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA 0x1578
#define REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA_S 0
#define REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA 0x157c
#define REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA 0x1580
#define REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA_E 0
#define REG_SW_EN_ACIFIR2DEMOD0 0x1584
#define REG_SW_EN_ACIFIR2DEMOD0_S 0
#define REG_SW_EN_ACIFIR2DEMOD0_E 0
#define REG_SW_EN_ADCD_I_IN2DMD_ANA 0x1588
#define REG_SW_EN_ADCD_I_IN2DMD_ANA_S 0
#define REG_SW_EN_ADCD_I_IN2DMD_ANA_E 0
#define REG_SW_EN_ADCD_I_OUT2DMD_ANA 0x158c
#define REG_SW_EN_ADCD_I_OUT2DMD_ANA_S 0
#define REG_SW_EN_ADCD_I_OUT2DMD_ANA_E 0
#define REG_SW_EN_ADCD_Q_IN2DMD_ANA 0x1590
#define REG_SW_EN_ADCD_Q_IN2DMD_ANA_S 0
#define REG_SW_EN_ADCD_Q_IN2DMD_ANA_E 0
#define REG_SW_EN_ADCD_Q_OUT2DMD_ANA 0x1594
#define REG_SW_EN_ADCD_Q_OUT2DMD_ANA_S 0
#define REG_SW_EN_ADCD_Q_OUT2DMD_ANA_E 0
#define REG_SW_EN_ADCD2DEMOD0 0x1598
#define REG_SW_EN_ADCD2DEMOD0_S 0
#define REG_SW_EN_ADCD2DEMOD0_E 0
#define REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0 0x159c
#define REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0_S 0
#define REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0_E 0
#define REG_SW_EN_ATSC_CE252DEMOD0 0x15a0
#define REG_SW_EN_ATSC_CE252DEMOD0_S 0
#define REG_SW_EN_ATSC_CE252DEMOD0_E 0
#define REG_SW_EN_ATSC_EQ252DEMOD0 0x15a4
#define REG_SW_EN_ATSC_EQ252DEMOD0_S 0
#define REG_SW_EN_ATSC_EQ252DEMOD0_E 0
#define REG_SW_EN_ATSC200_PH12DEMOD0 0x15a8
#define REG_SW_EN_ATSC200_PH12DEMOD0_S 0
#define REG_SW_EN_ATSC200_PH12DEMOD0_E 0
#define REG_SW_EN_ATSC200_PH32DEMOD0 0x15ac
#define REG_SW_EN_ATSC200_PH32DEMOD0_S 0
#define REG_SW_EN_ATSC200_PH32DEMOD0_E 0
#define REG_SW_EN_ATSC252DEMOD0 0x15b0
#define REG_SW_EN_ATSC252DEMOD0_S 0
#define REG_SW_EN_ATSC252DEMOD0_E 0
#define REG_SW_EN_ATSC4002DEMOD0 0x15b4
#define REG_SW_EN_ATSC4002DEMOD0_S 0
#define REG_SW_EN_ATSC4002DEMOD0_E 0
#define REG_SW_EN_ATSC502DEMOD0 0x15b8
#define REG_SW_EN_ATSC502DEMOD0_S 0
#define REG_SW_EN_ATSC502DEMOD0_E 0
#define REG_SW_EN_DEC_XTAL_I2DMD_ANA 0x15bc
#define REG_SW_EN_DEC_XTAL_I2DMD_ANA_S 0
#define REG_SW_EN_DEC_XTAL_I2DMD_ANA_E 0
#define REG_SW_EN_DEC_XTAL_Q2DMD_ANA 0x15c0
#define REG_SW_EN_DEC_XTAL_Q2DMD_ANA_S 0
#define REG_SW_EN_DEC_XTAL_Q2DMD_ANA_E 0
#define REG_SW_EN_DEINTER2DEMOD1 0x15c4
#define REG_SW_EN_DEINTER2DEMOD1_S 0
#define REG_SW_EN_DEINTER2DEMOD1_E 0
#define REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV 0x15c8
#define REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV_S 0
#define REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV_E 0
#define REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL 0x15cc
#define REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMD_DMA2DEMOD0 0x15d0
#define REG_SW_EN_DMD_DMA2DEMOD0_S 0
#define REG_SW_EN_DMD_DMA2DEMOD0_E 0
#define REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL 0x15d4
#define REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL 0x15d8
#define REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL 0x15dc
#define REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL 0x15e0
#define REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL 0x15e4
#define REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL 0x15e8
#define REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL 0x15ec
#define REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL 0x15f0
#define REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL 0x15f4
#define REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL 0x15f8
#define REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL 0x15fc
#define REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL 0x1600
#define REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL 0x1604
#define REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL 0x1608
#define REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL 0x160c
#define REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL 0x1610
#define REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DTMB_ADC2DEMOD0 0x1614
#define REG_SW_EN_DTMB_ADC2DEMOD0_S 0
#define REG_SW_EN_DTMB_ADC2DEMOD0_E 0
#define REG_SW_EN_DTMB_BCH2DEMOD0 0x1618
#define REG_SW_EN_DTMB_BCH2DEMOD0_S 0
#define REG_SW_EN_DTMB_BCH2DEMOD0_E 0
#define REG_SW_EN_DTMB_BCH2DEMOD1 0x161c
#define REG_SW_EN_DTMB_BCH2DEMOD1_S 0
#define REG_SW_EN_DTMB_BCH2DEMOD1_E 0
#define REG_SW_EN_DTMB_EQ0P25X2DEMOD0 0x1620
#define REG_SW_EN_DTMB_EQ0P25X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ0P25X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ0P5X2DEMOD0 0x1624
#define REG_SW_EN_DTMB_EQ0P5X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ0P5X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ1X2DEMOD0 0x1628
#define REG_SW_EN_DTMB_EQ1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0 0x162c
#define REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0 0x1630
#define REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0 0x1634
#define REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X2DEMOD0 0x1638
#define REG_SW_EN_DTMB_EQ2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0 0x163c
#define REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0 0x1640
#define REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0 0x1644
#define REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0 0x1648
#define REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X2DEMOD0 0x164c
#define REG_SW_EN_DTMB_INNER12X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0 0x1650
#define REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER1X2DEMOD0 0x1654
#define REG_SW_EN_DTMB_INNER1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0 0x1658
#define REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER24X2DEMOD0 0x165c
#define REG_SW_EN_DTMB_INNER24X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER24X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0 0x1660
#define REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0 0x1664
#define REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER2X2DEMOD0 0x1668
#define REG_SW_EN_DTMB_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0 0x166c
#define REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0 0x1670
#define REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER4X2DEMOD0 0x1674
#define REG_SW_EN_DTMB_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER6X2DEMOD0 0x1678
#define REG_SW_EN_DTMB_INNER6X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER6X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0 0x167c
#define REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER8X2DEMOD0 0x1680
#define REG_SW_EN_DTMB_INNER8X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER8X2DEMOD0_E 0
#define REG_SW_EN_DTMB_LDPC2DEMOD0 0x1684
#define REG_SW_EN_DTMB_LDPC2DEMOD0_S 0
#define REG_SW_EN_DTMB_LDPC2DEMOD0_E 0
#define REG_SW_EN_DTMB_LDPC2X2DEMOD0 0x1688
#define REG_SW_EN_DTMB_LDPC2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_LDPC2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD0 0x168c
#define REG_SW_EN_DTMB_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD1 0x1690
#define REG_SW_EN_DTMB_OUTER1X2DEMOD1_S 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD1_E 0
#define REG_SW_EN_DTMB_OUTER2X2DEMOD0 0x1694
#define REG_SW_EN_DTMB_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_OUTER8X2DEMOD0 0x1698
#define REG_SW_EN_DTMB_OUTER8X2DEMOD0_S 0
#define REG_SW_EN_DTMB_OUTER8X2DEMOD0_E 0
#define REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0 0x169c
#define REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0_S 0
#define REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER1X2DEMOD0 0x16a0
#define REG_SW_EN_DVBS_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0 0x16a4
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0 0x16a8
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0 0x16ac
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X2DEMOD0 0x16b0
#define REG_SW_EN_DVBS_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBS2_BCH2DEMOD0 0x16b4
#define REG_SW_EN_DVBS2_BCH2DEMOD0_S 0
#define REG_SW_EN_DVBS2_BCH2DEMOD0_E 0
#define REG_SW_EN_DVBS2_DEMAPPER2DEMOD1 0x16b8
#define REG_SW_EN_DVBS2_DEMAPPER2DEMOD1_S 0
#define REG_SW_EN_DVBS2_DEMAPPER2DEMOD1_E 0
#define REG_SW_EN_DVBS2_DISEQC2DEMOD0 0x16bc
#define REG_SW_EN_DVBS2_DISEQC2DEMOD0_S 0
#define REG_SW_EN_DVBS2_DISEQC2DEMOD0_E 0
#define REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1 0x16c0
#define REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1_S 0
#define REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1_E 0
#define REG_SW_EN_DVBS2_INNER2DEMOD0 0x16c4
#define REG_SW_EN_DVBS2_INNER2DEMOD0_S 0
#define REG_SW_EN_DVBS2_INNER2DEMOD0_E 0
#define REG_SW_EN_DVBS2_OPPRO2DEMOD0 0x16c8
#define REG_SW_EN_DVBS2_OPPRO2DEMOD0_S 0
#define REG_SW_EN_DVBS2_OPPRO2DEMOD0_E 0
#define REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1 0x16cc
#define REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1_S 0
#define REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1_E 0
#define REG_SW_EN_DVBT_INNER1X2DEMOD0 0x16d0
#define REG_SW_EN_DVBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0 0x16d4
#define REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0_E 0
#define REG_SW_EN_DVBT_INNER2X2DEMOD0 0x16d8
#define REG_SW_EN_DVBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DVBT_INNER4X2DEMOD0 0x16dc
#define REG_SW_EN_DVBT_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DVBT_OUTER1X2DEMOD0 0x16e0
#define REG_SW_EN_DVBT_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_DVBT_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_DVBT_OUTER2X2DEMOD0 0x16e4
#define REG_SW_EN_DVBT_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBT_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_DEMAPPER2DEMOD1 0x16e8
#define REG_SW_EN_DVBT2_DEMAPPER2DEMOD1_S 0
#define REG_SW_EN_DVBT2_DEMAPPER2DEMOD1_E 0
#define REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1 0x16ec
#define REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1_S 0
#define REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1_E 0
#define REG_SW_EN_DVBT2_INNER1X2DEMOD0 0x16f0
#define REG_SW_EN_DVBT2_INNER1X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER1X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0 0x16f4
#define REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER2X2DEMOD0 0x16f8
#define REG_SW_EN_DVBT2_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0 0x16fc
#define REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0 0x1700
#define REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER4X2DEMOD0 0x1704
#define REG_SW_EN_DVBT2_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1 0x1708
#define REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1_S 0
#define REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1_E 0
#define REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1 0x170c
#define REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1_S 0
#define REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1_E 0
#define REG_SW_EN_DVBT2_S2_BCH2DEMOD1 0x1710
#define REG_SW_EN_DVBT2_S2_BCH2DEMOD1_S 0
#define REG_SW_EN_DVBT2_S2_BCH2DEMOD1_E 0
#define REG_SW_EN_DVBTC_ADC_I2DMD_ANA 0x1718
#define REG_SW_EN_DVBTC_ADC_I2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_I2DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC_Q2DMD_ANA 0x1720
#define REG_SW_EN_DVBTC_ADC_Q2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_Q2DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC2DEMOD0 0x1724
#define REG_SW_EN_DVBTC_ADC2DEMOD0_S 0
#define REG_SW_EN_DVBTC_ADC2DEMOD0_E 0
#define REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0 0x1728
#define REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0_S 0
#define REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0_E 0
#define REG_SW_EN_DVBTC_OUTER2X2DEMOD0 0x172c
#define REG_SW_EN_DVBTC_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBTC_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBTC_RS2DEMOD0 0x1730
#define REG_SW_EN_DVBTC_RS2DEMOD0_S 0
#define REG_SW_EN_DVBTC_RS2DEMOD0_E 0
#define REG_SW_EN_DVBTC_SRAM12DEMOD0 0x1734
#define REG_SW_EN_DVBTC_SRAM12DEMOD0_S 0
#define REG_SW_EN_DVBTC_SRAM12DEMOD0_E 0
#define REG_SW_EN_DVBTC_SRAM32DEMOD0 0x1738
#define REG_SW_EN_DVBTC_SRAM32DEMOD0_S 0
#define REG_SW_EN_DVBTC_SRAM32DEMOD0_E 0
#define REG_SW_EN_DVBTC_SRAM42DEMOD0 0x173c
#define REG_SW_EN_DVBTC_SRAM42DEMOD0_S 0
#define REG_SW_EN_DVBTC_SRAM42DEMOD0_E 0
#define REG_SW_EN_DVBTC_TS2DEMOD0 0x1740
#define REG_SW_EN_DVBTC_TS2DEMOD0_S 0
#define REG_SW_EN_DVBTC_TS2DEMOD0_E 0
#define REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0 0x1744
#define REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0 0x1748
#define REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0 0x174c
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0 0x1750
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0 0x1754
#define REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0 0x1758
#define REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0 0x175c
#define REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0 0x1760
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0 0x1764
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0 0x1768
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0 0x176c
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0 0x1770
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0 0x1774
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0 0x1778
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0 0x177c
#define REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0 0x1780
#define REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER1X2DEMOD0 0x1784
#define REG_SW_EN_ISDBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0 0x1788
#define REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER2X2DEMOD0 0x178c
#define REG_SW_EN_ISDBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0 0x1790
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0 0x1794
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER4X2DEMOD0 0x1798
#define REG_SW_EN_ISDBT_INNER4X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER4X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER_RS2DEMOD0 0x179c
#define REG_SW_EN_ISDBT_OUTER_RS2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER_RS2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER12X2DEMOD0 0x17a0
#define REG_SW_EN_ISDBT_OUTER12X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER12X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0 0x17a4
#define REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER1X2DEMOD0 0x17a8
#define REG_SW_EN_ISDBT_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER4X2DEMOD0 0x17ac
#define REG_SW_EN_ISDBT_OUTER4X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER4X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0 0x17b0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0 0x17b4
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0 0x17b8
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0 0x17bc
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X2DEMOD0 0x17c0
#define REG_SW_EN_ISDBT_OUTER6X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X2DEMOD0_E 0
#define REG_SW_EN_LDPC1X2DEMOD1 0x17c4
#define REG_SW_EN_LDPC1X2DEMOD1_S 0
#define REG_SW_EN_LDPC1X2DEMOD1_E 0
#define REG_SW_EN_LDPC2X2DEMOD1 0x17c8
#define REG_SW_EN_LDPC2X2DEMOD1_S 0
#define REG_SW_EN_LDPC2X2DEMOD1_E 0
#define REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1 0x17e0
#define REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1_E 0
#define REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1 0x17e4
#define REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1_E 0
#define REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1 0x17e8
#define REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1_E 0
#define REG_SW_EN_SRAM_SHARE_00_02DEMOD0 0x17ec
#define REG_SW_EN_SRAM_SHARE_00_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_00_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_00_12DEMOD0 0x17f0
#define REG_SW_EN_SRAM_SHARE_00_12DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_00_12DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_01_02DEMOD0 0x17f4
#define REG_SW_EN_SRAM_SHARE_01_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_01_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_02_02DEMOD0 0x17f8
#define REG_SW_EN_SRAM_SHARE_02_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_02_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_03_02DEMOD0 0x17fc
#define REG_SW_EN_SRAM_SHARE_03_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_03_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_03_12DEMOD0 0x1800
#define REG_SW_EN_SRAM_SHARE_03_12DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_03_12DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_04_02DEMOD0 0x1804
#define REG_SW_EN_SRAM_SHARE_04_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_04_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_04_12DEMOD0 0x1808
#define REG_SW_EN_SRAM_SHARE_04_12DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_04_12DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_052DEMOD0 0x180c
#define REG_SW_EN_SRAM_SHARE_052DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_052DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_062DEMOD0 0x1810
#define REG_SW_EN_SRAM_SHARE_062DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_062DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_072DEMOD0 0x1814
#define REG_SW_EN_SRAM_SHARE_072DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_072DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_082DEMOD0 0x1818
#define REG_SW_EN_SRAM_SHARE_082DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_082DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_092DEMOD0 0x181c
#define REG_SW_EN_SRAM_SHARE_092DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_092DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_102DEMOD0 0x1820
#define REG_SW_EN_SRAM_SHARE_102DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_102DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_112DEMOD0 0x1824
#define REG_SW_EN_SRAM_SHARE_112DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_112DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_122DEMOD0 0x1828
#define REG_SW_EN_SRAM_SHARE_122DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_122DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_132DEMOD0 0x182c
#define REG_SW_EN_SRAM_SHARE_132DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_132DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_14_R2DEMOD0 0x1830
#define REG_SW_EN_SRAM_SHARE_14_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_14_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_14_W2DEMOD0 0x1834
#define REG_SW_EN_SRAM_SHARE_14_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_14_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_15_R2DEMOD0 0x1838
#define REG_SW_EN_SRAM_SHARE_15_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_15_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_15_W2DEMOD0 0x183c
#define REG_SW_EN_SRAM_SHARE_15_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_15_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_162DEMOD0 0x1840
#define REG_SW_EN_SRAM_SHARE_162DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_162DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_182DEMOD0 0x1844
#define REG_SW_EN_SRAM_SHARE_182DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_182DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_192DEMOD0 0x1848
#define REG_SW_EN_SRAM_SHARE_192DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_192DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_202DEMOD0 0x184c
#define REG_SW_EN_SRAM_SHARE_202DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_202DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_212DEMOD0 0x1850
#define REG_SW_EN_SRAM_SHARE_212DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_212DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_222DEMOD0 0x1854
#define REG_SW_EN_SRAM_SHARE_222DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_222DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_232DEMOD0 0x1858
#define REG_SW_EN_SRAM_SHARE_232DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_232DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_242DEMOD0 0x185c
#define REG_SW_EN_SRAM_SHARE_242DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_242DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_262DEMOD0 0x1860
#define REG_SW_EN_SRAM_SHARE_262DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_262DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_272DEMOD0 0x1864
#define REG_SW_EN_SRAM_SHARE_272DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_272DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_282DEMOD0 0x1868
#define REG_SW_EN_SRAM_SHARE_282DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_282DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_292DEMOD0 0x186c
#define REG_SW_EN_SRAM_SHARE_292DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_292DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_342DEMOD0 0x1870
#define REG_SW_EN_SRAM_SHARE_342DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_342DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_352DEMOD0 0x1874
#define REG_SW_EN_SRAM_SHARE_352DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_352DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_362DEMOD0 0x1878
#define REG_SW_EN_SRAM_SHARE_362DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_362DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_402DEMOD0 0x187c
#define REG_SW_EN_SRAM_SHARE_402DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_402DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_422DEMOD0 0x1880
#define REG_SW_EN_SRAM_SHARE_422DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_422DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_442DEMOD0 0x1884
#define REG_SW_EN_SRAM_SHARE_442DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_442DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_462DEMOD0 0x1888
#define REG_SW_EN_SRAM_SHARE_462DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_462DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_472DEMOD0 0x188c
#define REG_SW_EN_SRAM_SHARE_472DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_472DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_50_02DEMOD0 0x1890
#define REG_SW_EN_SRAM_SHARE_50_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_50_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_52_02DEMOD0 0x1894
#define REG_SW_EN_SRAM_SHARE_52_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_52_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_53_02DEMOD0 0x1898
#define REG_SW_EN_SRAM_SHARE_53_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_53_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_55_02DEMOD0 0x189c
#define REG_SW_EN_SRAM_SHARE_55_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_55_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_562DEMOD0 0x18a0
#define REG_SW_EN_SRAM_SHARE_562DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_562DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_572DEMOD0 0x18a4
#define REG_SW_EN_SRAM_SHARE_572DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_572DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_582DEMOD0 0x18a8
#define REG_SW_EN_SRAM_SHARE_582DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_582DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_592DEMOD0 0x18ac
#define REG_SW_EN_SRAM_SHARE_592DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_592DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_602DEMOD0 0x18b0
#define REG_SW_EN_SRAM_SHARE_602DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_602DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_612DEMOD0 0x18b4
#define REG_SW_EN_SRAM_SHARE_612DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_612DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_622DEMOD0 0x18b8
#define REG_SW_EN_SRAM_SHARE_622DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_622DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_642DEMOD0 0x18bc
#define REG_SW_EN_SRAM_SHARE_642DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_642DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_662DEMOD0 0x18c0
#define REG_SW_EN_SRAM_SHARE_662DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_662DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_672DEMOD0 0x18c4
#define REG_SW_EN_SRAM_SHARE_672DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_672DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_68_02DEMOD0 0x18c8
#define REG_SW_EN_SRAM_SHARE_68_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_68_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_68_22DEMOD0 0x18cc
#define REG_SW_EN_SRAM_SHARE_68_22DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_68_22DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_69_02DEMOD0 0x18d0
#define REG_SW_EN_SRAM_SHARE_69_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_69_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_702DEMOD0 0x18d4
#define REG_SW_EN_SRAM_SHARE_702DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_702DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_712DEMOD0 0x18d8
#define REG_SW_EN_SRAM_SHARE_712DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_712DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_772DEMOD0 0x18dc
#define REG_SW_EN_SRAM_SHARE_772DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_772DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_792DEMOD0 0x18e0
#define REG_SW_EN_SRAM_SHARE_792DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_792DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_812DEMOD0 0x18e4
#define REG_SW_EN_SRAM_SHARE_812DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_812DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_852DEMOD0 0x18e8
#define REG_SW_EN_SRAM_SHARE_852DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_852DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_872DEMOD0 0x18ec
#define REG_SW_EN_SRAM_SHARE_872DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_872DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_892DEMOD0 0x18f0
#define REG_SW_EN_SRAM_SHARE_892DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_892DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_912DEMOD0 0x18f4
#define REG_SW_EN_SRAM_SHARE_912DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_912DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_922DEMOD0 0x18f8
#define REG_SW_EN_SRAM_SHARE_922DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_922DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_932DEMOD0 0x18fc
#define REG_SW_EN_SRAM_SHARE_932DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_932DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_942DEMOD0 0x1900
#define REG_SW_EN_SRAM_SHARE_942DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_942DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_962DEMOD0 0x1904
#define REG_SW_EN_SRAM_SHARE_962DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_962DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_982DEMOD0 0x1908
#define REG_SW_EN_SRAM_SHARE_982DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_982DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_992DEMOD0 0x190c
#define REG_SW_EN_SRAM_SHARE_992DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_992DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1002DEMOD0 0x1910
#define REG_SW_EN_SRAM_SHARE_1002DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1002DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1032DEMOD0 0x1914
#define REG_SW_EN_SRAM_SHARE_1032DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1032DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1052DEMOD0 0x1918
#define REG_SW_EN_SRAM_SHARE_1052DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1052DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1072DEMOD0 0x191c
#define REG_SW_EN_SRAM_SHARE_1072DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1072DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1092DEMOD0 0x1920
#define REG_SW_EN_SRAM_SHARE_1092DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1092DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1102DEMOD0 0x1924
#define REG_SW_EN_SRAM_SHARE_1102DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1102DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1112DEMOD0 0x1928
#define REG_SW_EN_SRAM_SHARE_1112DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1112DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1122DEMOD0 0x192c
#define REG_SW_EN_SRAM_SHARE_1122DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1122DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1242DEMOD0 0x1930
#define REG_SW_EN_SRAM_SHARE_1242DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1242DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1282DEMOD0 0x1934
#define REG_SW_EN_SRAM_SHARE_1282DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1282DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1292DEMOD0 0x1938
#define REG_SW_EN_SRAM_SHARE_1292DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1292DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1302DEMOD0 0x193c
#define REG_SW_EN_SRAM_SHARE_1302DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1302DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1312DEMOD0 0x1940
#define REG_SW_EN_SRAM_SHARE_1312DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1312DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1322DEMOD0 0x1944
#define REG_SW_EN_SRAM_SHARE_1322DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1322DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_134_R2DEMOD0 0x1948
#define REG_SW_EN_SRAM_SHARE_134_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_134_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_134_W2DEMOD0 0x194c
#define REG_SW_EN_SRAM_SHARE_134_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_134_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_136_R2DEMOD0 0x1950
#define REG_SW_EN_SRAM_SHARE_136_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_136_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_136_W2DEMOD0 0x1954
#define REG_SW_EN_SRAM_SHARE_136_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_136_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_137_R2DEMOD0 0x1958
#define REG_SW_EN_SRAM_SHARE_137_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_137_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_137_W2DEMOD0 0x195c
#define REG_SW_EN_SRAM_SHARE_137_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_137_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_138_R2DEMOD0 0x1960
#define REG_SW_EN_SRAM_SHARE_138_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_138_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_138_W2DEMOD0 0x1964
#define REG_SW_EN_SRAM_SHARE_138_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_138_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_139_R2DEMOD0 0x1968
#define REG_SW_EN_SRAM_SHARE_139_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_139_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_139_W2DEMOD0 0x196c
#define REG_SW_EN_SRAM_SHARE_139_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_139_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_140_R2DEMOD0 0x1970
#define REG_SW_EN_SRAM_SHARE_140_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_140_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_140_W2DEMOD0 0x1974
#define REG_SW_EN_SRAM_SHARE_140_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_140_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_141_R2DEMOD0 0x1978
#define REG_SW_EN_SRAM_SHARE_141_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_141_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_141_W2DEMOD0 0x197c
#define REG_SW_EN_SRAM_SHARE_141_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_141_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_142_R2DEMOD0 0x1980
#define REG_SW_EN_SRAM_SHARE_142_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_142_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_142_W2DEMOD0 0x1984
#define REG_SW_EN_SRAM_SHARE_142_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_142_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_143_R2DEMOD0 0x1988
#define REG_SW_EN_SRAM_SHARE_143_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_143_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_143_W2DEMOD0 0x198c
#define REG_SW_EN_SRAM_SHARE_143_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_143_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_144_R2DEMOD0 0x1990
#define REG_SW_EN_SRAM_SHARE_144_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_144_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_144_W2DEMOD0 0x1994
#define REG_SW_EN_SRAM_SHARE_144_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_144_W2DEMOD0_E 0
#define REG_SW_EN_TDP_JL_INNER1X2DEMOD0 0x1998
#define REG_SW_EN_TDP_JL_INNER1X2DEMOD0_S 0
#define REG_SW_EN_TDP_JL_INNER1X2DEMOD0_E 0
#define REG_SW_EN_TDP_JL_INNER4X2DEMOD0 0x199c
#define REG_SW_EN_TDP_JL_INNER4X2DEMOD0_S 0
#define REG_SW_EN_TDP_JL_INNER4X2DEMOD0_E 0
#define REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0 0x19a0
#define REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0_S 0
#define REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0_E 0
#define REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0 0x19a4
#define REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0_S 0
#define REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0_E 0
#define REG_SW_EN_TR2DEMOD0 0x19a8
#define REG_SW_EN_TR2DEMOD0_S 0
#define REG_SW_EN_TR2DEMOD0_E 0
#define REG_SW_EN_TS_IN2DEMOD0 0x19ac
#define REG_SW_EN_TS_IN2DEMOD0_S 0
#define REG_SW_EN_TS_IN2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_144M2DEMOD0 0x19b0
#define REG_SW_EN_VIFDBB_144M2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_144M2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_43M2DEMOD0 0x19b4
#define REG_SW_EN_VIFDBB_43M2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_43M2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_86M2DEMOD0 0x19b8
#define REG_SW_EN_VIFDBB_86M2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_86M2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_DAC2DEMOD0 0x19bc
#define REG_SW_EN_VIFDBB_DAC2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_DAC2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0 0x19c0
#define REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_VDAC2DEMOD0 0x19c4
#define REG_SW_EN_VIFDBB_VDAC2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_VDAC2DEMOD0_E 0
#define REG_SW_EN_XTAL_12M2DEMOD0 0x19c8
#define REG_SW_EN_XTAL_12M2DEMOD0_S 0
#define REG_SW_EN_XTAL_12M2DEMOD0_E 0
#define REG_SW_EN_XTAL_24M2DEMOD0 0x19cc
#define REG_SW_EN_XTAL_24M2DEMOD0_S 0
#define REG_SW_EN_XTAL_24M2DEMOD0_E 0
#define REG_SW_EN_XTAL_24M2DEMOD1 0x19d0
#define REG_SW_EN_XTAL_24M2DEMOD1_S 0
#define REG_SW_EN_XTAL_24M2DEMOD1_E 0
#define REG_SW_EN_XTAL_12M2DEMOD1 0x19d4
#define REG_SW_EN_XTAL_12M2DEMOD1_S 0
#define REG_SW_EN_XTAL_12M2DEMOD1_E 0
#define REG_SW_EN_VIFDBB_DAC_FROM_TOP2DEMOD0 0x19d8
#define REG_SW_EN_VIFDBB_DAC_FROM_TOP2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_DAC_FROM_TOP2DEMOD0_E 0
#define REG_SW_EN_DVBTC_ADC2X2DEMOD0 0x19dc
#define REG_SW_EN_DVBTC_ADC2X2DEMOD0_S 0
#define REG_SW_EN_DVBTC_ADC2X2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_002DEMOD0 0x19e0
#define REG_SW_EN_SRAM_SHARE_002DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_002DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_29_302DEMOD0 0x19e4
#define REG_SW_EN_SRAM_SHARE_29_302DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_29_302DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_31_32_332DEMOD0 0x19e8
#define REG_SW_EN_SRAM_SHARE_31_32_332DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_31_32_332DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_34_TO_412DEMOD0 0x19ec
#define REG_SW_EN_SRAM_SHARE_34_TO_412DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_34_TO_412DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_42_432DEMOD0 0x19f0
#define REG_SW_EN_SRAM_SHARE_42_432DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_42_432DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_70_02DEMOD0 0x19f4
#define REG_SW_EN_SRAM_SHARE_70_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_70_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_71_02DEMOD0 0x19f8
#define REG_SW_EN_SRAM_SHARE_71_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_71_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_EQ_38_TO_452DEMOD0 0x19fc
#define REG_SW_EN_SRAM_SHARE_EQ_38_TO_452DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_EQ_38_TO_452DEMOD0_E 0
#define REG_SW_EN_AESDMA2DSCRMB 0x1a00
#define REG_SW_EN_AESDMA2DSCRMB_S 0
#define REG_SW_EN_AESDMA2DSCRMB_E 0
#define REG_SW_EN_SRAM_SHARE_EQ_OTHER2DEMOD0 0x1a04
#define REG_SW_EN_SRAM_SHARE_EQ_OTHER2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_EQ_OTHER2DEMOD0_E 0
#define REG_SW_EN_VIF_FRONTEND4X2DEMOD0 0x1a08
#define REG_SW_EN_VIF_FRONTEND4X2DEMOD0_S 0
#define REG_SW_EN_VIF_FRONTEND4X2DEMOD0_E 0
#define REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE 0x1a10
#define REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE_S 0
#define REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE_E 0
#define REG_SW_EN_SRAM_LDPC1X2X_ME2DEMOD1 0x1a1c
#define REG_SW_EN_SRAM_LDPC1X2X_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_LDPC1X2X_ME2DEMOD1_E 0
#define REG_SW_EN_SMART_SYNTH_272PIU 0x1a24
#define REG_SW_EN_SMART_SYNTH_272PIU_S 0
#define REG_SW_EN_SMART_SYNTH_272PIU_E 0
#define REG_SW_EN_SMART_SYNTH_4322PIU 0x1a28
#define REG_SW_EN_SMART_SYNTH_4322PIU_S 0
#define REG_SW_EN_SMART_SYNTH_4322PIU_E 0
#define REG_SW_EN_SMART2_SYNTH_272PIU 0x1a2c
#define REG_SW_EN_SMART2_SYNTH_272PIU_S 0
#define REG_SW_EN_SMART2_SYNTH_272PIU_E 0
#define REG_SW_EN_SMART2_SYNTH_4322PIU 0x1a30
#define REG_SW_EN_SMART2_SYNTH_4322PIU_S 0
#define REG_SW_EN_SMART2_SYNTH_4322PIU_E 0
#define REG_SW_EN_SMART22PIU 0x1a34
#define REG_SW_EN_SMART22PIU_S 0
#define REG_SW_EN_SMART22PIU_E 0
#define REG_SW_EN_SMART2PIU 0x1a38
#define REG_SW_EN_SMART2PIU_S 0
#define REG_SW_EN_SMART2PIU_E 0
#define REG_SW_EN_VIF_SSC_MUX2DEMOD0 0x1a3c
#define REG_SW_EN_VIF_SSC_MUX2DEMOD0_S 0
#define REG_SW_EN_VIF_SSC_MUX2DEMOD0_E 0
#define REG_SW_EN_FIQ0_27M2TSP 0x1a48
#define REG_SW_EN_FIQ0_27M2TSP_S 0
#define REG_SW_EN_FIQ0_27M2TSP_E 0
#define REG_SW_EN_MM0_27M2TSP 0x1a4c
#define REG_SW_EN_MM0_27M2TSP_S 0
#define REG_SW_EN_MM0_27M2TSP_E 0
#define REG_SW_EN_MM1_27M2TSP 0x1a50
#define REG_SW_EN_MM1_27M2TSP_S 0
#define REG_SW_EN_MM1_27M2TSP_E 0
#define REG_SW_EN_PARSER2TSP 0x1a54
#define REG_SW_EN_PARSER2TSP_S 0
#define REG_SW_EN_PARSER2TSP_E 0
#define REG_SW_EN_PARSER2VD_PES_PARSER 0x1a54
#define REG_SW_EN_PARSER2VD_PES_PARSER_S 1
#define REG_SW_EN_PARSER2VD_PES_PARSER_E 1
#define REG_SW_EN_VIVA_PARSER2PARSER 0x1a54
#define REG_SW_EN_VIVA_PARSER2PARSER_S 2
#define REG_SW_EN_VIVA_PARSER2PARSER_E 2
#define REG_SW_EN_PVR1_27M2TSP 0x1a58
#define REG_SW_EN_PVR1_27M2TSP_S 0
#define REG_SW_EN_PVR1_27M2TSP_E 0
#define REG_SW_EN_PVR2_27M2TSP 0x1a5c
#define REG_SW_EN_PVR2_27M2TSP_S 0
#define REG_SW_EN_PVR2_27M2TSP_E 0
#define REG_SW_EN_PVR3_27M2TSP 0x1a60
#define REG_SW_EN_PVR3_27M2TSP_S 0
#define REG_SW_EN_PVR3_27M2TSP_E 0
#define REG_SW_EN_PVR4_27M2TSP 0x1a64
#define REG_SW_EN_PVR4_27M2TSP_S 0
#define REG_SW_EN_PVR4_27M2TSP_E 0
#define REG_SW_EN_STAMP2TSO 0x1a6c
#define REG_SW_EN_STAMP2TSO_S 0
#define REG_SW_EN_STAMP2TSO_E 0
#define REG_SW_EN_STAMP2TSO2 0x1a70
#define REG_SW_EN_STAMP2TSO2_S 0
#define REG_SW_EN_STAMP2TSO2_E 0
#define REG_SW_EN_STAMP2TSP 0x1a74
#define REG_SW_EN_STAMP2TSP_S 0
#define REG_SW_EN_STAMP2TSP_E 0
#define REG_SW_EN_SYN_STC02TS_SAMPLE 0x1a78
#define REG_SW_EN_SYN_STC02TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC02TS_SAMPLE_E 0
#define REG_SW_EN_SYN_STC12TS_SAMPLE 0x1a7c
#define REG_SW_EN_SYN_STC12TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC12TS_SAMPLE_E 0
#define REG_SW_EN_SYN_STC22TS_SAMPLE 0x1a80
#define REG_SW_EN_SYN_STC22TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC22TS_SAMPLE_E 0
#define REG_SW_EN_SYN_STC32TS_SAMPLE 0x1a84
#define REG_SW_EN_SYN_STC32TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC32TS_SAMPLE_E 0
#define REG_SW_EN_SYS_TIME0_27M2TSP 0x1a88
#define REG_SW_EN_SYS_TIME0_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME0_27M2TSP_E 0
#define REG_SW_EN_SYS_TIME1_27M2TSP 0x1a8c
#define REG_SW_EN_SYS_TIME1_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME1_27M2TSP_E 0
#define REG_SW_EN_SYS_TIME2_27M2TSP 0x1a90
#define REG_SW_EN_SYS_TIME2_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME2_27M2TSP_E 0
#define REG_SW_EN_SYS_TIME3_27M2TSP 0x1a94
#define REG_SW_EN_SYS_TIME3_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME3_27M2TSP_E 0
#define REG_SW_EN_TLV0_27M2TSP 0x1a98
#define REG_SW_EN_TLV0_27M2TSP_S 0
#define REG_SW_EN_TLV0_27M2TSP_E 0
#define REG_SW_EN_TLV1_27M2TSP 0x1a9c
#define REG_SW_EN_TLV1_27M2TSP_S 0
#define REG_SW_EN_TLV1_27M2TSP_E 0
#define REG_SW_EN_TLV2_27M2TSP 0x1aa0
#define REG_SW_EN_TLV2_27M2TSP_S 0
#define REG_SW_EN_TLV2_27M2TSP_E 0
#define REG_SW_EN_TS_ALP02TSP 0x1aa8
#define REG_SW_EN_TS_ALP02TSP_S 0
#define REG_SW_EN_TS_ALP02TSP_E 0
#define REG_SW_EN_TS_ALP12TSP 0x1aac
#define REG_SW_EN_TS_ALP12TSP_S 0
#define REG_SW_EN_TS_ALP12TSP_E 0
#define REG_SW_EN_TS_SAMPLE2TS_SAMPLE 0x1ab4
#define REG_SW_EN_TS_SAMPLE2TS_SAMPLE_S 0
#define REG_SW_EN_TS_SAMPLE2TS_SAMPLE_E 0
#define REG_SW_EN_TS0_IN_DFT2TS_SAMPLE 0x1ac0
#define REG_SW_EN_TS0_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS0_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS02TSP 0x1ac4
#define REG_SW_EN_TS02TSP_S 0
#define REG_SW_EN_TS02TSP_E 0
#define REG_SW_EN_TS1_IN_DFT2TS_SAMPLE 0x1ac8
#define REG_SW_EN_TS1_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS1_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS12TSP 0x1acc
#define REG_SW_EN_TS12TSP_S 0
#define REG_SW_EN_TS12TSP_E 0
#define REG_SW_EN_TS2_IN_DFT2TS_SAMPLE 0x1ad0
#define REG_SW_EN_TS2_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS2_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS22TSP 0x1ad4
#define REG_SW_EN_TS22TSP_S 0
#define REG_SW_EN_TS22TSP_E 0
#define REG_SW_EN_TS3_IN_DFT2TS_SAMPLE 0x1ad8
#define REG_SW_EN_TS3_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS3_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS4_IN_DFT2TS_SAMPLE 0x1adc
#define REG_SW_EN_TS4_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS4_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS5_IN_DFT2TS_SAMPLE 0x1ae0
#define REG_SW_EN_TS5_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS5_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TSFI2TSP 0x1ae4
#define REG_SW_EN_TSFI2TSP_S 0
#define REG_SW_EN_TSFI2TSP_E 0
#define REG_SW_EN_TSIF0_27M2TSP 0x1ae8
#define REG_SW_EN_TSIF0_27M2TSP_S 0
#define REG_SW_EN_TSIF0_27M2TSP_E 0
#define REG_SW_EN_TSO_CH1_27M2TSO 0x1aec
#define REG_SW_EN_TSO_CH1_27M2TSO_S 0
#define REG_SW_EN_TSO_CH1_27M2TSO_E 0
#define REG_SW_EN_TSO_CH12TSO 0x1af0
#define REG_SW_EN_TSO_CH12TSO_S 0
#define REG_SW_EN_TSO_CH12TSO_E 0
#define REG_SW_EN_TSO_CH5_27M2TSO 0x1af4
#define REG_SW_EN_TSO_CH5_27M2TSO_S 0
#define REG_SW_EN_TSO_CH5_27M2TSO_E 0
#define REG_SW_EN_TSO_CH52TSO 0x1af8
#define REG_SW_EN_TSO_CH52TSO_S 0
#define REG_SW_EN_TSO_CH52TSO_E 0
#define REG_SW_EN_TSO_CH6_27M2TSO 0x1afc
#define REG_SW_EN_TSO_CH6_27M2TSO_S 0
#define REG_SW_EN_TSO_CH6_27M2TSO_E 0
#define REG_SW_EN_TSO_CH62TSO 0x1b00
#define REG_SW_EN_TSO_CH62TSO_S 0
#define REG_SW_EN_TSO_CH62TSO_E 0
#define REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE 0x1b04
#define REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE_S 0
#define REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE_E 0
#define REG_SW_EN_TSO_OUT2TSO 0x1b08
#define REG_SW_EN_TSO_OUT2TSO_S 0
#define REG_SW_EN_TSO_OUT2TSO_E 0
#define REG_SW_EN_TSO_S2P12TSO 0x1b0c
#define REG_SW_EN_TSO_S2P12TSO_S 0
#define REG_SW_EN_TSO_S2P12TSO_E 0
#define REG_SW_EN_TSO_S2P2TSO 0x1b10
#define REG_SW_EN_TSO_S2P2TSO_S 0
#define REG_SW_EN_TSO_S2P2TSO_E 0
#define REG_SW_EN_TSO_TRACE_IN2TSO 0x1b14
#define REG_SW_EN_TSO_TRACE_IN2TSO_S 0
#define REG_SW_EN_TSO_TRACE_IN2TSO_E 0
#define REG_SW_EN_TSO_TRACE2TSO 0x1b18
#define REG_SW_EN_TSO_TRACE2TSO_S 0
#define REG_SW_EN_TSO_TRACE2TSO_E 0
#define REG_SW_EN_TSO2_CH1_27M2TSO2 0x1b1c
#define REG_SW_EN_TSO2_CH1_27M2TSO2_S 0
#define REG_SW_EN_TSO2_CH1_27M2TSO2_E 0
#define REG_SW_EN_TSO2_CH12TSO2 0x1b20
#define REG_SW_EN_TSO2_CH12TSO2_S 0
#define REG_SW_EN_TSO2_CH12TSO2_E 0
#define REG_SW_EN_TSO2_CH5_27M2TSO2 0x1b24
#define REG_SW_EN_TSO2_CH5_27M2TSO2_S 0
#define REG_SW_EN_TSO2_CH5_27M2TSO2_E 0
#define REG_SW_EN_TSO2_CH52TSO2 0x1b28
#define REG_SW_EN_TSO2_CH52TSO2_S 0
#define REG_SW_EN_TSO2_CH52TSO2_E 0
#define REG_SW_EN_TSO2_CH6_27M2TSO2 0x1b2c
#define REG_SW_EN_TSO2_CH6_27M2TSO2_S 0
#define REG_SW_EN_TSO2_CH6_27M2TSO2_E 0
#define REG_SW_EN_TSO2_CH62TSO2 0x1b30
#define REG_SW_EN_TSO2_CH62TSO2_S 0
#define REG_SW_EN_TSO2_CH62TSO2_E 0
#define REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE 0x1b34
#define REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE_S 0
#define REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE_E 0
#define REG_SW_EN_TSO2_OUT2TSO2 0x1b38
#define REG_SW_EN_TSO2_OUT2TSO2_S 0
#define REG_SW_EN_TSO2_OUT2TSO2_E 0
#define REG_SW_EN_TSO2_S2P12TSO2 0x1b3c
#define REG_SW_EN_TSO2_S2P12TSO2_S 0
#define REG_SW_EN_TSO2_S2P12TSO2_E 0
#define REG_SW_EN_TSO2_S2P2TSO2 0x1b40
#define REG_SW_EN_TSO2_S2P2TSO2_S 0
#define REG_SW_EN_TSO2_S2P2TSO2_E 0
#define REG_SW_EN_TSO2_TRACE_IN2TSO2 0x1b44
#define REG_SW_EN_TSO2_TRACE_IN2TSO2_S 0
#define REG_SW_EN_TSO2_TRACE_IN2TSO2_E 0
#define REG_SW_EN_TSO2_TRACE2TSO2 0x1b48
#define REG_SW_EN_TSO2_TRACE2TSO2_S 0
#define REG_SW_EN_TSO2_TRACE2TSO2_E 0
#define REG_SW_EN_TSP2DSCRMB 0x1b4c
#define REG_SW_EN_TSP2DSCRMB_S 0
#define REG_SW_EN_TSP2DSCRMB_E 0
#define REG_SW_EN_TSP2TSO 0x1b50
#define REG_SW_EN_TSP2TSO_S 0
#define REG_SW_EN_TSP2TSO_E 0
#define REG_SW_EN_TSP2TSO2 0x1b50
#define REG_SW_EN_TSP2TSO2_S 1
#define REG_SW_EN_TSP2TSO2_E 1
#define REG_SW_EN_TSP2TSP 0x1b50
#define REG_SW_EN_TSP2TSP_S 2
#define REG_SW_EN_TSP2TSP_E 2
#define REG_SW_EN_TS_TLV02TSP 0x1b54
#define REG_SW_EN_TS_TLV02TSP_S 0
#define REG_SW_EN_TS_TLV02TSP_E 0
#define REG_SW_EN_TS_TLV12TSP 0x1b58
#define REG_SW_EN_TS_TLV12TSP_S 0
#define REG_SW_EN_TS_TLV12TSP_E 0
#define REG_SW_EN_TS_TLV22TSP 0x1b5c
#define REG_SW_EN_TS_TLV22TSP_S 0
#define REG_SW_EN_TS_TLV22TSP_E 0
#define REG_SW_EN_PATH0_27M2TSP 0x1b60
#define REG_SW_EN_PATH0_27M2TSP_S 0
#define REG_SW_EN_PATH0_27M2TSP_E 0
#define REG_SW_EN_PATH1_27M2TSP 0x1b64
#define REG_SW_EN_PATH1_27M2TSP_S 0
#define REG_SW_EN_PATH1_27M2TSP_E 0
#define REG_SW_EN_PATH2_27M2TSP 0x1b68
#define REG_SW_EN_PATH2_27M2TSP_S 0
#define REG_SW_EN_PATH2_27M2TSP_E 0
#define REG_SW_EN_PATH_FI_27M2TSP 0x1b6c
#define REG_SW_EN_PATH_FI_27M2TSP_S 0
#define REG_SW_EN_PATH_FI_27M2TSP_E 0
#define REG_SW_EN_VIVA_AB_MAC_10CH2AB_MAC_10CH 0x1b78
#define REG_SW_EN_VIVA_AB_MAC_10CH2AB_MAC_10CH_S 0
#define REG_SW_EN_VIVA_AB_MAC_10CH2AB_MAC_10CH_E 0
#define REG_SW_EN_RIU2EARC_DMACRO 0x1b7c
#define REG_SW_EN_RIU2EARC_DMACRO_S 0
#define REG_SW_EN_RIU2EARC_DMACRO_E 0
#define REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS 0x1b80
#define REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS_S 0
#define REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS_E 0
#define REG_SW_EN_AUSDM_3M2AUSDM_DMACRO 0x1b90
#define REG_SW_EN_AUSDM_3M2AUSDM_DMACRO_S 0
#define REG_SW_EN_AUSDM_3M2AUSDM_DMACRO_E 0
#define REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2 0x1b94
#define REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2_S 0
#define REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2_E 0
#define REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER 0x1b98
#define REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER_S 0
#define REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER_E 0
#define REG_SW_EN_EARC_AUDIO2EARC_DMACRO 0x1b9c
#define REG_SW_EN_EARC_AUDIO2EARC_DMACRO_S 0
#define REG_SW_EN_EARC_AUDIO2EARC_DMACRO_E 0
#define REG_SW_EN_VIVA_AB_MAC2AB_MAC 0x1ba0
#define REG_SW_EN_VIVA_AB_MAC2AB_MAC_S 0
#define REG_SW_EN_VIVA_AB_MAC2AB_MAC_E 0
#define REG_SW_EN_VIVA_AB3_MAC2AB3_MAC 0x1ba4
#define REG_SW_EN_VIVA_AB3_MAC2AB3_MAC_S 0
#define REG_SW_EN_VIVA_AB3_MAC2AB3_MAC_E 0
#define REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS 0x1ba8
#define REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS_S 0
#define REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS_E 0
#define REG_SW_EN_VIVA_AU_MCU2AU_MCU 0x1bac
#define REG_SW_EN_VIVA_AU_MCU2AU_MCU_S 0
#define REG_SW_EN_VIVA_AU_MCU2AU_MCU_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS 0x1bb0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN 0x1bb4
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF 0x1bb8
#define REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS 0x1bbc
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN 0x1bc0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF 0x1bc4
#define REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2 0x1bc8
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2_S 0
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2_E 0
#define REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2 0x1bd0
#define REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2_S 0
#define REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2_E 0
#define REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI 0x1bd4
#define REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI_S 0
#define REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI_E 0
#define REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI 0x1bd8
#define REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI_S 0
#define REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI_E 0
#define REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI 0x1bdc
#define REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI_S 0
#define REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI_E 0
#define REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI 0x1be0
#define REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI_S 0
#define REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI_E 0
#define REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI 0x1be4
#define REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI_S 0
#define REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI_E 0
#define REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI 0x1be8
#define REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI_S 0
#define REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI_E 0
#define REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI 0x1bec
#define REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI_S 0
#define REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI_E 0
#define REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI 0x1bf0
#define REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI_S 0
#define REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI_E 0
#define REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI 0x1bf4
#define REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI_S 0
#define REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI_E 0
#define REG_SW_EN_VIVA_CODEC_SH2CODEC_SH 0x1bf8
#define REG_SW_EN_VIVA_CODEC_SH2CODEC_SH_S 0
#define REG_SW_EN_VIVA_CODEC_SH2CODEC_SH_E 0
#define REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS 0x1bfc
#define REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS_S 0
#define REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230 0x1c00
#define REG_SW_EN_VIVA_DSP2DSP_230_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_1 0x1c04
#define REG_SW_EN_VIVA_DSP2DSP_230_1_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_1_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_2 0x1c08
#define REG_SW_EN_VIVA_DSP2DSP_230_2_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_2_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_3 0x1c0c
#define REG_SW_EN_VIVA_DSP2DSP_230_3_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_3_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF 0x1c10
#define REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_TM 0x1c14
#define REG_SW_EN_VIVA_DSP2DSP_230_TM_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_TM_E 0
#define REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF 0x1c18
#define REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS 0x1c1c
#define REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF 0x1c20
#define REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS 0x1c24
#define REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF 0x1c28
#define REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS 0x1c2c
#define REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF 0x1c30
#define REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS 0x1c34
#define REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS 0x1c38
#define REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS 0x1c3c
#define REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS 0x1c40
#define REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS_S 0
#define REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS_E 0
#define REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS 0x1c44
#define REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS_S 0
#define REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS_E 0
#define REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS 0x1c48
#define REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS_S 0
#define REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS_E 0
#define REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF 0x1c4c
#define REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL 0x1c50
#define REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL_S 0
#define REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL_E 0
#define REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS 0x1c54
#define REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS_S 0
#define REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS_E 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF 0x1c58
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF_S 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF_E 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF 0x1c5c
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR 0x1c60
#define REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR_S 0
#define REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR_E 0
#define REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO 0x1c64
#define REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO_S 0
#define REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO_E 0
#define REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO 0x1c68
#define REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO_S 0
#define REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO_E 0
#define REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO 0x1c6c
#define REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO_S 0
#define REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO_E 0
#define REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432 0x1c70
#define REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432_S 0
#define REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432_E 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS 0x1c74
#define REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS 0x1c78
#define REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF 0x1c7c
#define REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP 0x1c80
#define REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP_S 0
#define REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432 0x1c84
#define REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS 0x1c88
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS 0x1c8c
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF 0x1c90
#define REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP 0x1c94
#define REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP_E 0
#define REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS 0x1c98
#define REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS_S 0
#define REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS_E 0
#define REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS 0x1c9c
#define REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS_S 0
#define REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS_E 0
#define REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF 0x1ca0
#define REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2 0x1ca4
#define REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2_S 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2_E 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG 0x1ca8
#define REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG_S 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG_E 0
#define REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF 0x1cac
#define REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF 0x1cb0
#define REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF 0x1cb4
#define REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN 0x1cb8
#define REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF 0x1cbc
#define REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS 0x1cc0
#define REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS_S 0
#define REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS_E 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2 0x1cc4
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2_S 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2_E 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER 0x1cc8
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER_S 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER_E 0
#define REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF 0x1ccc
#define REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF 0x1cd0
#define REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF 0x1cd4
#define REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN 0x1cd8
#define REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF 0x1cdc
#define REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN 0x1ce0
#define REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF 0x1ce4
#define REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216 0x1ce8
#define REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216_S 0
#define REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216_E 0
#define REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL 0x1cec
#define REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL_S 0
#define REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL_E 0
#define REG_SW_EN_VIVA_R2_WB2R2_WB 0x1cf0
#define REG_SW_EN_VIVA_R2_WB2R2_WB_S 0
#define REG_SW_EN_VIVA_R2_WB2R2_WB_E 0
#define REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG 0x1cf4
#define REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG_S 0
#define REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG_E 0
#define REG_SW_EN_VIVA_RIU_R22RIU_R2 0x1cf8
#define REG_SW_EN_VIVA_RIU_R22RIU_R2_S 0
#define REG_SW_EN_VIVA_RIU_R22RIU_R2_E 0
#define REG_SW_EN_VIVA_SH2CH1_SH 0x1cfc
#define REG_SW_EN_VIVA_SH2CH1_SH_S 0
#define REG_SW_EN_VIVA_SH2CH1_SH_E 0
#define REG_SW_EN_VIVA_SH2CH2_SH 0x1d00
#define REG_SW_EN_VIVA_SH2CH2_SH_S 0
#define REG_SW_EN_VIVA_SH2CH2_SH_E 0
#define REG_SW_EN_VIVA_SH2CH3_SH 0x1d04
#define REG_SW_EN_VIVA_SH2CH3_SH_S 0
#define REG_SW_EN_VIVA_SH2CH3_SH_E 0
#define REG_SW_EN_VIVA_SH2CH4_SH 0x1d08
#define REG_SW_EN_VIVA_SH2CH4_SH_S 0
#define REG_SW_EN_VIVA_SH2CH4_SH_E 0
#define REG_SW_EN_VIVA_SH2CH5_SH 0x1d0c
#define REG_SW_EN_VIVA_SH2CH5_SH_S 0
#define REG_SW_EN_VIVA_SH2CH5_SH_E 0
#define REG_SW_EN_VIVA_SH2CH6_SH 0x1d10
#define REG_SW_EN_VIVA_SH2CH6_SH_S 0
#define REG_SW_EN_VIVA_SH2CH6_SH_E 0
#define REG_SW_EN_VIVA_SH2CH7_SH 0x1d14
#define REG_SW_EN_VIVA_SH2CH7_SH_S 0
#define REG_SW_EN_VIVA_SH2CH7_SH_E 0
#define REG_SW_EN_VIVA_SH2CH8_SH 0x1d18
#define REG_SW_EN_VIVA_SH2CH8_SH_S 0
#define REG_SW_EN_VIVA_SH2CH8_SH_E 0
#define REG_SW_EN_VIVA_SH2CH9_SH 0x1d1c
#define REG_SW_EN_VIVA_SH2CH9_SH_S 0
#define REG_SW_EN_VIVA_SH2CH9_SH_E 0
#define REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC 0x1d20
#define REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC_S 0
#define REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC_E 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN 0x1d24
#define REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN_S 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN_E 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B 0x1d28
#define REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B_S 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B_E 0
#define REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC 0x1d2c
#define REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC_S 0
#define REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC_E 0
#define REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH 0x1d30
#define REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH_S 0
#define REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH_E 0
#define REG_SW_EN_VIVA_SIN_GEN2SIN_GEN 0x1d34
#define REG_SW_EN_VIVA_SIN_GEN2SIN_GEN_S 0
#define REG_SW_EN_VIVA_SIN_GEN2SIN_GEN_E 0
#define REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS 0x1d38
#define REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS_S 0
#define REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS_E 0
#define REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG 0x1d3c
#define REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG_S 0
#define REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG_E 0
#define REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF 0x1d40
#define REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS 0x1d44
#define REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS_E 0
#define REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS 0x1d48
#define REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS_E 0
#define REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF 0x1d4c
#define REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS 0x1d50
#define REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS_E 0
#define REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS 0x1d54
#define REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS_E 0
#define REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER 0x1d58
#define REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER_S 0
#define REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER_E 0
#define REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC 0x1d5c
#define REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC_S 0
#define REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC_E 0
#define REG_SW_EN_VIVA_TEST_BUS2TEST_BUS 0x1d60
#define REG_SW_EN_VIVA_TEST_BUS2TEST_BUS_S 0
#define REG_SW_EN_VIVA_TEST_BUS2TEST_BUS_E 0
#define REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU 0x1d64
#define REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU_S 0
#define REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU_E 0
#define REG_SW_EN_VIVA_XTAL_12M2XTAL 0x1d68
#define REG_SW_EN_VIVA_XTAL_12M2XTAL_S 0
#define REG_SW_EN_VIVA_XTAL_12M2XTAL_E 0
#define REG_SW_EN_VIVA_XTAL_24M2XTAL 0x1d6c
#define REG_SW_EN_VIVA_XTAL_24M2XTAL_S 0
#define REG_SW_EN_VIVA_XTAL_24M2XTAL_E 0
#define REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS 0x1d7c
#define REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS_S 0
#define REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS_E 0
#define REG_SW_EN_RV_AUDEC2AUDEC 0x1d80
#define REG_SW_EN_RV_AUDEC2AUDEC_S 0
#define REG_SW_EN_RV_AUDEC2AUDEC_E 0
#define REG_SW_EN_RV_AUDEC2AUDECDFS 0x1d80
#define REG_SW_EN_RV_AUDEC2AUDECDFS_S 1
#define REG_SW_EN_RV_AUDEC2AUDECDFS_E 1
#define REG_SW_EN_RV_AUSND2AUSND 0x1d80
#define REG_SW_EN_RV_AUSND2AUSND_S 2
#define REG_SW_EN_RV_AUSND2AUSND_E 2
#define REG_SW_EN_RV_AUSND2AUSNDDFS 0x1d80
#define REG_SW_EN_RV_AUSND2AUSNDDFS_S 3
#define REG_SW_EN_RV_AUSND2AUSNDDFS_E 3
#define REG_SW_EN_TCK_AUDAP2AUDAP 0x1d88
#define REG_SW_EN_TCK_AUDAP2AUDAP_S 0
#define REG_SW_EN_TCK_AUDAP2AUDAP_E 0
#define REG_SW_EN_TCK_AUDEC2AUDEC 0x1d88
#define REG_SW_EN_TCK_AUDEC2AUDEC_S 1
#define REG_SW_EN_TCK_AUDEC2AUDEC_E 1
#define REG_SW_EN_TCK_AUSND2AUSND 0x1d88
#define REG_SW_EN_TCK_AUSND2AUSND_S 2
#define REG_SW_EN_TCK_AUSND2AUSND_E 2
#define REG_SW_EN_GPD2GPD 0x1d90
#define REG_SW_EN_GPD2GPD_S 0
#define REG_SW_EN_GPD2GPD_E 0
#define REG_SW_EN_ZDEC_LZD2ZDEC 0x1d94
#define REG_SW_EN_ZDEC_LZD2ZDEC_S 0
#define REG_SW_EN_ZDEC_LZD2ZDEC_E 0
#define REG_SW_EN_NJPD2JPD 0x1d98
#define REG_SW_EN_NJPD2JPD_S 0
#define REG_SW_EN_NJPD2JPD_E 0
#define REG_SW_EN_VDEC_BUS2CORE0 0x1da0
#define REG_SW_EN_VDEC_BUS2CORE0_S 0
#define REG_SW_EN_VDEC_BUS2CORE0_E 0
#define REG_SW_EN_VDEC_SYS2CORE0 0x1dac
#define REG_SW_EN_VDEC_SYS2CORE0_S 1
#define REG_SW_EN_VDEC_SYS2CORE0_E 1
#define REG_SW_EN_XTAL_24M2CORE0 0x1db0
#define REG_SW_EN_XTAL_24M2CORE0_S 1
#define REG_SW_EN_XTAL_24M2CORE0_E 1
#define REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI 0x1e00
#define REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI_S 0
#define REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI 0x1e04
#define REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI 0x1e08
#define REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI 0x1e0c
#define REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI 0x1e10
#define REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI 0x1e14
#define REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI 0x1e18
#define REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI 0x1e1c
#define REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI 0x1e20
#define REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI 0x1e24
#define REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI 0x1e28
#define REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI 0x1e2c
#define REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI 0x1e30
#define REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI 0x1e34
#define REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI 0x1e38
#define REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI 0x1e3c
#define REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI 0x1e40
#define REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI_E 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK 0x1e44
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK_S 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK_E 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO 0x1e48
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO_S 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO_E 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK 0x1e4c
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK_S 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK_E 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO 0x1e50
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO_S 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO_E 0
#define REG_SW_EN_VIVA_SH2CH10_SH 0x1e54
#define REG_SW_EN_VIVA_SH2CH10_SH_S 0
#define REG_SW_EN_VIVA_SH2CH10_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M1_SH 0x1e58
#define REG_SW_EN_VIVA_SH2CH_M1_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M1_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M2_SH 0x1e5c
#define REG_SW_EN_VIVA_SH2CH_M2_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M2_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M3_SH 0x1e60
#define REG_SW_EN_VIVA_SH2CH_M3_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M3_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M4_SH 0x1e64
#define REG_SW_EN_VIVA_SH2CH_M4_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M4_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M5_SH 0x1e68
#define REG_SW_EN_VIVA_SH2CH_M5_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M5_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M6_SH 0x1e6c
#define REG_SW_EN_VIVA_SH2CH_M6_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M6_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M7_SH 0x1e70
#define REG_SW_EN_VIVA_SH2CH_M7_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M7_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M8_SH 0x1e74
#define REG_SW_EN_VIVA_SH2CH_M8_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M8_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M9_SH 0x1e78
#define REG_SW_EN_VIVA_SH2CH_M9_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M9_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M10_SH 0x1e7c
#define REG_SW_EN_VIVA_SH2CH_M10_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M10_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M11_SH 0x1e80
#define REG_SW_EN_VIVA_SH2CH_M11_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M11_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M12_SH 0x1e84
#define REG_SW_EN_VIVA_SH2CH_M12_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M12_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M13_SH 0x1e88
#define REG_SW_EN_VIVA_SH2CH_M13_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M13_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M14_SH 0x1e8c
#define REG_SW_EN_VIVA_SH2CH_M14_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M14_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M15_SH 0x1e90
#define REG_SW_EN_VIVA_SH2CH_M15_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M15_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M16_SH 0x1e94
#define REG_SW_EN_VIVA_SH2CH_M16_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M16_SH_E 0
#define REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE 0x1e98
#define REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE_S 0
#define REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE_E 0
#define REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP 0x1e9c
#define REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP_S 0
#define REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP_E 0
#define REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK 0x1e9c
#define REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK_S 1
#define REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK_E 1
#define REG_PD_SYS3PLL 0x1ec0
#define REG_PD_SYS3PLL_S 0
#define REG_PD_SYS3PLL_E 0
#define REG_PD_SYS3PLL_CLK_DIV2P5 0x1ec0
#define REG_PD_SYS3PLL_CLK_DIV2P5_S 4
#define REG_PD_SYS3PLL_CLK_DIV2P5_E 4
#define REG_PD_SYS3PLL_CLK_DIV2 0x1ec0
#define REG_PD_SYS3PLL_CLK_DIV2_S 8
#define REG_PD_SYS3PLL_CLK_DIV2_E 8
#define REG_PD_SYS3PLL_CLK_DIV3 0x1ec0
#define REG_PD_SYS3PLL_CLK_DIV3_S 12
#define REG_PD_SYS3PLL_CLK_DIV3_E 12
#define REG_PD_SYS3PLL_CLK_DIV5 0x1ec4
#define REG_PD_SYS3PLL_CLK_DIV5_S 0
#define REG_PD_SYS3PLL_CLK_DIV5_E 0
#define REG_PD_SYS3PLL_POSTDIV 0x1ec4
#define REG_PD_SYS3PLL_POSTDIV_S 4
#define REG_PD_SYS3PLL_POSTDIV_E 4
#define REG_PD_SYS3PLL_CLK_DIV30 0x1ec4
#define REG_PD_SYS3PLL_CLK_DIV30_S 8
#define REG_PD_SYS3PLL_CLK_DIV30_E 8
#define REG_EN_SYS3PLL_VCO_DIV3 0x1ec8
#define REG_EN_SYS3PLL_VCO_DIV3_S 0
#define REG_EN_SYS3PLL_VCO_DIV3_E 0
#define REG_EN_SYS3PLL_OCC_DIV128 0x1ec8
#define REG_EN_SYS3PLL_OCC_DIV128_S 4
#define REG_EN_SYS3PLL_OCC_DIV128_E 4
#define REG_EN_SYS3PLL_XTAL 0x1ec8
#define REG_EN_SYS3PLL_XTAL_S 8
#define REG_EN_SYS3PLL_XTAL_E 8
#define REG_EN_SYS3PLL_TEST 0x1ec8
#define REG_EN_SYS3PLL_TEST_S 12
#define REG_EN_SYS3PLL_TEST_E 12
#define REG_EN_SYS3PLL_PRDT 0x1ecc
#define REG_EN_SYS3PLL_PRDT_S 0
#define REG_EN_SYS3PLL_PRDT_E 0
#define REG_EN_SYS3PLL_RST 0x1ecc
#define REG_EN_SYS3PLL_RST_S 4
#define REG_EN_SYS3PLL_RST_E 4
#define REG_GC_SYS3PLL_INPUT_DIV 0x1ed0
#define REG_GC_SYS3PLL_INPUT_DIV_S 0
#define REG_GC_SYS3PLL_INPUT_DIV_E 1
#define REG_GC_SYS3PLL_CP_SW 0x1ed4
#define REG_GC_SYS3PLL_CP_SW_S 0
#define REG_GC_SYS3PLL_CP_SW_E 1
#define REG_GC_SYS3PLL_ICTRL 0x1ed4
#define REG_GC_SYS3PLL_ICTRL_S 8
#define REG_GC_SYS3PLL_ICTRL_E 10
#define REG_GC_SYS3PLL_OUTPUT_DIV_FIRST 0x1ed8
#define REG_GC_SYS3PLL_OUTPUT_DIV_FIRST_S 0
#define REG_GC_SYS3PLL_OUTPUT_DIV_FIRST_E 1
#define REG_GC_SYS3PLL_OUTPUT_DIV 0x1ed8
#define REG_GC_SYS3PLL_OUTPUT_DIV_S 8
#define REG_GC_SYS3PLL_OUTPUT_DIV_E 10
#define REG_GC_SYS3PLL_LOOPDIV_FIRST 0x1edc
#define REG_GC_SYS3PLL_LOOPDIV_FIRST_S 0
#define REG_GC_SYS3PLL_LOOPDIV_FIRST_E 1
#define REG_GC_SYS3PLL_LOOPDIV_SECOND 0x1ee0
#define REG_GC_SYS3PLL_LOOPDIV_SECOND_S 0
#define REG_GC_SYS3PLL_LOOPDIV_SECOND_E 7
#define REG_RO_SYS3PLL_LOCK 0x1ee8
#define REG_RO_SYS3PLL_LOCK_S 0
#define REG_RO_SYS3PLL_LOCK_E 0
#define REG_TEST_SYS3PLL 0x1ef8
#define REG_TEST_SYS3PLL_S 0
#define REG_TEST_SYS3PLL_E 15
#define REG_PD_GPUBRDGPLL 0x1f00
#define REG_PD_GPUBRDGPLL_S 0
#define REG_PD_GPUBRDGPLL_E 0
#define REG_PD_GPUBRDGPLL_CLK_DIV2P5 0x1f00
#define REG_PD_GPUBRDGPLL_CLK_DIV2P5_S 4
#define REG_PD_GPUBRDGPLL_CLK_DIV2P5_E 4
#define REG_PD_GPUBRDGPLL_CLK_DIV2 0x1f00
#define REG_PD_GPUBRDGPLL_CLK_DIV2_S 8
#define REG_PD_GPUBRDGPLL_CLK_DIV2_E 8
#define REG_PD_GPUBRDGPLL_CLK_DIV3 0x1f00
#define REG_PD_GPUBRDGPLL_CLK_DIV3_S 12
#define REG_PD_GPUBRDGPLL_CLK_DIV3_E 12
#define REG_PD_GPUBRDGPLL_CLK_DIV5 0x1f04
#define REG_PD_GPUBRDGPLL_CLK_DIV5_S 0
#define REG_PD_GPUBRDGPLL_CLK_DIV5_E 0
#define REG_PD_GPUBRDGPLL_POSTDIV 0x1f04
#define REG_PD_GPUBRDGPLL_POSTDIV_S 4
#define REG_PD_GPUBRDGPLL_POSTDIV_E 4
#define REG_PD_GPUBRDGPLL_CLK_DIV30 0x1f04
#define REG_PD_GPUBRDGPLL_CLK_DIV30_S 8
#define REG_PD_GPUBRDGPLL_CLK_DIV30_E 8
#define REG_EN_GPUBRDGPLL_VCO_DIV3 0x1f08
#define REG_EN_GPUBRDGPLL_VCO_DIV3_S 0
#define REG_EN_GPUBRDGPLL_VCO_DIV3_E 0
#define REG_EN_GPUBRDGPLL_OCC_DIV128 0x1f08
#define REG_EN_GPUBRDGPLL_OCC_DIV128_S 4
#define REG_EN_GPUBRDGPLL_OCC_DIV128_E 4
#define REG_EN_GPUBRDGPLL_XTAL 0x1f08
#define REG_EN_GPUBRDGPLL_XTAL_S 8
#define REG_EN_GPUBRDGPLL_XTAL_E 8
#define REG_EN_GPUBRDGPLL_TEST 0x1f08
#define REG_EN_GPUBRDGPLL_TEST_S 12
#define REG_EN_GPUBRDGPLL_TEST_E 12
#define REG_EN_GPUBRDGPLL_PRDT 0x1f0c
#define REG_EN_GPUBRDGPLL_PRDT_S 0
#define REG_EN_GPUBRDGPLL_PRDT_E 0
#define REG_EN_GPUBRDGPLL_RST 0x1f0c
#define REG_EN_GPUBRDGPLL_RST_S 4
#define REG_EN_GPUBRDGPLL_RST_E 4
#define REG_GC_GPUBRDGPLL_INPUT_DIV 0x1f10
#define REG_GC_GPUBRDGPLL_INPUT_DIV_S 0
#define REG_GC_GPUBRDGPLL_INPUT_DIV_E 1
#define REG_GC_GPUBRDGPLL_CP_SW 0x1f14
#define REG_GC_GPUBRDGPLL_CP_SW_S 0
#define REG_GC_GPUBRDGPLL_CP_SW_E 1
#define REG_GC_GPUBRDGPLL_ICTRL 0x1f14
#define REG_GC_GPUBRDGPLL_ICTRL_S 8
#define REG_GC_GPUBRDGPLL_ICTRL_E 10
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST 0x1f18
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST_S 0
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST_E 1
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV 0x1f18
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_S 8
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_E 10
#define REG_GC_GPUBRDGPLL_LOOPDIV_FIRST 0x1f1c
#define REG_GC_GPUBRDGPLL_LOOPDIV_FIRST_S 0
#define REG_GC_GPUBRDGPLL_LOOPDIV_FIRST_E 1
#define REG_GC_GPUBRDGPLL_LOOPDIV_SECOND 0x1f20
#define REG_GC_GPUBRDGPLL_LOOPDIV_SECOND_S 0
#define REG_GC_GPUBRDGPLL_LOOPDIV_SECOND_E 7
#define REG_RO_GPUBRDGPLL_LOCK 0x1f28
#define REG_RO_GPUBRDGPLL_LOCK_S 0
#define REG_RO_GPUBRDGPLL_LOCK_E 0
#define REG_TEST_GPUBRDGPLL 0x1f38
#define REG_TEST_GPUBRDGPLL_S 0
#define REG_TEST_GPUBRDGPLL_E 15
#define REG_CKG_DVBTM_TS_DIVNUM 0x1f80
#define REG_CKG_DVBTM_TS_DIVNUM_S 0
#define REG_CKG_DVBTM_TS_DIVNUM_E 7
#define REG_CKG_ATSC_DVB_DIV_SEL 0x1f80
#define REG_CKG_ATSC_DVB_DIV_SEL_S 8
#define REG_CKG_ATSC_DVB_DIV_SEL_E 10
#define REG_CKG_ATSC_DVBTC_TS_INV 0x1f80
#define REG_CKG_ATSC_DVBTC_TS_INV_S 11
#define REG_CKG_ATSC_DVBTC_TS_INV_E 11
#define REG_CKG_DVBTM_TS_OUT_MODE 0x1f80
#define REG_CKG_DVBTM_TS_OUT_MODE_S 12
#define REG_CKG_DVBTM_TS_OUT_MODE_E 12
#define REG_CKG_DEMOD_TEST_IN_EN 0x1f80
#define REG_CKG_DEMOD_TEST_IN_EN_S 13
#define REG_CKG_DEMOD_TEST_IN_EN_E 13
#define REG_CKG_TSOUT_PH_TUN_EN 0x1f80
#define REG_CKG_TSOUT_PH_TUN_EN_S 14
#define REG_CKG_TSOUT_PH_TUN_EN_E 14
#define REG_ATSC_DVB_DIV_RESET 0x1f84
#define REG_ATSC_DVB_DIV_RESET_S 0
#define REG_ATSC_DVB_DIV_RESET_E 0
#define REG_CKG_ATSC_TS 0x1f88
#define REG_CKG_ATSC_TS_S 0
#define REG_CKG_ATSC_TS_E 3
#define REG_CKG_DVBTC_TS_TOP 0x1f8c
#define REG_CKG_DVBTC_TS_TOP_S 8
#define REG_CKG_DVBTC_TS_TOP_E 11
#define REG_CKG_TSOUT_PH_TUN_NUM 0x1f90
#define REG_CKG_TSOUT_PH_TUN_NUM_S 8
#define REG_CKG_TSOUT_PH_TUN_NUM_E 12
#define REG_CKG_VIFDBB_DAC_TOP 0x1f94
#define REG_CKG_VIFDBB_DAC_TOP_S 0
#define REG_CKG_VIFDBB_DAC_TOP_E 3
#define REG_CKG_DACA2 0x1f98
#define REG_CKG_DACA2_S 0
#define REG_CKG_DACA2_E 4
#define REG_CKG_DACB2 0x1f98
#define REG_CKG_DACB2_S 8
#define REG_CKG_DACB2_E 11
#define REG_CKG_VD_SEL 0x1fa0
#define REG_CKG_VD_SEL_S 0
#define REG_CKG_VD_SEL_E 0
#define REG_CKG_VD_BUF_SEL 0x1fa0
#define REG_CKG_VD_BUF_SEL_S 4
#define REG_CKG_VD_BUF_SEL_E 4
#define REG_CKGEN00_DUMMY0 0x1ff0
#define REG_CKGEN00_DUMMY0_S 0
#define REG_CKGEN00_DUMMY0_E 15
#define REG_CKGEN00_DUMMY1 0x1ff4
#define REG_CKGEN00_DUMMY1_S 0
#define REG_CKGEN00_DUMMY1_E 15
#define REG_CKGEN00_DUMMY2 0x1ff8
#define REG_CKGEN00_DUMMY2_S 0
#define REG_CKGEN00_DUMMY2_E 15
#define REG_CKGEN00_DUMMY3 0x1ffc
#define REG_CKGEN00_DUMMY3_S 0
#define REG_CKGEN00_DUMMY3_E 15
#endif
