/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5896_E3_CKGEN01_H
#define _DT_BINDINGS_CLK_MT5896_E3_CKGEN01_H

#define REG_CKG_ADC2MIU 0x2000
#define REG_CKG_ADC2MIU_S 0
#define REG_CKG_ADC2MIU_E 3
#define REG_CKG_ADC2MIUSC 0x2008
#define REG_CKG_ADC2MIUSC_S 0
#define REG_CKG_ADC2MIUSC_E 3
#define REG_CKG_ADC2SC 0x2010
#define REG_CKG_ADC2SC_S 0
#define REG_CKG_ADC2SC_E 3
#define REG_CKG_ADC 0x2018
#define REG_CKG_ADC_S 0
#define REG_CKG_ADC_E 2
#define REG_CKG_ADCPLL200 0x2020
#define REG_CKG_ADCPLL200_S 0
#define REG_CKG_ADCPLL200_E 1
#define REG_CKG_ADCPLL400 0x2028
#define REG_CKG_ADCPLL400_S 0
#define REG_CKG_ADCPLL400_E 1
#define REG_CKG_ADCPLLB_MPLL_216M 0x2030
#define REG_CKG_ADCPLLB_MPLL_216M_S 0
#define REG_CKG_ADCPLLB_MPLL_216M_E 1
#define REG_CKG_B_ADC 0x2038
#define REG_CKG_B_ADC_S 0
#define REG_CKG_B_ADC_E 3
#define REG_CKG_B_INT 0x2040
#define REG_CKG_B_INT_S 0
#define REG_CKG_B_INT_E 3
#define REG_CKG_CLK_TSTBUS_DIV 0x2048
#define REG_CKG_CLK_TSTBUS_DIV_S 0
#define REG_CKG_CLK_TSTBUS_DIV_E 1
#define REG_CKG_CLKD_ADC_P 0x2058
#define REG_CKG_CLKD_ADC_P_S 0
#define REG_CKG_CLKD_ADC_P_E 3
#define REG_CKG_CLKD_ATOP 0x2060
#define REG_CKG_CLKD_ATOP_S 0
#define REG_CKG_CLKD_ATOP_E 3
#define REG_CKG_CLKD_ATOP_INTERNAL 0x2068
#define REG_CKG_CLKD_ATOP_INTERNAL_S 0
#define REG_CKG_CLKD_ATOP_INTERNAL_E 3
#define REG_CKG_CLKPLL 0x2070
#define REG_CKG_CLKPLL_S 0
#define REG_CKG_CLKPLL_E 1
#define REG_CKG_CVBS_DAC_A_DIGITAL0 0x2078
#define REG_CKG_CVBS_DAC_A_DIGITAL0_S 0
#define REG_CKG_CVBS_DAC_A_DIGITAL0_E 2
#define REG_CKG_CVBS_DAC_A_DIGITAL0_MUX 0x2080
#define REG_CKG_CVBS_DAC_A_DIGITAL0_MUX_S 0
#define REG_CKG_CVBS_DAC_A_DIGITAL0_MUX_E 2
#define REG_CKG_CVBS_DAC_A_DIGITAL1 0x2088
#define REG_CKG_CVBS_DAC_A_DIGITAL1_S 0
#define REG_CKG_CVBS_DAC_A_DIGITAL1_E 2
#define REG_CKG_DIG_108 0x2090
#define REG_CKG_DIG_108_S 0
#define REG_CKG_DIG_108_E 1
#define REG_CKG_DIG_216 0x2098
#define REG_CKG_DIG_216_S 0
#define REG_CKG_DIG_216_E 1
#define REG_CKG_FBLANK 0x20a0
#define REG_CKG_FBLANK_S 0
#define REG_CKG_FBLANK_E 2
#define REG_CKG_FSC_VD 0x20a8
#define REG_CKG_FSC_VD_S 0
#define REG_CKG_FSC_VD_E 1
#define REG_CKG_FSCX2_FB2ATOP 0x20b0
#define REG_CKG_FSCX2_FB2ATOP_S 0
#define REG_CKG_FSCX2_FB2ATOP_E 2
#define REG_CKG_G_ADC 0x20b8
#define REG_CKG_G_ADC_S 0
#define REG_CKG_G_ADC_E 3
#define REG_CKG_G_INT 0x20c0
#define REG_CKG_G_INT_S 0
#define REG_CKG_G_INT_E 3
#define REG_CKG_ICLAMP_RGB 0x20c8
#define REG_CKG_ICLAMP_RGB_S 0
#define REG_CKG_ICLAMP_RGB_E 3
#define REG_CKG_ISOG 0x20d0
#define REG_CKG_ISOG_S 0
#define REG_CKG_ISOG_E 1
#define REG_CKG_NCO_CLK 0x20e0
#define REG_CKG_NCO_CLK_S 0
#define REG_CKG_NCO_CLK_E 1
#define REG_CKG_R_ADC 0x20f0
#define REG_CKG_R_ADC_S 0
#define REG_CKG_R_ADC_E 3
#define REG_CKG_R_INT 0x20f8
#define REG_CKG_R_INT_S 0
#define REG_CKG_R_INT_E 3
#define REG_CKG_VD_ICLAMP 0x2108
#define REG_CKG_VD_ICLAMP_S 0
#define REG_CKG_VD_ICLAMP_E 1
#define REG_CKG_VD_ADCPLL 0x2110
#define REG_CKG_VD_ADCPLL_S 0
#define REG_CKG_VD_ADCPLL_E 2
#define REG_CKG_VD_NCO_CLK 0x2118
#define REG_CKG_VD_NCO_CLK_S 0
#define REG_CKG_VD_NCO_CLK_E 1
#define REG_CKG_VDPLL400 0x2120
#define REG_CKG_VDPLL400_S 0
#define REG_CKG_VDPLL400_E 1
#define REG_CKG_XTAL12_4INTERRUPT 0x2128
#define REG_CKG_XTAL12_4INTERRUPT_S 0
#define REG_CKG_XTAL12_4INTERRUPT_E 1
#define REG_CKG_XTAL12_4PLUGDET 0x2130
#define REG_CKG_XTAL12_4PLUGDET_S 0
#define REG_CKG_XTAL12_4PLUGDET_E 1
#define REG_CKG_XTAL12 0x2138
#define REG_CKG_XTAL12_S 0
#define REG_CKG_XTAL12_E 1
#define REG_CKG_XTAL24 0x2140
#define REG_CKG_XTAL24_S 0
#define REG_CKG_XTAL24_E 1
#define REG_CKG_Y_ADC 0x2148
#define REG_CKG_Y_ADC_S 0
#define REG_CKG_Y_ADC_E 2
#define REG_CKG_Y_INT 0x2150
#define REG_CKG_Y_INT_S 0
#define REG_CKG_Y_INT_E 2
#define REG_CKG_YUV_ADC 0x2158
#define REG_CKG_YUV_ADC_S 0
#define REG_CKG_YUV_ADC_E 2
#define REG_CKG_ADCPLB_MPLL_MHEG5 0x2160
#define REG_CKG_ADCPLB_MPLL_MHEG5_S 8
#define REG_CKG_ADCPLB_MPLL_MHEG5_E 9
#define REG_CKG_FRC_FCLK 0x21e8
#define REG_CKG_FRC_FCLK_S 0
#define REG_CKG_FRC_FCLK_E 3
#define REG_CKG_FRC_FCLK_FRCMI 0x21e8
#define REG_CKG_FRC_FCLK_FRCMI_S 4
#define REG_CKG_FRC_FCLK_FRCMI_E 6
#define REG_CKG_FRC_FCLK_FRCIOPMRV55 0x21e8
#define REG_CKG_FRC_FCLK_FRCIOPMRV55_S 8
#define REG_CKG_FRC_FCLK_FRCIOPMRV55_E 9
#define REG_CKG_FRC_FCLK_FRCMEHALO 0x21e8
#define REG_CKG_FRC_FCLK_FRCMEHALO_S 10
#define REG_CKG_FRC_FCLK_FRCMEHALO_E 11
#define REG_CKG_DAP 0x21ec
#define REG_CKG_DAP_S 0
#define REG_CKG_DAP_E 3
#define REG_CKG_FRC_FCLK_2X 0x21f0
#define REG_CKG_FRC_FCLK_2X_S 0
#define REG_CKG_FRC_FCLK_2X_E 3
#define REG_CKG_FRC_FCLK_2X_FRCIOPMRV55 0x21f0
#define REG_CKG_FRC_FCLK_2X_FRCIOPMRV55_S 8
#define REG_CKG_FRC_FCLK_2X_FRCIOPMRV55_E 10
#define REG_CKG_FRC_FCLK_2X_FRCMEHALO 0x21f4
#define REG_CKG_FRC_FCLK_2X_FRCMEHALO_S 0
#define REG_CKG_FRC_FCLK_2X_FRCMEHALO_E 2
#define REG_CKG_FRC_FCLK_2XPLUS 0x21f8
#define REG_CKG_FRC_FCLK_2XPLUS_S 0
#define REG_CKG_FRC_FCLK_2XPLUS_E 3
#define REG_CKG_FRC_FCLK_2XPLUS_FRCIOPMRV55 0x21f8
#define REG_CKG_FRC_FCLK_2XPLUS_FRCIOPMRV55_S 8
#define REG_CKG_FRC_FCLK_2XPLUS_FRCIOPMRV55_E 9
#define REG_CKG_FRC_FCLK_2XPLUS_SCMW 0x21f8
#define REG_CKG_FRC_FCLK_2XPLUS_SCMW_S 12
#define REG_CKG_FRC_FCLK_2XPLUS_SCMW_E 13
#define REG_CKG_FRC_FCLK_2XPLUS_SCIP 0x21f8
#define REG_CKG_FRC_FCLK_2XPLUS_SCIP_S 14
#define REG_CKG_FRC_FCLK_2XPLUS_SCIP_E 15
#define REG_CKG_RV55FRC_RV55FRC 0x2200
#define REG_CKG_RV55FRC_RV55FRC_S 0
#define REG_CKG_RV55FRC_RV55FRC_E 4
#define REG_CKG_RV55FRC 0x2208
#define REG_CKG_RV55FRC_S 0
#define REG_CKG_RV55FRC_E 2
#define REG_CKG_RV55FRC_FRCIOPMRV55 0x2208
#define REG_CKG_RV55FRC_FRCIOPMRV55_S 8
#define REG_CKG_RV55FRC_FRCIOPMRV55_E 9
#define REG_CKG_RV55FRC_JTAG_TCK_FRCIOPMRV55 0x2210
#define REG_CKG_RV55FRC_JTAG_TCK_FRCIOPMRV55_S 0
#define REG_CKG_RV55FRC_JTAG_TCK_FRCIOPMRV55_E 1
#define REG_CKG_RV55FRC_JTAG_TCK_RV55FRC 0x2210
#define REG_CKG_RV55FRC_JTAG_TCK_RV55FRC_S 8
#define REG_CKG_RV55FRC_JTAG_TCK_RV55FRC_E 9
#define REG_CKG_RV55PQU_RV55PQU 0x2218
#define REG_CKG_RV55PQU_RV55PQU_S 0
#define REG_CKG_RV55PQU_RV55PQU_E 4
#define REG_CKG_RV55PQU 0x2220
#define REG_CKG_RV55PQU_S 0
#define REG_CKG_RV55PQU_E 2
#define REG_CKG_RV55PQU_FRCIOPMRV55 0x2220
#define REG_CKG_RV55PQU_FRCIOPMRV55_S 8
#define REG_CKG_RV55PQU_FRCIOPMRV55_E 9
#define REG_CKG_RV55PQU_JTAG_TCK_FRCIOPMRV55 0x2228
#define REG_CKG_RV55PQU_JTAG_TCK_FRCIOPMRV55_S 0
#define REG_CKG_RV55PQU_JTAG_TCK_FRCIOPMRV55_E 1
#define REG_CKG_RV55PQU_JTAG_TCK_RV55PQU 0x2228
#define REG_CKG_RV55PQU_JTAG_TCK_RV55PQU_S 8
#define REG_CKG_RV55PQU_JTAG_TCK_RV55PQU_E 9
#define REG_CKG_XCSRSPLL_SYN 0x2230
#define REG_CKG_XCSRSPLL_SYN_S 0
#define REG_CKG_XCSRSPLL_SYN_E 3
#define REG_CKG_DAP_FRCIOPMRV55 0x2238
#define REG_CKG_DAP_FRCIOPMRV55_S 0
#define REG_CKG_DAP_FRCIOPMRV55_E 1
#define REG_CKG_DAP_RV55FRC 0x2238
#define REG_CKG_DAP_RV55FRC_S 8
#define REG_CKG_DAP_RV55FRC_E 9
#define REG_CKG_DAP_RV55PQU 0x2238
#define REG_CKG_DAP_RV55PQU_S 10
#define REG_CKG_DAP_RV55PQU_E 11
#define REG_CKG_RV55DAP_JTAG_TCK_FRCIOPMRV55 0x2240
#define REG_CKG_RV55DAP_JTAG_TCK_FRCIOPMRV55_S 0
#define REG_CKG_RV55DAP_JTAG_TCK_FRCIOPMRV55_E 1
#define REG_CKG_XTAL_24M_FRCMI 0x2250
#define REG_CKG_XTAL_24M_FRCMI_S 0
#define REG_CKG_XTAL_24M_FRCMI_E 1
#define REG_CKG_XTAL_12M_FRCIOPMRV55 0x2258
#define REG_CKG_XTAL_12M_FRCIOPMRV55_S 0
#define REG_CKG_XTAL_12M_FRCIOPMRV55_E 1
#define REG_CKG_XTAL_24M_FRCIOPMRV55 0x2260
#define REG_CKG_XTAL_24M_FRCIOPMRV55_S 0
#define REG_CKG_XTAL_24M_FRCIOPMRV55_E 1
#define REG_CKG_XTAL_24M_FRCMEHALO 0x2268
#define REG_CKG_XTAL_24M_FRCMEHALO_S 0
#define REG_CKG_XTAL_24M_FRCMEHALO_E 1
#define REG_CKG_XTAL_12M_RV55FRC 0x2270
#define REG_CKG_XTAL_12M_RV55FRC_S 0
#define REG_CKG_XTAL_12M_RV55FRC_E 1
#define REG_CKG_XTAL_24M_RV55FRC 0x2278
#define REG_CKG_XTAL_24M_RV55FRC_S 0
#define REG_CKG_XTAL_24M_RV55FRC_E 1
#define REG_CKG_XTAL_12M_RV55PQU 0x2280
#define REG_CKG_XTAL_12M_RV55PQU_S 0
#define REG_CKG_XTAL_12M_RV55PQU_E 1
#define REG_CKG_XTAL_24M_RV55PQU 0x2288
#define REG_CKG_XTAL_24M_RV55PQU_S 0
#define REG_CKG_XTAL_24M_RV55PQU_E 1
#define REG_CKG_GE 0x22a0
#define REG_CKG_GE_S 0
#define REG_CKG_GE_E 4
#define REG_CKG_HDMI_R2 0x22b0
#define REG_CKG_HDMI_R2_S 0
#define REG_CKG_HDMI_R2_E 3
#define REG_CKG_HDMIRX_TIMESTAMP 0x22b8
#define REG_CKG_HDMIRX_TIMESTAMP_S 0
#define REG_CKG_HDMIRX_TIMESTAMP_E 1
#define REG_CKG_128FS_FB_S0 0x22c0
#define REG_CKG_128FS_FB_S0_S 0
#define REG_CKG_128FS_FB_S0_E 3
#define REG_CKG_128FS_FB_S1 0x22c8
#define REG_CKG_128FS_FB_S1_S 0
#define REG_CKG_128FS_FB_S1_E 3
#define REG_CKG_128FS_S0 0x22d0
#define REG_CKG_128FS_S0_S 0
#define REG_CKG_128FS_S0_E 3
#define REG_CKG_128FS_S1 0x22d8
#define REG_CKG_128FS_S1_S 0
#define REG_CKG_128FS_S1_E 3
#define REG_CKG_216 0x22e0
#define REG_CKG_216_S 0
#define REG_CKG_216_E 3
#define REG_CKG_256FS_S0 0x22e8
#define REG_CKG_256FS_S0_S 0
#define REG_CKG_256FS_S0_E 2
#define REG_CKG_256FS_S1 0x22f0
#define REG_CKG_256FS_S1_S 0
#define REG_CKG_256FS_S1_E 2
#define REG_CKG_432 0x22f8
#define REG_CKG_432_S 0
#define REG_CKG_432_E 2
#define REG_CKG_864 0x2300
#define REG_CKG_864_S 0
#define REG_CKG_864_E 2
#define REG_CKG_CLK_DET_INNER_MISC_0 0x2308
#define REG_CKG_CLK_DET_INNER_MISC_0_S 0
#define REG_CKG_CLK_DET_INNER_MISC_0_E 4
#define REG_CKG_CLK_DET_INNER_MISC_0_0 0x2310
#define REG_CKG_CLK_DET_INNER_MISC_0_0_S 0
#define REG_CKG_CLK_DET_INNER_MISC_0_0_E 4
#define REG_CKG_CLK_DET_INNER_MISC_1 0x2318
#define REG_CKG_CLK_DET_INNER_MISC_1_S 0
#define REG_CKG_CLK_DET_INNER_MISC_1_E 3
#define REG_CKG_CLK_DET_INNER_MISC_1_0 0x2320
#define REG_CKG_CLK_DET_INNER_MISC_1_0_S 0
#define REG_CKG_CLK_DET_INNER_MISC_1_0_E 4
#define REG_CKG_CTS_SYNTH_S0 0x2328
#define REG_CKG_CTS_SYNTH_S0_S 0
#define REG_CKG_CTS_SYNTH_S0_E 3
#define REG_CKG_CTS_SYNTH_S0_0 0x2330
#define REG_CKG_CTS_SYNTH_S0_0_S 0
#define REG_CKG_CTS_SYNTH_S0_0_E 4
#define REG_CKG_CTS_SYNTH_S1 0x2338
#define REG_CKG_CTS_SYNTH_S1_S 0
#define REG_CKG_CTS_SYNTH_S1_E 3
#define REG_CKG_CTS_SYNTH_S1_0 0x2340
#define REG_CKG_CTS_SYNTH_S1_0_S 0
#define REG_CKG_CTS_SYNTH_S1_0_E 4
#define REG_CKG_DSC_ENGINE 0x2348
#define REG_CKG_DSC_ENGINE_S 0
#define REG_CKG_DSC_ENGINE_E 3
#define REG_CKG_DVI2MIU_RD_S0 0x2350
#define REG_CKG_DVI2MIU_RD_S0_S 0
#define REG_CKG_DVI2MIU_RD_S0_E 3
#define REG_CKG_DVI2MIU_RD_S1 0x2358
#define REG_CKG_DVI2MIU_RD_S1_S 0
#define REG_CKG_DVI2MIU_RD_S1_E 3
#define REG_CKG_DVI2MIU_WR_S0 0x2360
#define REG_CKG_DVI2MIU_WR_S0_S 0
#define REG_CKG_DVI2MIU_WR_S0_E 3
#define REG_CKG_DVI2MIU_WR_S0_0 0x2368
#define REG_CKG_DVI2MIU_WR_S0_0_S 0
#define REG_CKG_DVI2MIU_WR_S0_0_E 4
#define REG_CKG_DVI2MIU_WR_S0_1 0x2370
#define REG_CKG_DVI2MIU_WR_S0_1_S 0
#define REG_CKG_DVI2MIU_WR_S0_1_E 3
#define REG_CKG_DVI2MIU_WR_S1 0x2398
#define REG_CKG_DVI2MIU_WR_S1_S 0
#define REG_CKG_DVI2MIU_WR_S1_E 3
#define REG_CKG_DVI2MIU_WR_S1_0 0x23a0
#define REG_CKG_DVI2MIU_WR_S1_0_S 0
#define REG_CKG_DVI2MIU_WR_S1_0_E 4
#define REG_CKG_DVI2MIU_WR_S1_1 0x23a8
#define REG_CKG_DVI2MIU_WR_S1_1_S 0
#define REG_CKG_DVI2MIU_WR_S1_1_E 3
#define REG_CKG_EARC_AUDIO 0x23d0
#define REG_CKG_EARC_AUDIO_S 0
#define REG_CKG_EARC_AUDIO_E 2
#define REG_CKG_EARC_CM 0x23d8
#define REG_CKG_EARC_CM_S 0
#define REG_CKG_EARC_CM_E 2
#define REG_CKG_EARC_DEBOUNCE 0x23e0
#define REG_CKG_EARC_DEBOUNCE_S 0
#define REG_CKG_EARC_DEBOUNCE_E 1
#define REG_CKG_EARC_DM_PRBS 0x23e8
#define REG_CKG_EARC_DM_PRBS_S 0
#define REG_CKG_EARC_DM_PRBS_E 2
#define REG_CKG_LINK_DSCD 0x23f0
#define REG_CKG_LINK_DSCD_S 0
#define REG_CKG_LINK_DSCD_E 4
#define REG_CKG_P0_CLK_DET_DEC_MISC_0 0x23f8
#define REG_CKG_P0_CLK_DET_DEC_MISC_0_S 0
#define REG_CKG_P0_CLK_DET_DEC_MISC_0_E 3
#define REG_CKG_P0_CLK_DET_DEC_MISC_0_0 0x2400
#define REG_CKG_P0_CLK_DET_DEC_MISC_0_0_S 0
#define REG_CKG_P0_CLK_DET_DEC_MISC_0_0_E 3
#define REG_CKG_P0_CLK_DET_DEC_MISC_1 0x2408
#define REG_CKG_P0_CLK_DET_DEC_MISC_1_S 0
#define REG_CKG_P0_CLK_DET_DEC_MISC_1_E 3
#define REG_CKG_P0_CLK_DET_DEC_MISC_1_0 0x2410
#define REG_CKG_P0_CLK_DET_DEC_MISC_1_0_S 0
#define REG_CKG_P0_CLK_DET_DEC_MISC_1_0_E 3
#define REG_CKG_P0_CLK_DET_DEP_MISC_0 0x2418
#define REG_CKG_P0_CLK_DET_DEP_MISC_0_S 0
#define REG_CKG_P0_CLK_DET_DEP_MISC_0_E 3
#define REG_CKG_P0_CLK_DET_DEP_MISC_0_0 0x2420
#define REG_CKG_P0_CLK_DET_DEP_MISC_0_0_S 0
#define REG_CKG_P0_CLK_DET_DEP_MISC_0_0_E 3
#define REG_CKG_P0_CLK_DET_DEP_MISC_1 0x2428
#define REG_CKG_P0_CLK_DET_DEP_MISC_1_S 0
#define REG_CKG_P0_CLK_DET_DEP_MISC_1_E 3
#define REG_CKG_P0_CLK_DET_DEP_MISC_1_0 0x2430
#define REG_CKG_P0_CLK_DET_DEP_MISC_1_0_S 0
#define REG_CKG_P0_CLK_DET_DEP_MISC_1_0_E 3
#define REG_CKG_P0_LINK 0x2438
#define REG_CKG_P0_LINK_S 0
#define REG_CKG_P0_LINK_E 3
#define REG_CKG_P0_PIX_1P 0x2440
#define REG_CKG_P0_PIX_1P_S 0
#define REG_CKG_P0_PIX_1P_E 3
#define REG_CKG_P0_PIX_8P 0x2448
#define REG_CKG_P0_PIX_8P_S 0
#define REG_CKG_P0_PIX_8P_E 4
#define REG_CKG_P0_PIX_DC_MUX 0x2450
#define REG_CKG_P0_PIX_DC_MUX_S 0
#define REG_CKG_P0_PIX_DC_MUX_E 4
#define REG_CKG_P0_PIX_RCV_MUX 0x2458
#define REG_CKG_P0_PIX_RCV_MUX_S 0
#define REG_CKG_P0_PIX_RCV_MUX_E 4
#define REG_CKG_P0_PIX_REP_1P 0x2460
#define REG_CKG_P0_PIX_REP_1P_S 0
#define REG_CKG_P0_PIX_REP_1P_E 3
#define REG_CKG_P0_PIX_TMDSPLL 0x2468
#define REG_CKG_P0_PIX_TMDSPLL_S 0
#define REG_CKG_P0_PIX_TMDSPLL_E 3
#define REG_CKG_P0_PIX_XC_MUX 0x2478
#define REG_CKG_P0_PIX_XC_MUX_S 0
#define REG_CKG_P0_PIX_XC_MUX_E 3
#define REG_CKG_P0_TIMING_DET_DEC 0x2480
#define REG_CKG_P0_TIMING_DET_DEC_S 0
#define REG_CKG_P0_TIMING_DET_DEC_E 4
#define REG_CKG_P0_TIMING_DET_DEP 0x2488
#define REG_CKG_P0_TIMING_DET_DEP_S 0
#define REG_CKG_P0_TIMING_DET_DEP_E 4
#define REG_CKG_P0_TIMING_DET_DTOP 0x2490
#define REG_CKG_P0_TIMING_DET_DTOP_S 0
#define REG_CKG_P0_TIMING_DET_DTOP_E 3
#define REG_CKG_P0_TMDS_FRL_8P 0x2498
#define REG_CKG_P0_TMDS_FRL_8P_S 0
#define REG_CKG_P0_TMDS_FRL_8P_E 3
#define REG_CKG_P0_TMDS_HDCP_1P 0x24a0
#define REG_CKG_P0_TMDS_HDCP_1P_S 0
#define REG_CKG_P0_TMDS_HDCP_1P_E 3
#define REG_CKG_P0_TMDS_HDCP_4P 0x24a8
#define REG_CKG_P0_TMDS_HDCP_4P_S 0
#define REG_CKG_P0_TMDS_HDCP_4P_E 3
#define REG_CKG_P0_TMDS_HDCP_8P 0x24b0
#define REG_CKG_P0_TMDS_HDCP_8P_S 0
#define REG_CKG_P0_TMDS_HDCP_8P_E 3
#define REG_CKG_P0_TMDS_HDCP_MUX 0x24b8
#define REG_CKG_P0_TMDS_HDCP_MUX_S 0
#define REG_CKG_P0_TMDS_HDCP_MUX_E 3
#define REG_CKG_P0_TMDS_HDMI_1P 0x24c0
#define REG_CKG_P0_TMDS_HDMI_1P_S 0
#define REG_CKG_P0_TMDS_HDMI_1P_E 3
#define REG_CKG_P0_TMDS_HDMI_8P 0x24c8
#define REG_CKG_P0_TMDS_HDMI_8P_S 0
#define REG_CKG_P0_TMDS_HDMI_8P_E 3
#define REG_CKG_P0_TMDS_HDMI_MUX 0x24d0
#define REG_CKG_P0_TMDS_HDMI_MUX_S 0
#define REG_CKG_P0_TMDS_HDMI_MUX_E 3
#define REG_CKG_P1_CLK_DET_DEC_MISC_0 0x24d8
#define REG_CKG_P1_CLK_DET_DEC_MISC_0_S 0
#define REG_CKG_P1_CLK_DET_DEC_MISC_0_E 3
#define REG_CKG_P1_CLK_DET_DEC_MISC_0_0 0x24e0
#define REG_CKG_P1_CLK_DET_DEC_MISC_0_0_S 0
#define REG_CKG_P1_CLK_DET_DEC_MISC_0_0_E 3
#define REG_CKG_P1_CLK_DET_DEC_MISC_1 0x24e8
#define REG_CKG_P1_CLK_DET_DEC_MISC_1_S 0
#define REG_CKG_P1_CLK_DET_DEC_MISC_1_E 3
#define REG_CKG_P1_CLK_DET_DEC_MISC_1_0 0x24f0
#define REG_CKG_P1_CLK_DET_DEC_MISC_1_0_S 0
#define REG_CKG_P1_CLK_DET_DEC_MISC_1_0_E 3
#define REG_CKG_P1_CLK_DET_DEP_MISC_0 0x24f8
#define REG_CKG_P1_CLK_DET_DEP_MISC_0_S 0
#define REG_CKG_P1_CLK_DET_DEP_MISC_0_E 3
#define REG_CKG_P1_CLK_DET_DEP_MISC_0_0 0x2500
#define REG_CKG_P1_CLK_DET_DEP_MISC_0_0_S 0
#define REG_CKG_P1_CLK_DET_DEP_MISC_0_0_E 3
#define REG_CKG_P1_CLK_DET_DEP_MISC_1 0x2508
#define REG_CKG_P1_CLK_DET_DEP_MISC_1_S 0
#define REG_CKG_P1_CLK_DET_DEP_MISC_1_E 3
#define REG_CKG_P1_CLK_DET_DEP_MISC_1_0 0x2510
#define REG_CKG_P1_CLK_DET_DEP_MISC_1_0_S 0
#define REG_CKG_P1_CLK_DET_DEP_MISC_1_0_E 3
#define REG_CKG_P1_LINK 0x2518
#define REG_CKG_P1_LINK_S 0
#define REG_CKG_P1_LINK_E 3
#define REG_CKG_P1_PIX_1P 0x2520
#define REG_CKG_P1_PIX_1P_S 0
#define REG_CKG_P1_PIX_1P_E 3
#define REG_CKG_P1_PIX_8P 0x2528
#define REG_CKG_P1_PIX_8P_S 0
#define REG_CKG_P1_PIX_8P_E 4
#define REG_CKG_P1_PIX_DC_MUX 0x2530
#define REG_CKG_P1_PIX_DC_MUX_S 0
#define REG_CKG_P1_PIX_DC_MUX_E 4
#define REG_CKG_P1_PIX_RCV_MUX 0x2538
#define REG_CKG_P1_PIX_RCV_MUX_S 0
#define REG_CKG_P1_PIX_RCV_MUX_E 4
#define REG_CKG_P1_PIX_REP_1P 0x2540
#define REG_CKG_P1_PIX_REP_1P_S 0
#define REG_CKG_P1_PIX_REP_1P_E 3
#define REG_CKG_P1_PIX_TMDSPLL 0x2548
#define REG_CKG_P1_PIX_TMDSPLL_S 0
#define REG_CKG_P1_PIX_TMDSPLL_E 3
#define REG_CKG_P1_PIX_XC_MUX 0x2558
#define REG_CKG_P1_PIX_XC_MUX_S 0
#define REG_CKG_P1_PIX_XC_MUX_E 3
#define REG_CKG_P1_TIMING_DET_DEC 0x2560
#define REG_CKG_P1_TIMING_DET_DEC_S 0
#define REG_CKG_P1_TIMING_DET_DEC_E 4
#define REG_CKG_P1_TIMING_DET_DEP 0x2568
#define REG_CKG_P1_TIMING_DET_DEP_S 0
#define REG_CKG_P1_TIMING_DET_DEP_E 4
#define REG_CKG_P1_TIMING_DET_DTOP 0x2570
#define REG_CKG_P1_TIMING_DET_DTOP_S 0
#define REG_CKG_P1_TIMING_DET_DTOP_E 3
#define REG_CKG_P1_TMDS_FRL_8P 0x2578
#define REG_CKG_P1_TMDS_FRL_8P_S 0
#define REG_CKG_P1_TMDS_FRL_8P_E 3
#define REG_CKG_P1_TMDS_HDCP_1P 0x2580
#define REG_CKG_P1_TMDS_HDCP_1P_S 0
#define REG_CKG_P1_TMDS_HDCP_1P_E 3
#define REG_CKG_P1_TMDS_HDCP_4P 0x2588
#define REG_CKG_P1_TMDS_HDCP_4P_S 0
#define REG_CKG_P1_TMDS_HDCP_4P_E 3
#define REG_CKG_P1_TMDS_HDCP_8P 0x2590
#define REG_CKG_P1_TMDS_HDCP_8P_S 0
#define REG_CKG_P1_TMDS_HDCP_8P_E 3
#define REG_CKG_P1_TMDS_HDCP_MUX 0x2598
#define REG_CKG_P1_TMDS_HDCP_MUX_S 0
#define REG_CKG_P1_TMDS_HDCP_MUX_E 3
#define REG_CKG_P1_TMDS_HDMI_1P 0x25a0
#define REG_CKG_P1_TMDS_HDMI_1P_S 0
#define REG_CKG_P1_TMDS_HDMI_1P_E 3
#define REG_CKG_P1_TMDS_HDMI_8P 0x25a8
#define REG_CKG_P1_TMDS_HDMI_8P_S 0
#define REG_CKG_P1_TMDS_HDMI_8P_E 3
#define REG_CKG_P1_TMDS_HDMI_MUX 0x25b0
#define REG_CKG_P1_TMDS_HDMI_MUX_S 0
#define REG_CKG_P1_TMDS_HDMI_MUX_E 3
#define REG_CKG_P2_CLK_DET_DEC_MISC_0 0x25b8
#define REG_CKG_P2_CLK_DET_DEC_MISC_0_S 0
#define REG_CKG_P2_CLK_DET_DEC_MISC_0_E 3
#define REG_CKG_P2_CLK_DET_DEC_MISC_0_0 0x25c0
#define REG_CKG_P2_CLK_DET_DEC_MISC_0_0_S 0
#define REG_CKG_P2_CLK_DET_DEC_MISC_0_0_E 3
#define REG_CKG_P2_CLK_DET_DEC_MISC_1 0x25c8
#define REG_CKG_P2_CLK_DET_DEC_MISC_1_S 0
#define REG_CKG_P2_CLK_DET_DEC_MISC_1_E 3
#define REG_CKG_P2_CLK_DET_DEC_MISC_1_0 0x25d0
#define REG_CKG_P2_CLK_DET_DEC_MISC_1_0_S 0
#define REG_CKG_P2_CLK_DET_DEC_MISC_1_0_E 3
#define REG_CKG_P2_CLK_DET_DEP_MISC_0 0x25d8
#define REG_CKG_P2_CLK_DET_DEP_MISC_0_S 0
#define REG_CKG_P2_CLK_DET_DEP_MISC_0_E 3
#define REG_CKG_P2_CLK_DET_DEP_MISC_0_0 0x25e0
#define REG_CKG_P2_CLK_DET_DEP_MISC_0_0_S 0
#define REG_CKG_P2_CLK_DET_DEP_MISC_0_0_E 3
#define REG_CKG_P2_CLK_DET_DEP_MISC_1 0x25e8
#define REG_CKG_P2_CLK_DET_DEP_MISC_1_S 0
#define REG_CKG_P2_CLK_DET_DEP_MISC_1_E 3
#define REG_CKG_P2_CLK_DET_DEP_MISC_1_0 0x25f0
#define REG_CKG_P2_CLK_DET_DEP_MISC_1_0_S 0
#define REG_CKG_P2_CLK_DET_DEP_MISC_1_0_E 3
#define REG_CKG_P2_LINK 0x25f8
#define REG_CKG_P2_LINK_S 0
#define REG_CKG_P2_LINK_E 3
#define REG_CKG_P2_PIX_1P 0x2600
#define REG_CKG_P2_PIX_1P_S 0
#define REG_CKG_P2_PIX_1P_E 3
#define REG_CKG_P2_PIX_8P 0x2608
#define REG_CKG_P2_PIX_8P_S 0
#define REG_CKG_P2_PIX_8P_E 4
#define REG_CKG_P2_PIX_DC_MUX 0x2610
#define REG_CKG_P2_PIX_DC_MUX_S 0
#define REG_CKG_P2_PIX_DC_MUX_E 4
#define REG_CKG_P2_PIX_RCV_MUX 0x2618
#define REG_CKG_P2_PIX_RCV_MUX_S 0
#define REG_CKG_P2_PIX_RCV_MUX_E 4
#define REG_CKG_P2_PIX_REP_1P 0x2620
#define REG_CKG_P2_PIX_REP_1P_S 0
#define REG_CKG_P2_PIX_REP_1P_E 3
#define REG_CKG_P2_PIX_TMDSPLL 0x2628
#define REG_CKG_P2_PIX_TMDSPLL_S 0
#define REG_CKG_P2_PIX_TMDSPLL_E 3
#define REG_CKG_P2_PIX_XC_MUX 0x2638
#define REG_CKG_P2_PIX_XC_MUX_S 0
#define REG_CKG_P2_PIX_XC_MUX_E 3
#define REG_CKG_P2_TIMING_DET_DEC 0x2640
#define REG_CKG_P2_TIMING_DET_DEC_S 0
#define REG_CKG_P2_TIMING_DET_DEC_E 4
#define REG_CKG_P2_TIMING_DET_DEP 0x2648
#define REG_CKG_P2_TIMING_DET_DEP_S 0
#define REG_CKG_P2_TIMING_DET_DEP_E 4
#define REG_CKG_P2_TIMING_DET_DTOP 0x2650
#define REG_CKG_P2_TIMING_DET_DTOP_S 0
#define REG_CKG_P2_TIMING_DET_DTOP_E 3
#define REG_CKG_P2_TMDS_FRL_8P 0x2658
#define REG_CKG_P2_TMDS_FRL_8P_S 0
#define REG_CKG_P2_TMDS_FRL_8P_E 3
#define REG_CKG_P2_TMDS_HDCP_1P 0x2660
#define REG_CKG_P2_TMDS_HDCP_1P_S 0
#define REG_CKG_P2_TMDS_HDCP_1P_E 3
#define REG_CKG_P2_TMDS_HDCP_4P 0x2668
#define REG_CKG_P2_TMDS_HDCP_4P_S 0
#define REG_CKG_P2_TMDS_HDCP_4P_E 3
#define REG_CKG_P2_TMDS_HDCP_8P 0x2670
#define REG_CKG_P2_TMDS_HDCP_8P_S 0
#define REG_CKG_P2_TMDS_HDCP_8P_E 3
#define REG_CKG_P2_TMDS_HDCP_MUX 0x2678
#define REG_CKG_P2_TMDS_HDCP_MUX_S 0
#define REG_CKG_P2_TMDS_HDCP_MUX_E 3
#define REG_CKG_P2_TMDS_HDMI_1P 0x2680
#define REG_CKG_P2_TMDS_HDMI_1P_S 0
#define REG_CKG_P2_TMDS_HDMI_1P_E 3
#define REG_CKG_P2_TMDS_HDMI_8P 0x2688
#define REG_CKG_P2_TMDS_HDMI_8P_S 0
#define REG_CKG_P2_TMDS_HDMI_8P_E 3
#define REG_CKG_P2_TMDS_HDMI_MUX 0x2690
#define REG_CKG_P2_TMDS_HDMI_MUX_S 0
#define REG_CKG_P2_TMDS_HDMI_MUX_E 3
#define REG_CKG_P3_CLK_DET_DEC_MISC_0 0x2698
#define REG_CKG_P3_CLK_DET_DEC_MISC_0_S 0
#define REG_CKG_P3_CLK_DET_DEC_MISC_0_E 3
#define REG_CKG_P3_CLK_DET_DEC_MISC_0_0 0x26a0
#define REG_CKG_P3_CLK_DET_DEC_MISC_0_0_S 0
#define REG_CKG_P3_CLK_DET_DEC_MISC_0_0_E 3
#define REG_CKG_P3_CLK_DET_DEC_MISC_1 0x26a8
#define REG_CKG_P3_CLK_DET_DEC_MISC_1_S 0
#define REG_CKG_P3_CLK_DET_DEC_MISC_1_E 3
#define REG_CKG_P3_CLK_DET_DEC_MISC_1_0 0x26b0
#define REG_CKG_P3_CLK_DET_DEC_MISC_1_0_S 0
#define REG_CKG_P3_CLK_DET_DEC_MISC_1_0_E 3
#define REG_CKG_P3_CLK_DET_DEP_MISC_0 0x26b8
#define REG_CKG_P3_CLK_DET_DEP_MISC_0_S 0
#define REG_CKG_P3_CLK_DET_DEP_MISC_0_E 3
#define REG_CKG_P3_CLK_DET_DEP_MISC_0_0 0x26c0
#define REG_CKG_P3_CLK_DET_DEP_MISC_0_0_S 0
#define REG_CKG_P3_CLK_DET_DEP_MISC_0_0_E 3
#define REG_CKG_P3_CLK_DET_DEP_MISC_1 0x26c8
#define REG_CKG_P3_CLK_DET_DEP_MISC_1_S 0
#define REG_CKG_P3_CLK_DET_DEP_MISC_1_E 3
#define REG_CKG_P3_CLK_DET_DEP_MISC_1_0 0x26d0
#define REG_CKG_P3_CLK_DET_DEP_MISC_1_0_S 0
#define REG_CKG_P3_CLK_DET_DEP_MISC_1_0_E 3
#define REG_CKG_P3_LINK 0x26d8
#define REG_CKG_P3_LINK_S 0
#define REG_CKG_P3_LINK_E 3
#define REG_CKG_P3_PIX_1P 0x26e0
#define REG_CKG_P3_PIX_1P_S 0
#define REG_CKG_P3_PIX_1P_E 3
#define REG_CKG_P3_PIX_8P 0x26e8
#define REG_CKG_P3_PIX_8P_S 0
#define REG_CKG_P3_PIX_8P_E 4
#define REG_CKG_P3_PIX_DC_MUX 0x26f0
#define REG_CKG_P3_PIX_DC_MUX_S 0
#define REG_CKG_P3_PIX_DC_MUX_E 4
#define REG_CKG_P3_PIX_RCV_MUX 0x26f8
#define REG_CKG_P3_PIX_RCV_MUX_S 0
#define REG_CKG_P3_PIX_RCV_MUX_E 4
#define REG_CKG_P3_PIX_REP_1P 0x2700
#define REG_CKG_P3_PIX_REP_1P_S 0
#define REG_CKG_P3_PIX_REP_1P_E 3
#define REG_CKG_P3_PIX_TMDSPLL 0x2708
#define REG_CKG_P3_PIX_TMDSPLL_S 0
#define REG_CKG_P3_PIX_TMDSPLL_E 3
#define REG_CKG_P3_PIX_XC_MUX 0x2718
#define REG_CKG_P3_PIX_XC_MUX_S 0
#define REG_CKG_P3_PIX_XC_MUX_E 3
#define REG_CKG_P3_TIMING_DET_DEC 0x2720
#define REG_CKG_P3_TIMING_DET_DEC_S 0
#define REG_CKG_P3_TIMING_DET_DEC_E 4
#define REG_CKG_P3_TIMING_DET_DEP 0x2728
#define REG_CKG_P3_TIMING_DET_DEP_S 0
#define REG_CKG_P3_TIMING_DET_DEP_E 4
#define REG_CKG_P3_TIMING_DET_DTOP 0x2730
#define REG_CKG_P3_TIMING_DET_DTOP_S 0
#define REG_CKG_P3_TIMING_DET_DTOP_E 3
#define REG_CKG_P3_TMDS_FRL_8P 0x2738
#define REG_CKG_P3_TMDS_FRL_8P_S 0
#define REG_CKG_P3_TMDS_FRL_8P_E 3
#define REG_CKG_P3_TMDS_HDCP_1P 0x2740
#define REG_CKG_P3_TMDS_HDCP_1P_S 0
#define REG_CKG_P3_TMDS_HDCP_1P_E 3
#define REG_CKG_P3_TMDS_HDCP_4P 0x2748
#define REG_CKG_P3_TMDS_HDCP_4P_S 0
#define REG_CKG_P3_TMDS_HDCP_4P_E 3
#define REG_CKG_P3_TMDS_HDCP_8P 0x2750
#define REG_CKG_P3_TMDS_HDCP_8P_S 0
#define REG_CKG_P3_TMDS_HDCP_8P_E 3
#define REG_CKG_P3_TMDS_HDCP_MUX 0x2758
#define REG_CKG_P3_TMDS_HDCP_MUX_S 0
#define REG_CKG_P3_TMDS_HDCP_MUX_E 3
#define REG_CKG_P3_TMDS_HDMI_1P 0x2760
#define REG_CKG_P3_TMDS_HDMI_1P_S 0
#define REG_CKG_P3_TMDS_HDMI_1P_E 3
#define REG_CKG_P3_TMDS_HDMI_8P 0x2768
#define REG_CKG_P3_TMDS_HDMI_8P_S 0
#define REG_CKG_P3_TMDS_HDMI_8P_E 3
#define REG_CKG_P3_TMDS_HDMI_MUX 0x2770
#define REG_CKG_P3_TMDS_HDMI_MUX_S 0
#define REG_CKG_P3_TMDS_HDMI_MUX_E 3
#define REG_CKG_PIX_TMDSPLL_DSCD 0x2778
#define REG_CKG_PIX_TMDSPLL_DSCD_S 0
#define REG_CKG_PIX_TMDSPLL_DSCD_E 4
#define REG_CKG_PIX_XC_S0 0x2780
#define REG_CKG_PIX_XC_S0_S 0
#define REG_CKG_PIX_XC_S0_E 4
#define REG_CKG_PIX_XC_S1 0x2788
#define REG_CKG_PIX_XC_S1_S 0
#define REG_CKG_PIX_XC_S1_E 4
#define REG_CKG_R2_HDMI 0x2790
#define REG_CKG_R2_HDMI_S 0
#define REG_CKG_R2_HDMI_E 1
#define REG_CKG_TIMING_DET_DTOP 0x2798
#define REG_CKG_TIMING_DET_DTOP_S 0
#define REG_CKG_TIMING_DET_DTOP_E 4
#define REG_CKG_TMDS_AUDIO_S0 0x27a0
#define REG_CKG_TMDS_AUDIO_S0_S 0
#define REG_CKG_TMDS_AUDIO_S0_E 3
#define REG_CKG_TMDS_AUDIO_S0_0 0x27a8
#define REG_CKG_TMDS_AUDIO_S0_0_S 0
#define REG_CKG_TMDS_AUDIO_S0_0_E 4
#define REG_CKG_TMDS_AUDIO_S1 0x27b0
#define REG_CKG_TMDS_AUDIO_S1_S 0
#define REG_CKG_TMDS_AUDIO_S1_E 3
#define REG_CKG_TMDS_AUDIO_S1_0 0x27b8
#define REG_CKG_TMDS_AUDIO_S1_0_S 0
#define REG_CKG_TMDS_AUDIO_S1_0_E 4
#define REG_CKG_TMDS_DSCD 0x27c0
#define REG_CKG_TMDS_DSCD_S 0
#define REG_CKG_TMDS_DSCD_E 4
#define REG_CKG_XTAL_24 0x27c8
#define REG_CKG_XTAL_24_S 0
#define REG_CKG_XTAL_24_E 1
#define REG_CKG_XTAL_HDMI_12 0x27d0
#define REG_CKG_XTAL_HDMI_12_S 0
#define REG_CKG_XTAL_HDMI_12_E 2
#define REG_CKG_P0_TMDSPLL_TEST_DIG 0x27d8
#define REG_CKG_P0_TMDSPLL_TEST_DIG_S 0
#define REG_CKG_P0_TMDSPLL_TEST_DIG_E 3
#define REG_CKG_P1_TMDSPLL_TEST_DIG 0x27e0
#define REG_CKG_P1_TMDSPLL_TEST_DIG_S 0
#define REG_CKG_P1_TMDSPLL_TEST_DIG_E 3
#define REG_CKG_P2_TMDSPLL_TEST_DIG 0x27e8
#define REG_CKG_P2_TMDSPLL_TEST_DIG_S 0
#define REG_CKG_P2_TMDSPLL_TEST_DIG_E 3
#define REG_CKG_P3_TMDSPLL_TEST_DIG 0x27f0
#define REG_CKG_P3_TMDSPLL_TEST_DIG_S 0
#define REG_CKG_P3_TMDSPLL_TEST_DIG_E 3
#define REG_CKG_128FS_FB_S0_FF 0x27f8
#define REG_CKG_128FS_FB_S0_FF_S 0
#define REG_CKG_128FS_FB_S0_FF_E 3
#define REG_CKG_128FS_FB_S1_FF 0x2800
#define REG_CKG_128FS_FB_S1_FF_S 0
#define REG_CKG_128FS_FB_S1_FF_E 3
#define REG_CKG_DET_RCLK 0x28e0
#define REG_CKG_DET_RCLK_S 0
#define REG_CKG_DET_RCLK_E 2
#define REG_CKG_DET_WCLK 0x28e8
#define REG_CKG_DET_WCLK_S 0
#define REG_CKG_DET_WCLK_E 5
#define REG_CKG_LPLL_ODCLK 0x28f0
#define REG_CKG_LPLL_ODCLK_S 0
#define REG_CKG_LPLL_ODCLK_E 5
#define REG_CKG_LPLL_ODCLK_NODIV 0x28f8
#define REG_CKG_LPLL_ODCLK_NODIV_S 0
#define REG_CKG_LPLL_ODCLK_NODIV_E 1
#define REG_CKG_LPLL_SYN_432 0x2900
#define REG_CKG_LPLL_SYN_432_S 0
#define REG_CKG_LPLL_SYN_432_E 2
#define REG_CKG_LPLL_SYN_864 0x2908
#define REG_CKG_LPLL_SYN_864_S 0
#define REG_CKG_LPLL_SYN_864_E 1
#define REG_CKG_MOD_A_ODCLK 0x2910
#define REG_CKG_MOD_A_ODCLK_S 0
#define REG_CKG_MOD_A_ODCLK_E 5
#define REG_CKG_MOD_D_ODCLK 0x2918
#define REG_CKG_MOD_D_ODCLK_S 0
#define REG_CKG_MOD_D_ODCLK_E 5
#define REG_CKG_MOD_O_SR_WCLK 0x291c
#define REG_CKG_MOD_O_SR_WCLK_S 0
#define REG_CKG_MOD_O_SR_WCLK_E 4
#define REG_CKG_MOD_V1_SR_WCLK 0x2920
#define REG_CKG_MOD_V1_SR_WCLK_S 0
#define REG_CKG_MOD_V1_SR_WCLK_E 4
#define REG_CKG_MOD_V2_SR_WCLK 0x2924
#define REG_CKG_MOD_V2_SR_WCLK_S 0
#define REG_CKG_MOD_V2_SR_WCLK_E 4
#define REG_CKG_O_MOD_SR_RCLK 0x2928
#define REG_CKG_O_MOD_SR_RCLK_S 0
#define REG_CKG_O_MOD_SR_RCLK_E 3
#define REG_CKG_O_ODCLK 0x2930
#define REG_CKG_O_ODCLK_S 0
#define REG_CKG_O_ODCLK_E 5
#define REG_CKG_O_ODCLK_STG1 0x2938
#define REG_CKG_O_ODCLK_STG1_S 0
#define REG_CKG_O_ODCLK_STG1_E 5
#define REG_CKG_O_ODCLK_STG2 0x2940
#define REG_CKG_O_ODCLK_STG2_S 0
#define REG_CKG_O_ODCLK_STG2_E 5
#define REG_CKG_O_ODCLK_STG3 0x2948
#define REG_CKG_O_ODCLK_STG3_S 0
#define REG_CKG_O_ODCLK_STG3_E 5
#define REG_CKG_O_ODCLK_STG4 0x2950
#define REG_CKG_O_ODCLK_STG4_S 0
#define REG_CKG_O_ODCLK_STG4_E 5
#define REG_CKG_O_ODCLK_STG5 0x2958
#define REG_CKG_O_ODCLK_STG5_S 0
#define REG_CKG_O_ODCLK_STG5_E 5
#define REG_CKG_O_ODCLK_STG6 0x2960
#define REG_CKG_O_ODCLK_STG6_S 0
#define REG_CKG_O_ODCLK_STG6_E 5
#define REG_CKG_PWM 0x2968
#define REG_CKG_PWM_S 0
#define REG_CKG_PWM_E 6
#define REG_CKG_V1_MOD_SR_RCLK 0x2970
#define REG_CKG_V1_MOD_SR_RCLK_S 0
#define REG_CKG_V1_MOD_SR_RCLK_E 3
#define REG_CKG_V1_ODCLK 0x2978
#define REG_CKG_V1_ODCLK_S 0
#define REG_CKG_V1_ODCLK_E 5
#define REG_CKG_V1_ODCLK_STG1 0x2980
#define REG_CKG_V1_ODCLK_STG1_S 0
#define REG_CKG_V1_ODCLK_STG1_E 5
#define REG_CKG_V1_ODCLK_STG2 0x2988
#define REG_CKG_V1_ODCLK_STG2_S 0
#define REG_CKG_V1_ODCLK_STG2_E 5
#define REG_CKG_V1_ODCLK_STG3 0x2990
#define REG_CKG_V1_ODCLK_STG3_S 0
#define REG_CKG_V1_ODCLK_STG3_E 5
#define REG_CKG_V1_ODCLK_STG4 0x2998
#define REG_CKG_V1_ODCLK_STG4_S 0
#define REG_CKG_V1_ODCLK_STG4_E 5
#define REG_CKG_V1_ODCLK_STG5 0x29a0
#define REG_CKG_V1_ODCLK_STG5_S 0
#define REG_CKG_V1_ODCLK_STG5_E 5
#define REG_CKG_V1_ODCLK_STG6 0x29a8
#define REG_CKG_V1_ODCLK_STG6_S 0
#define REG_CKG_V1_ODCLK_STG6_E 5
#define REG_CKG_V1_ODCLK_STG7 0x29b0
#define REG_CKG_V1_ODCLK_STG7_S 0
#define REG_CKG_V1_ODCLK_STG7_E 5
#define REG_CKG_V1_ODCLK_STG8 0x29b8
#define REG_CKG_V1_ODCLK_STG8_S 0
#define REG_CKG_V1_ODCLK_STG8_E 5
#define REG_CKG_V2_MOD_SR_RCLK 0x29c0
#define REG_CKG_V2_MOD_SR_RCLK_S 0
#define REG_CKG_V2_MOD_SR_RCLK_E 3
#define REG_CKG_V2_ODCLK 0x29c8
#define REG_CKG_V2_ODCLK_S 0
#define REG_CKG_V2_ODCLK_E 5
#define REG_CKG_V2_ODCLK_STG1 0x29d0
#define REG_CKG_V2_ODCLK_STG1_S 0
#define REG_CKG_V2_ODCLK_STG1_E 5
#define REG_CKG_V2_ODCLK_STG2 0x29d8
#define REG_CKG_V2_ODCLK_STG2_S 0
#define REG_CKG_V2_ODCLK_STG2_E 5
#define REG_CKG_V2_ODCLK_STG3 0x29e0
#define REG_CKG_V2_ODCLK_STG3_S 0
#define REG_CKG_V2_ODCLK_STG3_E 5
#define REG_CKG_V2_ODCLK_STG4 0x29e8
#define REG_CKG_V2_ODCLK_STG4_S 0
#define REG_CKG_V2_ODCLK_STG4_E 5
#define REG_CKG_V2_ODCLK_STG5 0x29f0
#define REG_CKG_V2_ODCLK_STG5_S 0
#define REG_CKG_V2_ODCLK_STG5_E 5
#define REG_CKG_V2_ODCLK_STG6 0x29f8
#define REG_CKG_V2_ODCLK_STG6_S 0
#define REG_CKG_V2_ODCLK_STG6_E 5
#define REG_CKG_V2_ODCLK_STG7 0x2a00
#define REG_CKG_V2_ODCLK_STG7_S 0
#define REG_CKG_V2_ODCLK_STG7_E 5
#define REG_CKG_O_MOD_SR_RCLK_FINIAL 0x2a08
#define REG_CKG_O_MOD_SR_RCLK_FINIAL_S 0
#define REG_CKG_O_MOD_SR_RCLK_FINIAL_E 2
#define REG_CKG_O_MOD_SR_RCLK_PRE0 0x2a10
#define REG_CKG_O_MOD_SR_RCLK_PRE0_S 0
#define REG_CKG_O_MOD_SR_RCLK_PRE0_E 2
#define REG_CKG_O_MOD_SR_RCLK_PRE1 0x2a18
#define REG_CKG_O_MOD_SR_RCLK_PRE1_S 0
#define REG_CKG_O_MOD_SR_RCLK_PRE1_E 2
#define REG_CKG_V1_MOD_SR_RCLK_FINIAL 0x2a20
#define REG_CKG_V1_MOD_SR_RCLK_FINIAL_S 0
#define REG_CKG_V1_MOD_SR_RCLK_FINIAL_E 2
#define REG_CKG_V1_MOD_SR_RCLK_PRE0 0x2a28
#define REG_CKG_V1_MOD_SR_RCLK_PRE0_S 0
#define REG_CKG_V1_MOD_SR_RCLK_PRE0_E 2
#define REG_CKG_V1_MOD_SR_RCLK_PRE1 0x2a30
#define REG_CKG_V1_MOD_SR_RCLK_PRE1_S 0
#define REG_CKG_V1_MOD_SR_RCLK_PRE1_E 2
#define REG_CKG_V2_MOD_SR_RCLK_FINIAL 0x2a38
#define REG_CKG_V2_MOD_SR_RCLK_FINIAL_S 0
#define REG_CKG_V2_MOD_SR_RCLK_FINIAL_E 2
#define REG_CKG_V2_MOD_SR_RCLK_PRE0 0x2a40
#define REG_CKG_V2_MOD_SR_RCLK_PRE0_S 0
#define REG_CKG_V2_MOD_SR_RCLK_PRE0_E 2
#define REG_CKG_V2_MOD_SR_RCLK_PRE1 0x2a48
#define REG_CKG_V2_MOD_SR_RCLK_PRE1_S 0
#define REG_CKG_V2_MOD_SR_RCLK_PRE1_E 2
#define REG_CKG_IDCLK_MOD 0x2a50
#define REG_CKG_IDCLK_MOD_S 0
#define REG_CKG_IDCLK_MOD_E 2
#define REG_CKG_V1_ODCLK_STG9 0x2a58
#define REG_CKG_V1_ODCLK_STG9_S 0
#define REG_CKG_V1_ODCLK_STG9_E 5
#define REG_CKG_XTAL_12M_MOD 0x2a60
#define REG_CKG_XTAL_12M_MOD_S 0
#define REG_CKG_XTAL_12M_MOD_E 1
#define REG_CKG_XTAL_24M_MOD 0x2a68
#define REG_CKG_XTAL_24M_MOD_S 0
#define REG_CKG_XTAL_24M_MOD_E 1
#define REG_CKG_XC_OD_DELTA_SCIP 0x2a7c
#define REG_CKG_XC_OD_DELTA_SCIP_S 0
#define REG_CKG_XC_OD_DELTA_SCIP_E 1
#define REG_CKG_XC_OD_DELTA_SCSCL 0x2a80
#define REG_CKG_XC_OD_DELTA_SCSCL_S 0
#define REG_CKG_XC_OD_DELTA_SCSCL_E 1
#define REG_CKG_XC_OD_SCSCL 0x2a80
#define REG_CKG_XC_OD_SCSCL_S 8
#define REG_CKG_XC_OD_SCSCL_E 9
#define REG_CKG_V1_ODCLK_SCSCL 0x2a84
#define REG_CKG_V1_ODCLK_SCSCL_S 0
#define REG_CKG_V1_ODCLK_SCSCL_E 5
#define REG_CKG_V2_ODCLK_SCSCL 0x2a84
#define REG_CKG_V2_ODCLK_SCSCL_S 8
#define REG_CKG_V2_ODCLK_SCSCL_E 13
#define REG_V1_V2_O_ODCLK_FROM_MOD 0x2a88
#define REG_V1_V2_O_ODCLK_FROM_MOD_S 0
#define REG_V1_V2_O_ODCLK_FROM_MOD_E 0
#define REG_CKG_V1_ODCLK_SCIP 0x2a8c
#define REG_CKG_V1_ODCLK_SCIP_S 0
#define REG_CKG_V1_ODCLK_SCIP_E 5
#define REG_CKG_V2_ODCLK_SCIP 0x2a8c
#define REG_CKG_V2_ODCLK_SCIP_S 8
#define REG_CKG_V2_ODCLK_SCIP_E 13
#define REG_CKG_V1_ODCLK_SCTCON 0x2a90
#define REG_CKG_V1_ODCLK_SCTCON_S 0
#define REG_CKG_V1_ODCLK_SCTCON_E 5
#define REG_CKG_V1_ODCLK_SCDISP 0x2a90
#define REG_CKG_V1_ODCLK_SCDISP_S 8
#define REG_CKG_V1_ODCLK_SCDISP_E 13
#define REG_CKG_V1_ODCLK_SCMW 0x2a94
#define REG_CKG_V1_ODCLK_SCMW_S 0
#define REG_CKG_V1_ODCLK_SCMW_E 5
#define REG_CKG_V2_ODCLK_SCTCON 0x2a98
#define REG_CKG_V2_ODCLK_SCTCON_S 0
#define REG_CKG_V2_ODCLK_SCTCON_E 5
#define REG_CKG_O_ODCLK_SCTCON 0x2a9c
#define REG_CKG_O_ODCLK_SCTCON_S 0
#define REG_CKG_O_ODCLK_SCTCON_E 5
#define REG_CKG_XC_DC0 0x2aa0
#define REG_CKG_XC_DC0_S 0
#define REG_CKG_XC_DC0_E 4
#define REG_CKG_XC_SUB1_DC0 0x2aa4
#define REG_CKG_XC_SUB1_DC0_S 0
#define REG_CKG_XC_SUB1_DC0_E 4
#define REG_CKG_XC_SUB_DC0 0x2aa8
#define REG_CKG_XC_SUB_DC0_S 0
#define REG_CKG_XC_SUB_DC0_E 4
#define REG_CKG_XC_VEIN_SCIP 0x2aac
#define REG_CKG_XC_VEIN_SCIP_S 0
#define REG_CKG_XC_VEIN_SCIP_E 3
#define REG_CKG_XC_B2R 0x2ab0
#define REG_CKG_XC_B2R_S 0
#define REG_CKG_XC_B2R_E 2
#define REG_CKG_XC_OD_META_SCTCON 0x2ab4
#define REG_CKG_XC_OD_META_SCTCON_S 0
#define REG_CKG_XC_OD_META_SCTCON_E 1
#define REG_CKG_XC_B2R_SUB 0x2ab8
#define REG_CKG_XC_B2R_SUB_S 0
#define REG_CKG_XC_B2R_SUB_E 2
#define REG_CKG_XC_OD_DELTA_META_SCTCON 0x2abc
#define REG_CKG_XC_OD_DELTA_META_SCTCON_S 0
#define REG_CKG_XC_OD_DELTA_META_SCTCON_E 1
#define REG_CKG_XC_ED 0x2ac0
#define REG_CKG_XC_ED_S 0
#define REG_CKG_XC_ED_E 3
#define REG_CKG_XC_OD_OSD_META_SCTCON 0x2ac4
#define REG_CKG_XC_OD_OSD_META_SCTCON_S 0
#define REG_CKG_XC_OD_OSD_META_SCTCON_E 1
#define REG_CKG_XC_FD 0x2ac8
#define REG_CKG_XC_FD_S 0
#define REG_CKG_XC_FD_E 3
#define REG_CKG_XC_FD_SCIP 0x2ac8
#define REG_CKG_XC_FD_SCIP_S 8
#define REG_CKG_XC_FD_SCIP_E 9
#define REG_CKG_XC_FD_SCSCL 0x2ac8
#define REG_CKG_XC_FD_SCSCL_S 12
#define REG_CKG_XC_FD_SCSCL_E 13
#define REG_CKG_V1_META_ODCLK_SCTCON 0x2acc
#define REG_CKG_V1_META_ODCLK_SCTCON_S 0
#define REG_CKG_V1_META_ODCLK_SCTCON_E 5
#define REG_CKG_XC_FN 0x2ad0
#define REG_CKG_XC_FN_S 0
#define REG_CKG_XC_FN_E 3
#define REG_CKG_V2_META_ODCLK_SCTCON 0x2ad4
#define REG_CKG_V2_META_ODCLK_SCTCON_S 0
#define REG_CKG_V2_META_ODCLK_SCTCON_E 5
#define REG_CKG_XC_FS 0x2ad8
#define REG_CKG_XC_FS_S 0
#define REG_CKG_XC_FS_E 3
#define REG_CKG_XC_FS_SCNR 0x2ad8
#define REG_CKG_XC_FS_SCNR_S 4
#define REG_CKG_XC_FS_SCNR_E 5
#define REG_CKG_XC_FS_SCIP 0x2ad8
#define REG_CKG_XC_FS_SCIP_S 8
#define REG_CKG_XC_FS_SCIP_E 9
#define REG_CKG_O_META_ODCLK_SCTCON 0x2adc
#define REG_CKG_O_META_ODCLK_SCTCON_S 0
#define REG_CKG_O_META_ODCLK_SCTCON_E 5
#define REG_CKG_XC_OD 0x2ae0
#define REG_CKG_XC_OD_S 0
#define REG_CKG_XC_OD_E 2
#define REG_CKG_XC_OD_SCIP 0x2ae0
#define REG_CKG_XC_OD_SCIP_S 8
#define REG_CKG_XC_OD_SCIP_E 9
#define REG_CKG_XC_SLOW 0x2ae8
#define REG_CKG_XC_SLOW_S 0
#define REG_CKG_XC_SLOW_E 2
#define REG_CKG_XC_SRS 0x2af0
#define REG_CKG_XC_SRS_S 0
#define REG_CKG_XC_SRS_E 2
#define REG_CKG_XC_FS_SCACE 0x2af8
#define REG_CKG_XC_FS_SCACE_S 0
#define REG_CKG_XC_FS_SCACE_E 1
#define REG_CKG_XTAL_12M_SCACE 0x2b00
#define REG_CKG_XTAL_12M_SCACE_S 0
#define REG_CKG_XTAL_12M_SCACE_E 1
#define REG_CKG_XTAL_24M_SCACE 0x2b08
#define REG_CKG_XTAL_24M_SCACE_S 0
#define REG_CKG_XTAL_24M_SCACE_E 1
#define REG_CKG_XC_DC0_SCIP 0x2b10
#define REG_CKG_XC_DC0_SCIP_S 0
#define REG_CKG_XC_DC0_SCIP_E 1
#define REG_CKG_XC_DBG2MIU_SCIP 0x2b18
#define REG_CKG_XC_DBG2MIU_SCIP_S 0
#define REG_CKG_XC_DBG2MIU_SCIP_E 3
#define REG_CKG_XC_ED0_SCIP 0x2b20
#define REG_CKG_XC_ED0_SCIP_S 0
#define REG_CKG_XC_ED0_SCIP_E 1
#define REG_CKG_XC_ED1_SCIP 0x2b28
#define REG_CKG_XC_ED1_SCIP_S 0
#define REG_CKG_XC_ED1_SCIP_E 1
#define REG_CKG_XC_FN_SCIP 0x2b30
#define REG_CKG_XC_FN_SCIP_S 0
#define REG_CKG_XC_FN_SCIP_E 1
#define REG_CKG_XC_ID0_SCIP 0x2b38
#define REG_CKG_XC_ID0_SCIP_S 0
#define REG_CKG_XC_ID0_SCIP_E 4
#define REG_CKG_XC_ID1_SCIP 0x2b40
#define REG_CKG_XC_ID1_SCIP_S 0
#define REG_CKG_XC_ID1_SCIP_E 4
#define REG_CKG_XTAL_24M_SCIP 0x2b48
#define REG_CKG_XTAL_24M_SCIP_S 0
#define REG_CKG_XTAL_24M_SCIP_E 1
#define REG_CKG_XTAL_12M_SCIP 0x2b50
#define REG_CKG_XTAL_12M_SCIP_S 0
#define REG_CKG_XTAL_12M_SCIP_E 1
#define REG_CKG_XTAL_IP1_SCIP 0x2b58
#define REG_CKG_XTAL_IP1_SCIP_S 0
#define REG_CKG_XTAL_IP1_SCIP_E 3
#define REG_CKG_XC_FD_SCMW 0x2b60
#define REG_CKG_XC_FD_SCMW_S 0
#define REG_CKG_XC_FD_SCMW_E 1
#define REG_CKG_XC_FN_SCMW 0x2b68
#define REG_CKG_XC_FN_SCMW_S 0
#define REG_CKG_XC_FN_SCMW_E 1
#define REG_CKG_XC_FS_SCMW 0x2b70
#define REG_CKG_XC_FS_SCMW_S 0
#define REG_CKG_XC_FS_SCMW_E 1
#define REG_CKG_XC_OD_SCMW 0x2b78
#define REG_CKG_XC_OD_SCMW_S 0
#define REG_CKG_XC_OD_SCMW_E 1
#define REG_CKG_XTAL_24M_SCMW 0x2b80
#define REG_CKG_XTAL_24M_SCMW_S 0
#define REG_CKG_XTAL_24M_SCMW_E 1
#define REG_CKG_XC_FN_SCNR 0x2b88
#define REG_CKG_XC_FN_SCNR_S 0
#define REG_CKG_XC_FN_SCNR_E 1
#define REG_CKG_XTAL_24M_SCNR 0x2b98
#define REG_CKG_XTAL_24M_SCNR_S 0
#define REG_CKG_XTAL_24M_SCNR_E 1
#define REG_CKG_XC_FN_SCPQ 0x2ba0
#define REG_CKG_XC_FN_SCPQ_S 0
#define REG_CKG_XC_FN_SCPQ_E 1
#define REG_CKG_XTAL_24M_SCPQ 0x2ba8
#define REG_CKG_XTAL_24M_SCPQ_S 0
#define REG_CKG_XTAL_24M_SCPQ_E 1
#define REG_CKG_XC_FN_SCSCL 0x2bb0
#define REG_CKG_XC_FN_SCSCL_S 0
#define REG_CKG_XC_FN_SCSCL_E 1
#define REG_CKG_XC_FS_SCSCL 0x2bb8
#define REG_CKG_XC_FS_SCSCL_S 0
#define REG_CKG_XC_FS_SCSCL_E 1
#define REG_CKG_XC_SRS_SCSCL 0x2bbc
#define REG_CKG_XC_SRS_SCSCL_S 0
#define REG_CKG_XC_SRS_SCSCL_E 1
#define REG_CKG_XTAL_12M_SCSCL 0x2bc0
#define REG_CKG_XTAL_12M_SCSCL_S 0
#define REG_CKG_XTAL_12M_SCSCL_E 1
#define REG_CKG_XTAL_24M_SCSCL 0x2bc8
#define REG_CKG_XTAL_24M_SCSCL_S 0
#define REG_CKG_XTAL_24M_SCSCL_E 1
#define REG_CKG_XC_FS_SCSR 0x2bd0
#define REG_CKG_XC_FS_SCSR_S 0
#define REG_CKG_XC_FS_SCSR_E 1
#define REG_CKG_XC_SR_ALAI_SCSR 0x2bd8
#define REG_CKG_XC_SR_ALAI_SCSR_S 0
#define REG_CKG_XC_SR_ALAI_SCSR_E 2
#define REG_CKG_XC_SR_SRAM_SHARE_SCSR 0x2be0
#define REG_CKG_XC_SR_SRAM_SHARE_SCSR_S 0
#define REG_CKG_XC_SR_SRAM_SHARE_SCSR_E 2
#define REG_CKG_XC_SRS_SCSR 0x2be8
#define REG_CKG_XC_SRS_SCSR_S 0
#define REG_CKG_XC_SRS_SCSR_E 1
#define REG_CKG_XTAL_12M_SCSR 0x2bf0
#define REG_CKG_XTAL_12M_SCSR_S 0
#define REG_CKG_XTAL_12M_SCSR_E 1
#define REG_CKG_XTAL_24M_SCSR 0x2bf8
#define REG_CKG_XTAL_24M_SCSR_S 0
#define REG_CKG_XTAL_24M_SCSR_E 1
#define REG_CKG_XC_FD_SCTCON 0x2c00
#define REG_CKG_XC_FD_SCTCON_S 0
#define REG_CKG_XC_FD_SCTCON_E 1
#define REG_CKG_XC_FD_SCDISP 0x2c00
#define REG_CKG_XC_FD_SCDISP_S 4
#define REG_CKG_XC_FD_SCDISP_E 5
#define REG_CKG_XC_FN_SCTCON 0x2c08
#define REG_CKG_XC_FN_SCTCON_S 0
#define REG_CKG_XC_FN_SCTCON_E 1
#define REG_CKG_XC_FN_SCDISP 0x2c08
#define REG_CKG_XC_FN_SCDISP_S 4
#define REG_CKG_XC_FN_SCDISP_E 5
#define REG_CKG_XC_OD_SCTCON 0x2c10
#define REG_CKG_XC_OD_SCTCON_S 0
#define REG_CKG_XC_OD_SCTCON_E 1
#define REG_CKG_XTAL_12M_SCTCON 0x2c18
#define REG_CKG_XTAL_12M_SCTCON_S 0
#define REG_CKG_XTAL_12M_SCTCON_E 1
#define REG_CKG_XTAL_12M_SCDISP 0x2c18
#define REG_CKG_XTAL_12M_SCDISP_S 4
#define REG_CKG_XTAL_12M_SCDISP_E 5
#define REG_CKG_XTAL_24M_SCTCON 0x2c20
#define REG_CKG_XTAL_24M_SCTCON_S 0
#define REG_CKG_XTAL_24M_SCTCON_E 1
#define REG_CKG_XTAL_24M_SCDISP 0x2c20
#define REG_CKG_XTAL_24M_SCDISP_S 4
#define REG_CKG_XTAL_24M_SCDISP_E 5
#define REG_CKG_XC_FN_SCDV 0x2c28
#define REG_CKG_XC_FN_SCDV_S 0
#define REG_CKG_XC_FN_SCDV_E 1
#define REG_CKG_XTAL_12M_SCDV 0x2c30
#define REG_CKG_XTAL_12M_SCDV_S 0
#define REG_CKG_XTAL_12M_SCDV_E 1
#define REG_CKG_XTAL_24M_SCDV 0x2c38
#define REG_CKG_XTAL_24M_SCDV_S 0
#define REG_CKG_XTAL_24M_SCDV_E 1
#define REG_CKG_XCPLL_SYN 0x2c40
#define REG_CKG_XCPLL_SYN_S 0
#define REG_CKG_XCPLL_SYN_E 3
#define REG_CKG_DELTA_B2P2_SRAM 0x2c48
#define REG_CKG_DELTA_B2P2_SRAM_S 0
#define REG_CKG_DELTA_B2P2_SRAM_E 2
#define REG_CKG_GUCD_18_LUT2_SRAM 0x2c50
#define REG_CKG_GUCD_18_LUT2_SRAM_S 0
#define REG_CKG_GUCD_18_LUT2_SRAM_E 2
#define REG_CKG_GUCD_256_LUT2_SRAM 0x2c58
#define REG_CKG_GUCD_256_LUT2_SRAM_S 0
#define REG_CKG_GUCD_256_LUT2_SRAM_E 2
#define REG_CKG_HSY_8P3_SRAM 0x2c60
#define REG_CKG_HSY_8P3_SRAM_S 0
#define REG_CKG_HSY_8P3_SRAM_E 2
#define REG_CKG_HSY_8P_SRAM 0x2c68
#define REG_CKG_HSY_8P_SRAM_S 0
#define REG_CKG_HSY_8P_SRAM_E 2
#define REG_CKG_DIP1_HVSP_SRAM 0x2c6c
#define REG_CKG_DIP1_HVSP_SRAM_S 0
#define REG_CKG_DIP1_HVSP_SRAM_E 2
#define REG_CKG_LCE_ACE_SRAM 0x2c70
#define REG_CKG_LCE_ACE_SRAM_S 0
#define REG_CKG_LCE_ACE_SRAM_E 2
#define REG_CKG_DIP1_XVYCC_SRAM 0x2c74
#define REG_CKG_DIP1_XVYCC_SRAM_S 0
#define REG_CKG_DIP1_XVYCC_SRAM_E 2
#define REG_CKG_PQ_GAMMA_SRAM 0x2c78
#define REG_CKG_PQ_GAMMA_SRAM_S 0
#define REG_CKG_PQ_GAMMA_SRAM_E 2
#define REG_CKG_RGB_3DLUT_SRAM 0x2c80
#define REG_CKG_RGB_3DLUT_SRAM_S 0
#define REG_CKG_RGB_3DLUT_SRAM_E 2
#define REG_CKG_VIP_ACE_SRAM 0x2c88
#define REG_CKG_VIP_ACE_SRAM_S 0
#define REG_CKG_VIP_ACE_SRAM_E 2
#define REG_CKG_XVYCC_SRAM 0x2c90
#define REG_CKG_XVYCC_SRAM_S 0
#define REG_CKG_XVYCC_SRAM_E 2
#define REG_CKG_DV_HW5_SRAM 0x2c98
#define REG_CKG_DV_HW5_SRAM_S 0
#define REG_CKG_DV_HW5_SRAM_E 2
#define REG_CKG_DC0_SRAM 0x2ca0
#define REG_CKG_DC0_SRAM_S 0
#define REG_CKG_DC0_SRAM_E 2
#define REG_CKG_UCD_ST_SRAM 0x2ca8
#define REG_CKG_UCD_ST_SRAM_S 0
#define REG_CKG_UCD_ST_SRAM_E 2
#define REG_CKG_XC_ADC_SCIP 0x2cb0
#define REG_CKG_XC_ADC_SCIP_S 0
#define REG_CKG_XC_ADC_SCIP_E 2
#define REG_CKG_XC_SUB_DC0_SCIP 0x2cb8
#define REG_CKG_XC_SUB_DC0_SCIP_S 0
#define REG_CKG_XC_SUB_DC0_SCIP_E 1
#define REG_CKG_XC_SUB1_DC0_SCIP 0x2cbc
#define REG_CKG_XC_SUB1_DC0_SCIP_S 0
#define REG_CKG_XC_SUB1_DC0_SCIP_E 1
#define REG_CKG_XC_DISP_MFDEC_SCIP 0x2cc0
#define REG_CKG_XC_DISP_MFDEC_SCIP_S 0
#define REG_CKG_XC_DISP_MFDEC_SCIP_E 1
#define REG_CKG_XC_HD2MIU_M_SCIP 0x2cc8
#define REG_CKG_XC_HD2MIU_M_SCIP_S 0
#define REG_CKG_XC_HD2MIU_M_SCIP_E 2
#define REG_CKG_XC_HD2MIU_S_SCIP 0x2cd0
#define REG_CKG_XC_HD2MIU_S_SCIP_S 0
#define REG_CKG_XC_HD2MIU_S_SCIP_E 2
#define REG_CKG_XC_HDMI0_SCIP 0x2cd8
#define REG_CKG_XC_HDMI0_SCIP_S 0
#define REG_CKG_XC_HDMI0_SCIP_E 2
#define REG_CKG_XC_HDMI1_SCIP 0x2ce0
#define REG_CKG_XC_HDMI1_SCIP_S 0
#define REG_CKG_XC_HDMI1_SCIP_E 2
#define REG_CKG_XC_HDMI2_SCIP 0x2ce8
#define REG_CKG_XC_HDMI2_SCIP_S 0
#define REG_CKG_XC_HDMI2_SCIP_E 2
#define REG_CKG_XC_HDMI3_SCIP 0x2cf0
#define REG_CKG_XC_HDMI3_SCIP_S 0
#define REG_CKG_XC_HDMI3_SCIP_E 2
#define REG_CKG_XC_IP2_SRC_SCIP 0x2cf8
#define REG_CKG_XC_IP2_SRC_SCIP_S 0
#define REG_CKG_XC_IP2_SRC_SCIP_E 3
#define REG_CKG_XC_SLOW_SCIP 0x2d00
#define REG_CKG_XC_SLOW_SCIP_S 0
#define REG_CKG_XC_SLOW_SCIP_E 1
#define REG_CKG_XC_TGEN_WIN_SCIP 0x2d08
#define REG_CKG_XC_TGEN_WIN_SCIP_S 0
#define REG_CKG_XC_TGEN_WIN_SCIP_E 4
#define REG_CKG_XC_UCD_STAT_SCIP 0x2d10
#define REG_CKG_XC_UCD_STAT_SCIP_S 0
#define REG_CKG_XC_UCD_STAT_SCIP_E 3
#define REG_CKG_XC_VD_SCIP 0x2d18
#define REG_CKG_XC_VD_SCIP_S 0
#define REG_CKG_XC_VD_SCIP_E 1
#define REG_CKG_XC_VE_SCIP 0x2d20
#define REG_CKG_XC_VE_SCIP_S 0
#define REG_CKG_XC_VE_SCIP_E 3
#define REG_CKG_XC_VEDAC 0x2d28
#define REG_CKG_XC_VEDAC_S 0
#define REG_CKG_XC_VEDAC_E 1
#define REG_CKG_DBK_HW_SRAM 0x2d30
#define REG_CKG_DBK_HW_SRAM_S 0
#define REG_CKG_DBK_HW_SRAM_E 2
#define REG_CKG_SCNR_HDR_SRAM 0x2d38
#define REG_CKG_SCNR_HDR_SRAM_S 0
#define REG_CKG_SCNR_HDR_SRAM_E 2
#define REG_CKG_SPF_HDBK_SRAM 0x2d40
#define REG_CKG_SPF_HDBK_SRAM_S 0
#define REG_CKG_SPF_HDBK_SRAM_E 2
#define REG_CKG_VDBK_SRAM 0x2d48
#define REG_CKG_VDBK_SRAM_S 0
#define REG_CKG_VDBK_SRAM_E 2
#define REG_CKG_DELTA_B2P_SRAM 0x2d50
#define REG_CKG_DELTA_B2P_SRAM_S 0
#define REG_CKG_DELTA_B2P_SRAM_E 2
#define REG_CKG_GUCD_18_SRAM 0x2d58
#define REG_CKG_GUCD_18_SRAM_S 0
#define REG_CKG_GUCD_18_SRAM_E 2
#define REG_CKG_GUCD_256_SRAM 0x2d60
#define REG_CKG_GUCD_256_SRAM_S 0
#define REG_CKG_GUCD_256_SRAM_E 2
#define REG_CKG_HSY_SP3_SRAM 0x2d68
#define REG_CKG_HSY_SP3_SRAM_S 0
#define REG_CKG_HSY_SP3_SRAM_E 2
#define REG_CKG_HSY_SP_SRAM 0x2d70
#define REG_CKG_HSY_SP_SRAM_S 0
#define REG_CKG_HSY_SP_SRAM_E 2
#define REG_CKG_HVSP_STP1_SRAM 0x2d78
#define REG_CKG_HVSP_STP1_SRAM_S 0
#define REG_CKG_HVSP_STP1_SRAM_E 2
#define REG_CKG_HVSP_STP2_SRAM 0x2d80
#define REG_CKG_HVSP_STP2_SRAM_S 0
#define REG_CKG_HVSP_STP2_SRAM_E 2
#define REG_CKG_LCE_SCL_SRAM 0x2d88
#define REG_CKG_LCE_SCL_SRAM_S 0
#define REG_CKG_LCE_SCL_SRAM_E 2
#define REG_CKG_VIP_PQ_SRAM 0x2d90
#define REG_CKG_VIP_PQ_SRAM_S 0
#define REG_CKG_VIP_PQ_SRAM_E 2
#define REG_CKG_AISR_SRAM 0x2d98
#define REG_CKG_AISR_SRAM_S 0
#define REG_CKG_AISR_SRAM_E 3
#define REG_CKG_AISR_HVSP_SRAM 0x2d9c
#define REG_CKG_AISR_HVSP_SRAM_S 0
#define REG_CKG_AISR_HVSP_SRAM_E 3
#define REG_CKG_XC_AISR_SCSR 0x2da0
#define REG_CKG_XC_AISR_SCSR_S 0
#define REG_CKG_XC_AISR_SCSR_E 2
#define REG_CKG_XC_FN_SCSR 0x2da8
#define REG_CKG_XC_FN_SCSR_S 0
#define REG_CKG_XC_FN_SCSR_E 1
#define REG_CKG_GOP0_SRAM 0x2db8
#define REG_CKG_GOP0_SRAM_S 0
#define REG_CKG_GOP0_SRAM_E 2
#define REG_CKG_GOP1_SRAM 0x2dc0
#define REG_CKG_GOP1_SRAM_S 0
#define REG_CKG_GOP1_SRAM_E 2
#define REG_CKG_GOP2_SRAM 0x2dc8
#define REG_CKG_GOP2_SRAM_S 0
#define REG_CKG_GOP2_SRAM_E 2
#define REG_CKG_GOP3_SRAM 0x2dd0
#define REG_CKG_GOP3_SRAM_S 0
#define REG_CKG_GOP3_SRAM_E 2
#define REG_CKG_LD_EDGE2D_SRAM 0x2dd8
#define REG_CKG_LD_EDGE2D_SRAM_S 0
#define REG_CKG_LD_EDGE2D_SRAM_E 2
#define REG_CKG_LDCOMP_SRAM 0x2de0
#define REG_CKG_LDCOMP_SRAM_S 0
#define REG_CKG_LDCOMP_SRAM_E 2
#define REG_CKG_LDM_GA_SRAM 0x2de8
#define REG_CKG_LDM_GA_SRAM_S 0
#define REG_CKG_LDM_GA_SRAM_E 2
#define REG_CKG_PQ_GA_SRAM 0x2dec
#define REG_CKG_PQ_GA_SRAM_S 0
#define REG_CKG_PQ_GA_SRAM_E 2
#define REG_CKG_LDMCG_SRAM 0x2df0
#define REG_CKG_LDMCG_SRAM_S 0
#define REG_CKG_LDMCG_SRAM_E 2
#define REG_CKG_OSD_DV_HW5_SRAM 0x2e00
#define REG_CKG_OSD_DV_HW5_SRAM_S 0
#define REG_CKG_OSD_DV_HW5_SRAM_E 2
#define REG_CKG_PADJ_SRAM 0x2e08
#define REG_CKG_PADJ_SRAM_S 0
#define REG_CKG_PADJ_SRAM_E 2
#define REG_CKG_PANEL_GA_SRAM 0x2e10
#define REG_CKG_PANEL_GA_SRAM_S 0
#define REG_CKG_PANEL_GA_SRAM_E 2
#define REG_CKG_SIDCLK_HD0_SCIP 0x2e14
#define REG_CKG_SIDCLK_HD0_SCIP_S 0
#define REG_CKG_SIDCLK_HD0_SCIP_E 1
#define REG_CKG_SIDCLK_HD1_SCIP 0x2e18
#define REG_CKG_SIDCLK_HD1_SCIP_S 0
#define REG_CKG_SIDCLK_HD1_SCIP_E 1
#define REG_CKG_SIDCLK_HD2_SCIP 0x2e1c
#define REG_CKG_SIDCLK_HD2_SCIP_S 0
#define REG_CKG_SIDCLK_HD2_SCIP_E 1
#define REG_CKG_SIDCLK_HD3_SCIP 0x2e20
#define REG_CKG_SIDCLK_HD3_SCIP_S 0
#define REG_CKG_SIDCLK_HD3_SCIP_E 1
#define REG_CKG_XC_DIP0_SCIP 0x2e24
#define REG_CKG_XC_DIP0_SCIP_S 0
#define REG_CKG_XC_DIP0_SCIP_E 4
#define REG_CKG_XC_DIP1_SCIP 0x2e28
#define REG_CKG_XC_DIP1_SCIP_S 0
#define REG_CKG_XC_DIP1_SCIP_E 4
#define REG_CKG_XC_DIP2_SCIP 0x2e2c
#define REG_CKG_XC_DIP2_SCIP_S 0
#define REG_CKG_XC_DIP2_SCIP_E 4
#define REG_CKG_XC_AFBC_SCTCON 0x2e30
#define REG_CKG_XC_AFBC_SCTCON_S 0
#define REG_CKG_XC_AFBC_SCTCON_E 1
#define REG_CKG_XC_GOP0_DST_SCTCON 0x2e34
#define REG_CKG_XC_GOP0_DST_SCTCON_S 0
#define REG_CKG_XC_GOP0_DST_SCTCON_E 2
#define REG_CKG_XC_GOP_SCL_SCTCON 0x2e38
#define REG_CKG_XC_GOP_SCL_SCTCON_S 0
#define REG_CKG_XC_GOP_SCL_SCTCON_E 2
#define REG_CKG_XC_GOP_SCTCON 0x2e3c
#define REG_CKG_XC_GOP_SCTCON_S 0
#define REG_CKG_XC_GOP_SCTCON_E 1
#define REG_CKG_XC_GOPC_DST_SCTCON 0x2e40
#define REG_CKG_XC_GOPC_DST_SCTCON_S 0
#define REG_CKG_XC_GOPC_DST_SCTCON_E 2
#define REG_CKG_XC_GOPG_DST_SCTCON 0x2e44
#define REG_CKG_XC_GOPG_DST_SCTCON_S 0
#define REG_CKG_XC_GOPG_DST_SCTCON_E 2
#define REG_CKG_XC_OD_DELTA_SCTCON 0x2e48
#define REG_CKG_XC_OD_DELTA_SCTCON_S 0
#define REG_CKG_XC_OD_DELTA_SCTCON_E 1
#define REG_CKG_XC_OD_DIV2_SCDISP 0x2e4c
#define REG_CKG_XC_OD_DIV2_SCDISP_S 0
#define REG_CKG_XC_OD_DIV2_SCDISP_E 1
#define REG_CKG_XC_OD_DIV4_SCDISP 0x2e50
#define REG_CKG_XC_OD_DIV4_SCDISP_S 0
#define REG_CKG_XC_OD_DIV4_SCDISP_E 2
#define REG_CKG_XC_OD_SCDISP 0x2e50
#define REG_CKG_XC_OD_SCDISP_S 4
#define REG_CKG_XC_OD_SCDISP_E 5
#define REG_FLOW_CTRL_RATE_XC_ED 0x2e54
#define REG_FLOW_CTRL_RATE_XC_ED_S 0
#define REG_FLOW_CTRL_RATE_XC_ED_E 5
#define REG_FLOW_CTRL_RATE_XC_ED_SLD_NO_SCAN 0x2e54
#define REG_FLOW_CTRL_RATE_XC_ED_SLD_NO_SCAN_S 12
#define REG_FLOW_CTRL_RATE_XC_ED_SLD_NO_SCAN_E 12
#define REG_FLOW_CTRL_RATE_XC_FN 0x2e58
#define REG_FLOW_CTRL_RATE_XC_FN_S 0
#define REG_FLOW_CTRL_RATE_XC_FN_E 5
#define REG_FLOW_CTRL_RATE_XC_FN_SLD_NO_SCAN 0x2e58
#define REG_FLOW_CTRL_RATE_XC_FN_SLD_NO_SCAN_S 12
#define REG_FLOW_CTRL_RATE_XC_FN_SLD_NO_SCAN_E 12
#define REG_FLOW_CTRL_RATE_XC_FS 0x2e5c
#define REG_FLOW_CTRL_RATE_XC_FS_S 0
#define REG_FLOW_CTRL_RATE_XC_FS_E 5
#define REG_FLOW_CTRL_RATE_XC_FS_SLD_NO_SCAN 0x2e5c
#define REG_FLOW_CTRL_RATE_XC_FS_SLD_NO_SCAN_S 12
#define REG_FLOW_CTRL_RATE_XC_FS_SLD_NO_SCAN_E 12
#define REG_FLOW_CTRL_RATE_XC_FD 0x2e60
#define REG_FLOW_CTRL_RATE_XC_FD_S 0
#define REG_FLOW_CTRL_RATE_XC_FD_E 5
#define REG_FLOW_CTRL_RATE_XC_FD_SLD_NO_SCAN 0x2e60
#define REG_FLOW_CTRL_RATE_XC_FD_SLD_NO_SCAN_S 12
#define REG_FLOW_CTRL_RATE_XC_FD_SLD_NO_SCAN_E 12
#define REG_CKG_XC_OD_OSD_SCTCON 0x2e68
#define REG_CKG_XC_OD_OSD_SCTCON_S 0
#define REG_CKG_XC_OD_OSD_SCTCON_E 1
#define REG_CKG_XC_FS_SCTCON 0x2e70
#define REG_CKG_XC_FS_SCTCON_S 0
#define REG_CKG_XC_FS_SCTCON_E 1
#define REG_CKG_XC_FS_SCDISP 0x2e70
#define REG_CKG_XC_FS_SCDISP_S 2
#define REG_CKG_XC_FS_SCDISP_E 3
#define REG_CKG_XC_SC2FPLL_SCIP 0x2e78
#define REG_CKG_XC_SC2FPLL_SCIP_S 0
#define REG_CKG_XC_SC2FPLL_SCIP_E 4
#define REG_GATE_XC_ED 0x2e80
#define REG_GATE_XC_ED_S 0
#define REG_GATE_XC_ED_E 0
#define REG_GATE_XC_FN 0x2e84
#define REG_GATE_XC_FN_S 0
#define REG_GATE_XC_FN_E 0
#define REG_GATE_XC_FS 0x2e88
#define REG_GATE_XC_FS_S 0
#define REG_GATE_XC_FS_E 0
#define REG_GATE_XC_FD 0x2e8c
#define REG_GATE_XC_FD_S 0
#define REG_GATE_XC_FD_E 0
#define REG_CKG_MCU_MAIL0 0x2ee0
#define REG_CKG_MCU_MAIL0_S 0
#define REG_CKG_MCU_MAIL0_E 2
#define REG_CKG_MCU_MAIL1 0x2ee8
#define REG_CKG_MCU_MAIL1_S 0
#define REG_CKG_MCU_MAIL1_E 2
#define REG_CKG_VD2X 0x2ef0
#define REG_CKG_VD2X_S 0
#define REG_CKG_VD2X_E 3
#define REG_CKG_VD2X_MHEG5 0x2ef0
#define REG_CKG_VD2X_MHEG5_S 8
#define REG_CKG_VD2X_MHEG5_E 9
#define REG_CKG_VD_32FSC 0x2ef8
#define REG_CKG_VD_32FSC_S 0
#define REG_CKG_VD_32FSC_E 2
#define REG_CKG_VD_32FSC_MHEG5 0x2ef8
#define REG_CKG_VD_32FSC_MHEG5_S 8
#define REG_CKG_VD_32FSC_MHEG5_E 9
#define REG_CKG_VD 0x2f00
#define REG_CKG_VD_S 0
#define REG_CKG_VD_E 3
#define REG_CKG_VD_MHEG5 0x2f00
#define REG_CKG_VD_MHEG5_S 8
#define REG_CKG_VD_MHEG5_E 9
#define REG_CKG_CMBAI 0x2f08
#define REG_CKG_CMBAI_S 0
#define REG_CKG_CMBAI_E 1
#define REG_CKG_CMBAO 0x2f10
#define REG_CKG_CMBAO_S 0
#define REG_CKG_CMBAO_E 1
#define REG_CKG_CMBBI 0x2f18
#define REG_CKG_CMBBI_S 0
#define REG_CKG_CMBBI_E 1
#define REG_CKG_CMBBO 0x2f20
#define REG_CKG_CMBBO_S 0
#define REG_CKG_CMBBO_E 1
#define REG_CKG_VE 0x2f40
#define REG_CKG_VE_S 0
#define REG_CKG_VE_E 3
#define REG_CKG_VEDAC 0x2f48
#define REG_CKG_VEDAC_S 0
#define REG_CKG_VEDAC_E 4
#define REG_CKG_VENC 0x2f50
#define REG_CKG_VENC_S 0
#define REG_CKG_VENC_E 3
#define REG_CKG_VENC_MHEG5 0x2f50
#define REG_CKG_VENC_MHEG5_S 8
#define REG_CKG_VENC_MHEG5_E 9
#define REG_CKG_SMI_FCIE_SEL 0x2f68
#define REG_CKG_SMI_FCIE_SEL_S 0
#define REG_CKG_SMI_FCIE_SEL_E 3
#define REG_CKG_ECC 0x2f70
#define REG_CKG_ECC_S 0
#define REG_CKG_ECC_E 4
#define REG_CKG_ECC_TSP 0x2f70
#define REG_CKG_ECC_TSP_S 8
#define REG_CKG_ECC_TSP_E 9
#define REG_CKG_FCIE 0x2f78
#define REG_CKG_FCIE_S 0
#define REG_CKG_FCIE_E 4
#define REG_CKG_FCIE_TSP 0x2f78
#define REG_CKG_FCIE_TSP_S 8
#define REG_CKG_FCIE_TSP_E 11
#define REG_CKG_FCIE_SYN 0x2f80
#define REG_CKG_FCIE_SYN_S 0
#define REG_CKG_FCIE_SYN_E 1
#define REG_CKG_GMAC_AHB 0x2f90
#define REG_CKG_GMAC_AHB_S 0
#define REG_CKG_GMAC_AHB_E 3
#define REG_CKG_GMAC_AHB_MHEG5 0x2f90
#define REG_CKG_GMAC_AHB_MHEG5_S 8
#define REG_CKG_GMAC_AHB_MHEG5_E 9
#define REG_CKG_GMAC_RX_MHEG5 0x2f98
#define REG_CKG_GMAC_RX_MHEG5_S 8
#define REG_CKG_GMAC_RX_MHEG5_E 9
#define REG_CKG_GMAC_TX_MHEG5 0x2fa0
#define REG_CKG_GMAC_TX_MHEG5_S 8
#define REG_CKG_GMAC_TX_MHEG5_E 9
#define REG_CKG_PEXTP_PL_PCLK_TSP 0x2fb4
#define REG_CKG_PEXTP_PL_PCLK_TSP_S 0
#define REG_CKG_PEXTP_PL_PCLK_TSP_E 2
#define REG_CKG_XTAL_12M_PCIE_PHY 0x2fb8
#define REG_CKG_XTAL_12M_PCIE_PHY_S 0
#define REG_CKG_XTAL_12M_PCIE_PHY_E 1
#define REG_CKG_PEXTP_TL 0x2fc0
#define REG_CKG_PEXTP_TL_S 0
#define REG_CKG_PEXTP_TL_E 3
#define REG_CKG_PEXTP_TL_TSP 0x2fc0
#define REG_CKG_PEXTP_TL_TSP_S 8
#define REG_CKG_PEXTP_TL_TSP_E 9
#define REG_CKG_SSUSB_USB20_PHY_CLK_TSP 0x2fc4
#define REG_CKG_SSUSB_USB20_PHY_CLK_TSP_S 0
#define REG_CKG_SSUSB_USB20_PHY_CLK_TSP_E 2
#define REG_CKG_SSUSB_USB20_PHY_CLK_1P_TSP 0x2fc8
#define REG_CKG_SSUSB_USB20_PHY_CLK_1P_TSP_S 0
#define REG_CKG_SSUSB_USB20_PHY_CLK_1P_TSP_E 2
#define REG_CKG_SSUSB_USB20_PHY_CLK_2P_TSP 0x2fcc
#define REG_CKG_SSUSB_USB20_PHY_CLK_2P_TSP_S 0
#define REG_CKG_SSUSB_USB20_PHY_CLK_2P_TSP_E 2
#define REG_CKG_SSUSB_FRMCNT_TSP 0x2fd0
#define REG_CKG_SSUSB_FRMCNT_TSP_S 0
#define REG_CKG_SSUSB_FRMCNT_TSP_E 2
#define REG_CKG_SSUSB_MISC_48M_TSP 0x2fd0
#define REG_CKG_SSUSB_MISC_48M_TSP_S 4
#define REG_CKG_SSUSB_MISC_48M_TSP_E 5
#define REG_CKG_SSUSB_PCLK_TSP 0x2fd4
#define REG_CKG_SSUSB_PCLK_TSP_S 0
#define REG_CKG_SSUSB_PCLK_TSP_E 2
#define REG_CKG_SSUSB_PCLK_1P_TSP 0x2fd8
#define REG_CKG_SSUSB_PCLK_1P_TSP_S 0
#define REG_CKG_SSUSB_PCLK_1P_TSP_E 2
#define REG_CKG_XTAL_12M_USB_PHY 0x2fe0
#define REG_CKG_XTAL_12M_USB_PHY_S 0
#define REG_CKG_XTAL_12M_USB_PHY_E 1
#define REG_CKG_SSUSB_SYS_TSP 0x2fe8
#define REG_CKG_SSUSB_SYS_TSP_S 0
#define REG_CKG_SSUSB_SYS_TSP_E 1
#define REG_CKG_SSUSB_XHCI_TSP 0x2fec
#define REG_CKG_SSUSB_XHCI_TSP_S 0
#define REG_CKG_SSUSB_XHCI_TSP_E 1
#define REG_CKG_USBPHY240_TSP 0x2ff0
#define REG_CKG_USBPHY240_TSP_S 0
#define REG_CKG_USBPHY240_TSP_E 2
#define REG_CKG_USBPHY240_MUX_TSP 0x2ff4
#define REG_CKG_USBPHY240_MUX_TSP_S 0
#define REG_CKG_USBPHY240_MUX_TSP_E 2
#define REG_CKG_USBPHY30_TSP 0x2ff8
#define REG_CKG_USBPHY30_TSP_S 0
#define REG_CKG_USBPHY30_TSP_E 2
#define REG_CKG_SMI_UHC_SEL 0x2ffc
#define REG_CKG_SMI_UHC_SEL_S 0
#define REG_CKG_SMI_UHC_SEL_E 3
#define REG_CKG_UFS 0x3000
#define REG_CKG_UFS_S 0
#define REG_CKG_UFS_E 3
#define REG_CKG_UFS_TSP 0x3000
#define REG_CKG_UFS_TSP_S 8
#define REG_CKG_UFS_TSP_E 9
#define REG_CKG_UFS_AES 0x3008
#define REG_CKG_UFS_AES_S 0
#define REG_CKG_UFS_AES_E 3
#define REG_CKG_UFS_AES_TSP 0x3008
#define REG_CKG_UFS_AES_TSP_S 8
#define REG_CKG_UFS_AES_TSP_E 9
#define REG_CKG_UFS_MP_SAP_CFG_TSP 0x300c
#define REG_CKG_UFS_MP_SAP_CFG_TSP_S 0
#define REG_CKG_UFS_MP_SAP_CFG_TSP_E 1
#define REG_CKG_UFS_RX_SYMBOL_TSP 0x3010
#define REG_CKG_UFS_RX_SYMBOL_TSP_S 0
#define REG_CKG_UFS_RX_SYMBOL_TSP_E 2
#define REG_CKG_UFS_TX_SYMBOL_TSP 0x3014
#define REG_CKG_UFS_TX_SYMBOL_TSP_S 0
#define REG_CKG_UFS_TX_SYMBOL_TSP_E 2
#define REG_CKG_UFS_UNIPRO_CG_SYN 0x3018
#define REG_CKG_UFS_UNIPRO_CG_SYN_S 0
#define REG_CKG_UFS_UNIPRO_CG_SYN_E 3
#define REG_CKG_UFS_UNIPRO_CG_SYN_TSP 0x3018
#define REG_CKG_UFS_UNIPRO_CG_SYN_TSP_S 8
#define REG_CKG_UFS_UNIPRO_CG_SYN_TSP_E 9
#define REG_CKG_SMI_AESDMA_SEL 0x3020
#define REG_CKG_SMI_AESDMA_SEL_S 0
#define REG_CKG_SMI_AESDMA_SEL_E 3
#define REG_CKG_SMI_TSP_SEL 0x3028
#define REG_CKG_SMI_TSP_SEL_S 0
#define REG_CKG_SMI_TSP_SEL_E 3
#define REG_CKG_SMI_SSUSB_SEL 0x3028
#define REG_CKG_SMI_SSUSB_SEL_S 8
#define REG_CKG_SMI_SSUSB_SEL_E 9
#define REG_CKG_SMI_UFS_SEL 0x3028
#define REG_CKG_SMI_UFS_SEL_S 10
#define REG_CKG_SMI_UFS_SEL_E 11
#define REG_CKG_MCU_NONPM 0x3040
#define REG_CKG_MCU_NONPM_S 0
#define REG_CKG_MCU_NONPM_E 4
#define REG_CKG_MCU_NONPM_DEMOD0 0x3040
#define REG_CKG_MCU_NONPM_DEMOD0_S 8
#define REG_CKG_MCU_NONPM_DEMOD0_E 9
#define REG_CKG_MCU_NONPM_FRCIOPMRV55 0x3040
#define REG_CKG_MCU_NONPM_FRCIOPMRV55_S 10
#define REG_CKG_MCU_NONPM_FRCIOPMRV55_E 11
#define REG_CKG_MCU_NONPM_FRCMEHALO 0x3040
#define REG_CKG_MCU_NONPM_FRCMEHALO_S 12
#define REG_CKG_MCU_NONPM_FRCMEHALO_E 13
#define REG_CKG_MCU_NONPM_PCIE_PHY 0x3040
#define REG_CKG_MCU_NONPM_PCIE_PHY_S 14
#define REG_CKG_MCU_NONPM_PCIE_PHY_E 15
#define REG_CKG_MCU_NONPM_SCACE 0x3048
#define REG_CKG_MCU_NONPM_SCACE_S 0
#define REG_CKG_MCU_NONPM_SCACE_E 1
#define REG_CKG_MCU_NONPM_SCDV 0x3048
#define REG_CKG_MCU_NONPM_SCDV_S 2
#define REG_CKG_MCU_NONPM_SCDV_E 3
#define REG_CKG_MCU_NONPM_SCIP 0x3048
#define REG_CKG_MCU_NONPM_SCIP_S 4
#define REG_CKG_MCU_NONPM_SCIP_E 5
#define REG_CKG_MCU_NONPM_SCMW 0x3048
#define REG_CKG_MCU_NONPM_SCMW_S 6
#define REG_CKG_MCU_NONPM_SCMW_E 7
#define REG_CKG_MCU_NONPM_SCNR 0x3048
#define REG_CKG_MCU_NONPM_SCNR_S 8
#define REG_CKG_MCU_NONPM_SCNR_E 9
#define REG_CKG_MCU_NONPM_SCPQ 0x3048
#define REG_CKG_MCU_NONPM_SCPQ_S 10
#define REG_CKG_MCU_NONPM_SCPQ_E 11
#define REG_CKG_MCU_NONPM_SCSCL 0x3048
#define REG_CKG_MCU_NONPM_SCSCL_S 12
#define REG_CKG_MCU_NONPM_SCSCL_E 13
#define REG_CKG_MCU_NONPM_SCSR 0x3048
#define REG_CKG_MCU_NONPM_SCSR_S 14
#define REG_CKG_MCU_NONPM_SCSR_E 15
#define REG_CKG_MCU_NONPM_SCDISP 0x304c
#define REG_CKG_MCU_NONPM_SCDISP_S 0
#define REG_CKG_MCU_NONPM_SCDISP_E 1
#define REG_CKG_MCU_NONPM_SCTCON 0x3050
#define REG_CKG_MCU_NONPM_SCTCON_S 0
#define REG_CKG_MCU_NONPM_SCTCON_E 1
#define REG_CKG_MCU_NONPM_UFS_PHY 0x3050
#define REG_CKG_MCU_NONPM_UFS_PHY_S 2
#define REG_CKG_MCU_NONPM_UFS_PHY_E 3
#define REG_CKG_MCU_NONPM_USB_PHY 0x3050
#define REG_CKG_MCU_NONPM_USB_PHY_S 4
#define REG_CKG_MCU_NONPM_USB_PHY_E 5
#define REG_CKG_XIU_VDEC_SOC 0x3050
#define REG_CKG_XIU_VDEC_SOC_S 6
#define REG_CKG_XIU_VDEC_SOC_E 7
#define REG_CKG_MCU_NONPM_AIA 0x3050
#define REG_CKG_MCU_NONPM_AIA_S 8
#define REG_CKG_MCU_NONPM_AIA_E 9
#define REG_CKG_MCU_NONPM_MHEG5 0x3050
#define REG_CKG_MCU_NONPM_MHEG5_S 10
#define REG_CKG_MCU_NONPM_MHEG5_E 11
#define REG_CKG_MCU_NONPM_GPU_DIE 0x3050
#define REG_CKG_MCU_NONPM_GPU_DIE_S 12
#define REG_CKG_MCU_NONPM_GPU_DIE_E 13
#define REG_CKG_MCU_NONPM_GPU_NODIE 0x3050
#define REG_CKG_MCU_NONPM_GPU_NODIE_S 14
#define REG_CKG_MCU_NONPM_GPU_NODIE_E 15
#define REG_CKG_MCU_NONPM_RV55FRC 0x3054
#define REG_CKG_MCU_NONPM_RV55FRC_S 0
#define REG_CKG_MCU_NONPM_RV55FRC_E 1
#define REG_CKG_MCU_NONPM_RV55PQU 0x3054
#define REG_CKG_MCU_NONPM_RV55PQU_S 2
#define REG_CKG_MCU_NONPM_RV55PQU_E 3
#define REG_CKG_MCU_NONPM_HDMIRX 0x3058
#define REG_CKG_MCU_NONPM_HDMIRX_S 0
#define REG_CKG_MCU_NONPM_HDMIRX_E 1
#define REG_CKG_MCU_NONPM_IP_WRAP 0x3058
#define REG_CKG_MCU_NONPM_IP_WRAP_S 2
#define REG_CKG_MCU_NONPM_IP_WRAP_E 3
#define REG_CKG_MCU_NONPM_VIVA 0x3058
#define REG_CKG_MCU_NONPM_VIVA_S 4
#define REG_CKG_MCU_NONPM_VIVA_E 5
#define REG_CKG_MCU_NONPM_TSP 0x3058
#define REG_CKG_MCU_NONPM_TSP_S 6
#define REG_CKG_MCU_NONPM_TSP_E 7
#define REG_CKG_PEXTP_AHB_APB_TSP 0x3058
#define REG_CKG_PEXTP_AHB_APB_TSP_S 8
#define REG_CKG_PEXTP_AHB_APB_TSP_E 9
#define REG_CKG_MCU_AU 0x30e0
#define REG_CKG_MCU_AU_S 0
#define REG_CKG_MCU_AU_E 4
#define REG_CKG_VIVA_AU_MCU 0x30e0
#define REG_CKG_VIVA_AU_MCU_S 10
#define REG_CKG_VIVA_AU_MCU_E 12
#define REG_CKG_MCU_CODEC 0x30f8
#define REG_CKG_MCU_CODEC_S 0
#define REG_CKG_MCU_CODEC_E 4
#define REG_CKG_MCU_DMD 0x3110
#define REG_CKG_MCU_DMD_S 0
#define REG_CKG_MCU_DMD_E 4
#define REG_CKG_MCU_DMD_DEMOD0 0x3110
#define REG_CKG_MCU_DMD_DEMOD0_S 8
#define REG_CKG_MCU_DMD_DEMOD0_E 9
#define REG_CKG_MCU_FRC 0x3128
#define REG_CKG_MCU_FRC_S 0
#define REG_CKG_MCU_FRC_E 4
#define REG_CKG_MCU_FRC_FRCIOPMRV55 0x3128
#define REG_CKG_MCU_FRC_FRCIOPMRV55_S 8
#define REG_CKG_MCU_FRC_FRCIOPMRV55_E 9
#define REG_CKG_MCU_FRC_RV55FRC 0x3128
#define REG_CKG_MCU_FRC_RV55FRC_S 10
#define REG_CKG_MCU_FRC_RV55FRC_E 11
#define REG_CKG_MCU_FRC_RV55PQU 0x3128
#define REG_CKG_MCU_FRC_RV55PQU_S 12
#define REG_CKG_MCU_FRC_RV55PQU_E 13
#define REG_CKG_MCU_HDMI 0x3140
#define REG_CKG_MCU_HDMI_S 0
#define REG_CKG_MCU_HDMI_E 4
#define REG_CKG_MCU_HDMI_HDMIRX 0x3140
#define REG_CKG_MCU_HDMI_HDMIRX_S 10
#define REG_CKG_MCU_HDMI_HDMIRX_E 12
#define REG_CKG_MCU_SC 0x3170
#define REG_CKG_MCU_SC_S 0
#define REG_CKG_MCU_SC_E 4
#define REG_CKG_MCU_XC_SCACE 0x3170
#define REG_CKG_MCU_XC_SCACE_S 10
#define REG_CKG_MCU_XC_SCACE_E 11
#define REG_CKG_MCU_XC_SCDV 0x3170
#define REG_CKG_MCU_XC_SCDV_S 12
#define REG_CKG_MCU_XC_SCDV_E 13
#define REG_CKG_MCU_XC_SCIP 0x3170
#define REG_CKG_MCU_XC_SCIP_S 14
#define REG_CKG_MCU_XC_SCIP_E 15
#define REG_CKG_MCU_XC_SCMW 0x3178
#define REG_CKG_MCU_XC_SCMW_S 0
#define REG_CKG_MCU_XC_SCMW_E 1
#define REG_CKG_MCU_XC_SCNR 0x3178
#define REG_CKG_MCU_XC_SCNR_S 2
#define REG_CKG_MCU_XC_SCNR_E 3
#define REG_CKG_MCU_XC_SCPQ 0x3178
#define REG_CKG_MCU_XC_SCPQ_S 4
#define REG_CKG_MCU_XC_SCPQ_E 5
#define REG_CKG_MCU_XC_SCSCL 0x3178
#define REG_CKG_MCU_XC_SCSCL_S 6
#define REG_CKG_MCU_XC_SCSCL_E 7
#define REG_CKG_MCU_XC_SCSR 0x3178
#define REG_CKG_MCU_XC_SCSR_S 8
#define REG_CKG_MCU_XC_SCSR_E 9
#define REG_CKG_MCU_XC_SCTCON 0x3178
#define REG_CKG_MCU_XC_SCTCON_S 10
#define REG_CKG_MCU_XC_SCTCON_E 11
#define REG_CKG_MCU_XC_SCDISP 0x3178
#define REG_CKG_MCU_XC_SCDISP_S 12
#define REG_CKG_MCU_XC_SCDISP_E 13
#define REG_CKG_MCU_VD 0x31a0
#define REG_CKG_MCU_VD_S 0
#define REG_CKG_MCU_VD_E 4
#define REG_CKG_MCU_VD_MHEG5 0x31a0
#define REG_CKG_MCU_VD_MHEG5_S 10
#define REG_CKG_MCU_VD_MHEG5_E 11
#define REG_CKG_MCU_BUS 0x31b8
#define REG_CKG_MCU_BUS_S 0
#define REG_CKG_MCU_BUS_E 4
#define REG_CKG_MCU_BUS_FRCIOPMRV55 0x31b8
#define REG_CKG_MCU_BUS_FRCIOPMRV55_S 8
#define REG_CKG_MCU_BUS_FRCIOPMRV55_E 9
#define REG_CKG_MCU_BUS_SCSCL 0x31b8
#define REG_CKG_MCU_BUS_SCSCL_S 10
#define REG_CKG_MCU_BUS_SCSCL_E 11
#define REG_CKG_AU_MCU_BUS 0x31b8
#define REG_CKG_AU_MCU_BUS_S 12
#define REG_CKG_AU_MCU_BUS_E 14
#define REG_CKG_MCU_BUS_DEMOD0 0x31c0
#define REG_CKG_MCU_BUS_DEMOD0_S 0
#define REG_CKG_MCU_BUS_DEMOD0_E 1
#define REG_CKG_MCU_BUS_HDMIRX 0x31c0
#define REG_CKG_MCU_BUS_HDMIRX_S 2
#define REG_CKG_MCU_BUS_HDMIRX_E 3
#define REG_CKG_MCU_BUS_MHEG5 0x31c0
#define REG_CKG_MCU_BUS_MHEG5_S 4
#define REG_CKG_MCU_BUS_MHEG5_E 5
#define REG_CKG_MCU_BUS_RV55FRC 0x31c0
#define REG_CKG_MCU_BUS_RV55FRC_S 6
#define REG_CKG_MCU_BUS_RV55FRC_E 7
#define REG_CKG_MCU_BUS_RV55PQU 0x31c0
#define REG_CKG_MCU_BUS_RV55PQU_S 8
#define REG_CKG_MCU_BUS_RV55PQU_E 9
#define REG_CKG_MIIC0 0x31f0
#define REG_CKG_MIIC0_S 0
#define REG_CKG_MIIC0_E 3
#define REG_CKG_MIIC0_MHEG5 0x31f0
#define REG_CKG_MIIC0_MHEG5_S 8
#define REG_CKG_MIIC0_MHEG5_E 9
#define REG_CKG_MIIC1 0x31f8
#define REG_CKG_MIIC1_S 0
#define REG_CKG_MIIC1_E 3
#define REG_CKG_MIIC1_MHEG5 0x31f8
#define REG_CKG_MIIC1_MHEG5_S 8
#define REG_CKG_MIIC1_MHEG5_E 9
#define REG_CKG_MIIC2 0x3200
#define REG_CKG_MIIC2_S 0
#define REG_CKG_MIIC2_E 3
#define REG_CKG_MIIC2_MHEG5 0x3200
#define REG_CKG_MIIC2_MHEG5_S 8
#define REG_CKG_MIIC2_MHEG5_E 9
#define REG_CKG_MIIC3 0x3208
#define REG_CKG_MIIC3_S 0
#define REG_CKG_MIIC3_E 3
#define REG_CKG_MIIC3_MHEG5 0x3208
#define REG_CKG_MIIC3_MHEG5_S 8
#define REG_CKG_MIIC3_MHEG5_E 9
#define REG_CKG_MSPI_CILINK 0x3230
#define REG_CKG_MSPI_CILINK_S 0
#define REG_CKG_MSPI_CILINK_E 2
#define REG_CKG_MSPI_CILINK_MHEG5 0x3230
#define REG_CKG_MSPI_CILINK_MHEG5_S 8
#define REG_CKG_MSPI_CILINK_MHEG5_E 9
#define REG_CKG_MSPI_CILINK_DIV 0x3238
#define REG_CKG_MSPI_CILINK_DIV_S 0
#define REG_CKG_MSPI_CILINK_DIV_E 4
#define REG_CKG_MSPI0 0x3240
#define REG_CKG_MSPI0_S 0
#define REG_CKG_MSPI0_E 2
#define REG_CKG_MSPI0_MHEG5 0x3240
#define REG_CKG_MSPI0_MHEG5_S 8
#define REG_CKG_MSPI0_MHEG5_E 9
#define REG_CKG_MSPI0_DIV 0x3248
#define REG_CKG_MSPI0_DIV_S 0
#define REG_CKG_MSPI0_DIV_E 4
#define REG_CKG_MSPI1 0x3250
#define REG_CKG_MSPI1_S 0
#define REG_CKG_MSPI1_E 2
#define REG_CKG_MSPI1_MHEG5 0x3250
#define REG_CKG_MSPI1_MHEG5_S 8
#define REG_CKG_MSPI1_MHEG5_E 9
#define REG_CKG_MSPI1_DIV 0x3258
#define REG_CKG_MSPI1_DIV_S 0
#define REG_CKG_MSPI1_DIV_E 4
#define REG_CKG_MSPI2 0x3260
#define REG_CKG_MSPI2_S 0
#define REG_CKG_MSPI2_E 2
#define REG_CKG_MSPI2_MHEG5 0x3260
#define REG_CKG_MSPI2_MHEG5_S 8
#define REG_CKG_MSPI2_MHEG5_E 9
#define REG_CKG_MSPI2_DIV 0x3268
#define REG_CKG_MSPI2_DIV_S 0
#define REG_CKG_MSPI2_DIV_E 4
#define REG_CKG_MSPI3 0x3270
#define REG_CKG_MSPI3_S 0
#define REG_CKG_MSPI3_E 2
#define REG_CKG_MSPI3_MHEG5 0x3270
#define REG_CKG_MSPI3_MHEG5_S 8
#define REG_CKG_MSPI3_MHEG5_E 9
#define REG_CKG_MSPI3_DIV 0x3278
#define REG_CKG_MSPI3_DIV_S 0
#define REG_CKG_MSPI3_DIV_E 4
#define REG_CKG_MSPI4 0x3280
#define REG_CKG_MSPI4_S 0
#define REG_CKG_MSPI4_E 2
#define REG_CKG_MSPI4_MHEG5 0x3280
#define REG_CKG_MSPI4_MHEG5_S 8
#define REG_CKG_MSPI4_MHEG5_E 9
#define REG_CKG_MSPI4_DIV 0x3288
#define REG_CKG_MSPI4_DIV_S 0
#define REG_CKG_MSPI4_DIV_E 4
#define REG_CKG_MSPI5 0x3290
#define REG_CKG_MSPI5_S 0
#define REG_CKG_MSPI5_E 2
#define REG_CKG_MSPI5_MHEG5 0x3290
#define REG_CKG_MSPI5_MHEG5_S 8
#define REG_CKG_MSPI5_MHEG5_E 9
#define REG_CKG_MSPI5_DIV 0x3298
#define REG_CKG_MSPI5_DIV_S 0
#define REG_CKG_MSPI5_DIV_E 4
#define REG_CKG_MSPI6 0x32a0
#define REG_CKG_MSPI6_S 0
#define REG_CKG_MSPI6_E 2
#define REG_CKG_MSPI6_MHEG5 0x32a0
#define REG_CKG_MSPI6_MHEG5_S 8
#define REG_CKG_MSPI6_MHEG5_E 9
#define REG_CKG_MSPI6_DIV 0x32a8
#define REG_CKG_MSPI6_DIV_S 0
#define REG_CKG_MSPI6_DIV_E 4
#define REG_CKG_MSPI7 0x32b0
#define REG_CKG_MSPI7_S 0
#define REG_CKG_MSPI7_E 2
#define REG_CKG_MSPI7_MHEG5 0x32b0
#define REG_CKG_MSPI7_MHEG5_S 8
#define REG_CKG_MSPI7_MHEG5_E 9
#define REG_CKG_MSPI7_DIV 0x32b8
#define REG_CKG_MSPI7_DIV_S 0
#define REG_CKG_MSPI7_DIV_E 4
#define REG_CKG_FRC_MSPI0 0x32c0
#define REG_CKG_FRC_MSPI0_S 0
#define REG_CKG_FRC_MSPI0_E 2
#define REG_CKG_FRC_MSPI0_FRCIOPMRV55 0x32c8
#define REG_CKG_FRC_MSPI0_FRCIOPMRV55_S 0
#define REG_CKG_FRC_MSPI0_FRCIOPMRV55_E 1
#define REG_CKG_FRC_MSPI0_DIV 0x32d0
#define REG_CKG_FRC_MSPI0_DIV_S 0
#define REG_CKG_FRC_MSPI0_DIV_E 4
#define REG_CKG_SPI 0x32e8
#define REG_CKG_SPI_S 0
#define REG_CKG_SPI_E 4
#define REG_CKG_SPI_MHEG5 0x32e8
#define REG_CKG_SPI_MHEG5_S 8
#define REG_CKG_SPI_MHEG5_E 9
#define REG_CKG_UART0 0x3368
#define REG_CKG_UART0_S 0
#define REG_CKG_UART0_E 3
#define REG_CKG_UART0_MHEG5 0x3368
#define REG_CKG_UART0_MHEG5_S 8
#define REG_CKG_UART0_MHEG5_E 9
#define REG_CKG_UART0_SYNTH 0x3370
#define REG_CKG_UART0_SYNTH_S 0
#define REG_CKG_UART0_SYNTH_E 3
#define REG_CKG_UART1 0x3378
#define REG_CKG_UART1_S 0
#define REG_CKG_UART1_E 3
#define REG_CKG_UART1_MHEG5 0x3378
#define REG_CKG_UART1_MHEG5_S 8
#define REG_CKG_UART1_MHEG5_E 9
#define REG_CKG_UART1_SYNTH 0x3380
#define REG_CKG_UART1_SYNTH_S 0
#define REG_CKG_UART1_SYNTH_E 3
#define REG_CKG_UART2 0x3388
#define REG_CKG_UART2_S 0
#define REG_CKG_UART2_E 3
#define REG_CKG_UART2_MHEG5 0x3388
#define REG_CKG_UART2_MHEG5_S 8
#define REG_CKG_UART2_MHEG5_E 9
#define REG_CKG_UART2_SYNTH 0x3390
#define REG_CKG_UART2_SYNTH_S 0
#define REG_CKG_UART2_SYNTH_E 3
#define REG_CKG_FRC_UART0 0x3398
#define REG_CKG_FRC_UART0_S 0
#define REG_CKG_FRC_UART0_E 3
#define REG_CKG_FRC_UART0_FRCIOPMRV55 0x3398
#define REG_CKG_FRC_UART0_FRCIOPMRV55_S 8
#define REG_CKG_FRC_UART0_FRCIOPMRV55_E 9
#define REG_CKG_FRC_UART0_SYNTH 0x33a0
#define REG_CKG_FRC_UART0_SYNTH_S 0
#define REG_CKG_FRC_UART0_SYNTH_E 3
#define REG_CKG_FRC_UART1 0x33a8
#define REG_CKG_FRC_UART1_S 0
#define REG_CKG_FRC_UART1_E 3
#define REG_CKG_FRC_UART1_FRCIOPMRV55 0x33a8
#define REG_CKG_FRC_UART1_FRCIOPMRV55_S 8
#define REG_CKG_FRC_UART1_FRCIOPMRV55_E 9
#define REG_CKG_FRC_UART1_SYNTH 0x33b0
#define REG_CKG_FRC_UART1_SYNTH_S 0
#define REG_CKG_FRC_UART1_SYNTH_E 3
#define REG_CKG_FUART0 0x33b8
#define REG_CKG_FUART0_S 0
#define REG_CKG_FUART0_E 3
#define REG_CKG_FUART0_MHEG5 0x33b8
#define REG_CKG_FUART0_MHEG5_S 8
#define REG_CKG_FUART0_MHEG5_E 9
#define REG_CKG_FUART0_SYNTH 0x33c0
#define REG_CKG_FUART0_SYNTH_S 0
#define REG_CKG_FUART0_SYNTH_E 3
#define REG_CKG_AU_UART0 0x33c8
#define REG_CKG_AU_UART0_S 0
#define REG_CKG_AU_UART0_E 3
#define REG_CKG_AU_UART0_VIVA 0x33c8
#define REG_CKG_AU_UART0_VIVA_S 8
#define REG_CKG_AU_UART0_VIVA_E 9
#define REG_CKG_AU_UART0_SYNTH 0x33d0
#define REG_CKG_AU_UART0_SYNTH_S 0
#define REG_CKG_AU_UART0_SYNTH_E 3
#define REG_CKG_FRC_FUART0 0x33d8
#define REG_CKG_FRC_FUART0_S 0
#define REG_CKG_FRC_FUART0_E 3
#define REG_CKG_FRC_FUART0_FRCIOPMRV55 0x33d8
#define REG_CKG_FRC_FUART0_FRCIOPMRV55_S 8
#define REG_CKG_FRC_FUART0_FRCIOPMRV55_E 9
#define REG_CKG_FRC_FUART0_SYNTH 0x33e0
#define REG_CKG_FRC_FUART0_SYNTH_S 0
#define REG_CKG_FRC_FUART0_SYNTH_E 3
#define REG_SW_EN_CLKD_ADC2ADC_TOP_DATA 0x34a8
#define REG_SW_EN_CLKD_ADC2ADC_TOP_DATA_S 0
#define REG_SW_EN_CLKD_ADC2ADC_TOP_DATA_E 0
#define REG_SW_EN_CLKD_ADC2GEMIU2ADC_TOP_DATA 0x34ac
#define REG_SW_EN_CLKD_ADC2GEMIU2ADC_TOP_DATA_S 0
#define REG_SW_EN_CLKD_ADC2GEMIU2ADC_TOP_DATA_E 0
#define REG_SW_EN_CLKD_ADC2SC2ADC_TOP_DATA 0x34b0
#define REG_SW_EN_CLKD_ADC2SC2ADC_TOP_DATA_S 0
#define REG_SW_EN_CLKD_ADC2SC2ADC_TOP_DATA_E 0
#define REG_SW_EN_CLKD_FBLANK2ADC_TOP_DATA 0x34b4
#define REG_SW_EN_CLKD_FBLANK2ADC_TOP_DATA_S 0
#define REG_SW_EN_CLKD_FBLANK2ADC_TOP_DATA_E 0
#define REG_SW_EN_CLKD_VD2ADC_TOP_DATA 0x34b8
#define REG_SW_EN_CLKD_VD2ADC_TOP_DATA_S 0
#define REG_SW_EN_CLKD_VD2ADC_TOP_DATA_E 0
#define REG_SW_EN_CLKFSCX2_VD2ADC_TOP_DATA 0x34bc
#define REG_SW_EN_CLKFSCX2_VD2ADC_TOP_DATA_S 0
#define REG_SW_EN_CLKFSCX2_VD2ADC_TOP_DATA_E 0
#define REG_SW_EN_ADC2ADC 0x34c0
#define REG_SW_EN_ADC2ADC_S 0
#define REG_SW_EN_ADC2ADC_E 0
#define REG_SW_EN_ADC2MIU2ADC 0x34c4
#define REG_SW_EN_ADC2MIU2ADC_S 0
#define REG_SW_EN_ADC2MIU2ADC_E 0
#define REG_SW_EN_ADC2MIUSC2ADC 0x34c8
#define REG_SW_EN_ADC2MIUSC2ADC_S 0
#define REG_SW_EN_ADC2MIUSC2ADC_E 0
#define REG_SW_EN_ADC2SC2ADC 0x34cc
#define REG_SW_EN_ADC2SC2ADC_S 0
#define REG_SW_EN_ADC2SC2ADC_E 0
#define REG_SW_EN_ADCPLL2002ADC 0x34d0
#define REG_SW_EN_ADCPLL2002ADC_S 0
#define REG_SW_EN_ADCPLL2002ADC_E 0
#define REG_SW_EN_ADCPLL4002ADC 0x34d4
#define REG_SW_EN_ADCPLL4002ADC_S 0
#define REG_SW_EN_ADCPLL4002ADC_E 0
#define REG_SW_EN_B_ADC2ADC 0x34d8
#define REG_SW_EN_B_ADC2ADC_S 0
#define REG_SW_EN_B_ADC2ADC_E 0
#define REG_SW_EN_B_INT2ADC 0x34dc
#define REG_SW_EN_B_INT2ADC_S 0
#define REG_SW_EN_B_INT2ADC_E 0
#define REG_SW_EN_CLKPLL2ADC 0x34e0
#define REG_SW_EN_CLKPLL2ADC_S 0
#define REG_SW_EN_CLKPLL2ADC_E 0
#define REG_SW_EN_CVBS_DAC_A_DIGITAL0_MUX2ADC 0x34e4
#define REG_SW_EN_CVBS_DAC_A_DIGITAL0_MUX2ADC_S 0
#define REG_SW_EN_CVBS_DAC_A_DIGITAL0_MUX2ADC_E 0
#define REG_SW_EN_CVBS_DAC_A_DIGITAL02ADC 0x34e8
#define REG_SW_EN_CVBS_DAC_A_DIGITAL02ADC_S 0
#define REG_SW_EN_CVBS_DAC_A_DIGITAL02ADC_E 0
#define REG_SW_EN_CVBS_DAC_A_DIGITAL12ADC 0x34ec
#define REG_SW_EN_CVBS_DAC_A_DIGITAL12ADC_S 0
#define REG_SW_EN_CVBS_DAC_A_DIGITAL12ADC_E 0
#define REG_SW_EN_DIG_2162ADC 0x34f0
#define REG_SW_EN_DIG_2162ADC_S 0
#define REG_SW_EN_DIG_2162ADC_E 0
#define REG_SW_EN_FBLANK2ADC 0x34f4
#define REG_SW_EN_FBLANK2ADC_S 0
#define REG_SW_EN_FBLANK2ADC_E 0
#define REG_SW_EN_FSC_VD2ADC 0x34f8
#define REG_SW_EN_FSC_VD2ADC_S 0
#define REG_SW_EN_FSC_VD2ADC_E 0
#define REG_SW_EN_G_ADC2ADC 0x3500
#define REG_SW_EN_G_ADC2ADC_S 0
#define REG_SW_EN_G_ADC2ADC_E 0
#define REG_SW_EN_G_INT2ADC 0x3504
#define REG_SW_EN_G_INT2ADC_S 0
#define REG_SW_EN_G_INT2ADC_E 0
#define REG_SW_EN_ISOG2ADC 0x3508
#define REG_SW_EN_ISOG2ADC_S 0
#define REG_SW_EN_ISOG2ADC_E 0
#define REG_SW_EN_NCO_CLK2ADC 0x3510
#define REG_SW_EN_NCO_CLK2ADC_S 0
#define REG_SW_EN_NCO_CLK2ADC_E 0
#define REG_SW_EN_R_ADC2ADC 0x3518
#define REG_SW_EN_R_ADC2ADC_S 0
#define REG_SW_EN_R_ADC2ADC_E 0
#define REG_SW_EN_R_INT2ADC 0x351c
#define REG_SW_EN_R_INT2ADC_S 0
#define REG_SW_EN_R_INT2ADC_E 0
#define REG_SW_EN_VD_ICLAMP2ADC 0x3520
#define REG_SW_EN_VD_ICLAMP2ADC_S 0
#define REG_SW_EN_VD_ICLAMP2ADC_E 0
#define REG_SW_EN_VD_ICLAMP2VIDEO_ATOP 0x3524
#define REG_SW_EN_VD_ICLAMP2VIDEO_ATOP_S 0
#define REG_SW_EN_VD_ICLAMP2VIDEO_ATOP_E 0
#define REG_SW_EN_VD_NCO_CLK2ADC 0x3528
#define REG_SW_EN_VD_NCO_CLK2ADC_S 0
#define REG_SW_EN_VD_NCO_CLK2ADC_E 0
#define REG_SW_EN_VD2ADC 0x352c
#define REG_SW_EN_VD2ADC_S 0
#define REG_SW_EN_VD2ADC_E 0
#define REG_SW_EN_VDPLL4002ADC 0x3530
#define REG_SW_EN_VDPLL4002ADC_S 0
#define REG_SW_EN_VDPLL4002ADC_E 0
#define REG_SW_EN_XTAL12_4INTERRUPT2ADC 0x3534
#define REG_SW_EN_XTAL12_4INTERRUPT2ADC_S 0
#define REG_SW_EN_XTAL12_4INTERRUPT2ADC_E 0
#define REG_SW_EN_XTAL12_4PLUGDET2ADC 0x3538
#define REG_SW_EN_XTAL12_4PLUGDET2ADC_S 0
#define REG_SW_EN_XTAL12_4PLUGDET2ADC_E 0
#define REG_SW_EN_XTAL122ADC 0x353c
#define REG_SW_EN_XTAL122ADC_S 0
#define REG_SW_EN_XTAL122ADC_E 0
#define REG_SW_EN_XTAL242ADC 0x3540
#define REG_SW_EN_XTAL242ADC_S 0
#define REG_SW_EN_XTAL242ADC_E 0
#define REG_SW_EN_Y_ADC2ADC 0x3544
#define REG_SW_EN_Y_ADC2ADC_S 0
#define REG_SW_EN_Y_ADC2ADC_E 0
#define REG_SW_EN_Y_INT2ADC 0x3548
#define REG_SW_EN_Y_INT2ADC_S 0
#define REG_SW_EN_Y_INT2ADC_E 0
#define REG_SW_EN_YUV_ADC2ADC 0x354c
#define REG_SW_EN_YUV_ADC2ADC_S 0
#define REG_SW_EN_YUV_ADC2ADC_E 0
#define REG_SW_EN_ADCPLB_MPLL2ADC 0x3550
#define REG_SW_EN_ADCPLB_MPLL2ADC_S 0
#define REG_SW_EN_ADCPLB_MPLL2ADC_E 0
#define REG_SW_EN_DISP_MFDEC2GPU_NODIE 0x3564
#define REG_SW_EN_DISP_MFDEC2GPU_NODIE_S 0
#define REG_SW_EN_DISP_MFDEC2GPU_NODIE_E 0
#define REG_SW_EN_DISP_MFDEC2SCNR 0x3564
#define REG_SW_EN_DISP_MFDEC2SCNR_S 1
#define REG_SW_EN_DISP_MFDEC2SCNR_E 1
#define REG_SW_EN_DAP2FRCIOPM 0x3570
#define REG_SW_EN_DAP2FRCIOPM_S 0
#define REG_SW_EN_DAP2FRCIOPM_E 0
#define REG_SW_EN_DAP2FRCIOPMRV55 0x3570
#define REG_SW_EN_DAP2FRCIOPMRV55_S 1
#define REG_SW_EN_DAP2FRCIOPMRV55_E 1
#define REG_SW_EN_DAP2RV55FRC 0x3570
#define REG_SW_EN_DAP2RV55FRC_S 3
#define REG_SW_EN_DAP2RV55FRC_E 3
#define REG_SW_EN_DAP2RV55PQU 0x3570
#define REG_SW_EN_DAP2RV55PQU_S 4
#define REG_SW_EN_DAP2RV55PQU_E 4
#define REG_SW_EN_FRC_FCLK_2X2DEFLICKER 0x3578
#define REG_SW_EN_FRC_FCLK_2X2DEFLICKER_S 0
#define REG_SW_EN_FRC_FCLK_2X2DEFLICKER_E 0
#define REG_SW_EN_FRC_FCLK_2X2FDCLK_2X 0x3578
#define REG_SW_EN_FRC_FCLK_2X2FDCLK_2X_S 1
#define REG_SW_EN_FRC_FCLK_2X2FDCLK_2X_E 1
#define REG_SW_EN_FRC_FCLK_2X2FRCIOPM 0x3578
#define REG_SW_EN_FRC_FCLK_2X2FRCIOPM_S 2
#define REG_SW_EN_FRC_FCLK_2X2FRCIOPM_E 2
#define REG_SW_EN_FRC_FCLK_2X2FRCIOPMRV55 0x3578
#define REG_SW_EN_FRC_FCLK_2X2FRCIOPMRV55_S 3
#define REG_SW_EN_FRC_FCLK_2X2FRCIOPMRV55_E 3
#define REG_SW_EN_FRC_FCLK_2X2MI_PH3 0x3578
#define REG_SW_EN_FRC_FCLK_2X2MI_PH3_S 4
#define REG_SW_EN_FRC_FCLK_2X2MI_PH3_E 4
#define REG_SW_EN_FRC_FCLK_2X2MI_PH4 0x3578
#define REG_SW_EN_FRC_FCLK_2X2MI_PH4_S 5
#define REG_SW_EN_FRC_FCLK_2X2MI_PH4_E 5
#define REG_SW_EN_FRC_FCLK_2X2OUT_STAGE 0x3578
#define REG_SW_EN_FRC_FCLK_2X2OUT_STAGE_S 6
#define REG_SW_EN_FRC_FCLK_2X2OUT_STAGE_E 6
#define REG_SW_EN_FRC_FCLK_2X2SNR 0x3578
#define REG_SW_EN_FRC_FCLK_2X2SNR_S 8
#define REG_SW_EN_FRC_FCLK_2X2SNR_E 8
#define REG_SW_EN_FRC_FCLK_2X2FRCMEHALO 0x3578
#define REG_SW_EN_FRC_FCLK_2X2FRCMEHALO_S 9
#define REG_SW_EN_FRC_FCLK_2X2FRCMEHALO_E 9
#define REG_SW_EN_FRC_FCLK_2XPLUS2FRCIOPMRV55 0x357c
#define REG_SW_EN_FRC_FCLK_2XPLUS2FRCIOPMRV55_S 0
#define REG_SW_EN_FRC_FCLK_2XPLUS2FRCIOPMRV55_E 0
#define REG_SW_EN_FRC_FCLK_2XPLUS2SCIP 0x357c
#define REG_SW_EN_FRC_FCLK_2XPLUS2SCIP_S 1
#define REG_SW_EN_FRC_FCLK_2XPLUS2SCIP_E 1
#define REG_SW_EN_FRC_FCLK_2XPLUS2SCMW 0x357c
#define REG_SW_EN_FRC_FCLK_2XPLUS2SCMW_S 2
#define REG_SW_EN_FRC_FCLK_2XPLUS2SCMW_E 2
#define REG_SW_EN_FRC_FCLK2FDCLK 0x3580
#define REG_SW_EN_FRC_FCLK2FDCLK_S 0
#define REG_SW_EN_FRC_FCLK2FDCLK_E 0
#define REG_SW_EN_FRC_FCLK2FRCIOPM 0x3580
#define REG_SW_EN_FRC_FCLK2FRCIOPM_S 1
#define REG_SW_EN_FRC_FCLK2FRCIOPM_E 1
#define REG_SW_EN_FRC_FCLK2FRCIOPMRV55 0x3580
#define REG_SW_EN_FRC_FCLK2FRCIOPMRV55_S 2
#define REG_SW_EN_FRC_FCLK2FRCIOPMRV55_E 2
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_ALL 0x3580
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_ALL_S 14
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_ALL_E 14
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_L 0x3580
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_L_S 15
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_L_E 15
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_R 0x3584
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_R_S 0
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_R_E 0
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_L 0x3584
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_L_S 1
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_L_E 1
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_R 0x3584
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_R_S 2
#define REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_R_E 2
#define REG_SW_EN_FRC_FCLK2ME 0x3584
#define REG_SW_EN_FRC_FCLK2ME_S 3
#define REG_SW_EN_FRC_FCLK2ME_E 3
#define REG_SW_EN_FRC_FCLK2ME_4X4 0x3584
#define REG_SW_EN_FRC_FCLK2ME_4X4_S 4
#define REG_SW_EN_FRC_FCLK2ME_4X4_E 4
#define REG_SW_EN_FRC_FCLK2ME_PH1 0x3584
#define REG_SW_EN_FRC_FCLK2ME_PH1_S 5
#define REG_SW_EN_FRC_FCLK2ME_PH1_E 5
#define REG_SW_EN_FRC_FCLK2ME_PH2 0x3584
#define REG_SW_EN_FRC_FCLK2ME_PH2_S 6
#define REG_SW_EN_FRC_FCLK2ME_PH2_E 6
#define REG_SW_EN_FRC_FCLK2FRCMEHALO 0x3584
#define REG_SW_EN_FRC_FCLK2FRCMEHALO_S 8
#define REG_SW_EN_FRC_FCLK2FRCMEHALO_E 8
#define REG_SW_EN_RV55FRC_JTAG_TCK2RV55FRC 0x358c
#define REG_SW_EN_RV55FRC_JTAG_TCK2RV55FRC_S 0
#define REG_SW_EN_RV55FRC_JTAG_TCK2RV55FRC_E 0
#define REG_SW_EN_RV55PQU_JTAG_TCK2RV55PQU 0x3590
#define REG_SW_EN_RV55PQU_JTAG_TCK2RV55PQU_S 0
#define REG_SW_EN_RV55PQU_JTAG_TCK2RV55PQU_E 0
#define REG_SW_EN_RV_TCK2RV55FRC 0x3594
#define REG_SW_EN_RV_TCK2RV55FRC_S 0
#define REG_SW_EN_RV_TCK2RV55FRC_E 0
#define REG_SW_EN_RV_TCK2RV55PQU 0x3594
#define REG_SW_EN_RV_TCK2RV55PQU_S 1
#define REG_SW_EN_RV_TCK2RV55PQU_E 1
#define REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPM 0x359c
#define REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPM_S 0
#define REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPM_E 0
#define REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55 0x359c
#define REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55_S 1
#define REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55_E 1
#define REG_SW_EN_RV55FRC2RV55FRC 0x35a4
#define REG_SW_EN_RV55FRC2RV55FRC_S 0
#define REG_SW_EN_RV55FRC2RV55FRC_E 0
#define REG_SW_EN_RV55PQU2RV55PQU 0x35a8
#define REG_SW_EN_RV55PQU2RV55PQU_S 0
#define REG_SW_EN_RV55PQU2RV55PQU_E 0
#define REG_SW_EN_XCSRSPLL_SYN2XCSRSPLL_DMACRO 0x35ac
#define REG_SW_EN_XCSRSPLL_SYN2XCSRSPLL_DMACRO_S 0
#define REG_SW_EN_XCSRSPLL_SYN2XCSRSPLL_DMACRO_E 0
#define REG_SW_EN_XTAL_12M2FRCIOPM 0x35b4
#define REG_SW_EN_XTAL_12M2FRCIOPM_S 0
#define REG_SW_EN_XTAL_12M2FRCIOPM_E 0
#define REG_SW_EN_XTAL_12M2FRCIOPMRV55 0x35b4
#define REG_SW_EN_XTAL_12M2FRCIOPMRV55_S 1
#define REG_SW_EN_XTAL_12M2FRCIOPMRV55_E 1
#define REG_SW_EN_XTAL_12M2RV55FRC 0x35b4
#define REG_SW_EN_XTAL_12M2RV55FRC_S 3
#define REG_SW_EN_XTAL_12M2RV55FRC_E 3
#define REG_SW_EN_XTAL_12M2RV55PQU 0x35b4
#define REG_SW_EN_XTAL_12M2RV55PQU_S 4
#define REG_SW_EN_XTAL_12M2RV55PQU_E 4
#define REG_SW_EN_XTAL_24M2FRCIOPM 0x35c0
#define REG_SW_EN_XTAL_24M2FRCIOPM_S 0
#define REG_SW_EN_XTAL_24M2FRCIOPM_E 0
#define REG_SW_EN_XTAL_24M2FRCIOPMRV55 0x35c0
#define REG_SW_EN_XTAL_24M2FRCIOPMRV55_S 1
#define REG_SW_EN_XTAL_24M2FRCIOPMRV55_E 1
#define REG_SW_EN_XTAL_24M2FRCMEHALO 0x35c0
#define REG_SW_EN_XTAL_24M2FRCMEHALO_S 2
#define REG_SW_EN_XTAL_24M2FRCMEHALO_E 2
#define REG_SW_EN_XTAL_24M2FRCMI 0x35c0
#define REG_SW_EN_XTAL_24M2FRCMI_S 4
#define REG_SW_EN_XTAL_24M2FRCMI_E 4
#define REG_SW_EN_XTAL_24M2RV55FRC 0x35c0
#define REG_SW_EN_XTAL_24M2RV55FRC_S 6
#define REG_SW_EN_XTAL_24M2RV55FRC_E 6
#define REG_SW_EN_XTAL_24M2RV55PQU 0x35c0
#define REG_SW_EN_XTAL_24M2RV55PQU_S 7
#define REG_SW_EN_XTAL_24M2RV55PQU_E 7
#define REG_SW_EN_GE_FIFO_R2GE 0x35cc
#define REG_SW_EN_GE_FIFO_R2GE_S 0
#define REG_SW_EN_GE_FIFO_R2GE_E 0
#define REG_SW_EN_GE_FIFO_W2GE 0x35d0
#define REG_SW_EN_GE_FIFO_W2GE_S 0
#define REG_SW_EN_GE_FIFO_W2GE_E 0
#define REG_SW_EN_GE_PSRAM2GE 0x35d4
#define REG_SW_EN_GE_PSRAM2GE_S 0
#define REG_SW_EN_GE_PSRAM2GE_E 0
#define REG_SW_EN_GE2GE 0x35d8
#define REG_SW_EN_GE2GE_S 0
#define REG_SW_EN_GE2GE_E 0
#define REG_SW_EN_V1_ODCLK2SCDISP 0x35dc
#define REG_SW_EN_V1_ODCLK2SCDISP_S 0
#define REG_SW_EN_V1_ODCLK2SCDISP_E 0
#define REG_SW_EN_CLK_128FS_FB_S02MAC 0x35e4
#define REG_SW_EN_CLK_128FS_FB_S02MAC_S 0
#define REG_SW_EN_CLK_128FS_FB_S02MAC_E 0
#define REG_SW_EN_CLK_128FS_FB_S12MAC 0x35e8
#define REG_SW_EN_CLK_128FS_FB_S12MAC_S 0
#define REG_SW_EN_CLK_128FS_FB_S12MAC_E 0
#define REG_SW_EN_CLK_128FS_S02MAC 0x35ec
#define REG_SW_EN_CLK_128FS_S02MAC_S 0
#define REG_SW_EN_CLK_128FS_S02MAC_E 0
#define REG_SW_EN_CLK_128FS_S12MAC 0x35f0
#define REG_SW_EN_CLK_128FS_S12MAC_S 0
#define REG_SW_EN_CLK_128FS_S12MAC_E 0
#define REG_SW_EN_CLK_2162MAC 0x35f4
#define REG_SW_EN_CLK_2162MAC_S 0
#define REG_SW_EN_CLK_2162MAC_E 0
#define REG_SW_EN_CLK_CTS_SYNTH_S02MAC 0x35f8
#define REG_SW_EN_CLK_CTS_SYNTH_S02MAC_S 0
#define REG_SW_EN_CLK_CTS_SYNTH_S02MAC_E 0
#define REG_SW_EN_CLK_CTS_SYNTH_S12MAC 0x35fc
#define REG_SW_EN_CLK_CTS_SYNTH_S12MAC_S 0
#define REG_SW_EN_CLK_CTS_SYNTH_S12MAC_E 0
#define REG_SW_EN_CLK_DET_INNER_MISC_02MAC 0x3600
#define REG_SW_EN_CLK_DET_INNER_MISC_02MAC_S 0
#define REG_SW_EN_CLK_DET_INNER_MISC_02MAC_E 0
#define REG_SW_EN_CLK_DET_INNER_MISC_12MAC 0x3604
#define REG_SW_EN_CLK_DET_INNER_MISC_12MAC_S 0
#define REG_SW_EN_CLK_DET_INNER_MISC_12MAC_E 0
#define REG_SW_EN_CLK_DSC_ENGINE2DSC 0x3608
#define REG_SW_EN_CLK_DSC_ENGINE2DSC_S 0
#define REG_SW_EN_CLK_DSC_ENGINE2DSC_E 0
#define REG_SW_EN_CLK_DVI2MIU_RD_S02MAC 0x360c
#define REG_SW_EN_CLK_DVI2MIU_RD_S02MAC_S 0
#define REG_SW_EN_CLK_DVI2MIU_RD_S02MAC_E 0
#define REG_SW_EN_CLK_DVI2MIU_RD_S12MAC 0x3610
#define REG_SW_EN_CLK_DVI2MIU_RD_S12MAC_S 0
#define REG_SW_EN_CLK_DVI2MIU_RD_S12MAC_E 0
#define REG_SW_EN_CLK_DVI2MIU_WR_S02MAC 0x3614
#define REG_SW_EN_CLK_DVI2MIU_WR_S02MAC_S 0
#define REG_SW_EN_CLK_DVI2MIU_WR_S02MAC_E 0
#define REG_SW_EN_CLK_DVI2MIU_WR_S12MAC 0x3618
#define REG_SW_EN_CLK_DVI2MIU_WR_S12MAC_S 0
#define REG_SW_EN_CLK_DVI2MIU_WR_S12MAC_E 0
#define REG_SW_EN_CLK_LINK_DSCD2MAC 0x361c
#define REG_SW_EN_CLK_LINK_DSCD2MAC_S 0
#define REG_SW_EN_CLK_LINK_DSCD2MAC_E 0
#define REG_SW_EN_CLK_MPLL_4322MAC 0x3620
#define REG_SW_EN_CLK_MPLL_4322MAC_S 0
#define REG_SW_EN_CLK_MPLL_4322MAC_E 0
#define REG_SW_EN_CLK_MPLL_8642PHY 0x3624
#define REG_SW_EN_CLK_MPLL_8642PHY_S 0
#define REG_SW_EN_CLK_MPLL_8642PHY_E 0
#define REG_SW_EN_CLK_PIX_TMDSPLL_DSCD2MAC 0x3628
#define REG_SW_EN_CLK_PIX_TMDSPLL_DSCD2MAC_S 0
#define REG_SW_EN_CLK_PIX_TMDSPLL_DSCD2MAC_E 0
#define REG_SW_EN_CLK_PIX_XC_S02MAC 0x362c
#define REG_SW_EN_CLK_PIX_XC_S02MAC_S 0
#define REG_SW_EN_CLK_PIX_XC_S02MAC_E 0
#define REG_SW_EN_CLK_PIX_XC_S12MAC 0x3630
#define REG_SW_EN_CLK_PIX_XC_S12MAC_S 0
#define REG_SW_EN_CLK_PIX_XC_S12MAC_E 0
#define REG_SW_EN_CLK_R2_HDMI2MAC 0x3634
#define REG_SW_EN_CLK_R2_HDMI2MAC_S 0
#define REG_SW_EN_CLK_R2_HDMI2MAC_E 0
#define REG_SW_EN_CLK_TIMING_DET_DTOP2MAC 0x3638
#define REG_SW_EN_CLK_TIMING_DET_DTOP2MAC_S 0
#define REG_SW_EN_CLK_TIMING_DET_DTOP2MAC_E 0
#define REG_SW_EN_CLK_TMDS_AUDIO_S02MAC 0x363c
#define REG_SW_EN_CLK_TMDS_AUDIO_S02MAC_S 0
#define REG_SW_EN_CLK_TMDS_AUDIO_S02MAC_E 0
#define REG_SW_EN_CLK_TMDS_AUDIO_S12MAC 0x3640
#define REG_SW_EN_CLK_TMDS_AUDIO_S12MAC_S 0
#define REG_SW_EN_CLK_TMDS_AUDIO_S12MAC_E 0
#define REG_SW_EN_CLK_TMDS_DSCD2MAC 0x3644
#define REG_SW_EN_CLK_TMDS_DSCD2MAC_S 0
#define REG_SW_EN_CLK_TMDS_DSCD2MAC_E 0
#define REG_SW_EN_CLK_XTAL_242MAC 0x3648
#define REG_SW_EN_CLK_XTAL_242MAC_S 0
#define REG_SW_EN_CLK_XTAL_242MAC_E 0
#define REG_SW_EN_CLK_XTAL_HDMI_122MAC 0x364c
#define REG_SW_EN_CLK_XTAL_HDMI_122MAC_S 0
#define REG_SW_EN_CLK_XTAL_HDMI_122MAC_E 0
#define REG_SW_EN_EARC_AUDIO2EARC 0x3650
#define REG_SW_EN_EARC_AUDIO2EARC_S 0
#define REG_SW_EN_EARC_AUDIO2EARC_E 0
#define REG_SW_EN_EARC_CM2EARC 0x3654
#define REG_SW_EN_EARC_CM2EARC_S 0
#define REG_SW_EN_EARC_CM2EARC_E 0
#define REG_SW_EN_EARC_DEBOUNCE2EARC 0x3658
#define REG_SW_EN_EARC_DEBOUNCE2EARC_S 0
#define REG_SW_EN_EARC_DEBOUNCE2EARC_E 0
#define REG_SW_EN_EARC_DM_PRBS2EARC 0x365c
#define REG_SW_EN_EARC_DM_PRBS2EARC_S 0
#define REG_SW_EN_EARC_DM_PRBS2EARC_E 0
#define REG_SW_EN_P0_CLK_DET_DEC_MISC_02MAC 0x3664
#define REG_SW_EN_P0_CLK_DET_DEC_MISC_02MAC_S 0
#define REG_SW_EN_P0_CLK_DET_DEC_MISC_02MAC_E 0
#define REG_SW_EN_P0_CLK_DET_DEC_MISC_12MAC 0x3668
#define REG_SW_EN_P0_CLK_DET_DEC_MISC_12MAC_S 0
#define REG_SW_EN_P0_CLK_DET_DEC_MISC_12MAC_E 0
#define REG_SW_EN_P0_CLK_DET_DEP_MISC_02MAC 0x366c
#define REG_SW_EN_P0_CLK_DET_DEP_MISC_02MAC_S 0
#define REG_SW_EN_P0_CLK_DET_DEP_MISC_02MAC_E 0
#define REG_SW_EN_P0_CLK_DET_DEP_MISC_12MAC 0x3670
#define REG_SW_EN_P0_CLK_DET_DEP_MISC_12MAC_S 0
#define REG_SW_EN_P0_CLK_DET_DEP_MISC_12MAC_E 0
#define REG_SW_EN_P0_CLK_LINK2MAC 0x3674
#define REG_SW_EN_P0_CLK_LINK2MAC_S 0
#define REG_SW_EN_P0_CLK_LINK2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_1P2MAC 0x3678
#define REG_SW_EN_P0_CLK_PIX_1P2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_1P2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_8P2MAC 0x367c
#define REG_SW_EN_P0_CLK_PIX_8P2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_8P2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_DC_MUX2MAC 0x3680
#define REG_SW_EN_P0_CLK_PIX_DC_MUX2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_DC_MUX2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_RCV_MUX2MAC 0x3684
#define REG_SW_EN_P0_CLK_PIX_RCV_MUX2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_RCV_MUX2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_REP_1P2MAC 0x3688
#define REG_SW_EN_P0_CLK_PIX_REP_1P2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_REP_1P2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_TMDSPLL2MAC 0x368c
#define REG_SW_EN_P0_CLK_PIX_TMDSPLL2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_TMDSPLL2MAC_E 0
#define REG_SW_EN_P0_CLK_PIX_XC_MUX2MAC 0x3690
#define REG_SW_EN_P0_CLK_PIX_XC_MUX2MAC_S 0
#define REG_SW_EN_P0_CLK_PIX_XC_MUX2MAC_E 0
#define REG_SW_EN_P0_CLK_TIMING_DET_DEC2MAC 0x3694
#define REG_SW_EN_P0_CLK_TIMING_DET_DEC2MAC_S 0
#define REG_SW_EN_P0_CLK_TIMING_DET_DEC2MAC_E 0
#define REG_SW_EN_P0_CLK_TIMING_DET_DEP2MAC 0x3698
#define REG_SW_EN_P0_CLK_TIMING_DET_DEP2MAC_S 0
#define REG_SW_EN_P0_CLK_TIMING_DET_DEP2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_FRL_8P2MAC 0x369c
#define REG_SW_EN_P0_CLK_TMDS_FRL_8P2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_FRL_8P2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_1P2MAC 0x36a0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_1P2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_1P2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_4P2MAC 0x36a4
#define REG_SW_EN_P0_CLK_TMDS_HDCP_4P2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_4P2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_8P2MAC 0x36a8
#define REG_SW_EN_P0_CLK_TMDS_HDCP_8P2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_8P2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_MUX2MAC 0x36ac
#define REG_SW_EN_P0_CLK_TMDS_HDCP_MUX2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDCP_MUX2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_1P2MAC 0x36b0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_1P2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_1P2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_8P2MAC 0x36b4
#define REG_SW_EN_P0_CLK_TMDS_HDMI_8P2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_8P2MAC_E 0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_MUX2MAC 0x36b8
#define REG_SW_EN_P0_CLK_TMDS_HDMI_MUX2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDS_HDMI_MUX2MAC_E 0
#define REG_SW_EN_P1_CLK_DET_DEC_MISC_02MAC 0x36bc
#define REG_SW_EN_P1_CLK_DET_DEC_MISC_02MAC_S 0
#define REG_SW_EN_P1_CLK_DET_DEC_MISC_02MAC_E 0
#define REG_SW_EN_P1_CLK_DET_DEC_MISC_12MAC 0x36c0
#define REG_SW_EN_P1_CLK_DET_DEC_MISC_12MAC_S 0
#define REG_SW_EN_P1_CLK_DET_DEC_MISC_12MAC_E 0
#define REG_SW_EN_P1_CLK_DET_DEP_MISC_02MAC 0x36c4
#define REG_SW_EN_P1_CLK_DET_DEP_MISC_02MAC_S 0
#define REG_SW_EN_P1_CLK_DET_DEP_MISC_02MAC_E 0
#define REG_SW_EN_P1_CLK_DET_DEP_MISC_12MAC 0x36c8
#define REG_SW_EN_P1_CLK_DET_DEP_MISC_12MAC_S 0
#define REG_SW_EN_P1_CLK_DET_DEP_MISC_12MAC_E 0
#define REG_SW_EN_P1_CLK_LINK2MAC 0x36cc
#define REG_SW_EN_P1_CLK_LINK2MAC_S 0
#define REG_SW_EN_P1_CLK_LINK2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_1P2MAC 0x36d0
#define REG_SW_EN_P1_CLK_PIX_1P2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_1P2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_8P2MAC 0x36d4
#define REG_SW_EN_P1_CLK_PIX_8P2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_8P2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_DC_MUX2MAC 0x36d8
#define REG_SW_EN_P1_CLK_PIX_DC_MUX2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_DC_MUX2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_RCV_MUX2MAC 0x36dc
#define REG_SW_EN_P1_CLK_PIX_RCV_MUX2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_RCV_MUX2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_REP_1P2MAC 0x36e0
#define REG_SW_EN_P1_CLK_PIX_REP_1P2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_REP_1P2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_TMDSPLL2MAC 0x36e4
#define REG_SW_EN_P1_CLK_PIX_TMDSPLL2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_TMDSPLL2MAC_E 0
#define REG_SW_EN_P1_CLK_PIX_XC_MUX2MAC 0x36e8
#define REG_SW_EN_P1_CLK_PIX_XC_MUX2MAC_S 0
#define REG_SW_EN_P1_CLK_PIX_XC_MUX2MAC_E 0
#define REG_SW_EN_P1_CLK_TIMING_DET_DEC2MAC 0x36ec
#define REG_SW_EN_P1_CLK_TIMING_DET_DEC2MAC_S 0
#define REG_SW_EN_P1_CLK_TIMING_DET_DEC2MAC_E 0
#define REG_SW_EN_P1_CLK_TIMING_DET_DEP2MAC 0x36f0
#define REG_SW_EN_P1_CLK_TIMING_DET_DEP2MAC_S 0
#define REG_SW_EN_P1_CLK_TIMING_DET_DEP2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_FRL_8P2MAC 0x36f4
#define REG_SW_EN_P1_CLK_TMDS_FRL_8P2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_FRL_8P2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_1P2MAC 0x36f8
#define REG_SW_EN_P1_CLK_TMDS_HDCP_1P2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_1P2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_4P2MAC 0x36fc
#define REG_SW_EN_P1_CLK_TMDS_HDCP_4P2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_4P2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_8P2MAC 0x3700
#define REG_SW_EN_P1_CLK_TMDS_HDCP_8P2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_8P2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_MUX2MAC 0x3704
#define REG_SW_EN_P1_CLK_TMDS_HDCP_MUX2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDCP_MUX2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDMI_1P2MAC 0x3708
#define REG_SW_EN_P1_CLK_TMDS_HDMI_1P2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDMI_1P2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDMI_8P2MAC 0x370c
#define REG_SW_EN_P1_CLK_TMDS_HDMI_8P2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDMI_8P2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDS_HDMI_MUX2MAC 0x3710
#define REG_SW_EN_P1_CLK_TMDS_HDMI_MUX2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDS_HDMI_MUX2MAC_E 0
#define REG_SW_EN_P2_CLK_DET_DEC_MISC_02MAC 0x3714
#define REG_SW_EN_P2_CLK_DET_DEC_MISC_02MAC_S 0
#define REG_SW_EN_P2_CLK_DET_DEC_MISC_02MAC_E 0
#define REG_SW_EN_P2_CLK_DET_DEC_MISC_12MAC 0x3718
#define REG_SW_EN_P2_CLK_DET_DEC_MISC_12MAC_S 0
#define REG_SW_EN_P2_CLK_DET_DEC_MISC_12MAC_E 0
#define REG_SW_EN_P2_CLK_DET_DEP_MISC_02MAC 0x371c
#define REG_SW_EN_P2_CLK_DET_DEP_MISC_02MAC_S 0
#define REG_SW_EN_P2_CLK_DET_DEP_MISC_02MAC_E 0
#define REG_SW_EN_P2_CLK_DET_DEP_MISC_12MAC 0x3720
#define REG_SW_EN_P2_CLK_DET_DEP_MISC_12MAC_S 0
#define REG_SW_EN_P2_CLK_DET_DEP_MISC_12MAC_E 0
#define REG_SW_EN_P2_CLK_LINK2MAC 0x3724
#define REG_SW_EN_P2_CLK_LINK2MAC_S 0
#define REG_SW_EN_P2_CLK_LINK2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_1P2MAC 0x3728
#define REG_SW_EN_P2_CLK_PIX_1P2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_1P2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_8P2MAC 0x372c
#define REG_SW_EN_P2_CLK_PIX_8P2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_8P2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_DC_MUX2MAC 0x3730
#define REG_SW_EN_P2_CLK_PIX_DC_MUX2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_DC_MUX2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_RCV_MUX2MAC 0x3734
#define REG_SW_EN_P2_CLK_PIX_RCV_MUX2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_RCV_MUX2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_REP_1P2MAC 0x3738
#define REG_SW_EN_P2_CLK_PIX_REP_1P2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_REP_1P2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_TMDSPLL2MAC 0x373c
#define REG_SW_EN_P2_CLK_PIX_TMDSPLL2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_TMDSPLL2MAC_E 0
#define REG_SW_EN_P2_CLK_PIX_XC_MUX2MAC 0x3740
#define REG_SW_EN_P2_CLK_PIX_XC_MUX2MAC_S 0
#define REG_SW_EN_P2_CLK_PIX_XC_MUX2MAC_E 0
#define REG_SW_EN_P2_CLK_TIMING_DET_DEC2MAC 0x3744
#define REG_SW_EN_P2_CLK_TIMING_DET_DEC2MAC_S 0
#define REG_SW_EN_P2_CLK_TIMING_DET_DEC2MAC_E 0
#define REG_SW_EN_P2_CLK_TIMING_DET_DEP2MAC 0x3748
#define REG_SW_EN_P2_CLK_TIMING_DET_DEP2MAC_S 0
#define REG_SW_EN_P2_CLK_TIMING_DET_DEP2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_FRL_8P2MAC 0x374c
#define REG_SW_EN_P2_CLK_TMDS_FRL_8P2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_FRL_8P2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_1P2MAC 0x3750
#define REG_SW_EN_P2_CLK_TMDS_HDCP_1P2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_1P2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_4P2MAC 0x3754
#define REG_SW_EN_P2_CLK_TMDS_HDCP_4P2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_4P2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_8P2MAC 0x3758
#define REG_SW_EN_P2_CLK_TMDS_HDCP_8P2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_8P2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_MUX2MAC 0x375c
#define REG_SW_EN_P2_CLK_TMDS_HDCP_MUX2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDCP_MUX2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDMI_1P2MAC 0x3760
#define REG_SW_EN_P2_CLK_TMDS_HDMI_1P2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDMI_1P2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDMI_8P2MAC 0x3764
#define REG_SW_EN_P2_CLK_TMDS_HDMI_8P2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDMI_8P2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDS_HDMI_MUX2MAC 0x3768
#define REG_SW_EN_P2_CLK_TMDS_HDMI_MUX2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDS_HDMI_MUX2MAC_E 0
#define REG_SW_EN_P3_CLK_DET_DEC_MISC_02MAC 0x376c
#define REG_SW_EN_P3_CLK_DET_DEC_MISC_02MAC_S 0
#define REG_SW_EN_P3_CLK_DET_DEC_MISC_02MAC_E 0
#define REG_SW_EN_P3_CLK_DET_DEC_MISC_12MAC 0x3770
#define REG_SW_EN_P3_CLK_DET_DEC_MISC_12MAC_S 0
#define REG_SW_EN_P3_CLK_DET_DEC_MISC_12MAC_E 0
#define REG_SW_EN_P3_CLK_DET_DEP_MISC_02MAC 0x3774
#define REG_SW_EN_P3_CLK_DET_DEP_MISC_02MAC_S 0
#define REG_SW_EN_P3_CLK_DET_DEP_MISC_02MAC_E 0
#define REG_SW_EN_P3_CLK_DET_DEP_MISC_12MAC 0x3778
#define REG_SW_EN_P3_CLK_DET_DEP_MISC_12MAC_S 0
#define REG_SW_EN_P3_CLK_DET_DEP_MISC_12MAC_E 0
#define REG_SW_EN_P3_CLK_LINK2MAC 0x377c
#define REG_SW_EN_P3_CLK_LINK2MAC_S 0
#define REG_SW_EN_P3_CLK_LINK2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_1P2MAC 0x3780
#define REG_SW_EN_P3_CLK_PIX_1P2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_1P2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_8P2MAC 0x3784
#define REG_SW_EN_P3_CLK_PIX_8P2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_8P2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_DC_MUX2MAC 0x3788
#define REG_SW_EN_P3_CLK_PIX_DC_MUX2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_DC_MUX2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_RCV_MUX2MAC 0x378c
#define REG_SW_EN_P3_CLK_PIX_RCV_MUX2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_RCV_MUX2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_REP_1P2MAC 0x3790
#define REG_SW_EN_P3_CLK_PIX_REP_1P2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_REP_1P2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_TMDSPLL2MAC 0x3794
#define REG_SW_EN_P3_CLK_PIX_TMDSPLL2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_TMDSPLL2MAC_E 0
#define REG_SW_EN_P3_CLK_PIX_XC_MUX2MAC 0x3798
#define REG_SW_EN_P3_CLK_PIX_XC_MUX2MAC_S 0
#define REG_SW_EN_P3_CLK_PIX_XC_MUX2MAC_E 0
#define REG_SW_EN_P3_CLK_TIMING_DET_DEC2MAC 0x379c
#define REG_SW_EN_P3_CLK_TIMING_DET_DEC2MAC_S 0
#define REG_SW_EN_P3_CLK_TIMING_DET_DEC2MAC_E 0
#define REG_SW_EN_P3_CLK_TIMING_DET_DEP2MAC 0x37a0
#define REG_SW_EN_P3_CLK_TIMING_DET_DEP2MAC_S 0
#define REG_SW_EN_P3_CLK_TIMING_DET_DEP2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_FRL_8P2MAC 0x37a4
#define REG_SW_EN_P3_CLK_TMDS_FRL_8P2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_FRL_8P2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_1P2MAC 0x37a8
#define REG_SW_EN_P3_CLK_TMDS_HDCP_1P2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_1P2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_4P2MAC 0x37ac
#define REG_SW_EN_P3_CLK_TMDS_HDCP_4P2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_4P2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_8P2MAC 0x37b0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_8P2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_8P2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_MUX2MAC 0x37b4
#define REG_SW_EN_P3_CLK_TMDS_HDCP_MUX2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDCP_MUX2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_1P2MAC 0x37b8
#define REG_SW_EN_P3_CLK_TMDS_HDMI_1P2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_1P2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_8P2MAC 0x37bc
#define REG_SW_EN_P3_CLK_TMDS_HDMI_8P2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_8P2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_MUX2MAC 0x37c0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_MUX2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDS_HDMI_MUX2MAC_E 0
#define REG_SW_EN_XC_LPLL_DIV42SCDISP 0x37c4
#define REG_SW_EN_XC_LPLL_DIV42SCDISP_S 0
#define REG_SW_EN_XC_LPLL_DIV42SCDISP_E 0
#define REG_SW_EN_XC_AFBC2SCTCON 0x37c8
#define REG_SW_EN_XC_AFBC2SCTCON_S 0
#define REG_SW_EN_XC_AFBC2SCTCON_E 0
#define REG_SW_EN_XC_GOP0_DST2SCTCON 0x37cc
#define REG_SW_EN_XC_GOP0_DST2SCTCON_S 0
#define REG_SW_EN_XC_GOP0_DST2SCTCON_E 0
#define REG_SW_EN_XC_GOP_SCL2SCTCON 0x37d0
#define REG_SW_EN_XC_GOP_SCL2SCTCON_S 0
#define REG_SW_EN_XC_GOP_SCL2SCTCON_E 0
#define REG_SW_EN_XC_GOP2SCTCON 0x37d4
#define REG_SW_EN_XC_GOP2SCTCON_S 0
#define REG_SW_EN_XC_GOP2SCTCON_E 0
#define REG_SW_EN_XC_GOPC_DST2SCTCON 0x37d8
#define REG_SW_EN_XC_GOPC_DST2SCTCON_S 0
#define REG_SW_EN_XC_GOPC_DST2SCTCON_E 0
#define REG_SW_EN_XC_GOPG_DST2SCTCON 0x37dc
#define REG_SW_EN_XC_GOPG_DST2SCTCON_S 0
#define REG_SW_EN_XC_GOPG_DST2SCTCON_E 0
#define REG_SW_EN_XC_OD_DELTA2SCTCON 0x37e0
#define REG_SW_EN_XC_OD_DELTA2SCTCON_S 0
#define REG_SW_EN_XC_OD_DELTA2SCTCON_E 0
#define REG_SW_EN_XC_OD_DELTA2SCIP 0x37e0
#define REG_SW_EN_XC_OD_DELTA2SCIP_S 8
#define REG_SW_EN_XC_OD_DELTA2SCIP_E 8
#define REG_SW_EN_XC_OD_DELTA2SCSCL 0x37e0
#define REG_SW_EN_XC_OD_DELTA2SCSCL_S 1
#define REG_SW_EN_XC_OD_DELTA2SCSCL_E 1
#define REG_SW_EN_XC_OD_DIV22SCTCON 0x37e4
#define REG_SW_EN_XC_OD_DIV22SCTCON_S 0
#define REG_SW_EN_XC_OD_DIV22SCTCON_E 0
#define REG_SW_EN_XC_OD_DIV42SCTCON 0x37e8
#define REG_SW_EN_XC_OD_DIV42SCTCON_S 0
#define REG_SW_EN_XC_OD_DIV42SCTCON_E 0
#define REG_SW_EN_XC_OD_DIV22SCDISP 0x37ec
#define REG_SW_EN_XC_OD_DIV22SCDISP_S 0
#define REG_SW_EN_XC_OD_DIV22SCDISP_E 0
#define REG_SW_EN_LPLL_SYN_864_PIPE2FPLL 0x37f0
#define REG_SW_EN_LPLL_SYN_864_PIPE2FPLL_S 0
#define REG_SW_EN_LPLL_SYN_864_PIPE2FPLL_E 0
#define REG_SW_EN_DET_RCLK2DET 0x37f4
#define REG_SW_EN_DET_RCLK2DET_S 0
#define REG_SW_EN_DET_RCLK2DET_E 0
#define REG_SW_EN_DET_WCLK2DET 0x37f8
#define REG_SW_EN_DET_WCLK2DET_S 0
#define REG_SW_EN_DET_WCLK2DET_E 0
#define REG_SW_EN_IDCLK2FPLL 0x37fc
#define REG_SW_EN_IDCLK2FPLL_S 0
#define REG_SW_EN_IDCLK2FPLL_E 0
#define REG_SW_EN_LPLL_ODCLK_NODIV2FPLL 0x3800
#define REG_SW_EN_LPLL_ODCLK_NODIV2FPLL_S 0
#define REG_SW_EN_LPLL_ODCLK_NODIV2FPLL_E 0
#define REG_SW_EN_LPLL_ODCLK_NODIV2TTL 0x3800
#define REG_SW_EN_LPLL_ODCLK_NODIV2TTL_S 1
#define REG_SW_EN_LPLL_ODCLK_NODIV2TTL_E 1
#define REG_SW_EN_LPLL_ODCLK2FPLL 0x3804
#define REG_SW_EN_LPLL_ODCLK2FPLL_S 0
#define REG_SW_EN_LPLL_ODCLK2FPLL_E 0
#define REG_SW_EN_LPLL_SYN_4322FPLL 0x3808
#define REG_SW_EN_LPLL_SYN_4322FPLL_S 0
#define REG_SW_EN_LPLL_SYN_4322FPLL_E 0
#define REG_SW_EN_LPLL_SYN_8642FPLL 0x380c
#define REG_SW_EN_LPLL_SYN_8642FPLL_S 0
#define REG_SW_EN_LPLL_SYN_8642FPLL_E 0
#define REG_SW_EN_MOD_A_ODCLK2MOD_A 0x3810
#define REG_SW_EN_MOD_A_ODCLK2MOD_A_S 0
#define REG_SW_EN_MOD_A_ODCLK2MOD_A_E 0
#define REG_SW_EN_MOD_D_ODCLK2MOD_D 0x3814
#define REG_SW_EN_MOD_D_ODCLK2MOD_D_S 0
#define REG_SW_EN_MOD_D_ODCLK2MOD_D_E 0
#define REG_SW_EN_MOD_D_ODCLK2LVDS 0x3814
#define REG_SW_EN_MOD_D_ODCLK2LVDS_S 1
#define REG_SW_EN_MOD_D_ODCLK2LVDS_E 1
#define REG_SW_EN_MOD_D_ODCLK2TTL 0x3814
#define REG_SW_EN_MOD_D_ODCLK2TTL_S 2
#define REG_SW_EN_MOD_D_ODCLK2TTL_E 2
#define REG_SW_EN_MOD_O_SR_WCLK2O 0x3818
#define REG_SW_EN_MOD_O_SR_WCLK2O_S 0
#define REG_SW_EN_MOD_O_SR_WCLK2O_E 0
#define REG_SW_EN_MOD_O_SR_WCLK2VBY1_O 0x3818
#define REG_SW_EN_MOD_O_SR_WCLK2VBY1_O_S 1
#define REG_SW_EN_MOD_O_SR_WCLK2VBY1_O_E 1
#define REG_SW_EN_MOD_V1_SR_WCLK2V1 0x381c
#define REG_SW_EN_MOD_V1_SR_WCLK2V1_S 0
#define REG_SW_EN_MOD_V1_SR_WCLK2V1_E 0
#define REG_SW_EN_MOD_V1_SR_WCLK2VBY1_V1 0x381c
#define REG_SW_EN_MOD_V1_SR_WCLK2VBY1_V1_S 1
#define REG_SW_EN_MOD_V1_SR_WCLK2VBY1_V1_E 1
#define REG_SW_EN_MOD_V2_SR_WCLK2V2 0x3820
#define REG_SW_EN_MOD_V2_SR_WCLK2V2_S 0
#define REG_SW_EN_MOD_V2_SR_WCLK2V2_E 0
#define REG_SW_EN_MOD_V2_SR_WCLK2VBY1_V2 0x3820
#define REG_SW_EN_MOD_V2_SR_WCLK2VBY1_V2_S 1
#define REG_SW_EN_MOD_V2_SR_WCLK2VBY1_V2_E 1
#define REG_SW_EN_O_MOD_SR_RCLK2O 0x3824
#define REG_SW_EN_O_MOD_SR_RCLK2O_S 0
#define REG_SW_EN_O_MOD_SR_RCLK2O_E 0
#define REG_SW_EN_O_ODCLK_STG12O 0x3828
#define REG_SW_EN_O_ODCLK_STG12O_S 0
#define REG_SW_EN_O_ODCLK_STG12O_E 0
#define REG_SW_EN_O_ODCLK_STG22O 0x382c
#define REG_SW_EN_O_ODCLK_STG22O_S 0
#define REG_SW_EN_O_ODCLK_STG22O_E 0
#define REG_SW_EN_O_ODCLK_STG32O 0x3830
#define REG_SW_EN_O_ODCLK_STG32O_S 0
#define REG_SW_EN_O_ODCLK_STG32O_E 0
#define REG_SW_EN_O_ODCLK_STG42O 0x3834
#define REG_SW_EN_O_ODCLK_STG42O_S 0
#define REG_SW_EN_O_ODCLK_STG42O_E 0
#define REG_SW_EN_O_ODCLK_STG52O 0x3838
#define REG_SW_EN_O_ODCLK_STG52O_S 0
#define REG_SW_EN_O_ODCLK_STG52O_E 0
#define REG_SW_EN_O_ODCLK_STG62O 0x383c
#define REG_SW_EN_O_ODCLK_STG62O_S 0
#define REG_SW_EN_O_ODCLK_STG62O_E 0
#define REG_SW_EN_O_ODCLK2O 0x3840
#define REG_SW_EN_O_ODCLK2O_S 0
#define REG_SW_EN_O_ODCLK2O_E 0
#define REG_SW_EN_PWM2PWM 0x3844
#define REG_SW_EN_PWM2PWM_S 0
#define REG_SW_EN_PWM2PWM_E 0
#define REG_SW_EN_V1_MOD_SR_RCLK2V1 0x3848
#define REG_SW_EN_V1_MOD_SR_RCLK2V1_S 0
#define REG_SW_EN_V1_MOD_SR_RCLK2V1_E 0
#define REG_SW_EN_V1_ODCLK_STG12V1 0x384c
#define REG_SW_EN_V1_ODCLK_STG12V1_S 0
#define REG_SW_EN_V1_ODCLK_STG12V1_E 0
#define REG_SW_EN_V1_ODCLK_STG22V1 0x3850
#define REG_SW_EN_V1_ODCLK_STG22V1_S 0
#define REG_SW_EN_V1_ODCLK_STG22V1_E 0
#define REG_SW_EN_V1_ODCLK_STG32V1 0x3854
#define REG_SW_EN_V1_ODCLK_STG32V1_S 0
#define REG_SW_EN_V1_ODCLK_STG32V1_E 0
#define REG_SW_EN_V1_ODCLK_STG42V1 0x3858
#define REG_SW_EN_V1_ODCLK_STG42V1_S 0
#define REG_SW_EN_V1_ODCLK_STG42V1_E 0
#define REG_SW_EN_V1_ODCLK_STG52V1 0x385c
#define REG_SW_EN_V1_ODCLK_STG52V1_S 0
#define REG_SW_EN_V1_ODCLK_STG52V1_E 0
#define REG_SW_EN_V1_ODCLK_STG62V1 0x3860
#define REG_SW_EN_V1_ODCLK_STG62V1_S 0
#define REG_SW_EN_V1_ODCLK_STG62V1_E 0
#define REG_SW_EN_V1_ODCLK_STG72V1 0x3864
#define REG_SW_EN_V1_ODCLK_STG72V1_S 0
#define REG_SW_EN_V1_ODCLK_STG72V1_E 0
#define REG_SW_EN_V1_ODCLK_STG82V1 0x3868
#define REG_SW_EN_V1_ODCLK_STG82V1_S 0
#define REG_SW_EN_V1_ODCLK_STG82V1_E 0
#define REG_SW_EN_V1_ODCLK2V1 0x386c
#define REG_SW_EN_V1_ODCLK2V1_S 0
#define REG_SW_EN_V1_ODCLK2V1_E 0
#define REG_SW_EN_V2_MOD_SR_RCLK2V2 0x3870
#define REG_SW_EN_V2_MOD_SR_RCLK2V2_S 0
#define REG_SW_EN_V2_MOD_SR_RCLK2V2_E 0
#define REG_SW_EN_V2_ODCLK_STG12V2 0x3874
#define REG_SW_EN_V2_ODCLK_STG12V2_S 0
#define REG_SW_EN_V2_ODCLK_STG12V2_E 0
#define REG_SW_EN_V2_ODCLK_STG22V2 0x3878
#define REG_SW_EN_V2_ODCLK_STG22V2_S 0
#define REG_SW_EN_V2_ODCLK_STG22V2_E 0
#define REG_SW_EN_V2_ODCLK_STG32V2 0x387c
#define REG_SW_EN_V2_ODCLK_STG32V2_S 0
#define REG_SW_EN_V2_ODCLK_STG32V2_E 0
#define REG_SW_EN_V2_ODCLK_STG42V2 0x3880
#define REG_SW_EN_V2_ODCLK_STG42V2_S 0
#define REG_SW_EN_V2_ODCLK_STG42V2_E 0
#define REG_SW_EN_V2_ODCLK_STG52V2 0x3884
#define REG_SW_EN_V2_ODCLK_STG52V2_S 0
#define REG_SW_EN_V2_ODCLK_STG52V2_E 0
#define REG_SW_EN_V2_ODCLK_STG62V2 0x3888
#define REG_SW_EN_V2_ODCLK_STG62V2_S 0
#define REG_SW_EN_V2_ODCLK_STG62V2_E 0
#define REG_SW_EN_V2_ODCLK_STG72V2 0x388c
#define REG_SW_EN_V2_ODCLK_STG72V2_S 0
#define REG_SW_EN_V2_ODCLK_STG72V2_E 0
#define REG_SW_EN_V2_ODCLK2V2 0x3890
#define REG_SW_EN_V2_ODCLK2V2_S 0
#define REG_SW_EN_V2_ODCLK2V2_E 0
#define REG_SW_EN_XTAL_12M2MOD_A 0x3894
#define REG_SW_EN_XTAL_12M2MOD_A_S 0
#define REG_SW_EN_XTAL_12M2MOD_A_E 0
#define REG_SW_EN_XTAL_12M2PWM 0x3894
#define REG_SW_EN_XTAL_12M2PWM_S 1
#define REG_SW_EN_XTAL_12M2PWM_E 1
#define REG_SW_EN_XTAL_24M2FPLL 0x3898
#define REG_SW_EN_XTAL_24M2FPLL_S 0
#define REG_SW_EN_XTAL_24M2FPLL_E 0
#define REG_SW_EN_O_MOD_SR_RCLK_FINIAL2O 0x389c
#define REG_SW_EN_O_MOD_SR_RCLK_FINIAL2O_S 0
#define REG_SW_EN_O_MOD_SR_RCLK_FINIAL2O_E 0
#define REG_SW_EN_O_MOD_SR_RCLK_PRE02O 0x38a0
#define REG_SW_EN_O_MOD_SR_RCLK_PRE02O_S 0
#define REG_SW_EN_O_MOD_SR_RCLK_PRE02O_E 0
#define REG_SW_EN_O_MOD_SR_RCLK_PRE12O 0x38a4
#define REG_SW_EN_O_MOD_SR_RCLK_PRE12O_S 0
#define REG_SW_EN_O_MOD_SR_RCLK_PRE12O_E 0
#define REG_SW_EN_V1_MOD_SR_RCLK_FINIAL2V1 0x38a8
#define REG_SW_EN_V1_MOD_SR_RCLK_FINIAL2V1_S 0
#define REG_SW_EN_V1_MOD_SR_RCLK_FINIAL2V1_E 0
#define REG_SW_EN_V1_MOD_SR_RCLK_PRE02V1 0x38ac
#define REG_SW_EN_V1_MOD_SR_RCLK_PRE02V1_S 0
#define REG_SW_EN_V1_MOD_SR_RCLK_PRE02V1_E 0
#define REG_SW_EN_V1_MOD_SR_RCLK_PRE12V1 0x38b0
#define REG_SW_EN_V1_MOD_SR_RCLK_PRE12V1_S 0
#define REG_SW_EN_V1_MOD_SR_RCLK_PRE12V1_E 0
#define REG_SW_EN_V2_MOD_SR_RCLK_FINIAL2V2 0x38b4
#define REG_SW_EN_V2_MOD_SR_RCLK_FINIAL2V2_S 0
#define REG_SW_EN_V2_MOD_SR_RCLK_FINIAL2V2_E 0
#define REG_SW_EN_V2_MOD_SR_RCLK_PRE02V2 0x38b8
#define REG_SW_EN_V2_MOD_SR_RCLK_PRE02V2_S 0
#define REG_SW_EN_V2_MOD_SR_RCLK_PRE02V2_E 0
#define REG_SW_EN_V2_MOD_SR_RCLK_PRE12V2 0x38bc
#define REG_SW_EN_V2_MOD_SR_RCLK_PRE12V2_S 0
#define REG_SW_EN_V2_MOD_SR_RCLK_PRE12V2_E 0
#define REG_SW_EN_V1_ODCLK_STG92V1 0x38c0
#define REG_SW_EN_V1_ODCLK_STG92V1_S 0
#define REG_SW_EN_V1_ODCLK_STG92V1_E 0
#define REG_SW_EN_PQ_GA_SRAM2SCDISP 0x38c4
#define REG_SW_EN_PQ_GA_SRAM2SCDISP_S 0
#define REG_SW_EN_PQ_GA_SRAM2SCDISP_E 0
#define REG_SW_EN_AISR_HVSP_SRAM2SCSR 0x38c8
#define REG_SW_EN_AISR_HVSP_SRAM2SCSR_S 0
#define REG_SW_EN_AISR_HVSP_SRAM2SCSR_E 0
#define REG_SW_EN_XC_FS2SCTCON 0x38cc
#define REG_SW_EN_XC_FS2SCTCON_S 0
#define REG_SW_EN_XC_FS2SCTCON_E 0
#define REG_SW_EN_XC_OD_OSD2SCTCON 0x38d0
#define REG_SW_EN_XC_OD_OSD2SCTCON_S 0
#define REG_SW_EN_XC_OD_OSD2SCTCON_E 0
#define REG_SW_EN_AISR_SRAM2SCSR 0x38d4
#define REG_SW_EN_AISR_SRAM2SCSR_S 0
#define REG_SW_EN_AISR_SRAM2SCSR_E 0
#define REG_SW_EN_AISR_SRAM_PH_12SCSR 0x38d4
#define REG_SW_EN_AISR_SRAM_PH_12SCSR_S 1
#define REG_SW_EN_AISR_SRAM_PH_12SCSR_E 1
#define REG_SW_EN_DC0_SRAM2SCIP 0x38d8
#define REG_SW_EN_DC0_SRAM2SCIP_S 0
#define REG_SW_EN_DC0_SRAM2SCIP_E 0
#define REG_SW_EN_DBK_HW_SRAM2SCPQ 0x38dc
#define REG_SW_EN_DBK_HW_SRAM2SCPQ_S 0
#define REG_SW_EN_DBK_HW_SRAM2SCPQ_E 0
#define REG_SW_EN_DELTA_B2P_SRAM2SCSCL 0x38e0
#define REG_SW_EN_DELTA_B2P_SRAM2SCSCL_S 0
#define REG_SW_EN_DELTA_B2P_SRAM2SCSCL_E 0
#define REG_SW_EN_DELTA_B2P2_SRAM2SCACE 0x38e4
#define REG_SW_EN_DELTA_B2P2_SRAM2SCACE_S 0
#define REG_SW_EN_DELTA_B2P2_SRAM2SCACE_E 0
#define REG_SW_EN_DEMURA_SRAM2SCTCON 0x38e8
#define REG_SW_EN_DEMURA_SRAM2SCTCON_S 0
#define REG_SW_EN_DEMURA_SRAM2SCTCON_E 0
#define REG_SW_EN_DV_HW5_SRAM2SCDV 0x38ec
#define REG_SW_EN_DV_HW5_SRAM2SCDV_S 0
#define REG_SW_EN_DV_HW5_SRAM2SCDV_E 0
#define REG_SW_EN_GOP0_SRAM2SCTCON 0x38f0
#define REG_SW_EN_GOP0_SRAM2SCTCON_S 0
#define REG_SW_EN_GOP0_SRAM2SCTCON_E 0
#define REG_SW_EN_GOP1_SRAM2SCTCON 0x38f4
#define REG_SW_EN_GOP1_SRAM2SCTCON_S 0
#define REG_SW_EN_GOP1_SRAM2SCTCON_E 0
#define REG_SW_EN_GOP2_SRAM2SCTCON 0x38f8
#define REG_SW_EN_GOP2_SRAM2SCTCON_S 0
#define REG_SW_EN_GOP2_SRAM2SCTCON_E 0
#define REG_SW_EN_GOP3_SRAM2SCTCON 0x38fc
#define REG_SW_EN_GOP3_SRAM2SCTCON_S 0
#define REG_SW_EN_GOP3_SRAM2SCTCON_E 0
#define REG_SW_EN_GUCD_18_LUT2_SRAM2SCACE 0x3900
#define REG_SW_EN_GUCD_18_LUT2_SRAM2SCACE_S 0
#define REG_SW_EN_GUCD_18_LUT2_SRAM2SCACE_E 0
#define REG_SW_EN_GUCD_18_SRAM2SCSCL 0x3904
#define REG_SW_EN_GUCD_18_SRAM2SCSCL_S 0
#define REG_SW_EN_GUCD_18_SRAM2SCSCL_E 0
#define REG_SW_EN_GUCD_256_LUT2_SRAM2SCACE 0x3908
#define REG_SW_EN_GUCD_256_LUT2_SRAM2SCACE_S 0
#define REG_SW_EN_GUCD_256_LUT2_SRAM2SCACE_E 0
#define REG_SW_EN_GUCD_256_SRAM2SCSCL 0x390c
#define REG_SW_EN_GUCD_256_SRAM2SCSCL_S 0
#define REG_SW_EN_GUCD_256_SRAM2SCSCL_E 0
#define REG_SW_EN_HSY_8P_SRAM2SCMW 0x3910
#define REG_SW_EN_HSY_8P_SRAM2SCMW_S 0
#define REG_SW_EN_HSY_8P_SRAM2SCMW_E 0
#define REG_SW_EN_HSY_8P_SRAM2SCACE 0x3910
#define REG_SW_EN_HSY_8P_SRAM2SCACE_S 1
#define REG_SW_EN_HSY_8P_SRAM2SCACE_E 1
#define REG_SW_EN_HSY_8P3_SRAM2SCMW 0x3914
#define REG_SW_EN_HSY_8P3_SRAM2SCMW_S 0
#define REG_SW_EN_HSY_8P3_SRAM2SCMW_E 0
#define REG_SW_EN_HSY_8P3_SRAM2SCACE 0x3914
#define REG_SW_EN_HSY_8P3_SRAM2SCACE_S 1
#define REG_SW_EN_HSY_8P3_SRAM2SCACE_E 1
#define REG_SW_EN_HSY_SP_SRAM2SCSCL 0x3918
#define REG_SW_EN_HSY_SP_SRAM2SCSCL_S 0
#define REG_SW_EN_HSY_SP_SRAM2SCSCL_E 0
#define REG_SW_EN_HSY_SP3_SRAM2SCSCL 0x391c
#define REG_SW_EN_HSY_SP3_SRAM2SCSCL_S 0
#define REG_SW_EN_HSY_SP3_SRAM2SCSCL_E 0
#define REG_SW_EN_HVSP_STP1_SRAM2SCSCL 0x3920
#define REG_SW_EN_HVSP_STP1_SRAM2SCSCL_S 0
#define REG_SW_EN_HVSP_STP1_SRAM2SCSCL_E 0
#define REG_SW_EN_HVSP_STP2_SRAM2SCSCL 0x3924
#define REG_SW_EN_HVSP_STP2_SRAM2SCSCL_S 0
#define REG_SW_EN_HVSP_STP2_SRAM2SCSCL_E 0
#define REG_SW_EN_LCE_ACE_SRAM2SCACE 0x3928
#define REG_SW_EN_LCE_ACE_SRAM2SCACE_S 0
#define REG_SW_EN_LCE_ACE_SRAM2SCACE_E 0
#define REG_SW_EN_LCE_SCL_SRAM2SCSCL 0x392c
#define REG_SW_EN_LCE_SCL_SRAM2SCSCL_S 0
#define REG_SW_EN_LCE_SCL_SRAM2SCSCL_E 0
#define REG_SW_EN_LD_EDGE2D_SRAM2SCDISP 0x3930
#define REG_SW_EN_LD_EDGE2D_SRAM2SCDISP_S 0
#define REG_SW_EN_LD_EDGE2D_SRAM2SCDISP_E 0
#define REG_SW_EN_LDCOMP_SRAM2SCDISP 0x3934
#define REG_SW_EN_LDCOMP_SRAM2SCDISP_S 0
#define REG_SW_EN_LDCOMP_SRAM2SCDISP_E 0
#define REG_SW_EN_LDM_GA_SRAM2SCDISP 0x3938
#define REG_SW_EN_LDM_GA_SRAM2SCDISP_S 0
#define REG_SW_EN_LDM_GA_SRAM2SCDISP_E 0
#define REG_SW_EN_LDMCG_SRAM2SCDISP 0x393c
#define REG_SW_EN_LDMCG_SRAM2SCDISP_S 0
#define REG_SW_EN_LDMCG_SRAM2SCDISP_E 0
#define REG_SW_EN_LPQ_PA_SRAM2SCTCON 0x3940
#define REG_SW_EN_LPQ_PA_SRAM2SCTCON_S 0
#define REG_SW_EN_LPQ_PA_SRAM2SCTCON_E 0
#define REG_SW_EN_OSD_DV_HW5_SRAM2SCTCON 0x3944
#define REG_SW_EN_OSD_DV_HW5_SRAM2SCTCON_S 0
#define REG_SW_EN_OSD_DV_HW5_SRAM2SCTCON_E 0
#define REG_SW_EN_PADJ_SRAM2SCTCON 0x3948
#define REG_SW_EN_PADJ_SRAM2SCTCON_S 0
#define REG_SW_EN_PADJ_SRAM2SCTCON_E 0
#define REG_SW_EN_PANEL_GA_SRAM2SCTCON 0x394c
#define REG_SW_EN_PANEL_GA_SRAM2SCTCON_S 0
#define REG_SW_EN_PANEL_GA_SRAM2SCTCON_E 0
#define REG_SW_EN_PQ_GAMMA_SRAM2SCMW 0x3950
#define REG_SW_EN_PQ_GAMMA_SRAM2SCMW_S 0
#define REG_SW_EN_PQ_GAMMA_SRAM2SCMW_E 0
#define REG_SW_EN_RGB_3DLUT_SRAM2SCMW 0x3954
#define REG_SW_EN_RGB_3DLUT_SRAM2SCMW_S 0
#define REG_SW_EN_RGB_3DLUT_SRAM2SCMW_E 0
#define REG_SW_EN_SCNR_HDR_SRAM2SCPQ 0x3958
#define REG_SW_EN_SCNR_HDR_SRAM2SCPQ_S 0
#define REG_SW_EN_SCNR_HDR_SRAM2SCPQ_E 0
#define REG_SW_EN_SPF_HDBK_SRAM2SCPQ 0x395c
#define REG_SW_EN_SPF_HDBK_SRAM2SCPQ_S 0
#define REG_SW_EN_SPF_HDBK_SRAM2SCPQ_E 0
#define REG_SW_EN_UCD_ST_SRAM2SCIP 0x3960
#define REG_SW_EN_UCD_ST_SRAM2SCIP_S 0
#define REG_SW_EN_UCD_ST_SRAM2SCIP_E 0
#define REG_SW_EN_VDBK_SRAM2SCPQ 0x3964
#define REG_SW_EN_VDBK_SRAM2SCPQ_S 0
#define REG_SW_EN_VDBK_SRAM2SCPQ_E 0
#define REG_SW_EN_VIP_ACE_SRAM2SCACE 0x3968
#define REG_SW_EN_VIP_ACE_SRAM2SCACE_S 0
#define REG_SW_EN_VIP_ACE_SRAM2SCACE_E 0
#define REG_SW_EN_VIP_PQ_SRAM2SCSCL 0x396c
#define REG_SW_EN_VIP_PQ_SRAM2SCSCL_S 0
#define REG_SW_EN_VIP_PQ_SRAM2SCSCL_E 0
#define REG_SW_EN_XC_ADC2SCIP 0x3970
#define REG_SW_EN_XC_ADC2SCIP_S 0
#define REG_SW_EN_XC_ADC2SCIP_E 0
#define REG_SW_EN_XC_AISR2SCSR 0x3974
#define REG_SW_EN_XC_AISR2SCSR_S 0
#define REG_SW_EN_XC_AISR2SCSR_E 0
#define REG_SW_EN_XC_SUB_DC02SCIP 0x3978
#define REG_SW_EN_XC_SUB_DC02SCIP_S 0
#define REG_SW_EN_XC_SUB_DC02SCIP_E 0
#define REG_SW_EN_XC_DC02SCIP 0x397c
#define REG_SW_EN_XC_DC02SCIP_S 0
#define REG_SW_EN_XC_DC02SCIP_E 0
#define REG_SW_EN_XC_DBG2MIU2SCIP 0x3980
#define REG_SW_EN_XC_DBG2MIU2SCIP_S 0
#define REG_SW_EN_XC_DBG2MIU2SCIP_E 0
#define REG_SW_EN_XC_DISP_MFDEC2SCIP 0x3984
#define REG_SW_EN_XC_DISP_MFDEC2SCIP_S 0
#define REG_SW_EN_XC_DISP_MFDEC2SCIP_E 0
#define REG_SW_EN_XC_ED02SCIP 0x3988
#define REG_SW_EN_XC_ED02SCIP_S 0
#define REG_SW_EN_XC_ED02SCIP_E 0
#define REG_SW_EN_XC_ED12SCIP 0x398c
#define REG_SW_EN_XC_ED12SCIP_S 0
#define REG_SW_EN_XC_ED12SCIP_E 0
#define REG_SW_EN_XC_FD2SCMW 0x3990
#define REG_SW_EN_XC_FD2SCMW_S 0
#define REG_SW_EN_XC_FD2SCMW_E 0
#define REG_SW_EN_XC_FD2SCTCON 0x3990
#define REG_SW_EN_XC_FD2SCTCON_S 1
#define REG_SW_EN_XC_FD2SCTCON_E 1
#define REG_SW_EN_XC_FD2SCIP 0x3990
#define REG_SW_EN_XC_FD2SCIP_S 2
#define REG_SW_EN_XC_FD2SCIP_E 2
#define REG_SW_EN_XC_FD2SCSCL 0x3990
#define REG_SW_EN_XC_FD2SCSCL_S 3
#define REG_SW_EN_XC_FD2SCSCL_E 3
#define REG_SW_EN_XC_FD_ABF2SCTCON 0x3990
#define REG_SW_EN_XC_FD_ABF2SCTCON_S 4
#define REG_SW_EN_XC_FD_ABF2SCTCON_E 4
#define REG_SW_EN_XC_FD_GOP02SCTCON 0x3990
#define REG_SW_EN_XC_FD_GOP02SCTCON_S 5
#define REG_SW_EN_XC_FD_GOP02SCTCON_E 5
#define REG_SW_EN_XC_FD_DV2SCTCON 0x3990
#define REG_SW_EN_XC_FD_DV2SCTCON_S 6
#define REG_SW_EN_XC_FD_DV2SCTCON_E 6
#define REG_SW_EN_XC_FD2SCDISP 0x3990
#define REG_SW_EN_XC_FD2SCDISP_S 7
#define REG_SW_EN_XC_FD2SCDISP_E 7
#define REG_SW_EN_XC_FN2SCDV 0x3994
#define REG_SW_EN_XC_FN2SCDV_S 0
#define REG_SW_EN_XC_FN2SCDV_E 0
#define REG_SW_EN_XC_FN2SCIP 0x3994
#define REG_SW_EN_XC_FN2SCIP_S 1
#define REG_SW_EN_XC_FN2SCIP_E 1
#define REG_SW_EN_XC_FN2SCM 0x3994
#define REG_SW_EN_XC_FN2SCM_S 2
#define REG_SW_EN_XC_FN2SCM_E 2
#define REG_SW_EN_XC_FN2SCMO 0x3994
#define REG_SW_EN_XC_FN2SCMO_S 3
#define REG_SW_EN_XC_FN2SCMO_E 3
#define REG_SW_EN_XC_FN2SCMW 0x3994
#define REG_SW_EN_XC_FN2SCMW_S 4
#define REG_SW_EN_XC_FN2SCMW_E 4
#define REG_SW_EN_XC_FN2SCNR 0x3994
#define REG_SW_EN_XC_FN2SCNR_S 5
#define REG_SW_EN_XC_FN2SCNR_E 5
#define REG_SW_EN_XC_FN2SCPQ_DOLBY 0x3994
#define REG_SW_EN_XC_FN2SCPQ_DOLBY_S 6
#define REG_SW_EN_XC_FN2SCPQ_DOLBY_E 6
#define REG_SW_EN_XC_FN2SCPQ_SPF 0x3994
#define REG_SW_EN_XC_FN2SCPQ_SPF_S 7
#define REG_SW_EN_XC_FN2SCPQ_SPF_E 7
#define REG_SW_EN_XC_FN2SCSCL 0x3994
#define REG_SW_EN_XC_FN2SCSCL_S 8
#define REG_SW_EN_XC_FN2SCSCL_E 8
#define REG_SW_EN_XC_FN2SCSR 0x3994
#define REG_SW_EN_XC_FN2SCSR_S 9
#define REG_SW_EN_XC_FN2SCSR_E 9
#define REG_SW_EN_XC_FN2SCTCON 0x3994
#define REG_SW_EN_XC_FN2SCTCON_S 10
#define REG_SW_EN_XC_FN2SCTCON_E 10
#define REG_SW_EN_XC_FN_22SCDV 0x3994
#define REG_SW_EN_XC_FN_22SCDV_S 11
#define REG_SW_EN_XC_FN_22SCDV_E 11
#define REG_SW_EN_XC_FN2SCDISP 0x3994
#define REG_SW_EN_XC_FN2SCDISP_S 12
#define REG_SW_EN_XC_FN2SCDISP_E 12
#define REG_SW_EN_XC_FS2SCACE_HSY 0x3998
#define REG_SW_EN_XC_FS2SCACE_HSY_S 0
#define REG_SW_EN_XC_FS2SCACE_HSY_E 0
#define REG_SW_EN_XC_FS2SCACE_VIP 0x3998
#define REG_SW_EN_XC_FS2SCACE_VIP_S 1
#define REG_SW_EN_XC_FS2SCACE_VIP_E 1
#define REG_SW_EN_XC_FS2SCACE_VOP2 0x3998
#define REG_SW_EN_XC_FS2SCACE_VOP2_S 2
#define REG_SW_EN_XC_FS2SCACE_VOP2_E 2
#define REG_SW_EN_XC_FS2SCMW 0x3998
#define REG_SW_EN_XC_FS2SCMW_S 3
#define REG_SW_EN_XC_FS2SCMW_E 3
#define REG_SW_EN_XC_FS2SCSCL 0x3998
#define REG_SW_EN_XC_FS2SCSCL_S 4
#define REG_SW_EN_XC_FS2SCSCL_E 4
#define REG_SW_EN_XC_FS2SCSR 0x3998
#define REG_SW_EN_XC_FS2SCSR_S 5
#define REG_SW_EN_XC_FS2SCSR_E 5
#define REG_SW_EN_XC_FS2SCIP 0x3998
#define REG_SW_EN_XC_FS2SCIP_S 6
#define REG_SW_EN_XC_FS2SCIP_E 6
#define REG_SW_EN_XC_FS2SCDISP 0x3998
#define REG_SW_EN_XC_FS2SCDISP_S 7
#define REG_SW_EN_XC_FS2SCDISP_E 7
#define REG_SW_EN_XC_FS2SCNR 0x3998
#define REG_SW_EN_XC_FS2SCNR_S 9
#define REG_SW_EN_XC_FS2SCNR_E 9
#define REG_SW_EN_XC_HD2MIU_M2SCIP 0x399c
#define REG_SW_EN_XC_HD2MIU_M2SCIP_S 0
#define REG_SW_EN_XC_HD2MIU_M2SCIP_E 0
#define REG_SW_EN_XC_HD2MIU_S2SCIP 0x39a0
#define REG_SW_EN_XC_HD2MIU_S2SCIP_S 0
#define REG_SW_EN_XC_HD2MIU_S2SCIP_E 0
#define REG_SW_EN_XC_HDMI02SCIP 0x39a4
#define REG_SW_EN_XC_HDMI02SCIP_S 0
#define REG_SW_EN_XC_HDMI02SCIP_E 0
#define REG_SW_EN_XC_HDMI12SCIP 0x39a8
#define REG_SW_EN_XC_HDMI12SCIP_S 0
#define REG_SW_EN_XC_HDMI12SCIP_E 0
#define REG_SW_EN_XC_HDMI22SCIP 0x39ac
#define REG_SW_EN_XC_HDMI22SCIP_S 0
#define REG_SW_EN_XC_HDMI22SCIP_E 0
#define REG_SW_EN_XC_HDMI32SCIP 0x39b0
#define REG_SW_EN_XC_HDMI32SCIP_S 0
#define REG_SW_EN_XC_HDMI32SCIP_E 0
#define REG_SW_EN_XC_ID02SCIP 0x39b4
#define REG_SW_EN_XC_ID02SCIP_S 0
#define REG_SW_EN_XC_ID02SCIP_E 0
#define REG_SW_EN_XC_ID12SCIP 0x39b8
#define REG_SW_EN_XC_ID12SCIP_S 0
#define REG_SW_EN_XC_ID12SCIP_E 0
#define REG_SW_EN_XC_IP2_SRC2SCIP 0x39bc
#define REG_SW_EN_XC_IP2_SRC2SCIP_S 0
#define REG_SW_EN_XC_IP2_SRC2SCIP_E 0
#define REG_SW_EN_XC_MFDEC2SCIP 0x39c0
#define REG_SW_EN_XC_MFDEC2SCIP_S 0
#define REG_SW_EN_XC_MFDEC2SCIP_E 0
#define REG_SW_EN_XC_OD2SCMW 0x39c4
#define REG_SW_EN_XC_OD2SCMW_S 0
#define REG_SW_EN_XC_OD2SCMW_E 0
#define REG_SW_EN_XC_OD2SCTCON 0x39c4
#define REG_SW_EN_XC_OD2SCTCON_S 1
#define REG_SW_EN_XC_OD2SCTCON_E 1
#define REG_SW_EN_XC_OD2SCIP 0x39c4
#define REG_SW_EN_XC_OD2SCIP_S 2
#define REG_SW_EN_XC_OD2SCIP_E 2
#define REG_SW_EN_XC_OD2SCSCL 0x39c4
#define REG_SW_EN_XC_OD2SCSCL_S 3
#define REG_SW_EN_XC_OD2SCSCL_E 3
#define REG_SW_EN_XC_OD_EDGE2SCTCON 0x39c4
#define REG_SW_EN_XC_OD_EDGE2SCTCON_S 4
#define REG_SW_EN_XC_OD_EDGE2SCTCON_E 4
#define REG_SW_EN_XC_SC2FPLL2SCIP 0x39c4
#define REG_SW_EN_XC_SC2FPLL2SCIP_S 6
#define REG_SW_EN_XC_SC2FPLL2SCIP_E 6
#define REG_SW_EN_XC_OD2SCDISP 0x39c4
#define REG_SW_EN_XC_OD2SCDISP_S 8
#define REG_SW_EN_XC_OD2SCDISP_E 8
#define REG_SW_EN_XC_SLOW2SCIP 0x39c8
#define REG_SW_EN_XC_SLOW2SCIP_S 0
#define REG_SW_EN_XC_SLOW2SCIP_E 0
#define REG_SW_EN_XC_SR_ALAI2SCSR 0x39cc
#define REG_SW_EN_XC_SR_ALAI2SCSR_S 0
#define REG_SW_EN_XC_SR_ALAI2SCSR_E 0
#define REG_SW_EN_XC_SR_SRAM_SHARE2SCSR 0x39d0
#define REG_SW_EN_XC_SR_SRAM_SHARE2SCSR_S 0
#define REG_SW_EN_XC_SR_SRAM_SHARE2SCSR_E 0
#define REG_SW_EN_XC_SRS2SCSR 0x39d4
#define REG_SW_EN_XC_SRS2SCSR_S 0
#define REG_SW_EN_XC_SRS2SCSR_E 0
#define REG_SW_EN_XC_SRS2SCSCL 0x39d4
#define REG_SW_EN_XC_SRS2SCSCL_S 1
#define REG_SW_EN_XC_SRS2SCSCL_E 1
#define REG_SW_EN_XC_TGEN_WIN2SCIP 0x39d8
#define REG_SW_EN_XC_TGEN_WIN2SCIP_S 0
#define REG_SW_EN_XC_TGEN_WIN2SCIP_E 0
#define REG_SW_EN_XC_UCD_STAT2SCIP 0x39dc
#define REG_SW_EN_XC_UCD_STAT2SCIP_S 0
#define REG_SW_EN_XC_UCD_STAT2SCIP_E 0
#define REG_SW_EN_XC_VD2SCIP 0x39e0
#define REG_SW_EN_XC_VD2SCIP_S 0
#define REG_SW_EN_XC_VD2SCIP_E 0
#define REG_SW_EN_XC_VE2SCIP 0x39e4
#define REG_SW_EN_XC_VE2SCIP_S 0
#define REG_SW_EN_XC_VE2SCIP_E 0
#define REG_SW_EN_XCPLL_SYN2XCPLL_DMACRO 0x39e8
#define REG_SW_EN_XCPLL_SYN2XCPLL_DMACRO_S 0
#define REG_SW_EN_XCPLL_SYN2XCPLL_DMACRO_E 0
#define REG_SW_EN_XTAL_12M2SCACE 0x39ec
#define REG_SW_EN_XTAL_12M2SCACE_S 0
#define REG_SW_EN_XTAL_12M2SCACE_E 0
#define REG_SW_EN_XTAL_12M2SCDV 0x39ec
#define REG_SW_EN_XTAL_12M2SCDV_S 1
#define REG_SW_EN_XTAL_12M2SCDV_E 1
#define REG_SW_EN_XTAL_12M2SCNR 0x39ec
#define REG_SW_EN_XTAL_12M2SCNR_S 2
#define REG_SW_EN_XTAL_12M2SCNR_E 2
#define REG_SW_EN_XTAL_12M2SCSCL 0x39ec
#define REG_SW_EN_XTAL_12M2SCSCL_S 3
#define REG_SW_EN_XTAL_12M2SCSCL_E 3
#define REG_SW_EN_XTAL_12M2SCSR 0x39ec
#define REG_SW_EN_XTAL_12M2SCSR_S 4
#define REG_SW_EN_XTAL_12M2SCSR_E 4
#define REG_SW_EN_XTAL_12M2SCTCON 0x39ec
#define REG_SW_EN_XTAL_12M2SCTCON_S 5
#define REG_SW_EN_XTAL_12M2SCTCON_E 5
#define REG_SW_EN_XTAL_12M2SCIP 0x39ec
#define REG_SW_EN_XTAL_12M2SCIP_S 6
#define REG_SW_EN_XTAL_12M2SCIP_E 6
#define REG_SW_EN_XTAL_12M2SCDISP 0x39ec
#define REG_SW_EN_XTAL_12M2SCDISP_S 7
#define REG_SW_EN_XTAL_12M2SCDISP_E 7
#define REG_SW_EN_XTAL_24M2SCACE 0x39f0
#define REG_SW_EN_XTAL_24M2SCACE_S 0
#define REG_SW_EN_XTAL_24M2SCACE_E 0
#define REG_SW_EN_XTAL_24M2SCDV 0x39f0
#define REG_SW_EN_XTAL_24M2SCDV_S 1
#define REG_SW_EN_XTAL_24M2SCDV_E 1
#define REG_SW_EN_XTAL_24M2SCIP 0x39f0
#define REG_SW_EN_XTAL_24M2SCIP_S 2
#define REG_SW_EN_XTAL_24M2SCIP_E 2
#define REG_SW_EN_XTAL_24M2SCMW 0x39f0
#define REG_SW_EN_XTAL_24M2SCMW_S 3
#define REG_SW_EN_XTAL_24M2SCMW_E 3
#define REG_SW_EN_XTAL_24M2SCNR 0x39f0
#define REG_SW_EN_XTAL_24M2SCNR_S 4
#define REG_SW_EN_XTAL_24M2SCNR_E 4
#define REG_SW_EN_XTAL_24M2SCPQ 0x39f0
#define REG_SW_EN_XTAL_24M2SCPQ_S 5
#define REG_SW_EN_XTAL_24M2SCPQ_E 5
#define REG_SW_EN_XTAL_24M2SCSCL 0x39f0
#define REG_SW_EN_XTAL_24M2SCSCL_S 6
#define REG_SW_EN_XTAL_24M2SCSCL_E 6
#define REG_SW_EN_XTAL_24M2SCSR 0x39f0
#define REG_SW_EN_XTAL_24M2SCSR_S 7
#define REG_SW_EN_XTAL_24M2SCSR_E 7
#define REG_SW_EN_XTAL_24M2SCTCON 0x39f0
#define REG_SW_EN_XTAL_24M2SCTCON_S 8
#define REG_SW_EN_XTAL_24M2SCTCON_E 8
#define REG_SW_EN_XTAL_24M2SCDISP 0x39f0
#define REG_SW_EN_XTAL_24M2SCDISP_S 9
#define REG_SW_EN_XTAL_24M2SCDISP_E 9
#define REG_SW_EN_XTAL_IP12SCIP 0x39f4
#define REG_SW_EN_XTAL_IP12SCIP_S 0
#define REG_SW_EN_XTAL_IP12SCIP_E 0
#define REG_SW_EN_XC_SUB1_DC02SCIP 0x39f8
#define REG_SW_EN_XC_SUB1_DC02SCIP_S 0
#define REG_SW_EN_XC_SUB1_DC02SCIP_E 0
#define REG_SW_EN_XVYCC_SRAM2SCMW 0x39fc
#define REG_SW_EN_XVYCC_SRAM2SCMW_S 0
#define REG_SW_EN_XVYCC_SRAM2SCMW_E 0
#define REG_SW_EN_SIDCLK_HD02SCIP 0x3a00
#define REG_SW_EN_SIDCLK_HD02SCIP_S 0
#define REG_SW_EN_SIDCLK_HD02SCIP_E 0
#define REG_SW_EN_SIDCLK_HD12SCIP 0x3a04
#define REG_SW_EN_SIDCLK_HD12SCIP_S 0
#define REG_SW_EN_SIDCLK_HD12SCIP_E 0
#define REG_SW_EN_SIDCLK_HD22SCIP 0x3a08
#define REG_SW_EN_SIDCLK_HD22SCIP_S 0
#define REG_SW_EN_SIDCLK_HD22SCIP_E 0
#define REG_SW_EN_SIDCLK_HD32SCIP 0x3a0c
#define REG_SW_EN_SIDCLK_HD32SCIP_S 0
#define REG_SW_EN_SIDCLK_HD32SCIP_E 0
#define REG_SW_EN_XC_DIP02SCIP 0x3a10
#define REG_SW_EN_XC_DIP02SCIP_S 0
#define REG_SW_EN_XC_DIP02SCIP_E 0
#define REG_SW_EN_XC_DIP12SCIP 0x3a14
#define REG_SW_EN_XC_DIP12SCIP_S 0
#define REG_SW_EN_XC_DIP12SCIP_E 0
#define REG_SW_EN_XC_DIP22SCIP 0x3a18
#define REG_SW_EN_XC_DIP22SCIP_S 0
#define REG_SW_EN_XC_DIP22SCIP_E 0
#define REG_SW_EN_XC_VEDAC2SCIP 0x3a1c
#define REG_SW_EN_XC_VEDAC2SCIP_S 0
#define REG_SW_EN_XC_VEDAC2SCIP_E 0
#define REG_SW_EN_XC_VEIN2SCIP 0x3a20
#define REG_SW_EN_XC_VEIN2SCIP_S 0
#define REG_SW_EN_XC_VEIN2SCIP_E 0
#define REG_SW_EN_V1_ODCLK2SCIP 0x3a20
#define REG_SW_EN_V1_ODCLK2SCIP_S 9
#define REG_SW_EN_V1_ODCLK2SCIP_E 9
#define REG_SW_EN_V2_ODCLK2SCIP 0x3a20
#define REG_SW_EN_V2_ODCLK2SCIP_S 10
#define REG_SW_EN_V2_ODCLK2SCIP_E 10
#define REG_SW_EN_DIP1_HVSP_SRAM2SCMW 0x3a24
#define REG_SW_EN_DIP1_HVSP_SRAM2SCMW_S 0
#define REG_SW_EN_DIP1_HVSP_SRAM2SCMW_E 0
#define REG_SW_EN_DIP1_XVYCC_SRAM2SCMW 0x3a28
#define REG_SW_EN_DIP1_XVYCC_SRAM2SCMW_S 0
#define REG_SW_EN_DIP1_XVYCC_SRAM2SCMW_E 0
#define REG_SW_EN_CMBAI2VD 0x3a2c
#define REG_SW_EN_CMBAI2VD_S 0
#define REG_SW_EN_CMBAI2VD_E 0
#define REG_SW_EN_CMBAO2VD 0x3a30
#define REG_SW_EN_CMBAO2VD_S 0
#define REG_SW_EN_CMBAO2VD_E 0
#define REG_SW_EN_CMBBI2VD 0x3a34
#define REG_SW_EN_CMBBI2VD_S 0
#define REG_SW_EN_CMBBI2VD_E 0
#define REG_SW_EN_CMBBO2VD 0x3a38
#define REG_SW_EN_CMBBO2VD_S 0
#define REG_SW_EN_CMBBO2VD_E 0
#define REG_SW_EN_MCU_MAIL02VD 0x3a3c
#define REG_SW_EN_MCU_MAIL02VD_S 0
#define REG_SW_EN_MCU_MAIL02VD_E 0
#define REG_SW_EN_MCU_MAIL12VD 0x3a40
#define REG_SW_EN_MCU_MAIL12VD_S 0
#define REG_SW_EN_MCU_MAIL12VD_E 0
#define REG_SW_EN_VD_32FSC2VD 0x3a44
#define REG_SW_EN_VD_32FSC2VD_S 0
#define REG_SW_EN_VD_32FSC2VD_E 0
#define REG_SW_EN_VD2MHEG5_ADC 0x3a48
#define REG_SW_EN_VD2MHEG5_ADC_S 0
#define REG_SW_EN_VD2MHEG5_ADC_E 0
#define REG_SW_EN_VD2VD 0x3a48
#define REG_SW_EN_VD2VD_S 1
#define REG_SW_EN_VD2VD_E 1
#define REG_SW_EN_VD2X2MHEG5_ADC 0x3a4c
#define REG_SW_EN_VD2X2MHEG5_ADC_S 0
#define REG_SW_EN_VD2X2MHEG5_ADC_E 0
#define REG_SW_EN_VD2X2VD 0x3a4c
#define REG_SW_EN_VD2X2VD_S 1
#define REG_SW_EN_VD2X2VD_E 1
#define REG_SW_EN_XC_OD_META2SCTCON 0x3a50
#define REG_SW_EN_XC_OD_META2SCTCON_S 0
#define REG_SW_EN_XC_OD_META2SCTCON_E 0
#define REG_SW_EN_XC_OD_DELTA_META2SCTCON 0x3a54
#define REG_SW_EN_XC_OD_DELTA_META2SCTCON_S 0
#define REG_SW_EN_XC_OD_DELTA_META2SCTCON_E 0
#define REG_SW_EN_VENC2VENC 0x3a58
#define REG_SW_EN_VENC2VENC_S 0
#define REG_SW_EN_VENC2VENC_E 0
#define REG_SW_EN_VENC2VENC_IP 0x3a58
#define REG_SW_EN_VENC2VENC_IP_S 1
#define REG_SW_EN_VENC2VENC_IP_E 1
#define REG_SW_EN_XC_OD_OSD_META2SCTCON 0x3a5c
#define REG_SW_EN_XC_OD_OSD_META2SCTCON_S 0
#define REG_SW_EN_XC_OD_OSD_META2SCTCON_E 0
#define REG_SW_EN_CLK_IP_1X_N2FLASH_DMACRO 0x3a60
#define REG_SW_EN_CLK_IP_1X_N2FLASH_DMACRO_S 0
#define REG_SW_EN_CLK_IP_1X_N2FLASH_DMACRO_E 0
#define REG_SW_EN_CLK_IP_1X2FLASH_DMACRO 0x3a64
#define REG_SW_EN_CLK_IP_1X2FLASH_DMACRO_S 0
#define REG_SW_EN_CLK_IP_1X2FLASH_DMACRO_E 0
#define REG_SW_EN_CLK_M_2X_N2FLASH_DMACRO 0x3a68
#define REG_SW_EN_CLK_M_2X_N2FLASH_DMACRO_S 0
#define REG_SW_EN_CLK_M_2X_N2FLASH_DMACRO_E 0
#define REG_SW_EN_CLK_M_2X2FLASH_DMACRO 0x3a6c
#define REG_SW_EN_CLK_M_2X2FLASH_DMACRO_S 0
#define REG_SW_EN_CLK_M_2X2FLASH_DMACRO_E 0
#define REG_SW_EN_CLK_M_4X_MID2FLASH_DMACRO 0x3a70
#define REG_SW_EN_CLK_M_4X_MID2FLASH_DMACRO_S 0
#define REG_SW_EN_CLK_M_4X_MID2FLASH_DMACRO_E 0
#define REG_SW_EN_CLK_M_4X2FLASH_DMACRO 0x3a74
#define REG_SW_EN_CLK_M_4X2FLASH_DMACRO_S 0
#define REG_SW_EN_CLK_M_4X2FLASH_DMACRO_E 0
#define REG_SW_EN_FB_MCLK2FLASH_DMACRO 0x3a78
#define REG_SW_EN_FB_MCLK2FLASH_DMACRO_S 0
#define REG_SW_EN_FB_MCLK2FLASH_DMACRO_E 0
#define REG_SW_EN_MPLL2FLASH_DMACRO 0x3a7c
#define REG_SW_EN_MPLL2FLASH_DMACRO_S 0
#define REG_SW_EN_MPLL2FLASH_DMACRO_E 0
#define REG_SW_EN_OSP2FLASH_DMACRO 0x3a80
#define REG_SW_EN_OSP2FLASH_DMACRO_S 0
#define REG_SW_EN_OSP2FLASH_DMACRO_E 0
#define REG_SW_EN_ECC2FCIE 0x3a84
#define REG_SW_EN_ECC2FCIE_S 0
#define REG_SW_EN_ECC2FCIE_E 0
#define REG_SW_EN_FCIE_N2FCIE 0x3a88
#define REG_SW_EN_FCIE_N2FCIE_S 0
#define REG_SW_EN_FCIE_N2FCIE_E 0
#define REG_SW_EN_FCIE2FCIE 0x3a8c
#define REG_SW_EN_FCIE2FCIE_S 0
#define REG_SW_EN_FCIE2FCIE_E 0
#define REG_SW_EN_FCIE2SD_SDR_MACRO 0x3a8c
#define REG_SW_EN_FCIE2SD_SDR_MACRO_S 1
#define REG_SW_EN_FCIE2SD_SDR_MACRO_E 1
#define REG_SW_EN_PAD_SD2SD_SDR_MACRO 0x3a90
#define REG_SW_EN_PAD_SD2SD_SDR_MACRO_S 0
#define REG_SW_EN_PAD_SD2SD_SDR_MACRO_E 0
#define REG_SW_EN_EMMC_DQS_SKEW2EMMC_DQS_SKEW 0x3a94
#define REG_SW_EN_EMMC_DQS_SKEW2EMMC_DQS_SKEW_S 0
#define REG_SW_EN_EMMC_DQS_SKEW2EMMC_DQS_SKEW_E 0
#define REG_SW_EN_EMMC_DQS_SKEW2SD_DQS_SKEW 0x3a94
#define REG_SW_EN_EMMC_DQS_SKEW2SD_DQS_SKEW_S 1
#define REG_SW_EN_EMMC_DQS_SKEW2SD_DQS_SKEW_E 1
#define REG_SW_EN_EMMC_DQS_DLY_N2SKEW_LATCH 0x3a98
#define REG_SW_EN_EMMC_DQS_DLY_N2SKEW_LATCH_S 0
#define REG_SW_EN_EMMC_DQS_DLY_N2SKEW_LATCH_E 0
#define REG_SW_EN_EMMC_DQS_DLY_N2DQS 0x3a98
#define REG_SW_EN_EMMC_DQS_DLY_N2DQS_S 1
#define REG_SW_EN_EMMC_DQS_DLY_N2DQS_E 1
#define REG_SW_EN_EMMC_DQS_DLY_2ND_N2SKEW_LATCH_CMD 0x3a9c
#define REG_SW_EN_EMMC_DQS_DLY_2ND_N2SKEW_LATCH_CMD_S 0
#define REG_SW_EN_EMMC_DQS_DLY_2ND_N2SKEW_LATCH_CMD_E 0
#define REG_SW_EN_GMAC_AHB2GMAC 0x3aac
#define REG_SW_EN_GMAC_AHB2GMAC_S 0
#define REG_SW_EN_GMAC_AHB2GMAC_E 0
#define REG_SW_EN_GMAC_REF2GMAC 0x3ab0
#define REG_SW_EN_GMAC_REF2GMAC_S 0
#define REG_SW_EN_GMAC_REF2GMAC_E 0
#define REG_SW_EN_GMAC_RX2GMAC 0x3ab4
#define REG_SW_EN_GMAC_RX2GMAC_S 0
#define REG_SW_EN_GMAC_RX2GMAC_E 0
#define REG_SW_EN_GMAC_TX2GMAC 0x3ab8
#define REG_SW_EN_GMAC_TX2GMAC_S 0
#define REG_SW_EN_GMAC_TX2GMAC_E 0
#define REG_SW_EN_AU_UART0_SYNTH2MCU_CKCTRL_TOP 0x3acc
#define REG_SW_EN_AU_UART0_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_AU_UART0_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_AU_UART02AU_UART0 0x3ad0
#define REG_SW_EN_AU_UART02AU_UART0_S 0
#define REG_SW_EN_AU_UART02AU_UART0_E 0
#define REG_SW_EN_FRC_FUART0_SYNTH2MCU_CKCTRL_TOP 0x3ad4
#define REG_SW_EN_FRC_FUART0_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_FRC_FUART0_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_FRC_FUART02FRCIOPM 0x3ad8
#define REG_SW_EN_FRC_FUART02FRCIOPM_S 0
#define REG_SW_EN_FRC_FUART02FRCIOPM_E 0
#define REG_SW_EN_FRC_FUART02FRCIOPMRV55 0x3ad8
#define REG_SW_EN_FRC_FUART02FRCIOPMRV55_S 1
#define REG_SW_EN_FRC_FUART02FRCIOPMRV55_E 1
#define REG_SW_EN_FRC_MSPI0_DIV2MCU_CKCTRL_TOP 0x3adc
#define REG_SW_EN_FRC_MSPI0_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_FRC_MSPI0_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_FRC_MSPI02FRCIOPM 0x3ae0
#define REG_SW_EN_FRC_MSPI02FRCIOPM_S 0
#define REG_SW_EN_FRC_MSPI02FRCIOPM_E 0
#define REG_SW_EN_FRC_MSPI02FRCIOPMRV55 0x3ae0
#define REG_SW_EN_FRC_MSPI02FRCIOPMRV55_S 1
#define REG_SW_EN_FRC_MSPI02FRCIOPMRV55_E 1
#define REG_SW_EN_FRC_UART0_SYNTH2MCU_CKCTRL_TOP 0x3ae4
#define REG_SW_EN_FRC_UART0_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_FRC_UART0_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_FRC_UART02FRCIOPM 0x3ae8
#define REG_SW_EN_FRC_UART02FRCIOPM_S 0
#define REG_SW_EN_FRC_UART02FRCIOPM_E 0
#define REG_SW_EN_FRC_UART02FRCIOPMRV55 0x3ae8
#define REG_SW_EN_FRC_UART02FRCIOPMRV55_S 1
#define REG_SW_EN_FRC_UART02FRCIOPMRV55_E 1
#define REG_SW_EN_FRC_UART1_SYNTH2MCU_CKCTRL_TOP 0x3aec
#define REG_SW_EN_FRC_UART1_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_FRC_UART1_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_FRC_UART12FRCIOPM 0x3af0
#define REG_SW_EN_FRC_UART12FRCIOPM_S 0
#define REG_SW_EN_FRC_UART12FRCIOPM_E 0
#define REG_SW_EN_FRC_UART12FRCIOPMRV55 0x3af0
#define REG_SW_EN_FRC_UART12FRCIOPMRV55_S 1
#define REG_SW_EN_FRC_UART12FRCIOPMRV55_E 1
#define REG_SW_EN_FUART0_SYNTH2MCU_CKCTRL_TOP 0x3af4
#define REG_SW_EN_FUART0_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_FUART0_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_FUART02MCU_FUART0 0x3af8
#define REG_SW_EN_FUART02MCU_FUART0_S 0
#define REG_SW_EN_FUART02MCU_FUART0_E 0
#define REG_SW_EN_UART0_SYNTH2MCU_CKCTRL_TOP 0x3afc
#define REG_SW_EN_UART0_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_UART0_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_UART02MCU_UART0 0x3b00
#define REG_SW_EN_UART02MCU_UART0_S 0
#define REG_SW_EN_UART02MCU_UART0_E 0
#define REG_SW_EN_UART1_SYNTH2MCU_CKCTRL_TOP 0x3b04
#define REG_SW_EN_UART1_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_UART1_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_UART12MCU_UART1 0x3b08
#define REG_SW_EN_UART12MCU_UART1_S 0
#define REG_SW_EN_UART12MCU_UART1_E 0
#define REG_SW_EN_UART2_SYNTH2MCU_CKCTRL_TOP 0x3b0c
#define REG_SW_EN_UART2_SYNTH2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_UART2_SYNTH2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_UART22MCU_UART2 0x3b10
#define REG_SW_EN_UART22MCU_UART2_S 0
#define REG_SW_EN_UART22MCU_UART2_E 0
#define REG_SW_EN_MCU_BUS2FRCIOPM 0x3b4c
#define REG_SW_EN_MCU_BUS2FRCIOPM_S 0
#define REG_SW_EN_MCU_BUS2FRCIOPM_E 0
#define REG_SW_EN_MCU_BUS2FRCIOPMRV55 0x3b4c
#define REG_SW_EN_MCU_BUS2FRCIOPMRV55_S 1
#define REG_SW_EN_MCU_BUS2FRCIOPMRV55_E 1
#define REG_SW_EN_MCU_BUS2MAC 0x3b4c
#define REG_SW_EN_MCU_BUS2MAC_S 2
#define REG_SW_EN_MCU_BUS2MAC_E 2
#define REG_SW_EN_MCU_BUS2SCSCL 0x3b4c
#define REG_SW_EN_MCU_BUS2SCSCL_S 3
#define REG_SW_EN_MCU_BUS2SCSCL_E 3
#define REG_SW_EN_AU_MCU_BUS2AU_MCU 0x3b4c
#define REG_SW_EN_AU_MCU_BUS2AU_MCU_S 4
#define REG_SW_EN_AU_MCU_BUS2AU_MCU_E 4
#define REG_SW_EN_MCU_BUS2DEMOD0 0x3b4c
#define REG_SW_EN_MCU_BUS2DEMOD0_S 5
#define REG_SW_EN_MCU_BUS2DEMOD0_E 5
#define REG_SW_EN_MCU_BUS2MCU_M2MCU 0x3b4c
#define REG_SW_EN_MCU_BUS2MCU_M2MCU_S 6
#define REG_SW_EN_MCU_BUS2MCU_M2MCU_E 6
#define REG_SW_EN_MCU_BUS2RV55FRC 0x3b4c
#define REG_SW_EN_MCU_BUS2RV55FRC_S 7
#define REG_SW_EN_MCU_BUS2RV55FRC_E 7
#define REG_SW_EN_MCU_BUS2RV55PQU 0x3b4c
#define REG_SW_EN_MCU_BUS2RV55PQU_S 8
#define REG_SW_EN_MCU_BUS2RV55PQU_E 8
#define REG_SW_EN_MCU_BUS2MCU_NONPM_RIU_BRIDGE 0x3b4c
#define REG_SW_EN_MCU_BUS2MCU_NONPM_RIU_BRIDGE_S 9
#define REG_SW_EN_MCU_BUS2MCU_NONPM_RIU_BRIDGE_E 9
#define REG_SW_EN_MCU_BUS2MCU_CODEC_RIU_BRIDGE 0x3b4c
#define REG_SW_EN_MCU_BUS2MCU_CODEC_RIU_BRIDGE_S 10
#define REG_SW_EN_MCU_BUS2MCU_CODEC_RIU_BRIDGE_E 10
#define REG_SW_EN_MCU_BUS2MCUSYS_XIU_BRIDGE 0x3b4c
#define REG_SW_EN_MCU_BUS2MCUSYS_XIU_BRIDGE_S 11
#define REG_SW_EN_MCU_BUS2MCUSYS_XIU_BRIDGE_E 11
#define REG_SW_EN_MCU_CODEC2MCU_CODEC_RIU_BRIDGE 0x3b54
#define REG_SW_EN_MCU_CODEC2MCU_CODEC_RIU_BRIDGE_S 0
#define REG_SW_EN_MCU_CODEC2MCU_CODEC_RIU_BRIDGE_E 0
#define REG_SW_EN_MCU_CODEC2SECURE_TOP_CODEC 0x3b54
#define REG_SW_EN_MCU_CODEC2SECURE_TOP_CODEC_S 2
#define REG_SW_EN_MCU_CODEC2SECURE_TOP_CODEC_E 2
#define REG_SW_EN_MCU_DMD2DEMOD0 0x3b5c
#define REG_SW_EN_MCU_DMD2DEMOD0_S 0
#define REG_SW_EN_MCU_DMD2DEMOD0_E 0
#define REG_SW_EN_MCU_FRC2FRCIOPM 0x3b64
#define REG_SW_EN_MCU_FRC2FRCIOPM_S 0
#define REG_SW_EN_MCU_FRC2FRCIOPM_E 0
#define REG_SW_EN_MCU_FRC2FRCIOPMRV55 0x3b64
#define REG_SW_EN_MCU_FRC2FRCIOPMRV55_S 1
#define REG_SW_EN_MCU_FRC2FRCIOPMRV55_E 1
#define REG_SW_EN_MCU_FRC2RV55FRC 0x3b64
#define REG_SW_EN_MCU_FRC2RV55FRC_S 2
#define REG_SW_EN_MCU_FRC2RV55FRC_E 2
#define REG_SW_EN_MCU_FRC2RV55PQU 0x3b64
#define REG_SW_EN_MCU_FRC2RV55PQU_S 3
#define REG_SW_EN_MCU_FRC2RV55PQU_E 3
#define REG_SW_EN_MCU_HDMI2MAC 0x3b6c
#define REG_SW_EN_MCU_HDMI2MAC_S 1
#define REG_SW_EN_MCU_HDMI2MAC_E 1
#define REG_SW_EN_MCU_NONPM2CHIP_REG 0x3b74
#define REG_SW_EN_MCU_NONPM2CHIP_REG_S 0
#define REG_SW_EN_MCU_NONPM2CHIP_REG_E 0
#define REG_SW_EN_MCU_NONPM2CMDQ 0x3b74
#define REG_SW_EN_MCU_NONPM2CMDQ_S 1
#define REG_SW_EN_MCU_NONPM2CMDQ_E 1
#define REG_SW_EN_MCU_NONPM2DEMOD0 0x3b74
#define REG_SW_EN_MCU_NONPM2DEMOD0_S 2
#define REG_SW_EN_MCU_NONPM2DEMOD0_E 2
#define REG_SW_EN_MCU_NONPM2DSCRMB 0x3b74
#define REG_SW_EN_MCU_NONPM2DSCRMB_S 3
#define REG_SW_EN_MCU_NONPM2DSCRMB_E 3
#define REG_SW_EN_MCU_NONPM2FCIE 0x3b74
#define REG_SW_EN_MCU_NONPM2FCIE_S 4
#define REG_SW_EN_MCU_NONPM2FCIE_E 4
#define REG_SW_EN_MCU_NONPM2PAD_TOP 0x3b74
#define REG_SW_EN_MCU_NONPM2PAD_TOP_S 5
#define REG_SW_EN_MCU_NONPM2PAD_TOP_E 5
#define REG_SW_EN_MCU_NONPM2FRCIOPMRV55 0x3b74
#define REG_SW_EN_MCU_NONPM2FRCIOPMRV55_S 6
#define REG_SW_EN_MCU_NONPM2FRCIOPMRV55_E 6
#define REG_SW_EN_MCU_NONPM2FRCMEHALO 0x3b74
#define REG_SW_EN_MCU_NONPM2FRCMEHALO_S 7
#define REG_SW_EN_MCU_NONPM2FRCMEHALO_E 7
#define REG_SW_EN_MCU_NONPM2GE 0x3b74
#define REG_SW_EN_MCU_NONPM2GE_S 8
#define REG_SW_EN_MCU_NONPM2GE_E 8
#define REG_SW_EN_MCU_NONPM2GMAC 0x3b74
#define REG_SW_EN_MCU_NONPM2GMAC_S 9
#define REG_SW_EN_MCU_NONPM2GMAC_E 9
#define REG_SW_EN_MCU_NONPM2GPD 0x3b74
#define REG_SW_EN_MCU_NONPM2GPD_S 10
#define REG_SW_EN_MCU_NONPM2GPD_E 10
#define REG_SW_EN_MCU_NONPM2GPU_DIE 0x3b74
#define REG_SW_EN_MCU_NONPM2GPU_DIE_S 11
#define REG_SW_EN_MCU_NONPM2GPU_DIE_E 11
#define REG_SW_EN_MCU_NONPM2GPU_NODIE 0x3b74
#define REG_SW_EN_MCU_NONPM2GPU_NODIE_S 12
#define REG_SW_EN_MCU_NONPM2GPU_NODIE_E 12
#define REG_SW_EN_MCU_NONPM2INTR_CTRL_TOP_WP 0x3b74
#define REG_SW_EN_MCU_NONPM2INTR_CTRL_TOP_WP_S 13
#define REG_SW_EN_MCU_NONPM2INTR_CTRL_TOP_WP_E 13
#define REG_SW_EN_MCU_NONPM2MAC 0x3b74
#define REG_SW_EN_MCU_NONPM2MAC_S 14
#define REG_SW_EN_MCU_NONPM2MAC_E 14
#define REG_SW_EN_MCU_NONPM2MCU_BDMA 0x3b74
#define REG_SW_EN_MCU_NONPM2MCU_BDMA_S 15
#define REG_SW_EN_MCU_NONPM2MCU_BDMA_E 15
#define REG_SW_EN_MCU_NONPM2MCU_DEMURA 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_DEMURA_S 0
#define REG_SW_EN_MCU_NONPM2MCU_DEMURA_E 0
#define REG_SW_EN_MCU_NONPM2MCU_FUART 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_FUART_S 1
#define REG_SW_EN_MCU_NONPM2MCU_FUART_E 1
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX0 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX0_S 2
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX0_E 2
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX1 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX1_S 3
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX1_E 3
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX2 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX2_S 4
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX2_E 4
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX3 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX3_S 5
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX3_E 5
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX4 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX4_S 6
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX4_E 6
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX5 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX5_S 7
#define REG_SW_EN_MCU_NONPM2MCU_MAILBOX5_E 7
#define REG_SW_EN_MCU_NONPM2MCU_MCUIF 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MCUIF_S 8
#define REG_SW_EN_MCU_NONPM2MCU_MCUIF_E 8
#define REG_SW_EN_MCU_NONPM2MCU_MIIC0 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MIIC0_S 9
#define REG_SW_EN_MCU_NONPM2MCU_MIIC0_E 9
#define REG_SW_EN_MCU_NONPM2MCU_MIIC1 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MIIC1_S 10
#define REG_SW_EN_MCU_NONPM2MCU_MIIC1_E 10
#define REG_SW_EN_MCU_NONPM2MCU_MIIC2 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MIIC2_S 11
#define REG_SW_EN_MCU_NONPM2MCU_MIIC2_E 11
#define REG_SW_EN_MCU_NONPM2MCU_MIIC3 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MIIC3_S 12
#define REG_SW_EN_MCU_NONPM2MCU_MIIC3_E 12
#define REG_SW_EN_MCU_NONPM2MCU_MSPI_ALL 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_MSPI_ALL_S 13
#define REG_SW_EN_MCU_NONPM2MCU_MSPI_ALL_E 13
#define REG_SW_EN_MCU_NONPM2MCU_FMLY_ROM 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_FMLY_ROM_S 14
#define REG_SW_EN_MCU_NONPM2MCU_FMLY_ROM_E 14
#define REG_SW_EN_MCU_NONPM2MCU_NONPM_RIU_BRIDGE 0x3b78
#define REG_SW_EN_MCU_NONPM2MCU_NONPM_RIU_BRIDGE_S 15
#define REG_SW_EN_MCU_NONPM2MCU_NONPM_RIU_BRIDGE_E 15
#define REG_SW_EN_MCU_NONPM2MCU_UART0 0x3b7c
#define REG_SW_EN_MCU_NONPM2MCU_UART0_S 1
#define REG_SW_EN_MCU_NONPM2MCU_UART0_E 1
#define REG_SW_EN_MCU_NONPM2MCU_UART1 0x3b7c
#define REG_SW_EN_MCU_NONPM2MCU_UART1_S 2
#define REG_SW_EN_MCU_NONPM2MCU_UART1_E 2
#define REG_SW_EN_MCU_NONPM2MCU_UART2 0x3b7c
#define REG_SW_EN_MCU_NONPM2MCU_UART2_S 3
#define REG_SW_EN_MCU_NONPM2MCU_UART2_E 3
#define REG_SW_EN_MCU_NONPM2MCU_XD2MIU 0x3b7c
#define REG_SW_EN_MCU_NONPM2MCU_XD2MIU_S 4
#define REG_SW_EN_MCU_NONPM2MCU_XD2MIU_E 4
#define REG_SW_EN_MCU_NONPM2MCUSYS_XIU_BRIDGE 0x3b7c
#define REG_SW_EN_MCU_NONPM2MCUSYS_XIU_BRIDGE_S 5
#define REG_SW_EN_MCU_NONPM2MCUSYS_XIU_BRIDGE_E 5
#define REG_SW_EN_MCU_NONPM2MHEG5_SMI 0x3b7c
#define REG_SW_EN_MCU_NONPM2MHEG5_SMI_S 6
#define REG_SW_EN_MCU_NONPM2MHEG5_SMI_E 6
#define REG_SW_EN_MCU_NONPM2PEXTP 0x3b7c
#define REG_SW_EN_MCU_NONPM2PEXTP_S 7
#define REG_SW_EN_MCU_NONPM2PEXTP_E 7
#define REG_SW_EN_MCU_NONPM2PEXTP_PHY_TOP 0x3b7c
#define REG_SW_EN_MCU_NONPM2PEXTP_PHY_TOP_S 8
#define REG_SW_EN_MCU_NONPM2PEXTP_PHY_TOP_E 8
#define REG_SW_EN_MCU_NONPM2PREARB2PM_RIU_TOP 0x3b7c
#define REG_SW_EN_MCU_NONPM2PREARB2PM_RIU_TOP_S 9
#define REG_SW_EN_MCU_NONPM2PREARB2PM_RIU_TOP_E 9
#define REG_SW_EN_MCU_NONPM2RV55FRC 0x3b7c
#define REG_SW_EN_MCU_NONPM2RV55FRC_S 10
#define REG_SW_EN_MCU_NONPM2RV55FRC_E 10
#define REG_SW_EN_MCU_NONPM2RV55PQU 0x3b7c
#define REG_SW_EN_MCU_NONPM2RV55PQU_S 11
#define REG_SW_EN_MCU_NONPM2RV55PQU_E 11
#define REG_SW_EN_MCU_NONPM2SCACE 0x3b7c
#define REG_SW_EN_MCU_NONPM2SCACE_S 12
#define REG_SW_EN_MCU_NONPM2SCACE_E 12
#define REG_SW_EN_MCU_NONPM2SCDV 0x3b7c
#define REG_SW_EN_MCU_NONPM2SCDV_S 13
#define REG_SW_EN_MCU_NONPM2SCDV_E 13
#define REG_SW_EN_MCU_NONPM2SCIP 0x3b7c
#define REG_SW_EN_MCU_NONPM2SCIP_S 14
#define REG_SW_EN_MCU_NONPM2SCIP_E 14
#define REG_SW_EN_MCU_NONPM2SCMW 0x3b7c
#define REG_SW_EN_MCU_NONPM2SCMW_S 15
#define REG_SW_EN_MCU_NONPM2SCMW_E 15
#define REG_SW_EN_MCU_NONPM2SCNR 0x3b80
#define REG_SW_EN_MCU_NONPM2SCNR_S 0
#define REG_SW_EN_MCU_NONPM2SCNR_E 0
#define REG_SW_EN_MCU_NONPM2SCPQ 0x3b80
#define REG_SW_EN_MCU_NONPM2SCPQ_S 1
#define REG_SW_EN_MCU_NONPM2SCPQ_E 1
#define REG_SW_EN_MCU_NONPM2SCSCL 0x3b80
#define REG_SW_EN_MCU_NONPM2SCSCL_S 2
#define REG_SW_EN_MCU_NONPM2SCSCL_E 2
#define REG_SW_EN_MCU_NONPM2SCSR 0x3b80
#define REG_SW_EN_MCU_NONPM2SCSR_S 3
#define REG_SW_EN_MCU_NONPM2SCSR_E 3
#define REG_SW_EN_MCU_NONPM2SCTCON 0x3b80
#define REG_SW_EN_MCU_NONPM2SCTCON_S 4
#define REG_SW_EN_MCU_NONPM2SCTCON_E 4
#define REG_SW_EN_MCU_NONPM2SMART0 0x3b80
#define REG_SW_EN_MCU_NONPM2SMART0_S 5
#define REG_SW_EN_MCU_NONPM2SMART0_E 5
#define REG_SW_EN_MCU_NONPM2SMART1 0x3b80
#define REG_SW_EN_MCU_NONPM2SMART1_S 6
#define REG_SW_EN_MCU_NONPM2SMART1_E 6
#define REG_SW_EN_MCU_NONPM2SSUSB 0x3b80
#define REG_SW_EN_MCU_NONPM2SSUSB_S 7
#define REG_SW_EN_MCU_NONPM2SSUSB_E 7
#define REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP 0x3b80
#define REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_S 8
#define REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_E 8
#define REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_P1 0x3b80
#define REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_P1_S 9
#define REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_P1_E 9
#define REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP 0x3b80
#define REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP_S 10
#define REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP_E 10
#define REG_SW_EN_MCU_NONPM2TSP 0x3b80
#define REG_SW_EN_MCU_NONPM2TSP_S 11
#define REG_SW_EN_MCU_NONPM2TSP_E 11
#define REG_SW_EN_MCU_NONPM2TSP_SMI 0x3b80
#define REG_SW_EN_MCU_NONPM2TSP_SMI_S 12
#define REG_SW_EN_MCU_NONPM2TSP_SMI_E 12
#define REG_SW_EN_MCU_NONPM2UFS 0x3b80
#define REG_SW_EN_MCU_NONPM2UFS_S 13
#define REG_SW_EN_MCU_NONPM2UFS_E 13
#define REG_SW_EN_MCU_NONPM2UFS_PHY 0x3b80
#define REG_SW_EN_MCU_NONPM2UFS_PHY_S 14
#define REG_SW_EN_MCU_NONPM2UFS_PHY_E 14
#define REG_SW_EN_MCU_NONPM2USB20 0x3b80
#define REG_SW_EN_MCU_NONPM2USB20_S 15
#define REG_SW_EN_MCU_NONPM2USB20_E 15
#define REG_SW_EN_MCU_NONPM2VD 0x3b84
#define REG_SW_EN_MCU_NONPM2VD_S 0
#define REG_SW_EN_MCU_NONPM2VD_E 0
#define REG_SW_EN_MCU_NONPM2VENC 0x3b84
#define REG_SW_EN_MCU_NONPM2VENC_S 1
#define REG_SW_EN_MCU_NONPM2VENC_E 1
#define REG_SW_EN_XIU2GCE_BIU 0x3b84
#define REG_SW_EN_XIU2GCE_BIU_S 2
#define REG_SW_EN_XIU2GCE_BIU_E 2
#define REG_SW_EN_MCU_NONPM2XIU2APB 0x3b84
#define REG_SW_EN_MCU_NONPM2XIU2APB_S 3
#define REG_SW_EN_MCU_NONPM2XIU2APB_E 3
#define REG_SW_EN_MCU_NONPM2IP_WRAP 0x3b84
#define REG_SW_EN_MCU_NONPM2IP_WRAP_S 4
#define REG_SW_EN_MCU_NONPM2IP_WRAP_E 4
#define REG_SW_EN_MCU_NONPM2VIVA_SMI 0x3b84
#define REG_SW_EN_MCU_NONPM2VIVA_SMI_S 5
#define REG_SW_EN_MCU_NONPM2VIVA_SMI_E 5
#define REG_SW_EN_MCU_NONPM2VIVA_VBDMA 0x3b84
#define REG_SW_EN_MCU_NONPM2VIVA_VBDMA_S 6
#define REG_SW_EN_MCU_NONPM2VIVA_VBDMA_E 6
#define REG_SW_EN_MCU_NONPM2SCDISP 0x3b84
#define REG_SW_EN_MCU_NONPM2SCDISP_S 11
#define REG_SW_EN_MCU_NONPM2SCDISP_E 11
#define REG_SW_EN_MCU_VD2MCU_M2MCU 0x3bac
#define REG_SW_EN_MCU_VD2MCU_M2MCU_S 0
#define REG_SW_EN_MCU_VD2MCU_M2MCU_E 0
#define REG_SW_EN_MCU_VD2MCU_MCUIF 0x3bac
#define REG_SW_EN_MCU_VD2MCU_MCUIF_S 1
#define REG_SW_EN_MCU_VD2MCU_MCUIF_E 1
#define REG_SW_EN_MCU_VD2VD 0x3bac
#define REG_SW_EN_MCU_VD2VD_S 4
#define REG_SW_EN_MCU_VD2VD_E 4
#define REG_SW_EN_MCU_SC2RV55FRC 0x3bb4
#define REG_SW_EN_MCU_SC2RV55FRC_S 0
#define REG_SW_EN_MCU_SC2RV55FRC_E 0
#define REG_SW_EN_MCU_SC2RV55PQU 0x3bb4
#define REG_SW_EN_MCU_SC2RV55PQU_S 1
#define REG_SW_EN_MCU_SC2RV55PQU_E 1
#define REG_SW_EN_MCU_XC2SCACE 0x3bb4
#define REG_SW_EN_MCU_XC2SCACE_S 2
#define REG_SW_EN_MCU_XC2SCACE_E 2
#define REG_SW_EN_MCU_XC2SCDV 0x3bb4
#define REG_SW_EN_MCU_XC2SCDV_S 3
#define REG_SW_EN_MCU_XC2SCDV_E 3
#define REG_SW_EN_MCU_XC2SCIP 0x3bb4
#define REG_SW_EN_MCU_XC2SCIP_S 4
#define REG_SW_EN_MCU_XC2SCIP_E 4
#define REG_SW_EN_MCU_XC2SCMW 0x3bb4
#define REG_SW_EN_MCU_XC2SCMW_S 5
#define REG_SW_EN_MCU_XC2SCMW_E 5
#define REG_SW_EN_MCU_XC2SCNR 0x3bb4
#define REG_SW_EN_MCU_XC2SCNR_S 6
#define REG_SW_EN_MCU_XC2SCNR_E 6
#define REG_SW_EN_MCU_XC2SCPQ 0x3bb4
#define REG_SW_EN_MCU_XC2SCPQ_S 7
#define REG_SW_EN_MCU_XC2SCPQ_E 7
#define REG_SW_EN_MCU_XC2SCSCL 0x3bb4
#define REG_SW_EN_MCU_XC2SCSCL_S 8
#define REG_SW_EN_MCU_XC2SCSCL_E 8
#define REG_SW_EN_MCU_XC2SCSR 0x3bb4
#define REG_SW_EN_MCU_XC2SCSR_S 9
#define REG_SW_EN_MCU_XC2SCSR_E 9
#define REG_SW_EN_MCU_XC2SCTCON 0x3bb4
#define REG_SW_EN_MCU_XC2SCTCON_S 10
#define REG_SW_EN_MCU_XC2SCTCON_E 10
#define REG_SW_EN_MCU_XC2SCDISP 0x3bb4
#define REG_SW_EN_MCU_XC2SCDISP_S 11
#define REG_SW_EN_MCU_XC2SCDISP_E 11
#define REG_SW_EN_MIIC02MCU_MIIC0 0x3bc4
#define REG_SW_EN_MIIC02MCU_MIIC0_S 0
#define REG_SW_EN_MIIC02MCU_MIIC0_E 0
#define REG_SW_EN_MIIC12MCU_MIIC1 0x3bc8
#define REG_SW_EN_MIIC12MCU_MIIC1_S 0
#define REG_SW_EN_MIIC12MCU_MIIC1_E 0
#define REG_SW_EN_MIIC22MCU_MIIC2 0x3bcc
#define REG_SW_EN_MIIC22MCU_MIIC2_S 0
#define REG_SW_EN_MIIC22MCU_MIIC2_E 0
#define REG_SW_EN_MIIC32MCU_MIIC3 0x3bd0
#define REG_SW_EN_MIIC32MCU_MIIC3_S 0
#define REG_SW_EN_MIIC32MCU_MIIC3_E 0
#define REG_SW_EN_MSPI12MCU_MSPI1 0x3be4
#define REG_SW_EN_MSPI12MCU_MSPI1_S 0
#define REG_SW_EN_MSPI12MCU_MSPI1_E 0
#define REG_SW_EN_MSPI22MCU_MSPI2 0x3be8
#define REG_SW_EN_MSPI22MCU_MSPI2_S 0
#define REG_SW_EN_MSPI22MCU_MSPI2_E 0
#define REG_SW_EN_MSPI32MCU_MSPI3 0x3bec
#define REG_SW_EN_MSPI32MCU_MSPI3_S 0
#define REG_SW_EN_MSPI32MCU_MSPI3_E 0
#define REG_SW_EN_MSPI42MCU_MSPI4 0x3bf0
#define REG_SW_EN_MSPI42MCU_MSPI4_S 0
#define REG_SW_EN_MSPI42MCU_MSPI4_E 0
#define REG_SW_EN_MSPI52MCU_MSPI5 0x3bf4
#define REG_SW_EN_MSPI52MCU_MSPI5_S 0
#define REG_SW_EN_MSPI52MCU_MSPI5_E 0
#define REG_SW_EN_MSPI62MCU_MSPI6 0x3bf8
#define REG_SW_EN_MSPI62MCU_MSPI6_S 0
#define REG_SW_EN_MSPI62MCU_MSPI6_E 0
#define REG_SW_EN_MSPI72MCU_MSPI7 0x3bfc
#define REG_SW_EN_MSPI72MCU_MSPI7_S 0
#define REG_SW_EN_MSPI72MCU_MSPI7_E 0
#define REG_SW_EN_MSPI_CILINK_DIV2MCU_CKCTRL_TOP 0x3c00
#define REG_SW_EN_MSPI_CILINK_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI_CILINK_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI_CILINK2MCU_MSPI_CILINK 0x3c04
#define REG_SW_EN_MSPI_CILINK2MCU_MSPI_CILINK_S 0
#define REG_SW_EN_MSPI_CILINK2MCU_MSPI_CILINK_E 0
#define REG_SW_EN_MSPI0_DIV2MCU_CKCTRL_TOP 0x3c08
#define REG_SW_EN_MSPI0_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI0_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI1_DIV2MCU_CKCTRL_TOP 0x3c0c
#define REG_SW_EN_MSPI1_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI1_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI2_DIV2MCU_CKCTRL_TOP 0x3c10
#define REG_SW_EN_MSPI2_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI2_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI02MCU_MSPI0 0x3c14
#define REG_SW_EN_MSPI02MCU_MSPI0_S 0
#define REG_SW_EN_MSPI02MCU_MSPI0_E 0
#define REG_SW_EN_MSPI3_DIV2MCU_CKCTRL_TOP 0x3c18
#define REG_SW_EN_MSPI3_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI3_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI4_DIV2MCU_CKCTRL_TOP 0x3c1c
#define REG_SW_EN_MSPI4_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI4_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI5_DIV2MCU_CKCTRL_TOP 0x3c20
#define REG_SW_EN_MSPI5_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI5_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI6_DIV2MCU_CKCTRL_TOP 0x3c24
#define REG_SW_EN_MSPI6_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI6_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_MSPI7_DIV2MCU_CKCTRL_TOP 0x3c28
#define REG_SW_EN_MSPI7_DIV2MCU_CKCTRL_TOP_S 0
#define REG_SW_EN_MSPI7_DIV2MCU_CKCTRL_TOP_E 0
#define REG_SW_EN_SPI2MCU_SPI 0x3c34
#define REG_SW_EN_SPI2MCU_SPI_S 0
#define REG_SW_EN_SPI2MCU_SPI_E 0
#define REG_SW_EN_SPI2MCUSYS_XIU_BRIDGE 0x3c34
#define REG_SW_EN_SPI2MCUSYS_XIU_BRIDGE_S 1
#define REG_SW_EN_SPI2MCUSYS_XIU_BRIDGE_E 1
#define REG_SW_EN_XTAL_12M2PEXTP_PHY_TOP 0x3c54
#define REG_SW_EN_XTAL_12M2PEXTP_PHY_TOP_S 0
#define REG_SW_EN_XTAL_12M2PEXTP_PHY_TOP_E 0
#define REG_SW_EN_PEXTP_AHB_APB2PEXTP 0x3c58
#define REG_SW_EN_PEXTP_AHB_APB2PEXTP_S 0
#define REG_SW_EN_PEXTP_AHB_APB2PEXTP_E 0
#define REG_SW_EN_PEXTP_PL_PCLK2PEXTP 0x3c60
#define REG_SW_EN_PEXTP_PL_PCLK2PEXTP_S 0
#define REG_SW_EN_PEXTP_PL_PCLK2PEXTP_E 0
#define REG_SW_EN_PEXTP_TL2PEXTP 0x3c64
#define REG_SW_EN_PEXTP_TL2PEXTP_S 0
#define REG_SW_EN_PEXTP_TL2PEXTP_E 0
#define REG_SW_EN_UFS_AES2UFS 0x3c78
#define REG_SW_EN_UFS_AES2UFS_S 0
#define REG_SW_EN_UFS_AES2UFS_E 0
#define REG_SW_EN_UFS_AHB2UFS 0x3c7c
#define REG_SW_EN_UFS_AHB2UFS_S 0
#define REG_SW_EN_UFS_AHB2UFS_E 0
#define REG_SW_EN_UFS_MP_SAP_CFG2UFS 0x3c84
#define REG_SW_EN_UFS_MP_SAP_CFG2UFS_S 0
#define REG_SW_EN_UFS_MP_SAP_CFG2UFS_E 0
#define REG_SW_EN_UFS_RX_SYMBOL2UFS 0x3c88
#define REG_SW_EN_UFS_RX_SYMBOL2UFS_S 0
#define REG_SW_EN_UFS_RX_SYMBOL2UFS_E 0
#define REG_SW_EN_UFS_TX_SYMBOL2UFS 0x3c8c
#define REG_SW_EN_UFS_TX_SYMBOL2UFS_S 0
#define REG_SW_EN_UFS_TX_SYMBOL2UFS_E 0
#define REG_SW_EN_UFS_UNIPRO_CG_SYN2UFS 0x3c90
#define REG_SW_EN_UFS_UNIPRO_CG_SYN2UFS_S 0
#define REG_SW_EN_UFS_UNIPRO_CG_SYN2UFS_E 0
#define REG_SW_EN_UFS2UFS 0x3c94
#define REG_SW_EN_UFS2UFS_S 0
#define REG_SW_EN_UFS2UFS_E 0
#define REG_SW_EN_UFS_PHY_SCAN_150M2UFS_PHY 0x3c98
#define REG_SW_EN_UFS_PHY_SCAN_150M2UFS_PHY_S 0
#define REG_SW_EN_UFS_PHY_SCAN_150M2UFS_PHY_E 0
#define REG_SW_EN_UFS_PHY_SCAN_300M2UFS_PHY 0x3c9c
#define REG_SW_EN_UFS_PHY_SCAN_300M2UFS_PHY_S 0
#define REG_SW_EN_UFS_PHY_SCAN_300M2UFS_PHY_E 0
#define REG_SW_EN_UFS_PHY_SCAN_600M2UFS_PHY 0x3ca0
#define REG_SW_EN_UFS_PHY_SCAN_600M2UFS_PHY_S 0
#define REG_SW_EN_UFS_PHY_SCAN_600M2UFS_PHY_E 0
#define REG_SW_EN_UFS_PHY_SCAN_26M2UFS_PHY 0x3ca4
#define REG_SW_EN_UFS_PHY_SCAN_26M2UFS_PHY_S 0
#define REG_SW_EN_UFS_PHY_SCAN_26M2UFS_PHY_E 0
#define REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP 0x3cb4
#define REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_S 0
#define REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_E 0
#define REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_P1 0x3cb8
#define REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_P1_S 0
#define REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_P1_E 0
#define REG_SW_EN_XTAL_12M2SSUSB_U2_PHY_TOP 0x3cbc
#define REG_SW_EN_XTAL_12M2SSUSB_U2_PHY_TOP_S 0
#define REG_SW_EN_XTAL_12M2SSUSB_U2_PHY_TOP_E 0
#define REG_SW_EN_SSUSB_FRMCNT2SSUSB 0x3cc0
#define REG_SW_EN_SSUSB_FRMCNT2SSUSB_S 0
#define REG_SW_EN_SSUSB_FRMCNT2SSUSB_E 0
#define REG_SW_EN_SSUSB_PCLK_1P2SSUSB 0x3cc4
#define REG_SW_EN_SSUSB_PCLK_1P2SSUSB_S 0
#define REG_SW_EN_SSUSB_PCLK_1P2SSUSB_E 0
#define REG_SW_EN_SSUSB_PCLK2SSUSB 0x3cc8
#define REG_SW_EN_SSUSB_PCLK2SSUSB_S 0
#define REG_SW_EN_SSUSB_PCLK2SSUSB_E 0
#define REG_SW_EN_SSUSB_SCL2SSUSB 0x3ccc
#define REG_SW_EN_SSUSB_SCL2SSUSB_S 0
#define REG_SW_EN_SSUSB_SCL2SSUSB_E 0
#define REG_SW_EN_SSUSB_SDIN2SSUSB 0x3cd0
#define REG_SW_EN_SSUSB_SDIN2SSUSB_S 0
#define REG_SW_EN_SSUSB_SDIN2SSUSB_E 0
#define REG_SW_EN_SSUSB_SYS2SSUSB 0x3cd4
#define REG_SW_EN_SSUSB_SYS2SSUSB_S 0
#define REG_SW_EN_SSUSB_SYS2SSUSB_E 0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK_1P2SSUSB 0x3cd8
#define REG_SW_EN_SSUSB_USB20_PHY_CLK_1P2SSUSB_S 0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK_1P2SSUSB_E 0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK_2P2SSUSB 0x3cdc
#define REG_SW_EN_SSUSB_USB20_PHY_CLK_2P2SSUSB_S 0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK_2P2SSUSB_E 0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK2SSUSB 0x3ce0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK2SSUSB_S 0
#define REG_SW_EN_SSUSB_USB20_PHY_CLK2SSUSB_E 0
#define REG_SW_EN_SSUSB_XHCI2SSUSB 0x3ce4
#define REG_SW_EN_SSUSB_XHCI2SSUSB_S 0
#define REG_SW_EN_SSUSB_XHCI2SSUSB_E 0
#define REG_SW_EN_USBPHY240_MUX2USB20_SHBG 0x3ce8
#define REG_SW_EN_USBPHY240_MUX2USB20_SHBG_S 0
#define REG_SW_EN_USBPHY240_MUX2USB20_SHBG_E 0
#define REG_SW_EN_USBPHY2402USB20_SHBG 0x3cec
#define REG_SW_EN_USBPHY2402USB20_SHBG_S 0
#define REG_SW_EN_USBPHY2402USB20_SHBG_E 0
#define REG_SW_EN_USBPHY302USB20_SHBG 0x3cf0
#define REG_SW_EN_USBPHY302USB20_SHBG_S 0
#define REG_SW_EN_USBPHY302USB20_SHBG_E 0
#define REG_SW_EN_SSUSB_MISC_48M2SSUSB 0x3cf4
#define REG_SW_EN_SSUSB_MISC_48M2SSUSB_S 0
#define REG_SW_EN_SSUSB_MISC_48M2SSUSB_E 0
#define REG_SW_EN_P0_CLK_TMDSPLL_TEST_DIG2MAC 0x3d14
#define REG_SW_EN_P0_CLK_TMDSPLL_TEST_DIG2MAC_S 0
#define REG_SW_EN_P0_CLK_TMDSPLL_TEST_DIG2MAC_E 0
#define REG_SW_EN_P1_CLK_TMDSPLL_TEST_DIG2MAC 0x3d18
#define REG_SW_EN_P1_CLK_TMDSPLL_TEST_DIG2MAC_S 0
#define REG_SW_EN_P1_CLK_TMDSPLL_TEST_DIG2MAC_E 0
#define REG_SW_EN_P2_CLK_TMDSPLL_TEST_DIG2MAC 0x3d1c
#define REG_SW_EN_P2_CLK_TMDSPLL_TEST_DIG2MAC_S 0
#define REG_SW_EN_P2_CLK_TMDSPLL_TEST_DIG2MAC_E 0
#define REG_SW_EN_P3_CLK_TMDSPLL_TEST_DIG2MAC 0x3d20
#define REG_SW_EN_P3_CLK_TMDSPLL_TEST_DIG2MAC_S 0
#define REG_SW_EN_P3_CLK_TMDSPLL_TEST_DIG2MAC_E 0
#define REG_SW_EN_CLK_128FS_FB_S0_FF2MAC 0x3d24
#define REG_SW_EN_CLK_128FS_FB_S0_FF2MAC_S 0
#define REG_SW_EN_CLK_128FS_FB_S0_FF2MAC_E 0
#define REG_SW_EN_CLK_128FS_FB_S1_FF2MAC 0x3d28
#define REG_SW_EN_CLK_128FS_FB_S1_FF2MAC_S 0
#define REG_SW_EN_CLK_128FS_FB_S1_FF2MAC_E 0
#define REG_SW_EN_XTAL_24M2MHEG5_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2MHEG5_MBIST_S 0
#define REG_SW_EN_XTAL_24M2MHEG5_MBIST_E 0
#define REG_SW_EN_XTAL_24M2TSP_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2TSP_MBIST_S 1
#define REG_SW_EN_XTAL_24M2TSP_MBIST_E 1
#define REG_SW_EN_XTAL_24M2DEMOD0_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2DEMOD0_MBIST_S 2
#define REG_SW_EN_XTAL_24M2DEMOD0_MBIST_E 2
#define REG_SW_EN_XTAL_24M2DEMOD1_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2DEMOD1_MBIST_S 3
#define REG_SW_EN_XTAL_24M2DEMOD1_MBIST_E 3
#define REG_SW_EN_GCE_F26M2VDEC_SOC_MBIST 0x3d80
#define REG_SW_EN_GCE_F26M2VDEC_SOC_MBIST_S 4
#define REG_SW_EN_GCE_F26M2VDEC_SOC_MBIST_E 4
#define REG_SW_EN_XTAL_24M2VDEC_CORE0_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2VDEC_CORE0_MBIST_S 5
#define REG_SW_EN_XTAL_24M2VDEC_CORE0_MBIST_E 5
#define REG_SW_EN_XTAL_24M2VDEC_CORE1_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2VDEC_CORE1_MBIST_S 6
#define REG_SW_EN_XTAL_24M2VDEC_CORE1_MBIST_E 6
#define REG_SW_EN_XTAL_24M2AIA_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2AIA_MBIST_S 8
#define REG_SW_EN_XTAL_24M2AIA_MBIST_E 8
#define REG_SW_EN_XTAL_24M2DRAMC0_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2DRAMC0_MBIST_S 9
#define REG_SW_EN_XTAL_24M2DRAMC0_MBIST_E 9
#define REG_SW_EN_XTAL_24M2DRAMC1_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2DRAMC1_MBIST_S 10
#define REG_SW_EN_XTAL_24M2DRAMC1_MBIST_E 10
#define REG_SW_EN_XTAL_24M2DRAMC2_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2DRAMC2_MBIST_S 11
#define REG_SW_EN_XTAL_24M2DRAMC2_MBIST_E 11
#define REG_SW_EN_XTAL_24M2GPU_DIE_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2GPU_DIE_MBIST_S 12
#define REG_SW_EN_XTAL_24M2GPU_DIE_MBIST_E 12
#define REG_SW_EN_XTAL_24M2GPU_NODIE_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2GPU_NODIE_MBIST_S 13
#define REG_SW_EN_XTAL_24M2GPU_NODIE_MBIST_E 13
#define REG_SW_EN_CLK_XTAL_242HDMIRX_MBIST 0x3d80
#define REG_SW_EN_CLK_XTAL_242HDMIRX_MBIST_S 14
#define REG_SW_EN_CLK_XTAL_242HDMIRX_MBIST_E 14
#define REG_SW_EN_XTAL_24M2IP_WRAP_MBIST 0x3d80
#define REG_SW_EN_XTAL_24M2IP_WRAP_MBIST_S 15
#define REG_SW_EN_XTAL_24M2IP_WRAP_MBIST_E 15
#define REG_SW_EN_XTAL_24M2MCUSYS_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2MCUSYS_MBIST_S 0
#define REG_SW_EN_XTAL_24M2MCUSYS_MBIST_E 0
#define REG_SW_EN_XTAL_24M2MOD_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2MOD_MBIST_S 1
#define REG_SW_EN_XTAL_24M2MOD_MBIST_E 1
#define REG_SW_EN_VIVA_XTAL_24M2VIVALDI9_MBIST 0x3d84
#define REG_SW_EN_VIVA_XTAL_24M2VIVALDI9_MBIST_S 2
#define REG_SW_EN_VIVA_XTAL_24M2VIVALDI9_MBIST_E 2
#define REG_SW_EN_XTAL_24M2FRCIOPMRV55_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2FRCIOPMRV55_MBIST_S 5
#define REG_SW_EN_XTAL_24M2FRCIOPMRV55_MBIST_E 5
#define REG_SW_EN_XTAL_24M2RV55FRC_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2RV55FRC_MBIST_S 6
#define REG_SW_EN_XTAL_24M2RV55FRC_MBIST_E 6
#define REG_SW_EN_XTAL_24M2RV55PQU_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2RV55PQU_MBIST_S 7
#define REG_SW_EN_XTAL_24M2RV55PQU_MBIST_E 7
#define REG_SW_EN_XTAL_24M2FRCMEHALO_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2FRCMEHALO_MBIST_S 8
#define REG_SW_EN_XTAL_24M2FRCMEHALO_MBIST_E 8
#define REG_SW_EN_XTAL_24M2FRCMI_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2FRCMI_MBIST_S 10
#define REG_SW_EN_XTAL_24M2FRCMI_MBIST_E 10
#define REG_SW_EN_XTAL_24M2SCACE_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2SCACE_MBIST_S 11
#define REG_SW_EN_XTAL_24M2SCACE_MBIST_E 11
#define REG_SW_EN_XTAL_24M2SCDV_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2SCDV_MBIST_S 12
#define REG_SW_EN_XTAL_24M2SCDV_MBIST_E 12
#define REG_SW_EN_XTAL_24M2SCIP_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2SCIP_MBIST_S 13
#define REG_SW_EN_XTAL_24M2SCIP_MBIST_E 13
#define REG_SW_EN_XTAL_24M2SCMW_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2SCMW_MBIST_S 14
#define REG_SW_EN_XTAL_24M2SCMW_MBIST_E 14
#define REG_SW_EN_XTAL_24M2SCNR_MBIST 0x3d84
#define REG_SW_EN_XTAL_24M2SCNR_MBIST_S 15
#define REG_SW_EN_XTAL_24M2SCNR_MBIST_E 15
#define REG_SW_EN_XTAL_24M2SCPQ_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2SCPQ_MBIST_S 0
#define REG_SW_EN_XTAL_24M2SCPQ_MBIST_E 0
#define REG_SW_EN_XTAL_24M2SCSCL_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2SCSCL_MBIST_S 1
#define REG_SW_EN_XTAL_24M2SCSCL_MBIST_E 1
#define REG_SW_EN_XTAL_24M2SCSR_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2SCSR_MBIST_S 2
#define REG_SW_EN_XTAL_24M2SCSR_MBIST_E 2
#define REG_SW_EN_XTAL_24M2SCTCON_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2SCTCON_MBIST_S 3
#define REG_SW_EN_XTAL_24M2SCTCON_MBIST_E 3
#define REG_SW_EN_XTAL_24M2SCDISP_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2SCDISP_MBIST_S 6
#define REG_SW_EN_XTAL_24M2SCDISP_MBIST_E 6
#define REG_SW_EN_XTAL_24M2VDEC_CORE0_MERGE_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2VDEC_CORE0_MERGE_MBIST_S 7
#define REG_SW_EN_XTAL_24M2VDEC_CORE0_MERGE_MBIST_E 7
#define REG_SW_EN_XTAL_24M2VDEC_CORE1_MERGE_MBIST 0x3d88
#define REG_SW_EN_XTAL_24M2VDEC_CORE1_MERGE_MBIST_S 8
#define REG_SW_EN_XTAL_24M2VDEC_CORE1_MERGE_MBIST_E 8
#define REG_VDEC_CORE1_MERGE_TEST_ENABLE 0x3db8
#define REG_VDEC_CORE1_MERGE_TEST_ENABLE_S 0
#define REG_VDEC_CORE1_MERGE_TEST_ENABLE_E 0
#define REG_VDEC_CORE1_MERGE_TEST_DIV_SEL 0x3db8
#define REG_VDEC_CORE1_MERGE_TEST_DIV_SEL_S 4
#define REG_VDEC_CORE1_MERGE_TEST_DIV_SEL_E 6
#define REG_VDEC_CORE1_MERGE_TEST_SRC_SEL 0x3db8
#define REG_VDEC_CORE1_MERGE_TEST_SRC_SEL_S 8
#define REG_VDEC_CORE1_MERGE_TEST_SRC_SEL_E 15
#define REG_VDEC_CORE0_MERGE_TEST_ENABLE 0x3dbc
#define REG_VDEC_CORE0_MERGE_TEST_ENABLE_S 0
#define REG_VDEC_CORE0_MERGE_TEST_ENABLE_E 0
#define REG_VDEC_CORE0_MERGE_TEST_DIV_SEL 0x3dbc
#define REG_VDEC_CORE0_MERGE_TEST_DIV_SEL_S 4
#define REG_VDEC_CORE0_MERGE_TEST_DIV_SEL_E 6
#define REG_VDEC_CORE0_MERGE_TEST_SRC_SEL 0x3dbc
#define REG_VDEC_CORE0_MERGE_TEST_SRC_SEL_S 8
#define REG_VDEC_CORE0_MERGE_TEST_SRC_SEL_E 15
#define REG_ADCPLL_TEST_ENABLE 0x3dc0
#define REG_ADCPLL_TEST_ENABLE_S 0
#define REG_ADCPLL_TEST_ENABLE_E 0
#define REG_ADCPLL_TEST_DIV_SEL 0x3dc0
#define REG_ADCPLL_TEST_DIV_SEL_S 4
#define REG_ADCPLL_TEST_DIV_SEL_E 6
#define REG_ADCPLL_TEST_SRC_SEL 0x3dc0
#define REG_ADCPLL_TEST_SRC_SEL_S 8
#define REG_ADCPLL_TEST_SRC_SEL_E 15
#define REG_AIA_TOP_TEST_ENABLE 0x3dc4
#define REG_AIA_TOP_TEST_ENABLE_S 0
#define REG_AIA_TOP_TEST_ENABLE_E 0
#define REG_AIA_TOP_TEST_DIV_SEL 0x3dc4
#define REG_AIA_TOP_TEST_DIV_SEL_S 4
#define REG_AIA_TOP_TEST_DIV_SEL_E 6
#define REG_AIA_TOP_TEST_SRC_SEL 0x3dc4
#define REG_AIA_TOP_TEST_SRC_SEL_S 8
#define REG_AIA_TOP_TEST_SRC_SEL_E 15
#define REG_DEMOD0_TEST_ENABLE 0x3dc8
#define REG_DEMOD0_TEST_ENABLE_S 0
#define REG_DEMOD0_TEST_ENABLE_E 0
#define REG_DEMOD0_TEST_DIV_SEL 0x3dc8
#define REG_DEMOD0_TEST_DIV_SEL_S 4
#define REG_DEMOD0_TEST_DIV_SEL_E 6
#define REG_DEMOD0_TEST_SRC_SEL 0x3dc8
#define REG_DEMOD0_TEST_SRC_SEL_S 8
#define REG_DEMOD0_TEST_SRC_SEL_E 15
#define REG_DEMOD1_TEST_ENABLE 0x3dcc
#define REG_DEMOD1_TEST_ENABLE_S 0
#define REG_DEMOD1_TEST_ENABLE_E 0
#define REG_DEMOD1_TEST_DIV_SEL 0x3dcc
#define REG_DEMOD1_TEST_DIV_SEL_S 4
#define REG_DEMOD1_TEST_DIV_SEL_E 6
#define REG_DEMOD1_TEST_SRC_SEL 0x3dcc
#define REG_DEMOD1_TEST_SRC_SEL_S 8
#define REG_DEMOD1_TEST_SRC_SEL_E 15
#define REG_VDEC_SOC_TEST_ENABLE 0x3dd0
#define REG_VDEC_SOC_TEST_ENABLE_S 0
#define REG_VDEC_SOC_TEST_ENABLE_E 0
#define REG_VDEC_SOC_TEST_DIV_SEL 0x3dd0
#define REG_VDEC_SOC_TEST_DIV_SEL_S 4
#define REG_VDEC_SOC_TEST_DIV_SEL_E 6
#define REG_VDEC_SOC_TEST_SRC_SEL 0x3dd0
#define REG_VDEC_SOC_TEST_SRC_SEL_S 8
#define REG_VDEC_SOC_TEST_SRC_SEL_E 15
#define REG_VDEC_CORE0_TEST_ENABLE 0x3dd4
#define REG_VDEC_CORE0_TEST_ENABLE_S 0
#define REG_VDEC_CORE0_TEST_ENABLE_E 0
#define REG_VDEC_CORE0_TEST_DIV_SEL 0x3dd4
#define REG_VDEC_CORE0_TEST_DIV_SEL_S 4
#define REG_VDEC_CORE0_TEST_DIV_SEL_E 6
#define REG_VDEC_CORE0_TEST_SRC_SEL 0x3dd4
#define REG_VDEC_CORE0_TEST_SRC_SEL_S 8
#define REG_VDEC_CORE0_TEST_SRC_SEL_E 15
#define REG_VDEC_CORE1_TEST_ENABLE 0x3dd8
#define REG_VDEC_CORE1_TEST_ENABLE_S 0
#define REG_VDEC_CORE1_TEST_ENABLE_E 0
#define REG_VDEC_CORE1_TEST_DIV_SEL 0x3dd8
#define REG_VDEC_CORE1_TEST_DIV_SEL_S 4
#define REG_VDEC_CORE1_TEST_DIV_SEL_E 6
#define REG_VDEC_CORE1_TEST_SRC_SEL 0x3dd8
#define REG_VDEC_CORE1_TEST_SRC_SEL_S 8
#define REG_VDEC_CORE1_TEST_SRC_SEL_E 15
#define REG_DRAMC0_TEST_ENABLE 0x3de0
#define REG_DRAMC0_TEST_ENABLE_S 0
#define REG_DRAMC0_TEST_ENABLE_E 0
#define REG_DRAMC0_TEST_DIV_SEL 0x3de0
#define REG_DRAMC0_TEST_DIV_SEL_S 4
#define REG_DRAMC0_TEST_DIV_SEL_E 6
#define REG_DRAMC0_TEST_SRC_SEL 0x3de0
#define REG_DRAMC0_TEST_SRC_SEL_S 8
#define REG_DRAMC0_TEST_SRC_SEL_E 15
#define REG_DRAMC1_TEST_ENABLE 0x3de4
#define REG_DRAMC1_TEST_ENABLE_S 0
#define REG_DRAMC1_TEST_ENABLE_E 0
#define REG_DRAMC1_TEST_DIV_SEL 0x3de4
#define REG_DRAMC1_TEST_DIV_SEL_S 4
#define REG_DRAMC1_TEST_DIV_SEL_E 6
#define REG_DRAMC1_TEST_SRC_SEL 0x3de4
#define REG_DRAMC1_TEST_SRC_SEL_S 8
#define REG_DRAMC1_TEST_SRC_SEL_E 15
#define REG_DRAMC2_TEST_ENABLE 0x3de8
#define REG_DRAMC2_TEST_ENABLE_S 0
#define REG_DRAMC2_TEST_ENABLE_E 0
#define REG_DRAMC2_TEST_DIV_SEL 0x3de8
#define REG_DRAMC2_TEST_DIV_SEL_S 4
#define REG_DRAMC2_TEST_DIV_SEL_E 6
#define REG_DRAMC2_TEST_SRC_SEL 0x3de8
#define REG_DRAMC2_TEST_SRC_SEL_S 8
#define REG_DRAMC2_TEST_SRC_SEL_E 15
#define REG_TOP_TEST_ENABLE 0x3dec
#define REG_TOP_TEST_ENABLE_S 0
#define REG_TOP_TEST_ENABLE_E 0
#define REG_TOP_TEST_DIV_SEL 0x3dec
#define REG_TOP_TEST_DIV_SEL_S 4
#define REG_TOP_TEST_DIV_SEL_E 6
#define REG_TOP_TEST_SRC_SEL 0x3dec
#define REG_TOP_TEST_SRC_SEL_S 8
#define REG_TOP_TEST_SRC_SEL_E 15
#define REG_MHEG5_TEST_ENABLE 0x3df0
#define REG_MHEG5_TEST_ENABLE_S 0
#define REG_MHEG5_TEST_ENABLE_E 0
#define REG_MHEG5_TEST_DIV_SEL 0x3df0
#define REG_MHEG5_TEST_DIV_SEL_S 4
#define REG_MHEG5_TEST_DIV_SEL_E 6
#define REG_MHEG5_TEST_SRC_SEL 0x3df0
#define REG_MHEG5_TEST_SRC_SEL_S 8
#define REG_MHEG5_TEST_SRC_SEL_E 15
#define REG_GPU_DIE_TEST_ENABLE 0x3df4
#define REG_GPU_DIE_TEST_ENABLE_S 0
#define REG_GPU_DIE_TEST_ENABLE_E 0
#define REG_GPU_DIE_TEST_DIV_SEL 0x3df4
#define REG_GPU_DIE_TEST_DIV_SEL_S 4
#define REG_GPU_DIE_TEST_DIV_SEL_E 6
#define REG_GPU_DIE_TEST_SRC_SEL 0x3df4
#define REG_GPU_DIE_TEST_SRC_SEL_S 8
#define REG_GPU_DIE_TEST_SRC_SEL_E 15
#define REG_GPU_NODIE_TEST_ENABLE 0x3df8
#define REG_GPU_NODIE_TEST_ENABLE_S 0
#define REG_GPU_NODIE_TEST_ENABLE_E 0
#define REG_GPU_NODIE_TEST_DIV_SEL 0x3df8
#define REG_GPU_NODIE_TEST_DIV_SEL_S 4
#define REG_GPU_NODIE_TEST_DIV_SEL_E 6
#define REG_GPU_NODIE_TEST_SRC_SEL 0x3df8
#define REG_GPU_NODIE_TEST_SRC_SEL_S 8
#define REG_GPU_NODIE_TEST_SRC_SEL_E 15
#define REG_GPU_SHADER_TEST_ENABLE 0x3dfc
#define REG_GPU_SHADER_TEST_ENABLE_S 0
#define REG_GPU_SHADER_TEST_ENABLE_E 0
#define REG_GPU_SHADER_TEST_DIV_SEL 0x3dfc
#define REG_GPU_SHADER_TEST_DIV_SEL_S 4
#define REG_GPU_SHADER_TEST_DIV_SEL_E 6
#define REG_GPU_SHADER_TEST_SRC_SEL 0x3dfc
#define REG_GPU_SHADER_TEST_SRC_SEL_S 8
#define REG_GPU_SHADER_TEST_SRC_SEL_E 15
#define REG_HDMIRX_TEST_ENABLE 0x3e00
#define REG_HDMIRX_TEST_ENABLE_S 0
#define REG_HDMIRX_TEST_ENABLE_E 0
#define REG_HDMIRX_TEST_DIV_SEL 0x3e00
#define REG_HDMIRX_TEST_DIV_SEL_S 4
#define REG_HDMIRX_TEST_DIV_SEL_E 6
#define REG_HDMIRX_TEST_SRC_SEL 0x3e00
#define REG_HDMIRX_TEST_SRC_SEL_S 8
#define REG_HDMIRX_TEST_SRC_SEL_E 15
#define REG_IP_WRAP_TEST_ENABLE 0x3e04
#define REG_IP_WRAP_TEST_ENABLE_S 0
#define REG_IP_WRAP_TEST_ENABLE_E 0
#define REG_IP_WRAP_TEST_DIV_SEL 0x3e04
#define REG_IP_WRAP_TEST_DIV_SEL_S 4
#define REG_IP_WRAP_TEST_DIV_SEL_E 6
#define REG_IP_WRAP_TEST_SRC_SEL 0x3e04
#define REG_IP_WRAP_TEST_SRC_SEL_S 8
#define REG_IP_WRAP_TEST_SRC_SEL_E 15
#define REG_MCUSYS_TEST_ENABLE 0x3e08
#define REG_MCUSYS_TEST_ENABLE_S 0
#define REG_MCUSYS_TEST_ENABLE_E 0
#define REG_MCUSYS_TEST_DIV_SEL 0x3e08
#define REG_MCUSYS_TEST_DIV_SEL_S 4
#define REG_MCUSYS_TEST_DIV_SEL_E 6
#define REG_MCUSYS_TEST_SRC_SEL 0x3e08
#define REG_MCUSYS_TEST_SRC_SEL_S 8
#define REG_MCUSYS_TEST_SRC_SEL_E 15
#define REG_MOD_TEST_ENABLE 0x3e0c
#define REG_MOD_TEST_ENABLE_S 0
#define REG_MOD_TEST_ENABLE_E 0
#define REG_MOD_TEST_DIV_SEL 0x3e0c
#define REG_MOD_TEST_DIV_SEL_S 4
#define REG_MOD_TEST_DIV_SEL_E 6
#define REG_MOD_TEST_SRC_SEL 0x3e0c
#define REG_MOD_TEST_SRC_SEL_S 8
#define REG_MOD_TEST_SRC_SEL_E 15
#define REG_MOD_DOT_TEST_ENABLE 0x3e10
#define REG_MOD_DOT_TEST_ENABLE_S 0
#define REG_MOD_DOT_TEST_ENABLE_E 0
#define REG_MOD_DOT_TEST_DIV_SEL 0x3e10
#define REG_MOD_DOT_TEST_DIV_SEL_S 4
#define REG_MOD_DOT_TEST_DIV_SEL_E 6
#define REG_MOD_DOT_TEST_SRC_SEL 0x3e10
#define REG_MOD_DOT_TEST_SRC_SEL_S 8
#define REG_MOD_DOT_TEST_SRC_SEL_E 15
#define REG_LPLL_TEST_ENABLE 0x3e14
#define REG_LPLL_TEST_ENABLE_S 0
#define REG_LPLL_TEST_ENABLE_E 0
#define REG_LPLL_TEST_DIV_SEL 0x3e14
#define REG_LPLL_TEST_DIV_SEL_S 4
#define REG_LPLL_TEST_DIV_SEL_E 6
#define REG_LPLL_TEST_SRC_SEL 0x3e14
#define REG_LPLL_TEST_SRC_SEL_S 8
#define REG_LPLL_TEST_SRC_SEL_E 15
#define REG_VIVALDI9_TEST_ENABLE 0x3e18
#define REG_VIVALDI9_TEST_ENABLE_S 0
#define REG_VIVALDI9_TEST_ENABLE_E 0
#define REG_VIVALDI9_TEST_DIV_SEL 0x3e18
#define REG_VIVALDI9_TEST_DIV_SEL_S 4
#define REG_VIVALDI9_TEST_DIV_SEL_E 6
#define REG_VIVALDI9_TEST_SRC_SEL 0x3e18
#define REG_VIVALDI9_TEST_SRC_SEL_S 7
#define REG_VIVALDI9_TEST_SRC_SEL_E 15
#define REG_TSP_TEST_ENABLE 0x3e24
#define REG_TSP_TEST_ENABLE_S 0
#define REG_TSP_TEST_ENABLE_E 0
#define REG_TSP_TEST_DIV_SEL 0x3e24
#define REG_TSP_TEST_DIV_SEL_S 4
#define REG_TSP_TEST_DIV_SEL_E 6
#define REG_TSP_TEST_SRC_SEL 0x3e24
#define REG_TSP_TEST_SRC_SEL_S 8
#define REG_TSP_TEST_SRC_SEL_E 15
#define REG_FRCIOPMRV55_TEST_ENABLE 0x3e28
#define REG_FRCIOPMRV55_TEST_ENABLE_S 0
#define REG_FRCIOPMRV55_TEST_ENABLE_E 0
#define REG_FRCIOPMRV55_TEST_DIV_SEL 0x3e28
#define REG_FRCIOPMRV55_TEST_DIV_SEL_S 4
#define REG_FRCIOPMRV55_TEST_DIV_SEL_E 6
#define REG_FRCIOPMRV55_TEST_SRC_SEL 0x3e28
#define REG_FRCIOPMRV55_TEST_SRC_SEL_S 8
#define REG_FRCIOPMRV55_TEST_SRC_SEL_E 15
#define REG_RV55FRC_TEST_ENABLE 0x3e2c
#define REG_RV55FRC_TEST_ENABLE_S 0
#define REG_RV55FRC_TEST_ENABLE_E 0
#define REG_RV55FRC_TEST_DIV_SEL 0x3e2c
#define REG_RV55FRC_TEST_DIV_SEL_S 4
#define REG_RV55FRC_TEST_DIV_SEL_E 6
#define REG_RV55FRC_TEST_SRC_SEL 0x3e2c
#define REG_RV55FRC_TEST_SRC_SEL_S 8
#define REG_RV55FRC_TEST_SRC_SEL_E 15
#define REG_RV55PQU_TEST_ENABLE 0x3e30
#define REG_RV55PQU_TEST_ENABLE_S 0
#define REG_RV55PQU_TEST_ENABLE_E 0
#define REG_RV55PQU_TEST_DIV_SEL 0x3e30
#define REG_RV55PQU_TEST_DIV_SEL_S 4
#define REG_RV55PQU_TEST_DIV_SEL_E 6
#define REG_RV55PQU_TEST_SRC_SEL 0x3e30
#define REG_RV55PQU_TEST_SRC_SEL_S 8
#define REG_RV55PQU_TEST_SRC_SEL_E 15
#define REG_FRCMEHALO_TEST_ENABLE 0x3e34
#define REG_FRCMEHALO_TEST_ENABLE_S 0
#define REG_FRCMEHALO_TEST_ENABLE_E 0
#define REG_FRCMEHALO_TEST_DIV_SEL 0x3e34
#define REG_FRCMEHALO_TEST_DIV_SEL_S 4
#define REG_FRCMEHALO_TEST_DIV_SEL_E 6
#define REG_FRCMEHALO_TEST_SRC_SEL 0x3e34
#define REG_FRCMEHALO_TEST_SRC_SEL_S 8
#define REG_FRCMEHALO_TEST_SRC_SEL_E 15
#define REG_FRCMI_TEST_ENABLE 0x3e3c
#define REG_FRCMI_TEST_ENABLE_S 0
#define REG_FRCMI_TEST_ENABLE_E 0
#define REG_FRCMI_TEST_DIV_SEL 0x3e3c
#define REG_FRCMI_TEST_DIV_SEL_S 4
#define REG_FRCMI_TEST_DIV_SEL_E 6
#define REG_FRCMI_TEST_SRC_SEL 0x3e3c
#define REG_FRCMI_TEST_SRC_SEL_S 8
#define REG_FRCMI_TEST_SRC_SEL_E 15
#define REG_SCACE_TEST_ENABLE 0x3e40
#define REG_SCACE_TEST_ENABLE_S 0
#define REG_SCACE_TEST_ENABLE_E 0
#define REG_SCACE_TEST_DIV_SEL 0x3e40
#define REG_SCACE_TEST_DIV_SEL_S 4
#define REG_SCACE_TEST_DIV_SEL_E 6
#define REG_SCACE_TEST_SRC_SEL 0x3e40
#define REG_SCACE_TEST_SRC_SEL_S 8
#define REG_SCACE_TEST_SRC_SEL_E 15
#define REG_SCDV_TEST_ENABLE 0x3e44
#define REG_SCDV_TEST_ENABLE_S 0
#define REG_SCDV_TEST_ENABLE_E 0
#define REG_SCDV_TEST_DIV_SEL 0x3e44
#define REG_SCDV_TEST_DIV_SEL_S 4
#define REG_SCDV_TEST_DIV_SEL_E 6
#define REG_SCDV_TEST_SRC_SEL 0x3e44
#define REG_SCDV_TEST_SRC_SEL_S 8
#define REG_SCDV_TEST_SRC_SEL_E 15
#define REG_SCIP_TEST_ENABLE 0x3e48
#define REG_SCIP_TEST_ENABLE_S 0
#define REG_SCIP_TEST_ENABLE_E 0
#define REG_SCIP_TEST_DIV_SEL 0x3e48
#define REG_SCIP_TEST_DIV_SEL_S 4
#define REG_SCIP_TEST_DIV_SEL_E 6
#define REG_SCIP_TEST_SRC_SEL 0x3e48
#define REG_SCIP_TEST_SRC_SEL_S 8
#define REG_SCIP_TEST_SRC_SEL_E 15
#define REG_SCMW_TEST_ENABLE 0x3e4c
#define REG_SCMW_TEST_ENABLE_S 0
#define REG_SCMW_TEST_ENABLE_E 0
#define REG_SCMW_TEST_DIV_SEL 0x3e4c
#define REG_SCMW_TEST_DIV_SEL_S 4
#define REG_SCMW_TEST_DIV_SEL_E 6
#define REG_SCMW_TEST_SRC_SEL 0x3e4c
#define REG_SCMW_TEST_SRC_SEL_S 8
#define REG_SCMW_TEST_SRC_SEL_E 15
#define REG_SCNR_TEST_ENABLE 0x3e50
#define REG_SCNR_TEST_ENABLE_S 0
#define REG_SCNR_TEST_ENABLE_E 0
#define REG_SCNR_TEST_DIV_SEL 0x3e50
#define REG_SCNR_TEST_DIV_SEL_S 4
#define REG_SCNR_TEST_DIV_SEL_E 6
#define REG_SCNR_TEST_SRC_SEL 0x3e50
#define REG_SCNR_TEST_SRC_SEL_S 8
#define REG_SCNR_TEST_SRC_SEL_E 15
#define REG_SCPQ_TEST_ENABLE 0x3e54
#define REG_SCPQ_TEST_ENABLE_S 0
#define REG_SCPQ_TEST_ENABLE_E 0
#define REG_SCPQ_TEST_DIV_SEL 0x3e54
#define REG_SCPQ_TEST_DIV_SEL_S 4
#define REG_SCPQ_TEST_DIV_SEL_E 6
#define REG_SCPQ_TEST_SRC_SEL 0x3e54
#define REG_SCPQ_TEST_SRC_SEL_S 8
#define REG_SCPQ_TEST_SRC_SEL_E 15
#define REG_SCSCL_TEST_ENABLE 0x3e58
#define REG_SCSCL_TEST_ENABLE_S 0
#define REG_SCSCL_TEST_ENABLE_E 0
#define REG_SCSCL_TEST_DIV_SEL 0x3e58
#define REG_SCSCL_TEST_DIV_SEL_S 4
#define REG_SCSCL_TEST_DIV_SEL_E 6
#define REG_SCSCL_TEST_SRC_SEL 0x3e58
#define REG_SCSCL_TEST_SRC_SEL_S 8
#define REG_SCSCL_TEST_SRC_SEL_E 15
#define REG_SCSR_TEST_ENABLE 0x3e5c
#define REG_SCSR_TEST_ENABLE_S 0
#define REG_SCSR_TEST_ENABLE_E 0
#define REG_SCSR_TEST_DIV_SEL 0x3e5c
#define REG_SCSR_TEST_DIV_SEL_S 4
#define REG_SCSR_TEST_DIV_SEL_E 6
#define REG_SCSR_TEST_SRC_SEL 0x3e5c
#define REG_SCSR_TEST_SRC_SEL_S 8
#define REG_SCSR_TEST_SRC_SEL_E 15
#define REG_SCTCON_TEST_ENABLE 0x3e60
#define REG_SCTCON_TEST_ENABLE_S 0
#define REG_SCTCON_TEST_ENABLE_E 0
#define REG_SCTCON_TEST_DIV_SEL 0x3e60
#define REG_SCTCON_TEST_DIV_SEL_S 4
#define REG_SCTCON_TEST_DIV_SEL_E 6
#define REG_SCTCON_TEST_SRC_SEL 0x3e60
#define REG_SCTCON_TEST_SRC_SEL_S 8
#define REG_SCTCON_TEST_SRC_SEL_E 15
#define REG_HDMIRX_DPHY_TEST_ENABLE 0x3e64
#define REG_HDMIRX_DPHY_TEST_ENABLE_S 0
#define REG_HDMIRX_DPHY_TEST_ENABLE_E 0
#define REG_HDMIRX_DPHY_TEST_DIV_SEL 0x3e64
#define REG_HDMIRX_DPHY_TEST_DIV_SEL_S 4
#define REG_HDMIRX_DPHY_TEST_DIV_SEL_E 6
#define REG_HDMIRX_DPHY_TEST_SRC_SEL 0x3e64
#define REG_HDMIRX_DPHY_TEST_SRC_SEL_S 8
#define REG_HDMIRX_DPHY_TEST_SRC_SEL_E 15
#define REG_HDMIRX_APHY_TEST_ENABLE 0x3e68
#define REG_HDMIRX_APHY_TEST_ENABLE_S 0
#define REG_HDMIRX_APHY_TEST_ENABLE_E 0
#define REG_HDMIRX_APHY_TEST_DIV_SEL 0x3e68
#define REG_HDMIRX_APHY_TEST_DIV_SEL_S 4
#define REG_HDMIRX_APHY_TEST_DIV_SEL_E 6
#define REG_HDMIRX_APHY_TEST_SRC_SEL 0x3e68
#define REG_HDMIRX_APHY_TEST_SRC_SEL_S 8
#define REG_HDMIRX_APHY_TEST_SRC_SEL_E 15
#define REG_AUSDM_TEST_ENABLE 0x3e6c
#define REG_AUSDM_TEST_ENABLE_S 0
#define REG_AUSDM_TEST_ENABLE_E 0
#define REG_AUSDM_TEST_DIV_SEL 0x3e6c
#define REG_AUSDM_TEST_DIV_SEL_S 4
#define REG_AUSDM_TEST_DIV_SEL_E 6
#define REG_AUSDM_TEST_SRC_SEL 0x3e6c
#define REG_AUSDM_TEST_SRC_SEL_S 8
#define REG_AUSDM_TEST_SRC_SEL_E 15
#define REG_AUPLL_TEST_ENABLE 0x3e74
#define REG_AUPLL_TEST_ENABLE_S 0
#define REG_AUPLL_TEST_ENABLE_E 0
#define REG_AUPLL_TEST_DIV_SEL 0x3e74
#define REG_AUPLL_TEST_DIV_SEL_S 4
#define REG_AUPLL_TEST_DIV_SEL_E 6
#define REG_AUPLL_TEST_SRC_SEL 0x3e74
#define REG_AUPLL_TEST_SRC_SEL_S 8
#define REG_AUPLL_TEST_SRC_SEL_E 15
#define REG_MCUSYS_DIE_TEST_ENABLE 0x3e78
#define REG_MCUSYS_DIE_TEST_ENABLE_S 0
#define REG_MCUSYS_DIE_TEST_ENABLE_E 0
#define REG_MCUSYS_DIE_TEST_DIV_SEL 0x3e78
#define REG_MCUSYS_DIE_TEST_DIV_SEL_S 4
#define REG_MCUSYS_DIE_TEST_DIV_SEL_E 6
#define REG_MCUSYS_DIE_TEST_SRC_SEL 0x3e78
#define REG_MCUSYS_DIE_TEST_SRC_SEL_S 8
#define REG_MCUSYS_DIE_TEST_SRC_SEL_E 15
#define REG_DMD_ANA_MISC_TEST_ENABLE 0x3e7c
#define REG_DMD_ANA_MISC_TEST_ENABLE_S 0
#define REG_DMD_ANA_MISC_TEST_ENABLE_E 0
#define REG_DMD_ANA_MISC_TEST_DIV_SEL 0x3e7c
#define REG_DMD_ANA_MISC_TEST_DIV_SEL_S 4
#define REG_DMD_ANA_MISC_TEST_DIV_SEL_E 6
#define REG_DMD_ANA_MISC_TEST_SRC_SEL 0x3e7c
#define REG_DMD_ANA_MISC_TEST_SRC_SEL_S 8
#define REG_DMD_ANA_MISC_TEST_SRC_SEL_E 15
#define REG_ARMPLL_TEST_ENABLE 0x3e80
#define REG_ARMPLL_TEST_ENABLE_S 0
#define REG_ARMPLL_TEST_ENABLE_E 0
#define REG_ARMPLL_TEST_DIV_SEL 0x3e80
#define REG_ARMPLL_TEST_DIV_SEL_S 4
#define REG_ARMPLL_TEST_DIV_SEL_E 6
#define REG_ARMPLL_TEST_SRC_SEL 0x3e80
#define REG_ARMPLL_TEST_SRC_SEL_S 8
#define REG_ARMPLL_TEST_SRC_SEL_E 15
#define REG_ARM2PLL_TEST_ENABLE 0x3e84
#define REG_ARM2PLL_TEST_ENABLE_S 0
#define REG_ARM2PLL_TEST_ENABLE_E 0
#define REG_ARM2PLL_TEST_DIV_SEL 0x3e84
#define REG_ARM2PLL_TEST_DIV_SEL_S 4
#define REG_ARM2PLL_TEST_DIV_SEL_E 6
#define REG_ARM2PLL_TEST_SRC_SEL 0x3e84
#define REG_ARM2PLL_TEST_SRC_SEL_S 8
#define REG_ARM2PLL_TEST_SRC_SEL_E 15
#define REG_ARMPLL_GPU_TEST_ENABLE 0x3e88
#define REG_ARMPLL_GPU_TEST_ENABLE_S 0
#define REG_ARMPLL_GPU_TEST_ENABLE_E 0
#define REG_ARMPLL_GPU_TEST_DIV_SEL 0x3e88
#define REG_ARMPLL_GPU_TEST_DIV_SEL_S 4
#define REG_ARMPLL_GPU_TEST_DIV_SEL_E 6
#define REG_ARMPLL_GPU_TEST_SRC_SEL 0x3e88
#define REG_ARMPLL_GPU_TEST_SRC_SEL_S 8
#define REG_ARMPLL_GPU_TEST_SRC_SEL_E 15
#define REG_ARMPLL_APU_TEST_ENABLE 0x3e8c
#define REG_ARMPLL_APU_TEST_ENABLE_S 0
#define REG_ARMPLL_APU_TEST_ENABLE_E 0
#define REG_ARMPLL_APU_TEST_DIV_SEL 0x3e8c
#define REG_ARMPLL_APU_TEST_DIV_SEL_S 4
#define REG_ARMPLL_APU_TEST_DIV_SEL_E 6
#define REG_ARMPLL_APU_TEST_SRC_SEL 0x3e8c
#define REG_ARMPLL_APU_TEST_SRC_SEL_S 8
#define REG_ARMPLL_APU_TEST_SRC_SEL_E 15
#define REG_EARC_DMACRO_TEST_ENABLE 0x3e90
#define REG_EARC_DMACRO_TEST_ENABLE_S 0
#define REG_EARC_DMACRO_TEST_ENABLE_E 0
#define REG_EARC_DMACRO_TEST_DIV_SEL 0x3e90
#define REG_EARC_DMACRO_TEST_DIV_SEL_S 4
#define REG_EARC_DMACRO_TEST_DIV_SEL_E 6
#define REG_EARC_DMACRO_TEST_SRC_SEL 0x3e90
#define REG_EARC_DMACRO_TEST_SRC_SEL_S 8
#define REG_EARC_DMACRO_TEST_SRC_SEL_E 15
#define REG_USB_PHY_TEST_ENABLE 0x3e94
#define REG_USB_PHY_TEST_ENABLE_S 0
#define REG_USB_PHY_TEST_ENABLE_E 0
#define REG_USB_PHY_TEST_DIV_SEL 0x3e94
#define REG_USB_PHY_TEST_DIV_SEL_S 4
#define REG_USB_PHY_TEST_DIV_SEL_E 6
#define REG_USB_PHY_TEST_SRC_SEL 0x3e94
#define REG_USB_PHY_TEST_SRC_SEL_S 8
#define REG_USB_PHY_TEST_SRC_SEL_E 15
#define REG_PCIE_PHY_TEST_ENABLE 0x3e98
#define REG_PCIE_PHY_TEST_ENABLE_S 0
#define REG_PCIE_PHY_TEST_ENABLE_E 0
#define REG_PCIE_PHY_TEST_DIV_SEL 0x3e98
#define REG_PCIE_PHY_TEST_DIV_SEL_S 4
#define REG_PCIE_PHY_TEST_DIV_SEL_E 6
#define REG_PCIE_PHY_TEST_SRC_SEL 0x3e98
#define REG_PCIE_PHY_TEST_SRC_SEL_S 8
#define REG_PCIE_PHY_TEST_SRC_SEL_E 15
#define REG_UFS_PHY_TEST_ENABLE 0x3e9c
#define REG_UFS_PHY_TEST_ENABLE_S 0
#define REG_UFS_PHY_TEST_ENABLE_E 0
#define REG_UFS_PHY_TEST_DIV_SEL 0x3e9c
#define REG_UFS_PHY_TEST_DIV_SEL_S 4
#define REG_UFS_PHY_TEST_DIV_SEL_E 6
#define REG_UFS_PHY_TEST_SRC_SEL 0x3e9c
#define REG_UFS_PHY_TEST_SRC_SEL_S 8
#define REG_UFS_PHY_TEST_SRC_SEL_E 15
#define REG_FLASH_DMACRO_TEST_ENABLE 0x3ea0
#define REG_FLASH_DMACRO_TEST_ENABLE_S 0
#define REG_FLASH_DMACRO_TEST_ENABLE_E 0
#define REG_FLASH_DMACRO_TEST_DIV_SEL 0x3ea0
#define REG_FLASH_DMACRO_TEST_DIV_SEL_S 4
#define REG_FLASH_DMACRO_TEST_DIV_SEL_E 6
#define REG_FLASH_DMACRO_TEST_SRC_SEL 0x3ea0
#define REG_FLASH_DMACRO_TEST_SRC_SEL_S 8
#define REG_FLASH_DMACRO_TEST_SRC_SEL_E 15
#define REG_FLASH_32BIF_TEST_ENABLE 0x3ea4
#define REG_FLASH_32BIF_TEST_ENABLE_S 0
#define REG_FLASH_32BIF_TEST_ENABLE_E 0
#define REG_FLASH_32BIF_TEST_DIV_SEL 0x3ea4
#define REG_FLASH_32BIF_TEST_DIV_SEL_S 4
#define REG_FLASH_32BIF_TEST_DIV_SEL_E 6
#define REG_FLASH_32BIF_TEST_SRC_SEL 0x3ea4
#define REG_FLASH_32BIF_TEST_SRC_SEL_S 8
#define REG_FLASH_32BIF_TEST_SRC_SEL_E 15
#define REG_FLASH_8BIT_TEST_ENABLE 0x3ea8
#define REG_FLASH_8BIT_TEST_ENABLE_S 0
#define REG_FLASH_8BIT_TEST_ENABLE_E 0
#define REG_FLASH_8BIT_TEST_DIV_SEL 0x3ea8
#define REG_FLASH_8BIT_TEST_DIV_SEL_S 4
#define REG_FLASH_8BIT_TEST_DIV_SEL_E 6
#define REG_FLASH_8BIT_TEST_SRC_SEL 0x3ea8
#define REG_FLASH_8BIT_TEST_SRC_SEL_S 8
#define REG_FLASH_8BIT_TEST_SRC_SEL_E 15
#define REG_SD_SDR_MACRO_TEST_ENABLE 0x3eac
#define REG_SD_SDR_MACRO_TEST_ENABLE_S 0
#define REG_SD_SDR_MACRO_TEST_ENABLE_E 0
#define REG_SD_SDR_MACRO_TEST_DIV_SEL 0x3eac
#define REG_SD_SDR_MACRO_TEST_DIV_SEL_S 4
#define REG_SD_SDR_MACRO_TEST_DIV_SEL_E 6
#define REG_SD_SDR_MACRO_TEST_SRC_SEL 0x3eac
#define REG_SD_SDR_MACRO_TEST_SRC_SEL_S 8
#define REG_SD_SDR_MACRO_TEST_SRC_SEL_E 15
#define REG_VDECPLL_DMACRO_TEST_ENABLE 0x3eb0
#define REG_VDECPLL_DMACRO_TEST_ENABLE_S 0
#define REG_VDECPLL_DMACRO_TEST_ENABLE_E 0
#define REG_VDECPLL_DMACRO_TEST_DIV_SEL 0x3eb0
#define REG_VDECPLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_VDECPLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_VDECPLL_DMACRO_TEST_SRC_SEL 0x3eb0
#define REG_VDECPLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_VDECPLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_SYS0PLL_DMACRO_TEST_ENABLE 0x3eb4
#define REG_SYS0PLL_DMACRO_TEST_ENABLE_S 0
#define REG_SYS0PLL_DMACRO_TEST_ENABLE_E 0
#define REG_SYS0PLL_DMACRO_TEST_DIV_SEL 0x3eb4
#define REG_SYS0PLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_SYS0PLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_SYS0PLL_DMACRO_TEST_SRC_SEL 0x3eb4
#define REG_SYS0PLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_SYS0PLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_SYS1PLL_DMACRO_TEST_ENABLE 0x3eb8
#define REG_SYS1PLL_DMACRO_TEST_ENABLE_S 0
#define REG_SYS1PLL_DMACRO_TEST_ENABLE_E 0
#define REG_SYS1PLL_DMACRO_TEST_DIV_SEL 0x3eb8
#define REG_SYS1PLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_SYS1PLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_SYS1PLL_DMACRO_TEST_SRC_SEL 0x3eb8
#define REG_SYS1PLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_SYS1PLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_SYS2PLL_DMACRO_TEST_ENABLE 0x3ebc
#define REG_SYS2PLL_DMACRO_TEST_ENABLE_S 0
#define REG_SYS2PLL_DMACRO_TEST_ENABLE_E 0
#define REG_SYS2PLL_DMACRO_TEST_DIV_SEL 0x3ebc
#define REG_SYS2PLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_SYS2PLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_SYS2PLL_DMACRO_TEST_SRC_SEL 0x3ebc
#define REG_SYS2PLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_SYS2PLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_RV55FRCPLL_DMACRO_TEST_ENABLE 0x3ec0
#define REG_RV55FRCPLL_DMACRO_TEST_ENABLE_S 0
#define REG_RV55FRCPLL_DMACRO_TEST_ENABLE_E 0
#define REG_RV55FRCPLL_DMACRO_TEST_DIV_SEL 0x3ec0
#define REG_RV55FRCPLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_RV55FRCPLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_RV55FRCPLL_DMACRO_TEST_SRC_SEL 0x3ec0
#define REG_RV55FRCPLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_RV55FRCPLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_XCPLL_DMACRO_TEST_ENABLE 0x3ec4
#define REG_XCPLL_DMACRO_TEST_ENABLE_S 0
#define REG_XCPLL_DMACRO_TEST_ENABLE_E 0
#define REG_XCPLL_DMACRO_TEST_DIV_SEL 0x3ec4
#define REG_XCPLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_XCPLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_XCPLL_DMACRO_TEST_SRC_SEL 0x3ec4
#define REG_XCPLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_XCPLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_XCSRSPLL_DMACRO_TEST_ENABLE 0x3ec8
#define REG_XCSRSPLL_DMACRO_TEST_ENABLE_S 0
#define REG_XCSRSPLL_DMACRO_TEST_ENABLE_E 0
#define REG_XCSRSPLL_DMACRO_TEST_DIV_SEL 0x3ec8
#define REG_XCSRSPLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_XCSRSPLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_XCSRSPLL_DMACRO_TEST_SRC_SEL 0x3ec8
#define REG_XCSRSPLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_XCSRSPLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_SYS3PLL_DMACRO_TEST_ENABLE 0x3ecc
#define REG_SYS3PLL_DMACRO_TEST_ENABLE_S 0
#define REG_SYS3PLL_DMACRO_TEST_ENABLE_E 0
#define REG_SYS3PLL_DMACRO_TEST_DIV_SEL 0x3ecc
#define REG_SYS3PLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_SYS3PLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_SYS3PLL_DMACRO_TEST_SRC_SEL 0x3ecc
#define REG_SYS3PLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_SYS3PLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_GPUBRDGPLL_DMACRO_TEST_ENABLE 0x3ed0
#define REG_GPUBRDGPLL_DMACRO_TEST_ENABLE_S 0
#define REG_GPUBRDGPLL_DMACRO_TEST_ENABLE_E 0
#define REG_GPUBRDGPLL_DMACRO_TEST_DIV_SEL 0x3ed0
#define REG_GPUBRDGPLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_GPUBRDGPLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_GPUBRDGPLL_DMACRO_TEST_SRC_SEL 0x3ed0
#define REG_GPUBRDGPLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_GPUBRDGPLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_APUBUSPLL_DMACRO_TEST_ENABLE 0x3ed4
#define REG_APUBUSPLL_DMACRO_TEST_ENABLE_S 0
#define REG_APUBUSPLL_DMACRO_TEST_ENABLE_E 0
#define REG_APUBUSPLL_DMACRO_TEST_DIV_SEL 0x3ed4
#define REG_APUBUSPLL_DMACRO_TEST_DIV_SEL_S 4
#define REG_APUBUSPLL_DMACRO_TEST_DIV_SEL_E 6
#define REG_APUBUSPLL_DMACRO_TEST_SRC_SEL 0x3ed4
#define REG_APUBUSPLL_DMACRO_TEST_SRC_SEL_S 8
#define REG_APUBUSPLL_DMACRO_TEST_SRC_SEL_E 15
#define REG_SCDISP_TEST_ENABLE 0x3ee8
#define REG_SCDISP_TEST_ENABLE_S 0
#define REG_SCDISP_TEST_ENABLE_E 0
#define REG_SCDISP_TEST_DIV_SEL 0x3ee8
#define REG_SCDISP_TEST_DIV_SEL_S 4
#define REG_SCDISP_TEST_DIV_SEL_E 6
#define REG_SCDISP_TEST_SRC_SEL 0x3ee8
#define REG_SCDISP_TEST_SRC_SEL_S 8
#define REG_SCDISP_TEST_SRC_SEL_E 15
#define REG_DISP_MFDEC_BRG_TEST_ENABLE 0x3eec
#define REG_DISP_MFDEC_BRG_TEST_ENABLE_S 0
#define REG_DISP_MFDEC_BRG_TEST_ENABLE_E 0
#define REG_DISP_MFDEC_BRG_TEST_DIV_SEL 0x3eec
#define REG_DISP_MFDEC_BRG_TEST_DIV_SEL_S 4
#define REG_DISP_MFDEC_BRG_TEST_DIV_SEL_E 6
#define REG_DISP_MFDEC_BRG_TEST_SRC_SEL 0x3eec
#define REG_DISP_MFDEC_BRG_TEST_SRC_SEL_S 8
#define REG_DISP_MFDEC_BRG_TEST_SRC_SEL_E 15
#define REG_GATE_INV_WLOCK_PASSWD 0x3f38
#define REG_GATE_INV_WLOCK_PASSWD_S 0
#define REG_GATE_INV_WLOCK_PASSWD_E 15
#define REG_ALL_SW_EN_PASSWD 0x3f3c
#define REG_ALL_SW_EN_PASSWD_S 0
#define REG_ALL_SW_EN_PASSWD_E 15
#define REG_XCPLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_XCPLL_DMACRO_ALL_SW_EN_OVERWRITE_S 0
#define REG_XCPLL_DMACRO_ALL_SW_EN_OVERWRITE_E 0
#define REG_XCSRSPLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_XCSRSPLL_DMACRO_ALL_SW_EN_OVERWRITE_S 1
#define REG_XCSRSPLL_DMACRO_ALL_SW_EN_OVERWRITE_E 1
#define REG_VDECPLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_VDECPLL_DMACRO_ALL_SW_EN_OVERWRITE_S 2
#define REG_VDECPLL_DMACRO_ALL_SW_EN_OVERWRITE_E 2
#define REG_SYS0PLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_SYS0PLL_DMACRO_ALL_SW_EN_OVERWRITE_S 3
#define REG_SYS0PLL_DMACRO_ALL_SW_EN_OVERWRITE_E 3
#define REG_SYS1PLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_SYS1PLL_DMACRO_ALL_SW_EN_OVERWRITE_S 4
#define REG_SYS1PLL_DMACRO_ALL_SW_EN_OVERWRITE_E 4
#define REG_SYS2PLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_SYS2PLL_DMACRO_ALL_SW_EN_OVERWRITE_S 5
#define REG_SYS2PLL_DMACRO_ALL_SW_EN_OVERWRITE_E 5
#define REG_SYS3PLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_SYS3PLL_DMACRO_ALL_SW_EN_OVERWRITE_S 6
#define REG_SYS3PLL_DMACRO_ALL_SW_EN_OVERWRITE_E 6
#define REG_ARMPLL_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_ARMPLL_ALL_SW_EN_OVERWRITE_S 7
#define REG_ARMPLL_ALL_SW_EN_OVERWRITE_E 7
#define REG_ARM2PLL_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_ARM2PLL_ALL_SW_EN_OVERWRITE_S 8
#define REG_ARM2PLL_ALL_SW_EN_OVERWRITE_E 8
#define REG_ARMPLL_APU_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_ARMPLL_APU_ALL_SW_EN_OVERWRITE_S 9
#define REG_ARMPLL_APU_ALL_SW_EN_OVERWRITE_E 9
#define REG_APUBUSPLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_APUBUSPLL_DMACRO_ALL_SW_EN_OVERWRITE_S 10
#define REG_APUBUSPLL_DMACRO_ALL_SW_EN_OVERWRITE_E 10
#define REG_AUPLL_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_AUPLL_ALL_SW_EN_OVERWRITE_S 11
#define REG_AUPLL_ALL_SW_EN_OVERWRITE_E 11
#define REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_OVERWRITE_S 12
#define REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_OVERWRITE_E 12
#define REG_RV55FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_RV55FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE_S 13
#define REG_RV55FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE_E 13
#define REG_DMD_ANA_MISC_ALL_SW_EN_OVERWRITE 0x3f40
#define REG_DMD_ANA_MISC_ALL_SW_EN_OVERWRITE_S 14
#define REG_DMD_ANA_MISC_ALL_SW_EN_OVERWRITE_E 14
#define REG_AUSDM_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_AUSDM_ALL_SW_EN_OVERWRITE_S 0
#define REG_AUSDM_ALL_SW_EN_OVERWRITE_E 0
#define REG_EARC_DMACRO_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_EARC_DMACRO_ALL_SW_EN_OVERWRITE_S 1
#define REG_EARC_DMACRO_ALL_SW_EN_OVERWRITE_E 1
#define REG_FLASH_8BIT_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_FLASH_8BIT_ALL_SW_EN_OVERWRITE_S 3
#define REG_FLASH_8BIT_ALL_SW_EN_OVERWRITE_E 3
#define REG_FLASH_32BIF_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_FLASH_32BIF_ALL_SW_EN_OVERWRITE_S 4
#define REG_FLASH_32BIF_ALL_SW_EN_OVERWRITE_E 4
#define REG_FLASH_DMACRO_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_FLASH_DMACRO_ALL_SW_EN_OVERWRITE_S 5
#define REG_FLASH_DMACRO_ALL_SW_EN_OVERWRITE_E 5
#define REG_HDMIRX_APHY_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_HDMIRX_APHY_ALL_SW_EN_OVERWRITE_S 7
#define REG_HDMIRX_APHY_ALL_SW_EN_OVERWRITE_E 7
#define REG_HDMIRX_DPHY_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_HDMIRX_DPHY_ALL_SW_EN_OVERWRITE_S 8
#define REG_HDMIRX_DPHY_ALL_SW_EN_OVERWRITE_E 8
#define REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_OVERWRITE_S 9
#define REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_OVERWRITE_E 9
#define REG_IP_WRAP_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_IP_WRAP_ALL_SW_EN_OVERWRITE_S 10
#define REG_IP_WRAP_ALL_SW_EN_OVERWRITE_E 10
#define REG_MHEG5_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_MHEG5_ALL_SW_EN_OVERWRITE_S 12
#define REG_MHEG5_ALL_SW_EN_OVERWRITE_E 12
#define REG_SD_SDR_MACRO_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_SD_SDR_MACRO_ALL_SW_EN_OVERWRITE_S 13
#define REG_SD_SDR_MACRO_ALL_SW_EN_OVERWRITE_E 13
#define REG_USB_PHY_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_USB_PHY_ALL_SW_EN_OVERWRITE_S 14
#define REG_USB_PHY_ALL_SW_EN_OVERWRITE_E 14
#define REG_MOD_DOT_ALL_SW_EN_OVERWRITE 0x3f44
#define REG_MOD_DOT_ALL_SW_EN_OVERWRITE_S 15
#define REG_MOD_DOT_ALL_SW_EN_OVERWRITE_E 15
#define REG_VDEC_CORE0_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_VDEC_CORE0_ALL_SW_EN_OVERWRITE_S 0
#define REG_VDEC_CORE0_ALL_SW_EN_OVERWRITE_E 0
#define REG_SCSR_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_SCSR_ALL_SW_EN_OVERWRITE_S 1
#define REG_SCSR_ALL_SW_EN_OVERWRITE_E 1
#define REG_TOP_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_TOP_ALL_SW_EN_OVERWRITE_S 4
#define REG_TOP_ALL_SW_EN_OVERWRITE_E 4
#define REG_VDEC_CORE0_MERGE_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_VDEC_CORE0_MERGE_ALL_SW_EN_OVERWRITE_S 6
#define REG_VDEC_CORE0_MERGE_ALL_SW_EN_OVERWRITE_E 6
#define REG_RV55FRC_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_RV55FRC_ALL_SW_EN_OVERWRITE_S 9
#define REG_RV55FRC_ALL_SW_EN_OVERWRITE_E 9
#define REG_RV55PQU_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_RV55PQU_ALL_SW_EN_OVERWRITE_S 10
#define REG_RV55PQU_ALL_SW_EN_OVERWRITE_E 10
#define REG_SCACE_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_SCACE_ALL_SW_EN_OVERWRITE_S 11
#define REG_SCACE_ALL_SW_EN_OVERWRITE_E 11
#define REG_SCDV_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_SCDV_ALL_SW_EN_OVERWRITE_S 12
#define REG_SCDV_ALL_SW_EN_OVERWRITE_E 12
#define REG_SCNR_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_SCNR_ALL_SW_EN_OVERWRITE_S 13
#define REG_SCNR_ALL_SW_EN_OVERWRITE_E 13
#define REG_DISP_MFDEC_BRG_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_DISP_MFDEC_BRG_ALL_SW_EN_OVERWRITE_S 14
#define REG_DISP_MFDEC_BRG_ALL_SW_EN_OVERWRITE_E 14
#define REG_MOD_ALL_SW_EN_OVERWRITE 0x3f48
#define REG_MOD_ALL_SW_EN_OVERWRITE_S 15
#define REG_MOD_ALL_SW_EN_OVERWRITE_E 15
#define REG_DRAMC0_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_DRAMC0_ALL_SW_EN_OVERWRITE_S 4
#define REG_DRAMC0_ALL_SW_EN_OVERWRITE_E 4
#define REG_DRAMC1_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_DRAMC1_ALL_SW_EN_OVERWRITE_S 5
#define REG_DRAMC1_ALL_SW_EN_OVERWRITE_E 5
#define REG_VDEC_SOC_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_VDEC_SOC_ALL_SW_EN_OVERWRITE_S 6
#define REG_VDEC_SOC_ALL_SW_EN_OVERWRITE_E 6
#define REG_SCDISP_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_SCDISP_ALL_SW_EN_OVERWRITE_S 7
#define REG_SCDISP_ALL_SW_EN_OVERWRITE_E 7
#define REG_SCSCL_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_SCSCL_ALL_SW_EN_OVERWRITE_S 8
#define REG_SCSCL_ALL_SW_EN_OVERWRITE_E 8
#define REG_TSP_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_TSP_ALL_SW_EN_OVERWRITE_S 9
#define REG_TSP_ALL_SW_EN_OVERWRITE_E 9
#define REG_SCIP_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_SCIP_ALL_SW_EN_OVERWRITE_S 11
#define REG_SCIP_ALL_SW_EN_OVERWRITE_E 11
#define REG_SCMW_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_SCMW_ALL_SW_EN_OVERWRITE_S 12
#define REG_SCMW_ALL_SW_EN_OVERWRITE_E 12
#define REG_SCPQ_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_SCPQ_ALL_SW_EN_OVERWRITE_S 13
#define REG_SCPQ_ALL_SW_EN_OVERWRITE_E 13
#define REG_SCTCON_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_SCTCON_ALL_SW_EN_OVERWRITE_S 14
#define REG_SCTCON_ALL_SW_EN_OVERWRITE_E 14
#define REG_VIVALDI9_ALL_SW_EN_OVERWRITE 0x3f4c
#define REG_VIVALDI9_ALL_SW_EN_OVERWRITE_S 15
#define REG_VIVALDI9_ALL_SW_EN_OVERWRITE_E 15
#define REG_DRAMC2_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_DRAMC2_ALL_SW_EN_OVERWRITE_S 0
#define REG_DRAMC2_ALL_SW_EN_OVERWRITE_E 0
#define REG_FRCIOPMRV55_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_FRCIOPMRV55_ALL_SW_EN_OVERWRITE_S 1
#define REG_FRCIOPMRV55_ALL_SW_EN_OVERWRITE_E 1
#define REG_FRCMEHALO_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_FRCMEHALO_ALL_SW_EN_OVERWRITE_S 3
#define REG_FRCMEHALO_ALL_SW_EN_OVERWRITE_E 3
#define REG_FRCMI_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_FRCMI_ALL_SW_EN_OVERWRITE_S 4
#define REG_FRCMI_ALL_SW_EN_OVERWRITE_E 4
#define REG_MCUSYS2AIA_BRIDGE_WRAP_2P_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_MCUSYS2AIA_BRIDGE_WRAP_2P_ALL_SW_EN_OVERWRITE_S 6
#define REG_MCUSYS2AIA_BRIDGE_WRAP_2P_ALL_SW_EN_OVERWRITE_E 6
#define REG_ARMPLL_GPU_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_ARMPLL_GPU_ALL_SW_EN_OVERWRITE_S 7
#define REG_ARMPLL_GPU_ALL_SW_EN_OVERWRITE_E 7
#define REG_PCIE_PHY_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_PCIE_PHY_ALL_SW_EN_OVERWRITE_S 8
#define REG_PCIE_PHY_ALL_SW_EN_OVERWRITE_E 8
#define REG_UFS_PHY_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_UFS_PHY_ALL_SW_EN_OVERWRITE_S 9
#define REG_UFS_PHY_ALL_SW_EN_OVERWRITE_E 9
#define REG_VDEC_CORE1_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_VDEC_CORE1_ALL_SW_EN_OVERWRITE_S 10
#define REG_VDEC_CORE1_ALL_SW_EN_OVERWRITE_E 10
#define REG_LPLL_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_LPLL_ALL_SW_EN_OVERWRITE_S 11
#define REG_LPLL_ALL_SW_EN_OVERWRITE_E 11
#define REG_VDEC_CORE1_MERGE_ALL_SW_EN_OVERWRITE 0x3f50
#define REG_VDEC_CORE1_MERGE_ALL_SW_EN_OVERWRITE_S 12
#define REG_VDEC_CORE1_MERGE_ALL_SW_EN_OVERWRITE_E 12
#define REG_XCPLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_XCPLL_DMACRO_ALL_SW_EN_VALUE_S 0
#define REG_XCPLL_DMACRO_ALL_SW_EN_VALUE_E 0
#define REG_XCSRSPLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_XCSRSPLL_DMACRO_ALL_SW_EN_VALUE_S 1
#define REG_XCSRSPLL_DMACRO_ALL_SW_EN_VALUE_E 1
#define REG_VDECPLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_VDECPLL_DMACRO_ALL_SW_EN_VALUE_S 2
#define REG_VDECPLL_DMACRO_ALL_SW_EN_VALUE_E 2
#define REG_SYS0PLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_SYS0PLL_DMACRO_ALL_SW_EN_VALUE_S 3
#define REG_SYS0PLL_DMACRO_ALL_SW_EN_VALUE_E 3
#define REG_SYS1PLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_SYS1PLL_DMACRO_ALL_SW_EN_VALUE_S 4
#define REG_SYS1PLL_DMACRO_ALL_SW_EN_VALUE_E 4
#define REG_SYS2PLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_SYS2PLL_DMACRO_ALL_SW_EN_VALUE_S 5
#define REG_SYS2PLL_DMACRO_ALL_SW_EN_VALUE_E 5
#define REG_SYS3PLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_SYS3PLL_DMACRO_ALL_SW_EN_VALUE_S 6
#define REG_SYS3PLL_DMACRO_ALL_SW_EN_VALUE_E 6
#define REG_ARMPLL_ALL_SW_EN_VALUE 0x3f60
#define REG_ARMPLL_ALL_SW_EN_VALUE_S 7
#define REG_ARMPLL_ALL_SW_EN_VALUE_E 7
#define REG_ARM2PLL_ALL_SW_EN_VALUE 0x3f60
#define REG_ARM2PLL_ALL_SW_EN_VALUE_S 8
#define REG_ARM2PLL_ALL_SW_EN_VALUE_E 8
#define REG_ARMPLL_APU_ALL_SW_EN_VALUE 0x3f60
#define REG_ARMPLL_APU_ALL_SW_EN_VALUE_S 9
#define REG_ARMPLL_APU_ALL_SW_EN_VALUE_E 9
#define REG_APUBUSPLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_APUBUSPLL_DMACRO_ALL_SW_EN_VALUE_S 10
#define REG_APUBUSPLL_DMACRO_ALL_SW_EN_VALUE_E 10
#define REG_AUPLL_ALL_SW_EN_VALUE 0x3f60
#define REG_AUPLL_ALL_SW_EN_VALUE_S 11
#define REG_AUPLL_ALL_SW_EN_VALUE_E 11
#define REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_VALUE_S 12
#define REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_VALUE_E 12
#define REG_RV55FRCPLL_DMACRO_ALL_SW_EN_VALUE 0x3f60
#define REG_RV55FRCPLL_DMACRO_ALL_SW_EN_VALUE_S 13
#define REG_RV55FRCPLL_DMACRO_ALL_SW_EN_VALUE_E 13
#define REG_DMD_ANA_MISC_ALL_SW_EN_VALUE 0x3f60
#define REG_DMD_ANA_MISC_ALL_SW_EN_VALUE_S 14
#define REG_DMD_ANA_MISC_ALL_SW_EN_VALUE_E 14
#define REG_AUSDM_ALL_SW_EN_VALUE 0x3f64
#define REG_AUSDM_ALL_SW_EN_VALUE_S 0
#define REG_AUSDM_ALL_SW_EN_VALUE_E 0
#define REG_EARC_DMACRO_ALL_SW_EN_VALUE 0x3f64
#define REG_EARC_DMACRO_ALL_SW_EN_VALUE_S 1
#define REG_EARC_DMACRO_ALL_SW_EN_VALUE_E 1
#define REG_FLASH_8BIT_ALL_SW_EN_VALUE 0x3f64
#define REG_FLASH_8BIT_ALL_SW_EN_VALUE_S 3
#define REG_FLASH_8BIT_ALL_SW_EN_VALUE_E 3
#define REG_FLASH_32BIF_ALL_SW_EN_VALUE 0x3f64
#define REG_FLASH_32BIF_ALL_SW_EN_VALUE_S 4
#define REG_FLASH_32BIF_ALL_SW_EN_VALUE_E 4
#define REG_FLASH_DMACRO_ALL_SW_EN_VALUE 0x3f64
#define REG_FLASH_DMACRO_ALL_SW_EN_VALUE_S 5
#define REG_FLASH_DMACRO_ALL_SW_EN_VALUE_E 5
#define REG_HDMIRX_APHY_ALL_SW_EN_VALUE 0x3f64
#define REG_HDMIRX_APHY_ALL_SW_EN_VALUE_S 7
#define REG_HDMIRX_APHY_ALL_SW_EN_VALUE_E 7
#define REG_HDMIRX_DPHY_ALL_SW_EN_VALUE 0x3f64
#define REG_HDMIRX_DPHY_ALL_SW_EN_VALUE_S 8
#define REG_HDMIRX_DPHY_ALL_SW_EN_VALUE_E 8
#define REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_VALUE 0x3f64
#define REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_VALUE_S 9
#define REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_VALUE_E 9
#define REG_IP_WRAP_ALL_SW_EN_VALUE 0x3f64
#define REG_IP_WRAP_ALL_SW_EN_VALUE_S 10
#define REG_IP_WRAP_ALL_SW_EN_VALUE_E 10
#define REG_MHEG5_ALL_SW_EN_VALUE 0x3f64
#define REG_MHEG5_ALL_SW_EN_VALUE_S 12
#define REG_MHEG5_ALL_SW_EN_VALUE_E 12
#define REG_SD_SDR_MACRO_ALL_SW_EN_VALUE 0x3f64
#define REG_SD_SDR_MACRO_ALL_SW_EN_VALUE_S 13
#define REG_SD_SDR_MACRO_ALL_SW_EN_VALUE_E 13
#define REG_USB_PHY_ALL_SW_EN_VALUE 0x3f64
#define REG_USB_PHY_ALL_SW_EN_VALUE_S 14
#define REG_USB_PHY_ALL_SW_EN_VALUE_E 14
#define REG_MOD_DOT_ALL_SW_EN_VALUE 0x3f64
#define REG_MOD_DOT_ALL_SW_EN_VALUE_S 15
#define REG_MOD_DOT_ALL_SW_EN_VALUE_E 15
#define REG_VDEC_CORE0_ALL_SW_EN_VALUE 0x3f68
#define REG_VDEC_CORE0_ALL_SW_EN_VALUE_S 0
#define REG_VDEC_CORE0_ALL_SW_EN_VALUE_E 0
#define REG_SCSR_ALL_SW_EN_VALUE 0x3f68
#define REG_SCSR_ALL_SW_EN_VALUE_S 1
#define REG_SCSR_ALL_SW_EN_VALUE_E 1
#define REG_TOP_ALL_SW_EN_VALUE 0x3f68
#define REG_TOP_ALL_SW_EN_VALUE_S 4
#define REG_TOP_ALL_SW_EN_VALUE_E 4
#define REG_VDEC_CORE0_MERGE_ALL_SW_EN_VALUE 0x3f68
#define REG_VDEC_CORE0_MERGE_ALL_SW_EN_VALUE_S 6
#define REG_VDEC_CORE0_MERGE_ALL_SW_EN_VALUE_E 6
#define REG_RV55FRC_ALL_SW_EN_VALUE 0x3f68
#define REG_RV55FRC_ALL_SW_EN_VALUE_S 9
#define REG_RV55FRC_ALL_SW_EN_VALUE_E 9
#define REG_RV55PQU_ALL_SW_EN_VALUE 0x3f68
#define REG_RV55PQU_ALL_SW_EN_VALUE_S 10
#define REG_RV55PQU_ALL_SW_EN_VALUE_E 10
#define REG_SCACE_ALL_SW_EN_VALUE 0x3f68
#define REG_SCACE_ALL_SW_EN_VALUE_S 11
#define REG_SCACE_ALL_SW_EN_VALUE_E 11
#define REG_SCDV_ALL_SW_EN_VALUE 0x3f68
#define REG_SCDV_ALL_SW_EN_VALUE_S 12
#define REG_SCDV_ALL_SW_EN_VALUE_E 12
#define REG_SCNR_ALL_SW_EN_VALUE 0x3f68
#define REG_SCNR_ALL_SW_EN_VALUE_S 13
#define REG_SCNR_ALL_SW_EN_VALUE_E 13
#define REG_DISP_MFDEC_BRG_ALL_SW_EN_VALUE 0x3f68
#define REG_DISP_MFDEC_BRG_ALL_SW_EN_VALUE_S 14
#define REG_DISP_MFDEC_BRG_ALL_SW_EN_VALUE_E 14
#define REG_MOD_ALL_SW_EN_VALUE 0x3f68
#define REG_MOD_ALL_SW_EN_VALUE_S 15
#define REG_MOD_ALL_SW_EN_VALUE_E 15
#define REG_DRAMC0_ALL_SW_EN_VALUE 0x3f6c
#define REG_DRAMC0_ALL_SW_EN_VALUE_S 4
#define REG_DRAMC0_ALL_SW_EN_VALUE_E 4
#define REG_DRAMC1_ALL_SW_EN_VALUE 0x3f6c
#define REG_DRAMC1_ALL_SW_EN_VALUE_S 5
#define REG_DRAMC1_ALL_SW_EN_VALUE_E 5
#define REG_VDEC_SOC_ALL_SW_EN_VALUE 0x3f6c
#define REG_VDEC_SOC_ALL_SW_EN_VALUE_S 6
#define REG_VDEC_SOC_ALL_SW_EN_VALUE_E 6
#define REG_SCDISP_ALL_SW_EN_VALUE 0x3f6c
#define REG_SCDISP_ALL_SW_EN_VALUE_S 7
#define REG_SCDISP_ALL_SW_EN_VALUE_E 7
#define REG_SCSCL_ALL_SW_EN_VALUE 0x3f6c
#define REG_SCSCL_ALL_SW_EN_VALUE_S 8
#define REG_SCSCL_ALL_SW_EN_VALUE_E 8
#define REG_TSP_ALL_SW_EN_VALUE 0x3f6c
#define REG_TSP_ALL_SW_EN_VALUE_S 9
#define REG_TSP_ALL_SW_EN_VALUE_E 9
#define REG_SCIP_ALL_SW_EN_VALUE 0x3f6c
#define REG_SCIP_ALL_SW_EN_VALUE_S 11
#define REG_SCIP_ALL_SW_EN_VALUE_E 11
#define REG_SCMW_ALL_SW_EN_VALUE 0x3f6c
#define REG_SCMW_ALL_SW_EN_VALUE_S 12
#define REG_SCMW_ALL_SW_EN_VALUE_E 12
#define REG_SCPQ_ALL_SW_EN_VALUE 0x3f6c
#define REG_SCPQ_ALL_SW_EN_VALUE_S 13
#define REG_SCPQ_ALL_SW_EN_VALUE_E 13
#define REG_SCTCON_ALL_SW_EN_VALUE 0x3f6c
#define REG_SCTCON_ALL_SW_EN_VALUE_S 14
#define REG_SCTCON_ALL_SW_EN_VALUE_E 14
#define REG_VIVALDI9_ALL_SW_EN_VALUE 0x3f6c
#define REG_VIVALDI9_ALL_SW_EN_VALUE_S 15
#define REG_VIVALDI9_ALL_SW_EN_VALUE_E 15
#define REG_DRAMC2_ALL_SW_EN_VALUE 0x3f70
#define REG_DRAMC2_ALL_SW_EN_VALUE_S 0
#define REG_DRAMC2_ALL_SW_EN_VALUE_E 0
#define REG_FRCIOPMRV55_ALL_SW_EN_VALUE 0x3f70
#define REG_FRCIOPMRV55_ALL_SW_EN_VALUE_S 1
#define REG_FRCIOPMRV55_ALL_SW_EN_VALUE_E 1
#define REG_FRCMEHALO_ALL_SW_EN_VALUE 0x3f70
#define REG_FRCMEHALO_ALL_SW_EN_VALUE_S 3
#define REG_FRCMEHALO_ALL_SW_EN_VALUE_E 3
#define REG_FRCMI_ALL_SW_EN_VALUE 0x3f70
#define REG_FRCMI_ALL_SW_EN_VALUE_S 4
#define REG_FRCMI_ALL_SW_EN_VALUE_E 4
#define REG_MCUSYS2AIA_BRIDGE_WRAP_2P_ALL_SW_EN_VALUE 0x3f70
#define REG_MCUSYS2AIA_BRIDGE_WRAP_2P_ALL_SW_EN_VALUE_S 6
#define REG_MCUSYS2AIA_BRIDGE_WRAP_2P_ALL_SW_EN_VALUE_E 6
#define REG_ARMPLL_GPU_ALL_SW_EN_VALUE 0x3f70
#define REG_ARMPLL_GPU_ALL_SW_EN_VALUE_S 7
#define REG_ARMPLL_GPU_ALL_SW_EN_VALUE_E 7
#define REG_PCIE_PHY_ALL_SW_EN_VALUE 0x3f70
#define REG_PCIE_PHY_ALL_SW_EN_VALUE_S 8
#define REG_PCIE_PHY_ALL_SW_EN_VALUE_E 8
#define REG_UFS_PHY_ALL_SW_EN_VALUE 0x3f70
#define REG_UFS_PHY_ALL_SW_EN_VALUE_S 9
#define REG_UFS_PHY_ALL_SW_EN_VALUE_E 9
#define REG_VDEC_CORE1_ALL_SW_EN_VALUE 0x3f70
#define REG_VDEC_CORE1_ALL_SW_EN_VALUE_S 10
#define REG_VDEC_CORE1_ALL_SW_EN_VALUE_E 10
#define REG_LPLL_ALL_SW_EN_VALUE 0x3f70
#define REG_LPLL_ALL_SW_EN_VALUE_S 11
#define REG_LPLL_ALL_SW_EN_VALUE_E 11
#define REG_VDEC_CORE1_MERGE_ALL_SW_EN_VALUE 0x3f70
#define REG_VDEC_CORE1_MERGE_ALL_SW_EN_VALUE_S 12
#define REG_VDEC_CORE1_MERGE_ALL_SW_EN_VALUE_E 12
#define REG_SW_EN_CALC2TEST_CLK_CALCULATE 0x3f88
#define REG_SW_EN_CALC2TEST_CLK_CALCULATE_S 0
#define REG_SW_EN_CALC2TEST_CLK_CALCULATE_E 0
#define REG_SW_EN_RIU_DMD2RIU_DFT_DEMOD1 0x3f90
#define REG_SW_EN_RIU_DMD2RIU_DFT_DEMOD1_S 0
#define REG_SW_EN_RIU_DMD2RIU_DFT_DEMOD1_E 0
#define REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY 0x3f98
#define REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY_S 0
#define REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY_E 0
#define REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY 0x3f98
#define REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY_S 1
#define REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY_E 1
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCACE 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCACE_S 0
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCACE_E 0
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDV 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDV_S 1
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDV_E 1
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCIP 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCIP_S 2
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCIP_E 2
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCMW 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCMW_S 3
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCMW_E 3
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCNR 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCNR_S 4
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCNR_E 4
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCPQ 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCPQ_S 5
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCPQ_E 5
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCSR 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCSR_S 6
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCSR_E 6
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCTCON 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCTCON_S 7
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCTCON_E 7
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDISP 0x3fa8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDISP_S 8
#define REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDISP_E 8
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55FRC 0x3fb4
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55FRC_S 0
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55FRC_E 0
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55PQU 0x3fb4
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55PQU_S 1
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55PQU_E 1
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMEHALO 0x3fb4
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMEHALO_S 2
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMEHALO_E 2
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMI 0x3fb4
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMI_S 4
#define REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMI_E 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_ADC 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_ADC_S 0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_ADC_E 0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_AIA 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_AIA_S 1
#define REG_SW_EN_RIU_NONPM2RIU_DFT_AIA_E 1
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD0 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD0_S 2
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD0_E 2
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD1 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD1_S 3
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD1_E 3
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_SOC 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_SOC_S 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_SOC_E 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_S 5
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_E 5
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1_S 6
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1_E 6
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC0 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC0_S 8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC0_E 8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC1 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC1_S 9
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC1_E 9
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC2 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC2_S 10
#define REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC2_E 10
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MHEG5 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MHEG5_S 11
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MHEG5_E 11
#define REG_SW_EN_RIU_NONPM2RIU_DFT_GPU_NODIE 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_GPU_NODIE_S 12
#define REG_SW_EN_RIU_NONPM2RIU_DFT_GPU_NODIE_E 12
#define REG_SW_EN_RIU_NONPM2RIU_DFT_HDMIRX 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_HDMIRX_S 13
#define REG_SW_EN_RIU_NONPM2RIU_DFT_HDMIRX_E 13
#define REG_SW_EN_RIU_NONPM2RIU_DFT_IP_WRAP 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_IP_WRAP_S 14
#define REG_SW_EN_RIU_NONPM2RIU_DFT_IP_WRAP_E 14
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MCUSYS 0x3fc0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MCUSYS_S 15
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MCUSYS_E 15
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MOD 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MOD_S 0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_MOD_E 0
#define REG_SW_EN_VIVA_RIU2RIU_DFT_VIVALDI9 0x3fc4
#define REG_SW_EN_VIVA_RIU2RIU_DFT_VIVALDI9_S 1
#define REG_SW_EN_VIVA_RIU2RIU_DFT_VIVALDI9_E 1
#define REG_SW_EN_RIU_NONPM2RIU_DFT_TSP 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_TSP_S 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_TSP_E 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_FRCIOPMRV55 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_FRCIOPMRV55_S 5
#define REG_SW_EN_RIU_NONPM2RIU_DFT_FRCIOPMRV55_E 5
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55FRC 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55FRC_S 6
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55FRC_E 6
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55PQU 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55PQU_S 7
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55PQU_E 7
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMEHALO 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMEHALO_S 8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMEHALO_E 8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMI 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMI_S 10
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMI_E 10
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCACE 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCACE_S 11
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCACE_E 11
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDV 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDV_S 12
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDV_E 12
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCIP 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCIP_S 13
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCIP_E 13
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCMW 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCMW_S 14
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCMW_E 14
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCNR 0x3fc4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCNR_S 15
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCNR_E 15
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCPQ 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCPQ_S 0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCPQ_E 0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSCL 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSCL_S 1
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSCL_E 1
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSR 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSR_S 2
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSR_E 2
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCTCON 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCTCON_S 3
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCTCON_E 3
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY_S 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY_E 4
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY_S 5
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY_E 5
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDISP 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDISP_S 8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDISP_E 8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE_S 9
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE_E 9
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1_MERGE 0x3fc8
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1_MERGE_S 10
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1_MERGE_E 10
#define REG_CKG_OCC_SRC_FOR_TEST_DIV 0x3fe8
#define REG_CKG_OCC_SRC_FOR_TEST_DIV_S 0
#define REG_CKG_OCC_SRC_FOR_TEST_DIV_E 1
#define REG_SW_EN_OCC_SRC_FOR_TEST_DIV2TEST_CTRL_WP 0x3fec
#define REG_SW_EN_OCC_SRC_FOR_TEST_DIV2TEST_CTRL_WP_S 0
#define REG_SW_EN_OCC_SRC_FOR_TEST_DIV2TEST_CTRL_WP_E 0
#define REG_CKGEN01_DUMMY0 0x3ff0
#define REG_CKGEN01_DUMMY0_S 0
#define REG_CKGEN01_DUMMY0_E 15
#define REG_CKGEN01_DUMMY1 0x3ff4
#define REG_CKGEN01_DUMMY1_S 0
#define REG_CKGEN01_DUMMY1_E 15
#define REG_CKGEN01_DUMMY2 0x3ff8
#define REG_CKGEN01_DUMMY2_S 0
#define REG_CKGEN01_DUMMY2_E 15
#define REG_CKGEN01_DUMMY3 0x3ffc
#define REG_CKGEN01_DUMMY3_S 0
#define REG_CKGEN01_DUMMY3_E 15
#endif
