/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TS_SAMPLE_TEST_1
#define REG_0000_TS_SAMPLE (0x000)
	#define TS_SAMPLE_REG_TS0_CLK_SAMPLE_0000_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TS0_CLK_SAMPLE_0000_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TS0_CLK_SAMPLE_0000_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TS0_CLK_SAMPLE_0000_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_TS1_CLK_SAMPLE_0000_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_TS1_CLK_SAMPLE_0000_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_TS1_CLK_SAMPLE_0000_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_TS1_CLK_SAMPLE_0000_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0004_TS_SAMPLE (0x004)
	#define TS_SAMPLE_REG_TS2_CLK_SAMPLE_0004_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TS2_CLK_SAMPLE_0004_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TS2_CLK_SAMPLE_0004_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TS2_CLK_SAMPLE_0004_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_TS3_CLK_SAMPLE_0004_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_TS3_CLK_SAMPLE_0004_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_TS3_CLK_SAMPLE_0004_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_TS3_CLK_SAMPLE_0004_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0008_TS_SAMPLE (0x008)
	#define TS_SAMPLE_REG_TS4_CLK_SAMPLE_0008_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TS4_CLK_SAMPLE_0008_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TS4_CLK_SAMPLE_0008_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TS4_CLK_SAMPLE_0008_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_TS5_CLK_SAMPLE_0008_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_TS5_CLK_SAMPLE_0008_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_TS5_CLK_SAMPLE_0008_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_TS5_CLK_SAMPLE_0008_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_000C_TS_SAMPLE (0x00C)
	#define TS_SAMPLE_REG_TSO_OUT_CLK_SAMPLE_000C_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TSO_OUT_CLK_SAMPLE_000C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TSO_OUT_CLK_SAMPLE_000C_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TSO_OUT_CLK_SAMPLE_000C_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0010_TS_SAMPLE (0x010)
	#define TS_SAMPLE_REG_TSO_S2P_OUT_CLK_SAMPLE_0010_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TSO_S2P_OUT_CLK_SAMPLE_0010_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TSO_S2P_OUT_CLK_SAMPLE_0010_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TSO_S2P_OUT_CLK_SAMPLE_0010_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_TSO_S2P1_OUT_CLK_SAMPLE_0010_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_TSO_S2P1_OUT_CLK_SAMPLE_0010_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_TSO_S2P1_OUT_CLK_SAMPLE_0010_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_TSO_S2P1_OUT_CLK_SAMPLE_0010_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0014_TS_SAMPLE (0x014)
	#define TS_SAMPLE_REG_TSO2_OUT_CLK_SAMPLE_0014_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TSO2_OUT_CLK_SAMPLE_0014_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TSO2_OUT_CLK_SAMPLE_0014_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TSO2_OUT_CLK_SAMPLE_0014_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0018_TS_SAMPLE (0x018)
	#define TS_SAMPLE_REG_TSO2_S2P_OUT_CLK_SAMPLE_0018_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_TSO2_S2P_OUT_CLK_SAMPLE_0018_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_TSO2_S2P_OUT_CLK_SAMPLE_0018_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_TSO2_S2P_OUT_CLK_SAMPLE_0018_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_TSO2_S2P1_OUT_CLK_SAMPLE_0018_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_TSO2_S2P1_OUT_CLK_SAMPLE_0018_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_TSO2_S2P1_OUT_CLK_SAMPLE_0018_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_TSO2_S2P1_OUT_CLK_SAMPLE_0018_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0040_TS_SAMPLE (0x040)
	#define TS_SAMPLE_REG_STC0SYN_RST_0040 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_STC0_CW_SEL_0040 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_UPDATE_STC0_CW_0040 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_UPDATE_DC0_FREERUN_CW_0040 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_UPDATE_DC0_SYNC_CW_0040 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_STC0_REF_DIV2_EN_0040 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_STC0_NTP_EN_0040 Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_0044_TS_SAMPLE (0x044)
	#define TS_SAMPLE_REG_STC0SYN_CW_0_0044 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0048_TS_SAMPLE (0x048)
	#define TS_SAMPLE_REG_STC0SYN_CW_1_0048 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_004C_TS_SAMPLE (0x04C)
	#define TS_SAMPLE_REG_DC0_FREERUN_CW_0_004C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_TS_SAMPLE (0x050)
	#define TS_SAMPLE_REG_DC0_FREERUN_CW_1_0050 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0054_TS_SAMPLE (0x054)
	#define TS_SAMPLE_REG_DC0_NUM_0054 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0058_TS_SAMPLE (0x058)
	#define TS_SAMPLE_REG_DC0_DEN_0058 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0060_TS_SAMPLE (0x060)
	#define TS_SAMPLE_REG_STC1SYN_RST_0060 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_STC1_CW_SEL_0060 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_UPDATE_STC1_CW_0060 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_UPDATE_DC1_FREERUN_CW_0060 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_UPDATE_DC1_SYNC_CW_0060 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_STC1_REF_DIV2_EN_0060 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_STC1_NTP_EN_0060 Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_0064_TS_SAMPLE (0x064)
	#define TS_SAMPLE_REG_STC1SYN_CW_0_0064 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_TS_SAMPLE (0x068)
	#define TS_SAMPLE_REG_STC1SYN_CW_1_0068 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_006C_TS_SAMPLE (0x06C)
	#define TS_SAMPLE_REG_DC1_FREERUN_CW_0_006C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0070_TS_SAMPLE (0x070)
	#define TS_SAMPLE_REG_DC1_FREERUN_CW_1_0070 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0074_TS_SAMPLE (0x074)
	#define TS_SAMPLE_REG_DC1_NUM_0074 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0078_TS_SAMPLE (0x078)
	#define TS_SAMPLE_REG_DC1_DEN_0078 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0080_TS_SAMPLE (0x080)
	#define TS_SAMPLE_REG_STC2SYN_RST_0080 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_STC2_CW_SEL_0080 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_UPDATE_STC2_CW_0080 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_UPDATE_DC2_FREERUN_CW_0080 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_UPDATE_DC2_SYNC_CW_0080 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_STC2_REF_DIV2_EN_0080 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_STC2_NTP_EN_0080 Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_0084_TS_SAMPLE (0x084)
	#define TS_SAMPLE_REG_STC2SYN_CW_0_0084 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0088_TS_SAMPLE (0x088)
	#define TS_SAMPLE_REG_STC2SYN_CW_1_0088 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_008C_TS_SAMPLE (0x08C)
	#define TS_SAMPLE_REG_DC2_FREERUN_CW_0_008C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0090_TS_SAMPLE (0x090)
	#define TS_SAMPLE_REG_DC2_FREERUN_CW_1_0090 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0094_TS_SAMPLE (0x094)
	#define TS_SAMPLE_REG_DC2_NUM_0094 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0098_TS_SAMPLE (0x098)
	#define TS_SAMPLE_REG_DC2_DEN_0098 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A0_TS_SAMPLE (0x0A0)
	#define TS_SAMPLE_REG_STC3SYN_RST_00A0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_STC3_CW_SEL_00A0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_UPDATE_STC3_CW_00A0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_UPDATE_DC3_FREERUN_CW_00A0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_UPDATE_DC3_SYNC_CW_00A0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_STC3_REF_DIV2_EN_00A0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_STC3_NTP_EN_00A0 Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_00A4_TS_SAMPLE (0x0A4)
	#define TS_SAMPLE_REG_STC3SYN_CW_0_00A4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A8_TS_SAMPLE (0x0A8)
	#define TS_SAMPLE_REG_STC3SYN_CW_1_00A8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00AC_TS_SAMPLE (0x0AC)
	#define TS_SAMPLE_REG_DC3_FREERUN_CW_0_00AC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B0_TS_SAMPLE (0x0B0)
	#define TS_SAMPLE_REG_DC3_FREERUN_CW_1_00B0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B4_TS_SAMPLE (0x0B4)
	#define TS_SAMPLE_REG_DC3_NUM_00B4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B8_TS_SAMPLE (0x0B8)
	#define TS_SAMPLE_REG_DC3_DEN_00B8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C0_TS_SAMPLE (0x0C0)
	#define TS_SAMPLE_REG_CKG_TSO2_MMT_00C0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_MMT_00C0_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_MMT_00C0_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO2_MMT_00C0_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_MMT_00C0_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO2_CH1_00C0_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO2_CH1_00C0_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO2_CH1_00C0_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO2_CH1_00C0_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO2_CH1_00C0_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00C4_TS_SAMPLE (0x0C4)
	#define TS_SAMPLE_REG_CKG_TSO2_CH2_00C4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_CH2_00C4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_CH2_00C4_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO2_CH2_00C4_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_CH2_00C4_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO2_CH3_00C4_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO2_CH3_00C4_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO2_CH3_00C4_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO2_CH3_00C4_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO2_CH3_00C4_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00C8_TS_SAMPLE (0x0C8)
	#define TS_SAMPLE_REG_CKG_TSO2_CH4_00C8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_CH4_00C8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_CH4_00C8_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO2_CH4_00C8_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_CH4_00C8_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO2_CH5_00C8_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO2_CH5_00C8_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO2_CH5_00C8_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO2_CH5_00C8_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO2_CH5_00C8_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00CC_TS_SAMPLE (0x0CC)
	#define TS_SAMPLE_REG_CKG_TSO2_CH6_00CC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_CH6_00CC_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_CH6_00CC_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO2_CH6_00CC_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_CH6_00CC_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_00D0_TS_SAMPLE (0x0D0)
	#define TS_SAMPLE_REG_CKG_TSO2_S2P_00D0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P_00D0_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P_00D0_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P_00D0_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P_00D0_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P1_00D0_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P1_00D0_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P1_00D0_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P1_00D0_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO2_S2P1_00D0_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00D4_TS_SAMPLE (0x0D4)
	#define TS_SAMPLE_REG_CKG_TS_TLV0_00D4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS_TLV0_00D4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS_TLV0_00D4_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TS_TLV0_00D4_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TS_TLV0_00D4_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TS_TLV1_00D4_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TS_TLV1_00D4_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TS_TLV1_00D4_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TS_TLV1_00D4_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TS_TLV1_00D4_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00D8_TS_SAMPLE (0x0D8)
	#define TS_SAMPLE_REG_CKG_TS_TLV2_00D8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS_TLV2_00D8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS_TLV2_00D8_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TS_TLV2_00D8_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TS_TLV2_00D8_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0138_TS_SAMPLE (0x138)
	#define TS_SAMPLE_REG_CKG_TS0_0138_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS0_0138_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS0_0138_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TS0_0138_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TS0_0138_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TS1_0138_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TS1_0138_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TS1_0138_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TS1_0138_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TS1_0138_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_013C_TS_SAMPLE (0x13C)
	#define TS_SAMPLE_REG_CKG_TS2_013C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS2_013C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS2_013C_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TS2_013C_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TS2_013C_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO_S2P_013C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO_S2P_013C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO_S2P_013C_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO_S2P_013C_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO_S2P_013C_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0140_TS_SAMPLE (0x140)
	#define TS_SAMPLE_REG_CKG_TSO_S2P1_0140_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_S2P1_0140_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_S2P1_0140_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO_S2P1_0140_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_S2P1_0140_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSFI_0140_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSFI_0140_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSFI_0140_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSFI_0140_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSFI_0140_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0144_TS_SAMPLE (0x144)
	#define TS_SAMPLE_REG_CKG_TS_ALP0_0144_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS_ALP0_0144_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS_ALP0_0144_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TS_ALP0_0144_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TS_ALP0_0144_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TS_ALP1_0144_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TS_ALP1_0144_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TS_ALP1_0144_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TS_ALP1_0144_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TS_ALP1_0144_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0148_TS_SAMPLE (0x148)
	#define TS_SAMPLE_REG_CKG_TS_ALP2_0148_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS_ALP2_0148_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS_ALP2_0148_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TS_ALP2_0148_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TS_ALP2_0148_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TS_ALP_FI_0148_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TS_ALP_FI_0148_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TS_ALP_FI_0148_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TS_ALP_FI_0148_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TS_ALP_FI_0148_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_014C_TS_SAMPLE (0x14C)
	#define TS_SAMPLE_REG_CKG_TSO_MMT_014C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_MMT_014C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_MMT_014C_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO_MMT_014C_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_MMT_014C_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO_CH1_014C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO_CH1_014C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO_CH1_014C_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO_CH1_014C_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO_CH1_014C_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0150_TS_SAMPLE (0x150)
	#define TS_SAMPLE_REG_CKG_TSO_CH2_0150_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_CH2_0150_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_CH2_0150_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO_CH2_0150_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_CH2_0150_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO_CH3_0150_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO_CH3_0150_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO_CH3_0150_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO_CH3_0150_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO_CH3_0150_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0154_TS_SAMPLE (0x154)
	#define TS_SAMPLE_REG_CKG_TSO_CH4_0154_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_CH4_0154_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_CH4_0154_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO_CH4_0154_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_CH4_0154_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO_CH5_0154_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO_CH5_0154_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO_CH5_0154_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO_CH5_0154_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO_CH5_0154_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0158_TS_SAMPLE (0x158)
	#define TS_SAMPLE_REG_CKG_TSO_CH6_0158_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_CH6_0158_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_CH6_0158_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CKG_TSO_CH6_0158_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_CH6_0158_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0164_TS_SAMPLE (0x164)
	#define TS_SAMPLE_REG_CKG_TS_TX_C1_0164_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS_TX_C1_0164_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TS_TX_C1_0164_5_2 Fld(4, 2, AC_MSKB0)//[5:2]
	#define TS_SAMPLE_REG_CLK_TS_TX_C1_EXT_DIV8_0164 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TS_SAMPLE_REG_CKG_TS_TX_C2_0164_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TS_TX_C2_0164_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TS_TX_C2_0164_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CLK_TS_TX_C2_EXT_DIV8_0164 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0168_TS_SAMPLE (0x168)
	#define TS_SAMPLE_REG_CKG_2B_RX_INT_0168_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_2B_RX_INT_0168_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_2B_RX_INT_0168_11_10 Fld(2, 10, AC_MSKB1)//[11:10]
	#define TS_SAMPLE_REG_CKG_2B_TX_0168_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TS_SAMPLE_REG_CKG_2B_TX_0168_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CKG_2B_TX_0168_15_14 Fld(2, 14, AC_MSKB1)//[15:14]

//Page TS_SAMPLE_TEST_2
#define REG_016C_TS_SAMPLE (0x16C)
	#define TS_SAMPLE_REG_CKG_CILINK_IF_016C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_CILINK_IF_016C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_CILINK_IF_016C_3_2 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0170_TS_SAMPLE (0x170)
	#define TS_SAMPLE_REG_CLK_2B_TX_EXT_INV_0170 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0178_TS_SAMPLE (0x178)
	#define TS_SAMPLE_REG_CKG_TSO_OUT_0178_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_OUT_0178_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_OUT_0178_4_2 Fld(3, 2, AC_MSKB0)//[4:2]
	#define TS_SAMPLE_REG_CKG_TSO_OUT_0178_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CKG_TSO_OUT_0178_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_OUT_0178_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_P_TSO_OUT_0178_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_P_TSO_OUT_0178_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_P_TSO_OUT_0178_12_10 Fld(3, 10, AC_MSKB1)//[12:10]
	#define TS_SAMPLE_REG_CKG_P_TSO_OUT_0178_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CKG_P_TSO_OUT_0178_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_P_TSO_OUT_0178_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_017C_TS_SAMPLE (0x17C)
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIVNUM_017C_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIVNUM_017C_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIVNUM_017C_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIVNUM_017C_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_PH_TUN_NUM_017C_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_PH_TUN_NUM_017C_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_PH_TUN_NUM_017C_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_PH_TUN_NUM_017C_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0180_TS_SAMPLE (0x180)
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIV_SEL_0180 Fld(2, 0, AC_MSKB0)//[1:0]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_PH_TUN_EN_0180 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0184_TS_SAMPLE (0x184)
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIV_MN_LOAD_0184 Fld(1, 15, AC_MSKB1)//[15:15]
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIV_MN_N_0184 Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_0188_TS_SAMPLE (0x188)
	#define TS_SAMPLE_REG_CLK_TSO_OUT_DIV_MN_M_0188 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_018C_TS_SAMPLE (0x18C)
	#define TS_SAMPLE_REG_CLK_TSO_TOPAD_INV_018C Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_11_10 Fld(2, 10, AC_MSKB1)//[11:10]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TS_SAMPLE_018C_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0190_TS_SAMPLE (0x190)
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_3_2 Fld(2, 2, AC_MSKB0)//[3:2]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_0190_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_IN_0190_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_IN_0190_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_IN_0190_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_IN_0190_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO_TRACE_IN_0190_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0194_TS_SAMPLE (0x194)
	#define TS_SAMPLE_REG_CKG_TSO2_OUT_0194_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_OUT_0194_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_OUT_0194_4_2 Fld(3, 2, AC_MSKB0)//[4:2]
	#define TS_SAMPLE_REG_CKG_TSO2_OUT_0194_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CKG_TSO2_OUT_0194_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_OUT_0194_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_P_TSO2_OUT_0194_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_P_TSO2_OUT_0194_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_P_TSO2_OUT_0194_12_10 Fld(3, 10, AC_MSKB1)//[12:10]
	#define TS_SAMPLE_REG_CKG_P_TSO2_OUT_0194_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CKG_P_TSO2_OUT_0194_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_P_TSO2_OUT_0194_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0198_TS_SAMPLE (0x198)
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIVNUM_0198_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIVNUM_0198_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIVNUM_0198_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIVNUM_0198_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_PH_TUN_NUM_0198_12_8 Fld(5, 8, AC_MSKB1)//[12:8]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_PH_TUN_NUM_0198_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_PH_TUN_NUM_0198_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_PH_TUN_NUM_0198_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_019C_TS_SAMPLE (0x19C)
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIV_SEL_019C Fld(2, 0, AC_MSKB0)//[1:0]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_PH_TUN_EN_019C Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_01A0_TS_SAMPLE (0x1A0)
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIV_MN_LOAD_01A0 Fld(1, 15, AC_MSKB1)//[15:15]
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIV_MN_N_01A0 Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_01A4_TS_SAMPLE (0x1A4)
	#define TS_SAMPLE_REG_CLK_TSO2_OUT_DIV_MN_M_01A4 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_01A8_TS_SAMPLE (0x1A8)
	#define TS_SAMPLE_REG_CLK_TSO2_TOPAD_INV_01A8 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01AC_TS_SAMPLE (0x1AC)
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_3_2 Fld(2, 2, AC_MSKB0)//[3:2]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_01AC_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_IN_01AC_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_IN_01AC_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_IN_01AC_13_10 Fld(4, 10, AC_MSKB1)//[13:10]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_IN_01AC_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CKG_TSO2_TRACE_IN_01AC_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01C0_TS_SAMPLE (0x1C0)
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSP_01C0_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01C4_TS_SAMPLE (0x1C4)
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CLK_GATING_IP_TSO_01C4_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01C8_TS_SAMPLE (0x1C8)
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TS_SAMPLE_REG_CLK_GATING_IP_DSCRMB_01C8_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01F4_TS_SAMPLE (0x1F4)
	#define TS_SAMPLE_REG_TS_SAMPLE_DEBUG_0_01F4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F8_TS_SAMPLE (0x1F8)
	#define TS_SAMPLE_REG_TS_SAMPLE_DEBUG_1_01F8 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_01FC_TS_SAMPLE (0x1FC)
	#define TS_SAMPLE_REG_DEBUG_SEL_01FC Fld(16, 0, AC_FULLW10)//[15:0]

