/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TSP2_TEST_1
#define REG_0000_TSP2 (0x000)
	#define TSP2_REG_PIDFLT_00_0_0000_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_00_0_0000_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_00_0_0000_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_00_0_0000_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0004_TSP2 (0x004)
	#define TSP2_REG_PIDFLT_00_1_0004_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_00_1_0004_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_00_1_0004_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0008_TSP2 (0x008)
	#define TSP2_REG_PIDFLT_01_0_0008_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_01_0_0008_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_01_0_0008_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_01_0_0008_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_000C_TSP2 (0x00C)
	#define TSP2_REG_PIDFLT_01_1_000C_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_01_1_000C_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_01_1_000C_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0010_TSP2 (0x010)
	#define TSP2_REG_PIDFLT_02_0_0010_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_02_0_0010_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_02_0_0010_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_02_0_0010_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0014_TSP2 (0x014)
	#define TSP2_REG_PIDFLT_02_1_0014_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_02_1_0014_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_02_1_0014_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0018_TSP2 (0x018)
	#define TSP2_REG_PIDFLT_03_0_0018_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_03_0_0018_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_03_0_0018_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_03_0_0018_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_001C_TSP2 (0x01C)
	#define TSP2_REG_PIDFLT_03_1_001C_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_03_1_001C_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_03_1_001C_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0020_TSP2 (0x020)
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI0_0_0020_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0024_TSP2 (0x024)
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI0_1_0024_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_0028_TSP2 (0x028)
	#define TSP2_REG_TSP_FILEIN_RNUM_MMFI0_0_0028 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_002C_TSP2 (0x02C)
	#define TSP2_REG_TSP_FILEIN_RNUM_MMFI0_1_002C Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0030_TSP2 (0x030)
	#define TSP2_REG_TSP_FILEIN_RSTART_MMFI0_0030 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_TSP_FILEIN_DONE_MMFI0_0030 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_TSP_FILEIN_INIT_TRUST_MMFI0_0030 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_TSP_FILE_TIMER_MMFI0_0030_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0034_TSP2 (0x034)
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI0_0034_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI0_0034_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI0_0034_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI0_0034_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI0_0034_9_8 Fld(2, 8, AC_MSKB1)//[9:8]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI0_0034_15_10 Fld(6, 10, AC_MSKB1)//[15:10]
#define REG_0038_TSP2 (0x038)
	#define TSP2_REG_MMFI0_CONFIG0_0038_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI0_CONFIG0_0038_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI0_CONFIG0_0038_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI0_CONFIG0_0038_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI0_CONFIG0_0038_15 Fld(1, 15, AC_MSKB1)//[15:15]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_MMFI0_CONFIG0_0038_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_003C_TSP2 (0x03C)
	#define TSP2_REG_MMFI0_CONFIG1_003C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI0_CONFIG1_003C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI0_CONFIG1_003C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI0_CONFIG1_003C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI0_CONFIG1_003C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI0_CONFIG1_003C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_MMFI0_CONFIG1_003C_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_MMFI0_CONFIG1_003C_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_MMFI0_CONFIG1_003C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_MMFI0_CONFIG1_003C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_MMFI0_CONFIG1_003C_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_MMFI0_CONFIG1_003C_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_MMFI0_CONFIG1_003C_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_MMFI0_CONFIG1_003C_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_MMFI0_CONFIG1_003C_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_MMFI0_CONFIG1_003C_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0040_TSP2 (0x040)
	#define TSP2_REG_TS_HEADER_FILE_MMFI0_0_0040 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0044_TSP2 (0x044)
	#define TSP2_REG_TS_HEADER_FILE_MMFI0_1_0044 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0060_TSP2 (0x060)
	#define TSP2_REG_TIMESTAMP_MMFI0_0_0060 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0064_TSP2 (0x064)
	#define TSP2_REG_TIMESTAMP_MMFI0_1_0064 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_TSP2 (0x068)
	#define TSP2_REG_SW_RSTZ_0068_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_SW_RSTZ_0068_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_SW_RSTZ_0068_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_SW_RSTZ_0068_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_SW_RSTZ_0068_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_SW_RSTZ_0068_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_SW_RSTZ_0068_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_SW_RSTZ_0068_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_SW_RSTZ_0068_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_SW_RSTZ_0068_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_SW_RSTZ_0068_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_SW_RSTZ_0068_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_SW_RSTZ_0068_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_SW_RSTZ_0068_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_SW_RSTZ_0068_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_SW_RSTZ_0068_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_006C_TSP2 (0x06C)
	#define TSP2_REG_INT_ENABLE_006C_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0070_TSP2 (0x070)
	#define TSP2_REG_PKT_CHK_SIZE_MMFI0_0070_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP2_REG_SYNC_BYTE_MMFI0_0070_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0078_TSP2 (0x078)
	#define TSP2_REG_TSP2MI_RADDR_MMFI0_0_0078 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_007C_TSP2 (0x07C)
	#define TSP2_REG_TSP2MI_RADDR_MMFI0_1_007C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0080_TSP2 (0x080)
	#define TSP2_REG_PIDFLT_10_0_0080_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_10_0_0080_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_10_0_0080_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_10_0_0080_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0084_TSP2 (0x084)
	#define TSP2_REG_PIDFLT_10_1_0084_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_10_1_0084_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_10_1_0084_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0088_TSP2 (0x088)
	#define TSP2_REG_PIDFLT_11_0_0088_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_11_0_0088_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_11_0_0088_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_11_0_0088_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_008C_TSP2 (0x08C)
	#define TSP2_REG_PIDFLT_11_1_008C_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_11_1_008C_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_11_1_008C_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0090_TSP2 (0x090)
	#define TSP2_REG_PIDFLT_12_0_0090_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_12_0_0090_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_12_0_0090_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_12_0_0090_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0094_TSP2 (0x094)
	#define TSP2_REG_PIDFLT_12_1_0094_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_12_1_0094_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_12_1_0094_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0098_TSP2 (0x098)
	#define TSP2_REG_PIDFLT_13_0_0098_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_13_0_0098_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_13_0_0098_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_13_0_0098_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_009C_TSP2 (0x09C)
	#define TSP2_REG_PIDFLT_13_1_009C_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_13_1_009C_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_13_1_009C_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_00A0_TSP2 (0x0A0)
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI1_0_00A0_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A4_TSP2 (0x0A4)
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI1_1_00A4_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_00A8_TSP2 (0x0A8)
	#define TSP2_REG_TSP_FILEIN_RNUM_MMFI1_0_00A8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00AC_TSP2 (0x0AC)
	#define TSP2_REG_TSP_FILEIN_RNUM_MMFI1_1_00AC Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00B0_TSP2 (0x0B0)
	#define TSP2_REG_TSP_FILEIN_RSTART_MMFI1_00B0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_TSP_FILEIN_DONE_MMFI1_00B0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_TSP_FILEIN_INIT_TRUST_MMFI1_00B0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_TSP_FILE_TIMER_MMFI1_00B0_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00B4_TSP2 (0x0B4)
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI1_00B4_4_0 Fld(5, 0, AC_MSKB0)//[4:0]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI1_00B4_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI1_00B4_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI1_00B4_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI1_00B4_9_8 Fld(2, 8, AC_MSKB1)//[9:8]
	#define TSP2_REG_CMD_QUEUE_STATUS_MMFI1_00B4_15_10 Fld(6, 10, AC_MSKB1)//[15:10]
#define REG_00B8_TSP2 (0x0B8)
	#define TSP2_REG_MMFI1_CONFIG0_00B8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_15 Fld(1, 15, AC_MSKB1)//[15:15]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_MMFI1_CONFIG0_00B8_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_00BC_TSP2 (0x0BC)
	#define TSP2_REG_MMFI1_CONFIG1_00BC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_MMFI1_CONFIG1_00BC_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00C0_TSP2 (0x0C0)
	#define TSP2_REG_TS_HEADER_FILE_MMFI1_0_00C0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C4_TSP2 (0x0C4)
	#define TSP2_REG_TS_HEADER_FILE_MMFI1_1_00C4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E0_TSP2 (0x0E0)
	#define TSP2_REG_TIMESTAMP_MMFI1_0_00E0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E4_TSP2 (0x0E4)
	#define TSP2_REG_TIMESTAMP_MMFI1_1_00E4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E8_TSP2 (0x0E8)
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI0_EXT_00E8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI0_EXT_00E8_RESERVED_1 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00EC_TSP2 (0x0EC)
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI1_EXT_00EC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_TSP_FILEIN_RADDR_MMFI1_EXT_00EC_RESERVED_1 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00F0_TSP2 (0x0F0)
	#define TSP2_REG_PKT_CHK_SIZE_MMFI1_00F0_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP2_REG_SYNC_BYTE_MMFI1_00F0_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00F8_TSP2 (0x0F8)
	#define TSP2_REG_TSP2MI_RADDR_MMFI1_0_00F8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00FC_TSP2 (0x0FC)
	#define TSP2_REG_TSP2MI_RADDR_MMFI1_1_00FC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0100_TSP2 (0x100)
	#define TSP2_REG_MMFI0_RVU_0100_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI0_RVU_0100_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI0_RVU_0100_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI0_RVU_0100_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI0_RVU_0100_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI0_RVU_0100_15_5 Fld(11, 5, AC_MSKW10)//[15:5]
#define REG_0104_TSP2 (0x104)
	#define TSP2_REG_MMFI1_RVU_0104_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI1_RVU_0104_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI1_RVU_0104_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI1_RVU_0104_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI1_RVU_0104_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI1_RVU_0104_15_5 Fld(11, 5, AC_MSKW10)//[15:5]
#define REG_0140_TSP2 (0x140)
	#define TSP2_REG_MMFI0_CONFIG2_0140_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI0_CONFIG2_0140_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI0_CONFIG2_0140_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI0_CONFIG2_0140_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI0_CONFIG2_0140_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI0_CONFIG2_0140_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_MMFI0_CONFIG2_0140_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_MMFI0_CONFIG2_0140_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_MMFI0_CONFIG2_0140_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_MMFI0_CONFIG2_0140_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_MMFI0_CONFIG2_0140_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_MMFI0_CONFIG2_0140_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_MMFI0_CONFIG2_0140_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_MMFI0_CONFIG2_0140_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_MMFI0_CONFIG2_0140_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_MMFI0_CONFIG2_0140_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0144_TSP2 (0x144)
	#define TSP2_REG_MMFI1_CONFIG2_0144_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_MMFI1_CONFIG2_0144_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_MMFI1_CONFIG2_0144_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP2_REG_MMFI1_CONFIG2_0144_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP2_REG_MMFI1_CONFIG2_0144_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP2_REG_MMFI1_CONFIG2_0144_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP2_REG_MMFI1_CONFIG2_0144_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP2_REG_MMFI1_CONFIG2_0144_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP2_REG_MMFI1_CONFIG2_0144_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP2_REG_MMFI1_CONFIG2_0144_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP2_REG_MMFI1_CONFIG2_0144_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP2_REG_MMFI1_CONFIG2_0144_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP2_REG_MMFI1_CONFIG2_0144_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP2_REG_MMFI1_CONFIG2_0144_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_MMFI1_CONFIG2_0144_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_MMFI1_CONFIG2_0144_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0158_TSP2 (0x158)
	#define TSP2_REG_PIDFLT_04_0_0158_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_04_0_0158_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_04_0_0158_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_04_0_0158_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_015C_TSP2 (0x15C)
	#define TSP2_REG_PIDFLT_04_1_015C_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_04_1_015C_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_04_1_015C_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0160_TSP2 (0x160)
	#define TSP2_REG_PIDFLT_05_0_0160_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_05_0_0160_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_05_0_0160_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_05_0_0160_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0164_TSP2 (0x164)
	#define TSP2_REG_PIDFLT_05_1_0164_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_05_1_0164_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_05_1_0164_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0178_TSP2 (0x178)
	#define TSP2_REG_PIDFLT_14_0_0178_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_14_0_0178_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_14_0_0178_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_14_0_0178_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_017C_TSP2 (0x17C)
	#define TSP2_REG_PIDFLT_14_1_017C_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_14_1_017C_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_14_1_017C_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0180_TSP2 (0x180)
	#define TSP2_REG_PIDFLT_15_0_0180_12_0 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP2_REG_PIDFLT_15_0_0180_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP2_REG_PIDFLT_15_0_0180_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP2_REG_PIDFLT_15_0_0180_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0184_TSP2 (0x184)
	#define TSP2_REG_PIDFLT_15_1_0184_16 Fld(1, 16, AC_MSKB2)//[16:16]
	#define TSP2_REG_PIDFLT_15_1_0184_17 Fld(1, 17, AC_MSKB2)//[17:17]
	#define TSP2_REG_PIDFLT_15_1_0184_18 Fld(1, 18, AC_MSKB2)//[18:18]
#define REG_0198_TSP2 (0x198)
	#define TSP2_REG_ATS_MODE_MMFI0_0198 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_ATS_OFFSET_EN_MMFI0_0198 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_ATS_OFFSET_MMFI0_0198_11_8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP2_REG_ATS_OFFSET_MMFI0_0198_12 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_019C_TSP2 (0x19C)
	#define TSP2_REG_ATS_MODE_MMFI1_019C Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_ATS_OFFSET_EN_MMFI1_019C Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_ATS_OFFSET_MMFI1_019C_11_8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP2_REG_ATS_OFFSET_MMFI1_019C_12 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_01A0_TSP2 (0x1A0)
	#define TSP2_REG_SYNC_BYTE_PRIVILEGE_MM0_01A0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP2_REG_REPLACE_PRIVILEGE_SYNC_BYTE_MM0_01A0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01A4_TSP2 (0x1A4)
	#define TSP2_REG_SYNC_BYTE_PRIVILEGE_MM1_01A4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP2_REG_REPLACE_PRIVILEGE_SYNC_BYTE_MM1_01A4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01A8_TSP2 (0x1A8)
	#define TSP2_REG_CHK_PRIVILEGE_SYNC_BYTE_ENABLE_MM0_01A8 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01AC_TSP2 (0x1AC)
	#define TSP2_REG_CHK_PRIVILEGE_SYNC_BYTE_ENABLE_MM1_01AC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01C0_TSP2 (0x1C0)
	#define TSP2_REG_QMEM_DBG_MODE_01C0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP2_REG_TSP_SEL_SRAM_01C0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP2_REG_ARM_SRAM_SEL_IN_TSP_TOP_GROUP_01C0 Fld(1, 2, AC_MSKB0)//[2:2]

//Page TSP2_TEST_2
#define REG_01C4_TSP2 (0x1C4)
	#define TSP2_REG_QMEM_DBG_RADDR_01C4_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C8_TSP2 (0x1C8)
	#define TSP2_REG_QMEM_DBG_RD_0_01C8_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01CC_TSP2 (0x1CC)
	#define TSP2_REG_QMEM_DBG_RD_1_01CC_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_01E0_TSP2 (0x1E0)
	#define TSP2_REG_UPDATE_MATCH_PID_PUSI_01E0 Fld(1, 7, AC_MSKB0)//[7:7]

