/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TSO_SEC2_TEST
#define REG_01C0_TSO_SEC2 (0x1C0)
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_0_01C0_3_0 Fld(4,0,AC_MSKB0)//[3:0]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_0_01C0_7_4 Fld(4,4,AC_MSKB0)//[7:4]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_0_01C0_11_8 Fld(4,8,AC_MSKB1)//[11:8]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_0_01C0_15_12 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01C4_TSO_SEC2 (0x1C4)
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_1_01C4_19_16 Fld(4,16,AC_MSKB2)//[19:16]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_1_01C4_23_20 Fld(4,20,AC_MSKB2)//[23:20]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_1_01C4_27_24 Fld(4,24,AC_MSKB3)//[27:24]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT0_1_01C4_31_28 Fld(4,28,AC_MSKB3)//[31:28]
#define REG_01C8_TSO_SEC2 (0x1C8)
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT1_01C8_3_0 Fld(4,0,AC_MSKB0)//[3:0]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT1_01C8_7_4 Fld(4,4,AC_MSKB0)//[7:4]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT1_01C8_11_8 Fld(4,8,AC_MSKB1)//[11:8]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT1_01C8_15_12 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01CC_TSO_SEC2 (0x1CC)
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT2_01CC_3_0 Fld(4,0,AC_MSKB0)//[3:0]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT2_01CC_7_4 Fld(4,4,AC_MSKB0)//[7:4]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT2_01CC_11_8 Fld(4,8,AC_MSKB1)//[11:8]
    #define TSO_SEC2_REG_MIU_LAT_THOLD_ABT2_01CC_15_12 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01D0_TSO_SEC2 (0x1D0)
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_0_01D0_3_0 Fld(4,0,AC_MSKB0)//[3:0]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_0_01D0_7_4 Fld(4,4,AC_MSKB0)//[7:4]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_0_01D0_11_8 Fld(4,8,AC_MSKB1)//[11:8]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_0_01D0_15_12 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01D4_TSO_SEC2 (0x1D4)
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_1_01D4_19_16 Fld(4,16,AC_MSKB2)//[19:16]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_1_01D4_23_20 Fld(4,20,AC_MSKB2)//[23:20]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_1_01D4_27_24 Fld(4,24,AC_MSKB3)//[27:24]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_1_01D4_31_28 Fld(4,28,AC_MSKB3)//[31:28]
#define REG_01D8_TSO_SEC2 (0x1D8)
    #define TSO_SEC2_REG_MIU_LAT_CYCLE_PER_TICK_01D8_15_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01DC_TSO_SEC2 (0x1DC)
    #define TSO_SEC2_REG_MIU_LAT_CYCLE_CNT_EN_01DC Fld(1,0,AC_MSKB0)//[0:0]
    #define TSO_SEC2_REG_MIU_LAT_CYCLE_CNT_CLR_01DC Fld(1,1,AC_MSKB0)//[1:1]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_EN_01DC Fld(1,2,AC_MSKB0)//[2:2]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_CLR_01DC Fld(1,3,AC_MSKB0)//[3:3]
    #define TSO_SEC2_REG_MIU_LAT_LEVEL_EVER_ABT_SEL_01DC_7_4 Fld(4,4,AC_MSKB0)//[7:4]
#define REG_01E0_TSO_SEC2 (0x1E0)
    #define TSO_SEC2_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_01E0_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define TSO_SEC2_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_01E0_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define TSO_SEC2_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_01E0_15_2 Fld(14,2,AC_MSKW10)//[15:2]
#define REG_01E4_TSO_SEC2 (0x1E4)
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_4 Fld(1,4,AC_MSKB0)//[4:4]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_0_01E4_RESERVED_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_0_01E4_9 Fld(1,9,AC_MSKB1)//[9:9]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_0_01E4_10 Fld(1,10,AC_MSKB1)//[10:10]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_0_01E4_11 Fld(1,11,AC_MSKB1)//[11:11]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_0_01E4_12 Fld(1,12,AC_MSKB1)//[12:12]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_0_01E4_13 Fld(1,13,AC_MSKB1)//[13:13]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_0_01E4_RESERVED_8 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_01E8_TSO_SEC2 (0x1E8)
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_4 Fld(1,4,AC_MSKB0)//[4:4]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_RESERVED_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_1_01E8_RESERVED_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_1_01E8_9 Fld(1,9,AC_MSKB1)//[9:9]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_1_01E8_10 Fld(1,10,AC_MSKB1)//[10:10]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_1_01E8_11 Fld(1,11,AC_MSKB1)//[11:11]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_1_01E8_12 Fld(1,12,AC_MSKB1)//[12:12]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_1_01E8_13 Fld(1,13,AC_MSKB1)//[13:13]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_1_01E8_RESERVED_8 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_01EC_TSO_SEC2 (0x1EC)
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_4 Fld(1,4,AC_MSKB0)//[4:4]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_RESERVED_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define TSO_SEC2_REG_MIU_ABT_CONFIG_2_01EC_RESERVED_7 Fld(1,7,AC_MSKB0)//[7:7]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_2_01EC_9 Fld(1,9,AC_MSKB1)//[9:9]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_2_01EC_10 Fld(1,10,AC_MSKB1)//[10:10]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_2_01EC_11 Fld(1,11,AC_MSKB1)//[11:11]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_2_01EC_12 Fld(1,12,AC_MSKB1)//[12:12]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_2_01EC_13 Fld(1,13,AC_MSKB1)//[13:13]
    #define TSO_SEC2_REG_MIU_ABT_STATUS_2_01EC_RESERVED_8 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_01F0_TSO_SEC2 (0x1F0)
    #define TSO_SEC2_REG_MIU_ULTRA_THOLD_01F0 Fld(4,8,AC_MSKB1)//[11:8]

