/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

#ifndef _REG_MAD_H_
#define _REG_MAD_H_
#include "mtk_dmx_regs.h"
//----------------------------------------
//	Macro and Define
//----------------------------------------
#define MAD_RIU_READ_BYTE(addr) \
	(reg16_mask_read((REG16 *)(addr), 0xFF, 0))
#define MAD_RIU_READ_WORD(addr) \
	(reg16_read((REG16 *)(addr)))
#define MAD_Read2Byte(addr) \
	(MAD_RIU_READ_WORD((addr)<<1))
#define MAD_RIU_MASK_READ_WORD(addr, mask, shift) \
	(reg16_mask_read((REG16 *)(addr), mask, shift))
#define MAD_RIU_WRITE_BYTE(addr, val) \
	{reg16_mask_write((REG16 *)(addr), 0xFF, val); }
#define MAD_RIU_WRITE_WORD(addr, val) \
	{reg16_write((REG16 *)(addr), val); }
#define MAD_WriteByteMask(addr, mask, val) \
	MAD_RIU_WRITE_BYTE((((addr) << 1) - ((addr) & 1)), \
	(MAD_RIU_READ_BYTE((((addr) << 1) - ((addr) & 1))) & ~(mask)) | \
	((val) & (mask)))

#define MAD_RIU_MASK_WRITE_WORD(addr, mask, val) \
	(reg16_mask_write((REG16 *)(addr), mask, val))

/* Parser Ctrl */
#define REG_PASA_SELECT_STR_TYPE	0xE
#define REG_PASB_SELECT_STR_TYPE	0xE00
#define REG_PASC_SELECT_STR_TYPE	0xE
#define REG_PASD_SELECT_STR_TYPE	0xE00
//=======================================================
//------------------------------------------------------------------------------
// Base Address
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MAD Reg
//------------------------------------------------------------------------------
// Configure PAS
#define REG_MAD_MCU_CTRL			(REG_MAD1_BASE + ((0x0)<<1))
#define REG_MAD_CTRL				(REG_MAD1_BASE + ((0x2)<<1))
#define REG_PAS_SELECT				(REG_MAD1_BASE + ((0x4)<<1))
#define REG_MAD_CTRL2				(REG_MAD1_BASE + ((0x4E)<<1))
#define REG_PAS_SELECT2				(REG_MAD1_BASE + ((0x50)<<1))
#define REG_MAD_CTRL3				(REG_MAD1_BASE + ((0xCA)<<1))

#define REG_PAS_SOURCE_SELECT				(REG_MAD3_BASE + ((0x4)<<1))

#define REG_PAS_PTS_INT                          (REG_MAD1_BASE + ((0x9A)<<1))
#define REG_PAS_PTS_INT_CTRL                     (REG_MAD1_BASE + ((0x9C)<<1))

#define REG_PASA_CTRL                            (REG_MAD1_BASE + ((0x6)<<1))
#define REG_PASA_STREAM_ID1                      (REG_MAD1_BASE + ((0x8)<<1))
#define REG_PASA_STREAM_ID2                      (REG_MAD1_BASE + ((0xA)<<1))
#define REG_PASA_EXTRA_HDR_CTRL                  (REG_MAD1_BASE + ((0xC)<<1))
#define REG_PASA_EXTRA_HDR_OFFSET                (REG_MAD1_BASE + ((0xE)<<1))
#define REG_PASA_RDATA_A                         (REG_MAD1_BASE + ((0x10)<<1))
#define REG_PASA_STATUS                          (REG_MAD1_BASE + ((0x12)<<1))
#define REG_PASA_ES1_CTRL                        (REG_MAD1_BASE + ((0x14)<<1))
#define REG_PASA_ES1_RDCNT                       (REG_MAD1_BASE + ((0x16)<<1))
#define REG_PASA_ES1_UPDCNT                      (REG_MAD1_BASE + ((0x18)<<1))
#define REG_PASA_PTS_L                           (REG_MAD1_BASE + ((0x1A)<<1))
#define REG_PASA_PTS_H                           (REG_MAD1_BASE + ((0x1C)<<1))
#define REG_PASA_SCR_0                           (REG_MAD1_BASE + ((0x1E)<<1))
#define REG_PASA_SCR_1                           (REG_MAD1_BASE + ((0x20)<<1))
#define REG_PASA_SCR_2                           (REG_MAD1_BASE + ((0x22)<<1))
#define REG_PASA_SCR_3                           (REG_MAD1_BASE + ((0x24)<<1))

#define REG_PASB_CTRL                            (REG_MAD1_BASE + ((0x26)<<1))
#define REG_PASB_STREAM_ID1                      (REG_MAD1_BASE + ((0x28)<<1))
#define REG_PASB_STREAM_ID2                      (REG_MAD1_BASE + ((0x2A)<<1))
#define REG_PASB_EXTRA_HDR_CTRL                  (REG_MAD1_BASE + ((0x2C)<<1))
#define REG_PASB_EXTRA_HDR_OFFSET                (REG_MAD1_BASE + ((0x2E)<<1))
#define REG_PASB_RDATA_A                         (REG_MAD1_BASE + ((0x30)<<1))
#define REG_PASB_STATUS                          (REG_MAD1_BASE + ((0x32)<<1))
#define REG_PASB_ES2_CTRL                        (REG_MAD1_BASE + ((0x34)<<1))
#define REG_PASB_ES2_RDCNT                       (REG_MAD1_BASE + ((0x36)<<1))
#define REG_PASB_ES2_UPDCNT                      (REG_MAD1_BASE + ((0x38)<<1))
#define REG_PASB_PTS_L                           (REG_MAD1_BASE + ((0x3A)<<1))
#define REG_PASB_PTS_H                           (REG_MAD1_BASE + ((0x3C)<<1))
#define REG_PASB_SCR_0                           (REG_MAD1_BASE + ((0x3E)<<1))
#define REG_PASB_SCR_1                           (REG_MAD1_BASE + ((0x40)<<1))
#define REG_PASB_SCR_2                           (REG_MAD1_BASE + ((0x42)<<1))
#define REG_PASB_SCR_3                           (REG_MAD1_BASE + ((0x44)<<1))

#define REG_PASC_CTRL                            (REG_MAD1_BASE + ((0x52)<<1))
#define REG_PASC_STREAM_ID1                      (REG_MAD1_BASE + ((0x54)<<1))
#define REG_PASC_STREAM_ID2                      (REG_MAD1_BASE + ((0x56)<<1))
#define REG_PASC_EXTRA_HDR_CTRL                  (REG_MAD1_BASE + ((0x58)<<1))
#define REG_PASC_EXTRA_HDR_OFFSET                (REG_MAD1_BASE + ((0x5A)<<1))
#define REG_PASC_RDATA_A                         (REG_MAD1_BASE + ((0x5C)<<1))
#define REG_PASC_STATUS                          (REG_MAD1_BASE + ((0x5E)<<1))
#define REG_PASC_ES3_CTRL                        (REG_MAD1_BASE + ((0x60)<<1))
#define REG_PASC_ES3_RDCNT                       (REG_MAD1_BASE + ((0x62)<<1))
#define REG_PASC_ES3_UPDCNT                      (REG_MAD1_BASE + ((0x64)<<1))
#define REG_PASC_PTS_L                           (REG_MAD1_BASE + ((0x66)<<1))
#define REG_PASC_PTS_H                           (REG_MAD1_BASE + ((0x68)<<1))
#define REG_PASC_SCR_0                           (REG_MAD1_BASE + ((0x6A)<<1))
#define REG_PASC_SCR_1                           (REG_MAD1_BASE + ((0x6C)<<1))
#define REG_PASC_SCR_2                           (REG_MAD1_BASE + ((0x6E)<<1))
#define REG_PASC_SCR_3                           (REG_MAD1_BASE + ((0x70)<<1))

#define REG_PASD_CTRL                            (REG_MAD1_BASE + ((0x72)<<1))
#define REG_PASD_STREAM_ID1                      (REG_MAD1_BASE + ((0x74)<<1))
#define REG_PASD_STREAM_ID2                      (REG_MAD1_BASE + ((0x76)<<1))
#define REG_PASD_EXTRA_HDR_CTRL                  (REG_MAD1_BASE + ((0x78)<<1))
#define REG_PASD_EXTRA_HDR_OFFSET                (REG_MAD1_BASE + ((0x7A)<<1))
#define REG_PASD_RDATA_A                         (REG_MAD1_BASE + ((0x7C)<<1))
#define REG_PASD_STATUS                          (REG_MAD1_BASE + ((0x7E)<<1))
#define REG_PASD_ES4_CTRL                        (REG_MAD1_BASE + ((0x80)<<1))
#define REG_PASD_ES4_RDCNT                       (REG_MAD1_BASE + ((0x82)<<1))
#define REG_PASD_ES4_UPDCNT                      (REG_MAD1_BASE + ((0x84)<<1))
#define REG_PASD_PTS_L                           (REG_MAD1_BASE + ((0x86)<<1))
#define REG_PASD_PTS_H                           (REG_MAD1_BASE + ((0x88)<<1))
#define REG_PASD_SCR_0                           (REG_MAD1_BASE + ((0x8A)<<1))
#define REG_PASD_SCR_1                           (REG_MAD1_BASE + ((0x8C)<<1))
#define REG_PASD_SCR_2                           (REG_MAD1_BASE + ((0x8E)<<1))
#define REG_PASD_SCR_3                           (REG_MAD1_BASE + ((0x90)<<1))

#define REG_PASA_DMA_CTRL                        (REG_MAD0_BASE + ((0x00)<<1))
#define REG_PASA_DMA_CTRL_1                      (REG_MAD0_BASE + ((0x02)<<1))
#define REG_PASA_DMA_DRAM_L                      (REG_MAD0_BASE + ((0x04)<<1))
#define REG_PASA_DMA_DRAM_H                      (REG_MAD0_BASE + ((0x06)<<1))
#define REG_PASA_DMA_DRAM_SIZE                   (REG_MAD0_BASE + ((0x08)<<1))
#define REG_PASA_DMA_MIU_BURST_LENGTH            (REG_MAD0_BASE + ((0x0A)<<1))
#define REG_PASA_DMA_MCU_READ_SIZE               (REG_MAD0_BASE + ((0x0C)<<1))
#define REG_PASA_DMA_DRAM_OVERRUN_THRESHOLD      (REG_MAD0_BASE + ((0x0E)<<1))
#define REG_PASA_DMA_ES1_RDCNT                   (REG_MAD0_BASE + ((0x10)<<1))
#define REG_PASA_DMA_ES1_UPDCNT                  (REG_MAD0_BASE + ((0x12)<<1))
#define REG_PASA_DMA_DRAM_LEVEL_CNT              (REG_MAD0_BASE + ((0x14)<<1))
#define REG_PASA_DMA_DRAM_WRITE_POINT            (REG_MAD0_BASE + ((0x16)<<1))
#define REG_PASA_DMA_FIFO_STATUS                 (REG_MAD0_BASE + ((0x18)<<1))
#define REG_PASA_DMA_DRAM_STATUS                 (REG_MAD0_BASE + ((0x1A)<<1))
#define REG_PASA_DMA_TEST_MODE                   (REG_MAD0_BASE + ((0x1C)<<1))
#define REG_PASA_DMA_SCR_3                       (REG_MAD0_BASE + ((0x1E)<<1))

#define REG_PASB_DMA_CTRL                        (REG_MAD0_BASE + ((0x20)<<1))
#define REG_PASB_DMA_CTRL_1                      (REG_MAD0_BASE + ((0x22)<<1))
#define REG_PASB_DMA_DRAM_L                      (REG_MAD0_BASE + ((0x24)<<1))
#define REG_PASB_DMA_DRAM_H                      (REG_MAD0_BASE + ((0x26)<<1))
#define REG_PASB_DMA_DRAM_SIZE                   (REG_MAD0_BASE + ((0x28)<<1))
#define REG_PASB_DMA_MIU_BURST_LENGTH            (REG_MAD0_BASE + ((0x2A)<<1))
#define REG_PASB_DMA_MCU_READ_SIZE               (REG_MAD0_BASE + ((0x2C)<<1))
#define REG_PASB_DMA_DRAM_OVERRUN_THRESHOLD      (REG_MAD0_BASE + ((0x2E)<<1))
#define REG_PASB_DMA_ES2_RDCNT                   (REG_MAD0_BASE + ((0x30)<<1))
#define REG_PASB_DMA_ES2_UPDCNT                  (REG_MAD0_BASE + ((0x32)<<1))
#define REG_PASB_DMA_DRAM_LEVEL_CNT              (REG_MAD0_BASE + ((0x34)<<1))
#define REG_PASB_DMA_DRAM_WRITE_POINT            (REG_MAD0_BASE + ((0x36)<<1))
#define REG_PASB_DMA_FIFO_STATUS                 (REG_MAD0_BASE + ((0x38)<<1))
#define REG_PASB_DMA_DRAM_STATUS                 (REG_MAD0_BASE + ((0x3A)<<1))
#define REG_PASB_DMA_TEST_MODE                   (REG_MAD0_BASE + ((0x3C)<<1))
#define REG_PASB_DMA_SCR_3                       (REG_MAD0_BASE + ((0x3E)<<1))

#define REG_PASC_DMA_CTRL                        (REG_MAD0_BASE + ((0x40)<<1))
#define REG_PASC_DMA_CTRL_1                      (REG_MAD0_BASE + ((0x42)<<1))
#define REG_PASC_DMA_DRAM_L                      (REG_MAD0_BASE + ((0x44)<<1))
#define REG_PASC_DMA_DRAM_H                      (REG_MAD0_BASE + ((0x46)<<1))
#define REG_PASC_DMA_DRAM_SIZE                   (REG_MAD0_BASE + ((0x48)<<1))
#define REG_PASC_DMA_MIU_BURST_LENGTH            (REG_MAD0_BASE + ((0x4A)<<1))
#define REG_PASC_DMA_MCU_READ_SIZE               (REG_MAD0_BASE + ((0x4C)<<1))
#define REG_PASC_DMA_DRAM_OVERRUN_THRESHOLD      (REG_MAD0_BASE + ((0x4E)<<1))
#define REG_PASC_DMA_ES3_RDCNT                   (REG_MAD0_BASE + ((0x50)<<1))
#define REG_PASC_DMA_ES3_UPDCNT                  (REG_MAD0_BASE + ((0x52)<<1))
#define REG_PASC_DMA_DRAM_LEVEL_CNT              (REG_MAD0_BASE + ((0x54)<<1))
#define REG_PASC_DMA_DRAM_WRITE_POINT            (REG_MAD0_BASE + ((0x56)<<1))
#define REG_PASC_DMA_FIFO_STATUS                 (REG_MAD0_BASE + ((0x58)<<1))
#define REG_PASC_DMA_DRAM_STATUS                 (REG_MAD0_BASE + ((0x5A)<<1))
#define REG_PASC_DMA_TEST_MODE                   (REG_MAD0_BASE + ((0x5C)<<1))
#define REG_PASC_DMA_SCR_3                       (REG_MAD0_BASE + ((0x5E)<<1))

#define REG_PASD_DMA_CTRL                        (REG_MAD0_BASE + ((0x60)<<1))
#define REG_PASD_DMA_CTRL_1                      (REG_MAD0_BASE + ((0x62)<<1))
#define REG_PASD_DMA_DRAM_L                      (REG_MAD0_BASE + ((0x64)<<1))
#define REG_PASD_DMA_DRAM_H                      (REG_MAD0_BASE + ((0x66)<<1))
#define REG_PASD_DMA_DRAM_SIZE                   (REG_MAD0_BASE + ((0x68)<<1))
#define REG_PASD_DMA_MIU_BURST_LENGTH            (REG_MAD0_BASE + ((0x6A)<<1))
#define REG_PASD_DMA_MCU_READ_SIZE               (REG_MAD0_BASE + ((0x6C)<<1))
#define REG_PASD_DMA_DRAM_OVERRUN_THRESHOLD      (REG_MAD0_BASE + ((0x6E)<<1))
#define REG_PASD_DMA_ES4_RDCNT                   (REG_MAD0_BASE + ((0x70)<<1))
#define REG_PASD_DMA_ES4_UPDCNT                  (REG_MAD0_BASE + ((0x72)<<1))
#define REG_PASD_DMA_DRAM_LEVEL_CNT              (REG_MAD0_BASE + ((0x74)<<1))
#define REG_PASD_DMA_DRAM_WRITE_POINT            (REG_MAD0_BASE + ((0x76)<<1))
#define REG_PASD_DMA_FIFO_STATUS                 (REG_MAD0_BASE + ((0x78)<<1))
#define REG_PASD_DMA_DRAM_STATUS                 (REG_MAD0_BASE + ((0x7A)<<1))
#define REG_PASD_DMA_TEST_MODE                   (REG_MAD0_BASE + ((0x7C)<<1))
#define REG_PASD_DMA_SCR_3                       (REG_MAD0_BASE + ((0x7E)<<1))

#define REG_PASA_CTRL_2ND                        (REG_MAD2_BASE + ((0x00)<<1))
#define REG_PASA_CTRL_2ND_1                      (REG_MAD2_BASE + ((0x02)<<1))
#define REG_PASA_CTRL_2ND_INFO                   (REG_MAD2_BASE + ((0x0A)<<1))
#define REG_PASA_ISDB_PARSER_BYTE_COUNT_L        (REG_MAD2_BASE + ((0x0C)<<1))
#define REG_PASA_ISDB_PARSER_BYTE_COUNT_H        (REG_MAD2_BASE + ((0x0E)<<1))
#define REG_PASA_ISDB_PARSER_LNG_L               (REG_MAD2_BASE + ((0x10)<<1))
#define REG_PASA_ISDB_PARSER_LNG_H               (REG_MAD2_BASE + ((0x12)<<1))
#define REG_PASA_ISDB_PARSER_SEQ_L               (REG_MAD2_BASE + ((0x14)<<1))
#define REG_PASA_ISDB_PARSER_SEQ_H               (REG_MAD2_BASE + ((0x16)<<1))

#define REG_PASB_CTRL_2ND                        (REG_MAD2_BASE + ((0x40)<<1))
#define REG_PASB_CTRL_2ND_1                      (REG_MAD2_BASE + ((0x42)<<1))
#define REG_PASB_CTRL_2ND_INFO                   (REG_MAD2_BASE + ((0x4A)<<1))
#define REG_PASB_ISDB_PARSER_BYTE_COUNT_L        (REG_MAD2_BASE + ((0x4C)<<1))
#define REG_PASB_ISDB_PARSER_BYTE_COUNT_H        (REG_MAD2_BASE + ((0x4E)<<1))
#define REG_PASB_ISDB_PARSER_LNG_L               (REG_MAD2_BASE + ((0x50)<<1))
#define REG_PASB_ISDB_PARSER_LNG_H               (REG_MAD2_BASE + ((0x52)<<1))
#define REG_PASB_ISDB_PARSER_SEQ_L               (REG_MAD2_BASE + ((0x54)<<1))
#define REG_PASB_ISDB_PARSER_SEQ_H               (REG_MAD2_BASE + ((0x56)<<1))

#define REG_PASC_CTRL_2ND                        (REG_MAD2_BASE + ((0x80)<<1))
#define REG_PASC_CTRL_2ND_1                      (REG_MAD2_BASE + ((0x82)<<1))
#define REG_PASC_CTRL_2ND_INFO                   (REG_MAD2_BASE + ((0x8A)<<1))
#define REG_PASC_ISDB_PARSER_BYTE_COUNT_L        (REG_MAD2_BASE + ((0x8C)<<1))
#define REG_PASC_ISDB_PARSER_BYTE_COUNT_H        (REG_MAD2_BASE + ((0x8E)<<1))
#define REG_PASC_ISDB_PARSER_LNG_L               (REG_MAD2_BASE + ((0x90)<<1))
#define REG_PASC_ISDB_PARSER_LNG_H               (REG_MAD2_BASE + ((0x92)<<1))
#define REG_PASC_ISDB_PARSER_SEQ_L               (REG_MAD2_BASE + ((0x94)<<1))
#define REG_PASC_ISDB_PARSER_SEQ_H               (REG_MAD2_BASE + ((0x96)<<1))

#define REG_PASD_CTRL_2ND                        (REG_MAD2_BASE + ((0xC0)<<1))
#define REG_PASD_CTRL_2ND_1                      (REG_MAD2_BASE + ((0xC2)<<1))
#define REG_PASD_CTRL_2ND_INFO                   (REG_MAD2_BASE + ((0xCA)<<1))
#define REG_PASD_ISDB_PARSER_BYTE_COUNT_L        (REG_MAD2_BASE + ((0xCC)<<1))
#define REG_PASD_ISDB_PARSER_BYTE_COUNT_H        (REG_MAD2_BASE + ((0xCE)<<1))
#define REG_PASD_ISDB_PARSER_LNG_L               (REG_MAD2_BASE + ((0xD0)<<1))
#define REG_PASD_ISDB_PARSER_LNG_H               (REG_MAD2_BASE + ((0xD2)<<1))
#define REG_PASD_ISDB_PARSER_SEQ_L               (REG_MAD2_BASE + ((0xD4)<<1))
#define REG_PASD_ISDB_PARSER_SEQ_H               (REG_MAD2_BASE + ((0xD6)<<1))
#define REG_PAS_AB_PTS_BYTE_CTRL    (REG_MAD1_BASE + ((0xA6)<<1))
#define REG_PAS_CD_PTS_BYTE_CTRL    (REG_MAD1_BASE + ((0xCA)<<1))
#define REG_PASA_PTS_BYTE_COUNT_L   (REG_MAD1_BASE + ((0xEE)<<1))
#define REG_PASA_PTS_BYTE_COUNT_H   (REG_MAD1_BASE + ((0xF0)<<1))
#define REG_PASB_PTS_BYTE_COUNT_L   (REG_MAD1_BASE + ((0xF2)<<1))
#define REG_PASB_PTS_BYTE_COUNT_H   (REG_MAD1_BASE + ((0xF4)<<1))
#define REG_PASC_PTS_BYTE_COUNT_L   (REG_MAD1_BASE + ((0xF6)<<1))
#define REG_PASC_PTS_BYTE_COUNT_H   (REG_MAD1_BASE + ((0xF8)<<1))
#define REG_PASD_PTS_BYTE_COUNT_L   (REG_MAD1_BASE + ((0xFA)<<1))
#define REG_PASD_PTS_BYTE_COUNT_H   (REG_MAD1_BASE + ((0xFC)<<1))

#endif // _REG_MAD_H_
