/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
#ifndef __MTK_IOMMU_AGILE_DMAHEAP_H__
#define __MTK_IOMMU_AGILE_DMAHEAP_H__


#define NUM_ORDERS 3
#define CMA_POOL_IS_ENABLE 1
extern struct mtk_iommu_dmabuf_page_pool *agile_pools[NUM_ORDERS];
#if CMA_POOL_IS_ENABLE
#define AGILE_CMA_ALIGN SZ_4M
extern struct mtk_iommu_dmabuf_page_pool *cma_pool;
extern atomic_t cma_used;
extern bool agile_has_cma;
#endif
extern unsigned long max_cma_size;
extern unsigned int out_of_pool_times;
void mtk_iommu_collect(size_t *size);
int mtk_agile_dmaheap_create(struct device *dev);
void mtk_agile_dmaheap_destroy(void);

#endif
