/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _REG_PCMCIA_H_
#define _REG_PCMCIA_H_

//-----------------------------------------------------------------------------
//	Hardware Capability
//-----------------------------------------------------------------------------
// Base address should be initial.
#define PCMCIA_RIU_MAP u32PCMCIA_RIU_BaseAdd	//obtain in init

//-----------------------------------------------------------------------------
//	Macro and Define
//-----------------------------------------------------------------------------
//hardware spec



#define PCMBURST_WRITE			 0x0001
#define PCMBURST_READ			 0x0010
#define PCMBURST_STATUS			 0x0100

#define REG_COMPANION_PM_CLKGEN	0x000F00
#define REG_CKG_MCU				(REG_COMPANION_PM_CLKGEN + 0x40UL)
#define SW_MCU_CLK				0x80UL

#define REG_COMPANION_TOP_BANK		 0x101E00
#define REG_COMPANION_CHIPTOP_TS0_GPIO_OEN_LSB0 (REG_COMPANION_TOP_BANK + 0x48UL)  // 0x24 [7:0]
#define REG_COMPANION_CHIPTOP_TS0_GPIO_OEN_LSB1 (REG_COMPANION_TOP_BANK + 0x49UL)  // 0x24 [15:8]
#define REG_COMPANION_CHIPTOP_TS0_GPIO_OEN_MSB0 (REG_COMPANION_TOP_BANK + 0x4AUL)  // 0x25 [7:0]
#define REG_COMPANION_CHIPTOP_TS0_GPIO_OEN_MSB1 (REG_COMPANION_TOP_BANK + 0x4BUL)  // 0x25 [15:8]

#define REG_COMPANION_CHIPTOP_TS1_GPIO_OEN_LSB0 (REG_COMPANION_TOP_BANK + 0x54UL)  // 0x2a [7:0]
#define REG_COMPANION_CHIPTOP_TS1_GPIO_OEN_LSB1 (REG_COMPANION_TOP_BANK + 0x55UL)  // 0x2a [15:8]
#define REG_COMPANION_CHIPTOP_TS1_GPIO_OEN_MSB0 (REG_COMPANION_TOP_BANK + 0x56UL)  // 0x2b [7:0]
#define REG_COMPANION_CHIPTOP_TS1_GPIO_OEN_MSB1 (REG_COMPANION_TOP_BANK + 0x57UL)  // 0x2b [15:8]
	#define GPIO_OEN_MASK_L                     0xFFUL
	#define GPIO_OEN_MASK_H                     0x3FUL
	#define GPIO_OEN_EN                         0xFFUL
	#define GPIO_OEN_EN_00                      0x00UL

#define REG_PCM_GPIO_IN_30                      (REG_COMPANION_TOP_BANK + 0x60UL) //offset_30
	#define REG_PCM_GPIO_CARDDETECT_MASK        0x08
	#define REG_PCM_GPIO_CARD_IN                0x00
	#define REG_PCM_GPIO_CARD_OUT               0x08

#define REG_PCM_GPIO_OUT_33_L                   (REG_COMPANION_TOP_BANK + 0x66UL) //offset_33
#define REG_PCM_GPIO_OUT_33_H                   (REG_COMPANION_TOP_BANK + 0x67UL) //offset_33
#define REG_PCM_GPIO_OUT_34_L                   (REG_COMPANION_TOP_BANK + 0x68UL) //offset_34
#define REG_PCM_GPIO_OUT_34_H                   (REG_COMPANION_TOP_BANK + 0x69UL) //offset_34
#define REG_PCM_GPIO_OUT_35_L                   (REG_COMPANION_TOP_BANK + 0x6AUL) //offset_35
#define REG_PCM_GPIO_OUT_35_H                   (REG_COMPANION_TOP_BANK + 0x6BUL) //offset_35

#define REG_PCM_GPIO_OEN_36_L                   (REG_COMPANION_TOP_BANK + 0x6CUL) //offset_36
#define REG_PCM_GPIO_OEN_36_H                   (REG_COMPANION_TOP_BANK + 0x6DUL) //offset_36
#define REG_PCM_GPIO_OEN_37_L                   (REG_COMPANION_TOP_BANK + 0x6EUL) //offset_37
#define REG_PCM_GPIO_OEN_37_H                   (REG_COMPANION_TOP_BANK + 0x6FUL) //offset_37
#define REG_PCM_GPIO_OEN_38_L                   (REG_COMPANION_TOP_BANK + 0x70UL) //offset_38
#define REG_PCM_GPIO_OEN_38_H                   (REG_COMPANION_TOP_BANK + 0x71UL) //offset_38

#define REG_CHIPTOP_CILINK_RX_PAD_DRV_LOW	(REG_COMPANION_TOP_BANK + 0x82UL)
#define REG_CHIPTOP_CILINK_RX_PAD_DRV_LOW_MASK		0xFF
#define REG_CHIPTOP_CILINK_RX_PAD_DRV_HIGH	(REG_COMPANION_TOP_BANK + 0x83UL)
#define REG_CHIPTOP_CILINK_RX_PAD_DRV_HIGH_MASK		0xFF
#define REG_CHIPTOP_TS0_TX_DRV	(REG_COMPANION_TOP_BANK + 0x8CUL)
#define REG_CHIPTOP_TS0_TX_DRV_MASK			0xFFUL
#define REG_CHIPTOP_TS0_RX_DRV	(REG_COMPANION_TOP_BANK + 0x8DUL)
#define REG_CHIPTOP_TS0_RX_DRV_MASK			0xFFUL
#define REG_CHIPTOP_TS1_TX_DRV	(REG_COMPANION_TOP_BANK + 0x8EUL)
#define REG_CHIPTOP_TS1_TX_DRV_MASK			0xFFUL
#define REG_CHIPTOP_TS1_RX_DRV	(REG_COMPANION_TOP_BANK + 0x8FUL)
#define REG_CHIPTOP_TS1_RX_DRV_MASK			0xFFUL

#define REG_COMPANION_CHIPTOP_TS0_TX_PE_LSB     (REG_COMPANION_TOP_BANK + 0x90UL)  // 0x48 [7:0]
#define REG_COMPANION_CHIPTOP_TS0_TX_PE_MSB     (REG_COMPANION_TOP_BANK + 0x91UL)  // 0x48 [15:8]
#define REG_COMPANION_CHIPTOP_TS0_RX_PE_LSB     (REG_COMPANION_TOP_BANK + 0x92UL)  // 0x49 [7:0]
#define REG_COMPANION_CHIPTOP_TS0_RX_PE_MSB     (REG_COMPANION_TOP_BANK + 0x93UL)  // 0x49 [15:8]

#define REG_COMPANION_CHIPTOP_TS1_TX_PE_LSB     (REG_COMPANION_TOP_BANK + 0x94UL)  // 0x4a [7:0]
#define REG_COMPANION_CHIPTOP_TS1_TX_PE_MSB     (REG_COMPANION_TOP_BANK + 0x95UL)  // 0x4a [15:8]
#define REG_COMPANION_CHIPTOP_TS1_RX_PE_LSB     (REG_COMPANION_TOP_BANK + 0x96UL)  // 0x4b [7:0]
#define REG_COMPANION_CHIPTOP_TS1_RX_PE_MSB     (REG_COMPANION_TOP_BANK + 0x97UL)  // 0x4b [15:8]
	#define PE_MASK                             0xFFUL
	#define PE_EN                               0xFFUL
	#define PE_EN_00                            0x00UL

#define REG_COMPANION_CHIPTOP_TS0_TX_PS_LSB     (REG_COMPANION_TOP_BANK + 0x98UL)  // 0x4c [7:0]
#define REG_COMPANION_CHIPTOP_TS0_TX_PS_MSB     (REG_COMPANION_TOP_BANK + 0x99UL)  // 0x4c [15:8]
#define REG_COMPANION_CHIPTOP_TS0_RX_PS_LSB     (REG_COMPANION_TOP_BANK + 0x9AUL)  // 0x4d [7:0]
#define REG_COMPANION_CHIPTOP_TS0_RX_PS_MSB     (REG_COMPANION_TOP_BANK + 0x9BUL)  // 0x4d [15:8]

#define REG_COMPANION_CHIPTOP_TS1_TX_PS_LSB     (REG_COMPANION_TOP_BANK + 0x9CUL)  // 0x4e [7:0]
#define REG_COMPANION_CHIPTOP_TS1_TX_PS_MSB     (REG_COMPANION_TOP_BANK + 0x9DUL)  // 0x4e [15:8]
#define REG_COMPANION_CHIPTOP_TS1_RX_PS_LSB     (REG_COMPANION_TOP_BANK + 0x9EUL)  // 0x4f [7:0]
#define REG_COMPANION_CHIPTOP_TS1_RX_PS_MSB     (REG_COMPANION_TOP_BANK + 0x9FUL)  // 0x4f [15:8]
	#define PS_MASK                             0xFFUL
	#define PS_EN                               0xFFUL
	#define PS_EN_00                            0x00UL
#define REG_CHIPTOP_ALLPAD_IN	(REG_COMPANION_TOP_BANK + 0xA1UL)
#define ALL_PAD_IN_MASK						0x80UL
#define ALL_PAD_IN_DISABLE					0x00UL

#define REG_CHIPTOP_CILINK_EN	(REG_COMPANION_TOP_BANK + 0xA2UL)
#define REG_COMPANION_CHIPTOP_CILINK_EN		(REG_COMPANION_TOP_BANK + 0xA2UL)  // 0x51 [7:0]
#define CILINK0_RX_EN			0x01UL
#define CILINK0_TX_EN			0x02UL
#define CILINK1_RX_EN			0x04UL
#define CILINK1_TX_EN			0x08UL
#define TS0_RX_EN				0x10UL
#define TS0_TX_EN				0x20UL
#define TS1_RX_EN				0x40UL
#define TS1_TX_EN				0x80UL
#define CILINK_TS_RXTX_MASK		0xFFUL
#define CILINK_TS_RXTX_EN		0xFFUL
#define TS0_RXTX_MASK			0x30UL
#define TS1_RXTX_MASK			0xC0UL
#define RXTX_DISABLE			0x00UL

#define REG_CHIPTOP_PCM_EN		(REG_COMPANION_TOP_BANK + 0xA3UL)
#define PCM_ENABLE_MASK						0x03UL
#define PCM_ENABLE							0x03UL
#define REG_CHIPTOP_PCM_PE		(REG_COMPANION_TOP_BANK + 0x81UL)
#define PE_ENABLE							0xFFUL

#define REG_PCM1_PWR_OEN		(REG_COMPANION_TOP_BANK + 0x76UL)
#define PCM1_PWR_OEN_MASK					0x01UL
#define PCM1_PWR_OUT						0x00UL
#define REG_PCM1_PWR_OUT		(REG_COMPANION_TOP_BANK + 0x74UL)
#define PCM1_PWR_OUT_MASK					0x01UL
#define PCM1_PWR_OUT_HIGH					0x01UL
#define PCM1_PWR_OUT_LOW					0x00UL
//reg_sspi_drv[7:6]
#define REG_CHIPTOP_SSPI_DRV	(REG_COMPANION_TOP_BANK + 0x7AUL)
#define PAD_SSPI_DO_MASK					0xC0UL
#define PAD_SSPI_DO_0						0x00UL
#define PAD_SSPI_DO_1						0x40UL
#define PAD_SSPI_DO_2						0x80UL
#define PAD_SSPI_DO_3						0xC0UL

#define REG_DEVICE_ID			(REG_COMPANION_TOP_BANK + 0xCCUL)
#define REG_TEST_ADDRESS_1		(REG_COMPANION_TOP_BANK + 0xF2UL)
#define REG_TEST_ADDRESS_2		(REG_COMPANION_TOP_BANK + 0xF3UL)




#define REG_COMPANION_ANA_MISC_BANK		  0x110C00
#define REG_MPLL_CLK_PD			(REG_COMPANION_ANA_MISC_BANK + 0x03UL)
#define MPLL_PD_DISABLE_MASK				0x07UL
#define MPLL_PD_DISABLE_DISABLE				0x00UL
#define REG_MPLL_CLK_PD_CTRL	(REG_COMPANION_ANA_MISC_BANK + 0x0AUL)
#define REG_MPLL_CLK_PD_CTRL1	(REG_COMPANION_ANA_MISC_BANK + 0x0BUL)
#define REG_MPLL_CLK_PD_CTRL2	(REG_COMPANION_ANA_MISC_BANK + 0x0CUL)
#define REG_MPLL_CLK_PD_CTRL3	(REG_COMPANION_ANA_MISC_BANK + 0x0DUL)
#define MPLL_PD_CTRL_DISABLE_MASK			0xFFUL
#define MPLL_PD_CTRL_DISABLE				0x00UL



#define REG_COMPANION_CLKGEN0_BANK	 0x100B00
#define REG_CLKGEN0_SW_MCU_CLK		(REG_COMPANION_CLKGEN0_BANK + 0x20UL)
#define SELECT_TO_CKG_MCU					0x01UL
#define REG_CLKGEN0_CKG_MCU			(REG_COMPANION_CLKGEN0_BANK + 0x21UL)
#define CKG_MCU_216M						0x00UL
#define REG_CLKGEN0_CKG_SSPI		(REG_COMPANION_CLKGEN0_BANK + 0x2bUL)
#define CKG_SSPI_108M						0x20UL
#define REG_CLKGEN0_PCM				(REG_COMPANION_CLKGEN0_BANK + 0x34UL)
#define CLK_ON								0x00UL
#define CLK_OFF								0x01UL
#define REG_CLKGEN0_CILINK			(REG_COMPANION_CLKGEN0_BANK + 0xE2UL)
#define CILINK_TRACING_MASK					0x0FUL
#define CILINK_TRACING_DISABLE				0x01UL
#define CILINK_TRACING_216M					0x00UL
#define CILINK_IF_MASK						0xF0UL
#define CILINK_IF_DISABLE					0x10UL
#define CILINK_IF_36M						0x00UL
#define REG_CLKGEN0_2B				(REG_COMPANION_CLKGEN0_BANK + 0xE3UL)
#define CKG_2B_TX_MASK						0x0FUL
#define CKG_2B_TX_DISABLE					0x01UL
#define CKG_2B_TX_CLKINV					0x02UL
#define CKG_2B_TX_FROM_MAIN					0x00UL
#define CKG_2B_RX_INIT_MASK					0xF0UL
#define CKG_2B_RX_INIT_DISABLE				0x10UL
#define CKG_2B_RX_INIT_FROM_ATOP			0x00UL
#define REG_CLKGEN0_CILINK_SYN		(REG_COMPANION_CLKGEN0_BANK + 0xE4UL)
#define CILINK_SYN_2B_MASK					0x0FUL
#define CILINK_SYN_2B_DISABLE				0x01UL
#define CILINK_SYN_2B_216M					0x00UL
#define CILINK_SYN_S_MASK					0xF0UL
#define CILINK_SYN_S_DISABLE				0x10UL
#define CILINK_SYN_S_216M					0x00UL
#define REG_CLKGEN0_FROMCARD		(REG_COMPANION_CLKGEN0_BANK + 0xE5UL)
#define CKG_FROMCARD_C1_MASK				0x0FUL
#define CKG_FROMCARD_C1_TS_SAMPLE_TOP		0x00UL
#define CKG_FROMCARD_C1_INTERNAL_LOOP		0x04UL
#define CKG_FROMCARD_C2_MASK				0xF0UL
#define CKG_FROMCARD_C2_TS_SAMPLE_TOP		0x00UL
#define CKG_FROMCARD_C2_INTERNAL_LOOP		0x40UL
#define REG_CLKGEN0_TS_SAMPLE		(REG_COMPANION_CLKGEN0_BANK + 0xE6UL)
#define CKG_TS_SAMPLE_MASK					0x0FUL
#define CKG_TS_SAMPLE_216M					0x00UL
#define CKG_TS_SAMPLE_432M					0x04UL
#define REG_CLKGEN0_TOCARD_C1_EXT	(REG_COMPANION_CLKGEN0_BANK + 0xE8UL)
#define CKG_TOCARD_C1_DIVIN_MASK			0x1FUL
#define CKG_TOCARD_C1_DIVIN_72M				0x18UL
#define CKG_TOCARD_C1_EXT_MASK				0x60UL
#define CKG_TOCARD_C1_EXT_DISABLE			0x20UL
#define CKG_TOCARD_C1_EXT_ENABLE			0x00UL
#define CKG_TOCARD_C1_EXT_INVERT			0x40UL
#define REG_CLKGEN0_TOCARD_C2_EXT	(REG_COMPANION_CLKGEN0_BANK + 0xE9UL)
#define CKG_TOCARD_C2_EXT_MASK				0x60UL
#define CKG_TOCARD_C2_EXT_DISABLE			0x20UL
#define CKG_TOCARD_C2_EXT_ENABLE			0x00UL
#define CKG_TOCARD_C2_EXT_ENABLE			0x00UL
#define REG_CLKGEN0_TOCARD_C1		(REG_COMPANION_CLKGEN0_BANK + 0xEAUL)
#define CKG_TOCARD_C1_MASK					0x1FUL
#define CKG_TS_TX_C1_DISABLE				0x01UL
#define CKG_TS_TX_C1_CLKINV					0x02UL
#define CKG_TS_TX_C1_FROM_SOC				0x00UL
#define CKG_TS_TX_C1_DIV_OUT				0x08UL
#define REG_CLKGEN0_TOCARD_C2		(REG_COMPANION_CLKGEN0_BANK + 0xEBUL)
#define CKG_TOCARD_C2_MASK					0x1FUL
#define CKG_TS_TX_C2_CLKINV					0x02UL
#define CKG_TS_TX_C2_DISABLE				0x01UL
#define CKG_TS_TX_C2_FROM_SOC				0x00UL
#define CKG_2B_RX_EXT_MASK					0x60UL
#define CKG_2B_RX_EXT_DISABLE				0x20UL
#define CKG_2B_RX_EXT_CLKINV				0x40UL
#define CKG_2B_RX_EXT_ENABLE				0x00UL

#define REG_COMPANION_CILINK_TS_SAMPLE_BANK	0x110900
#define REG_COMPANION_SAMPLE_FROMCARD_C1        (REG_COMPANION_CILINK_TS_SAMPLE_BANK + 0x02UL)    // 0x01
#define REG_COMPANION_SAMPLE_FROMCARD_C1_MASK   0xFFUL
#define REG_CILINK_C1_DIV_N_L		(REG_COMPANION_CILINK_TS_SAMPLE_BANK + 0x84UL)
#define REG_CILINK_C1_DIV_N_L_MASK			0xFFUL
#define REG_CILINK_C1_DIV_N_H		(REG_COMPANION_CILINK_TS_SAMPLE_BANK + 0x85UL)
#define REG_CILINK_C1_DIV_N_H_MASK			0x0FUL
#define REG_CILINK_C1_DIV_LOAD_MASK			0x80UL
#define REG_CILINK_C1_DIV_LOAD				0x80UL
#define REG_CILINK_C1_DIV_M			(REG_COMPANION_CILINK_TS_SAMPLE_BANK + 0x86UL)
#define REG_CILINK_C1_DIV_M_MASK			0xFFUL

#define REG_COMPANION_CILINK_CMP_IF_BANK	0x110A00
#define REG_CILINK_CMP_IF_06		(REG_COMPANION_CILINK_CMP_IF_BANK + 0x0CUL)
#define INTERLOOP_RX_2B						0x10
#define INTERLOOP_RX_2B_MASK				0x10
#define REG_FIX_TO_CARD_SYNC		(REG_COMPANION_CILINK_CMP_IF_BANK + 0x2FUL)
#define FIX_TO_CARD_SYNC					0x10
#define REG_FIX_TO_CARD_SYNC_MASK			0xFFUL


#define REG_COMPANION_ATOP1_BANK   0x110B00
#define REG_ATOP_CIPLL_PD			(REG_COMPANION_ATOP1_BANK + 0xC3UL)
#define CIPLL_PD_POWERDOWN					0x01
#define CIPLL_PD_POWERUP					0x00
#define CIPLL_PD_MASK						0x01
#define REG_ATOP_CIPLL_DIV			(REG_COMPANION_ATOP1_BANK + 0xC7UL)
#define CIPLL_OUTPUT_DIV_MASK				0x0F
#define CIPLL_OUTPUT_DIV_72M				0x02
#define CIPLL_OUTPUT_DIV_18M				0x04
#define REG_ATOP_CISYN_SLD			(REG_COMPANION_ATOP1_BANK + 0xE8UL)
#define CISYN_SLD							0x01
#define CISYN_SLD_MASK						0x01
#define REG_ATOP_CIPLL_PD_KP1		(REG_COMPANION_ATOP1_BANK + 0xF0UL)
#define CIPLL_PD_KP1_MASK					0x04
#define CIPLL_PD_KP1_POWERUP				0x00
#define CIPLL_PD_KP1_POWERDOWN				0x04
#define REG_ATOP_CISYN_PD			(REG_COMPANION_ATOP1_BANK + 0xF4UL)
#define CISYN_PD_RST						0x01
#define CISYN_PD_RST_DISABLE				0x00



#define REG_COMPANION_INTR_CTRL_BANK 0x101900
#define REG_COMPANION_PCM_BANK		 0x103500
#define REG_COMPANION_PCM2_BANK		 0x103600
#define REG_COMPANION_PCMBURST_BANK	 0x103700

#define REG_COMPANION_PCMBURST_ADDR	 0x800002F4	// bank 1037, addr 0x7A)
#define REG_COMPANION_PCMBURST_SIZE    0x800002FC       //size
#define REG_COMPANION_PCMBURST_TRIGGER 0x800002FE       //trigger
#define REG_COMPANION_PCMBURST_WFIFO 0x80000300
#define REG_COMPANION_PCMBURST_RFIFO 0x80000A00

#define MSPI_CMD_RIU_W          0x1A
#define MSPI_CMD_RIU_W1			0x1D
// W : | RIU_W (1byte)	 | ADDR (2byte) | data ...
#define MSPI_CMD_RIU_RIT1		0x15
// W : | RIU_RT1 (1byte) | ADDR (2byte) | TA (turn around, 1byte) |
#define MSPI_CMD_MIU_W			0x25
// W : | MIU_W (1byte)	 | ADDR (4byte) | data ...
#define MSPI_CMD_MIU_R			0x20
// W : | MIU_R (1byte)	 | ADDR (4byte) | len = 0 (1byte)
#define MSPI_CMD_MIU_ST			0x21
// W : | MIU_ST (1byte)	 | 0 (1byte)
#define MSPI_CMD_CFG_W			0x05

#define MSPI_MIU_STATUS_NONE	0x00	// Initial status
#define MSPI_MIU_STATUS_WBUSY	0x01	// FIFO is not empty or MIU IF is busy
#define MSPI_MIU_STATUS_RBUSY	0x02	// FIFO is not empty or MIU IF is busy
#define MSPI_MIU_STATUS_OV		0x03	// FIFO overflow
#define MSPI_MIU_STATUS_COL		0x04	// SSPI and MIU interface collision
#define MSPI_MIU_STATUS_DONE	0x0A	// RIU_W or RIU_R done



#define MAX_MSPI_BURST_WRITE_SIZE			128
#define MAX_MSPI_BURST_READ_SIZE			32
#define MAX_PCMCIA_BURST_WRITE_SIZE			128
#define MAX_PCMCIA_BURST_READ_SIZE			128

#define MAX_MSPI_STATUS_COUNT				0x1024

#define REG_PCMCIA_BASE						0x3500UL
#define REG_CLKGEN0_BASE					0x0B00UL

#define REG_PCMCIA_PCM_MEM_IO_CMD		   (REG_COMPANION_PCM_BANK + 0x00UL)
#define REG_PCMCIA_ADDR0				   (REG_COMPANION_PCM_BANK + 0x02UL)
#define REG_PCMCIA_ADDR1				   (REG_COMPANION_PCM_BANK + 0x03UL)
#define REG_PCMCIA_WRITE_DATA			   (REG_COMPANION_PCM_BANK + 0x04UL)
#define REG_PCMCIA_FIRE_READ_DATA_CLEAR	   (REG_COMPANION_PCM_BANK + 0x06UL)
#define REG_PCMCIA_READ_DATA			   (REG_COMPANION_PCM_BANK + 0x08UL)
#define REG_PCMCIA_READ_DATA_DONE_BUS_IDLE (REG_COMPANION_PCM_BANK + 0x09UL)
#define REG_PCMCIA_INT_MASK_CLEAR		   (REG_COMPANION_PCM_BANK + 0x0AUL)
#define REG_PCMCIA_INT_MASK_CLEAR1		   (REG_COMPANION_PCM_BANK + 0x0BUL)
#define REG_PCMCIA_STAT_INT_RAW_INT		   (REG_COMPANION_PCM_BANK + 0x0EUL)
#define REG_PCMCIA_STAT_INT_RAW_INT1	   (REG_COMPANION_PCM_BANK + 0x0FUL)
#define REG_PCMCIA_MODULE_VCC_OOB		   (REG_COMPANION_PCM_BANK + 0x10UL)
#define REG_PCMCIA_CONFIG				   (REG_COMPANION_PCM_BANK + 0x11UL)
#define PCM_CD1_OR_CD2					0x01UL

#define REG_PCM_BURST_CTRL (REG_COMPANION_PCMBURST_BANK + 0x00UL)
#define REG_PCM_BURST_SW_RST_ON			0x01UL
#define REG_PCM_BURST_SW_RST_OFF		0x00UL
#define REG_PCM_BURST_SW_RST_MASK		0x01UL

#define REG_PCM_BURST_STATUS_CLR (REG_COMPANION_PCMBURST_BANK + 0x8UL)
#define REG_PCM_WRITE_FINISH_CLR		0x01UL
#define REG_PCM_READ_FINISH_CLR			0x02UL
#define REG_PCM_STATUS_READ_FINISH_CLR	0x04UL

#define REG_PCM_BURST_STATUS_0 (REG_COMPANION_PCMBURST_BANK + 0x14UL)
#define REG_PCM_BURST_WRITE_DONE		0x01UL
#define REG_PCM_BURST_READ_DONE			0x02UL
#define REG_PCM_BURST_READ_STATUS_DONE	0x04UL

#define REG_PCM_BURST_STATUS_1 (REG_COMPANION_PCMBURST_BANK + 0x16UL)
#define REG_PCM_WFIFO_EMPTY				0x01UL
#define REG_PCM_WFIFO_FULL				0x02UL
#define REG_PCM_RFIFO_EMPTY				0x40UL
#define REG_PCM_RFIFO_FULL				0x80UL

#define REG_PCM_BURST_WFIFO_RMN (REG_COMPANION_PCMBURST_BANK + 0x18UL)	// [6:0] max 127
#define REG_PCM_BURST_RFIFO_RMN (REG_COMPANION_PCMBURST_BANK + 0x19UL)	// [6:0] max 127

#define REG_HST0_IRQ_MASK_15_0	(REG_COMPANION_INTR_CTRL_BANK + 0x29UL)
#define REG_PCM_IRQ_BIT_SHFT			2UL
#define REG_PCM_IRQ_BIT_MASK			(0x1UL << REG_PCM_IRQ_BIT_SHFT)
#define IRQ_MASK						(1UL << REG_PCM_IRQ_BIT_SHFT)
#define IRQ_UNMASK						(0UL << REG_PCM_IRQ_BIT_SHFT)

#define PCMCIA_ATTRIBMEMORY_READ			0x03UL
#define PCMCIA_ATTRIBMEMORY_WRITE			0x04UL
#define PCMCIA_IO_READ						0x05UL
#define PCMCIA_IO_WRITE						0x06UL

#define PCM_OOB_BIT_MASK					0x03UL
#define PCM_OOB_BIT_SHFT					6UL

#define PCM_OOB_CYCLE_EXTEND				0x3UL
						// 00:th(CE)=4T (extend 3 active cycle)
						// 01:th(CE)=3T (extend 2 active cycle)
						// 10:th(CE)=2T (extend 1 active cycle)
						// 11:th(CE)=1T

//-----------------------------------------------------------------------------
//	Type and Structure
//-----------------------------------------------------------------------------

#endif				// _REG_PCMCIA_H_
