/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page MERGE_PCMCIA
#define REG_0080_PCM (0x080)
    #define REG_PCM_CMD_0080 Fld(3, 0, AC_MSKB0)//[2:0]
    #define REG_MEM_CMD_0080 Fld(3, 3, AC_MSKB0)//[5:3]
    #define REG_IO_CMD_0080 Fld(3, 6, AC_MSKW10)//[8:6]
    #define REG_PCM1_CE_SW_CTRL_0080 Fld(1, 12, AC_MSKB1)//[12:12]
    #define REG_PCM2_CE_SW_CTRL_0080 Fld(1, 13, AC_MSKB1)//[13:13]
    #define REG_PCM1_RESET_OE_0080 Fld(1, 14, AC_MSKB1)//[14:14]
    #define REG_PCM2_RESET_OE_0080 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0084_PCM (0x084)
    #define REG_ADR_0084 Fld(15, 0, AC_MSKW10)//[14:0]
#define REG_0088_PCM (0x088)
    #define REG_WD_0088 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_008C_PCM (0x08C)
    #define REG_FIRE_008C Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_RD_CLR_008C Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0090_PCM (0x090)
    #define REG_STAT_RD_0090 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_STAT_RD_DONE_0090 Fld(1, 8, AC_MSKB1)//[8:8]
    #define REG_STAT_BUS_IDLE_0090 Fld(1, 9, AC_MSKB1)//[9:9]
    #define REG_PCM1_CD_0090 Fld(1, 10, AC_MSKB1)//[10:10]
    #define REG_PCM2_CD_0090 Fld(1, 11, AC_MSKB1)//[11:11]
    #define REG_STAT_WD_DONE_0090 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0094_PCM (0x094)
    #define REG_INT_MASK_0094 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_INT_CLR_0094 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0098_PCM (0x098)
    #define REG_INT_FORCE_0098 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_009C_PCM (0x09C)
    #define REG_STAT_INT_RAW_009C Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_STAT_INT_009C Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A0_PCM (0x0A0)
    #define REG_MODULE_SEL_00A0 Fld(2, 0, AC_MSKB0)//[1:0]
    #define REG_MODULE_RST_A_00A0 Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_MODULE_RST_B_00A0 Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_SINGLE_CARD_00A0 Fld(1, 4, AC_MSKB0)//[4:4]
    #define REG_VCC_EN_00A0 Fld(1, 5, AC_MSKB0)//[5:5]
    #define REG_OOB_EN_00A0 Fld(2, 6, AC_MSKB0)//[7:6]
    #define REG_PCM_OR_CD12_EN_00A0 Fld(1, 8, AC_MSKB1)//[8:8]
    #define REG_CHECK_TIME_OUT_00A0 Fld(1, 9, AC_MSKB1)//[9:9]
    #define REG_AUTO_CLR_EN_00A0 Fld(1, 10, AC_MSKB1)//[10:10]
    #define REG_SW_RST_00A0 Fld(1, 11, AC_MSKB1)//[11:11]
    #define REG_PCM_DUMMY_00A0 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00A4_PCM (0x0A4)
    #define REG_ADR_OE_00A4 Fld(15, 0, AC_MSKW10)//[14:0]
#define REG_00A8_PCM (0x0A8)
    #define REG_TAVWL_00A8 Fld(2, 0, AC_MSKB0)//[1:0]
    #define REG_TWLWTV_00A8 Fld(3, 2, AC_MSKB0)//[4:2]
    #define REG_TDVWH_00A8 Fld(4, 5, AC_MSKW10)//[8:5]
    #define REG_TWHGL_00A8 Fld(2, 9, AC_MSKB1)//[10:9]
#define REG_00AC_PCM (0x0AC)
    #define REG_TAVGL_00AC Fld(3, 0, AC_MSKB0)//[2:0]
    #define REG_TAVQV_00AC Fld(5, 3, AC_MSKB0)//[7:3]
    #define REG_TGHEH_00AC Fld(2, 8, AC_MSKB1)//[9:8]
#define REG_00B0_PCM (0x0B0)
    #define REG_TELIWL_00B0 Fld(2, 0, AC_MSKB0)//[1:0]
    #define REG_TDVIWL_00B0 Fld(5, 2, AC_MSKB0)//[6:2]
    #define REG_TIWHRGH_00B0 Fld(2, 7, AC_MSKW10)//[8:7]
#define REG_00B4_PCM (0x0B4)
    #define REG_TELIGL_00B4 Fld(2, 0, AC_MSKB0)//[1:0]
    #define REG_TIGLQV_00B4 Fld(5, 2, AC_MSKB0)//[6:2]
#define REG_00B8_PCM (0x0B8)
    #define REG_CHECK_CNT_00B8 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0000_PCM2 (0x000)
    #define REG_DBG_SEL_0000 Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0004_PCM2 (0x004)
    #define REG_PCM_DEBUG_0004 Fld(16, 0, AC_FULLW10)//[15:0]

