/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_CLK_MT5897_CKGEN00_H
#define _DT_BINDINGS_CLK_MT5897_CKGEN00_H

#define ckgen00(x)	x

#define REG_CKG_CALC ckgen00(0x0)
#define REG_CKG_CALC_S 0
#define REG_CKG_CALC_E 4
#define REG_CKG_CORECLK ckgen00(0x8)
#define REG_CKG_CORECLK_S 0
#define REG_CKG_CORECLK_E 2
#define REG_CKG_CORECLK_MID ckgen00(0x10)
#define REG_CKG_CORECLK_MID_S 0
#define REG_CKG_CORECLK_MID_E 2
#define REG_CKG_SCLK ckgen00(0x18)
#define REG_CKG_SCLK_S 0
#define REG_CKG_SCLK_E 2
#define REG_CKG_SCLK_MID ckgen00(0x20)
#define REG_CKG_SCLK_MID_S 0
#define REG_CKG_SCLK_MID_E 2
#define REG_CKG_BIU ckgen00(0x28)
#define REG_CKG_BIU_S 0
#define REG_CKG_BIU_E 2
#define REG_CKG_CALC_MCUSYS ckgen00(0x30)
#define REG_CKG_CALC_MCUSYS_S 0
#define REG_CKG_CALC_MCUSYS_E 4
#define REG_CKG_EMI0_MCUSYS ckgen00(0x38)
#define REG_CKG_EMI0_MCUSYS_S 0
#define REG_CKG_EMI0_MCUSYS_E 2
#define REG_CKG_EMI1_MCUSYS ckgen00(0x40)
#define REG_CKG_EMI1_MCUSYS_S 0
#define REG_CKG_EMI1_MCUSYS_E 2
#define REG_CKG_MIPS_SYN_ARMPLL ckgen00(0x50)
#define REG_CKG_MIPS_SYN_ARMPLL_S 0
#define REG_CKG_MIPS_SYN_ARMPLL_E 1
#define REG_CKG_MIPS_SYN_ARM2PLL ckgen00(0x54)
#define REG_CKG_MIPS_SYN_ARM2PLL_S 0
#define REG_CKG_MIPS_SYN_ARM2PLL_E 1
#define REG_CKG_XTAL_MPLL ckgen00(0x58)
#define REG_CKG_XTAL_MPLL_S 0
#define REG_CKG_XTAL_MPLL_E 2
#define REG_CKG_PTP ckgen00(0x60)
#define REG_CKG_PTP_S 0
#define REG_CKG_PTP_E 3
#define REG_CKG_LZMA_MCUSYS ckgen00(0x68)
#define REG_CKG_LZMA_MCUSYS_S 0
#define REG_CKG_LZMA_MCUSYS_E 2
#define REG_CKG_MPU_MCUSYS ckgen00(0x70)
#define REG_CKG_MPU_MCUSYS_S 0
#define REG_CKG_MPU_MCUSYS_E 2
#define REG_CKG_GPU_GPU_PAR_GP ckgen00(0xc8)
#define REG_CKG_GPU_GPU_PAR_GP_S 0
#define REG_CKG_GPU_GPU_PAR_GP_E 1
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP ckgen00(0xcc)
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_S 0
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_E 4
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD ckgen00(0xcc)
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD_S 12
#define REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD_E 12
#define REG_CKG_SHADER_CORE ckgen00(0xd0)
#define REG_CKG_SHADER_CORE_S 0
#define REG_CKG_SHADER_CORE_E 1
#define REG_CKG_MIPS_SYN_ARMPLL_GPU ckgen00(0xd8)
#define REG_CKG_MIPS_SYN_ARMPLL_GPU_S 0
#define REG_CKG_MIPS_SYN_ARMPLL_GPU_E 1
#define REG_CKG_AIA_BUS_AIA ckgen00(0xf0)
#define REG_CKG_AIA_BUS_AIA_S 8
#define REG_CKG_AIA_BUS_AIA_E 10
#define REG_CKG_MIPS_SYN_ARMPLL_APU ckgen00(0xf4)
#define REG_CKG_MIPS_SYN_ARMPLL_APU_S 0
#define REG_CKG_MIPS_SYN_ARMPLL_APU_E 1
#define REG_CKG_MDLA_AIA ckgen00(0x100)
#define REG_CKG_MDLA_AIA_S 8
#define REG_CKG_MDLA_AIA_E 10
#define REG_CKG_XTAL_24M_AIA ckgen00(0x108)
#define REG_CKG_XTAL_24M_AIA_S 0
#define REG_CKG_XTAL_24M_AIA_E 1
#define REG_CKG_EMI2_AIA ckgen00(0x110)
#define REG_CKG_EMI2_AIA_S 0
#define REG_CKG_EMI2_AIA_E 1
#define REG_CKG_DRAMC_CH0 ckgen00(0x120)
#define REG_CKG_DRAMC_CH0_S 0
#define REG_CKG_DRAMC_CH0_E 3
#define REG_CKG_DRAMC_CH2 ckgen00(0x128)
#define REG_CKG_DRAMC_CH2_S 0
#define REG_CKG_DRAMC_CH2_E 3
#define REG_CKG_DRAMC_CH4 ckgen00(0x130)
#define REG_CKG_DRAMC_CH4_S 0
#define REG_CKG_DRAMC_CH4_E 3
#define REG_CKG_DRAMC0_CGCLK_FAST_CHA ckgen00(0x138)
#define REG_CKG_DRAMC0_CGCLK_FAST_CHA_S 0
#define REG_CKG_DRAMC0_CGCLK_FAST_CHA_E 2
#define REG_CKG_DRAMC0_CGCLK_FAST_CHC ckgen00(0x13c)
#define REG_CKG_DRAMC0_CGCLK_FAST_CHC_S 0
#define REG_CKG_DRAMC0_CGCLK_FAST_CHC_E 2
#define REG_CKG_XTAL_24M_DRAMC0 ckgen00(0x140)
#define REG_CKG_XTAL_24M_DRAMC0_S 0
#define REG_CKG_XTAL_24M_DRAMC0_E 1
#define REG_CKG_EMI0_IP_WRAP ckgen00(0x168)
#define REG_CKG_EMI0_IP_WRAP_S 0
#define REG_CKG_EMI0_IP_WRAP_E 1
#define REG_CKG_EMI1_IP_WRAP ckgen00(0x170)
#define REG_CKG_EMI1_IP_WRAP_S 0
#define REG_CKG_EMI1_IP_WRAP_E 1
#define REG_CKG_EMI2_IP_WRAP ckgen00(0x178)
#define REG_CKG_EMI2_IP_WRAP_S 0
#define REG_CKG_EMI2_IP_WRAP_E 1
#define REG_CKG_IP_WRAP ckgen00(0x180)
#define REG_CKG_IP_WRAP_S 0
#define REG_CKG_IP_WRAP_E 1
#define REG_CKG_EMI0_DEB_IP_WRAP ckgen00(0x188)
#define REG_CKG_EMI0_DEB_IP_WRAP_S 0
#define REG_CKG_EMI0_DEB_IP_WRAP_E 1
#define REG_CKG_EMI1_DEB_IP_WRAP ckgen00(0x190)
#define REG_CKG_EMI1_DEB_IP_WRAP_S 0
#define REG_CKG_EMI1_DEB_IP_WRAP_E 1
#define REG_CKG_EMI2_DEB_IP_WRAP ckgen00(0x198)
#define REG_CKG_EMI2_DEB_IP_WRAP_S 0
#define REG_CKG_EMI2_DEB_IP_WRAP_E 1
#define REG_CKG_XTAL_12M_IP_WRAP ckgen00(0x1a0)
#define REG_CKG_XTAL_12M_IP_WRAP_S 0
#define REG_CKG_XTAL_12M_IP_WRAP_E 1
#define REG_CKG_XTAL_24M_IP_WRAP ckgen00(0x1a8)
#define REG_CKG_XTAL_24M_IP_WRAP_S 0
#define REG_CKG_XTAL_24M_IP_WRAP_E 1
#define REG_CKG_DRAMC0_PLL54M_108M ckgen00(0x1b0)
#define REG_CKG_DRAMC0_PLL54M_108M_S 0
#define REG_CKG_DRAMC0_PLL54M_108M_E 2
#define REG_CKG_SMI ckgen00(0x1d8)
#define REG_CKG_SMI_S 0
#define REG_CKG_SMI_E 2
#define REG_CKG_SMI_DEMOD0 ckgen00(0x1d8)
#define REG_CKG_SMI_DEMOD0_S 8
#define REG_CKG_SMI_DEMOD0_E 9
#define REG_CKG_SMI_SCACE ckgen00(0x1dc)
#define REG_CKG_SMI_SCACE_S 0
#define REG_CKG_SMI_SCACE_E 1
#define REG_CKG_SMI_SCIP ckgen00(0x1dc)
#define REG_CKG_SMI_SCIP_S 2
#define REG_CKG_SMI_SCIP_E 3
#define REG_CKG_SMI_SCMW ckgen00(0x1dc)
#define REG_CKG_SMI_SCMW_S 4
#define REG_CKG_SMI_SCMW_E 5
#define REG_CKG_SMI_SCNR ckgen00(0x1dc)
#define REG_CKG_SMI_SCNR_S 6
#define REG_CKG_SMI_SCNR_E 7
#define REG_CKG_SMI_SCPQ ckgen00(0x1dc)
#define REG_CKG_SMI_SCPQ_S 8
#define REG_CKG_SMI_SCPQ_E 9
#define REG_CKG_SMI_SCSCL ckgen00(0x1dc)
#define REG_CKG_SMI_SCSCL_S 10
#define REG_CKG_SMI_SCSCL_E 11
#define REG_CKG_SMI_SCSR ckgen00(0x1dc)
#define REG_CKG_SMI_SCSR_S 12
#define REG_CKG_SMI_SCSR_E 13
#define REG_CKG_SMI_SCTCON ckgen00(0x1dc)
#define REG_CKG_SMI_SCTCON_S 14
#define REG_CKG_SMI_SCTCON_E 15
#define REG_CKG_SMI_SCDV ckgen00(0x1e0)
#define REG_CKG_SMI_SCDV_S 0
#define REG_CKG_SMI_SCDV_E 1
#define REG_CKG_SMI_VDEC_SOC ckgen00(0x1e0)
#define REG_CKG_SMI_VDEC_SOC_S 2
#define REG_CKG_SMI_VDEC_SOC_E 3
#define REG_CKG_SMI_SCDISP ckgen00(0x1e0)
#define REG_CKG_SMI_SCDISP_S 4
#define REG_CKG_SMI_SCDISP_E 5
#define REG_CKG_SMI_VDEC_CORE0 ckgen00(0x1e0)
#define REG_CKG_SMI_VDEC_CORE0_S 6
#define REG_CKG_SMI_VDEC_CORE0_E 7
#define REG_CKG_SMI_AUDIO_R2 ckgen00(0x1e4)
#define REG_CKG_SMI_AUDIO_R2_S 0
#define REG_CKG_SMI_AUDIO_R2_E 1
#define REG_CKG_SMI_AIA ckgen00(0x1e4)
#define REG_CKG_SMI_AIA_S 6
#define REG_CKG_SMI_AIA_E 7
#define REG_CKG_VIVA_SMI ckgen00(0x1e8)
#define REG_CKG_VIVA_SMI_S 0
#define REG_CKG_VIVA_SMI_E 1
#define REG_CKG_SMI_MHEG5 ckgen00(0x1e8)
#define REG_CKG_SMI_MHEG5_S 4
#define REG_CKG_SMI_MHEG5_E 5
#define REG_CKG_SMI_HDMIRX ckgen00(0x1e8)
#define REG_CKG_SMI_HDMIRX_S 6
#define REG_CKG_SMI_HDMIRX_E 7
#define REG_CKG_SMI_TSP ckgen00(0x1e8)
#define REG_CKG_SMI_TSP_S 8
#define REG_CKG_SMI_TSP_E 9
#define REG_CKG_SMI_RV55FRC ckgen00(0x1e8)
#define REG_CKG_SMI_RV55FRC_S 10
#define REG_CKG_SMI_RV55FRC_E 11
#define REG_CKG_SMI_RV55PQU ckgen00(0x1e8)
#define REG_CKG_SMI_RV55PQU_S 12
#define REG_CKG_SMI_RV55PQU_E 13
#define REG_CKG_SMI_FRCCORE1 ckgen00(0x1ec)
#define REG_CKG_SMI_FRCCORE1_S 0
#define REG_CKG_SMI_FRCCORE1_E 1
#define REG_CKG_SMI_FRCCORE2 ckgen00(0x1ec)
#define REG_CKG_SMI_FRCCORE2_S 2
#define REG_CKG_SMI_FRCCORE2_E 3
#define REG_CKG_SMI_FRCCORE3 ckgen00(0x1ec)
#define REG_CKG_SMI_FRCCORE3_S 4
#define REG_CKG_SMI_FRCCORE3_E 5
#define REG_CKG_SMI_FRCMISC ckgen00(0x1ec)
#define REG_CKG_SMI_FRCMISC_S 6
#define REG_CKG_SMI_FRCMISC_E 7
#define REG_CKG_VIVA_SMI_BRG ckgen00(0x1f4)
#define REG_CKG_VIVA_SMI_BRG_S 0
#define REG_CKG_VIVA_SMI_BRG_E 1
#define REG_CKG_FRC_IMI ckgen00(0x260)
#define REG_CKG_FRC_IMI_S 0
#define REG_CKG_FRC_IMI_E 3
#define REG_CKG_IMI ckgen00(0x268)
#define REG_CKG_IMI_S 0
#define REG_CKG_IMI_E 3
#define REG_CKG_IMI_TSP ckgen00(0x268)
#define REG_CKG_IMI_TSP_S 8
#define REG_CKG_IMI_TSP_E 9
#define REG_CKG_LZMA ckgen00(0x270)
#define REG_CKG_LZMA_S 0
#define REG_CKG_LZMA_E 3
#define REG_CKG_XTAL_12M ckgen00(0x278)
#define REG_CKG_XTAL_12M_S 0
#define REG_CKG_XTAL_12M_E 1
#define REG_CKG_XTAL_12M_MHEG5 ckgen00(0x278)
#define REG_CKG_XTAL_12M_MHEG5_S 8
#define REG_CKG_XTAL_12M_MHEG5_E 9
#define REG_CKG_XTAL_12M_GPU_PAR_GP ckgen00(0x278)
#define REG_CKG_XTAL_12M_GPU_PAR_GP_S 10
#define REG_CKG_XTAL_12M_GPU_PAR_GP_E 11
#define REG_CKG_XTAL_24M ckgen00(0x280)
#define REG_CKG_XTAL_24M_S 0
#define REG_CKG_XTAL_24M_E 1
#define REG_CKG_XTAL_24M_MHEG5 ckgen00(0x280)
#define REG_CKG_XTAL_24M_MHEG5_S 8
#define REG_CKG_XTAL_24M_MHEG5_E 9
#define REG_CKG_XTAL_24M_GPU_PAR_GP ckgen00(0x280)
#define REG_CKG_XTAL_24M_GPU_PAR_GP_S 10
#define REG_CKG_XTAL_24M_GPU_PAR_GP_E 11
#define REG_CKG_XTAL_24M_GPU_SHADER ckgen00(0x280)
#define REG_CKG_XTAL_24M_GPU_SHADER_S 14
#define REG_CKG_XTAL_24M_GPU_SHADER_E 15
#define REG_CKG_XTAL_24M_TSP ckgen00(0x284)
#define REG_CKG_XTAL_24M_TSP_S 0
#define REG_CKG_XTAL_24M_TSP_E 1
#define REG_CKG_DEMOD_ADC ckgen00(0x2b8)
#define REG_CKG_DEMOD_ADC_S 0
#define REG_CKG_DEMOD_ADC_E 2
#define REG_CKG_XTAL_12M_DEMOD0 ckgen00(0x2c0)
#define REG_CKG_XTAL_12M_DEMOD0_S 0
#define REG_CKG_XTAL_12M_DEMOD0_E 1
#define REG_CKG_XTAL_24M_DEMOD0 ckgen00(0x2c8)
#define REG_CKG_XTAL_24M_DEMOD0_S 0
#define REG_CKG_XTAL_24M_DEMOD0_E 1
#define REG_CKG_ACIFIR ckgen00(0x2d0)
#define REG_CKG_ACIFIR_S 0
#define REG_CKG_ACIFIR_E 1
#define REG_CKG_ADCD ckgen00(0x2d8)
#define REG_CKG_ADCD_S 0
#define REG_CKG_ADCD_E 1
#define REG_CKG_ATSC200_PH1 ckgen00(0x2e0)
#define REG_CKG_ATSC200_PH1_S 0
#define REG_CKG_ATSC200_PH1_E 1
#define REG_CKG_ATSC200_PH3 ckgen00(0x2e8)
#define REG_CKG_ATSC200_PH3_S 0
#define REG_CKG_ATSC200_PH3_E 1
#define REG_CKG_ATSC25 ckgen00(0x2f0)
#define REG_CKG_ATSC25_S 0
#define REG_CKG_ATSC25_E 1
#define REG_CKG_ATSC400 ckgen00(0x2f8)
#define REG_CKG_ATSC400_S 0
#define REG_CKG_ATSC400_E 1
#define REG_CKG_ATSC50 ckgen00(0x300)
#define REG_CKG_ATSC50_S 0
#define REG_CKG_ATSC50_E 1
#define REG_CKG_ATSC_ADCD_SYNC ckgen00(0x308)
#define REG_CKG_ATSC_ADCD_SYNC_S 0
#define REG_CKG_ATSC_ADCD_SYNC_E 1
#define REG_CKG_ATSC_CE25 ckgen00(0x310)
#define REG_CKG_ATSC_CE25_S 0
#define REG_CKG_ATSC_CE25_E 1
#define REG_CKG_ATSC_EQ25 ckgen00(0x318)
#define REG_CKG_ATSC_EQ25_S 0
#define REG_CKG_ATSC_EQ25_E 1
#define REG_CKG_DMD_DMA ckgen00(0x320)
#define REG_CKG_DMD_DMA_S 0
#define REG_CKG_DMD_DMA_E 1
#define REG_CKG_DTMB_ADC ckgen00(0x328)
#define REG_CKG_DTMB_ADC_S 0
#define REG_CKG_DTMB_ADC_E 1
#define REG_CKG_DTMB_BCH_DEMOD0 ckgen00(0x330)
#define REG_CKG_DTMB_BCH_DEMOD0_S 0
#define REG_CKG_DTMB_BCH_DEMOD0_E 1
#define REG_CKG_DTMB_EQ0P25X ckgen00(0x338)
#define REG_CKG_DTMB_EQ0P25X_S 0
#define REG_CKG_DTMB_EQ0P25X_E 1
#define REG_CKG_DTMB_EQ0P5X ckgen00(0x340)
#define REG_CKG_DTMB_EQ0P5X_S 0
#define REG_CKG_DTMB_EQ0P5X_E 1
#define REG_CKG_DTMB_EQ1X ckgen00(0x348)
#define REG_CKG_DTMB_EQ1X_S 0
#define REG_CKG_DTMB_EQ1X_E 1
#define REG_CKG_DTMB_EQ2X ckgen00(0x350)
#define REG_CKG_DTMB_EQ2X_S 0
#define REG_CKG_DTMB_EQ2X_E 1
#define REG_CKG_DTMB_EQ2X_INNER12X ckgen00(0x358)
#define REG_CKG_DTMB_EQ2X_INNER12X_S 0
#define REG_CKG_DTMB_EQ2X_INNER12X_E 1
#define REG_CKG_DTMB_EQ2X_INNER2X_12X ckgen00(0x360)
#define REG_CKG_DTMB_EQ2X_INNER2X_12X_S 0
#define REG_CKG_DTMB_EQ2X_INNER2X_12X_E 1
#define REG_CKG_DTMB_EQ2X_INNER4X ckgen00(0x368)
#define REG_CKG_DTMB_EQ2X_INNER4X_S 0
#define REG_CKG_DTMB_EQ2X_INNER4X_E 1
#define REG_CKG_DTMB_INNER12X ckgen00(0x370)
#define REG_CKG_DTMB_INNER12X_S 0
#define REG_CKG_DTMB_INNER12X_E 1
#define REG_CKG_DTMB_INNER12X_EQ0P25X ckgen00(0x378)
#define REG_CKG_DTMB_INNER12X_EQ0P25X_S 0
#define REG_CKG_DTMB_INNER12X_EQ0P25X_E 1
#define REG_CKG_DTMB_INNER12X_INNER4X ckgen00(0x380)
#define REG_CKG_DTMB_INNER12X_INNER4X_S 0
#define REG_CKG_DTMB_INNER12X_INNER4X_E 1
#define REG_CKG_DTMB_INNER12X_INNER6X ckgen00(0x388)
#define REG_CKG_DTMB_INNER12X_INNER6X_S 0
#define REG_CKG_DTMB_INNER12X_INNER6X_E 1
#define REG_CKG_DTMB_INNER12X_INNER8X_TAP_COM ckgen00(0x390)
#define REG_CKG_DTMB_INNER12X_INNER8X_TAP_COM_S 0
#define REG_CKG_DTMB_INNER12X_INNER8X_TAP_COM_E 1
#define REG_CKG_DTMB_INNER1X ckgen00(0x398)
#define REG_CKG_DTMB_INNER1X_S 0
#define REG_CKG_DTMB_INNER1X_E 1
#define REG_CKG_DTMB_INNER1X_ATSC25 ckgen00(0x3a0)
#define REG_CKG_DTMB_INNER1X_ATSC25_S 0
#define REG_CKG_DTMB_INNER1X_ATSC25_E 1
#define REG_CKG_DTMB_INNER24X ckgen00(0x3a8)
#define REG_CKG_DTMB_INNER24X_S 0
#define REG_CKG_DTMB_INNER24X_E 1
#define REG_CKG_DTMB_INNER24X_ATSC_400 ckgen00(0x3b0)
#define REG_CKG_DTMB_INNER24X_ATSC_400_S 0
#define REG_CKG_DTMB_INNER24X_ATSC_400_E 1
#define REG_CKG_DTMB_INNER2X ckgen00(0x3b8)
#define REG_CKG_DTMB_INNER2X_S 0
#define REG_CKG_DTMB_INNER2X_E 1
#define REG_CKG_DTMB_INNER2X_4X_SR1X ckgen00(0x3c0)
#define REG_CKG_DTMB_INNER2X_4X_SR1X_S 0
#define REG_CKG_DTMB_INNER2X_4X_SR1X_E 1
#define REG_CKG_DTMB_INNER2X_SR0P5X ckgen00(0x3c8)
#define REG_CKG_DTMB_INNER2X_SR0P5X_S 0
#define REG_CKG_DTMB_INNER2X_SR0P5X_E 1
#define REG_CKG_DTMB_INNER4X ckgen00(0x3d0)
#define REG_CKG_DTMB_INNER4X_S 0
#define REG_CKG_DTMB_INNER4X_E 1
#define REG_CKG_DTMB_INNER4X_ATSC50 ckgen00(0x3d8)
#define REG_CKG_DTMB_INNER4X_ATSC50_S 0
#define REG_CKG_DTMB_INNER4X_ATSC50_E 1
#define REG_CKG_DTMB_INNER4X_SR1X ckgen00(0x3e0)
#define REG_CKG_DTMB_INNER4X_SR1X_S 0
#define REG_CKG_DTMB_INNER4X_SR1X_E 1
#define REG_CKG_DTMB_INNER6X ckgen00(0x3e8)
#define REG_CKG_DTMB_INNER6X_S 0
#define REG_CKG_DTMB_INNER6X_E 1
#define REG_CKG_DTMB_INNER8X ckgen00(0x3f0)
#define REG_CKG_DTMB_INNER8X_S 0
#define REG_CKG_DTMB_INNER8X_E 1
#define REG_CKG_DTMB_INNER8X_TAP_COM ckgen00(0x3f8)
#define REG_CKG_DTMB_INNER8X_TAP_COM_S 0
#define REG_CKG_DTMB_INNER8X_TAP_COM_E 1
#define REG_CKG_DTMB_LDPC ckgen00(0x400)
#define REG_CKG_DTMB_LDPC_S 0
#define REG_CKG_DTMB_LDPC_E 1
#define REG_CKG_DTMB_LDPC2X ckgen00(0x408)
#define REG_CKG_DTMB_LDPC2X_S 0
#define REG_CKG_DTMB_LDPC2X_E 1
#define REG_CKG_DTMB_OUTER1X ckgen00(0x410)
#define REG_CKG_DTMB_OUTER1X_S 0
#define REG_CKG_DTMB_OUTER1X_E 1
#define REG_CKG_DTMB_OUTER2X ckgen00(0x418)
#define REG_CKG_DTMB_OUTER2X_S 0
#define REG_CKG_DTMB_OUTER2X_E 1
#define REG_CKG_DTMB_OUTER8X ckgen00(0x420)
#define REG_CKG_DTMB_OUTER8X_S 0
#define REG_CKG_DTMB_OUTER8X_E 1
#define REG_CKG_DTMB_SRAM_DUMP ckgen00(0x428)
#define REG_CKG_DTMB_SRAM_DUMP_S 0
#define REG_CKG_DTMB_SRAM_DUMP_E 1
#define REG_CKG_DVBS2_BCH ckgen00(0x430)
#define REG_CKG_DVBS2_BCH_S 0
#define REG_CKG_DVBS2_BCH_E 1
#define REG_CKG_DVBS2_DISEQC ckgen00(0x438)
#define REG_CKG_DVBS2_DISEQC_S 0
#define REG_CKG_DVBS2_DISEQC_E 1
#define REG_CKG_DVBS2_INNER ckgen00(0x440)
#define REG_CKG_DVBS2_INNER_S 0
#define REG_CKG_DVBS2_INNER_E 1
#define REG_CKG_DVBS2_OPPRO ckgen00(0x448)
#define REG_CKG_DVBS2_OPPRO_S 0
#define REG_CKG_DVBS2_OPPRO_E 1
#define REG_CKG_DVBS_OUTER1X ckgen00(0x450)
#define REG_CKG_DVBS_OUTER1X_S 0
#define REG_CKG_DVBS_OUTER1X_E 1
#define REG_CKG_DVBS_OUTER2X ckgen00(0x458)
#define REG_CKG_DVBS_OUTER2X_S 0
#define REG_CKG_DVBS_OUTER2X_E 1
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X ckgen00(0x460)
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_S 0
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_E 1
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X ckgen00(0x468)
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X_S 0
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X_E 1
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_MIU ckgen00(0x470)
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_MIU_S 0
#define REG_CKG_DVBS_OUTER2X_DVBT_OUTER2X_MIU_E 1
#define REG_CKG_DVBT2_INNER1X ckgen00(0x478)
#define REG_CKG_DVBT2_INNER1X_S 0
#define REG_CKG_DVBT2_INNER1X_E 1
#define REG_CKG_DVBT2_INNER2X ckgen00(0x480)
#define REG_CKG_DVBT2_INNER2X_S 0
#define REG_CKG_DVBT2_INNER2X_E 1
#define REG_CKG_DVBT2_INNER2X_SRD0P5X ckgen00(0x488)
#define REG_CKG_DVBT2_INNER2X_SRD0P5X_S 0
#define REG_CKG_DVBT2_INNER2X_SRD0P5X_E 1
#define REG_CKG_DVBT2_INNER4X ckgen00(0x490)
#define REG_CKG_DVBT2_INNER4X_S 0
#define REG_CKG_DVBT2_INNER4X_E 1
#define REG_CKG_DVBT2_INNER4X_DVBTC_RS ckgen00(0x498)
#define REG_CKG_DVBT2_INNER4X_DVBTC_RS_S 0
#define REG_CKG_DVBT2_INNER4X_DVBTC_RS_E 1
#define REG_CKG_DVBT2_INNER4X_S2_INNER ckgen00(0x4a0)
#define REG_CKG_DVBT2_INNER4X_S2_INNER_S 0
#define REG_CKG_DVBT2_INNER4X_S2_INNER_E 1
#define REG_CKG_DVBT_INNER1X ckgen00(0x4a8)
#define REG_CKG_DVBT_INNER1X_S 0
#define REG_CKG_DVBT_INNER1X_E 1
#define REG_CKG_DVBT_INNER2X ckgen00(0x4b0)
#define REG_CKG_DVBT_INNER2X_S 0
#define REG_CKG_DVBT_INNER2X_E 1
#define REG_CKG_DVBT_INNER2X_SRD0P5X ckgen00(0x4b8)
#define REG_CKG_DVBT_INNER2X_SRD0P5X_S 0
#define REG_CKG_DVBT_INNER2X_SRD0P5X_E 1
#define REG_CKG_DVBT_INNER4X ckgen00(0x4c0)
#define REG_CKG_DVBT_INNER4X_S 0
#define REG_CKG_DVBT_INNER4X_E 1
#define REG_CKG_DVBT_OUTER1X_DEMOD0 ckgen00(0x4c8)
#define REG_CKG_DVBT_OUTER1X_DEMOD0_S 0
#define REG_CKG_DVBT_OUTER1X_DEMOD0_E 1
#define REG_CKG_DVBT_OUTER2X ckgen00(0x4d0)
#define REG_CKG_DVBT_OUTER2X_S 0
#define REG_CKG_DVBT_OUTER2X_E 1
#define REG_CKG_DVBTC_ADC ckgen00(0x4d8)
#define REG_CKG_DVBTC_ADC_S 0
#define REG_CKG_DVBTC_ADC_E 1
#define REG_CKG_DVBTC_OUTER2X ckgen00(0x4e0)
#define REG_CKG_DVBTC_OUTER2X_S 0
#define REG_CKG_DVBTC_OUTER2X_E 1
#define REG_CKG_DVBTC_OUTER2X_ISDBT_OUTER_RS ckgen00(0x4e8)
#define REG_CKG_DVBTC_OUTER2X_ISDBT_OUTER_RS_S 0
#define REG_CKG_DVBTC_OUTER2X_ISDBT_OUTER_RS_E 1
#define REG_CKG_DVBTC_RS ckgen00(0x4f0)
#define REG_CKG_DVBTC_RS_S 0
#define REG_CKG_DVBTC_RS_E 1
#define REG_CKG_DVBTC_SRAM1 ckgen00(0x4f8)
#define REG_CKG_DVBTC_SRAM1_S 0
#define REG_CKG_DVBTC_SRAM1_E 1
#define REG_CKG_DVBTC_SRAM3 ckgen00(0x500)
#define REG_CKG_DVBTC_SRAM3_S 0
#define REG_CKG_DVBTC_SRAM3_E 1
#define REG_CKG_DVBTC_SRAM4 ckgen00(0x508)
#define REG_CKG_DVBTC_SRAM4_S 0
#define REG_CKG_DVBTC_SRAM4_E 1
#define REG_CKG_DVBTC_TS ckgen00(0x510)
#define REG_CKG_DVBTC_TS_S 0
#define REG_CKG_DVBTC_TS_E 1
#define REG_CKG_DVBTM_ADC0P5X_EQ0P5X ckgen00(0x518)
#define REG_CKG_DVBTM_ADC0P5X_EQ0P5X_S 0
#define REG_CKG_DVBTM_ADC0P5X_EQ0P5X_E 1
#define REG_CKG_DVBTM_ADC1X_EQ1X ckgen00(0x520)
#define REG_CKG_DVBTM_ADC1X_EQ1X_S 0
#define REG_CKG_DVBTM_ADC1X_EQ1X_E 1
#define REG_CKG_DVBTM_SRAM_ADC_T22X ckgen00(0x528)
#define REG_CKG_DVBTM_SRAM_ADC_T22X_S 0
#define REG_CKG_DVBTM_SRAM_ADC_T22X_E 1
#define REG_CKG_DVBTM_SRAM_ADC_T22X_DVBTC_RS ckgen00(0x530)
#define REG_CKG_DVBTM_SRAM_ADC_T22X_DVBTC_RS_S 0
#define REG_CKG_DVBTM_SRAM_ADC_T22X_DVBTC_RS_E 1
#define REG_CKG_DVBTM_SRAM_T11X_T22X ckgen00(0x538)
#define REG_CKG_DVBTM_SRAM_T11X_T22X_S 0
#define REG_CKG_DVBTM_SRAM_T11X_T22X_E 1
#define REG_CKG_DVBTM_SRAM_T11X_T24X ckgen00(0x540)
#define REG_CKG_DVBTM_SRAM_T11X_T24X_S 0
#define REG_CKG_DVBTM_SRAM_T11X_T24X_E 1
#define REG_CKG_DVBTM_SRAM_T12X_T22X ckgen00(0x548)
#define REG_CKG_DVBTM_SRAM_T12X_T22X_S 0
#define REG_CKG_DVBTM_SRAM_T12X_T22X_E 1
#define REG_CKG_DVBTM_SRAM_T12X_T24X ckgen00(0x550)
#define REG_CKG_DVBTM_SRAM_T12X_T24X_S 0
#define REG_CKG_DVBTM_SRAM_T12X_T24X_E 1
#define REG_CKG_DVBTM_SRAM_T12X_T24X_S2INNER ckgen00(0x558)
#define REG_CKG_DVBTM_SRAM_T12X_T24X_S2INNER_S 0
#define REG_CKG_DVBTM_SRAM_T12X_T24X_S2INNER_E 1
#define REG_CKG_DVBTM_SRAM_T12X_T24X_SRD1X ckgen00(0x560)
#define REG_CKG_DVBTM_SRAM_T12X_T24X_SRD1X_S 0
#define REG_CKG_DVBTM_SRAM_T12X_T24X_SRD1X_E 1
#define REG_CKG_DVBTM_SRAM_T14X_T24X ckgen00(0x568)
#define REG_CKG_DVBTM_SRAM_T14X_T24X_S 0
#define REG_CKG_DVBTM_SRAM_T14X_T24X_E 1
#define REG_CKG_DVBTM_SRAM_T14X_T24X_S2INNER ckgen00(0x570)
#define REG_CKG_DVBTM_SRAM_T14X_T24X_S2INNER_S 0
#define REG_CKG_DVBTM_SRAM_T14X_T24X_S2INNER_E 1
#define REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC ckgen00(0x578)
#define REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC_S 0
#define REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC_E 1
#define REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC ckgen00(0x580)
#define REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC_S 0
#define REG_CKG_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC_E 1
#define REG_CKG_DVBTM_SRAM_T1OUTER1X_T24X ckgen00(0x588)
#define REG_CKG_DVBTM_SRAM_T1OUTER1X_T24X_S 0
#define REG_CKG_DVBTM_SRAM_T1OUTER1X_T24X_E 1
#define REG_CKG_ISDBT_INNER1X ckgen00(0x590)
#define REG_CKG_ISDBT_INNER1X_S 0
#define REG_CKG_ISDBT_INNER1X_E 1
#define REG_CKG_ISDBT_INNER1X_DVBT_INNER1X ckgen00(0x598)
#define REG_CKG_ISDBT_INNER1X_DVBT_INNER1X_S 0
#define REG_CKG_ISDBT_INNER1X_DVBT_INNER1X_E 1
#define REG_CKG_ISDBT_INNER2X ckgen00(0x5a0)
#define REG_CKG_ISDBT_INNER2X_S 0
#define REG_CKG_ISDBT_INNER2X_E 1
#define REG_CKG_ISDBT_INNER2X_DVBT_INNER2X ckgen00(0x5a8)
#define REG_CKG_ISDBT_INNER2X_DVBT_INNER2X_S 0
#define REG_CKG_ISDBT_INNER2X_DVBT_INNER2X_E 1
#define REG_CKG_ISDBT_INNER4X ckgen00(0x5b0)
#define REG_CKG_ISDBT_INNER4X_S 0
#define REG_CKG_ISDBT_INNER4X_E 1
#define REG_CKG_ISDBT_INNER4X_DVBT_INNER4X ckgen00(0x5b8)
#define REG_CKG_ISDBT_INNER4X_DVBT_INNER4X_S 0
#define REG_CKG_ISDBT_INNER4X_DVBT_INNER4X_E 1
#define REG_CKG_ISDBT_INNER4X_DVBT_INNER4X_ADC ckgen00(0x5c0)
#define REG_CKG_ISDBT_INNER4X_DVBT_INNER4X_ADC_S 0
#define REG_CKG_ISDBT_INNER4X_DVBT_INNER4X_ADC_E 1
#define REG_CKG_ISDBT_OUTER12X ckgen00(0x5c8)
#define REG_CKG_ISDBT_OUTER12X_S 0
#define REG_CKG_ISDBT_OUTER12X_E 1
#define REG_CKG_ISDBT_OUTER1X ckgen00(0x5d0)
#define REG_CKG_ISDBT_OUTER1X_S 0
#define REG_CKG_ISDBT_OUTER1X_E 1
#define REG_CKG_ISDBT_OUTER1X_DVBT_OUTER1X ckgen00(0x5d8)
#define REG_CKG_ISDBT_OUTER1X_DVBT_OUTER1X_S 0
#define REG_CKG_ISDBT_OUTER1X_DVBT_OUTER1X_E 1
#define REG_CKG_ISDBT_OUTER4X ckgen00(0x5e0)
#define REG_CKG_ISDBT_OUTER4X_S 0
#define REG_CKG_ISDBT_OUTER4X_E 1
#define REG_CKG_ISDBT_OUTER6X ckgen00(0x5e8)
#define REG_CKG_ISDBT_OUTER6X_S 0
#define REG_CKG_ISDBT_OUTER6X_E 1
#define REG_CKG_ISDBT_OUTER6X_DVBT_INNER1X ckgen00(0x5f0)
#define REG_CKG_ISDBT_OUTER6X_DVBT_INNER1X_S 0
#define REG_CKG_ISDBT_OUTER6X_DVBT_INNER1X_E 1
#define REG_CKG_ISDBT_OUTER6X_DVBT_INNER2X ckgen00(0x5f8)
#define REG_CKG_ISDBT_OUTER6X_DVBT_INNER2X_S 0
#define REG_CKG_ISDBT_OUTER6X_DVBT_INNER2X_E 1
#define REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X ckgen00(0x600)
#define REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X_S 0
#define REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X_E 1
#define REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X_C ckgen00(0x608)
#define REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X_C_S 0
#define REG_CKG_ISDBT_OUTER6X_DVBT_OUTER2X_C_E 1
#define REG_CKG_ISDBT_OUTER_RS ckgen00(0x610)
#define REG_CKG_ISDBT_OUTER_RS_S 0
#define REG_CKG_ISDBT_OUTER_RS_E 1
#define REG_CKG_SRAM_SHARE_00_0 ckgen00(0x640)
#define REG_CKG_SRAM_SHARE_00_0_S 0
#define REG_CKG_SRAM_SHARE_00_0_E 1
#define REG_CKG_SRAM_SHARE_00_1 ckgen00(0x648)
#define REG_CKG_SRAM_SHARE_00_1_S 0
#define REG_CKG_SRAM_SHARE_00_1_E 1
#define REG_CKG_SRAM_SHARE_01_0 ckgen00(0x650)
#define REG_CKG_SRAM_SHARE_01_0_S 0
#define REG_CKG_SRAM_SHARE_01_0_E 1
#define REG_CKG_SRAM_SHARE_02_0 ckgen00(0x658)
#define REG_CKG_SRAM_SHARE_02_0_S 0
#define REG_CKG_SRAM_SHARE_02_0_E 1
#define REG_CKG_SRAM_SHARE_03_0 ckgen00(0x660)
#define REG_CKG_SRAM_SHARE_03_0_S 0
#define REG_CKG_SRAM_SHARE_03_0_E 1
#define REG_CKG_SRAM_SHARE_03_1 ckgen00(0x668)
#define REG_CKG_SRAM_SHARE_03_1_S 0
#define REG_CKG_SRAM_SHARE_03_1_E 1
#define REG_CKG_SRAM_SHARE_04_0 ckgen00(0x670)
#define REG_CKG_SRAM_SHARE_04_0_S 0
#define REG_CKG_SRAM_SHARE_04_0_E 1
#define REG_CKG_SRAM_SHARE_04_1 ckgen00(0x678)
#define REG_CKG_SRAM_SHARE_04_1_S 0
#define REG_CKG_SRAM_SHARE_04_1_E 1
#define REG_CKG_SRAM_SHARE_05 ckgen00(0x680)
#define REG_CKG_SRAM_SHARE_05_S 0
#define REG_CKG_SRAM_SHARE_05_E 1
#define REG_CKG_SRAM_SHARE_06 ckgen00(0x688)
#define REG_CKG_SRAM_SHARE_06_S 0
#define REG_CKG_SRAM_SHARE_06_E 1
#define REG_CKG_SRAM_SHARE_07 ckgen00(0x690)
#define REG_CKG_SRAM_SHARE_07_S 0
#define REG_CKG_SRAM_SHARE_07_E 1
#define REG_CKG_SRAM_SHARE_08 ckgen00(0x698)
#define REG_CKG_SRAM_SHARE_08_S 0
#define REG_CKG_SRAM_SHARE_08_E 1
#define REG_CKG_SRAM_SHARE_09 ckgen00(0x6a0)
#define REG_CKG_SRAM_SHARE_09_S 0
#define REG_CKG_SRAM_SHARE_09_E 1
#define REG_CKG_SRAM_SHARE_10 ckgen00(0x6a8)
#define REG_CKG_SRAM_SHARE_10_S 0
#define REG_CKG_SRAM_SHARE_10_E 1
#define REG_CKG_SRAM_SHARE_11 ckgen00(0x6b0)
#define REG_CKG_SRAM_SHARE_11_S 0
#define REG_CKG_SRAM_SHARE_11_E 1
#define REG_CKG_SRAM_SHARE_12 ckgen00(0x6b8)
#define REG_CKG_SRAM_SHARE_12_S 0
#define REG_CKG_SRAM_SHARE_12_E 1
#define REG_CKG_SRAM_SHARE_13 ckgen00(0x6c0)
#define REG_CKG_SRAM_SHARE_13_S 0
#define REG_CKG_SRAM_SHARE_13_E 1
#define REG_CKG_SRAM_SHARE_14_R ckgen00(0x6c8)
#define REG_CKG_SRAM_SHARE_14_R_S 0
#define REG_CKG_SRAM_SHARE_14_R_E 1
#define REG_CKG_SRAM_SHARE_14_W ckgen00(0x6d0)
#define REG_CKG_SRAM_SHARE_14_W_S 0
#define REG_CKG_SRAM_SHARE_14_W_E 1
#define REG_CKG_SRAM_SHARE_15_R ckgen00(0x6d8)
#define REG_CKG_SRAM_SHARE_15_R_S 0
#define REG_CKG_SRAM_SHARE_15_R_E 1
#define REG_CKG_SRAM_SHARE_15_W ckgen00(0x6e0)
#define REG_CKG_SRAM_SHARE_15_W_S 0
#define REG_CKG_SRAM_SHARE_15_W_E 1
#define REG_CKG_SRAM_SHARE_16 ckgen00(0x6e8)
#define REG_CKG_SRAM_SHARE_16_S 0
#define REG_CKG_SRAM_SHARE_16_E 1
#define REG_CKG_SRAM_SHARE_18 ckgen00(0x6f0)
#define REG_CKG_SRAM_SHARE_18_S 0
#define REG_CKG_SRAM_SHARE_18_E 1
#define REG_CKG_SRAM_SHARE_19 ckgen00(0x6f8)
#define REG_CKG_SRAM_SHARE_19_S 0
#define REG_CKG_SRAM_SHARE_19_E 1
#define REG_CKG_SRAM_SHARE_20 ckgen00(0x700)
#define REG_CKG_SRAM_SHARE_20_S 0
#define REG_CKG_SRAM_SHARE_20_E 1
#define REG_CKG_SRAM_SHARE_21 ckgen00(0x708)
#define REG_CKG_SRAM_SHARE_21_S 0
#define REG_CKG_SRAM_SHARE_21_E 1
#define REG_CKG_SRAM_SHARE_22 ckgen00(0x710)
#define REG_CKG_SRAM_SHARE_22_S 0
#define REG_CKG_SRAM_SHARE_22_E 1
#define REG_CKG_SRAM_SHARE_23 ckgen00(0x718)
#define REG_CKG_SRAM_SHARE_23_S 0
#define REG_CKG_SRAM_SHARE_23_E 1
#define REG_CKG_SRAM_SHARE_24 ckgen00(0x720)
#define REG_CKG_SRAM_SHARE_24_S 0
#define REG_CKG_SRAM_SHARE_24_E 1
#define REG_CKG_SRAM_SHARE_26 ckgen00(0x728)
#define REG_CKG_SRAM_SHARE_26_S 0
#define REG_CKG_SRAM_SHARE_26_E 1
#define REG_CKG_SRAM_SHARE_27 ckgen00(0x730)
#define REG_CKG_SRAM_SHARE_27_S 0
#define REG_CKG_SRAM_SHARE_27_E 1
#define REG_CKG_SRAM_SHARE_28 ckgen00(0x738)
#define REG_CKG_SRAM_SHARE_28_S 0
#define REG_CKG_SRAM_SHARE_28_E 1
#define REG_CKG_SRAM_SHARE_29 ckgen00(0x740)
#define REG_CKG_SRAM_SHARE_29_S 0
#define REG_CKG_SRAM_SHARE_29_E 1
#define REG_CKG_SRAM_SHARE_34 ckgen00(0x748)
#define REG_CKG_SRAM_SHARE_34_S 0
#define REG_CKG_SRAM_SHARE_34_E 1
#define REG_CKG_SRAM_SHARE_35 ckgen00(0x750)
#define REG_CKG_SRAM_SHARE_35_S 0
#define REG_CKG_SRAM_SHARE_35_E 2
#define REG_CKG_SRAM_SHARE_36 ckgen00(0x758)
#define REG_CKG_SRAM_SHARE_36_S 0
#define REG_CKG_SRAM_SHARE_36_E 2
#define REG_CKG_SRAM_SHARE_40 ckgen00(0x760)
#define REG_CKG_SRAM_SHARE_40_S 0
#define REG_CKG_SRAM_SHARE_40_E 2
#define REG_CKG_SRAM_SHARE_42 ckgen00(0x768)
#define REG_CKG_SRAM_SHARE_42_S 0
#define REG_CKG_SRAM_SHARE_42_E 1
#define REG_CKG_SRAM_SHARE_44 ckgen00(0x770)
#define REG_CKG_SRAM_SHARE_44_S 0
#define REG_CKG_SRAM_SHARE_44_E 1
#define REG_CKG_SRAM_SHARE_46 ckgen00(0x778)
#define REG_CKG_SRAM_SHARE_46_S 0
#define REG_CKG_SRAM_SHARE_46_E 1
#define REG_CKG_SRAM_SHARE_47 ckgen00(0x780)
#define REG_CKG_SRAM_SHARE_47_S 0
#define REG_CKG_SRAM_SHARE_47_E 2
#define REG_CKG_SRAM_SHARE_50_0 ckgen00(0x788)
#define REG_CKG_SRAM_SHARE_50_0_S 0
#define REG_CKG_SRAM_SHARE_50_0_E 1
#define REG_CKG_SRAM_SHARE_52_0 ckgen00(0x790)
#define REG_CKG_SRAM_SHARE_52_0_S 0
#define REG_CKG_SRAM_SHARE_52_0_E 1
#define REG_CKG_SRAM_SHARE_53_0 ckgen00(0x798)
#define REG_CKG_SRAM_SHARE_53_0_S 0
#define REG_CKG_SRAM_SHARE_53_0_E 1
#define REG_CKG_SRAM_SHARE_55_0 ckgen00(0x7a0)
#define REG_CKG_SRAM_SHARE_55_0_S 0
#define REG_CKG_SRAM_SHARE_55_0_E 1
#define REG_CKG_SRAM_SHARE_56 ckgen00(0x7a8)
#define REG_CKG_SRAM_SHARE_56_S 0
#define REG_CKG_SRAM_SHARE_56_E 1
#define REG_CKG_SRAM_SHARE_57 ckgen00(0x7b0)
#define REG_CKG_SRAM_SHARE_57_S 0
#define REG_CKG_SRAM_SHARE_57_E 1
#define REG_CKG_SRAM_SHARE_58 ckgen00(0x7b8)
#define REG_CKG_SRAM_SHARE_58_S 0
#define REG_CKG_SRAM_SHARE_58_E 1
#define REG_CKG_SRAM_SHARE_59 ckgen00(0x7c0)
#define REG_CKG_SRAM_SHARE_59_S 0
#define REG_CKG_SRAM_SHARE_59_E 1
#define REG_CKG_SRAM_SHARE_60 ckgen00(0x7c8)
#define REG_CKG_SRAM_SHARE_60_S 0
#define REG_CKG_SRAM_SHARE_60_E 1
#define REG_CKG_SRAM_SHARE_61 ckgen00(0x7d0)
#define REG_CKG_SRAM_SHARE_61_S 0
#define REG_CKG_SRAM_SHARE_61_E 1
#define REG_CKG_SRAM_SHARE_62 ckgen00(0x7d8)
#define REG_CKG_SRAM_SHARE_62_S 0
#define REG_CKG_SRAM_SHARE_62_E 1
#define REG_CKG_SRAM_SHARE_64 ckgen00(0x7e0)
#define REG_CKG_SRAM_SHARE_64_S 0
#define REG_CKG_SRAM_SHARE_64_E 1
#define REG_CKG_SRAM_SHARE_66 ckgen00(0x7e8)
#define REG_CKG_SRAM_SHARE_66_S 0
#define REG_CKG_SRAM_SHARE_66_E 1
#define REG_CKG_SRAM_SHARE_67 ckgen00(0x7f0)
#define REG_CKG_SRAM_SHARE_67_S 0
#define REG_CKG_SRAM_SHARE_67_E 1
#define REG_CKG_SRAM_SHARE_68_0 ckgen00(0x7f8)
#define REG_CKG_SRAM_SHARE_68_0_S 0
#define REG_CKG_SRAM_SHARE_68_0_E 2
#define REG_CKG_SRAM_SHARE_68_2 ckgen00(0x800)
#define REG_CKG_SRAM_SHARE_68_2_S 0
#define REG_CKG_SRAM_SHARE_68_2_E 1
#define REG_CKG_SRAM_SHARE_69_0 ckgen00(0x808)
#define REG_CKG_SRAM_SHARE_69_0_S 0
#define REG_CKG_SRAM_SHARE_69_0_E 1
#define REG_CKG_SRAM_SHARE_70 ckgen00(0x810)
#define REG_CKG_SRAM_SHARE_70_S 0
#define REG_CKG_SRAM_SHARE_70_E 2
#define REG_CKG_SRAM_SHARE_71 ckgen00(0x818)
#define REG_CKG_SRAM_SHARE_71_S 0
#define REG_CKG_SRAM_SHARE_71_E 1
#define REG_CKG_SRAM_SHARE_77 ckgen00(0x820)
#define REG_CKG_SRAM_SHARE_77_S 0
#define REG_CKG_SRAM_SHARE_77_E 1
#define REG_CKG_SRAM_SHARE_79 ckgen00(0x828)
#define REG_CKG_SRAM_SHARE_79_S 0
#define REG_CKG_SRAM_SHARE_79_E 1
#define REG_CKG_SRAM_SHARE_81 ckgen00(0x830)
#define REG_CKG_SRAM_SHARE_81_S 0
#define REG_CKG_SRAM_SHARE_81_E 1
#define REG_CKG_SRAM_SHARE_85 ckgen00(0x838)
#define REG_CKG_SRAM_SHARE_85_S 0
#define REG_CKG_SRAM_SHARE_85_E 1
#define REG_CKG_SRAM_SHARE_87 ckgen00(0x840)
#define REG_CKG_SRAM_SHARE_87_S 0
#define REG_CKG_SRAM_SHARE_87_E 1
#define REG_CKG_SRAM_SHARE_89 ckgen00(0x848)
#define REG_CKG_SRAM_SHARE_89_S 0
#define REG_CKG_SRAM_SHARE_89_E 1
#define REG_CKG_SRAM_SHARE_91 ckgen00(0x850)
#define REG_CKG_SRAM_SHARE_91_S 0
#define REG_CKG_SRAM_SHARE_91_E 1
#define REG_CKG_SRAM_SHARE_92 ckgen00(0x858)
#define REG_CKG_SRAM_SHARE_92_S 0
#define REG_CKG_SRAM_SHARE_92_E 1
#define REG_CKG_SRAM_SHARE_93 ckgen00(0x860)
#define REG_CKG_SRAM_SHARE_93_S 0
#define REG_CKG_SRAM_SHARE_93_E 1
#define REG_CKG_SRAM_SHARE_94 ckgen00(0x868)
#define REG_CKG_SRAM_SHARE_94_S 0
#define REG_CKG_SRAM_SHARE_94_E 1
#define REG_CKG_SRAM_SHARE_96 ckgen00(0x870)
#define REG_CKG_SRAM_SHARE_96_S 0
#define REG_CKG_SRAM_SHARE_96_E 1
#define REG_CKG_SRAM_SHARE_98 ckgen00(0x878)
#define REG_CKG_SRAM_SHARE_98_S 0
#define REG_CKG_SRAM_SHARE_98_E 1
#define REG_CKG_SRAM_SHARE_99 ckgen00(0x880)
#define REG_CKG_SRAM_SHARE_99_S 0
#define REG_CKG_SRAM_SHARE_99_E 1
#define REG_CKG_SRAM_SHARE_100 ckgen00(0x888)
#define REG_CKG_SRAM_SHARE_100_S 0
#define REG_CKG_SRAM_SHARE_100_E 1
#define REG_CKG_SRAM_SHARE_103 ckgen00(0x890)
#define REG_CKG_SRAM_SHARE_103_S 0
#define REG_CKG_SRAM_SHARE_103_E 1
#define REG_CKG_SRAM_SHARE_105 ckgen00(0x898)
#define REG_CKG_SRAM_SHARE_105_S 0
#define REG_CKG_SRAM_SHARE_105_E 1
#define REG_CKG_SRAM_SHARE_107 ckgen00(0x8a0)
#define REG_CKG_SRAM_SHARE_107_S 0
#define REG_CKG_SRAM_SHARE_107_E 1
#define REG_CKG_SRAM_SHARE_109 ckgen00(0x8a8)
#define REG_CKG_SRAM_SHARE_109_S 0
#define REG_CKG_SRAM_SHARE_109_E 1
#define REG_CKG_SRAM_SHARE_110 ckgen00(0x8b0)
#define REG_CKG_SRAM_SHARE_110_S 0
#define REG_CKG_SRAM_SHARE_110_E 1
#define REG_CKG_SRAM_SHARE_111 ckgen00(0x8b8)
#define REG_CKG_SRAM_SHARE_111_S 0
#define REG_CKG_SRAM_SHARE_111_E 1
#define REG_CKG_SRAM_SHARE_112 ckgen00(0x8c0)
#define REG_CKG_SRAM_SHARE_112_S 0
#define REG_CKG_SRAM_SHARE_112_E 1
#define REG_CKG_SRAM_SHARE_124 ckgen00(0x8c8)
#define REG_CKG_SRAM_SHARE_124_S 0
#define REG_CKG_SRAM_SHARE_124_E 1
#define REG_CKG_SRAM_SHARE_128 ckgen00(0x8d0)
#define REG_CKG_SRAM_SHARE_128_S 0
#define REG_CKG_SRAM_SHARE_128_E 1
#define REG_CKG_SRAM_SHARE_129 ckgen00(0x8d8)
#define REG_CKG_SRAM_SHARE_129_S 0
#define REG_CKG_SRAM_SHARE_129_E 1
#define REG_CKG_SRAM_SHARE_130 ckgen00(0x8e0)
#define REG_CKG_SRAM_SHARE_130_S 0
#define REG_CKG_SRAM_SHARE_130_E 1
#define REG_CKG_SRAM_SHARE_131 ckgen00(0x8e8)
#define REG_CKG_SRAM_SHARE_131_S 0
#define REG_CKG_SRAM_SHARE_131_E 1
#define REG_CKG_SRAM_SHARE_132 ckgen00(0x8f0)
#define REG_CKG_SRAM_SHARE_132_S 0
#define REG_CKG_SRAM_SHARE_132_E 1
#define REG_CKG_SRAM_SHARE_134_R ckgen00(0x8f8)
#define REG_CKG_SRAM_SHARE_134_R_S 0
#define REG_CKG_SRAM_SHARE_134_R_E 1
#define REG_CKG_SRAM_SHARE_134_W ckgen00(0x900)
#define REG_CKG_SRAM_SHARE_134_W_S 0
#define REG_CKG_SRAM_SHARE_134_W_E 1
#define REG_CKG_SRAM_SHARE_136_R ckgen00(0x908)
#define REG_CKG_SRAM_SHARE_136_R_S 0
#define REG_CKG_SRAM_SHARE_136_R_E 1
#define REG_CKG_SRAM_SHARE_136_W ckgen00(0x910)
#define REG_CKG_SRAM_SHARE_136_W_S 0
#define REG_CKG_SRAM_SHARE_136_W_E 1
#define REG_CKG_SRAM_SHARE_137_R ckgen00(0x918)
#define REG_CKG_SRAM_SHARE_137_R_S 0
#define REG_CKG_SRAM_SHARE_137_R_E 1
#define REG_CKG_SRAM_SHARE_137_W ckgen00(0x920)
#define REG_CKG_SRAM_SHARE_137_W_S 0
#define REG_CKG_SRAM_SHARE_137_W_E 1
#define REG_CKG_SRAM_SHARE_138_R ckgen00(0x928)
#define REG_CKG_SRAM_SHARE_138_R_S 0
#define REG_CKG_SRAM_SHARE_138_R_E 1
#define REG_CKG_SRAM_SHARE_138_W ckgen00(0x930)
#define REG_CKG_SRAM_SHARE_138_W_S 0
#define REG_CKG_SRAM_SHARE_138_W_E 1
#define REG_CKG_SRAM_SHARE_139_R ckgen00(0x938)
#define REG_CKG_SRAM_SHARE_139_R_S 0
#define REG_CKG_SRAM_SHARE_139_R_E 1
#define REG_CKG_SRAM_SHARE_139_W ckgen00(0x940)
#define REG_CKG_SRAM_SHARE_139_W_S 0
#define REG_CKG_SRAM_SHARE_139_W_E 1
#define REG_CKG_SRAM_SHARE_140_R ckgen00(0x948)
#define REG_CKG_SRAM_SHARE_140_R_S 0
#define REG_CKG_SRAM_SHARE_140_R_E 1
#define REG_CKG_SRAM_SHARE_140_W ckgen00(0x950)
#define REG_CKG_SRAM_SHARE_140_W_S 0
#define REG_CKG_SRAM_SHARE_140_W_E 1
#define REG_CKG_SRAM_SHARE_141_R ckgen00(0x958)
#define REG_CKG_SRAM_SHARE_141_R_S 0
#define REG_CKG_SRAM_SHARE_141_R_E 1
#define REG_CKG_SRAM_SHARE_141_W ckgen00(0x960)
#define REG_CKG_SRAM_SHARE_141_W_S 0
#define REG_CKG_SRAM_SHARE_141_W_E 1
#define REG_CKG_SRAM_SHARE_142_R ckgen00(0x968)
#define REG_CKG_SRAM_SHARE_142_R_S 0
#define REG_CKG_SRAM_SHARE_142_R_E 1
#define REG_CKG_SRAM_SHARE_142_W ckgen00(0x970)
#define REG_CKG_SRAM_SHARE_142_W_S 0
#define REG_CKG_SRAM_SHARE_142_W_E 1
#define REG_CKG_SRAM_SHARE_143_R ckgen00(0x978)
#define REG_CKG_SRAM_SHARE_143_R_S 0
#define REG_CKG_SRAM_SHARE_143_R_E 1
#define REG_CKG_SRAM_SHARE_143_W ckgen00(0x980)
#define REG_CKG_SRAM_SHARE_143_W_S 0
#define REG_CKG_SRAM_SHARE_143_W_E 1
#define REG_CKG_SRAM_SHARE_144_R ckgen00(0x988)
#define REG_CKG_SRAM_SHARE_144_R_S 0
#define REG_CKG_SRAM_SHARE_144_R_E 1
#define REG_CKG_SRAM_SHARE_144_W ckgen00(0x990)
#define REG_CKG_SRAM_SHARE_144_W_S 0
#define REG_CKG_SRAM_SHARE_144_W_E 1
#define REG_CKG_TDP_JL_INNER1X ckgen00(0x998)
#define REG_CKG_TDP_JL_INNER1X_S 0
#define REG_CKG_TDP_JL_INNER1X_E 1
#define REG_CKG_TDP_JL_INNER4X ckgen00(0x9a0)
#define REG_CKG_TDP_JL_INNER4X_S 0
#define REG_CKG_TDP_JL_INNER4X_E 1
#define REG_CKG_TDP_TEQ_INNER1X ckgen00(0x9a8)
#define REG_CKG_TDP_TEQ_INNER1X_S 0
#define REG_CKG_TDP_TEQ_INNER1X_E 1
#define REG_CKG_TDP_TEQ_INNER2X ckgen00(0x9b0)
#define REG_CKG_TDP_TEQ_INNER2X_S 0
#define REG_CKG_TDP_TEQ_INNER2X_E 1
#define REG_CKG_TR ckgen00(0x9b8)
#define REG_CKG_TR_S 0
#define REG_CKG_TR_E 1
#define REG_CKG_TS_IN ckgen00(0x9c0)
#define REG_CKG_TS_IN_S 0
#define REG_CKG_TS_IN_E 1
#define REG_CKG_VIFDBB_144M ckgen00(0x9c8)
#define REG_CKG_VIFDBB_144M_S 0
#define REG_CKG_VIFDBB_144M_E 1
#define REG_CKG_VIFDBB_43M ckgen00(0x9d0)
#define REG_CKG_VIFDBB_43M_S 0
#define REG_CKG_VIFDBB_43M_E 1
#define REG_CKG_VIFDBB_86M ckgen00(0x9d8)
#define REG_CKG_VIFDBB_86M_S 0
#define REG_CKG_VIFDBB_86M_E 1
#define REG_CKG_VIFDBB_DAC ckgen00(0x9e0)
#define REG_CKG_VIFDBB_DAC_S 0
#define REG_CKG_VIFDBB_DAC_E 1
#define REG_CKG_VIFDBB_VDAC ckgen00(0x9e8)
#define REG_CKG_VIFDBB_VDAC_S 0
#define REG_CKG_VIFDBB_VDAC_E 1
#define REG_CKG_VIFDBB_VDAC_TMP ckgen00(0x9f0)
#define REG_CKG_VIFDBB_VDAC_TMP_S 0
#define REG_CKG_VIFDBB_VDAC_TMP_E 1
#define REG_CKG_DEINTER ckgen00(0x9f8)
#define REG_CKG_DEINTER_S 0
#define REG_CKG_DEINTER_E 1
#define REG_CKG_DTMB_BCH_DEMOD1 ckgen00(0xa00)
#define REG_CKG_DTMB_BCH_DEMOD1_S 0
#define REG_CKG_DTMB_BCH_DEMOD1_E 1
#define REG_CKG_DTMB_OUTER1X_DEMOD1 ckgen00(0xa08)
#define REG_CKG_DTMB_OUTER1X_DEMOD1_S 0
#define REG_CKG_DTMB_OUTER1X_DEMOD1_E 1
#define REG_CKG_DVBS2_DEMAPPER ckgen00(0xa10)
#define REG_CKG_DVBS2_DEMAPPER_S 0
#define REG_CKG_DVBS2_DEMAPPER_E 1
#define REG_CKG_DVBS2_DVBT2_DEMAPPER ckgen00(0xa18)
#define REG_CKG_DVBS2_DVBT2_DEMAPPER_S 0
#define REG_CKG_DVBS2_DVBT2_DEMAPPER_E 1
#define REG_CKG_DVBS2_OUTER_FIFO_IN ckgen00(0xa20)
#define REG_CKG_DVBS2_OUTER_FIFO_IN_S 0
#define REG_CKG_DVBS2_OUTER_FIFO_IN_E 1
#define REG_CKG_DVBT2_DEMAPPER ckgen00(0xa28)
#define REG_CKG_DVBT2_DEMAPPER_S 0
#define REG_CKG_DVBT2_DEMAPPER_E 1
#define REG_CKG_DVBT2_DVBS2_OUTER_FIFO_IN ckgen00(0xa30)
#define REG_CKG_DVBT2_DVBS2_OUTER_FIFO_IN_S 0
#define REG_CKG_DVBT2_DVBS2_OUTER_FIFO_IN_E 1
#define REG_CKG_DVBT2_OUTER_FIFO_IN ckgen00(0xa38)
#define REG_CKG_DVBT2_OUTER_FIFO_IN_S 0
#define REG_CKG_DVBT2_OUTER_FIFO_IN_E 1
#define REG_CKG_DVBT2_S2_BCH ckgen00(0xa40)
#define REG_CKG_DVBT2_S2_BCH_S 0
#define REG_CKG_DVBT2_S2_BCH_E 1
#define REG_CKG_DVBT2_S2_BCH_OUT ckgen00(0xa48)
#define REG_CKG_DVBT2_S2_BCH_OUT_S 0
#define REG_CKG_DVBT2_S2_BCH_OUT_E 1
#define REG_CKG_LDPC1X ckgen00(0xa50)
#define REG_CKG_LDPC1X_S 0
#define REG_CKG_LDPC1X_E 1
#define REG_CKG_LDPC2X ckgen00(0xa58)
#define REG_CKG_LDPC2X_S 0
#define REG_CKG_LDPC2X_E 1
#define REG_CKG_SRAM_DVBT2_S2_BCH_ME ckgen00(0xa60)
#define REG_CKG_SRAM_DVBT2_S2_BCH_ME_S 0
#define REG_CKG_SRAM_DVBT2_S2_BCH_ME_E 1
#define REG_CKG_SRAM_LDPC1X_ME ckgen00(0xa68)
#define REG_CKG_SRAM_LDPC1X_ME_S 0
#define REG_CKG_SRAM_LDPC1X_ME_E 1
#define REG_CKG_SRAM_LDPC2X_ME ckgen00(0xa70)
#define REG_CKG_SRAM_LDPC2X_ME_S 0
#define REG_CKG_SRAM_LDPC2X_ME_E 1
#define REG_CKG_XTAL_24M_DEMOD1 ckgen00(0xa78)
#define REG_CKG_XTAL_24M_DEMOD1_S 0
#define REG_CKG_XTAL_24M_DEMOD1_E 1
#define REG_CKG_XTAL_12M_DEMOD1 ckgen00(0xab8)
#define REG_CKG_XTAL_12M_DEMOD1_S 0
#define REG_CKG_XTAL_12M_DEMOD1_E 1
#define REG_CKG_AESDMA ckgen00(0xb10)
#define REG_CKG_AESDMA_S 0
#define REG_CKG_AESDMA_E 3
#define REG_CKG_AESDMA_TSP ckgen00(0xb10)
#define REG_CKG_AESDMA_TSP_S 8
#define REG_CKG_AESDMA_TSP_E 9
#define REG_CKG_PARSER ckgen00(0xb18)
#define REG_CKG_PARSER_S 0
#define REG_CKG_PARSER_E 3
#define REG_CKG_VIVA_PARSER ckgen00(0xb18)
#define REG_CKG_VIVA_PARSER_S 8
#define REG_CKG_VIVA_PARSER_E 11
#define REG_CKG_PARSER_TSP ckgen00(0xb18)
#define REG_CKG_PARSER_TSP_S 12
#define REG_CKG_PARSER_TSP_E 13
#define REG_CKG_SMART2 ckgen00(0xb28)
#define REG_CKG_SMART2_S 0
#define REG_CKG_SMART2_E 3
#define REG_CKG_SMART2_MHEG5 ckgen00(0xb28)
#define REG_CKG_SMART2_MHEG5_S 8
#define REG_CKG_SMART2_MHEG5_E 9
#define REG_CKG_SMART ckgen00(0xb30)
#define REG_CKG_SMART_S 0
#define REG_CKG_SMART_E 3
#define REG_CKG_SMART_MHEG5 ckgen00(0xb30)
#define REG_CKG_SMART_MHEG5_S 8
#define REG_CKG_SMART_MHEG5_E 9
#define REG_CKG_TSO2_OUT_DIV_MN_SRC ckgen00(0xb38)
#define REG_CKG_TSO2_OUT_DIV_MN_SRC_S 0
#define REG_CKG_TSO2_OUT_DIV_MN_SRC_E 4
#define REG_CKG_TSO_OUT_DIV_MN_SRC ckgen00(0xb40)
#define REG_CKG_TSO_OUT_DIV_MN_SRC_S 0
#define REG_CKG_TSO_OUT_DIV_MN_SRC_E 4
#define REG_CKG_TSP ckgen00(0xb48)
#define REG_CKG_TSP_S 0
#define REG_CKG_TSP_E 3
#define REG_CKG_TSP_TSP ckgen00(0xb48)
#define REG_CKG_TSP_TSP_S 4
#define REG_CKG_TSP_TSP_E 5
#define REG_CKG_FIQ0_27M ckgen00(0xb50)
#define REG_CKG_FIQ0_27M_S 0
#define REG_CKG_FIQ0_27M_E 4
#define REG_CKG_MM0_27M ckgen00(0xb58)
#define REG_CKG_MM0_27M_S 0
#define REG_CKG_MM0_27M_E 4
#define REG_CKG_MM1_27M ckgen00(0xb60)
#define REG_CKG_MM1_27M_S 0
#define REG_CKG_MM1_27M_E 4
#define REG_CKG_PVR1_27M ckgen00(0xb68)
#define REG_CKG_PVR1_27M_S 0
#define REG_CKG_PVR1_27M_E 4
#define REG_CKG_PVR2_27M ckgen00(0xb70)
#define REG_CKG_PVR2_27M_S 0
#define REG_CKG_PVR2_27M_E 4
#define REG_CKG_PVR3_27M ckgen00(0xb78)
#define REG_CKG_PVR3_27M_S 0
#define REG_CKG_PVR3_27M_E 4
#define REG_CKG_PVR4_27M ckgen00(0xb80)
#define REG_CKG_PVR4_27M_S 0
#define REG_CKG_PVR4_27M_E 4
#define REG_CKG_STAMP ckgen00(0xb88)
#define REG_CKG_STAMP_S 0
#define REG_CKG_STAMP_E 2
#define REG_CKG_SYN_STC0 ckgen00(0xb90)
#define REG_CKG_SYN_STC0_S 0
#define REG_CKG_SYN_STC0_E 4
#define REG_CKG_SYN_STC1 ckgen00(0xb98)
#define REG_CKG_SYN_STC1_S 0
#define REG_CKG_SYN_STC1_E 4
#define REG_CKG_SYN_STC2 ckgen00(0xba0)
#define REG_CKG_SYN_STC2_S 0
#define REG_CKG_SYN_STC2_E 4
#define REG_CKG_SYN_STC3 ckgen00(0xba8)
#define REG_CKG_SYN_STC3_S 0
#define REG_CKG_SYN_STC3_E 4
#define REG_CKG_SYS_TIME0_27M ckgen00(0xbb0)
#define REG_CKG_SYS_TIME0_27M_S 0
#define REG_CKG_SYS_TIME0_27M_E 4
#define REG_CKG_SYS_TIME1_27M ckgen00(0xbb8)
#define REG_CKG_SYS_TIME1_27M_S 0
#define REG_CKG_SYS_TIME1_27M_E 4
#define REG_CKG_SYS_TIME2_27M ckgen00(0xbc0)
#define REG_CKG_SYS_TIME2_27M_S 0
#define REG_CKG_SYS_TIME2_27M_E 4
#define REG_CKG_SYS_TIME3_27M ckgen00(0xbc8)
#define REG_CKG_SYS_TIME3_27M_S 0
#define REG_CKG_SYS_TIME3_27M_E 4
#define REG_CKG_TLV0_27M ckgen00(0xbd0)
#define REG_CKG_TLV0_27M_S 0
#define REG_CKG_TLV0_27M_E 4
#define REG_CKG_TLV1_27M ckgen00(0xbd8)
#define REG_CKG_TLV1_27M_S 0
#define REG_CKG_TLV1_27M_E 4
#define REG_CKG_TLV2_27M ckgen00(0xbe0)
#define REG_CKG_TLV2_27M_S 0
#define REG_CKG_TLV2_27M_E 4
#define REG_CKG_TSIF0_27M ckgen00(0xbe8)
#define REG_CKG_TSIF0_27M_S 0
#define REG_CKG_TSIF0_27M_E 4
#define REG_CKG_TSO2_CH1_27M ckgen00(0xbf0)
#define REG_CKG_TSO2_CH1_27M_S 0
#define REG_CKG_TSO2_CH1_27M_E 4
#define REG_CKG_TSO2_CH5_27M ckgen00(0xbf8)
#define REG_CKG_TSO2_CH5_27M_S 0
#define REG_CKG_TSO2_CH5_27M_E 4
#define REG_CKG_TSO2_CH6_27M ckgen00(0xc00)
#define REG_CKG_TSO2_CH6_27M_S 0
#define REG_CKG_TSO2_CH6_27M_E 4
#define REG_CKG_P_TSO2_OUT ckgen00(0xc08)
#define REG_CKG_P_TSO2_OUT_S 0
#define REG_CKG_P_TSO2_OUT_E 4
#define REG_CKG_TSO_CH1_27M ckgen00(0xc10)
#define REG_CKG_TSO_CH1_27M_S 0
#define REG_CKG_TSO_CH1_27M_E 4
#define REG_CKG_TSO_CH5_27M ckgen00(0xc18)
#define REG_CKG_TSO_CH5_27M_S 0
#define REG_CKG_TSO_CH5_27M_E 4
#define REG_CKG_TSO_CH6_27M ckgen00(0xc20)
#define REG_CKG_TSO_CH6_27M_S 0
#define REG_CKG_TSO_CH6_27M_E 4
#define REG_CKG_P_TSO_OUT ckgen00(0xc28)
#define REG_CKG_P_TSO_OUT_S 0
#define REG_CKG_P_TSO_OUT_E 4
#define REG_CKG_SMART2_SYNTH_432 ckgen00(0xc30)
#define REG_CKG_SMART2_SYNTH_432_S 0
#define REG_CKG_SMART2_SYNTH_432_E 1
#define REG_CKG_SMART2_SYNTH_432_MHEG5 ckgen00(0xc30)
#define REG_CKG_SMART2_SYNTH_432_MHEG5_S 8
#define REG_CKG_SMART2_SYNTH_432_MHEG5_E 9
#define REG_CKG_SMART2_SYNTH_27 ckgen00(0xc38)
#define REG_CKG_SMART2_SYNTH_27_S 0
#define REG_CKG_SMART2_SYNTH_27_E 1
#define REG_CKG_SMART2_SYNTH_27_MHEG5 ckgen00(0xc38)
#define REG_CKG_SMART2_SYNTH_27_MHEG5_S 8
#define REG_CKG_SMART2_SYNTH_27_MHEG5_E 9
#define REG_CKG_SMART_SYNTH_432 ckgen00(0xc40)
#define REG_CKG_SMART_SYNTH_432_S 0
#define REG_CKG_SMART_SYNTH_432_E 1
#define REG_CKG_SMART_SYNTH_432_MHEG5 ckgen00(0xc40)
#define REG_CKG_SMART_SYNTH_432_MHEG5_S 8
#define REG_CKG_SMART_SYNTH_432_MHEG5_E 9
#define REG_CKG_SMART_SYNTH_27 ckgen00(0xc48)
#define REG_CKG_SMART_SYNTH_27_S 0
#define REG_CKG_SMART_SYNTH_27_E 1
#define REG_CKG_SMART_SYNTH_27_MHEG5 ckgen00(0xc48)
#define REG_CKG_SMART_SYNTH_27_MHEG5_S 8
#define REG_CKG_SMART_SYNTH_27_MHEG5_E 9
#define REG_CKG_PATH0_27M ckgen00(0xc50)
#define REG_CKG_PATH0_27M_S 0
#define REG_CKG_PATH0_27M_E 4
#define REG_CKG_PATH1_27M ckgen00(0xc58)
#define REG_CKG_PATH1_27M_S 0
#define REG_CKG_PATH1_27M_E 4
#define REG_CKG_PATH2_27M ckgen00(0xc60)
#define REG_CKG_PATH2_27M_S 0
#define REG_CKG_PATH2_27M_E 4
#define REG_CKG_PATH_FI_27M ckgen00(0xc68)
#define REG_CKG_PATH_FI_27M_S 0
#define REG_CKG_PATH_FI_27M_E 4
#define REG_CKG_SYNTH_PCM_TRX_256FS_VIVALDI9 ckgen00(0xc94)
#define REG_CKG_SYNTH_PCM_TRX_256FS_VIVALDI9_S 0
#define REG_CKG_SYNTH_PCM_TRX_256FS_VIVALDI9_E 2
#define REG_CKG_AUSDM_3M ckgen00(0xc98)
#define REG_CKG_AUSDM_3M_S 0
#define REG_CKG_AUSDM_3M_E 3
#define REG_CKG_BCLK_I2S_ENCODER2 ckgen00(0xca0)
#define REG_CKG_BCLK_I2S_ENCODER2_S 0
#define REG_CKG_BCLK_I2S_ENCODER2_E 2
#define REG_CKG_BCLK_I2S_ENCODER ckgen00(0xca8)
#define REG_CKG_BCLK_I2S_ENCODER_S 0
#define REG_CKG_BCLK_I2S_ENCODER_E 2
#define REG_CKG_EARC_TX_PLL_256FS_REF ckgen00(0xcb0)
#define REG_CKG_EARC_TX_PLL_256FS_REF_S 0
#define REG_CKG_EARC_TX_PLL_256FS_REF_E 2
#define REG_CKG_EARC_TX_PLL_256FS_MUX ckgen00(0xcb4)
#define REG_CKG_EARC_TX_PLL_256FS_MUX_S 0
#define REG_CKG_EARC_TX_PLL_256FS_MUX_E 2
#define REG_CKG_VIVA_AB3_MAC ckgen00(0xcb8)
#define REG_CKG_VIVA_AB3_MAC_S 0
#define REG_CKG_VIVA_AB3_MAC_E 4
#define REG_CKG_VIVA_AB_MAC ckgen00(0xcc0)
#define REG_CKG_VIVA_AB_MAC_S 0
#define REG_CKG_VIVA_AB_MAC_E 3
#define REG_CKG_VIVA_ADC_512FS ckgen00(0xcc8)
#define REG_CKG_VIVA_ADC_512FS_S 0
#define REG_CKG_VIVA_ADC_512FS_E 3
#define REG_CKG_VIVA_AUDMA_V2_R1_256FS ckgen00(0xcd0)
#define REG_CKG_VIVA_AUDMA_V2_R1_256FS_S 0
#define REG_CKG_VIVA_AUDMA_V2_R1_256FS_E 2
#define REG_CKG_VIVA_AUDMA_V2_R1_SYNTH_REF ckgen00(0xcd8)
#define REG_CKG_VIVA_AUDMA_V2_R1_SYNTH_REF_S 0
#define REG_CKG_VIVA_AUDMA_V2_R1_SYNTH_REF_E 4
#define REG_CKG_VIVA_AUDMA_V2_R2_256FS ckgen00(0xce0)
#define REG_CKG_VIVA_AUDMA_V2_R2_256FS_S 0
#define REG_CKG_VIVA_AUDMA_V2_R2_256FS_E 2
#define REG_CKG_VIVA_AUDMA_V2_R2_SYNTH_REF ckgen00(0xce8)
#define REG_CKG_VIVA_AUDMA_V2_R2_SYNTH_REF_S 0
#define REG_CKG_VIVA_AUDMA_V2_R2_SYNTH_REF_E 4
#define REG_CKG_VIVA_AUPLL_IN ckgen00(0xcf0)
#define REG_CKG_VIVA_AUPLL_IN_S 0
#define REG_CKG_VIVA_AUPLL_IN_E 3
#define REG_CKG_VIVA_BCLK_I2S_DECODER2 ckgen00(0xcf8)
#define REG_CKG_VIVA_BCLK_I2S_DECODER2_S 0
#define REG_CKG_VIVA_BCLK_I2S_DECODER2_E 3
#define REG_CKG_VIVA_BCLK_I2S_DECODER ckgen00(0xd00)
#define REG_CKG_VIVA_BCLK_I2S_DECODER_S 0
#define REG_CKG_VIVA_BCLK_I2S_DECODER_E 3
#define REG_CKG_VIVA_BI2S_SYNTH_REF2 ckgen00(0xd08)
#define REG_CKG_VIVA_BI2S_SYNTH_REF2_S 0
#define REG_CKG_VIVA_BI2S_SYNTH_REF2_E 4
#define REG_CKG_VIVA_CH1_256FSI ckgen00(0xd10)
#define REG_CKG_VIVA_CH1_256FSI_S 0
#define REG_CKG_VIVA_CH1_256FSI_E 2
#define REG_CKG_VIVA_CH2_256FSI ckgen00(0xd18)
#define REG_CKG_VIVA_CH2_256FSI_S 0
#define REG_CKG_VIVA_CH2_256FSI_E 2
#define REG_CKG_VIVA_CH3_256FSI ckgen00(0xd20)
#define REG_CKG_VIVA_CH3_256FSI_S 0
#define REG_CKG_VIVA_CH3_256FSI_E 2
#define REG_CKG_VIVA_CH4_256FSI ckgen00(0xd28)
#define REG_CKG_VIVA_CH4_256FSI_S 0
#define REG_CKG_VIVA_CH4_256FSI_E 2
#define REG_CKG_VIVA_CH5_256FSI ckgen00(0xd30)
#define REG_CKG_VIVA_CH5_256FSI_S 0
#define REG_CKG_VIVA_CH5_256FSI_E 2
#define REG_CKG_VIVA_CH6_256FSI ckgen00(0xd38)
#define REG_CKG_VIVA_CH6_256FSI_S 0
#define REG_CKG_VIVA_CH6_256FSI_E 2
#define REG_CKG_VIVA_CH7_256FSI ckgen00(0xd40)
#define REG_CKG_VIVA_CH7_256FSI_S 0
#define REG_CKG_VIVA_CH7_256FSI_E 2
#define REG_CKG_VIVA_CH8_256FSI ckgen00(0xd48)
#define REG_CKG_VIVA_CH8_256FSI_S 0
#define REG_CKG_VIVA_CH8_256FSI_E 2
#define REG_CKG_VIVA_CH9_256FSI ckgen00(0xd50)
#define REG_CKG_VIVA_CH9_256FSI_S 0
#define REG_CKG_VIVA_CH9_256FSI_E 2
#define REG_CKG_VIVA_CODEC_SH ckgen00(0xd58)
#define REG_CKG_VIVA_CODEC_SH_S 0
#define REG_CKG_VIVA_CODEC_SH_E 3
#define REG_CKG_VIVA_DAC_512FS ckgen00(0xd60)
#define REG_CKG_VIVA_DAC_512FS_S 0
#define REG_CKG_VIVA_DAC_512FS_E 3
#define REG_CKG_VIVA_DSP ckgen00(0xd68)
#define REG_CKG_VIVA_DSP_S 0
#define REG_CKG_VIVA_DSP_E 4
#define REG_CKG_VIVA_DVB1_SYNTH_REF ckgen00(0xd70)
#define REG_CKG_VIVA_DVB1_SYNTH_REF_S 0
#define REG_CKG_VIVA_DVB1_SYNTH_REF_E 3
#define REG_CKG_VIVA_DVB1_TIMING_GEN_256FS ckgen00(0xd78)
#define REG_CKG_VIVA_DVB1_TIMING_GEN_256FS_S 0
#define REG_CKG_VIVA_DVB1_TIMING_GEN_256FS_E 2
#define REG_CKG_VIVA_DVB2_SYNTH_REF ckgen00(0xd80)
#define REG_CKG_VIVA_DVB2_SYNTH_REF_S 0
#define REG_CKG_VIVA_DVB2_SYNTH_REF_E 3
#define REG_CKG_VIVA_DVB2_TIMING_GEN_256FS ckgen00(0xd88)
#define REG_CKG_VIVA_DVB2_TIMING_GEN_256FS_S 0
#define REG_CKG_VIVA_DVB2_TIMING_GEN_256FS_E 2
#define REG_CKG_VIVA_DVB3_SYNTH_REF ckgen00(0xd90)
#define REG_CKG_VIVA_DVB3_SYNTH_REF_S 0
#define REG_CKG_VIVA_DVB3_SYNTH_REF_E 3
#define REG_CKG_VIVA_DVB3_TIMING_GEN_256FS ckgen00(0xd98)
#define REG_CKG_VIVA_DVB3_TIMING_GEN_256FS_S 0
#define REG_CKG_VIVA_DVB3_TIMING_GEN_256FS_E 2
#define REG_CKG_VIVA_DVB4_SYNTH_REF ckgen00(0xda0)
#define REG_CKG_VIVA_DVB4_SYNTH_REF_S 0
#define REG_CKG_VIVA_DVB4_SYNTH_REF_E 3
#define REG_CKG_VIVA_DVB4_TIMING_GEN_256FS ckgen00(0xda8)
#define REG_CKG_VIVA_DVB4_TIMING_GEN_256FS_S 0
#define REG_CKG_VIVA_DVB4_TIMING_GEN_256FS_E 2
#define REG_CKG_VIVA_DVB5_TIMING_GEN_256FS ckgen00(0xdb0)
#define REG_CKG_VIVA_DVB5_TIMING_GEN_256FS_S 0
#define REG_CKG_VIVA_DVB5_TIMING_GEN_256FS_E 2
#define REG_CKG_VIVA_DVB6_TIMING_GEN_256FS ckgen00(0xdb8)
#define REG_CKG_VIVA_DVB6_TIMING_GEN_256FS_S 0
#define REG_CKG_VIVA_DVB6_TIMING_GEN_256FS_E 2
#define REG_CKG_VIVA_EARC_TX_32XCHXFS ckgen00(0xdc0)
#define REG_CKG_VIVA_EARC_TX_32XCHXFS_S 0
#define REG_CKG_VIVA_EARC_TX_32XCHXFS_E 2
#define REG_CKG_VIVA_EARC_TX_32XFS ckgen00(0xdc8)
#define REG_CKG_VIVA_EARC_TX_32XFS_S 0
#define REG_CKG_VIVA_EARC_TX_32XFS_E 2
#define REG_CKG_VIVA_EARC_TX_64XCHXFS ckgen00(0xdd0)
#define REG_CKG_VIVA_EARC_TX_64XCHXFS_S 0
#define REG_CKG_VIVA_EARC_TX_64XCHXFS_E 2
#define REG_CKG_VIVA_EARC_TX_GPA_SYNTH_REF ckgen00(0xdd8)
#define REG_CKG_VIVA_EARC_TX_GPA_SYNTH_REF_S 0
#define REG_CKG_VIVA_EARC_TX_GPA_SYNTH_REF_E 2
#define REG_CKG_VIVA_EARC_TX_PLL ckgen00(0xde0)
#define REG_CKG_VIVA_EARC_TX_PLL_S 0
#define REG_CKG_VIVA_EARC_TX_PLL_E 2
#define REG_CKG_VIVA_EARC_TX_SOURCE_256FS ckgen00(0xde8)
#define REG_CKG_VIVA_EARC_TX_SOURCE_256FS_S 0
#define REG_CKG_VIVA_EARC_TX_SOURCE_256FS_E 2
#define REG_CKG_VIVA_EARC_TX_SYNTH_IIR_REF ckgen00(0xdf0)
#define REG_CKG_VIVA_EARC_TX_SYNTH_IIR_REF_S 0
#define REG_CKG_VIVA_EARC_TX_SYNTH_IIR_REF_E 2
#define REG_CKG_VIVA_EARC_TX_SYNTH_REF ckgen00(0xdf8)
#define REG_CKG_VIVA_EARC_TX_SYNTH_REF_S 0
#define REG_CKG_VIVA_EARC_TX_SYNTH_REF_E 3
#define REG_CKG_VIVA_FM_DEMODULATOR ckgen00(0xe00)
#define REG_CKG_VIVA_FM_DEMODULATOR_S 0
#define REG_CKG_VIVA_FM_DEMODULATOR_E 4
#define REG_CKG_VIVA_GPA_240FSO ckgen00(0xe08)
#define REG_CKG_VIVA_GPA_240FSO_S 0
#define REG_CKG_VIVA_GPA_240FSO_E 2
#define REG_CKG_VIVA_GPA_256FSO ckgen00(0xe10)
#define REG_CKG_VIVA_GPA_256FSO_S 0
#define REG_CKG_VIVA_GPA_256FSO_E 2
#define REG_CKG_VIVA_GPA_480FSO ckgen00(0xe18)
#define REG_CKG_VIVA_GPA_480FSO_S 0
#define REG_CKG_VIVA_GPA_480FSO_E 2
#define REG_CKG_VIVA_HDMI_RX2_MPLL_432 ckgen00(0xe20)
#define REG_CKG_VIVA_HDMI_RX2_MPLL_432_S 0
#define REG_CKG_VIVA_HDMI_RX2_MPLL_432_E 2
#define REG_CKG_VIVA_HDMI_RX2_S2P_128FS ckgen00(0xe28)
#define REG_CKG_VIVA_HDMI_RX2_S2P_128FS_S 0
#define REG_CKG_VIVA_HDMI_RX2_S2P_128FS_E 2
#define REG_CKG_VIVA_HDMI_RX2_S2P_256FS ckgen00(0xe30)
#define REG_CKG_VIVA_HDMI_RX2_S2P_256FS_S 0
#define REG_CKG_VIVA_HDMI_RX2_S2P_256FS_E 2
#define REG_CKG_VIVA_HDMI_RX2_SYNTH_REF ckgen00(0xe38)
#define REG_CKG_VIVA_HDMI_RX2_SYNTH_REF_S 0
#define REG_CKG_VIVA_HDMI_RX2_SYNTH_REF_E 2
#define REG_CKG_VIVA_HDMI_RX2_V2A_TIME_STAMP ckgen00(0xe40)
#define REG_CKG_VIVA_HDMI_RX2_V2A_TIME_STAMP_S 0
#define REG_CKG_VIVA_HDMI_RX2_V2A_TIME_STAMP_E 1
#define REG_CKG_VIVA_HDMI_RX_MPLL_432 ckgen00(0xe48)
#define REG_CKG_VIVA_HDMI_RX_MPLL_432_S 0
#define REG_CKG_VIVA_HDMI_RX_MPLL_432_E 2
#define REG_CKG_VIVA_HDMI_RX_S2P_128FS ckgen00(0xe50)
#define REG_CKG_VIVA_HDMI_RX_S2P_128FS_S 0
#define REG_CKG_VIVA_HDMI_RX_S2P_128FS_E 2
#define REG_CKG_VIVA_HDMI_RX_S2P_256FS ckgen00(0xe58)
#define REG_CKG_VIVA_HDMI_RX_S2P_256FS_S 0
#define REG_CKG_VIVA_HDMI_RX_S2P_256FS_E 2
#define REG_CKG_VIVA_HDMI_RX_SYNTH_REF ckgen00(0xe60)
#define REG_CKG_VIVA_HDMI_RX_SYNTH_REF_S 0
#define REG_CKG_VIVA_HDMI_RX_SYNTH_REF_E 2
#define REG_CKG_VIVA_HDMI_RX_V2A_TIME_STAMP ckgen00(0xe68)
#define REG_CKG_VIVA_HDMI_RX_V2A_TIME_STAMP_S 0
#define REG_CKG_VIVA_HDMI_RX_V2A_TIME_STAMP_E 1
#define REG_CKG_VIVA_HDMI_TX_128FS ckgen00(0xe70)
#define REG_CKG_VIVA_HDMI_TX_128FS_S 0
#define REG_CKG_VIVA_HDMI_TX_128FS_E 2
#define REG_CKG_VIVA_HDMI_TX_256FS ckgen00(0xe78)
#define REG_CKG_VIVA_HDMI_TX_256FS_S 0
#define REG_CKG_VIVA_HDMI_TX_256FS_E 2
#define REG_CKG_VIVA_I2S_2_BCLK_SYNTH_REF ckgen00(0xe80)
#define REG_CKG_VIVA_I2S_2_BCLK_SYNTH_REF_S 0
#define REG_CKG_VIVA_I2S_2_BCLK_SYNTH_REF_E 3
#define REG_CKG_VIVA_I2S_BCLK_DG2 ckgen00(0xe88)
#define REG_CKG_VIVA_I2S_BCLK_DG2_S 0
#define REG_CKG_VIVA_I2S_BCLK_DG2_E 2
#define REG_CKG_VIVA_I2S_BCLK_DG ckgen00(0xe90)
#define REG_CKG_VIVA_I2S_BCLK_DG_S 0
#define REG_CKG_VIVA_I2S_BCLK_DG_E 2
#define REG_CKG_VIVA_I2S_BCLK_SYNTH_REF ckgen00(0xe98)
#define REG_CKG_VIVA_I2S_BCLK_SYNTH_REF_S 0
#define REG_CKG_VIVA_I2S_BCLK_SYNTH_REF_E 3
#define REG_CKG_VIVA_I2S_MCLK_SYNTH_REF ckgen00(0xea0)
#define REG_CKG_VIVA_I2S_MCLK_SYNTH_REF_S 0
#define REG_CKG_VIVA_I2S_MCLK_SYNTH_REF_E 2
#define REG_CKG_VIVA_I2S_SYNTH_REF ckgen00(0xea8)
#define REG_CKG_VIVA_I2S_SYNTH_REF_S 0
#define REG_CKG_VIVA_I2S_SYNTH_REF_E 4
#define REG_CKG_VIVA_I2S_TRX_BCLK_TIMING_GEN ckgen00(0xeb0)
#define REG_CKG_VIVA_I2S_TRX_BCLK_TIMING_GEN_S 0
#define REG_CKG_VIVA_I2S_TRX_BCLK_TIMING_GEN_E 3
#define REG_CKG_VIVA_I2S_TRX_SYNTH_REF ckgen00(0xeb8)
#define REG_CKG_VIVA_I2S_TRX_SYNTH_REF_S 0
#define REG_CKG_VIVA_I2S_TRX_SYNTH_REF_E 4
#define REG_CKG_VIVA_I2S_TX_FIFO_256FS ckgen00(0xec0)
#define REG_CKG_VIVA_I2S_TX_FIFO_256FS_S 0
#define REG_CKG_VIVA_I2S_TX_FIFO_256FS_E 2
#define REG_CKG_VIVA_MCLK_I2S_DECODER2 ckgen00(0xec8)
#define REG_CKG_VIVA_MCLK_I2S_DECODER2_S 0
#define REG_CKG_VIVA_MCLK_I2S_DECODER2_E 4
#define REG_CKG_VIVA_MCLK_I2S_DECODER ckgen00(0xed0)
#define REG_CKG_VIVA_MCLK_I2S_DECODER_S 0
#define REG_CKG_VIVA_MCLK_I2S_DECODER_E 4
#define REG_CKG_VIVA_MCLK_I2S_ENCODER2 ckgen00(0xed8)
#define REG_CKG_VIVA_MCLK_I2S_ENCODER2_S 0
#define REG_CKG_VIVA_MCLK_I2S_ENCODER2_E 4
#define REG_CKG_VIVA_MCLK_I2S_ENCODER ckgen00(0xee0)
#define REG_CKG_VIVA_MCLK_I2S_ENCODER_S 0
#define REG_CKG_VIVA_MCLK_I2S_ENCODER_E 4
#define REG_CKG_VIVA_NPCM2_SYNTH_REF ckgen00(0xee8)
#define REG_CKG_VIVA_NPCM2_SYNTH_REF_S 0
#define REG_CKG_VIVA_NPCM2_SYNTH_REF_E 3
#define REG_CKG_VIVA_NPCM3_SYNTH_REF ckgen00(0xef0)
#define REG_CKG_VIVA_NPCM3_SYNTH_REF_S 0
#define REG_CKG_VIVA_NPCM3_SYNTH_REF_E 3
#define REG_CKG_VIVA_NPCM4_256FS_TIMING_GEN ckgen00(0xef8)
#define REG_CKG_VIVA_NPCM4_256FS_TIMING_GEN_S 0
#define REG_CKG_VIVA_NPCM4_256FS_TIMING_GEN_E 2
#define REG_CKG_VIVA_NPCM4_SYNTH_REF ckgen00(0xf00)
#define REG_CKG_VIVA_NPCM4_SYNTH_REF_S 0
#define REG_CKG_VIVA_NPCM4_SYNTH_REF_E 3
#define REG_CKG_VIVA_NPCM5_256FS_TIMING_GEN ckgen00(0xf08)
#define REG_CKG_VIVA_NPCM5_256FS_TIMING_GEN_S 0
#define REG_CKG_VIVA_NPCM5_256FS_TIMING_GEN_E 2
#define REG_CKG_VIVA_NPCM5_SYNTH_REF ckgen00(0xf10)
#define REG_CKG_VIVA_NPCM5_SYNTH_REF_S 0
#define REG_CKG_VIVA_NPCM5_SYNTH_REF_E 3
#define REG_CKG_VIVA_NPCM_SYNTH_REF ckgen00(0xf18)
#define REG_CKG_VIVA_NPCM_SYNTH_REF_S 0
#define REG_CKG_VIVA_NPCM_SYNTH_REF_E 3
#define REG_CKG_VIVA_PCM_CLK_216 ckgen00(0xf20)
#define REG_CKG_VIVA_PCM_CLK_216_S 0
#define REG_CKG_VIVA_PCM_CLK_216_E 2
#define REG_CKG_VIVA_PCM_CLK_AUPLL ckgen00(0xf28)
#define REG_CKG_VIVA_PCM_CLK_AUPLL_S 0
#define REG_CKG_VIVA_PCM_CLK_AUPLL_E 2
#define REG_CKG_R2_VIVALDI9 ckgen00(0xf2c)
#define REG_CKG_R2_VIVALDI9_S 0
#define REG_CKG_R2_VIVALDI9_E 1
#define REG_CKG_VIVA_R2_WB ckgen00(0xf30)
#define REG_CKG_VIVA_R2_WB_S 0
#define REG_CKG_VIVA_R2_WB_E 2
#define REG_CKG_AU_R2_WB ckgen00(0xf30)
#define REG_CKG_AU_R2_WB_S 8
#define REG_CKG_AU_R2_WB_E 9
#define REG_CKG_VIVA_RIU_BRG_R2 ckgen00(0xf38)
#define REG_CKG_VIVA_RIU_BRG_R2_S 0
#define REG_CKG_VIVA_RIU_BRG_R2_E 2
#define REG_CKG_MCU_WB_RV55FRC ckgen00(0xf3c)
#define REG_CKG_MCU_WB_RV55FRC_S 2
#define REG_CKG_MCU_WB_RV55FRC_E 3
#define REG_CKG_MCU_WB_RV55PQU ckgen00(0xf3c)
#define REG_CKG_MCU_WB_RV55PQU_S 4
#define REG_CKG_MCU_WB_RV55PQU_E 5
#define REG_CKG_VIVA_RIU_R2 ckgen00(0xf40)
#define REG_CKG_VIVA_RIU_R2_S 0
#define REG_CKG_VIVA_RIU_R2_E 3
#define REG_CKG_VIVA_SH ckgen00(0xf48)
#define REG_CKG_VIVA_SH_S 0
#define REG_CKG_VIVA_SH_E 2
#define REG_CKG_VIVA_SIF_ADC_CIC ckgen00(0xf50)
#define REG_CKG_VIVA_SIF_ADC_CIC_S 0
#define REG_CKG_VIVA_SIF_ADC_CIC_E 3
#define REG_CKG_VIVA_SIF_ADC_R2B_FIFO_IN ckgen00(0xf58)
#define REG_CKG_VIVA_SIF_ADC_R2B_FIFO_IN_S 0
#define REG_CKG_VIVA_SIF_ADC_R2B_FIFO_IN_E 3
#define REG_CKG_VIVA_SIF_ADC_R2B ckgen00(0xf60)
#define REG_CKG_VIVA_SIF_ADC_R2B_S 0
#define REG_CKG_VIVA_SIF_ADC_R2B_E 3
#define REG_CKG_SIF_CORDIC ckgen00(0xf68)
#define REG_CKG_SIF_CORDIC_S 0
#define REG_CKG_SIF_CORDIC_E 4
#define REG_CKG_VIVA_SIF_SYNTH ckgen00(0xf70)
#define REG_CKG_VIVA_SIF_SYNTH_S 0
#define REG_CKG_VIVA_SIF_SYNTH_E 3
#define REG_CKG_VIVA_SIN_GEN ckgen00(0xf78)
#define REG_CKG_VIVA_SIN_GEN_S 0
#define REG_CKG_VIVA_SIN_GEN_E 2
#define REG_CKG_VIVA_SPDIF_EXTEARC ckgen00(0xf80)
#define REG_CKG_VIVA_SPDIF_EXTEARC_S 0
#define REG_CKG_VIVA_SPDIF_EXTEARC_E 2
#define REG_CKG_VIVA_SPDIF_RX_128FS ckgen00(0xf88)
#define REG_CKG_VIVA_SPDIF_RX_128FS_S 0
#define REG_CKG_VIVA_SPDIF_RX_128FS_E 2
#define REG_CKG_VIVA_SPDIF_RX_DG ckgen00(0xf90)
#define REG_CKG_VIVA_SPDIF_RX_DG_S 0
#define REG_CKG_VIVA_SPDIF_RX_DG_E 2
#define REG_CKG_VIVA_SPDIF_RX_SYNTH_REF ckgen00(0xf98)
#define REG_CKG_VIVA_SPDIF_RX_SYNTH_REF_S 0
#define REG_CKG_VIVA_SPDIF_RX_SYNTH_REF_E 3
#define REG_CKG_VIVA_SPDIF_TX2_128FS ckgen00(0xfa0)
#define REG_CKG_VIVA_SPDIF_TX2_128FS_S 0
#define REG_CKG_VIVA_SPDIF_TX2_128FS_E 2
#define REG_CKG_VIVA_SPDIF_TX2_256FS ckgen00(0xfa8)
#define REG_CKG_VIVA_SPDIF_TX2_256FS_S 0
#define REG_CKG_VIVA_SPDIF_TX2_256FS_E 2
#define REG_CKG_VIVA_SPDIF_TX_128FS ckgen00(0xfb0)
#define REG_CKG_VIVA_SPDIF_TX_128FS_S 0
#define REG_CKG_VIVA_SPDIF_TX_128FS_E 2
#define REG_CKG_VIVA_SPDIF_TX_256FS ckgen00(0xfb8)
#define REG_CKG_VIVA_SPDIF_TX_256FS_S 0
#define REG_CKG_VIVA_SPDIF_TX_256FS_E 2
#define REG_CKG_VIVA_SPDIF_TX_SYNTH_REF ckgen00(0xfc0)
#define REG_CKG_VIVA_SPDIF_TX_SYNTH_REF_S 0
#define REG_CKG_VIVA_SPDIF_TX_SYNTH_REF_E 2
#define REG_CKG_VIVA_SYNTH_2ND_ORDER ckgen00(0xfc8)
#define REG_CKG_VIVA_SYNTH_2ND_ORDER_S 0
#define REG_CKG_VIVA_SYNTH_2ND_ORDER_E 3
#define REG_CKG_VIVA_SYNTH_CODEC ckgen00(0xfd0)
#define REG_CKG_VIVA_SYNTH_CODEC_S 0
#define REG_CKG_VIVA_SYNTH_CODEC_E 3
#define REG_CKG_VIVA_TEST_BUS ckgen00(0xfd8)
#define REG_CKG_VIVA_TEST_BUS_S 0
#define REG_CKG_VIVA_TEST_BUS_E 2
#define REG_CKG_VIVA_VBDMA_MCU ckgen00(0xfe0)
#define REG_CKG_VIVA_VBDMA_MCU_S 0
#define REG_CKG_VIVA_VBDMA_MCU_E 2
#define REG_CKG_VIVA_XTAL_12M ckgen00(0xfe8)
#define REG_CKG_VIVA_XTAL_12M_S 0
#define REG_CKG_VIVA_XTAL_12M_E 1
#define REG_CKG_VIVA_XTAL_24M ckgen00(0xff0)
#define REG_CKG_VIVA_XTAL_24M_S 0
#define REG_CKG_VIVA_XTAL_24M_E 1
#define REG_CKG_AU_R2_DFS ckgen00(0xff8)
#define REG_CKG_AU_R2_DFS_S 0
#define REG_CKG_AU_R2_DFS_E 2
#define REG_CKG_AU_R2_PLL ckgen00(0x1000)
#define REG_CKG_AU_R2_PLL_S 0
#define REG_CKG_AU_R2_PLL_E 2
#define REG_CKG_XTAL_12M_AUDIO_R2 ckgen00(0x1010)
#define REG_CKG_XTAL_12M_AUDIO_R2_S 0
#define REG_CKG_XTAL_12M_AUDIO_R2_E 1
#define REG_CKG_XTAL_24M_AUDIO_R2 ckgen00(0x1014)
#define REG_CKG_XTAL_24M_AUDIO_R2_S 0
#define REG_CKG_XTAL_24M_AUDIO_R2_E 1
#define REG_CKG_AUDMA_V2_R1_256FS ckgen00(0x1020)
#define REG_CKG_AUDMA_V2_R1_256FS_S 0
#define REG_CKG_AUDMA_V2_R1_256FS_E 0
#define REG_CKG_BCLK_I2S_ENCODER2_MUX ckgen00(0x1028)
#define REG_CKG_BCLK_I2S_ENCODER2_MUX_S 0
#define REG_CKG_BCLK_I2S_ENCODER2_MUX_E 2
#define REG_CKG_BCLK_I2S_ENCODER_MUX ckgen00(0x1030)
#define REG_CKG_BCLK_I2S_ENCODER_MUX_S 0
#define REG_CKG_BCLK_I2S_ENCODER_MUX_E 2
#define REG_CKG_CH5_256FSI_MUX ckgen00(0x1058)
#define REG_CKG_CH5_256FSI_MUX_S 0
#define REG_CKG_CH5_256FSI_MUX_E 4
#define REG_CKG_CH6_256FSI_MUX ckgen00(0x1060)
#define REG_CKG_CH6_256FSI_MUX_S 0
#define REG_CKG_CH6_256FSI_MUX_E 4
#define REG_CKG_CH7_256FSI_MUX ckgen00(0x1068)
#define REG_CKG_CH7_256FSI_MUX_S 0
#define REG_CKG_CH7_256FSI_MUX_E 4
#define REG_CKG_CH8_256FSI_MUX ckgen00(0x1070)
#define REG_CKG_CH8_256FSI_MUX_S 0
#define REG_CKG_CH8_256FSI_MUX_E 4
#define REG_CKG_CH9_256FSI_MUX ckgen00(0x1078)
#define REG_CKG_CH9_256FSI_MUX_S 0
#define REG_CKG_CH9_256FSI_MUX_E 4
#define REG_CKG_DEC1_SYNTH_HDMI_CTSN_DIV_MUX ckgen00(0x1080)
#define REG_CKG_DEC1_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC1_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX ckgen00(0x1088)
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_DEC2_SYNTH_HDMI_CTSN_DIV_MUX ckgen00(0x1090)
#define REG_CKG_DEC2_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC2_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX ckgen00(0x1098)
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_DEC3_SYNTH_HDMI_CTSN_DIV_MUX ckgen00(0x10a0)
#define REG_CKG_DEC3_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC3_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX ckgen00(0x10a8)
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_DEC4_SYNTH_HDMI_CTSN_DIV_MUX ckgen00(0x10b0)
#define REG_CKG_DEC4_SYNTH_HDMI_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC4_SYNTH_HDMI_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX ckgen00(0x10b8)
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX_S 0
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX_E 0
#define REG_CKG_DECODER1_FUNCTION_MUX ckgen00(0x10c0)
#define REG_CKG_DECODER1_FUNCTION_MUX_S 0
#define REG_CKG_DECODER1_FUNCTION_MUX_E 3
#define REG_CKG_DECODER2_FUNCTION_MUX ckgen00(0x10c8)
#define REG_CKG_DECODER2_FUNCTION_MUX_S 0
#define REG_CKG_DECODER2_FUNCTION_MUX_E 3
#define REG_CKG_DECODER3_FUNCTION_MUX ckgen00(0x10d0)
#define REG_CKG_DECODER3_FUNCTION_MUX_S 0
#define REG_CKG_DECODER3_FUNCTION_MUX_E 3
#define REG_CKG_DECODER4_FUNCTION_MUX ckgen00(0x10d8)
#define REG_CKG_DECODER4_FUNCTION_MUX_S 0
#define REG_CKG_DECODER4_FUNCTION_MUX_E 3
#define REG_CKG_EARC_TX_GPA_SYNTH_MUX ckgen00(0x10e0)
#define REG_CKG_EARC_TX_GPA_SYNTH_MUX_S 0
#define REG_CKG_EARC_TX_GPA_SYNTH_MUX_E 1
#define REG_CKG_EARC_TX_SOURCE_MUX ckgen00(0x10e8)
#define REG_CKG_EARC_TX_SOURCE_MUX_S 0
#define REG_CKG_EARC_TX_SOURCE_MUX_E 2
#define REG_CKG_HDMI2_PATGEN_EN ckgen00(0x10f0)
#define REG_CKG_HDMI2_PATGEN_EN_S 0
#define REG_CKG_HDMI2_PATGEN_EN_E 0
#define REG_CKG_HDMI_PATGEN_EN ckgen00(0x10f8)
#define REG_CKG_HDMI_PATGEN_EN_S 0
#define REG_CKG_HDMI_PATGEN_EN_E 0
#define REG_CKG_HDMI_RX_BYPASS_TO_TX ckgen00(0x1100)
#define REG_CKG_HDMI_RX_BYPASS_TO_TX_S 0
#define REG_CKG_HDMI_RX_BYPASS_TO_TX_E 0
#define REG_CKG_HDMI_TX_256FS_MUX0 ckgen00(0x1108)
#define REG_CKG_HDMI_TX_256FS_MUX0_S 0
#define REG_CKG_HDMI_TX_256FS_MUX0_E 0
#define REG_CKG_HDMI_TX_256FS_MUX1 ckgen00(0x1110)
#define REG_CKG_HDMI_TX_256FS_MUX1_S 0
#define REG_CKG_HDMI_TX_256FS_MUX1_E 0
#define REG_CKG_HDMI_TX_TO_I2S_TX ckgen00(0x1118)
#define REG_CKG_HDMI_TX_TO_I2S_TX_S 0
#define REG_CKG_HDMI_TX_TO_I2S_TX_E 0
#define REG_CKG_I2S_2_SYNTH_SSC_MUX ckgen00(0x1120)
#define REG_CKG_I2S_2_SYNTH_SSC_MUX_S 0
#define REG_CKG_I2S_2_SYNTH_SSC_MUX_E 0
#define REG_CKG_I2S_CH ckgen00(0x1128)
#define REG_CKG_I2S_CH_S 0
#define REG_CKG_I2S_CH_E 0
#define REG_CKG_I2S_SYNTH_SSC_MUX ckgen00(0x1130)
#define REG_CKG_I2S_SYNTH_SSC_MUX_S 0
#define REG_CKG_I2S_SYNTH_SSC_MUX_E 0
#define REG_CKG_PCM_MODE ckgen00(0x1138)
#define REG_CKG_PCM_MODE_S 0
#define REG_CKG_PCM_MODE_E 0
#define REG_CKG_R2_WB_MUX ckgen00(0x1140)
#define REG_CKG_R2_WB_MUX_S 0
#define REG_CKG_R2_WB_MUX_E 2
#define REG_CKG_SPDIF_EXTEARC_128FS_MUX ckgen00(0x1148)
#define REG_CKG_SPDIF_EXTEARC_128FS_MUX_S 0
#define REG_CKG_SPDIF_EXTEARC_128FS_MUX_E 2
#define REG_CKG_SPDIF_EXTEARC_256FS_MUX ckgen00(0x1150)
#define REG_CKG_SPDIF_EXTEARC_256FS_MUX_S 0
#define REG_CKG_SPDIF_EXTEARC_256FS_MUX_E 2
#define REG_CKG_SPDIF_EXTEARC_MUX ckgen00(0x1158)
#define REG_CKG_SPDIF_EXTEARC_MUX_S 0
#define REG_CKG_SPDIF_EXTEARC_MUX_E 0
#define REG_CKG_SPDIF_EXTEARC_MUX0 ckgen00(0x1160)
#define REG_CKG_SPDIF_EXTEARC_MUX0_S 0
#define REG_CKG_SPDIF_EXTEARC_MUX0_E 0
#define REG_CKG_SPDIF_TX2_GPA_SYNTH_MUX ckgen00(0x1168)
#define REG_CKG_SPDIF_TX2_GPA_SYNTH_MUX_S 0
#define REG_CKG_SPDIF_TX2_GPA_SYNTH_MUX_E 1
#define REG_CKG_SPDIF_TX2_MUX ckgen00(0x1170)
#define REG_CKG_SPDIF_TX2_MUX_S 0
#define REG_CKG_SPDIF_TX2_MUX_E 2
#define REG_CKG_SPDIF_TX_GPA_SYNTH_MUX ckgen00(0x1178)
#define REG_CKG_SPDIF_TX_GPA_SYNTH_MUX_S 0
#define REG_CKG_SPDIF_TX_GPA_SYNTH_MUX_E 1
#define REG_CKG_SPDIF_TX_MUX ckgen00(0x1180)
#define REG_CKG_SPDIF_TX_MUX_S 0
#define REG_CKG_SPDIF_TX_MUX_E 2
#define REG_CKG_VIVA_I2S_TX_2_FIFO_256FS ckgen00(0x1184)
#define REG_CKG_VIVA_I2S_TX_2_FIFO_256FS_S 0
#define REG_CKG_VIVA_I2S_TX_2_FIFO_256FS_E 3
#define REG_CKG_EARC_AUDIO_EARC_DMACRO ckgen00(0x1188)
#define REG_CKG_EARC_AUDIO_EARC_DMACRO_S 0
#define REG_CKG_EARC_AUDIO_EARC_DMACRO_E 2
#define REG_CKG_AUSDM_3M_CK ckgen00(0x1190)
#define REG_CKG_AUSDM_3M_CK_S 0
#define REG_CKG_AUSDM_3M_CK_E 1
#define REG_CKG_CH10_256FSI_MUX ckgen00(0x1194)
#define REG_CKG_CH10_256FSI_MUX_S 0
#define REG_CKG_CH10_256FSI_MUX_E 4
#define REG_CKG_CH_M1_256FSI_MUX ckgen00(0x1198)
#define REG_CKG_CH_M1_256FSI_MUX_S 0
#define REG_CKG_CH_M1_256FSI_MUX_E 3
#define REG_CKG_CH_M2_256FSI_MUX ckgen00(0x119c)
#define REG_CKG_CH_M2_256FSI_MUX_S 0
#define REG_CKG_CH_M2_256FSI_MUX_E 3
#define REG_CKG_CH_M3_256FSI_MUX ckgen00(0x11a0)
#define REG_CKG_CH_M3_256FSI_MUX_S 0
#define REG_CKG_CH_M3_256FSI_MUX_E 3
#define REG_CKG_CH_M4_256FSI_MUX ckgen00(0x11a4)
#define REG_CKG_CH_M4_256FSI_MUX_S 0
#define REG_CKG_CH_M4_256FSI_MUX_E 3
#define REG_CKG_CH_M5_256FSI_MUX ckgen00(0x11a8)
#define REG_CKG_CH_M5_256FSI_MUX_S 0
#define REG_CKG_CH_M5_256FSI_MUX_E 3
#define REG_CKG_CH_M6_256FSI_MUX ckgen00(0x11ac)
#define REG_CKG_CH_M6_256FSI_MUX_S 0
#define REG_CKG_CH_M6_256FSI_MUX_E 3
#define REG_CKG_CH_M7_256FSI_MUX ckgen00(0x11b0)
#define REG_CKG_CH_M7_256FSI_MUX_S 0
#define REG_CKG_CH_M7_256FSI_MUX_E 3
#define REG_CKG_CH_M8_256FSI_MUX ckgen00(0x11b4)
#define REG_CKG_CH_M8_256FSI_MUX_S 0
#define REG_CKG_CH_M8_256FSI_MUX_E 3
#define REG_CKG_CH_M9_256FSI_MUX ckgen00(0x11b8)
#define REG_CKG_CH_M9_256FSI_MUX_S 0
#define REG_CKG_CH_M9_256FSI_MUX_E 3
#define REG_CKG_CH_M10_256FSI_MUX ckgen00(0x11bc)
#define REG_CKG_CH_M10_256FSI_MUX_S 0
#define REG_CKG_CH_M10_256FSI_MUX_E 3
#define REG_CKG_CH_M11_256FSI_MUX ckgen00(0x11c0)
#define REG_CKG_CH_M11_256FSI_MUX_S 0
#define REG_CKG_CH_M11_256FSI_MUX_E 3
#define REG_CKG_CH_M12_256FSI_MUX ckgen00(0x11c4)
#define REG_CKG_CH_M12_256FSI_MUX_S 0
#define REG_CKG_CH_M12_256FSI_MUX_E 3
#define REG_CKG_CH_M13_256FSI_MUX ckgen00(0x11c8)
#define REG_CKG_CH_M13_256FSI_MUX_S 0
#define REG_CKG_CH_M13_256FSI_MUX_E 3
#define REG_CKG_CH_M14_256FSI_MUX ckgen00(0x11cc)
#define REG_CKG_CH_M14_256FSI_MUX_S 0
#define REG_CKG_CH_M14_256FSI_MUX_E 3
#define REG_CKG_CH_M15_256FSI_MUX ckgen00(0x11d0)
#define REG_CKG_CH_M15_256FSI_MUX_S 0
#define REG_CKG_CH_M15_256FSI_MUX_E 3
#define REG_CKG_CH_M16_256FSI_MUX ckgen00(0x11d4)
#define REG_CKG_CH_M16_256FSI_MUX_S 0
#define REG_CKG_CH_M16_256FSI_MUX_E 3
#define REG_CKG_DAP_TCK_VIVALDI9 ckgen00(0x11d8)
#define REG_CKG_DAP_TCK_VIVALDI9_S 0
#define REG_CKG_DAP_TCK_VIVALDI9_E 1
#define REG_CKG_DAP_VIVALDI9 ckgen00(0x11dc)
#define REG_CKG_DAP_VIVALDI9_S 0
#define REG_CKG_DAP_VIVALDI9_E 1
#define REG_CKG_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX ckgen00(0x11e0)
#define REG_CKG_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV_MUX ckgen00(0x11e4)
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX ckgen00(0x11e8)
#define REG_CKG_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV_MUX ckgen00(0x11ec)
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX ckgen00(0x11f0)
#define REG_CKG_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV_MUX ckgen00(0x11f4)
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX ckgen00(0x11f8)
#define REG_CKG_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX_S 0
#define REG_CKG_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX_E 2
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV_MUX ckgen00(0x11fc)
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV_MUX_S 0
#define REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV_MUX_E 2
#define REG_CKG_VIVA_CH10_256FSI ckgen00(0x1208)
#define REG_CKG_VIVA_CH10_256FSI_S 0
#define REG_CKG_VIVA_CH10_256FSI_E 2
#define REG_CKG_VIVA_CH_M1_256FSI ckgen00(0x120c)
#define REG_CKG_VIVA_CH_M1_256FSI_S 0
#define REG_CKG_VIVA_CH_M1_256FSI_E 2
#define REG_CKG_VIVA_CH_M2_256FSI ckgen00(0x1210)
#define REG_CKG_VIVA_CH_M2_256FSI_S 0
#define REG_CKG_VIVA_CH_M2_256FSI_E 2
#define REG_CKG_VIVA_CH_M3_256FSI ckgen00(0x1214)
#define REG_CKG_VIVA_CH_M3_256FSI_S 0
#define REG_CKG_VIVA_CH_M3_256FSI_E 2
#define REG_CKG_VIVA_CH_M4_256FSI ckgen00(0x1218)
#define REG_CKG_VIVA_CH_M4_256FSI_S 0
#define REG_CKG_VIVA_CH_M4_256FSI_E 2
#define REG_CKG_VIVA_CH_M5_256FSI ckgen00(0x121c)
#define REG_CKG_VIVA_CH_M5_256FSI_S 0
#define REG_CKG_VIVA_CH_M5_256FSI_E 2
#define REG_CKG_VIVA_CH_M6_256FSI ckgen00(0x1220)
#define REG_CKG_VIVA_CH_M6_256FSI_S 0
#define REG_CKG_VIVA_CH_M6_256FSI_E 2
#define REG_CKG_VIVA_CH_M7_256FSI ckgen00(0x1224)
#define REG_CKG_VIVA_CH_M7_256FSI_S 0
#define REG_CKG_VIVA_CH_M7_256FSI_E 2
#define REG_CKG_VIVA_CH_M8_256FSI ckgen00(0x1228)
#define REG_CKG_VIVA_CH_M8_256FSI_S 0
#define REG_CKG_VIVA_CH_M8_256FSI_E 2
#define REG_CKG_VIVA_CH_M9_256FSI ckgen00(0x122c)
#define REG_CKG_VIVA_CH_M9_256FSI_S 0
#define REG_CKG_VIVA_CH_M9_256FSI_E 2
#define REG_CKG_VIVA_CH_M10_256FSI ckgen00(0x1230)
#define REG_CKG_VIVA_CH_M10_256FSI_S 0
#define REG_CKG_VIVA_CH_M10_256FSI_E 2
#define REG_CKG_VIVA_CH_M11_256FSI ckgen00(0x1234)
#define REG_CKG_VIVA_CH_M11_256FSI_S 0
#define REG_CKG_VIVA_CH_M11_256FSI_E 2
#define REG_CKG_VIVA_CH_M12_256FSI ckgen00(0x1238)
#define REG_CKG_VIVA_CH_M12_256FSI_S 0
#define REG_CKG_VIVA_CH_M12_256FSI_E 2
#define REG_CKG_VIVA_CH_M13_256FSI ckgen00(0x123c)
#define REG_CKG_VIVA_CH_M13_256FSI_S 0
#define REG_CKG_VIVA_CH_M13_256FSI_E 2
#define REG_CKG_VIVA_CH_M14_256FSI ckgen00(0x1240)
#define REG_CKG_VIVA_CH_M14_256FSI_S 0
#define REG_CKG_VIVA_CH_M14_256FSI_E 2
#define REG_CKG_VIVA_CH_M15_256FSI ckgen00(0x1244)
#define REG_CKG_VIVA_CH_M15_256FSI_S 0
#define REG_CKG_VIVA_CH_M15_256FSI_E 2
#define REG_CKG_VIVA_CH_M16_256FSI ckgen00(0x1248)
#define REG_CKG_VIVA_CH_M16_256FSI_S 0
#define REG_CKG_VIVA_CH_M16_256FSI_E 2
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK ckgen00(0x124c)
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK_S 0
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK_E 4
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD ckgen00(0x1250)
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_S 0
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_E 2
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_FIFO ckgen00(0x1254)
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_FIFO_S 0
#define REG_CKG_VIVA_I2S_TDM_1X16TX32B_FIFO_E 2
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK ckgen00(0x1258)
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK_S 0
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK_E 4
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD ckgen00(0x125c)
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_S 0
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_E 2
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_FIFO ckgen00(0x1260)
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_FIFO_S 0
#define REG_CKG_VIVA_I2S_TDM_6X16TX32B_FIFO_E 2
#define REG_CKG_VIVA_SRC_MAC_BSPLINE ckgen00(0x1264)
#define REG_CKG_VIVA_SRC_MAC_BSPLINE_S 0
#define REG_CKG_VIVA_SRC_MAC_BSPLINE_E 3
#define REG_CKG_DISP_MFDEC ckgen00(0x1268)
#define REG_CKG_DISP_MFDEC_S 0
#define REG_CKG_DISP_MFDEC_E 3
#define REG_CKG_DISP_MFDEC_GPU_PAR_GP ckgen00(0x1268)
#define REG_CKG_DISP_MFDEC_GPU_PAR_GP_S 8
#define REG_CKG_DISP_MFDEC_GPU_PAR_GP_E 9
#define REG_CKG_DISP_MFDEC_GPU ckgen00(0x1268)
#define REG_CKG_DISP_MFDEC_GPU_S 10
#define REG_CKG_DISP_MFDEC_GPU_E 11
#define REG_CKG_DISP_MFDEC_SCNR ckgen00(0x126c)
#define REG_CKG_DISP_MFDEC_SCNR_S 0
#define REG_CKG_DISP_MFDEC_SCNR_E 1
#define REG_CKG_GPD ckgen00(0x1270)
#define REG_CKG_GPD_S 0
#define REG_CKG_GPD_E 3
#define REG_CKG_GPD_MHEG5 ckgen00(0x1270)
#define REG_CKG_GPD_MHEG5_S 8
#define REG_CKG_GPD_MHEG5_E 9
#define REG_CKG_NJPD ckgen00(0x1278)
#define REG_CKG_NJPD_S 0
#define REG_CKG_NJPD_E 3
#define REG_CKG_NJPD_TSP ckgen00(0x1278)
#define REG_CKG_NJPD_TSP_S 8
#define REG_CKG_NJPD_TSP_E 9
#define REG_CKG_VDEC_LAE_MSB_SLOW ckgen00(0x1284)
#define REG_CKG_VDEC_LAE_MSB_SLOW_S 0
#define REG_CKG_VDEC_LAE_MSB_SLOW_E 2
#define REG_CKG_VDEC_LAE_SLOW ckgen00(0x1288)
#define REG_CKG_VDEC_LAE_SLOW_S 0
#define REG_CKG_VDEC_LAE_SLOW_E 4
#define REG_CKG_VDEC_BUS_VDEC_SOC ckgen00(0x1288)
#define REG_CKG_VDEC_BUS_VDEC_SOC_S 8
#define REG_CKG_VDEC_BUS_VDEC_SOC_E 9
#define REG_CKG_VDEC_BUS_VDEC_CORE0 ckgen00(0x1288)
#define REG_CKG_VDEC_BUS_VDEC_CORE0_S 10
#define REG_CKG_VDEC_BUS_VDEC_CORE0_E 11
#define REG_CKG_VDEC_SYS ckgen00(0x1290)
#define REG_CKG_VDEC_SYS_S 0
#define REG_CKG_VDEC_SYS_E 2
#define REG_CKG_VDEC_SYS_VDEC_SOC ckgen00(0x1290)
#define REG_CKG_VDEC_SYS_VDEC_SOC_S 8
#define REG_CKG_VDEC_SYS_VDEC_SOC_E 9
#define REG_CKG_VDEC_SYS_VDEC_CORE0 ckgen00(0x1290)
#define REG_CKG_VDEC_SYS_VDEC_CORE0_S 10
#define REG_CKG_VDEC_SYS_VDEC_CORE0_E 11
#define REG_CKG_VDEC_SYS_SLOW ckgen00(0x1298)
#define REG_CKG_VDEC_SYS_SLOW_S 0
#define REG_CKG_VDEC_SYS_SLOW_E 3
#define REG_CKG_VDEC_LAT0 ckgen00(0x12a0)
#define REG_CKG_VDEC_LAT0_S 0
#define REG_CKG_VDEC_LAT0_E 1
#define REG_CKG_GCE_F26M ckgen00(0x12b0)
#define REG_CKG_GCE_F26M_S 0
#define REG_CKG_GCE_F26M_E 1
#define REG_CKG_XTAL_24M_VDEC_CORE0 ckgen00(0x12b8)
#define REG_CKG_XTAL_24M_VDEC_CORE0_S 0
#define REG_CKG_XTAL_24M_VDEC_CORE0_E 1
#define REG_SW_EN_CALC2CALC_MCUSYS ckgen00(0x1400)
#define REG_SW_EN_CALC2CALC_MCUSYS_S 1
#define REG_SW_EN_CALC2CALC_MCUSYS_E 1
#define REG_SW_EN_GPU2GPU_PAR_GP ckgen00(0x1444)
#define REG_SW_EN_GPU2GPU_PAR_GP_S 0
#define REG_SW_EN_GPU2GPU_PAR_GP_E 0
#define REG_SW_EN_GPU_DFS2GPU_PAR_GP ckgen00(0x1444)
#define REG_SW_EN_GPU_DFS2GPU_PAR_GP_S 1
#define REG_SW_EN_GPU_DFS2GPU_PAR_GP_E 1
#define REG_SW_EN_SC2SHADER ckgen00(0x1448)
#define REG_SW_EN_SC2SHADER_S 0
#define REG_SW_EN_SC2SHADER_E 0
#define REG_SW_EN_XTAL_12M2MET ckgen00(0x144c)
#define REG_SW_EN_XTAL_12M2MET_S 0
#define REG_SW_EN_XTAL_12M2MET_E 0
#define REG_SW_EN_XTAL_24M2SYSCOUNT ckgen00(0x1450)
#define REG_SW_EN_XTAL_24M2SYSCOUNT_S 1
#define REG_SW_EN_XTAL_24M2SYSCOUNT_E 1
#define REG_SW_EN_XTAL_24M2XTAL ckgen00(0x1450)
#define REG_SW_EN_XTAL_24M2XTAL_S 2
#define REG_SW_EN_XTAL_24M2XTAL_E 2
#define REG_SW_EN_BUS_NODIE2AIATOP ckgen00(0x1460)
#define REG_SW_EN_BUS_NODIE2AIATOP_S 0
#define REG_SW_EN_BUS_NODIE2AIATOP_E 0
#define REG_SW_EN_BUS_NODIE2SMI ckgen00(0x1460)
#define REG_SW_EN_BUS_NODIE2SMI_S 1
#define REG_SW_EN_BUS_NODIE2SMI_E 1
#define REG_SW_EN_XTAL_24M2AIATOP ckgen00(0x1464)
#define REG_SW_EN_XTAL_24M2AIATOP_S 0
#define REG_SW_EN_XTAL_24M2AIATOP_E 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHC2DRAMC0 ckgen00(0x146c)
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHC2DRAMC0_S 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHC2DRAMC0_E 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0 ckgen00(0x1474)
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0_S 0
#define REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0_E 0
#define REG_SW_EN_XTAL_24M2DRAMC0 ckgen00(0x148c)
#define REG_SW_EN_XTAL_24M2DRAMC0_S 0
#define REG_SW_EN_XTAL_24M2DRAMC0_E 0
#define REG_SW_EN_EMI0_DEB2IP_WRAP ckgen00(0x1498)
#define REG_SW_EN_EMI0_DEB2IP_WRAP_S 0
#define REG_SW_EN_EMI0_DEB2IP_WRAP_E 0
#define REG_SW_EN_EMI02IP_WRAP ckgen00(0x149c)
#define REG_SW_EN_EMI02IP_WRAP_S 0
#define REG_SW_EN_EMI02IP_WRAP_E 0
#define REG_SW_EN_EMI1_DEB2IP_WRAP ckgen00(0x14a0)
#define REG_SW_EN_EMI1_DEB2IP_WRAP_S 0
#define REG_SW_EN_EMI1_DEB2IP_WRAP_E 0
#define REG_SW_EN_EMI12IP_WRAP ckgen00(0x14a4)
#define REG_SW_EN_EMI12IP_WRAP_S 0
#define REG_SW_EN_EMI12IP_WRAP_E 0
#define REG_SW_EN_EMI2_DEB2IP_WRAP ckgen00(0x14a8)
#define REG_SW_EN_EMI2_DEB2IP_WRAP_S 0
#define REG_SW_EN_EMI2_DEB2IP_WRAP_E 0
#define REG_SW_EN_EMI22IP_WRAP ckgen00(0x14ac)
#define REG_SW_EN_EMI22IP_WRAP_S 0
#define REG_SW_EN_EMI22IP_WRAP_E 0
#define REG_SW_EN_EMI22XPU ckgen00(0x14ac)
#define REG_SW_EN_EMI22XPU_S 1
#define REG_SW_EN_EMI22XPU_E 1
#define REG_SW_EN_IP_WRAP2IP_WRAP ckgen00(0x14b0)
#define REG_SW_EN_IP_WRAP2IP_WRAP_S 0
#define REG_SW_EN_IP_WRAP2IP_WRAP_E 0
#define REG_SW_EN_XTAL_12M2IP_WRAP ckgen00(0x14b4)
#define REG_SW_EN_XTAL_12M2IP_WRAP_S 0
#define REG_SW_EN_XTAL_12M2IP_WRAP_E 0
#define REG_SW_EN_XTAL_24M2IP_WRAP ckgen00(0x14b8)
#define REG_SW_EN_XTAL_24M2IP_WRAP_S 0
#define REG_SW_EN_XTAL_24M2IP_WRAP_E 0
#define REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0 ckgen00(0x14bc)
#define REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0_S 0
#define REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0_E 0
#define REG_SW_EN_SMI2AIA_SMI ckgen00(0x14e4)
#define REG_SW_EN_SMI2AIA_SMI_S 0
#define REG_SW_EN_SMI2AIA_SMI_E 0
#define REG_SW_EN_SMI2AUDIO_R2 ckgen00(0x14e4)
#define REG_SW_EN_SMI2AUDIO_R2_S 1
#define REG_SW_EN_SMI2AUDIO_R2_E 1
#define REG_SW_EN_SMI2CMDQ ckgen00(0x14e4)
#define REG_SW_EN_SMI2CMDQ_S 2
#define REG_SW_EN_SMI2CMDQ_E 2
#define REG_SW_EN_SMI2CORE0 ckgen00(0x14e4)
#define REG_SW_EN_SMI2CORE0_S 3
#define REG_SW_EN_SMI2CORE0_E 3
#define REG_SW_EN_SMI2SMI_DEMOD0 ckgen00(0x14e4)
#define REG_SW_EN_SMI2SMI_DEMOD0_S 6
#define REG_SW_EN_SMI2SMI_DEMOD0_E 6
#define REG_SW_EN_SMI2DSCRMB ckgen00(0x14e4)
#define REG_SW_EN_SMI2DSCRMB_S 7
#define REG_SW_EN_SMI2DSCRMB_E 7
#define REG_SW_EN_SMI2GE ckgen00(0x14e4)
#define REG_SW_EN_SMI2GE_S 11
#define REG_SW_EN_SMI2GE_E 11
#define REG_SW_EN_SMI2GMAC ckgen00(0x14e4)
#define REG_SW_EN_SMI2GMAC_S 12
#define REG_SW_EN_SMI2GMAC_E 12
#define REG_SW_EN_SMI2GPD ckgen00(0x14e4)
#define REG_SW_EN_SMI2GPD_S 13
#define REG_SW_EN_SMI2GPD_E 13
#define REG_SW_EN_SMI2RV55FRC_SMI ckgen00(0x14e4)
#define REG_SW_EN_SMI2RV55FRC_SMI_S 14
#define REG_SW_EN_SMI2RV55FRC_SMI_E 14
#define REG_SW_EN_SMI2JPD ckgen00(0x14e4)
#define REG_SW_EN_SMI2JPD_S 15
#define REG_SW_EN_SMI2JPD_E 15
#define REG_SW_EN_SMI2MAC ckgen00(0x14e8)
#define REG_SW_EN_SMI2MAC_S 0
#define REG_SW_EN_SMI2MAC_E 0
#define REG_SW_EN_SMI2MCU_BDMA ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_BDMA_S 1
#define REG_SW_EN_SMI2MCU_BDMA_E 1
#define REG_SW_EN_SMI2MCU_DEMURA ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_DEMURA_S 2
#define REG_SW_EN_SMI2MCU_DEMURA_E 2
#define REG_SW_EN_SMI2MCU_FUART ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_FUART_S 3
#define REG_SW_EN_SMI2MCU_FUART_E 3
#define REG_SW_EN_SMI2MCU_M2MCU ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_M2MCU_S 4
#define REG_SW_EN_SMI2MCU_M2MCU_E 4
#define REG_SW_EN_SMI2MCU_MIIC0 ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_MIIC0_S 5
#define REG_SW_EN_SMI2MCU_MIIC0_E 5
#define REG_SW_EN_SMI2MCU_MIIC1 ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_MIIC1_S 6
#define REG_SW_EN_SMI2MCU_MIIC1_E 6
#define REG_SW_EN_SMI2MCU_MIIC2 ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_MIIC2_S 7
#define REG_SW_EN_SMI2MCU_MIIC2_E 7
#define REG_SW_EN_SMI2MCU_MIIC3 ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_MIIC3_S 8
#define REG_SW_EN_SMI2MCU_MIIC3_E 8
#define REG_SW_EN_SMI2MCU_XD2MIU ckgen00(0x14e8)
#define REG_SW_EN_SMI2MCU_XD2MIU_S 9
#define REG_SW_EN_SMI2MCU_XD2MIU_E 9
#define REG_SW_EN_SMI2MHEG5_SMI ckgen00(0x14e8)
#define REG_SW_EN_SMI2MHEG5_SMI_S 10
#define REG_SW_EN_SMI2MHEG5_SMI_E 10
#define REG_SW_EN_SMI2RV55FRC ckgen00(0x14e8)
#define REG_SW_EN_SMI2RV55FRC_S 12
#define REG_SW_EN_SMI2RV55FRC_E 12
#define REG_SW_EN_SMI2RV55PQU ckgen00(0x14e8)
#define REG_SW_EN_SMI2RV55PQU_S 13
#define REG_SW_EN_SMI2RV55PQU_E 13
#define REG_SW_EN_SMI2SCACE ckgen00(0x14e8)
#define REG_SW_EN_SMI2SCACE_S 14
#define REG_SW_EN_SMI2SCACE_E 14
#define REG_SW_EN_SMI2SCDV ckgen00(0x14e8)
#define REG_SW_EN_SMI2SCDV_S 15
#define REG_SW_EN_SMI2SCDV_E 15
#define REG_SW_EN_SMI2SCIP ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCIP_S 0
#define REG_SW_EN_SMI2SCIP_E 0
#define REG_SW_EN_SMI2SCM ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCM_S 1
#define REG_SW_EN_SMI2SCM_E 1
#define REG_SW_EN_SMI2SCMO ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCMO_S 2
#define REG_SW_EN_SMI2SCMO_E 2
#define REG_SW_EN_SMI2SCMW ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCMW_S 3
#define REG_SW_EN_SMI2SCMW_E 3
#define REG_SW_EN_SMI2SCNR ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCNR_S 4
#define REG_SW_EN_SMI2SCNR_E 4
#define REG_SW_EN_SMI2SCPQ ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCPQ_S 5
#define REG_SW_EN_SMI2SCPQ_E 5
#define REG_SW_EN_SMI2SCSCL ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCSCL_S 6
#define REG_SW_EN_SMI2SCSCL_E 6
#define REG_SW_EN_SMI2SCSR ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCSR_S 7
#define REG_SW_EN_SMI2SCSR_E 7
#define REG_SW_EN_SMI2SCTCON ckgen00(0x14ec)
#define REG_SW_EN_SMI2SCTCON_S 8
#define REG_SW_EN_SMI2SCTCON_E 8
#define REG_SW_EN_SMI2SMI ckgen00(0x14ec)
#define REG_SW_EN_SMI2SMI_S 9
#define REG_SW_EN_SMI2SMI_E 9
#define REG_SW_EN_SMI2SOC ckgen00(0x14ec)
#define REG_SW_EN_SMI2SOC_S 10
#define REG_SW_EN_SMI2SOC_E 10
#define REG_SW_EN_SMI2SSUSB ckgen00(0x14ec)
#define REG_SW_EN_SMI2SSUSB_S 11
#define REG_SW_EN_SMI2SSUSB_E 11
#define REG_SW_EN_SMI2TSO ckgen00(0x14ec)
#define REG_SW_EN_SMI2TSO_S 12
#define REG_SW_EN_SMI2TSO_E 12
#define REG_SW_EN_SMI2TSO2 ckgen00(0x14ec)
#define REG_SW_EN_SMI2TSO2_S 13
#define REG_SW_EN_SMI2TSO2_E 13
#define REG_SW_EN_SMI2TSP ckgen00(0x14ec)
#define REG_SW_EN_SMI2TSP_S 14
#define REG_SW_EN_SMI2TSP_E 14
#define REG_SW_EN_SMI2VD ckgen00(0x14ec)
#define REG_SW_EN_SMI2VD_S 15
#define REG_SW_EN_SMI2VD_E 15
#define REG_SW_EN_SMI2VD_PES_PARSER ckgen00(0x14f0)
#define REG_SW_EN_SMI2VD_PES_PARSER_S 0
#define REG_SW_EN_SMI2VD_PES_PARSER_E 0
#define REG_SW_EN_SMI2SMI_LARB_SCMW ckgen00(0x14f0)
#define REG_SW_EN_SMI2SMI_LARB_SCMW_S 1
#define REG_SW_EN_SMI2SMI_LARB_SCMW_E 1
#define REG_SW_EN_SMI2LARB_TSP ckgen00(0x14f0)
#define REG_SW_EN_SMI2LARB_TSP_S 2
#define REG_SW_EN_SMI2LARB_TSP_E 2
#define REG_SW_EN_SMI_AESDMA2DSCRMB ckgen00(0x14f0)
#define REG_SW_EN_SMI_AESDMA2DSCRMB_S 3
#define REG_SW_EN_SMI_AESDMA2DSCRMB_E 3
#define REG_SW_EN_SMI_TSP2TSP ckgen00(0x14f0)
#define REG_SW_EN_SMI_TSP2TSP_S 4
#define REG_SW_EN_SMI_TSP2TSP_E 4
#define REG_SW_EN_SMI_FCIE2FCIE ckgen00(0x14f0)
#define REG_SW_EN_SMI_FCIE2FCIE_S 5
#define REG_SW_EN_SMI_FCIE2FCIE_E 5
#define REG_SW_EN_SMI_UHC2UHC ckgen00(0x14f0)
#define REG_SW_EN_SMI_UHC2UHC_S 6
#define REG_SW_EN_SMI_UHC2UHC_E 6
#define REG_SW_EN_VIVA_SMI2SMI ckgen00(0x14f0)
#define REG_SW_EN_VIVA_SMI2SMI_S 7
#define REG_SW_EN_VIVA_SMI2SMI_E 7
#define REG_SW_EN_SMI2DEMOD0 ckgen00(0x14f0)
#define REG_SW_EN_SMI2DEMOD0_S 8
#define REG_SW_EN_SMI2DEMOD0_E 8
#define REG_SW_EN_SMI2DEMOD0_DVBTM ckgen00(0x14f0)
#define REG_SW_EN_SMI2DEMOD0_DVBTM_S 9
#define REG_SW_EN_SMI2DEMOD0_DVBTM_E 9
#define REG_SW_EN_SMI2DEMOD0_ISDBT ckgen00(0x14f0)
#define REG_SW_EN_SMI2DEMOD0_ISDBT_S 10
#define REG_SW_EN_SMI2DEMOD0_ISDBT_E 10
#define REG_SW_EN_SMI2DEMOD0_DTMB ckgen00(0x14f0)
#define REG_SW_EN_SMI2DEMOD0_DTMB_S 11
#define REG_SW_EN_SMI2DEMOD0_DTMB_E 11
#define REG_SW_EN_SMI2DEMOD0_ADC_DUMP ckgen00(0x14f0)
#define REG_SW_EN_SMI2DEMOD0_ADC_DUMP_S 12
#define REG_SW_EN_SMI2DEMOD0_ADC_DUMP_E 12
#define REG_SW_EN_SMI2MCU_MSPI0 ckgen00(0x14f0)
#define REG_SW_EN_SMI2MCU_MSPI0_S 13
#define REG_SW_EN_SMI2MCU_MSPI0_E 13
#define REG_SW_EN_SMI2MCU_MSPI1 ckgen00(0x14f0)
#define REG_SW_EN_SMI2MCU_MSPI1_S 14
#define REG_SW_EN_SMI2MCU_MSPI1_E 14
#define REG_SW_EN_SMI2MCU_MSPI2 ckgen00(0x14f0)
#define REG_SW_EN_SMI2MCU_MSPI2_S 15
#define REG_SW_EN_SMI2MCU_MSPI2_E 15
#define REG_SW_EN_SMI2MCU_MSPI3 ckgen00(0x14f4)
#define REG_SW_EN_SMI2MCU_MSPI3_S 0
#define REG_SW_EN_SMI2MCU_MSPI3_E 0
#define REG_SW_EN_SMI2MCU_MSPI4 ckgen00(0x14f4)
#define REG_SW_EN_SMI2MCU_MSPI4_S 1
#define REG_SW_EN_SMI2MCU_MSPI4_E 1
#define REG_SW_EN_SMI2MCU_MSPI5 ckgen00(0x14f4)
#define REG_SW_EN_SMI2MCU_MSPI5_S 2
#define REG_SW_EN_SMI2MCU_MSPI5_E 2
#define REG_SW_EN_SMI2MCU_MSPI6 ckgen00(0x14f4)
#define REG_SW_EN_SMI2MCU_MSPI6_S 3
#define REG_SW_EN_SMI2MCU_MSPI6_E 3
#define REG_SW_EN_SMI2MCU_MSPI7 ckgen00(0x14f4)
#define REG_SW_EN_SMI2MCU_MSPI7_S 4
#define REG_SW_EN_SMI2MCU_MSPI7_E 4
#define REG_SW_EN_SMI2MCU_MSPI_CILINK ckgen00(0x14f4)
#define REG_SW_EN_SMI2MCU_MSPI_CILINK_S 5
#define REG_SW_EN_SMI2MCU_MSPI_CILINK_E 5
#define REG_SW_EN_SMI2PEXTP ckgen00(0x14f4)
#define REG_SW_EN_SMI2PEXTP_S 6
#define REG_SW_EN_SMI2PEXTP_E 6
#define REG_SW_EN_SMI2UFS ckgen00(0x14f4)
#define REG_SW_EN_SMI2UFS_S 7
#define REG_SW_EN_SMI2UFS_E 7
#define REG_SW_EN_SMI2SCDISP ckgen00(0x14f4)
#define REG_SW_EN_SMI2SCDISP_S 8
#define REG_SW_EN_SMI2SCDISP_E 8
#define REG_SW_EN_VIVA_SMI2SMI_BRG ckgen00(0x14f4)
#define REG_SW_EN_VIVA_SMI2SMI_BRG_S 9
#define REG_SW_EN_VIVA_SMI2SMI_BRG_E 9
#define REG_SW_EN_SMI2FRCCORE1 ckgen00(0x14f4)
#define REG_SW_EN_SMI2FRCCORE1_S 10
#define REG_SW_EN_SMI2FRCCORE1_E 10
#define REG_SW_EN_SMI2FRCCORE2 ckgen00(0x14f4)
#define REG_SW_EN_SMI2FRCCORE2_S 11
#define REG_SW_EN_SMI2FRCCORE2_E 11
#define REG_SW_EN_SMI2FRCCORE3 ckgen00(0x14f4)
#define REG_SW_EN_SMI2FRCCORE3_S 12
#define REG_SW_EN_SMI2FRCCORE3_E 12
#define REG_SW_EN_SMI2FRCMISC ckgen00(0x14f4)
#define REG_SW_EN_SMI2FRCMISC_S 13
#define REG_SW_EN_SMI2FRCMISC_E 13
#define REG_SW_EN_SMI_SSUSB2SSUSB ckgen00(0x14f4)
#define REG_SW_EN_SMI_SSUSB2SSUSB_S 14
#define REG_SW_EN_SMI_SSUSB2SSUSB_E 14
#define REG_SW_EN_SMI2RV55PQU_SMI ckgen00(0x14f4)
#define REG_SW_EN_SMI2RV55PQU_SMI_S 15
#define REG_SW_EN_SMI2RV55PQU_SMI_E 15
#define REG_SW_EN_SMI2SMI_FRCCORE1 ckgen00(0x14f8)
#define REG_SW_EN_SMI2SMI_FRCCORE1_S 0
#define REG_SW_EN_SMI2SMI_FRCCORE1_E 0
#define REG_SW_EN_SMI2GCE ckgen00(0x14f8)
#define REG_SW_EN_SMI2GCE_S 1
#define REG_SW_EN_SMI2GCE_E 1
#define REG_SW_EN_IMI2SHARE_SRAM_IMI ckgen00(0x1524)
#define REG_SW_EN_IMI2SHARE_SRAM_IMI_S 0
#define REG_SW_EN_IMI2SHARE_SRAM_IMI_E 0
#define REG_SW_EN_IMI2UFS ckgen00(0x1524)
#define REG_SW_EN_IMI2UFS_S 1
#define REG_SW_EN_IMI2UFS_E 1
#define REG_SW_EN_IMI2TSP ckgen00(0x1524)
#define REG_SW_EN_IMI2TSP_S 2
#define REG_SW_EN_IMI2TSP_E 2
#define REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP_S 0
#define REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP_E 0
#define REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY_S 2
#define REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY_E 2
#define REG_SW_EN_XTAL_12M2MCU_BDMA ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_BDMA_S 3
#define REG_SW_EN_XTAL_12M2MCU_BDMA_E 3
#define REG_SW_EN_XTAL_12M2MCU_DEMURA ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_DEMURA_S 4
#define REG_SW_EN_XTAL_12M2MCU_DEMURA_E 4
#define REG_SW_EN_XTAL_12M2MCU_FUART ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_FUART_S 5
#define REG_SW_EN_XTAL_12M2MCU_FUART_E 5
#define REG_SW_EN_XTAL_12M2MCU_M2MCU ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_M2MCU_S 6
#define REG_SW_EN_XTAL_12M2MCU_M2MCU_E 6
#define REG_SW_EN_XTAL_12M2MCU_M2RIU ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_M2RIU_S 7
#define REG_SW_EN_XTAL_12M2MCU_M2RIU_E 7
#define REG_SW_EN_XTAL_12M2MCU_MCUIF ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_MCUIF_S 8
#define REG_SW_EN_XTAL_12M2MCU_MCUIF_E 8
#define REG_SW_EN_XTAL_12M2MCU_MIIC0 ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_MIIC0_S 9
#define REG_SW_EN_XTAL_12M2MCU_MIIC0_E 9
#define REG_SW_EN_XTAL_12M2MCU_MIIC1 ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_MIIC1_S 10
#define REG_SW_EN_XTAL_12M2MCU_MIIC1_E 10
#define REG_SW_EN_XTAL_12M2MCU_MIIC2 ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_MIIC2_S 11
#define REG_SW_EN_XTAL_12M2MCU_MIIC2_E 11
#define REG_SW_EN_XTAL_12M2MCU_MIIC3 ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_MIIC3_S 12
#define REG_SW_EN_XTAL_12M2MCU_MIIC3_E 12
#define REG_SW_EN_XTAL_12M2MCU_XD2MIU ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2MCU_XD2MIU_S 13
#define REG_SW_EN_XTAL_12M2MCU_XD2MIU_E 13
#define REG_SW_EN_XTAL_12M2PAD_TOP ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2PAD_TOP_S 14
#define REG_SW_EN_XTAL_12M2PAD_TOP_E 14
#define REG_SW_EN_XTAL_12M2PREARB2PMRIU ckgen00(0x153c)
#define REG_SW_EN_XTAL_12M2PREARB2PMRIU_S 15
#define REG_SW_EN_XTAL_12M2PREARB2PMRIU_E 15
#define REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP_S 0
#define REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP_E 0
#define REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM_S 1
#define REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM_E 1
#define REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE_S 2
#define REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE_E 2
#define REG_SW_EN_XTAL_12M2TEST_CTRL ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2TEST_CTRL_S 3
#define REG_SW_EN_XTAL_12M2TEST_CTRL_E 3
#define REG_SW_EN_XTAL_12M2VD ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2VD_S 4
#define REG_SW_EN_XTAL_12M2VD_E 4
#define REG_SW_EN_XTAL_12M2MCU_MSPI0 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI0_S 5
#define REG_SW_EN_XTAL_12M2MCU_MSPI0_E 5
#define REG_SW_EN_XTAL_12M2MCU_MSPI1 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI1_S 6
#define REG_SW_EN_XTAL_12M2MCU_MSPI1_E 6
#define REG_SW_EN_XTAL_12M2MCU_MSPI2 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI2_S 7
#define REG_SW_EN_XTAL_12M2MCU_MSPI2_E 7
#define REG_SW_EN_XTAL_12M2MCU_MSPI3 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI3_S 8
#define REG_SW_EN_XTAL_12M2MCU_MSPI3_E 8
#define REG_SW_EN_XTAL_12M2MCU_MSPI4 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI4_S 9
#define REG_SW_EN_XTAL_12M2MCU_MSPI4_E 9
#define REG_SW_EN_XTAL_12M2MCU_MSPI5 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI5_S 10
#define REG_SW_EN_XTAL_12M2MCU_MSPI5_E 10
#define REG_SW_EN_XTAL_12M2MCU_MSPI6 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI6_S 11
#define REG_SW_EN_XTAL_12M2MCU_MSPI6_E 11
#define REG_SW_EN_XTAL_12M2MCU_MSPI7 ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI7_S 12
#define REG_SW_EN_XTAL_12M2MCU_MSPI7_E 12
#define REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK ckgen00(0x1540)
#define REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK_S 13
#define REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK_E 13
#define REG_SW_EN_XTAL_24M2DMD_RST_CTRL ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2DMD_RST_CTRL_S 0
#define REG_SW_EN_XTAL_24M2DMD_RST_CTRL_E 0
#define REG_SW_EN_XTAL_24M2DSCRMB ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2DSCRMB_S 1
#define REG_SW_EN_XTAL_24M2DSCRMB_E 1
#define REG_SW_EN_XTAL_24M2GMAC ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2GMAC_S 2
#define REG_SW_EN_XTAL_24M2GMAC_E 2
#define REG_SW_EN_XTAL_24M2PEXTP ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2PEXTP_S 4
#define REG_SW_EN_XTAL_24M2PEXTP_E 4
#define REG_SW_EN_XTAL_24M2SSUSB ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2SSUSB_S 5
#define REG_SW_EN_XTAL_24M2SSUSB_E 5
#define REG_SW_EN_XTAL_24M2TOP ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2TOP_S 6
#define REG_SW_EN_XTAL_24M2TOP_E 6
#define REG_SW_EN_XTAL_24M2USB20 ckgen00(0x1558)
#define REG_SW_EN_XTAL_24M2USB20_S 8
#define REG_SW_EN_XTAL_24M2USB20_E 8
#define REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA ckgen00(0x1578)
#define REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA_S 0
#define REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA ckgen00(0x157c)
#define REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA ckgen00(0x1580)
#define REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA_E 0
#define REG_SW_EN_ACIFIR2DEMOD0 ckgen00(0x1584)
#define REG_SW_EN_ACIFIR2DEMOD0_S 0
#define REG_SW_EN_ACIFIR2DEMOD0_E 0
#define REG_SW_EN_ADCD_I_IN2DMD_ANA ckgen00(0x1588)
#define REG_SW_EN_ADCD_I_IN2DMD_ANA_S 0
#define REG_SW_EN_ADCD_I_IN2DMD_ANA_E 0
#define REG_SW_EN_ADCD_I_OUT2DMD_ANA ckgen00(0x158c)
#define REG_SW_EN_ADCD_I_OUT2DMD_ANA_S 0
#define REG_SW_EN_ADCD_I_OUT2DMD_ANA_E 0
#define REG_SW_EN_ADCD_Q_IN2DMD_ANA ckgen00(0x1590)
#define REG_SW_EN_ADCD_Q_IN2DMD_ANA_S 0
#define REG_SW_EN_ADCD_Q_IN2DMD_ANA_E 0
#define REG_SW_EN_ADCD_Q_OUT2DMD_ANA ckgen00(0x1594)
#define REG_SW_EN_ADCD_Q_OUT2DMD_ANA_S 0
#define REG_SW_EN_ADCD_Q_OUT2DMD_ANA_E 0
#define REG_SW_EN_ADCD2DEMOD0 ckgen00(0x1598)
#define REG_SW_EN_ADCD2DEMOD0_S 0
#define REG_SW_EN_ADCD2DEMOD0_E 0
#define REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0 ckgen00(0x159c)
#define REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0_S 0
#define REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0_E 0
#define REG_SW_EN_ATSC_CE252DEMOD0 ckgen00(0x15a0)
#define REG_SW_EN_ATSC_CE252DEMOD0_S 0
#define REG_SW_EN_ATSC_CE252DEMOD0_E 0
#define REG_SW_EN_ATSC_EQ252DEMOD0 ckgen00(0x15a4)
#define REG_SW_EN_ATSC_EQ252DEMOD0_S 0
#define REG_SW_EN_ATSC_EQ252DEMOD0_E 0
#define REG_SW_EN_ATSC200_PH12DEMOD0 ckgen00(0x15a8)
#define REG_SW_EN_ATSC200_PH12DEMOD0_S 0
#define REG_SW_EN_ATSC200_PH12DEMOD0_E 0
#define REG_SW_EN_ATSC200_PH32DEMOD0 ckgen00(0x15ac)
#define REG_SW_EN_ATSC200_PH32DEMOD0_S 0
#define REG_SW_EN_ATSC200_PH32DEMOD0_E 0
#define REG_SW_EN_ATSC252DEMOD0 ckgen00(0x15b0)
#define REG_SW_EN_ATSC252DEMOD0_S 0
#define REG_SW_EN_ATSC252DEMOD0_E 0
#define REG_SW_EN_ATSC4002DEMOD0 ckgen00(0x15b4)
#define REG_SW_EN_ATSC4002DEMOD0_S 0
#define REG_SW_EN_ATSC4002DEMOD0_E 0
#define REG_SW_EN_ATSC502DEMOD0 ckgen00(0x15b8)
#define REG_SW_EN_ATSC502DEMOD0_S 0
#define REG_SW_EN_ATSC502DEMOD0_E 0
#define REG_SW_EN_DEC_XTAL_I2DMD_ANA ckgen00(0x15bc)
#define REG_SW_EN_DEC_XTAL_I2DMD_ANA_S 0
#define REG_SW_EN_DEC_XTAL_I2DMD_ANA_E 0
#define REG_SW_EN_DEC_XTAL_Q2DMD_ANA ckgen00(0x15c0)
#define REG_SW_EN_DEC_XTAL_Q2DMD_ANA_S 0
#define REG_SW_EN_DEC_XTAL_Q2DMD_ANA_E 0
#define REG_SW_EN_DEINTER2DEMOD1 ckgen00(0x15c4)
#define REG_SW_EN_DEINTER2DEMOD1_S 0
#define REG_SW_EN_DEINTER2DEMOD1_E 0
#define REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV ckgen00(0x15c8)
#define REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV_S 0
#define REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV_E 0
#define REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL ckgen00(0x15cc)
#define REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMD_DMA2DEMOD0 ckgen00(0x15d0)
#define REG_SW_EN_DMD_DMA2DEMOD0_S 0
#define REG_SW_EN_DMD_DMA2DEMOD0_E 0
#define REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL ckgen00(0x15d4)
#define REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL ckgen00(0x15d8)
#define REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL ckgen00(0x15dc)
#define REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL ckgen00(0x15e0)
#define REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL ckgen00(0x15e4)
#define REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL ckgen00(0x15e8)
#define REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL ckgen00(0x15ec)
#define REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL ckgen00(0x15f0)
#define REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL ckgen00(0x15f4)
#define REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL ckgen00(0x15f8)
#define REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL ckgen00(0x15fc)
#define REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL ckgen00(0x1600)
#define REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL ckgen00(0x1604)
#define REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL ckgen00(0x1608)
#define REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL ckgen00(0x160c)
#define REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL ckgen00(0x1610)
#define REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL_S 0
#define REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL_E 0
#define REG_SW_EN_DTMB_ADC2DEMOD0 ckgen00(0x1614)
#define REG_SW_EN_DTMB_ADC2DEMOD0_S 0
#define REG_SW_EN_DTMB_ADC2DEMOD0_E 0
#define REG_SW_EN_DTMB_BCH2DEMOD0 ckgen00(0x1618)
#define REG_SW_EN_DTMB_BCH2DEMOD0_S 0
#define REG_SW_EN_DTMB_BCH2DEMOD0_E 0
#define REG_SW_EN_DTMB_BCH2DEMOD1 ckgen00(0x161c)
#define REG_SW_EN_DTMB_BCH2DEMOD1_S 0
#define REG_SW_EN_DTMB_BCH2DEMOD1_E 0
#define REG_SW_EN_DTMB_EQ0P25X2DEMOD0 ckgen00(0x1620)
#define REG_SW_EN_DTMB_EQ0P25X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ0P25X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ0P5X2DEMOD0 ckgen00(0x1624)
#define REG_SW_EN_DTMB_EQ0P5X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ0P5X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ1X2DEMOD0 ckgen00(0x1628)
#define REG_SW_EN_DTMB_EQ1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0 ckgen00(0x162c)
#define REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0 ckgen00(0x1630)
#define REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0 ckgen00(0x1634)
#define REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DTMB_EQ2X2DEMOD0 ckgen00(0x1638)
#define REG_SW_EN_DTMB_EQ2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_EQ2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0 ckgen00(0x163c)
#define REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0 ckgen00(0x1640)
#define REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0 ckgen00(0x1644)
#define REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0 ckgen00(0x1648)
#define REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER12X2DEMOD0 ckgen00(0x164c)
#define REG_SW_EN_DTMB_INNER12X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER12X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0 ckgen00(0x1650)
#define REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER1X2DEMOD0 ckgen00(0x1654)
#define REG_SW_EN_DTMB_INNER1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0 ckgen00(0x1658)
#define REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER24X2DEMOD0 ckgen00(0x165c)
#define REG_SW_EN_DTMB_INNER24X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER24X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0 ckgen00(0x1660)
#define REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0 ckgen00(0x1664)
#define REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER2X2DEMOD0 ckgen00(0x1668)
#define REG_SW_EN_DTMB_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0 ckgen00(0x166c)
#define REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0 ckgen00(0x1670)
#define REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER4X2DEMOD0 ckgen00(0x1674)
#define REG_SW_EN_DTMB_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER6X2DEMOD0 ckgen00(0x1678)
#define REG_SW_EN_DTMB_INNER6X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER6X2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0 ckgen00(0x167c)
#define REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0_E 0
#define REG_SW_EN_DTMB_INNER8X2DEMOD0 ckgen00(0x1680)
#define REG_SW_EN_DTMB_INNER8X2DEMOD0_S 0
#define REG_SW_EN_DTMB_INNER8X2DEMOD0_E 0
#define REG_SW_EN_DTMB_LDPC2DEMOD0 ckgen00(0x1684)
#define REG_SW_EN_DTMB_LDPC2DEMOD0_S 0
#define REG_SW_EN_DTMB_LDPC2DEMOD0_E 0
#define REG_SW_EN_DTMB_LDPC2X2DEMOD0 ckgen00(0x1688)
#define REG_SW_EN_DTMB_LDPC2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_LDPC2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD0 ckgen00(0x168c)
#define REG_SW_EN_DTMB_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD1 ckgen00(0x1690)
#define REG_SW_EN_DTMB_OUTER1X2DEMOD1_S 0
#define REG_SW_EN_DTMB_OUTER1X2DEMOD1_E 0
#define REG_SW_EN_DTMB_OUTER2X2DEMOD0 ckgen00(0x1694)
#define REG_SW_EN_DTMB_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DTMB_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DTMB_OUTER8X2DEMOD0 ckgen00(0x1698)
#define REG_SW_EN_DTMB_OUTER8X2DEMOD0_S 0
#define REG_SW_EN_DTMB_OUTER8X2DEMOD0_E 0
#define REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0 ckgen00(0x169c)
#define REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0_S 0
#define REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER1X2DEMOD0 ckgen00(0x16a0)
#define REG_SW_EN_DVBS_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0 ckgen00(0x16a4)
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0 ckgen00(0x16a8)
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0 ckgen00(0x16ac)
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBS_OUTER2X2DEMOD0 ckgen00(0x16b0)
#define REG_SW_EN_DVBS_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBS_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBS2_BCH2DEMOD0 ckgen00(0x16b4)
#define REG_SW_EN_DVBS2_BCH2DEMOD0_S 0
#define REG_SW_EN_DVBS2_BCH2DEMOD0_E 0
#define REG_SW_EN_DVBS2_DEMAPPER2DEMOD1 ckgen00(0x16b8)
#define REG_SW_EN_DVBS2_DEMAPPER2DEMOD1_S 0
#define REG_SW_EN_DVBS2_DEMAPPER2DEMOD1_E 0
#define REG_SW_EN_DVBS2_DISEQC2DEMOD0 ckgen00(0x16bc)
#define REG_SW_EN_DVBS2_DISEQC2DEMOD0_S 0
#define REG_SW_EN_DVBS2_DISEQC2DEMOD0_E 0
#define REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1 ckgen00(0x16c0)
#define REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1_S 0
#define REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1_E 0
#define REG_SW_EN_DVBS2_INNER2DEMOD0 ckgen00(0x16c4)
#define REG_SW_EN_DVBS2_INNER2DEMOD0_S 0
#define REG_SW_EN_DVBS2_INNER2DEMOD0_E 0
#define REG_SW_EN_DVBS2_OPPRO2DEMOD0 ckgen00(0x16c8)
#define REG_SW_EN_DVBS2_OPPRO2DEMOD0_S 0
#define REG_SW_EN_DVBS2_OPPRO2DEMOD0_E 0
#define REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1 ckgen00(0x16cc)
#define REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1_S 0
#define REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1_E 0
#define REG_SW_EN_DVBT_INNER1X2DEMOD0 ckgen00(0x16d0)
#define REG_SW_EN_DVBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0 ckgen00(0x16d4)
#define REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0_E 0
#define REG_SW_EN_DVBT_INNER2X2DEMOD0 ckgen00(0x16d8)
#define REG_SW_EN_DVBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DVBT_INNER4X2DEMOD0 ckgen00(0x16dc)
#define REG_SW_EN_DVBT_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DVBT_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DVBT_OUTER1X2DEMOD0 ckgen00(0x16e0)
#define REG_SW_EN_DVBT_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_DVBT_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_DVBT_OUTER2X2DEMOD0 ckgen00(0x16e4)
#define REG_SW_EN_DVBT_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBT_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_DEMAPPER2DEMOD1 ckgen00(0x16e8)
#define REG_SW_EN_DVBT2_DEMAPPER2DEMOD1_S 0
#define REG_SW_EN_DVBT2_DEMAPPER2DEMOD1_E 0
#define REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1 ckgen00(0x16ec)
#define REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1_S 0
#define REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1_E 0
#define REG_SW_EN_DVBT2_INNER1X2DEMOD0 ckgen00(0x16f0)
#define REG_SW_EN_DVBT2_INNER1X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER1X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0 ckgen00(0x16f4)
#define REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER2X2DEMOD0 ckgen00(0x16f8)
#define REG_SW_EN_DVBT2_INNER2X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER2X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0 ckgen00(0x16fc)
#define REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0 ckgen00(0x1700)
#define REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0_E 0
#define REG_SW_EN_DVBT2_INNER4X2DEMOD0 ckgen00(0x1704)
#define REG_SW_EN_DVBT2_INNER4X2DEMOD0_S 0
#define REG_SW_EN_DVBT2_INNER4X2DEMOD0_E 0
#define REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1 ckgen00(0x1708)
#define REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1_S 0
#define REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1_E 0
#define REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1 ckgen00(0x170c)
#define REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1_S 0
#define REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1_E 0
#define REG_SW_EN_DVBT2_S2_BCH2DEMOD1 ckgen00(0x1710)
#define REG_SW_EN_DVBT2_S2_BCH2DEMOD1_S 0
#define REG_SW_EN_DVBT2_S2_BCH2DEMOD1_E 0
#define REG_SW_EN_DVBTC_ADC_I2DMD_ANA ckgen00(0x1718)
#define REG_SW_EN_DVBTC_ADC_I2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_I2DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC_Q2DMD_ANA ckgen00(0x1720)
#define REG_SW_EN_DVBTC_ADC_Q2DMD_ANA_S 0
#define REG_SW_EN_DVBTC_ADC_Q2DMD_ANA_E 0
#define REG_SW_EN_DVBTC_ADC2DEMOD0 ckgen00(0x1724)
#define REG_SW_EN_DVBTC_ADC2DEMOD0_S 0
#define REG_SW_EN_DVBTC_ADC2DEMOD0_E 0
#define REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0 ckgen00(0x1728)
#define REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0_S 0
#define REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0_E 0
#define REG_SW_EN_DVBTC_OUTER2X2DEMOD0 ckgen00(0x172c)
#define REG_SW_EN_DVBTC_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_DVBTC_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_DVBTC_RS2DEMOD0 ckgen00(0x1730)
#define REG_SW_EN_DVBTC_RS2DEMOD0_S 0
#define REG_SW_EN_DVBTC_RS2DEMOD0_E 0
#define REG_SW_EN_DVBTC_SRAM12DEMOD0 ckgen00(0x1734)
#define REG_SW_EN_DVBTC_SRAM12DEMOD0_S 0
#define REG_SW_EN_DVBTC_SRAM12DEMOD0_E 0
#define REG_SW_EN_DVBTC_SRAM32DEMOD0 ckgen00(0x1738)
#define REG_SW_EN_DVBTC_SRAM32DEMOD0_S 0
#define REG_SW_EN_DVBTC_SRAM32DEMOD0_E 0
#define REG_SW_EN_DVBTC_SRAM42DEMOD0 ckgen00(0x173c)
#define REG_SW_EN_DVBTC_SRAM42DEMOD0_S 0
#define REG_SW_EN_DVBTC_SRAM42DEMOD0_E 0
#define REG_SW_EN_DVBTC_TS2DEMOD0 ckgen00(0x1740)
#define REG_SW_EN_DVBTC_TS2DEMOD0_S 0
#define REG_SW_EN_DVBTC_TS2DEMOD0_E 0
#define REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0 ckgen00(0x1744)
#define REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0 ckgen00(0x1748)
#define REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0 ckgen00(0x174c)
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0 ckgen00(0x1750)
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0 ckgen00(0x1754)
#define REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0 ckgen00(0x1758)
#define REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0 ckgen00(0x175c)
#define REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0 ckgen00(0x1760)
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0 ckgen00(0x1764)
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0 ckgen00(0x1768)
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0 ckgen00(0x176c)
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0 ckgen00(0x1770)
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0 ckgen00(0x1774)
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0 ckgen00(0x1778)
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0_E 0
#define REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0 ckgen00(0x177c)
#define REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0_S 0
#define REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0 ckgen00(0x1780)
#define REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER1X2DEMOD0 ckgen00(0x1784)
#define REG_SW_EN_ISDBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0 ckgen00(0x1788)
#define REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER2X2DEMOD0 ckgen00(0x178c)
#define REG_SW_EN_ISDBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0 ckgen00(0x1790)
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0 ckgen00(0x1794)
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_INNER4X2DEMOD0 ckgen00(0x1798)
#define REG_SW_EN_ISDBT_INNER4X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_INNER4X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER_RS2DEMOD0 ckgen00(0x179c)
#define REG_SW_EN_ISDBT_OUTER_RS2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER_RS2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER12X2DEMOD0 ckgen00(0x17a0)
#define REG_SW_EN_ISDBT_OUTER12X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER12X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0 ckgen00(0x17a4)
#define REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER1X2DEMOD0 ckgen00(0x17a8)
#define REG_SW_EN_ISDBT_OUTER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER4X2DEMOD0 ckgen00(0x17ac)
#define REG_SW_EN_ISDBT_OUTER4X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER4X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0 ckgen00(0x17b0)
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0 ckgen00(0x17b4)
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0 ckgen00(0x17b8)
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0 ckgen00(0x17bc)
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0_E 0
#define REG_SW_EN_ISDBT_OUTER6X2DEMOD0 ckgen00(0x17c0)
#define REG_SW_EN_ISDBT_OUTER6X2DEMOD0_S 0
#define REG_SW_EN_ISDBT_OUTER6X2DEMOD0_E 0
#define REG_SW_EN_LDPC1X2DEMOD1 ckgen00(0x17c4)
#define REG_SW_EN_LDPC1X2DEMOD1_S 0
#define REG_SW_EN_LDPC1X2DEMOD1_E 0
#define REG_SW_EN_LDPC2X2DEMOD1 ckgen00(0x17c8)
#define REG_SW_EN_LDPC2X2DEMOD1_S 0
#define REG_SW_EN_LDPC2X2DEMOD1_E 0
#define REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1 ckgen00(0x17e0)
#define REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1_E 0
#define REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1 ckgen00(0x17e4)
#define REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1_E 0
#define REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1 ckgen00(0x17e8)
#define REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1_S 0
#define REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1_E 0
#define REG_SW_EN_SRAM_SHARE_00_02DEMOD0 ckgen00(0x17ec)
#define REG_SW_EN_SRAM_SHARE_00_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_00_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_00_12DEMOD0 ckgen00(0x17f0)
#define REG_SW_EN_SRAM_SHARE_00_12DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_00_12DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_01_02DEMOD0 ckgen00(0x17f4)
#define REG_SW_EN_SRAM_SHARE_01_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_01_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_02_02DEMOD0 ckgen00(0x17f8)
#define REG_SW_EN_SRAM_SHARE_02_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_02_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_03_02DEMOD0 ckgen00(0x17fc)
#define REG_SW_EN_SRAM_SHARE_03_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_03_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_03_12DEMOD0 ckgen00(0x1800)
#define REG_SW_EN_SRAM_SHARE_03_12DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_03_12DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_04_02DEMOD0 ckgen00(0x1804)
#define REG_SW_EN_SRAM_SHARE_04_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_04_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_04_12DEMOD0 ckgen00(0x1808)
#define REG_SW_EN_SRAM_SHARE_04_12DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_04_12DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_052DEMOD0 ckgen00(0x180c)
#define REG_SW_EN_SRAM_SHARE_052DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_052DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_062DEMOD0 ckgen00(0x1810)
#define REG_SW_EN_SRAM_SHARE_062DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_062DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_072DEMOD0 ckgen00(0x1814)
#define REG_SW_EN_SRAM_SHARE_072DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_072DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_082DEMOD0 ckgen00(0x1818)
#define REG_SW_EN_SRAM_SHARE_082DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_082DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_092DEMOD0 ckgen00(0x181c)
#define REG_SW_EN_SRAM_SHARE_092DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_092DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_102DEMOD0 ckgen00(0x1820)
#define REG_SW_EN_SRAM_SHARE_102DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_102DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_112DEMOD0 ckgen00(0x1824)
#define REG_SW_EN_SRAM_SHARE_112DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_112DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_122DEMOD0 ckgen00(0x1828)
#define REG_SW_EN_SRAM_SHARE_122DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_122DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_132DEMOD0 ckgen00(0x182c)
#define REG_SW_EN_SRAM_SHARE_132DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_132DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_14_R2DEMOD0 ckgen00(0x1830)
#define REG_SW_EN_SRAM_SHARE_14_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_14_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_14_W2DEMOD0 ckgen00(0x1834)
#define REG_SW_EN_SRAM_SHARE_14_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_14_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_15_R2DEMOD0 ckgen00(0x1838)
#define REG_SW_EN_SRAM_SHARE_15_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_15_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_15_W2DEMOD0 ckgen00(0x183c)
#define REG_SW_EN_SRAM_SHARE_15_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_15_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_162DEMOD0 ckgen00(0x1840)
#define REG_SW_EN_SRAM_SHARE_162DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_162DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_182DEMOD0 ckgen00(0x1844)
#define REG_SW_EN_SRAM_SHARE_182DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_182DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_192DEMOD0 ckgen00(0x1848)
#define REG_SW_EN_SRAM_SHARE_192DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_192DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_202DEMOD0 ckgen00(0x184c)
#define REG_SW_EN_SRAM_SHARE_202DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_202DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_212DEMOD0 ckgen00(0x1850)
#define REG_SW_EN_SRAM_SHARE_212DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_212DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_222DEMOD0 ckgen00(0x1854)
#define REG_SW_EN_SRAM_SHARE_222DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_222DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_232DEMOD0 ckgen00(0x1858)
#define REG_SW_EN_SRAM_SHARE_232DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_232DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_242DEMOD0 ckgen00(0x185c)
#define REG_SW_EN_SRAM_SHARE_242DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_242DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_262DEMOD0 ckgen00(0x1860)
#define REG_SW_EN_SRAM_SHARE_262DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_262DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_272DEMOD0 ckgen00(0x1864)
#define REG_SW_EN_SRAM_SHARE_272DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_272DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_282DEMOD0 ckgen00(0x1868)
#define REG_SW_EN_SRAM_SHARE_282DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_282DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_292DEMOD0 ckgen00(0x186c)
#define REG_SW_EN_SRAM_SHARE_292DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_292DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_342DEMOD0 ckgen00(0x1870)
#define REG_SW_EN_SRAM_SHARE_342DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_342DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_352DEMOD0 ckgen00(0x1874)
#define REG_SW_EN_SRAM_SHARE_352DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_352DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_362DEMOD0 ckgen00(0x1878)
#define REG_SW_EN_SRAM_SHARE_362DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_362DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_402DEMOD0 ckgen00(0x187c)
#define REG_SW_EN_SRAM_SHARE_402DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_402DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_422DEMOD0 ckgen00(0x1880)
#define REG_SW_EN_SRAM_SHARE_422DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_422DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_442DEMOD0 ckgen00(0x1884)
#define REG_SW_EN_SRAM_SHARE_442DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_442DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_462DEMOD0 ckgen00(0x1888)
#define REG_SW_EN_SRAM_SHARE_462DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_462DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_472DEMOD0 ckgen00(0x188c)
#define REG_SW_EN_SRAM_SHARE_472DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_472DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_50_02DEMOD0 ckgen00(0x1890)
#define REG_SW_EN_SRAM_SHARE_50_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_50_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_52_02DEMOD0 ckgen00(0x1894)
#define REG_SW_EN_SRAM_SHARE_52_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_52_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_53_02DEMOD0 ckgen00(0x1898)
#define REG_SW_EN_SRAM_SHARE_53_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_53_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_55_02DEMOD0 ckgen00(0x189c)
#define REG_SW_EN_SRAM_SHARE_55_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_55_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_562DEMOD0 ckgen00(0x18a0)
#define REG_SW_EN_SRAM_SHARE_562DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_562DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_572DEMOD0 ckgen00(0x18a4)
#define REG_SW_EN_SRAM_SHARE_572DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_572DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_582DEMOD0 ckgen00(0x18a8)
#define REG_SW_EN_SRAM_SHARE_582DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_582DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_592DEMOD0 ckgen00(0x18ac)
#define REG_SW_EN_SRAM_SHARE_592DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_592DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_602DEMOD0 ckgen00(0x18b0)
#define REG_SW_EN_SRAM_SHARE_602DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_602DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_612DEMOD0 ckgen00(0x18b4)
#define REG_SW_EN_SRAM_SHARE_612DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_612DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_622DEMOD0 ckgen00(0x18b8)
#define REG_SW_EN_SRAM_SHARE_622DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_622DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_642DEMOD0 ckgen00(0x18bc)
#define REG_SW_EN_SRAM_SHARE_642DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_642DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_662DEMOD0 ckgen00(0x18c0)
#define REG_SW_EN_SRAM_SHARE_662DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_662DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_672DEMOD0 ckgen00(0x18c4)
#define REG_SW_EN_SRAM_SHARE_672DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_672DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_68_02DEMOD0 ckgen00(0x18c8)
#define REG_SW_EN_SRAM_SHARE_68_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_68_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_68_22DEMOD0 ckgen00(0x18cc)
#define REG_SW_EN_SRAM_SHARE_68_22DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_68_22DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_69_02DEMOD0 ckgen00(0x18d0)
#define REG_SW_EN_SRAM_SHARE_69_02DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_69_02DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_702DEMOD0 ckgen00(0x18d4)
#define REG_SW_EN_SRAM_SHARE_702DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_702DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_712DEMOD0 ckgen00(0x18d8)
#define REG_SW_EN_SRAM_SHARE_712DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_712DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_772DEMOD0 ckgen00(0x18dc)
#define REG_SW_EN_SRAM_SHARE_772DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_772DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_792DEMOD0 ckgen00(0x18e0)
#define REG_SW_EN_SRAM_SHARE_792DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_792DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_812DEMOD0 ckgen00(0x18e4)
#define REG_SW_EN_SRAM_SHARE_812DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_812DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_852DEMOD0 ckgen00(0x18e8)
#define REG_SW_EN_SRAM_SHARE_852DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_852DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_872DEMOD0 ckgen00(0x18ec)
#define REG_SW_EN_SRAM_SHARE_872DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_872DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_892DEMOD0 ckgen00(0x18f0)
#define REG_SW_EN_SRAM_SHARE_892DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_892DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_912DEMOD0 ckgen00(0x18f4)
#define REG_SW_EN_SRAM_SHARE_912DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_912DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_922DEMOD0 ckgen00(0x18f8)
#define REG_SW_EN_SRAM_SHARE_922DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_922DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_932DEMOD0 ckgen00(0x18fc)
#define REG_SW_EN_SRAM_SHARE_932DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_932DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_942DEMOD0 ckgen00(0x1900)
#define REG_SW_EN_SRAM_SHARE_942DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_942DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_962DEMOD0 ckgen00(0x1904)
#define REG_SW_EN_SRAM_SHARE_962DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_962DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_982DEMOD0 ckgen00(0x1908)
#define REG_SW_EN_SRAM_SHARE_982DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_982DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_992DEMOD0 ckgen00(0x190c)
#define REG_SW_EN_SRAM_SHARE_992DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_992DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1002DEMOD0 ckgen00(0x1910)
#define REG_SW_EN_SRAM_SHARE_1002DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1002DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1032DEMOD0 ckgen00(0x1914)
#define REG_SW_EN_SRAM_SHARE_1032DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1032DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1052DEMOD0 ckgen00(0x1918)
#define REG_SW_EN_SRAM_SHARE_1052DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1052DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1072DEMOD0 ckgen00(0x191c)
#define REG_SW_EN_SRAM_SHARE_1072DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1072DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1092DEMOD0 ckgen00(0x1920)
#define REG_SW_EN_SRAM_SHARE_1092DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1092DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1102DEMOD0 ckgen00(0x1924)
#define REG_SW_EN_SRAM_SHARE_1102DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1102DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1112DEMOD0 ckgen00(0x1928)
#define REG_SW_EN_SRAM_SHARE_1112DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1112DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1122DEMOD0 ckgen00(0x192c)
#define REG_SW_EN_SRAM_SHARE_1122DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1122DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1242DEMOD0 ckgen00(0x1930)
#define REG_SW_EN_SRAM_SHARE_1242DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1242DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1282DEMOD0 ckgen00(0x1934)
#define REG_SW_EN_SRAM_SHARE_1282DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1282DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1292DEMOD0 ckgen00(0x1938)
#define REG_SW_EN_SRAM_SHARE_1292DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1292DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1302DEMOD0 ckgen00(0x193c)
#define REG_SW_EN_SRAM_SHARE_1302DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1302DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1312DEMOD0 ckgen00(0x1940)
#define REG_SW_EN_SRAM_SHARE_1312DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1312DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_1322DEMOD0 ckgen00(0x1944)
#define REG_SW_EN_SRAM_SHARE_1322DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_1322DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_134_R2DEMOD0 ckgen00(0x1948)
#define REG_SW_EN_SRAM_SHARE_134_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_134_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_134_W2DEMOD0 ckgen00(0x194c)
#define REG_SW_EN_SRAM_SHARE_134_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_134_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_136_R2DEMOD0 ckgen00(0x1950)
#define REG_SW_EN_SRAM_SHARE_136_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_136_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_136_W2DEMOD0 ckgen00(0x1954)
#define REG_SW_EN_SRAM_SHARE_136_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_136_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_137_R2DEMOD0 ckgen00(0x1958)
#define REG_SW_EN_SRAM_SHARE_137_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_137_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_137_W2DEMOD0 ckgen00(0x195c)
#define REG_SW_EN_SRAM_SHARE_137_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_137_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_138_R2DEMOD0 ckgen00(0x1960)
#define REG_SW_EN_SRAM_SHARE_138_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_138_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_138_W2DEMOD0 ckgen00(0x1964)
#define REG_SW_EN_SRAM_SHARE_138_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_138_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_139_R2DEMOD0 ckgen00(0x1968)
#define REG_SW_EN_SRAM_SHARE_139_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_139_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_139_W2DEMOD0 ckgen00(0x196c)
#define REG_SW_EN_SRAM_SHARE_139_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_139_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_140_R2DEMOD0 ckgen00(0x1970)
#define REG_SW_EN_SRAM_SHARE_140_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_140_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_140_W2DEMOD0 ckgen00(0x1974)
#define REG_SW_EN_SRAM_SHARE_140_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_140_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_141_R2DEMOD0 ckgen00(0x1978)
#define REG_SW_EN_SRAM_SHARE_141_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_141_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_141_W2DEMOD0 ckgen00(0x197c)
#define REG_SW_EN_SRAM_SHARE_141_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_141_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_142_R2DEMOD0 ckgen00(0x1980)
#define REG_SW_EN_SRAM_SHARE_142_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_142_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_142_W2DEMOD0 ckgen00(0x1984)
#define REG_SW_EN_SRAM_SHARE_142_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_142_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_143_R2DEMOD0 ckgen00(0x1988)
#define REG_SW_EN_SRAM_SHARE_143_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_143_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_143_W2DEMOD0 ckgen00(0x198c)
#define REG_SW_EN_SRAM_SHARE_143_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_143_W2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_144_R2DEMOD0 ckgen00(0x1990)
#define REG_SW_EN_SRAM_SHARE_144_R2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_144_R2DEMOD0_E 0
#define REG_SW_EN_SRAM_SHARE_144_W2DEMOD0 ckgen00(0x1994)
#define REG_SW_EN_SRAM_SHARE_144_W2DEMOD0_S 0
#define REG_SW_EN_SRAM_SHARE_144_W2DEMOD0_E 0
#define REG_SW_EN_TDP_JL_INNER1X2DEMOD0 ckgen00(0x1998)
#define REG_SW_EN_TDP_JL_INNER1X2DEMOD0_S 0
#define REG_SW_EN_TDP_JL_INNER1X2DEMOD0_E 0
#define REG_SW_EN_TDP_JL_INNER4X2DEMOD0 ckgen00(0x199c)
#define REG_SW_EN_TDP_JL_INNER4X2DEMOD0_S 0
#define REG_SW_EN_TDP_JL_INNER4X2DEMOD0_E 0
#define REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0 ckgen00(0x19a0)
#define REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0_S 0
#define REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0_E 0
#define REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0 ckgen00(0x19a4)
#define REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0_S 0
#define REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0_E 0
#define REG_SW_EN_TR2DEMOD0 ckgen00(0x19a8)
#define REG_SW_EN_TR2DEMOD0_S 0
#define REG_SW_EN_TR2DEMOD0_E 0
#define REG_SW_EN_TS_IN2DEMOD0 ckgen00(0x19ac)
#define REG_SW_EN_TS_IN2DEMOD0_S 0
#define REG_SW_EN_TS_IN2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_144M2DEMOD0 ckgen00(0x19b0)
#define REG_SW_EN_VIFDBB_144M2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_144M2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_43M2DEMOD0 ckgen00(0x19b4)
#define REG_SW_EN_VIFDBB_43M2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_43M2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_86M2DEMOD0 ckgen00(0x19b8)
#define REG_SW_EN_VIFDBB_86M2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_86M2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_DAC2DEMOD0 ckgen00(0x19bc)
#define REG_SW_EN_VIFDBB_DAC2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_DAC2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0 ckgen00(0x19c0)
#define REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0_E 0
#define REG_SW_EN_VIFDBB_VDAC2DEMOD0 ckgen00(0x19c4)
#define REG_SW_EN_VIFDBB_VDAC2DEMOD0_S 0
#define REG_SW_EN_VIFDBB_VDAC2DEMOD0_E 0
#define REG_SW_EN_XTAL_12M2DEMOD0 ckgen00(0x19c8)
#define REG_SW_EN_XTAL_12M2DEMOD0_S 0
#define REG_SW_EN_XTAL_12M2DEMOD0_E 0
#define REG_SW_EN_XTAL_24M2DEMOD0 ckgen00(0x19cc)
#define REG_SW_EN_XTAL_24M2DEMOD0_S 0
#define REG_SW_EN_XTAL_24M2DEMOD0_E 0
#define REG_SW_EN_XTAL_24M2DEMOD1 ckgen00(0x19d0)
#define REG_SW_EN_XTAL_24M2DEMOD1_S 0
#define REG_SW_EN_XTAL_24M2DEMOD1_E 0
#define REG_SW_EN_XTAL_12M2DEMOD1 ckgen00(0x19d4)
#define REG_SW_EN_XTAL_12M2DEMOD1_S 0
#define REG_SW_EN_XTAL_12M2DEMOD1_E 0
#define REG_SW_EN_AESDMA2DSCRMB ckgen00(0x1a00)
#define REG_SW_EN_AESDMA2DSCRMB_S 0
#define REG_SW_EN_AESDMA2DSCRMB_E 0
#define REG_SW_EN_CILINK_2B_RX2CILINK ckgen00(0x1a0c)
#define REG_SW_EN_CILINK_2B_RX2CILINK_S 0
#define REG_SW_EN_CILINK_2B_RX2CILINK_E 0
#define REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE ckgen00(0x1a10)
#define REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE_S 0
#define REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE_E 0
#define REG_SW_EN_CILINK_2B_TX2CILINK ckgen00(0x1a14)
#define REG_SW_EN_CILINK_2B_TX2CILINK_S 0
#define REG_SW_EN_CILINK_2B_TX2CILINK_E 0
#define REG_SW_EN_CILINK_IF2CILINK ckgen00(0x1a18)
#define REG_SW_EN_CILINK_IF2CILINK_S 0
#define REG_SW_EN_CILINK_IF2CILINK_E 0
#define REG_SW_EN_SMART_SYNTH_272PIU ckgen00(0x1a24)
#define REG_SW_EN_SMART_SYNTH_272PIU_S 0
#define REG_SW_EN_SMART_SYNTH_272PIU_E 0
#define REG_SW_EN_SMART_SYNTH_4322PIU ckgen00(0x1a28)
#define REG_SW_EN_SMART_SYNTH_4322PIU_S 0
#define REG_SW_EN_SMART_SYNTH_4322PIU_E 0
#define REG_SW_EN_SMART2_SYNTH_272PIU ckgen00(0x1a2c)
#define REG_SW_EN_SMART2_SYNTH_272PIU_S 0
#define REG_SW_EN_SMART2_SYNTH_272PIU_E 0
#define REG_SW_EN_SMART2_SYNTH_4322PIU ckgen00(0x1a30)
#define REG_SW_EN_SMART2_SYNTH_4322PIU_S 0
#define REG_SW_EN_SMART2_SYNTH_4322PIU_E 0
#define REG_SW_EN_SMART22PIU ckgen00(0x1a34)
#define REG_SW_EN_SMART22PIU_S 0
#define REG_SW_EN_SMART22PIU_E 0
#define REG_SW_EN_SMART2PIU ckgen00(0x1a38)
#define REG_SW_EN_SMART2PIU_S 0
#define REG_SW_EN_SMART2PIU_E 0
#define REG_SW_EN_FIQ0_27M2TSP ckgen00(0x1a48)
#define REG_SW_EN_FIQ0_27M2TSP_S 0
#define REG_SW_EN_FIQ0_27M2TSP_E 0
#define REG_SW_EN_MM0_27M2TSP ckgen00(0x1a4c)
#define REG_SW_EN_MM0_27M2TSP_S 0
#define REG_SW_EN_MM0_27M2TSP_E 0
#define REG_SW_EN_MM1_27M2TSP ckgen00(0x1a50)
#define REG_SW_EN_MM1_27M2TSP_S 0
#define REG_SW_EN_MM1_27M2TSP_E 0
#define REG_SW_EN_PARSER2TSP ckgen00(0x1a54)
#define REG_SW_EN_PARSER2TSP_S 0
#define REG_SW_EN_PARSER2TSP_E 0
#define REG_SW_EN_PARSER2VD_PES_PARSER ckgen00(0x1a54)
#define REG_SW_EN_PARSER2VD_PES_PARSER_S 1
#define REG_SW_EN_PARSER2VD_PES_PARSER_E 1
#define REG_SW_EN_VIVA_PARSER2PARSER ckgen00(0x1a54)
#define REG_SW_EN_VIVA_PARSER2PARSER_S 2
#define REG_SW_EN_VIVA_PARSER2PARSER_E 2
#define REG_SW_EN_PVR1_27M2TSP ckgen00(0x1a58)
#define REG_SW_EN_PVR1_27M2TSP_S 0
#define REG_SW_EN_PVR1_27M2TSP_E 0
#define REG_SW_EN_PVR2_27M2TSP ckgen00(0x1a5c)
#define REG_SW_EN_PVR2_27M2TSP_S 0
#define REG_SW_EN_PVR2_27M2TSP_E 0
#define REG_SW_EN_PVR3_27M2TSP ckgen00(0x1a60)
#define REG_SW_EN_PVR3_27M2TSP_S 0
#define REG_SW_EN_PVR3_27M2TSP_E 0
#define REG_SW_EN_PVR4_27M2TSP ckgen00(0x1a64)
#define REG_SW_EN_PVR4_27M2TSP_S 0
#define REG_SW_EN_PVR4_27M2TSP_E 0
#define REG_SW_EN_STAMP2TSO ckgen00(0x1a6c)
#define REG_SW_EN_STAMP2TSO_S 0
#define REG_SW_EN_STAMP2TSO_E 0
#define REG_SW_EN_STAMP2TSO2 ckgen00(0x1a70)
#define REG_SW_EN_STAMP2TSO2_S 0
#define REG_SW_EN_STAMP2TSO2_E 0
#define REG_SW_EN_STAMP2TSP ckgen00(0x1a74)
#define REG_SW_EN_STAMP2TSP_S 0
#define REG_SW_EN_STAMP2TSP_E 0
#define REG_SW_EN_SYN_STC02TS_SAMPLE ckgen00(0x1a78)
#define REG_SW_EN_SYN_STC02TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC02TS_SAMPLE_E 0
#define REG_SW_EN_SYN_STC12TS_SAMPLE ckgen00(0x1a7c)
#define REG_SW_EN_SYN_STC12TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC12TS_SAMPLE_E 0
#define REG_SW_EN_SYN_STC22TS_SAMPLE ckgen00(0x1a80)
#define REG_SW_EN_SYN_STC22TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC22TS_SAMPLE_E 0
#define REG_SW_EN_SYN_STC32TS_SAMPLE ckgen00(0x1a84)
#define REG_SW_EN_SYN_STC32TS_SAMPLE_S 0
#define REG_SW_EN_SYN_STC32TS_SAMPLE_E 0
#define REG_SW_EN_SYS_TIME0_27M2TSP ckgen00(0x1a88)
#define REG_SW_EN_SYS_TIME0_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME0_27M2TSP_E 0
#define REG_SW_EN_SYS_TIME1_27M2TSP ckgen00(0x1a8c)
#define REG_SW_EN_SYS_TIME1_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME1_27M2TSP_E 0
#define REG_SW_EN_SYS_TIME2_27M2TSP ckgen00(0x1a90)
#define REG_SW_EN_SYS_TIME2_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME2_27M2TSP_E 0
#define REG_SW_EN_SYS_TIME3_27M2TSP ckgen00(0x1a94)
#define REG_SW_EN_SYS_TIME3_27M2TSP_S 0
#define REG_SW_EN_SYS_TIME3_27M2TSP_E 0
#define REG_SW_EN_TLV0_27M2TSP ckgen00(0x1a98)
#define REG_SW_EN_TLV0_27M2TSP_S 0
#define REG_SW_EN_TLV0_27M2TSP_E 0
#define REG_SW_EN_TLV1_27M2TSP ckgen00(0x1a9c)
#define REG_SW_EN_TLV1_27M2TSP_S 0
#define REG_SW_EN_TLV1_27M2TSP_E 0
#define REG_SW_EN_TLV2_27M2TSP ckgen00(0x1aa0)
#define REG_SW_EN_TLV2_27M2TSP_S 0
#define REG_SW_EN_TLV2_27M2TSP_E 0
#define REG_SW_EN_TS_ALP02TSP ckgen00(0x1aa8)
#define REG_SW_EN_TS_ALP02TSP_S 0
#define REG_SW_EN_TS_ALP02TSP_E 0
#define REG_SW_EN_TS_ALP12TSP ckgen00(0x1aac)
#define REG_SW_EN_TS_ALP12TSP_S 0
#define REG_SW_EN_TS_ALP12TSP_E 0
#define REG_SW_EN_TS_SAMPLE2TS_SAMPLE ckgen00(0x1ab4)
#define REG_SW_EN_TS_SAMPLE2TS_SAMPLE_S 0
#define REG_SW_EN_TS_SAMPLE2TS_SAMPLE_E 0
#define REG_SW_EN_TS_TX_C12CILINK ckgen00(0x1ab8)
#define REG_SW_EN_TS_TX_C12CILINK_S 0
#define REG_SW_EN_TS_TX_C12CILINK_E 0
#define REG_SW_EN_TS_TX_C22CILINK ckgen00(0x1abc)
#define REG_SW_EN_TS_TX_C22CILINK_S 0
#define REG_SW_EN_TS_TX_C22CILINK_E 0
#define REG_SW_EN_TS0_IN_DFT2TS_SAMPLE ckgen00(0x1ac0)
#define REG_SW_EN_TS0_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS0_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS02TSP ckgen00(0x1ac4)
#define REG_SW_EN_TS02TSP_S 0
#define REG_SW_EN_TS02TSP_E 0
#define REG_SW_EN_TS1_IN_DFT2TS_SAMPLE ckgen00(0x1ac8)
#define REG_SW_EN_TS1_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS1_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS12TSP ckgen00(0x1acc)
#define REG_SW_EN_TS12TSP_S 0
#define REG_SW_EN_TS12TSP_E 0
#define REG_SW_EN_TS2_IN_DFT2TS_SAMPLE ckgen00(0x1ad0)
#define REG_SW_EN_TS2_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS2_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS22TSP ckgen00(0x1ad4)
#define REG_SW_EN_TS22TSP_S 0
#define REG_SW_EN_TS22TSP_E 0
#define REG_SW_EN_TS3_IN_DFT2TS_SAMPLE ckgen00(0x1ad8)
#define REG_SW_EN_TS3_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS3_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS4_IN_DFT2TS_SAMPLE ckgen00(0x1adc)
#define REG_SW_EN_TS4_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS4_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TS5_IN_DFT2TS_SAMPLE ckgen00(0x1ae0)
#define REG_SW_EN_TS5_IN_DFT2TS_SAMPLE_S 0
#define REG_SW_EN_TS5_IN_DFT2TS_SAMPLE_E 0
#define REG_SW_EN_TSFI2TSP ckgen00(0x1ae4)
#define REG_SW_EN_TSFI2TSP_S 0
#define REG_SW_EN_TSFI2TSP_E 0
#define REG_SW_EN_TSIF0_27M2TSP ckgen00(0x1ae8)
#define REG_SW_EN_TSIF0_27M2TSP_S 0
#define REG_SW_EN_TSIF0_27M2TSP_E 0
#define REG_SW_EN_TSO_CH1_27M2TSO ckgen00(0x1aec)
#define REG_SW_EN_TSO_CH1_27M2TSO_S 0
#define REG_SW_EN_TSO_CH1_27M2TSO_E 0
#define REG_SW_EN_TSO_CH12TSO ckgen00(0x1af0)
#define REG_SW_EN_TSO_CH12TSO_S 0
#define REG_SW_EN_TSO_CH12TSO_E 0
#define REG_SW_EN_TSO_CH5_27M2TSO ckgen00(0x1af4)
#define REG_SW_EN_TSO_CH5_27M2TSO_S 0
#define REG_SW_EN_TSO_CH5_27M2TSO_E 0
#define REG_SW_EN_TSO_CH52TSO ckgen00(0x1af8)
#define REG_SW_EN_TSO_CH52TSO_S 0
#define REG_SW_EN_TSO_CH52TSO_E 0
#define REG_SW_EN_TSO_CH6_27M2TSO ckgen00(0x1afc)
#define REG_SW_EN_TSO_CH6_27M2TSO_S 0
#define REG_SW_EN_TSO_CH6_27M2TSO_E 0
#define REG_SW_EN_TSO_CH62TSO ckgen00(0x1b00)
#define REG_SW_EN_TSO_CH62TSO_S 0
#define REG_SW_EN_TSO_CH62TSO_E 0
#define REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE ckgen00(0x1b04)
#define REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE_S 0
#define REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE_E 0
#define REG_SW_EN_TSO_OUT2TSO ckgen00(0x1b08)
#define REG_SW_EN_TSO_OUT2TSO_S 0
#define REG_SW_EN_TSO_OUT2TSO_E 0
#define REG_SW_EN_TSO_S2P12TSO ckgen00(0x1b0c)
#define REG_SW_EN_TSO_S2P12TSO_S 0
#define REG_SW_EN_TSO_S2P12TSO_E 0
#define REG_SW_EN_TSO_S2P2TSO ckgen00(0x1b10)
#define REG_SW_EN_TSO_S2P2TSO_S 0
#define REG_SW_EN_TSO_S2P2TSO_E 0
#define REG_SW_EN_TSO_TRACE_IN2TSO ckgen00(0x1b14)
#define REG_SW_EN_TSO_TRACE_IN2TSO_S 0
#define REG_SW_EN_TSO_TRACE_IN2TSO_E 0
#define REG_SW_EN_TSO_TRACE2TSO ckgen00(0x1b18)
#define REG_SW_EN_TSO_TRACE2TSO_S 0
#define REG_SW_EN_TSO_TRACE2TSO_E 0
#define REG_SW_EN_TSO2_CH1_27M2TSO2 ckgen00(0x1b1c)
#define REG_SW_EN_TSO2_CH1_27M2TSO2_S 0
#define REG_SW_EN_TSO2_CH1_27M2TSO2_E 0
#define REG_SW_EN_TSO2_CH12TSO2 ckgen00(0x1b20)
#define REG_SW_EN_TSO2_CH12TSO2_S 0
#define REG_SW_EN_TSO2_CH12TSO2_E 0
#define REG_SW_EN_TSO2_CH5_27M2TSO2 ckgen00(0x1b24)
#define REG_SW_EN_TSO2_CH5_27M2TSO2_S 0
#define REG_SW_EN_TSO2_CH5_27M2TSO2_E 0
#define REG_SW_EN_TSO2_CH52TSO2 ckgen00(0x1b28)
#define REG_SW_EN_TSO2_CH52TSO2_S 0
#define REG_SW_EN_TSO2_CH52TSO2_E 0
#define REG_SW_EN_TSO2_CH6_27M2TSO2 ckgen00(0x1b2c)
#define REG_SW_EN_TSO2_CH6_27M2TSO2_S 0
#define REG_SW_EN_TSO2_CH6_27M2TSO2_E 0
#define REG_SW_EN_TSO2_CH62TSO2 ckgen00(0x1b30)
#define REG_SW_EN_TSO2_CH62TSO2_S 0
#define REG_SW_EN_TSO2_CH62TSO2_E 0
#define REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE ckgen00(0x1b34)
#define REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE_S 0
#define REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE_E 0
#define REG_SW_EN_TSO2_OUT2TSO2 ckgen00(0x1b38)
#define REG_SW_EN_TSO2_OUT2TSO2_S 0
#define REG_SW_EN_TSO2_OUT2TSO2_E 0
#define REG_SW_EN_TSO2_S2P12TSO2 ckgen00(0x1b3c)
#define REG_SW_EN_TSO2_S2P12TSO2_S 0
#define REG_SW_EN_TSO2_S2P12TSO2_E 0
#define REG_SW_EN_TSO2_S2P2TSO2 ckgen00(0x1b40)
#define REG_SW_EN_TSO2_S2P2TSO2_S 0
#define REG_SW_EN_TSO2_S2P2TSO2_E 0
#define REG_SW_EN_TSO2_TRACE_IN2TSO2 ckgen00(0x1b44)
#define REG_SW_EN_TSO2_TRACE_IN2TSO2_S 0
#define REG_SW_EN_TSO2_TRACE_IN2TSO2_E 0
#define REG_SW_EN_TSO2_TRACE2TSO2 ckgen00(0x1b48)
#define REG_SW_EN_TSO2_TRACE2TSO2_S 0
#define REG_SW_EN_TSO2_TRACE2TSO2_E 0
#define REG_SW_EN_TSP2DSCRMB ckgen00(0x1b4c)
#define REG_SW_EN_TSP2DSCRMB_S 0
#define REG_SW_EN_TSP2DSCRMB_E 0
#define REG_SW_EN_TSP2TSO ckgen00(0x1b50)
#define REG_SW_EN_TSP2TSO_S 0
#define REG_SW_EN_TSP2TSO_E 0
#define REG_SW_EN_TSP2TSO2 ckgen00(0x1b50)
#define REG_SW_EN_TSP2TSO2_S 1
#define REG_SW_EN_TSP2TSO2_E 1
#define REG_SW_EN_TSP2TSP ckgen00(0x1b50)
#define REG_SW_EN_TSP2TSP_S 2
#define REG_SW_EN_TSP2TSP_E 2
#define REG_SW_EN_TS_TLV02TSP ckgen00(0x1b54)
#define REG_SW_EN_TS_TLV02TSP_S 0
#define REG_SW_EN_TS_TLV02TSP_E 0
#define REG_SW_EN_TS_TLV12TSP ckgen00(0x1b58)
#define REG_SW_EN_TS_TLV12TSP_S 0
#define REG_SW_EN_TS_TLV12TSP_E 0
#define REG_SW_EN_TS_TLV22TSP ckgen00(0x1b5c)
#define REG_SW_EN_TS_TLV22TSP_S 0
#define REG_SW_EN_TS_TLV22TSP_E 0
#define REG_SW_EN_PATH0_27M2TSP ckgen00(0x1b60)
#define REG_SW_EN_PATH0_27M2TSP_S 0
#define REG_SW_EN_PATH0_27M2TSP_E 0
#define REG_SW_EN_PATH1_27M2TSP ckgen00(0x1b64)
#define REG_SW_EN_PATH1_27M2TSP_S 0
#define REG_SW_EN_PATH1_27M2TSP_E 0
#define REG_SW_EN_PATH2_27M2TSP ckgen00(0x1b68)
#define REG_SW_EN_PATH2_27M2TSP_S 0
#define REG_SW_EN_PATH2_27M2TSP_E 0
#define REG_SW_EN_PATH_FI_27M2TSP ckgen00(0x1b6c)
#define REG_SW_EN_PATH_FI_27M2TSP_S 0
#define REG_SW_EN_PATH_FI_27M2TSP_E 0
#define REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS ckgen00(0x1b80)
#define REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS_S 0
#define REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS_E 0
#define REG_SW_EN_AU_R2_DFS2AUDIO_R2 ckgen00(0x1b84)
#define REG_SW_EN_AU_R2_DFS2AUDIO_R2_S 0
#define REG_SW_EN_AU_R2_DFS2AUDIO_R2_E 0
#define REG_SW_EN_AU_R2_PLL2AUDIO_R2 ckgen00(0x1b88)
#define REG_SW_EN_AU_R2_PLL2AUDIO_R2_S 0
#define REG_SW_EN_AU_R2_PLL2AUDIO_R2_E 0
#define REG_SW_EN_AU_R2_WB2AUDIO_R2 ckgen00(0x1b8c)
#define REG_SW_EN_AU_R2_WB2AUDIO_R2_S 0
#define REG_SW_EN_AU_R2_WB2AUDIO_R2_E 0
#define REG_SW_EN_AUSDM_3M2AUSDM_DMACRO ckgen00(0x1b90)
#define REG_SW_EN_AUSDM_3M2AUSDM_DMACRO_S 0
#define REG_SW_EN_AUSDM_3M2AUSDM_DMACRO_E 0
#define REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2 ckgen00(0x1b94)
#define REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2_S 0
#define REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2_E 0
#define REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER ckgen00(0x1b98)
#define REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER_S 0
#define REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER_E 0
#define REG_SW_EN_EARC_AUDIO2EARC_DMACRO ckgen00(0x1b9c)
#define REG_SW_EN_EARC_AUDIO2EARC_DMACRO_S 0
#define REG_SW_EN_EARC_AUDIO2EARC_DMACRO_E 0
#define REG_SW_EN_VIVA_AB_MAC2AB_MAC ckgen00(0x1ba0)
#define REG_SW_EN_VIVA_AB_MAC2AB_MAC_S 0
#define REG_SW_EN_VIVA_AB_MAC2AB_MAC_E 0
#define REG_SW_EN_VIVA_AB3_MAC2AB3_MAC ckgen00(0x1ba4)
#define REG_SW_EN_VIVA_AB3_MAC2AB3_MAC_S 0
#define REG_SW_EN_VIVA_AB3_MAC2AB3_MAC_E 0
#define REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS ckgen00(0x1ba8)
#define REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS_S 0
#define REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS_E 0
#define REG_SW_EN_VIVA_AU_MCU2AU_MCU ckgen00(0x1bac)
#define REG_SW_EN_VIVA_AU_MCU2AU_MCU_S 0
#define REG_SW_EN_VIVA_AU_MCU2AU_MCU_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS ckgen00(0x1bb0)
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN ckgen00(0x1bb4)
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF ckgen00(0x1bb8)
#define REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS ckgen00(0x1bbc)
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN ckgen00(0x1bc0)
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF ckgen00(0x1bc4)
#define REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2 ckgen00(0x1bc8)
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2_S 0
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2_E 0
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER2BCLK_I2S_DECODER ckgen00(0x1bcc)
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER2BCLK_I2S_DECODER_S 0
#define REG_SW_EN_VIVA_BCLK_I2S_DECODER2BCLK_I2S_DECODER_E 0
#define REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2 ckgen00(0x1bd0)
#define REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2_S 0
#define REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2_E 0
#define REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI ckgen00(0x1bd4)
#define REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI_S 0
#define REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI_E 0
#define REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI ckgen00(0x1bd8)
#define REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI_S 0
#define REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI_E 0
#define REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI ckgen00(0x1bdc)
#define REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI_S 0
#define REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI_E 0
#define REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI ckgen00(0x1be0)
#define REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI_S 0
#define REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI_E 0
#define REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI ckgen00(0x1be4)
#define REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI_S 0
#define REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI_E 0
#define REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI ckgen00(0x1be8)
#define REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI_S 0
#define REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI_E 0
#define REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI ckgen00(0x1bec)
#define REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI_S 0
#define REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI_E 0
#define REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI ckgen00(0x1bf0)
#define REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI_S 0
#define REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI_E 0
#define REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI ckgen00(0x1bf4)
#define REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI_S 0
#define REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI_E 0
#define REG_SW_EN_VIVA_CODEC_SH2CODEC_SH ckgen00(0x1bf8)
#define REG_SW_EN_VIVA_CODEC_SH2CODEC_SH_S 0
#define REG_SW_EN_VIVA_CODEC_SH2CODEC_SH_E 0
#define REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS ckgen00(0x1bfc)
#define REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS_S 0
#define REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230 ckgen00(0x1c00)
#define REG_SW_EN_VIVA_DSP2DSP_230_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_1 ckgen00(0x1c04)
#define REG_SW_EN_VIVA_DSP2DSP_230_1_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_1_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_2 ckgen00(0x1c08)
#define REG_SW_EN_VIVA_DSP2DSP_230_2_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_2_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_3 ckgen00(0x1c0c)
#define REG_SW_EN_VIVA_DSP2DSP_230_3_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_3_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF ckgen00(0x1c10)
#define REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF_E 0
#define REG_SW_EN_VIVA_DSP2DSP_230_TM ckgen00(0x1c14)
#define REG_SW_EN_VIVA_DSP2DSP_230_TM_S 0
#define REG_SW_EN_VIVA_DSP2DSP_230_TM_E 0
#define REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF ckgen00(0x1c18)
#define REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS ckgen00(0x1c1c)
#define REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF ckgen00(0x1c20)
#define REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS ckgen00(0x1c24)
#define REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF ckgen00(0x1c28)
#define REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS ckgen00(0x1c2c)
#define REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF ckgen00(0x1c30)
#define REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS ckgen00(0x1c34)
#define REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS ckgen00(0x1c38)
#define REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS ckgen00(0x1c3c)
#define REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS_S 0
#define REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS_E 0
#define REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS ckgen00(0x1c40)
#define REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS_S 0
#define REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS_E 0
#define REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS ckgen00(0x1c44)
#define REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS_S 0
#define REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS_E 0
#define REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS ckgen00(0x1c48)
#define REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS_S 0
#define REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS_E 0
#define REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF ckgen00(0x1c4c)
#define REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL ckgen00(0x1c50)
#define REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL_S 0
#define REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL_E 0
#define REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS ckgen00(0x1c54)
#define REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS_S 0
#define REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS_E 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF ckgen00(0x1c58)
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF_S 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF_E 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF ckgen00(0x1c5c)
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR ckgen00(0x1c60)
#define REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR_S 0
#define REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR_E 0
#define REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO ckgen00(0x1c64)
#define REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO_S 0
#define REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO_E 0
#define REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO ckgen00(0x1c68)
#define REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO_S 0
#define REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO_E 0
#define REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO ckgen00(0x1c6c)
#define REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO_S 0
#define REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO_E 0
#define REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432 ckgen00(0x1c70)
#define REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432_S 0
#define REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432_E 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS ckgen00(0x1c74)
#define REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS ckgen00(0x1c78)
#define REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF ckgen00(0x1c7c)
#define REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP ckgen00(0x1c80)
#define REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP_S 0
#define REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432 ckgen00(0x1c84)
#define REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS ckgen00(0x1c88)
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS ckgen00(0x1c8c)
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF ckgen00(0x1c90)
#define REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP ckgen00(0x1c94)
#define REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP_S 0
#define REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP_E 0
#define REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS ckgen00(0x1c98)
#define REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS_S 0
#define REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS_E 0
#define REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS ckgen00(0x1c9c)
#define REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS_S 0
#define REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS_E 0
#define REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF ckgen00(0x1ca0)
#define REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2 ckgen00(0x1ca4)
#define REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2_S 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2_E 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG ckgen00(0x1ca8)
#define REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG_S 0
#define REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG_E 0
#define REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF ckgen00(0x1cac)
#define REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF ckgen00(0x1cb0)
#define REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF ckgen00(0x1cb4)
#define REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN ckgen00(0x1cb8)
#define REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF ckgen00(0x1cbc)
#define REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS ckgen00(0x1cc0)
#define REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS_S 0
#define REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS_E 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2 ckgen00(0x1cc4)
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2_S 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2_E 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER ckgen00(0x1cc8)
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER_S 0
#define REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER_E 0
#define REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF ckgen00(0x1ccc)
#define REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF ckgen00(0x1cd0)
#define REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF ckgen00(0x1cd4)
#define REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN ckgen00(0x1cd8)
#define REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF ckgen00(0x1cdc)
#define REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN ckgen00(0x1ce0)
#define REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN_S 0
#define REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN_E 0
#define REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF ckgen00(0x1ce4)
#define REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216 ckgen00(0x1ce8)
#define REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216_S 0
#define REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216_E 0
#define REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL ckgen00(0x1cec)
#define REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL_S 0
#define REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL_E 0
#define REG_SW_EN_VIVA_R2_WB2R2_WB ckgen00(0x1cf0)
#define REG_SW_EN_VIVA_R2_WB2R2_WB_S 0
#define REG_SW_EN_VIVA_R2_WB2R2_WB_E 0
#define REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG ckgen00(0x1cf4)
#define REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG_S 0
#define REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG_E 0
#define REG_SW_EN_VIVA_RIU_R22RIU_R2 ckgen00(0x1cf8)
#define REG_SW_EN_VIVA_RIU_R22RIU_R2_S 0
#define REG_SW_EN_VIVA_RIU_R22RIU_R2_E 0
#define REG_SW_EN_VIVA_SH2CH1_SH ckgen00(0x1cfc)
#define REG_SW_EN_VIVA_SH2CH1_SH_S 0
#define REG_SW_EN_VIVA_SH2CH1_SH_E 0
#define REG_SW_EN_VIVA_SH2CH2_SH ckgen00(0x1d00)
#define REG_SW_EN_VIVA_SH2CH2_SH_S 0
#define REG_SW_EN_VIVA_SH2CH2_SH_E 0
#define REG_SW_EN_VIVA_SH2CH3_SH ckgen00(0x1d04)
#define REG_SW_EN_VIVA_SH2CH3_SH_S 0
#define REG_SW_EN_VIVA_SH2CH3_SH_E 0
#define REG_SW_EN_VIVA_SH2CH4_SH ckgen00(0x1d08)
#define REG_SW_EN_VIVA_SH2CH4_SH_S 0
#define REG_SW_EN_VIVA_SH2CH4_SH_E 0
#define REG_SW_EN_VIVA_SH2CH5_SH ckgen00(0x1d0c)
#define REG_SW_EN_VIVA_SH2CH5_SH_S 0
#define REG_SW_EN_VIVA_SH2CH5_SH_E 0
#define REG_SW_EN_VIVA_SH2CH6_SH ckgen00(0x1d10)
#define REG_SW_EN_VIVA_SH2CH6_SH_S 0
#define REG_SW_EN_VIVA_SH2CH6_SH_E 0
#define REG_SW_EN_VIVA_SH2CH7_SH ckgen00(0x1d14)
#define REG_SW_EN_VIVA_SH2CH7_SH_S 0
#define REG_SW_EN_VIVA_SH2CH7_SH_E 0
#define REG_SW_EN_VIVA_SH2CH8_SH ckgen00(0x1d18)
#define REG_SW_EN_VIVA_SH2CH8_SH_S 0
#define REG_SW_EN_VIVA_SH2CH8_SH_E 0
#define REG_SW_EN_VIVA_SH2CH9_SH ckgen00(0x1d1c)
#define REG_SW_EN_VIVA_SH2CH9_SH_S 0
#define REG_SW_EN_VIVA_SH2CH9_SH_E 0
#define REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC ckgen00(0x1d20)
#define REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC_S 0
#define REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC_E 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN ckgen00(0x1d24)
#define REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN_S 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN_E 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B ckgen00(0x1d28)
#define REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B_S 0
#define REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B_E 0
#define REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC ckgen00(0x1d2c)
#define REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC_S 0
#define REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC_E 0
#define REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH ckgen00(0x1d30)
#define REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH_S 0
#define REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH_E 0
#define REG_SW_EN_VIVA_SIN_GEN2SIN_GEN ckgen00(0x1d34)
#define REG_SW_EN_VIVA_SIN_GEN2SIN_GEN_S 0
#define REG_SW_EN_VIVA_SIN_GEN2SIN_GEN_E 0
#define REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS ckgen00(0x1d38)
#define REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS_S 0
#define REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS_E 0
#define REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG ckgen00(0x1d3c)
#define REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG_S 0
#define REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG_E 0
#define REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF ckgen00(0x1d40)
#define REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS ckgen00(0x1d44)
#define REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS_E 0
#define REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS ckgen00(0x1d48)
#define REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS_E 0
#define REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF ckgen00(0x1d4c)
#define REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF_S 0
#define REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF_E 0
#define REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS ckgen00(0x1d50)
#define REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS_E 0
#define REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS ckgen00(0x1d54)
#define REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS_S 0
#define REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS_E 0
#define REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER ckgen00(0x1d58)
#define REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER_S 0
#define REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER_E 0
#define REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC ckgen00(0x1d5c)
#define REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC_S 0
#define REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC_E 0
#define REG_SW_EN_VIVA_TEST_BUS2TEST_BUS ckgen00(0x1d60)
#define REG_SW_EN_VIVA_TEST_BUS2TEST_BUS_S 0
#define REG_SW_EN_VIVA_TEST_BUS2TEST_BUS_E 0
#define REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU ckgen00(0x1d64)
#define REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU_S 0
#define REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU_E 0
#define REG_SW_EN_VIVA_XTAL_12M2XTAL ckgen00(0x1d68)
#define REG_SW_EN_VIVA_XTAL_12M2XTAL_S 0
#define REG_SW_EN_VIVA_XTAL_12M2XTAL_E 0
#define REG_SW_EN_XTAL_12M2AUDIO_R2 ckgen00(0x1d68)
#define REG_SW_EN_XTAL_12M2AUDIO_R2_S 1
#define REG_SW_EN_XTAL_12M2AUDIO_R2_E 1
#define REG_SW_EN_VIVA_XTAL_24M2XTAL ckgen00(0x1d6c)
#define REG_SW_EN_VIVA_XTAL_24M2XTAL_S 0
#define REG_SW_EN_VIVA_XTAL_24M2XTAL_E 0
#define REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS ckgen00(0x1d7c)
#define REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS_S 0
#define REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS_E 0
#define REG_SW_EN_MCU_WB2RV55FRC ckgen00(0x1d80)
#define REG_SW_EN_MCU_WB2RV55FRC_S 4
#define REG_SW_EN_MCU_WB2RV55FRC_E 4
#define REG_SW_EN_MCU_WB2RV55PQU ckgen00(0x1d80)
#define REG_SW_EN_MCU_WB2RV55PQU_S 5
#define REG_SW_EN_MCU_WB2RV55PQU_E 5
#define REG_SW_EN_GPD2GPD ckgen00(0x1d90)
#define REG_SW_EN_GPD2GPD_S 0
#define REG_SW_EN_GPD2GPD_E 0
#define REG_SW_EN_NJPD2JPD ckgen00(0x1d98)
#define REG_SW_EN_NJPD2JPD_S 0
#define REG_SW_EN_NJPD2JPD_E 0
#define REG_SW_EN_VDEC_BUS2CORE0 ckgen00(0x1da0)
#define REG_SW_EN_VDEC_BUS2CORE0_S 0
#define REG_SW_EN_VDEC_BUS2CORE0_E 0
#define REG_SW_EN_GCE_F26M2GCE_BIU ckgen00(0x1da0)
#define REG_SW_EN_GCE_F26M2GCE_BIU_S 3
#define REG_SW_EN_GCE_F26M2GCE_BIU_E 3
#define REG_SW_EN_VDEC_BUS2SOC ckgen00(0x1da4)
#define REG_SW_EN_VDEC_BUS2SOC_S 0
#define REG_SW_EN_VDEC_BUS2SOC_E 0
#define REG_SW_EN_VDEC_LAT02SOC ckgen00(0x1da8)
#define REG_SW_EN_VDEC_LAT02SOC_S 0
#define REG_SW_EN_VDEC_LAT02SOC_E 0
#define REG_SW_EN_VDEC_SYS2CORE0 ckgen00(0x1dac)
#define REG_SW_EN_VDEC_SYS2CORE0_S 1
#define REG_SW_EN_VDEC_SYS2CORE0_E 1
#define REG_SW_EN_VDEC_SYS2SOC ckgen00(0x1db0)
#define REG_SW_EN_VDEC_SYS2SOC_S 0
#define REG_SW_EN_VDEC_SYS2SOC_E 0
#define REG_SW_EN_XTAL_24M2CORE0 ckgen00(0x1db0)
#define REG_SW_EN_XTAL_24M2CORE0_S 1
#define REG_SW_EN_XTAL_24M2CORE0_E 1
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE ckgen00(0x1db8)
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE_S 0
#define REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0_MERGE_E 0
#define REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI ckgen00(0x1e00)
#define REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI_S 0
#define REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI ckgen00(0x1e04)
#define REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI ckgen00(0x1e08)
#define REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI ckgen00(0x1e0c)
#define REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI ckgen00(0x1e10)
#define REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI ckgen00(0x1e14)
#define REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI ckgen00(0x1e18)
#define REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI ckgen00(0x1e1c)
#define REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI ckgen00(0x1e20)
#define REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI ckgen00(0x1e24)
#define REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI ckgen00(0x1e28)
#define REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI ckgen00(0x1e2c)
#define REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI ckgen00(0x1e30)
#define REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI ckgen00(0x1e34)
#define REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI ckgen00(0x1e38)
#define REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI ckgen00(0x1e3c)
#define REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI_E 0
#define REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI ckgen00(0x1e40)
#define REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI_S 0
#define REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI_E 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK ckgen00(0x1e44)
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK_S 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK_E 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO ckgen00(0x1e48)
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO_S 0
#define REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO_E 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK ckgen00(0x1e4c)
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK_S 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK_E 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO ckgen00(0x1e50)
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO_S 0
#define REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO_E 0
#define REG_SW_EN_VIVA_SH2CH10_SH ckgen00(0x1e54)
#define REG_SW_EN_VIVA_SH2CH10_SH_S 0
#define REG_SW_EN_VIVA_SH2CH10_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M1_SH ckgen00(0x1e58)
#define REG_SW_EN_VIVA_SH2CH_M1_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M1_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M2_SH ckgen00(0x1e5c)
#define REG_SW_EN_VIVA_SH2CH_M2_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M2_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M3_SH ckgen00(0x1e60)
#define REG_SW_EN_VIVA_SH2CH_M3_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M3_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M4_SH ckgen00(0x1e64)
#define REG_SW_EN_VIVA_SH2CH_M4_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M4_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M5_SH ckgen00(0x1e68)
#define REG_SW_EN_VIVA_SH2CH_M5_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M5_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M6_SH ckgen00(0x1e6c)
#define REG_SW_EN_VIVA_SH2CH_M6_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M6_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M7_SH ckgen00(0x1e70)
#define REG_SW_EN_VIVA_SH2CH_M7_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M7_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M8_SH ckgen00(0x1e74)
#define REG_SW_EN_VIVA_SH2CH_M8_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M8_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M9_SH ckgen00(0x1e78)
#define REG_SW_EN_VIVA_SH2CH_M9_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M9_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M10_SH ckgen00(0x1e7c)
#define REG_SW_EN_VIVA_SH2CH_M10_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M10_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M11_SH ckgen00(0x1e80)
#define REG_SW_EN_VIVA_SH2CH_M11_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M11_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M12_SH ckgen00(0x1e84)
#define REG_SW_EN_VIVA_SH2CH_M12_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M12_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M13_SH ckgen00(0x1e88)
#define REG_SW_EN_VIVA_SH2CH_M13_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M13_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M14_SH ckgen00(0x1e8c)
#define REG_SW_EN_VIVA_SH2CH_M14_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M14_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M15_SH ckgen00(0x1e90)
#define REG_SW_EN_VIVA_SH2CH_M15_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M15_SH_E 0
#define REG_SW_EN_VIVA_SH2CH_M16_SH ckgen00(0x1e94)
#define REG_SW_EN_VIVA_SH2CH_M16_SH_S 0
#define REG_SW_EN_VIVA_SH2CH_M16_SH_E 0
#define REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE ckgen00(0x1e98)
#define REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE_S 0
#define REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE_E 0
#define REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP ckgen00(0x1e9c)
#define REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP_S 0
#define REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP_E 0
#define REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK ckgen00(0x1e9c)
#define REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK_S 1
#define REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK_E 1
#define REG_PD_SYS3PLL ckgen00(0x1ec0)
#define REG_PD_SYS3PLL_S 0
#define REG_PD_SYS3PLL_E 0
#define REG_PD_SYS3PLL_CLK_DIV2P5 ckgen00(0x1ec0)
#define REG_PD_SYS3PLL_CLK_DIV2P5_S 4
#define REG_PD_SYS3PLL_CLK_DIV2P5_E 4
#define REG_PD_SYS3PLL_CLK_DIV2 ckgen00(0x1ec0)
#define REG_PD_SYS3PLL_CLK_DIV2_S 8
#define REG_PD_SYS3PLL_CLK_DIV2_E 8
#define REG_PD_SYS3PLL_CLK_DIV3 ckgen00(0x1ec0)
#define REG_PD_SYS3PLL_CLK_DIV3_S 12
#define REG_PD_SYS3PLL_CLK_DIV3_E 12
#define REG_PD_SYS3PLL_CLK_DIV5 ckgen00(0x1ec4)
#define REG_PD_SYS3PLL_CLK_DIV5_S 0
#define REG_PD_SYS3PLL_CLK_DIV5_E 0
#define REG_PD_SYS3PLL_POSTDIV ckgen00(0x1ec4)
#define REG_PD_SYS3PLL_POSTDIV_S 4
#define REG_PD_SYS3PLL_POSTDIV_E 4
#define REG_PD_SYS3PLL_CLK_DIV30 ckgen00(0x1ec4)
#define REG_PD_SYS3PLL_CLK_DIV30_S 8
#define REG_PD_SYS3PLL_CLK_DIV30_E 8
#define REG_EN_SYS3PLL_VCO_DIV3 ckgen00(0x1ec8)
#define REG_EN_SYS3PLL_VCO_DIV3_S 0
#define REG_EN_SYS3PLL_VCO_DIV3_E 0
#define REG_EN_SYS3PLL_OCC_DIV128 ckgen00(0x1ec8)
#define REG_EN_SYS3PLL_OCC_DIV128_S 4
#define REG_EN_SYS3PLL_OCC_DIV128_E 4
#define REG_EN_SYS3PLL_XTAL ckgen00(0x1ec8)
#define REG_EN_SYS3PLL_XTAL_S 8
#define REG_EN_SYS3PLL_XTAL_E 8
#define REG_EN_SYS3PLL_TEST ckgen00(0x1ec8)
#define REG_EN_SYS3PLL_TEST_S 12
#define REG_EN_SYS3PLL_TEST_E 12
#define REG_EN_SYS3PLL_PRDT ckgen00(0x1ecc)
#define REG_EN_SYS3PLL_PRDT_S 0
#define REG_EN_SYS3PLL_PRDT_E 0
#define REG_EN_SYS3PLL_RST ckgen00(0x1ecc)
#define REG_EN_SYS3PLL_RST_S 4
#define REG_EN_SYS3PLL_RST_E 4
#define REG_GC_SYS3PLL_INPUT_DIV ckgen00(0x1ed0)
#define REG_GC_SYS3PLL_INPUT_DIV_S 0
#define REG_GC_SYS3PLL_INPUT_DIV_E 1
#define REG_GC_SYS3PLL_CP_SW ckgen00(0x1ed4)
#define REG_GC_SYS3PLL_CP_SW_S 0
#define REG_GC_SYS3PLL_CP_SW_E 1
#define REG_GC_SYS3PLL_ICTRL ckgen00(0x1ed4)
#define REG_GC_SYS3PLL_ICTRL_S 8
#define REG_GC_SYS3PLL_ICTRL_E 10
#define REG_GC_SYS3PLL_OUTPUT_DIV_FIRST ckgen00(0x1ed8)
#define REG_GC_SYS3PLL_OUTPUT_DIV_FIRST_S 0
#define REG_GC_SYS3PLL_OUTPUT_DIV_FIRST_E 1
#define REG_GC_SYS3PLL_OUTPUT_DIV ckgen00(0x1ed8)
#define REG_GC_SYS3PLL_OUTPUT_DIV_S 8
#define REG_GC_SYS3PLL_OUTPUT_DIV_E 10
#define REG_GC_SYS3PLL_LOOPDIV_FIRST ckgen00(0x1edc)
#define REG_GC_SYS3PLL_LOOPDIV_FIRST_S 0
#define REG_GC_SYS3PLL_LOOPDIV_FIRST_E 1
#define REG_GC_SYS3PLL_LOOPDIV_SECOND ckgen00(0x1ee0)
#define REG_GC_SYS3PLL_LOOPDIV_SECOND_S 0
#define REG_GC_SYS3PLL_LOOPDIV_SECOND_E 7
#define REG_RO_SYS3PLL_LOCK ckgen00(0x1ee8)
#define REG_RO_SYS3PLL_LOCK_S 0
#define REG_RO_SYS3PLL_LOCK_E 0
#define REG_TEST_SYS3PLL ckgen00(0x1ef8)
#define REG_TEST_SYS3PLL_S 0
#define REG_TEST_SYS3PLL_E 15
#define REG_PD_GPUBRDGPLL ckgen00(0x1f00)
#define REG_PD_GPUBRDGPLL_S 0
#define REG_PD_GPUBRDGPLL_E 0
#define REG_PD_GPUBRDGPLL_CLK_DIV2P5 ckgen00(0x1f00)
#define REG_PD_GPUBRDGPLL_CLK_DIV2P5_S 4
#define REG_PD_GPUBRDGPLL_CLK_DIV2P5_E 4
#define REG_PD_GPUBRDGPLL_CLK_DIV2 ckgen00(0x1f00)
#define REG_PD_GPUBRDGPLL_CLK_DIV2_S 8
#define REG_PD_GPUBRDGPLL_CLK_DIV2_E 8
#define REG_PD_GPUBRDGPLL_CLK_DIV3 ckgen00(0x1f00)
#define REG_PD_GPUBRDGPLL_CLK_DIV3_S 12
#define REG_PD_GPUBRDGPLL_CLK_DIV3_E 12
#define REG_PD_GPUBRDGPLL_CLK_DIV5 ckgen00(0x1f04)
#define REG_PD_GPUBRDGPLL_CLK_DIV5_S 0
#define REG_PD_GPUBRDGPLL_CLK_DIV5_E 0
#define REG_PD_GPUBRDGPLL_POSTDIV ckgen00(0x1f04)
#define REG_PD_GPUBRDGPLL_POSTDIV_S 4
#define REG_PD_GPUBRDGPLL_POSTDIV_E 4
#define REG_PD_GPUBRDGPLL_CLK_DIV30 ckgen00(0x1f04)
#define REG_PD_GPUBRDGPLL_CLK_DIV30_S 8
#define REG_PD_GPUBRDGPLL_CLK_DIV30_E 8
#define REG_EN_GPUBRDGPLL_VCO_DIV3 ckgen00(0x1f08)
#define REG_EN_GPUBRDGPLL_VCO_DIV3_S 0
#define REG_EN_GPUBRDGPLL_VCO_DIV3_E 0
#define REG_EN_GPUBRDGPLL_OCC_DIV128 ckgen00(0x1f08)
#define REG_EN_GPUBRDGPLL_OCC_DIV128_S 4
#define REG_EN_GPUBRDGPLL_OCC_DIV128_E 4
#define REG_EN_GPUBRDGPLL_XTAL ckgen00(0x1f08)
#define REG_EN_GPUBRDGPLL_XTAL_S 8
#define REG_EN_GPUBRDGPLL_XTAL_E 8
#define REG_EN_GPUBRDGPLL_TEST ckgen00(0x1f08)
#define REG_EN_GPUBRDGPLL_TEST_S 12
#define REG_EN_GPUBRDGPLL_TEST_E 12
#define REG_EN_GPUBRDGPLL_PRDT ckgen00(0x1f0c)
#define REG_EN_GPUBRDGPLL_PRDT_S 0
#define REG_EN_GPUBRDGPLL_PRDT_E 0
#define REG_EN_GPUBRDGPLL_RST ckgen00(0x1f0c)
#define REG_EN_GPUBRDGPLL_RST_S 4
#define REG_EN_GPUBRDGPLL_RST_E 4
#define REG_GC_GPUBRDGPLL_INPUT_DIV ckgen00(0x1f10)
#define REG_GC_GPUBRDGPLL_INPUT_DIV_S 0
#define REG_GC_GPUBRDGPLL_INPUT_DIV_E 1
#define REG_GC_GPUBRDGPLL_CP_SW ckgen00(0x1f14)
#define REG_GC_GPUBRDGPLL_CP_SW_S 0
#define REG_GC_GPUBRDGPLL_CP_SW_E 1
#define REG_GC_GPUBRDGPLL_ICTRL ckgen00(0x1f14)
#define REG_GC_GPUBRDGPLL_ICTRL_S 8
#define REG_GC_GPUBRDGPLL_ICTRL_E 10
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST ckgen00(0x1f18)
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST_S 0
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST_E 1
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV ckgen00(0x1f18)
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_S 8
#define REG_GC_GPUBRDGPLL_OUTPUT_DIV_E 10
#define REG_GC_GPUBRDGPLL_LOOPDIV_FIRST ckgen00(0x1f1c)
#define REG_GC_GPUBRDGPLL_LOOPDIV_FIRST_S 0
#define REG_GC_GPUBRDGPLL_LOOPDIV_FIRST_E 1
#define REG_GC_GPUBRDGPLL_LOOPDIV_SECOND ckgen00(0x1f20)
#define REG_GC_GPUBRDGPLL_LOOPDIV_SECOND_S 0
#define REG_GC_GPUBRDGPLL_LOOPDIV_SECOND_E 7
#define REG_RO_GPUBRDGPLL_LOCK ckgen00(0x1f28)
#define REG_RO_GPUBRDGPLL_LOCK_S 0
#define REG_RO_GPUBRDGPLL_LOCK_E 0
#define REG_TEST_GPUBRDGPLL ckgen00(0x1f38)
#define REG_TEST_GPUBRDGPLL_S 0
#define REG_TEST_GPUBRDGPLL_E 15
#define REG_PD_APUBUSPLL ckgen00(0x1f40)
#define REG_PD_APUBUSPLL_S 0
#define REG_PD_APUBUSPLL_E 0
#define REG_PD_APUBUSPLL_CLK_DIV2P5 ckgen00(0x1f40)
#define REG_PD_APUBUSPLL_CLK_DIV2P5_S 4
#define REG_PD_APUBUSPLL_CLK_DIV2P5_E 4
#define REG_PD_APUBUSPLL_CLK_DIV2 ckgen00(0x1f40)
#define REG_PD_APUBUSPLL_CLK_DIV2_S 8
#define REG_PD_APUBUSPLL_CLK_DIV2_E 8
#define REG_PD_APUBUSPLL_CLK_DIV3 ckgen00(0x1f40)
#define REG_PD_APUBUSPLL_CLK_DIV3_S 12
#define REG_PD_APUBUSPLL_CLK_DIV3_E 12
#define REG_PD_APUBUSPLL_CLK_DIV5 ckgen00(0x1f44)
#define REG_PD_APUBUSPLL_CLK_DIV5_S 0
#define REG_PD_APUBUSPLL_CLK_DIV5_E 0
#define REG_PD_APUBUSPLL_POSTDIV ckgen00(0x1f44)
#define REG_PD_APUBUSPLL_POSTDIV_S 4
#define REG_PD_APUBUSPLL_POSTDIV_E 4
#define REG_PD_APUBUSPLL_CLK_DIV30 ckgen00(0x1f44)
#define REG_PD_APUBUSPLL_CLK_DIV30_S 8
#define REG_PD_APUBUSPLL_CLK_DIV30_E 8
#define REG_EN_APUBUSPLL_VCO_DIV3 ckgen00(0x1f48)
#define REG_EN_APUBUSPLL_VCO_DIV3_S 0
#define REG_EN_APUBUSPLL_VCO_DIV3_E 0
#define REG_EN_APUBUSPLL_OCC_DIV128 ckgen00(0x1f48)
#define REG_EN_APUBUSPLL_OCC_DIV128_S 4
#define REG_EN_APUBUSPLL_OCC_DIV128_E 4
#define REG_EN_APUBUSPLL_XTAL ckgen00(0x1f48)
#define REG_EN_APUBUSPLL_XTAL_S 8
#define REG_EN_APUBUSPLL_XTAL_E 8
#define REG_EN_APUBUSPLL_TEST ckgen00(0x1f48)
#define REG_EN_APUBUSPLL_TEST_S 12
#define REG_EN_APUBUSPLL_TEST_E 12
#define REG_EN_APUBUSPLL_PRDT ckgen00(0x1f4c)
#define REG_EN_APUBUSPLL_PRDT_S 0
#define REG_EN_APUBUSPLL_PRDT_E 0
#define REG_EN_APUBUSPLL_RST ckgen00(0x1f4c)
#define REG_EN_APUBUSPLL_RST_S 4
#define REG_EN_APUBUSPLL_RST_E 4
#define REG_GC_APUBUSPLL_INPUT_DIV ckgen00(0x1f50)
#define REG_GC_APUBUSPLL_INPUT_DIV_S 0
#define REG_GC_APUBUSPLL_INPUT_DIV_E 1
#define REG_GC_APUBUSPLL_CP_SW ckgen00(0x1f54)
#define REG_GC_APUBUSPLL_CP_SW_S 0
#define REG_GC_APUBUSPLL_CP_SW_E 1
#define REG_GC_APUBUSPLL_ICTRL ckgen00(0x1f54)
#define REG_GC_APUBUSPLL_ICTRL_S 8
#define REG_GC_APUBUSPLL_ICTRL_E 10
#define REG_GC_APUBUSPLL_OUTPUT_DIV_FIRST ckgen00(0x1f58)
#define REG_GC_APUBUSPLL_OUTPUT_DIV_FIRST_S 0
#define REG_GC_APUBUSPLL_OUTPUT_DIV_FIRST_E 1
#define REG_GC_APUBUSPLL_OUTPUT_DIV ckgen00(0x1f58)
#define REG_GC_APUBUSPLL_OUTPUT_DIV_S 8
#define REG_GC_APUBUSPLL_OUTPUT_DIV_E 10
#define REG_GC_APUBUSPLL_LOOPDIV_FIRST ckgen00(0x1f5c)
#define REG_GC_APUBUSPLL_LOOPDIV_FIRST_S 0
#define REG_GC_APUBUSPLL_LOOPDIV_FIRST_E 1
#define REG_GC_APUBUSPLL_LOOPDIV_SECOND ckgen00(0x1f60)
#define REG_GC_APUBUSPLL_LOOPDIV_SECOND_S 0
#define REG_GC_APUBUSPLL_LOOPDIV_SECOND_E 7
#define REG_RO_APUBUSPLL_LOCK ckgen00(0x1f68)
#define REG_RO_APUBUSPLL_LOCK_S 0
#define REG_RO_APUBUSPLL_LOCK_E 0
#define REG_TEST_APUBUSPLL ckgen00(0x1f78)
#define REG_TEST_APUBUSPLL_S 0
#define REG_TEST_APUBUSPLL_E 15
#define REG_CKG_DVBTM_TS_DIVNUM ckgen00(0x1f80)
#define REG_CKG_DVBTM_TS_DIVNUM_S 0
#define REG_CKG_DVBTM_TS_DIVNUM_E 7
#define REG_CKG_ATSC_DVB_DIV_SEL ckgen00(0x1f80)
#define REG_CKG_ATSC_DVB_DIV_SEL_S 8
#define REG_CKG_ATSC_DVB_DIV_SEL_E 10
#define REG_CKG_ATSC_DVBTC_TS_INV ckgen00(0x1f80)
#define REG_CKG_ATSC_DVBTC_TS_INV_S 11
#define REG_CKG_ATSC_DVBTC_TS_INV_E 11
#define REG_CKG_DVBTM_TS_OUT_MODE ckgen00(0x1f80)
#define REG_CKG_DVBTM_TS_OUT_MODE_S 12
#define REG_CKG_DVBTM_TS_OUT_MODE_E 12
#define REG_CKG_DEMOD_TEST_IN_EN ckgen00(0x1f80)
#define REG_CKG_DEMOD_TEST_IN_EN_S 13
#define REG_CKG_DEMOD_TEST_IN_EN_E 13
#define REG_CKG_TSOUT_PH_TUN_EN ckgen00(0x1f80)
#define REG_CKG_TSOUT_PH_TUN_EN_S 14
#define REG_CKG_TSOUT_PH_TUN_EN_E 14
#define REG_ATSC_DVB_DIV_RESET ckgen00(0x1f84)
#define REG_ATSC_DVB_DIV_RESET_S 0
#define REG_ATSC_DVB_DIV_RESET_E 0
#define REG_CKG_ATSC_TS ckgen00(0x1f88)
#define REG_CKG_ATSC_TS_S 0
#define REG_CKG_ATSC_TS_E 3
#define REG_CKG_DVBTC_TS_TOP ckgen00(0x1f8c)
#define REG_CKG_DVBTC_TS_TOP_S 8
#define REG_CKG_DVBTC_TS_TOP_E 11
#define REG_CKG_TSOUT_PH_TUN_NUM ckgen00(0x1f90)
#define REG_CKG_TSOUT_PH_TUN_NUM_S 8
#define REG_CKG_TSOUT_PH_TUN_NUM_E 12
#define REG_CKG_VIFDBB_DAC_TOP ckgen00(0x1f94)
#define REG_CKG_VIFDBB_DAC_TOP_S 0
#define REG_CKG_VIFDBB_DAC_TOP_E 3
#define REG_CKG_DACA2 ckgen00(0x1f98)
#define REG_CKG_DACA2_S 0
#define REG_CKG_DACA2_E 4
#define REG_CKG_DACB2 ckgen00(0x1f98)
#define REG_CKG_DACB2_S 8
#define REG_CKG_DACB2_E 11
#define REG_CKG_VD_SEL ckgen00(0x1fa0)
#define REG_CKG_VD_SEL_S 0
#define REG_CKG_VD_SEL_E 0
#define REG_CKG_VD_BUF_SEL ckgen00(0x1fa0)
#define REG_CKG_VD_BUF_SEL_S 4
#define REG_CKG_VD_BUF_SEL_E 4
#define REG_CKGEN00_DUMMY0 ckgen00(0x1ff0)
#define REG_CKGEN00_DUMMY0_S 0
#define REG_CKGEN00_DUMMY0_E 15
#define REG_CKGEN00_DUMMY1 ckgen00(0x1ff4)
#define REG_CKGEN00_DUMMY1_S 0
#define REG_CKGEN00_DUMMY1_E 15
#define REG_CKGEN00_DUMMY2 ckgen00(0x1ff8)
#define REG_CKGEN00_DUMMY2_S 0
#define REG_CKGEN00_DUMMY2_E 15
#define REG_CKGEN00_DUMMY3 ckgen00(0x1ffc)
#define REG_CKGEN00_DUMMY3_S 0
#define REG_CKGEN00_DUMMY3_E 15
#endif
