/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 *
 * Copyright (c) 2024 MediaTek Inc.
 */

#include "mali_kbase_platform_mtk_dtv.h"
#ifdef CONFIG_DEBUG_FS
extern int mali_debug_property;
#endif

/* Marcos to convert Mali frequency to register value */
#define GPU_CLOCK_STEP              12

/* Registers */
DEFINE_REG_BANK(GPU,        0x110800); //0x110800 ~ 0x1108ff
DEFINE_REG_BANK(GPUPLL,     0x160f00); //0x160f00 ~ 0x160fff
DEFINE_REG_BANK(CLKGEN1,    0x103300);

DEFINE_REG_BANK(MIU0,       0x101200);
DEFINE_REG_BANK(MIU1,       0x100600);

//bank for WROR and RROR
DEFINE_REG_BANK(RROR,       0x162100); //0x162100 ~ 0x1621ff
DEFINE_REG_BANK(WROR,       0x161000); //0x161000 ~ 0x1610ff

//reg for RROR
DEFINE_REG(RROR, ror_bypass,           0x00, 0, 0);
DEFINE_REG(RROR, ror_status_clear,     0x00, 8, 8);
DEFINE_REG(RROR, ror_inorder,          0x01, 0, 0);
DEFINE_REG(RROR, miu_hw_arb_update,    0x1f, 8, 8);

//req for WROR
DEFINE_REG(WROR, ror_bypass,           0x00, 0, 0);
DEFINE_REG(WROR, ror_status_clear,     0x00, 8, 8);
DEFINE_REG(WROR, ror_inorder,          0x01, 0, 0);
DEFINE_REG(WROR, miu_hw_arb_update,    0x1f, 8, 8);

//reg for g3d_status_clr
DEFINE_REG(GPU,  g3d_status_clear,     0x61, 3, 3);

DEFINE_REG(GPU, soft_reset,            0x0,  0, 0);
DEFINE_REG(GPU, secure_sw_reset,       0x0, 1, 1);
DEFINE_REG(GPU, sram_sd_en,            0x43, 3, 3);
DEFINE_REG(GPU, dynamic_clk_gating_en, 0x4b, 8, 8);
DEFINE_REG(GPU, gpu_dram_mask_en,      0x5b, 0, 0);
DEFINE_REG(GPU, rreq_rd_len0,          0x60, 8, 10);
DEFINE_REG(GPU, rreq_rd_len1,          0x61, 5, 7);

DEFINE_REG(GPU, riu,            0x6a,  0, 0);
DEFINE_REG(GPU, miu0_start,     0x75,  0, 15);
DEFINE_REG(GPU, miu0_end,       0x76,  0, 15);
DEFINE_REG(GPU, miu1_start,     0x77,  0, 15);
DEFINE_REG(GPU, miu1_end,       0x78,  0, 15);
DEFINE_REG(GPU, nodefine_hit_r, 0x7b,  4, 4);

DEFINE_REG(GPUPLL, ctrl0,       0x3,   0, 0);
DEFINE_REG(GPUPLL, ctrl1,       0x4,   0, 7);

DEFINE_REG(CLKGEN1, ckg_gpu,    0x20,  0, 0);

DEFINE_REG(MIU0, dram_size,     0x69, 12, 15);
DEFINE_REG(MIU1, dram_size,     0x69, 12, 15);

#if MTK_DTV_GPU_MFDEC
DEFINE_REG(GPU, mfdec_y_start_low,       0x18,  0, 15);
DEFINE_REG(GPU, mfdec_y_start_high,      0x19,  0, 5);
DEFINE_REG(GPU, mfdec_y_end_low,         0x1a,  0, 15);
DEFINE_REG(GPU, mfdec_y_end_high,        0x1b,  0, 5);
DEFINE_REG(GPU, mfdec_uv_start_low,      0x1c,  0, 15);
DEFINE_REG(GPU, mfdec_uv_start_high,     0x1d,  0, 5);
DEFINE_REG(GPU, mfdec_uv_end_low,        0x1e,  0, 15);
DEFINE_REG(GPU, mfdec_uv_end_high,       0x1f,  0, 5);
DEFINE_REG(GPU, mfdec_adr_idx,           0x3a,  0, 3);
DEFINE_REG(GPU, mfdec_adr_update,        0x3a,  4, 4);
DEFINE_REG(GPU, mfdec_rd_len,            0x41,  0, 2);
DEFINE_REG(GPU, mfdec_async_mode,        0x42, 13, 13);
DEFINE_REG(GPU, mfdec_divider_en,        0x42, 14, 14);
DEFINE_REG(GPU, mfdec_valid,             0x52,  0, 15);
DEFINE_REG(GPU, video_pitch,             0x53,  0, 14);
DEFINE_REG(GPU, mfdec_16b_mode,          0x54,  0, 15);
DEFINE_REG(GPU, mfdec_off,               0x6a,  1, 1);

DEFINE_REG_BANK(DISP_MFDEC0, 0x122d00);
DEFINE_REG(DISP_MFDEC0, mfdec_detile_rst,          0x29, 0, 0);

DEFINE_REG(DISP_MFDEC0, prg_fb_type,               0x8,  0, 1);
DEFINE_REG(DISP_MFDEC0, prg_fb_idx,                0x8,  4, 7);
DEFINE_REG(DISP_MFDEC0, fb_para_data_low,          0x9,  0, 15);
DEFINE_REG(DISP_MFDEC0, fb_para_data_high,         0xa,  0, 15);

#endif

