/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef MTK_MOD_H
#define MTK_MOD_H
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>

#define MOD_LABEL "[MOD] "

#ifndef TRUE
#define TRUE (1)
#endif
#ifndef FALSE
#define FALSE (0)
#endif


/* ============================================================================================== */
/* ------------------------------------------- Macros ------------------------------------------- */
/* ============================================================================================== */


#define LOG_LEVEL_MASK    (0xffff)
#define LOG_LEVEL_NORMAL  (1)
#define LOG_LEVEL_FATAL   (2)
#define LOG_LEVEL_ERROR   (3)
#define LOG_LEVEL_WARNING (4)
#define LOG_LEVEL_INFO    (5)
#define LOG_LEVEL_DEBUG   (6)


#define MOD_MSG_POINTER_CHECK() \
		do { \
			pr_err(MOD_LABEL"[%s,%d] pointer is NULL\n", __func__, __LINE__); \
			dump_stack(); \
		} while (0)

#define MOD_MSG_RETURN_CHECK(result) \
			pr_err(MOD_LABEL"[%s,%d] return is %d\n", __func__, __LINE__, (result))

#define MOD_GET_TIMESTAMP(tv) \
		do { \
			struct timespec ts; \
			ktime_get_ts(&ts); \
			((struct timeval *)tv)->tv_sec = ts.tv_sec; \
			((struct timeval *)tv)->tv_usec = ts.tv_nsec / EARC_NSEC_PER_USEC; \
		} while (0)

typedef enum {
	E_MOD_V1_EN_DELTA_B2P2_SRAM2SCACE = 0,
	E_MOD_V1_EN_GUCD_18_LUT2_SRAM2SCACE,
	E_MOD_V1_EN_GUCD_256_LUT2_SRAM2SCACE,
	E_MOD_V1_EN_HSY_8P3_SRAM2SCACE,
	E_MOD_V1_EN_HSY_8P_SRAM2SCACE,
	E_MOD_V1_EN_LCE_ACE_SRAM2SCACE,
	E_MOD_V1_EN_VIP_ACE_SRAM2SCACE,
	E_MOD_V1_EN_XC_FS2SCACE_HSY,
	E_MOD_V1_EN_XC_FS2SCACE_VIP,
	E_MOD_V1_EN_XTAL_12M2SCACE,
	E_MOD_V1_EN_XTAL_24M2SCACE,
	E_MOD_V1_EN_DV_HW5_SRAM2SCDV,
	E_MOD_V1_EN_XC_FN_22SCDV,
	E_MOD_V1_EN_XC_FN2SCDV,
	E_MOD_V1_EN_XTAL_12M2SCDV,
	E_MOD_V1_EN_XTAL_24M2SCDV,
	E_MOD_V1_EN_SIDCLK_HD02SCIP,
	E_MOD_V1_EN_SIDCLK_HD12SCIP,
	E_MOD_V1_EN_SIDCLK_HD22SCIP,
	E_MOD_V1_EN_SIDCLK_HD32SCIP,
	E_MOD_V1_EN_UCD_ST_SRAM2SCIP,
	E_MOD_V1_EN_XC_ADC2SCIP,
	E_MOD_V1_EN_XC_DBG2MIU2SCIP,
	E_MOD_V1_EN_XC_DIP02SCIP,
	E_MOD_V1_EN_XC_DIP12SCIP,
	E_MOD_V1_EN_XC_DIP22SCIP,
	E_MOD_V1_EN_XC_DISP_MFDEC2SCIP,
	E_MOD_V1_EN_XC_ED02SCIP,
	E_MOD_V1_EN_XC_ED12SCIP,
	E_MOD_V1_EN_XC_FD2SCIP,
	E_MOD_V1_EN_XC_FN2SCIP,
	E_MOD_V1_EN_XC_FS2SCIP,
	E_MOD_V1_EN_XC_HD2MIU_M2SCIP,
	E_MOD_V1_EN_XC_HD2MIU_S2SCIP,
	E_MOD_V1_EN_XC_HDMI02SCIP,
	E_MOD_V1_EN_XC_HDMI12SCIP,
	E_MOD_V1_EN_XC_HDMI22SCIP,
	E_MOD_V1_EN_XC_HDMI32SCIP,
	E_MOD_V1_EN_XC_ID02SCIP,
	E_MOD_V1_EN_XC_ID12SCIP,
	E_MOD_V1_EN_XC_IP2_SRC2SCIP,
	E_MOD_V1_EN_XC_OD_DELTA2SCIP,
	E_MOD_V1_EN_XC_OD2SCIP,
	E_MOD_V1_EN_XC_SLOW2SCIP,
	E_MOD_V1_EN_XC_UCD_STAT2SCIP,
	E_MOD_V1_EN_XC_VD2SCIP,
	E_MOD_V1_EN_XC_VE2SCIP,
	E_MOD_V1_EN_XC_VEIN2SCIP,
	E_MOD_V1_EN_XTAL_12M2SCIP,
	E_MOD_V1_EN_XTAL_24M2SCIP,
	E_MOD_V1_EN_XTAL_IP12SCIP,
	E_MOD_V1_EN_DIP1_HVSP_SRAM2SCMW,
	E_MOD_V1_EN_DIP1_XVYCC_SRAM2SCMW,
	E_MOD_V1_EN_HSY_8P3_SRAM2SCMW,
	E_MOD_V1_EN_HSY_8P_SRAM2SCMW,
	E_MOD_V1_EN_RGB_3DLUT_SRAM2SCMW,
	E_MOD_V1_EN_XC_FD2SCMW,
	E_MOD_V1_EN_XC_FN2SCMW,
	E_MOD_V1_EN_XC_FS2SCMW,
	E_MOD_V1_EN_XC_OD2SCMW,
	E_MOD_V1_EN_XTAL_24M2SCMW,
	E_MOD_V1_EN_XVYCC_SRAM2SCMW,
	E_MOD_V1_EN_DISP_MFDEC2SCNR,
	E_MOD_V1_EN_XC_FN2SCNR,
	E_MOD_V1_EN_XTAL_24M2SCNR,
	E_MOD_V1_EN_DBK_HW_SRAM2SCPQ,
	E_MOD_V1_EN_SCNR_HDR_SRAM2SCPQ,
	E_MOD_V1_EN_SPF_HDBK_SRAM2SCPQ,
	E_MOD_V1_EN_VDBK_SRAM2SCPQ,
	E_MOD_V1_EN_XC_FN2SCPQ_SPF,
	E_MOD_V1_EN_XC_FN2SCPQ_DOLBY,
	E_MOD_V1_EN_XTAL_24M2SCPQ,
	E_MOD_V1_EN_DELTA_B2P_SRAM2SCSCL,
	E_MOD_V1_EN_GUCD_18_SRAM2SCSCL,
	E_MOD_V1_EN_GUCD_256_SRAM2SCSCL,
	E_MOD_V1_EN_HSY_SP3_SRAM2SCSCL,
	E_MOD_V1_EN_HSY_SP_SRAM2SCSCL,
	E_MOD_V1_EN_HVSP_STP1_SRAM2SCSCL,
	E_MOD_V1_EN_HVSP_STP2_SRAM2SCSCL,
	E_MOD_V1_EN_LCE_SCL_SRAM2SCSCL,
	E_MOD_V1_EN_VIP_PQ_SRAM2SCSCL,
	E_MOD_V1_EN_XC_FD2SCSCL,
	E_MOD_V1_EN_XC_FN2SCSCL,
	E_MOD_V1_EN_XC_FS2SCSCL,
	E_MOD_V1_EN_XC_OD_DELTA2SCSCL,
	E_MOD_V1_EN_XC_OD2SCSCL,
	E_MOD_V1_EN_XTAL_12M2SCSCL,
	E_MOD_V1_EN_XTAL_24M2SCSCL,
	E_MOD_V1_EN_AISR_HVSP_SRAM2SCSR,
	E_MOD_V1_EN_AISR_SRAM2SCSR,
	E_MOD_V1_EN_AISR_SRAM_PH_12SCSR,
	E_MOD_V1_EN_XC_AISR2SCSR,
	E_MOD_V1_EN_XC_FN2SCSR,
	E_MOD_V1_EN_XC_FS2SCSR,
	E_MOD_V1_EN_XC_SR_ALAI2SCSR,
	E_MOD_V1_EN_XC_SR_SRAM_SHARE2SCSR,
	E_MOD_V1_EN_XC_SRS2SCSR,
	E_MOD_V1_EN_XTAL_12M2SCSR,
	E_MOD_V1_EN_XTAL_24M2SCSR,
	E_MOD_V1_EN_DEMURA_SRAM2SCTCON,
	E_MOD_V1_EN_GOP0_SRAM2SCTCON,
	E_MOD_V1_EN_GOP1_SRAM2SCTCON,
	E_MOD_V1_EN_GOP2_SRAM2SCTCON,
	E_MOD_V1_EN_GOP3_SRAM2SCTCON,
	E_MOD_V1_EN_LD_EDGE2D_SRAM2SCTCON,
	E_MOD_V1_EN_LDCOMP_SRAM2SCTCON,
	E_MOD_V1_EN_LDM_GA_SRAM2SCTCON,
	E_MOD_V1_EN_LDMCG_SRAM2SCTCON,
	E_MOD_V1_EN_LPQ_PA_SRAM2SCTCON,
	E_MOD_V1_EN_OSD_DV_HW5_SRAM2SCTCON,
	E_MOD_V1_EN_PADJ_SRAM2SCTCON,
	E_MOD_V1_EN_PANEL_GA_SRAM2SCTCON,
	E_MOD_V1_EN_XC_AFBC2SCTCON,
	E_MOD_V1_EN_XC_FD_ABF2SCTCON,
	E_MOD_V1_EN_XC_FD_DV2SCTCON,
	E_MOD_V1_EN_XC_FD_GOP02SCTCON,
	E_MOD_V1_EN_XC_FD2SCTCON,
	E_MOD_V1_EN_XC_FN2SCTCON,
	E_MOD_V1_EN_XC_FS2SCTCON,
	E_MOD_V1_EN_XC_GOP0_DST2SCTCON,
	E_MOD_V1_EN_XC_GOP2SCTCON,
	E_MOD_V1_EN_XC_GOP_SCL2SCTCON,
	E_MOD_V1_EN_XC_GOPC_DST2SCTCON,
	E_MOD_V1_EN_XC_GOPG_DST2SCTCON,
	E_MOD_V1_EN_XC_OD_DELTA2SCTCON,
	E_MOD_V1_EN_XC_OD_DELTA_META2SCTCON,
	E_MOD_V1_EN_XC_OD_DIV22SCTCON,
	E_MOD_V1_EN_XC_OD_DIV42SCTCON,
	E_MOD_V1_EN_XC_OD_EDGE2SCTCON,
	E_MOD_V1_EN_XC_OD2SCTCON,
	E_MOD_V1_EN_XC_OD_META2SCTCON,
	E_MOD_V1_EN_XC_OD_OSD2SCTCON,
	E_MOD_V1_EN_XC_OD_OSD_META2SCTCON,
	E_MOD_V1_EN_XTAL_12M2SCTCON,
	E_MOD_V1_EN_XTAL_24M2SCTCON,
	E_MOD_V1_EN_SMI2SCACE,
	E_MOD_V1_EN_SMI2SCDV,
	E_MOD_V1_EN_SMI2SCMW,
	E_MOD_V1_EN_SMI2SCPQ,
	E_MOD_V1_EN_SMI2SCSCL,
	E_MOD_V1_EN_SMI2SCSR,
	E_MOD_V1_EN_DAP2FRCIOPM,
	E_MOD_V1_EN_RV55DAP_JTAG_TCK2FRCIOPM,
	E_MOD_V1_EN_XTAL_12M2FRCIOPM,
	E_MOD_V1_EN_FRC_FUART02FRCIOPM,
	E_MOD_V1_EN_FRC_MSPI02FRCIOPM,
	E_MOD_V1_EN_FRC_UART02FRCIOPM,
	E_MOD_V1_EN_FRC_UART12FRCIOPM,
	E_MOD_V1_EN_MOD_A_ODCLK2MOD_A,
	E_MOD_V1_EN_XTAL_12M2MOD_A,
	E_MOD_V1_EN_LPLL_SYN_8642FPLL,
	E_MOD_V1_EN_MOD_D_ODCLK2MOD_D,
	E_MOD_V1_EN_MOD_D_ODCLK2LVDS,
	E_MOD_V1_EN_V1_ODCLK2V1,
	E_MOD_V1_EN_V1_ODCLK_STG12V1,
	E_MOD_V1_EN_V1_ODCLK_STG22V1,
	E_MOD_V1_EN_V1_ODCLK_STG32V1,
	E_MOD_V1_EN_V1_ODCLK_STG42V1,
	E_MOD_V1_EN_V1_ODCLK_STG52V1,
	E_MOD_V1_EN_V1_ODCLK_STG62V1,
	E_MOD_V1_EN_V1_ODCLK_STG72V1,
	E_MOD_V1_EN_MOD_V1_SR_WCLK2V1,
	E_MOD_V1_EN_V1_MOD_SR_RCLK2V1,
	E_MOD_V1_EN_V1_MOD_SR_RCLK_PRE02V1,
	E_MOD_V1_EN_V1_MOD_SR_RCLK_PRE12V1,
	E_MOD_V1_EN_V1_MOD_SR_RCLK_FINIAL2V1,
	E_MOD_V1_EN_V1_ODCLK_STG82V1,
	E_MOD_V1_EN_V1_ODCLK_STG92V1,
	E_MOD_V1_EN_MOD_V1_SR_WCLK2VBY1_V1,
	E_MOD_V1_EN_V2_ODCLK_STG32V2,
	E_MOD_V1_EN_MOD_V2_SR_WCLK2V2,
	E_MOD_V1_EN_V2_MOD_SR_RCLK2V2,
	E_MOD_V1_EN_V2_MOD_SR_RCLK_PRE02V2,
	E_MOD_V1_EN_V2_MOD_SR_RCLK_PRE12V2,
	E_MOD_V1_EN_LPLL_SYN_4322FPLL,
	E_MOD_V1_EN_XTAL_24M2FPLL,
	E_MOD_V1_EN_XC_SUB_DC02SCIP,
	E_MOD_V1_EN_XC_TGEN_WIN2SCIP,
	E_MOD_V1_EN_XC_VEDAC2SCIP,
	E_MOD_V1_EN_SMI2SCM,
	E_MOD_V1_EN_SMI2SCMO,
	E_MOD_V1_EN_LPLL_SYN_864_PIPE2FPLL,
	E_B2R_V1_EN_DC0_SRAM2SCIP,
	E_B2R_V1_EN_XC_DC02SCIP,
	E_MOD_V1_EN_NUM,
} EN_MOD_CLK_V1_EN;

typedef enum {
	E_MOD_V2_EN_LPLL_SYN_4322FPLL = 0,
	E_MOD_V2_EN_MOD_A_ODCLK2MOD_A,
	E_MOD_V2_EN_MOD_D_ODCLK2MOD_D,
	E_MOD_V2_EN_MOD_D_ODCLK2LVDS,
	E_MOD_V2_EN_MOD_V1_SR_WCLK2V1,
	E_MOD_V2_EN_MOD_V1_SR_WCLK2VBY1_V1,
	E_MOD_V2_EN_MOD_V2_SR_WCLK2V2,
	E_MOD_V2_EN_V1_MOD_SR_RCLK2V1,
	E_MOD_V2_EN_V1_ODCLK2V1,
	E_MOD_V2_EN_V1_ODCLK_STG12V1,
	E_MOD_V2_EN_V1_ODCLK_STG22V1,
	E_MOD_V2_EN_V1_ODCLK_STG32V1,
	E_MOD_V2_EN_V1_ODCLK_STG42V1,
	E_MOD_V2_EN_V1_ODCLK_STG52V1,
	E_MOD_V2_EN_V1_ODCLK_STG62V1,
	E_MOD_V2_EN_V1_ODCLK_STG72V1,
	E_MOD_V2_EN_V1_ODCLK_STG82V1,
	E_MOD_V2_EN_V1_ODCLK_STG92V1,
	E_MOD_V2_EN_V2_MOD_SR_RCLK2V2,
	E_MOD_V2_EN_V2_ODCLK_STG32V2,
	E_MOD_V2_EN_XTAL_12M2MOD_A,
	E_MOD_V2_EN_XTAL_24M2FPLL,
	E_MOD_V2_EN_V1_MOD_SR_RCLK_FINIAL2V1,
	E_MOD_V2_EN_V1_MOD_SR_RCLK_PRE02V1,
	E_MOD_V2_EN_V1_MOD_SR_RCLK_PRE12V1,
	E_MOD_V2_EN_V2_MOD_SR_RCLK_PRE02V2,
	E_MOD_V2_EN_V2_MOD_SR_RCLK_PRE12V2,
	E_MOD_V2_EN_DELTA_B2P2_SRAM2SCACE,
	E_MOD_V2_EN_GUCD_18_LUT2_SRAM2SCACE,
	E_MOD_V2_EN_GUCD_256_LUT2_SRAM2SCACE,
	E_MOD_V2_EN_HSY_8P3_SRAM2SCACE,
	E_MOD_V2_EN_HSY_8P_SRAM2SCACE,
	E_MOD_V2_EN_LCE_ACE_SRAM2SCACE,
	E_MOD_V2_EN_SMI2SCACE,
	E_MOD_V2_EN_VIP_ACE_SRAM2SCACE,
	E_MOD_V2_EN_XC_FS2SCACE_HSY,
	E_MOD_V2_EN_XC_FS2SCACE_VIP,
	E_MOD_V2_EN_XTAL_12M2SCACE,
	E_MOD_V2_EN_XTAL_24M2SCACE,
	E_MOD_V2_EN_DV_HW5_SRAM2SCDV,
	E_MOD_V2_EN_SMI2SCDV,
	E_MOD_V2_EN_XC_FN_22SCDV,
	E_MOD_V2_EN_XC_FN2SCDV,
	E_MOD_V2_EN_XTAL_12M2SCDV,
	E_MOD_V2_EN_XTAL_24M2SCDV,
	E_MOD_V2_EN_SIDCLK_HD02SCIP,
	E_MOD_V2_EN_SIDCLK_HD12SCIP,
	E_MOD_V2_EN_SIDCLK_HD22SCIP,
	E_MOD_V2_EN_SIDCLK_HD32SCIP,
	E_MOD_V2_EN_UCD_ST_SRAM2SCIP,
	E_MOD_V2_EN_XC_ADC2SCIP,
	E_MOD_V2_EN_XC_DBG2MIU2SCIP,
	E_MOD_V2_EN_XC_DIP02SCIP,
	E_MOD_V2_EN_XC_DIP12SCIP,
	E_MOD_V2_EN_XC_DIP22SCIP,
	E_MOD_V2_EN_XC_DISP_MFDEC2SCIP,
	E_MOD_V2_EN_XC_ED02SCIP,
	E_MOD_V2_EN_XC_ED12SCIP,
	E_MOD_V2_EN_XC_FD2SCIP,
	E_MOD_V2_EN_XC_FN2SCIP,
	E_MOD_V2_EN_XC_FS2SCIP,
	E_MOD_V2_EN_XC_HD2MIU_M2SCIP,
	E_MOD_V2_EN_XC_HD2MIU_S2SCIP,
	E_MOD_V2_EN_XC_HDMI02SCIP,
	E_MOD_V2_EN_XC_HDMI12SCIP,
	E_MOD_V2_EN_XC_HDMI22SCIP,
	E_MOD_V2_EN_XC_HDMI32SCIP,
	E_MOD_V2_EN_XC_ID02SCIP,
	E_MOD_V2_EN_XC_ID12SCIP,
	E_MOD_V2_EN_XC_IP2_SRC2SCIP,
	E_MOD_V2_EN_XC_OD_DELTA2SCIP,
	E_MOD_V2_EN_XC_OD2SCIP,
	E_MOD_V2_EN_XC_SLOW2SCIP,
	E_MOD_V2_EN_XC_SUB_DC02SCIP,
	E_MOD_V2_EN_XC_TGEN_WIN2SCIP,
	E_MOD_V2_EN_XC_UCD_STAT2SCIP,
	E_MOD_V2_EN_XC_VD2SCIP,
	E_MOD_V2_EN_XC_VE2SCIP,
	E_MOD_V2_EN_XC_VEDAC2SCIP,
	E_MOD_V2_EN_XC_VEIN2SCIP,
	E_MOD_V2_EN_XTAL_12M2SCIP,
	E_MOD_V2_EN_XTAL_24M2SCIP,
	E_MOD_V2_EN_XTAL_IP12SCIP,
	E_MOD_V2_EN_DIP1_HVSP_SRAM2SCMW,
	E_MOD_V2_EN_DIP1_XVYCC_SRAM2SCMW,
	E_MOD_V2_EN_HSY_8P3_SRAM2SCMW,
	E_MOD_V2_EN_HSY_8P_SRAM2SCMW,
	E_MOD_V2_EN_PQ_GAMMA_SRAM2SCMW,
	E_MOD_V2_EN_RGB_3DLUT_SRAM2SCMW,
	E_MOD_V2_EN_SMI2SCMW,
	E_MOD_V2_EN_XC_FD2SCMW,
	E_MOD_V2_EN_XC_FN2SCMW,
	E_MOD_V2_EN_XC_FS2SCMW,
	E_MOD_V2_EN_XC_OD2SCMW,
	E_MOD_V2_EN_XTAL_24M2SCMW,
	E_MOD_V2_EN_XVYCC_SRAM2SCMW,
	E_MOD_V2_EN_DISP_MFDEC2SCNR,
	E_MOD_V2_EN_XC_FN2SCNR,
	E_MOD_V2_EN_XTAL_24M2SCNR,
	E_MOD_V2_EN_DBK_HW_SRAM2SCPQ,
	E_MOD_V2_EN_SCNR_HDR_SRAM2SCPQ,
	E_MOD_V2_EN_SMI2SCPQ,
	E_MOD_V2_EN_SPF_HDBK_SRAM2SCPQ,
	E_MOD_V2_EN_VDBK_SRAM2SCPQ,
	E_MOD_V2_EN_XC_FN2SCPQ_SPF,
	E_MOD_V2_EN_XC_FN2SCPQ_DOLBY,
	E_MOD_V2_EN_XTAL_24M2SCPQ,
	E_MOD_V2_EN_DELTA_B2P_SRAM2SCSCL,
	E_MOD_V2_EN_GUCD_18_SRAM2SCSCL,
	E_MOD_V2_EN_GUCD_256_SRAM2SCSCL,
	E_MOD_V2_EN_HSY_SP3_SRAM2SCSCL,
	E_MOD_V2_EN_HSY_SP_SRAM2SCSCL,
	E_MOD_V2_EN_HVSP_STP1_SRAM2SCSCL,
	E_MOD_V2_EN_HVSP_STP2_SRAM2SCSCL,
	E_MOD_V2_EN_LCE_SCL_SRAM2SCSCL,
	E_MOD_V2_EN_SMI2SCSCL,
	E_MOD_V2_EN_VIP_PQ_SRAM2SCSCL,
	E_MOD_V2_EN_XC_FD2SCSCL,
	E_MOD_V2_EN_XC_FN2SCSCL,
	E_MOD_V2_EN_XC_FS2SCSCL,
	E_MOD_V2_EN_XC_OD_DELTA2SCSCL,
	E_MOD_V2_EN_XC_OD2SCSCL,
	E_MOD_V2_EN_XTAL_12M2SCSCL,
	E_MOD_V2_EN_XTAL_24M2SCSCL,
	E_MOD_V2_EN_AISR_HVSP_SRAM2SCSR,
	E_MOD_V2_EN_AISR_SRAM2SCSR,
	E_MOD_V2_EN_AISR_SRAM_PH_12SCSR,
	E_MOD_V2_EN_SMI2SCSR,
	E_MOD_V2_EN_XC_AISR2SCSR,
	E_MOD_V2_EN_XC_FS2SCSR,
	E_MOD_V2_EN_XC_SR_ALAI2SCSR,
	E_MOD_V2_EN_XC_SR_SRAM_SHARE2SCSR,
	E_MOD_V2_EN_XC_SRS2SCSR,
	E_MOD_V2_EN_XTAL_12M2SCSR,
	E_MOD_V2_EN_XTAL_24M2SCSR,
	E_MOD_V2_EN_GOP0_SRAM2SCTCON,
	E_MOD_V2_EN_GOP1_SRAM2SCTCON,
	E_MOD_V2_EN_GOP2_SRAM2SCTCON,
	E_MOD_V2_EN_GOP3_SRAM2SCTCON,
	E_MOD_V2_EN_PADJ_SRAM2SCTCON,
	E_MOD_V2_EN_PANEL_GA_SRAM2SCTCON,
	E_MOD_V2_EN_XC_FD2SCTCON,
	E_MOD_V2_EN_XC_FN2SCTCON,
	E_MOD_V2_EN_XC_FS2SCTCON,
	E_MOD_V2_EN_XC_GOP2SCTCON,
	E_MOD_V2_EN_XC_GOP_SCL2SCTCON,
	E_MOD_V2_EN_XC_OD_DELTA2SCTCON,
	E_MOD_V2_EN_XC_OD_DELTA_META2SCTCON,
	E_MOD_V2_EN_XC_OD2SCTCON,
	E_MOD_V2_EN_XC_OD_META2SCTCON,
	E_MOD_V2_EN_XC_OD_OSD2SCTCON,
	E_MOD_V2_EN_XC_OD_OSD_META2SCTCON,
	E_MOD_V2_EN_XTAL_12M2SCTCON,
	E_MOD_V2_EN_XTAL_24M2SCTCON,

	E_MOD_V2_EN_NUM,
} EN_MOD_CLK_V2_EN;

typedef enum {
	E_MOD_V3_EN_DAP2FRCIOPMRV55 = 0,
	E_MOD_V3_EN_FRC_FUART02FRCIOPMRV55,
	E_MOD_V3_EN_FRC_MSPI02FRCIOPMRV55,
	E_MOD_V3_EN_FRC_UART02FRCIOPMRV55,
	E_MOD_V3_EN_FRC_UART12FRCIOPMRV55,
	E_MOD_V3_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55,
	E_MOD_V3_EN_XTAL_12M2FRCIOPMRV55,
	E_MOD_V3_EN_LPLL_SYN_864_PIPE2FPLL,
	E_MOD_V3_EN_LPLL_SYN_4322FPLL,
	E_MOD_V3_EN_MOD_A_ODCLK2MOD_A,
	E_MOD_V3_EN_MOD_D_ODCLK2MOD_D,
	E_MOD_V3_EN_MOD_D_ODCLK2LVDS,
	E_MOD_V3_EN_MOD_V1_SR_WCLK2V1,
	E_MOD_V3_EN_MOD_V1_SR_WCLK2VBY1_V1,
	E_MOD_V3_EN_MOD_V2_SR_WCLK2V2,
	E_MOD_V3_EN_V1_MOD_SR_RCLK2V1,
	E_MOD_V3_EN_V1_ODCLK2V1,
	E_MOD_V3_EN_V1_ODCLK_STG12V1,
	E_MOD_V3_EN_V1_ODCLK_STG22V1,
	E_MOD_V3_EN_V1_ODCLK_STG32V1,
	E_MOD_V3_EN_V1_ODCLK_STG42V1,
	E_MOD_V3_EN_V1_ODCLK_STG52V1,
	E_MOD_V3_EN_V1_ODCLK_STG62V1,
	E_MOD_V3_EN_V1_ODCLK_STG72V1,
	E_MOD_V3_EN_V1_ODCLK_STG82V1,
	E_MOD_V3_EN_V1_ODCLK_STG92V1,
	E_MOD_V3_EN_V2_MOD_SR_RCLK2V2,
	E_MOD_V3_EN_V2_ODCLK_STG32V2,
	E_MOD_V3_EN_XTAL_12M2MOD_A,
	E_MOD_V3_EN_XTAL_24M2FPLL,
	E_MOD_V3_EN_V1_MOD_SR_RCLK_FINIAL2V1,
	E_MOD_V3_EN_V1_MOD_SR_RCLK_PRE02V1,
	E_MOD_V3_EN_V1_MOD_SR_RCLK_PRE12V1,
	E_MOD_V3_EN_V2_MOD_SR_RCLK_PRE02V2,
	E_MOD_V3_EN_V2_MOD_SR_RCLK_PRE12V2,
	E_MOD_V3_EN_SMI2SCACE,
	E_MOD_V3_EN_SMI2SCDV,
	E_MOD_V3_EN_SMI2SCMW,
	E_MOD_V3_EN_SMI2SCPQ,
	E_MOD_V3_EN_SMI2SCSCL,
	E_MOD_V3_EN_SMI2SCSR,
	E_B2R_V3_EN_DC0_SRAM2SCIP,
	E_B2R_V3_EN_XC_DC02SCIP,

	E_MOD_V3_EN_NUM,
} EN_MOD_CLK_V3_EN;

typedef enum {
	E_MOD_V4_EN_SMI2SCBE = 0,
	E_MOD_V4_EN_SMI2SCIP,
	E_MOD_V4_EN_SMI2SCTC,

	E_MOD_V4_EN_NUM,
} EN_MOD_CLK_V4_EN;

typedef enum {
	E_MOD_V5_EN_SMI2SCIP = 0,
	E_MOD_V5_EN_SMI2SCBE,
	E_MOD_V5_EN_SMI2SCTC,
	E_MOD_V5_EN_SMI2SCFE_EMI,
	E_MOD_V5_EN_SMI2SCFE_SMI_IP,
	E_MOD_V5_EN_DAP2FRCMISC,
	E_MOD_V5_EN_R2_FRC2FRCMISC,
	E_MOD_V5_EN_XTAL_12M2FRCMISC,

	E_MOD_V5_EN_NUM,
} EN_MOD_CLK_V5_EN;

typedef enum {
	E_MOD_V6_EN_SMI2SCBE = 0,
	E_MOD_V6_EN_XC_DIP02SCBE,
	E_MOD_V6_EN_XC_DIP12SCBE,
	E_MOD_V6_EN_SMI2SCIP,
	E_MOD_V6_EN_EN_XC_FN2XC_DC0_CG_SCIP,
	E_MOD_V6_EN_SMI2SCTC,
	E_MOD_V6_EN_NUM,
} EN_MOD_CLK_V6_EN;

enum EN_MOD_CLK_V7_EN {
	E_MOD_V7_EN_SMI2SCACE = 0,
	E_MOD_V7_EN_SMI2SCACE_GALS,
	//E_MOD_V7_EN_XC_FN2SCACE,
	E_MOD_V7_EN_XC_IP_AUL_CLK_MERGE2SCACE_TMP,
	E_MOD_V7_EN_XTAL_24M2SCACE,
	E_MOD_V7_EN_XTAL_24M2SCACE_MBIST,
	E_MOD_V7_EN_SIDCLK_DP02SCIP,
	E_MOD_V7_EN_SIDCLK_DP12SCIP,
	E_MOD_V7_EN_SIDCLK_DSC2SCIP,
	E_MOD_V7_EN_SIDCLK_HD02SCIP,
	E_MOD_V7_EN_SIDCLK_HD12SCIP,
	E_MOD_V7_EN_SIDCLK_HD22SCIP,
	E_MOD_V7_EN_SIDCLK_HD32SCIP,
	E_MOD_V7_EN_XC_ADC2SCIP,
	E_MOD_V7_EN_XC_DBG2MIU_M2SCIP,
	E_MOD_V7_EN_XC_DBG2MIU_S2SCIP,
	E_MOD_V7_EN_XC_DP02SCIP,
	E_MOD_V7_EN_XC_DP12SCIP,
	E_MOD_V7_EN_XC_DSC2SCIP,
	//E_MOD_V7_EN_XC_FN2SCIP,
	E_MOD_V7_EN_XC_FN2XC_DC0_CG_SCIP,
	E_MOD_V7_EN_XC_FN2XC_SUB_DC0_CG_SCIP,
	E_MOD_V7_EN_XC_FN2XC_SUB1_DC0_CG_SCIP,
	E_MOD_V7_EN_XC_FN2XC_MFDEC_CG_SCIP,
	E_MOD_V7_EN_XC_GPU_MFDEC2SCIP,
	E_MOD_V7_EN_XC_HDMI02SCIP,
	E_MOD_V7_EN_XC_HDMI12SCIP,
	E_MOD_V7_EN_XC_HDMI22SCIP,
	E_MOD_V7_EN_XC_HDMI32SCIP,
	E_MOD_V7_EN_XC_ID02SCIP,
	E_MOD_V7_EN_XC_ID12SCIP,
	E_MOD_V7_EN_XC_SC2FPLL2SCIP,
	E_MOD_V7_EN_XC_SLOW2SCIP,
	E_MOD_V7_EN_XC_TGEN_WIN2SCIP,
	E_MOD_V7_EN_XC_VD2SCIP,
	E_MOD_V7_EN_XTAL_12M2SCIP,
	E_MOD_V7_EN_XTAL_24M2SCIP,
	E_MOD_V7_EN_XTAL_24M2SCIP_MBIST,
	E_MOD_V7_EN_XTAL_IP12SCIP,
	E_MOD_V7_EN_FRC_FCLK_2XPLUS2SCMW,
	E_MOD_V7_EN_SMI2SCMW,
	//E_MOD_V7_EN_SMI2SCMW_GALS,
	E_MOD_V7_EN_XC_DIP02SCMW,
	E_MOD_V7_EN_XC_DIP12SCMW,
	E_MOD_V7_EN_XC_DIP22SCMW,
	//E_MOD_V7_EN_XC_FN2SCMW,
	E_MOD_V7_EN_XC_OD_1P2SCMW,
	E_MOD_V7_EN_XC_OD_B2P2SCMW,
	E_MOD_V7_EN_XTAL_12M2SCMW,
	E_MOD_V7_EN_XTAL_24M2SCMW,
	E_MOD_V7_EN_XTAL_24M2SCMW_MBIST,
	//E_MOD_V7_EN_XC_FN2SCNR,
	E_MOD_V7_EN_XTAL_24M2SCNR,
	E_MOD_V7_EN_XTAL_24M2SCNR_MBIST,
	E_MOD_V7_EN_MCU_NONPM2SCSR,
	E_MOD_V7_EN_SMI2SCSR,
	E_MOD_V7_EN_XC_FN2SCSR,
	E_MOD_V7_EN_XTAL_24M2SCSR,
	E_MOD_V7_EN_XTAL_24M2SCSR_MBIST,
	E_MOD_V7_EN_MCU_NONPM2SCTCON,
	E_MOD_V7_EN_SMI2SCTCON,
	E_MOD_V7_EN_XC_FN2SCTCON,
	//E_MOD_V7_EN_XC_GOP2SCTCON,
	E_MOD_V7_EN_XC_OD_1P2SCTCON,
	//E_MOD_V7_EN_XC_OD_B2P2SCTCON,
	E_MOD_V7_EN_XC_OD2SCTCON,
	E_MOD_V7_EN_XC_OD_META2SCTCON,
	E_MOD_V7_EN_XC_OD_OSD_META2SCTCON,
	E_MOD_V7_EN_XC_OD_OSD2SCTCON,
	E_MOD_V7_EN_XTAL_24M2SCTCON,
	E_MOD_V7_EN_XTAL_24M2SCTCON_MBIST,
	E_MOD_V7_EN_FRC_FCLK_2XPLUS2SCACE,
	E_MOD_V7_EN_NUM,
};

int mtk_mod_enable_clock(struct clk *st_mod_clk_en);
int mtk_mod_disable_clock(struct clk *st_mod_clk_disable);

int mtk_mod_clk_initV1(struct device *dev);
int mtk_mod_clk_initV2(struct device *dev);
int mtk_mod_clk_initV3(struct device *dev);
int mtk_mod_clk_initV4(struct device *dev);
int mtk_mod_clk_initV5(struct device *dev);
int mtk_mod_clk_initV6(struct device *dev);
int mtk_mod_clk_initV7(struct device *dev);

int mtk_video_mod_enable_clkV1(bool bEn, EN_MOD_CLK_V1_EN enClkSel);
int mtk_video_mod_enable_clkV2(bool bEn, EN_MOD_CLK_V2_EN enClkSel);
int mtk_video_mod_enable_clkV3(bool bEn, EN_MOD_CLK_V3_EN enClkSel);
int mtk_video_mod_enable_clkV4(bool bEn, EN_MOD_CLK_V4_EN enClkSel);
int mtk_video_mod_enable_clkV5(bool bEn, EN_MOD_CLK_V5_EN enClkSel);
int mtk_video_mod_enable_clkV6(bool bEn, EN_MOD_CLK_V6_EN enClkSel);
int mtk_video_mod_enable_clkV7(bool bEn, enum EN_MOD_CLK_V7_EN enClkSel);

#endif  //#ifndef MTK_EARC_H

