/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
//Page TSP6_TEST_1
#define REG_0000_TSP6 (0x000)
	#define TSP6_REG_PCR64_3_RIU_0_0000 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0004_TSP6 (0x004)
	#define TSP6_REG_PCR64_3_RIU_1_0004 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0008_TSP6 (0x008)
	#define TSP6_REG_PCR64_3_RIU_2_0008 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_000C_TSP6 (0x00C)
	#define TSP6_REG_PCR64_3_RIU_3_000C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0010_TSP6 (0x010)
	#define TSP6_REG_PCR64_4_RIU_0_0010 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0014_TSP6 (0x014)
	#define TSP6_REG_PCR64_4_RIU_1_0014 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0018_TSP6 (0x018)
	#define TSP6_REG_PCR64_4_RIU_2_0018 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_001C_TSP6 (0x01C)
	#define TSP6_REG_PCR64_4_RIU_3_001C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0040_TSP6 (0x040)
	#define TSP6_REG_PCR2_CONFIG_0040_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_PCR2_CONFIG_0040_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_PCR2_CONFIG_0040_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_PCR2_CONFIG_0040_7_4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_PCR2_CONFIG_0040_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0044_TSP6 (0x044)
	#define TSP6_REG_PIDFLT_PCR2_0_0044 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0048_TSP6 (0x048)
	#define TSP6_REG_PIDFLT_PCR2_1_0048 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_004C_TSP6 (0x04C)
	#define TSP6_REG_PCR2_LATCH_0_004C_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_TSP6 (0x050)
	#define TSP6_REG_PCR2_LATCH_1_0050_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_0054_TSP6 (0x054)
	#define TSP6_REG_PCR2_EXT_LATCH_0054_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_PCR2_EXT_LATCH_0054_9_1 Fld(9, 1, AC_MSKW10)//[9:1]
	#define TSP6_REG_PCR2_EXT_LATCH_0054_15_10 Fld(6, 10, AC_MSKB1)//[15:10]
#define REG_0058_TSP6 (0x058)
	#define TSP6_REG_PCR3_CONFIG_0058_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_PCR3_CONFIG_0058_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_PCR3_CONFIG_0058_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_PCR3_CONFIG_0058_7_4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_PCR3_CONFIG_0058_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_005C_TSP6 (0x05C)
	#define TSP6_REG_PIDFLT_PCR3_0_005C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0060_TSP6 (0x060)
	#define TSP6_REG_PIDFLT_PCR3_1_0060 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0064_TSP6 (0x064)
	#define TSP6_REG_PCR3_LATCH_0_0064_15_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_TSP6 (0x068)
	#define TSP6_REG_PCR3_LATCH_1_0068_31_16 Fld(16, 16, AC_FULLW32)//[31:16]
#define REG_006C_TSP6 (0x06C)
	#define TSP6_REG_PCR3_EXT_LATCH_006C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_PCR3_EXT_LATCH_006C_9_1 Fld(9, 1, AC_MSKW10)//[9:1]
	#define TSP6_REG_PCR3_EXT_LATCH_006C_15_10 Fld(6, 10, AC_MSKB1)//[15:10]
#define REG_0080_TSP6 (0x080)
	#define TSP6_REG_CLK_GATING_0080_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_CLK_GATING_0080_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_CLK_GATING_0080_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_CLK_GATING_0080_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_CLK_GATING_0080_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLK_GATING_0080_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_CLK_GATING_0080_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_CLK_GATING_0080_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_CLK_GATING_0080_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_CLK_GATING_0080_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_CLK_GATING_0080_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_CLK_GATING_0080_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_CLK_GATING_0080_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_CLK_GATING_0080_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_CLK_GATING_0080_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_CLK_GATING_0080_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0084_TSP6 (0x084)
	#define TSP6_REG_CLK_GATING_FIQ_0084_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_CLK_GATING_FIQ_0084_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_CLK_GATING_FIQ_0084_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_CLK_GATING_FIQ_0084_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_CLK_GATING_FIQ_0084_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLK_GATING_FIQ_0084_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_CLK_GATING_FIQ_0084_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_CLK_GATING_FIQ_0084_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_CLK_GATING_FIQ_0084_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_CLK_GATING_FIQ_0084_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_CLK_GATING_FIQ_0084_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_CLK_GATING_FIQ_0084_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_CLK_GATING_FIQ_0084_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_CLK_GATING_FIQ_0084_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0088_TSP6 (0x088)
	#define TSP6_REG_CLK_GATING_VQ_0088_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_CLK_GATING_VQ_0088_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_CLK_GATING_VQ_0088_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_CLK_GATING_VQ_0088_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_CLK_GATING_VQ_0088_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLK_GATING_VQ_0088_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_CLK_GATING_VQ_0088_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_CLK_GATING_VQ_0088_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_CLK_GATING_VQ_0088_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_CLK_GATING_VQ_0088_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_CLK_GATING_VQ_0088_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_CLK_GATING_VQ_0088_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_CLK_GATING_VQ_0088_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_CLK_GATING_VQ_0088_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_008C_TSP6 (0x08C)
	#define TSP6_REG_MIU_CLK_GATING_008C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_MIU_CLK_GATING_008C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_MIU_CLK_GATING_008C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_MIU_CLK_GATING_008C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_MIU_CLK_GATING_008C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_MIU_CLK_GATING_008C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_MIU_CLK_GATING_008C_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_MIU_CLK_GATING_008C_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_MIU_CLK_GATING_008C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_MIU_CLK_GATING_008C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_MIU_CLK_GATING_008C_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_MIU_CLK_GATING_008C_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_MIU_CLK_GATING_008C_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_MIU_CLK_GATING_008C_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_MIU_CLK_GATING_008C_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_MIU_CLK_GATING_008C_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0090_TSP6 (0x090)
	#define TSP6_REG_RESET_CTRL0_0090_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL0_0090_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL0_0090_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL0_0090_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL0_0090_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL0_0090_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL0_0090_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_RESET_CTRL0_0090_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL0_0090_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL0_0090_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL0_0090_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL0_0090_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL0_0090_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL0_0090_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0094_TSP6 (0x094)
	#define TSP6_REG_RESET_CTRL1_0094_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL1_0094_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL1_0094_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL1_0094_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL1_0094_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL1_0094_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL1_0094_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_RESET_CTRL1_0094_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_RESET_CTRL1_0094_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL1_0094_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL1_0094_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL1_0094_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL1_0094_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL1_0094_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL1_0094_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0098_TSP6 (0x098)
	#define TSP6_REG_RESET_CTRL2_0098_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL2_0098_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL2_0098_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL2_0098_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL2_0098_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL2_0098_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL2_0098_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_RESET_CTRL2_0098_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_RESET_CTRL2_0098_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL2_0098_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL2_0098_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL2_0098_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL2_0098_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL2_0098_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL2_0098_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_009C_TSP6 (0x09C)
	#define TSP6_REG_RESET_CTRL3_009C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL3_009C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL3_009C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL3_009C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL3_009C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL3_009C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL3_009C_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_RESET_CTRL3_009C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL3_009C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL3_009C_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL3_009C_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL3_009C_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL3_009C_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL3_009C_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00A0_TSP6 (0x0A0)
	#define TSP6_REG_RESET_CTRL4_00A0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL4_00A0_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL4_00A0_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL4_00A0_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL4_00A0_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL4_00A0_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL4_00A0_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_RESET_CTRL4_00A0_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL4_00A0_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL4_00A0_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL4_00A0_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL4_00A0_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL4_00A0_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL4_00A0_15_14 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00A4_TSP6 (0x0A4)
	#define TSP6_REG_RESET_CTRL5_00A4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL5_00A4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL5_00A4_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL5_00A4_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL5_00A4_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL5_00A4_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL5_00A4_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_RESET_CTRL5_00A4_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL5_00A4_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL5_00A4_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL5_00A4_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL5_00A4_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL5_00A4_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL5_00A4_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_RESET_CTRL5_00A4_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00A8_TSP6 (0x0A8)
	#define TSP6_REG_RESET_CTRL6_00A8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RESET_CTRL6_00A8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RESET_CTRL6_00A8_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RESET_CTRL6_00A8_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RESET_CTRL6_00A8_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RESET_CTRL6_00A8_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RESET_CTRL6_00A8_7_6 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_RESET_CTRL6_00A8_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RESET_CTRL6_00A8_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RESET_CTRL6_00A8_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RESET_CTRL6_00A8_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RESET_CTRL6_00A8_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RESET_CTRL6_00A8_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RESET_CTRL6_00A8_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_RESET_CTRL6_00A8_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00B0_TSP6 (0x0B0)
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_PRE_FIFO_STATUS_00B0_15_12 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00B4_TSP6 (0x0B4)
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_PRE_FIFO_CTRL_00B4_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00B8_TSP6 (0x0B8)
	#define TSP6_REG_TSIF_ALP0_EN_00B8 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_P_SEL_ALP0_00B8 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_EXT_SYNC_SEL_ALP0_00B8 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_TS_DATA_SWAP_ALP0_00B8 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_TS_DATA_1BIT_SWAP_ALP0_00B8 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLR_OVERFLOW_ALP0_00B8 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PKT_CHK_SIZE_ALP0_00B8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00BC_TSP6 (0x0BC)
	#define TSP6_REG_TSIF_ALP_FI_EN_00BC Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_P_SEL_ALP_FI_00BC Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_EXT_SYNC_SEL_ALP_FI_00BC Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_TS_DATA_SWAP_ALP_FI_00BC Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_TS_DATA_1BIT_SWAP_ALP_FI_00BC Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLR_OVERFLOW_ALP_FI_00BC Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PKT_CHK_SIZE_ALP_FI_00BC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C0_TSP6 (0x0C0)
	#define TSP6_REG_TSIF_ALP1_EN_00C0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_P_SEL_ALP1_00C0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_EXT_SYNC_SEL_ALP1_00C0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_TS_DATA_SWAP_ALP1_00C0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_TS_DATA_1BIT_SWAP_ALP1_00C0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLR_OVERFLOW_ALP1_00C0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PKT_CHK_SIZE_ALP1_00C0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C4_TSP6 (0x0C4)
	#define TSP6_REG_TSIF_ALP2_EN_00C4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_P_SEL_ALP2_00C4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_EXT_SYNC_SEL_ALP2_00C4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_TS_DATA_SWAP_ALP2_00C4 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_TS_DATA_1BIT_SWAP_ALP2_00C4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLR_OVERFLOW_ALP2_00C4 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PKT_CHK_SIZE_ALP2_00C4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C8_TSP6 (0x0C8)
	#define TSP6_REG_CLK_GATING_1_00C8_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_CLK_GATING_1_00C8_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_CLK_GATING_1_00C8_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_CLK_GATING_1_00C8_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_CLK_GATING_1_00C8_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]

//Page TSP6_TEST_2
#define REG_00CC_TSP6 (0x0CC)
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_POWER_SAVING_CONFIG_0_00CC_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_POWER_SAVING_CONFIG_FI_00CC_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00D0_TSP6 (0x0D0)
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_POWER_SAVING_CONFIG_1_00D0_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_POWER_SAVING_CONFIG_2_00D0_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00D4_TSP6 (0x0D4)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PRE_FIFO0_00D4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PRE_FIFO_FI_00D4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00D8_TSP6 (0x0D8)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PRE_FIFO1_00D8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PRE_FIFO2_00D8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00DC_TSP6 (0x0DC)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PID_MATCH0_00DC Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PID_MATCH_FI_00DC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00E0_TSP6 (0x0E0)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PID_MATCH1_00E0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PID_MATCH2_00E0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00E4_TSP6 (0x0E4)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_FIQ0_00E4 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_FIQ1_00E4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00E8_TSP6 (0x0E8)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PKT_CONVERTER0_00E8 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PKT_CONVERTER_FI_00E8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00EC_TSP6 (0x0EC)
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PKT_CONVERTER1_00EC Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_CHECK_TIMEOUT_CNT_PKT_CONVERTER2_00EC Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0100_TSP6 (0x100)
	#define TSP6_REG_SYNC_REG_CTRL_0100_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_SYNC_REG_CTRL_0100_7_4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_SYNC_REG_CTRL_0100_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
	#define TSP6_REG_SYNC_REG_CTRL_0100_RESERVED_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_SYNC_REG_CTRL_0100_RESERVED_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_SYNC_REG_CTRL_0100_RESERVED_3 Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_0104_TSP6 (0x104)
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_RESERVED_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_STR2MI_WP_LD_CONFIG_0104_RESERVED_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_FORCE_SYNC_EN_CONFIG_0104_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0108_TSP6 (0x108)
	#define TSP6_REG_VQRX_RP_LD_0108 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_SEC_PKT_BURST_EN_0108 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_SEC_PKT_FLUSH_EN_0108 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_REC_DATA3_INV_EN_0108 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_REC_DATA4_INV_EN_0108 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_PID_BYPASS3_REC_0108 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_PID_BYPASS4_REC_0108 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_REC_ALL3_0108 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_REC_ALL4_0108 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_VQRX2MIU_ADDR_R_EXT_0108 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_010C_TSP6 (0x10C)
	#define TSP6_REG_VQRX2MIU_ADDR_R_0_010C Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0110_TSP6 (0x110)
	#define TSP6_REG_VQRX2MIU_ADDR_R_1_0110 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0114_TSP6 (0x114)
	#define TSP6_REG_SYNC_BYTE_ENABLE_CONFIG0_0114_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_SYNC_BYTE_ENABLE_CONFIG0_0114_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0118_TSP6 (0x118)
	#define TSP6_REG_SYNC_BYTE_ENABLE_CONFIG1_0118_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_SYNC_BYTE_ENABLE_CONFIG1_0118_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0124_TSP6 (0x124)
	#define TSP6_REG_MASK_SCR_PVRFLT3_EN_0124 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_MASK_SCR_PVRFLT4_EN_0124 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_PVR3_BLOCK_DIS_0124 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_PVR4_BLOCK_DIS_0124 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_PVR5_BLOCK_DIS_0124 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_PVR6_BLOCK_DIS_0124 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_0128_TSP6 (0x128)
	#define TSP6_REG_FORCE_SYNC_BYTE_VAL_PVR1_0128 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FORCE_SYNC_BYTE_VAL_PVR2_0128 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_012C_TSP6 (0x12C)
	#define TSP6_REG_AUD_SECURE_FLAG_ENABLE_012C_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_AUD_SECURE_FLAG_ENABLE_012C_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_AUD_SECURE_FLAG_ENABLE_012C_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_AUD_SECURE_FLAG_ENABLE_012C_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_AUDB_SECURE_FLAG_ENABLE_012C_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_AUDB_SECURE_FLAG_ENABLE_012C_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_AUDB_SECURE_FLAG_ENABLE_012C_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_AUDB_SECURE_FLAG_ENABLE_012C_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_AUDC_SECURE_FLAG_ENABLE_012C_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_AUDC_SECURE_FLAG_ENABLE_012C_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_AUDC_SECURE_FLAG_ENABLE_012C_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_AUDC_SECURE_FLAG_ENABLE_012C_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_AUDD_SECURE_FLAG_ENABLE_012C_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_AUDD_SECURE_FLAG_ENABLE_012C_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_AUDD_SECURE_FLAG_ENABLE_012C_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_AUDD_SECURE_FLAG_ENABLE_012C_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0130_TSP6 (0x130)
	#define TSP6_REG_SW_RST_SECFLT_DMAW_0130 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_SW_RST_SECFLT_DMAR_0130 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_SW_RST_SECFLT_IND_0130 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_SW_RST_SECFLT_ABT_0130 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_SECFLT_ABT_REQ_EN_0130_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_SECFLT_ABT_REQ_EN_0130_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_SECFLT_ABT_REQ_EN_0130_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_SECFLT_ABT_REQ_EN_0130_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_SECFLT_ABT_RR_PRI_EN_0130 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_SECFLT_ABT_ST_BUSY_EN_0130 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_FIX_DMA_DONE_0130 Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_0134_TSP6 (0x134)
	#define TSP6_REG_RLD_ALL_RIU_0134_0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_4 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_6 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_7 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_8 Fld(1, 8, AC_MSKB1)//[8:8]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_9 Fld(1, 9, AC_MSKB1)//[9:9]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_10 Fld(1, 10, AC_MSKB1)//[10:10]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_RESERVED_11 Fld(1, 11, AC_MSKB1)//[11:11]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_RESERVED_12 Fld(1, 12, AC_MSKB1)//[12:12]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_RESERVED_13 Fld(1, 13, AC_MSKB1)//[13:13]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_RESERVED_14 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_RLD_ALL_CONFIG_0134_RESERVED_15 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0138_TSP6 (0x138)
	#define TSP6_REG_MUX_PVR1_SRC_0138 Fld(4, 0, AC_MSKB0)//[3:0]
		#define TSP6_REG_MUX_PVR_SRC_PVRFLT1 (0)
		#define TSP6_REG_MUX_PVR_SRC_PVRFLT2 (1)
		#define TSP6_REG_MUX_PVR_SRC_PVRFLT3 (2)
		#define TSP6_REG_MUX_PVR_SRC_PVRFLT4 (3)
		#define TSP6_REG_MUX_PVR_SRC_ALP0    (4)
		#define TSP6_REG_MUX_PVR_SRC_ALP_FI  (5)
		#define TSP6_REG_MUX_PVR_SRC_ALP1    (6)
		#define TSP6_REG_MUX_PVR_SRC_ALP2    (7)
	#define TSP6_REG_MUX_PVR2_SRC_0138 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_MUX_PVR3_SRC_0138 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_MUX_PVR4_SRC_0138 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_013C_TSP6 (0x13C)
	#define TSP6_REG_MUX_PVR5_SRC_013C Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_MUX_PVR6_SRC_013C Fld(4, 4, AC_MSKB0)//[7:4]
#define REG_0140_TSP6 (0x140)
	#define TSP6_REG_FIQ0_SRC_FILTER_0_0140_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_1_0140_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0144_TSP6 (0x144)
	#define TSP6_REG_FIQ0_SRC_FILTER_2_0144_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_3_0144_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0148_TSP6 (0x148)
	#define TSP6_REG_FIQ0_SRC_FILTER_4_0148_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_5_0148_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_014C_TSP6 (0x14C)
	#define TSP6_REG_FIQ0_SRC_FILTER_6_014C_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_7_014C_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0150_TSP6 (0x150)
	#define TSP6_REG_FIQ0_SRC_FILTER_8_0150_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_9_0150_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0154_TSP6 (0x154)
	#define TSP6_REG_FIQ0_SRC_FILTER_10_0154_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_11_0154_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0158_TSP6 (0x158)
	#define TSP6_REG_FIQ0_SRC_FILTER_12_0158_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_13_0158_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_015C_TSP6 (0x15C)
	#define TSP6_REG_FIQ0_SRC_FILTER_14_015C_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_SRC_FILTER_15_015C_15_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0160_TSP6 (0x160)
	#define TSP6_REG_FIQ0_SRC_FILTER_EN_0160 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0164_TSP6 (0x164)
	#define TSP6_REG_FIQ0_FILTER_0_PID_0164 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP6_REG_FIQ0_FILTER_0_EN_0164 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0168_TSP6 (0x168)
	#define TSP6_REG_FIQ0_FILTER_1_PID_0168 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP6_REG_FIQ0_FILTER_1_EN_0168 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_016C_TSP6 (0x16C)
	#define TSP6_REG_FIQ0_FILTER_2_PID_016C Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP6_REG_FIQ0_FILTER_2_EN_016C Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0170_TSP6 (0x170)
	#define TSP6_REG_FIQ0_FILTER_3_PID_0170 Fld(13, 0, AC_MSKW10)//[12:0]
	#define TSP6_REG_FIQ0_FILTER_3_EN_0170 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0174_TSP6 (0x174)
	#define TSP6_REG_FIQ0_FILTER_0_SYNC_BYTE_0174 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_FILTER_1_SYNC_BYTE_0174 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0178_TSP6 (0x178)
	#define TSP6_REG_FIQ0_FILTER_2_SYNC_BYTE_0178 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_FIQ0_FILTER_3_SYNC_BYTE_0178 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01C0_TSP6 (0x1C0)
	#define TSP6_REG_TS_PATH_ID00_01C0_3_0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID01_01C0 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID02_01C0 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID03_01C0 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01C4_TSP6 (0x1C4)
	#define TSP6_REG_TS_PATH_ID04_01C4 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID05_01C4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID06_01C4 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID07_01C4 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01C8_TSP6 (0x1C8)
	#define TSP6_REG_TS_PATH_ID_F0_01C8 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID_F1_01C8 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID_F2_01C8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID_F3_01C8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01CC_TSP6 (0x1CC)
	#define TSP6_REG_TS_PATH_ID_F4_01CC Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID_F5_01CC Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID_F6_01CC Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID_F7_01CC Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01D0_TSP6 (0x1D0)
	#define TSP6_REG_TS_PATH_ID10_01D0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID11_01D0 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID12_01D0 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID13_01D0 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01D4_TSP6 (0x1D4)
	#define TSP6_REG_TS_PATH_ID14_01D4 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID15_01D4 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID16_01D4 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID17_01D4 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01D8_TSP6 (0x1D8)
	#define TSP6_REG_TS_PATH_ID20_01D8 Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID21_01D8 Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID22_01D8 Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID23_01D8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01DC_TSP6 (0x1DC)
	#define TSP6_REG_TS_PATH_ID24_01DC Fld(4, 0, AC_MSKB0)//[3:0]
	#define TSP6_REG_TS_PATH_ID25_01DC Fld(4, 4, AC_MSKB0)//[7:4]
	#define TSP6_REG_TS_PATH_ID26_01DC Fld(4, 8, AC_MSKB1)//[11:8]
	#define TSP6_REG_TS_PATH_ID27_01DC Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01E0_TSP6 (0x1E0)
	#define TSP6_REG_SOURCE_EXT_ID00_01E0 Fld(2, 0, AC_MSKB0)//[1:0]
	#define TSP6_REG_SOURCE_EXT_ID01_01E0 Fld(2, 2, AC_MSKB0)//[3:2]
	#define TSP6_REG_SOURCE_EXT_ID02_01E0 Fld(2, 4, AC_MSKB0)//[5:4]
	#define TSP6_REG_SOURCE_EXT_ID03_01E0 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_SOURCE_EXT_ID04_01E0 Fld(2, 8, AC_MSKB1)//[9:8]
	#define TSP6_REG_SOURCE_EXT_ID05_01E0 Fld(2, 10, AC_MSKB1)//[11:10]
	#define TSP6_REG_SOURCE_EXT_ID06_01E0 Fld(2, 12, AC_MSKB1)//[13:12]
	#define TSP6_REG_SOURCE_EXT_ID07_01E0 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01E4_TSP6 (0x1E4)
	#define TSP6_REG_SOURCE_EXT_ID_F0_01E4 Fld(2, 0, AC_MSKB0)//[1:0]
	#define TSP6_REG_SOURCE_EXT_ID_F1_01E4 Fld(2, 2, AC_MSKB0)//[3:2]
	#define TSP6_REG_SOURCE_EXT_ID_F2_01E4 Fld(2, 4, AC_MSKB0)//[5:4]
	#define TSP6_REG_SOURCE_EXT_ID_F3_01E4 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_SOURCE_EXT_ID_F4_01E4 Fld(2, 8, AC_MSKB1)//[9:8]
	#define TSP6_REG_SOURCE_EXT_ID_F5_01E4 Fld(2, 10, AC_MSKB1)//[11:10]
	#define TSP6_REG_SOURCE_EXT_ID_F6_01E4 Fld(2, 12, AC_MSKB1)//[13:12]
	#define TSP6_REG_SOURCE_EXT_ID_F7_01E4 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01E8_TSP6 (0x1E8)
	#define TSP6_REG_SOURCE_EXT_ID10_01E8 Fld(2, 0, AC_MSKB0)//[1:0]
	#define TSP6_REG_SOURCE_EXT_ID11_01E8 Fld(2, 2, AC_MSKB0)//[3:2]
	#define TSP6_REG_SOURCE_EXT_ID12_01E8 Fld(2, 4, AC_MSKB0)//[5:4]
	#define TSP6_REG_SOURCE_EXT_ID13_01E8 Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_SOURCE_EXT_ID14_01E8 Fld(2, 8, AC_MSKB1)//[9:8]
	#define TSP6_REG_SOURCE_EXT_ID15_01E8 Fld(2, 10, AC_MSKB1)//[11:10]
	#define TSP6_REG_SOURCE_EXT_ID16_01E8 Fld(2, 12, AC_MSKB1)//[13:12]
	#define TSP6_REG_SOURCE_EXT_ID17_01E8 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01EC_TSP6 (0x1EC)
	#define TSP6_REG_SOURCE_EXT_ID20_01EC Fld(2, 0, AC_MSKB0)//[1:0]
	#define TSP6_REG_SOURCE_EXT_ID21_01EC Fld(2, 2, AC_MSKB0)//[3:2]
	#define TSP6_REG_SOURCE_EXT_ID22_01EC Fld(2, 4, AC_MSKB0)//[5:4]
	#define TSP6_REG_SOURCE_EXT_ID23_01EC Fld(2, 6, AC_MSKB0)//[7:6]
	#define TSP6_REG_SOURCE_EXT_ID24_01EC Fld(2, 8, AC_MSKB1)//[9:8]
	#define TSP6_REG_SOURCE_EXT_ID25_01EC Fld(2, 10, AC_MSKB1)//[11:10]
	#define TSP6_REG_SOURCE_EXT_ID26_01EC Fld(2, 12, AC_MSKB1)//[13:12]
	#define TSP6_REG_SOURCE_EXT_ID27_01EC Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01F0_TSP6 (0x1F0)
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_0_01F0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_F_01F0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_1_01F0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_2_01F0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_ALP0_01F0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_ALP_FI_01F0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_ALP1_01F0 Fld(1, 6, AC_MSKB0)//[6:6]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_ALP2_01F0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_MM0_01F0 Fld(1, 14, AC_MSKB1)//[14:14]
	#define TSP6_REG_MERGED_MATCH_SYNC_BYTE_EN_MM1_01F0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01F4_TSP6 (0x1F4)
	#define TSP6_REG_DISABLE_PATH_ID_CHK_IN_PKT_CONVERTER_01F4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define TSP6_REG_FIX_192_UNLOCK_HANG_EN_01F4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define TSP6_REG_DISABLE_PATH_ID_CHK_IN_SRC_ID_PARSER_01F4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define TSP6_REG_SECFLT_EXT_MODE_01F4 Fld(2, 3, AC_MSKB0)//[4:3]
	#define TSP6_REG_MMT_SYNC_BYTE_01F4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01F8_TSP6 (0x1F8)
	#define TSP6_REG_INIT_TRUST_SYNC_CNT_VALUE_MM0_01F8_7_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define TSP6_REG_INIT_TRUST_SYNC_CNT_VALUE_MM1_01F8_15_8 Fld(8, 8, AC_FULLB1)//[15:8]

