/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 *
 * Copyright (c) 2023 MediaTek Inc.
 */

#include "mali_kbase_platform_mtk_dtv.h"
#ifdef CONFIG_DEBUG_FS
extern int mali_debug_property;
#endif

#ifdef MTK_DTV_DEVICE_TREE_PROBE
extern ptrdiff_t GPUBRDGPLL_vaddr;
extern ptrdiff_t CKGEN00_vaddr;
extern ptrdiff_t CKGEN01_vaddr;
extern ptrdiff_t SRAM_PD_vaddr;
extern ptrdiff_t TZPC_AID_0_vaddr;
extern ptrdiff_t X32_GPU_vaddr;
extern ptrdiff_t IOMMU_GLOBAL_vaddr;
extern ptrdiff_t X32_IOMMU_LOCAL_GPU_vaddr;
#if defined(CONFIG_MALI_DEBUG) && defined(MTK_DTV_ZEBU)
extern ptrdiff_t mtk_pm_vaddr; // for Zebu debugfs only
extern ptrdiff_t EMI_vaddr;
#endif
extern ptrdiff_t MFDEC_BKA415_vaddr;
extern ptrdiff_t MIU_vaddr;
extern ptrdiff_t GPU_MPU_BYPASS_vaddr;
extern ptrdiff_t CPU_MPU_BYPASS_vaddr;
extern ptrdiff_t X32_SMI_CTRL_vaddr;

extern ptrdiff_t CKGEN1029_vaddr;
extern ptrdiff_t CKGEN1035_vaddr;
extern ptrdiff_t CKGEN1036_vaddr;
extern ptrdiff_t CKGEN1037_vaddr;
extern ptrdiff_t CKGEN103C_vaddr;
#endif

/* Marcos to convert Mali frequency to register value */
#define GPU_CLOCK_STEP              24

/* Registers */
// c_riubase_for_cpu.h
//#define    GPUBRDGPLL                              0x200e00    //0x200e00 ~ 0x200eff
DEFINE_REG_BANK(GPUBRDGPLL, 0x100700);
//#define    CKGEN00                                 0x204000    //0x204000 ~ 0x205fff
DEFINE_REG_BANK(CKGEN00, 0x102000);
//#define    CKGEN01                                 0x206000    //0x206000 ~ 0x207fff
DEFINE_REG_BANK(CKGEN01, 0x103000);
//#define    SRAM_PD                                 0x220000    //0x220000 ~ 0x22ffff
DEFINE_REG_BANK(SRAM_PD, 0x110000);
//#define    TZPC_AID_0                              0x240600    //0x240600 ~ 0x2407ff
DEFINE_REG_BANK(TZPC_AID_0, 0x120300);
//#define    X32_GPU                                 0x5dd200    //0x5dd200 ~ 0x5dd3ff
DEFINE_REG_BANK(X32_GPU, 0x2ee900);
//#define    IOMMU_GLOBAL                            0x241c00    //0x241c00 ~ 0x241dff
DEFINE_REG_BANK(IOMMU_GLOBAL, 0x120e00);
//#define    X32_IOMMU_LOCAL_GPU                     0x5dce00    //0x5dce00 ~ 0x5dcfff
DEFINE_REG_BANK(X32_IOMMU_LOCAL_GPU, 0x2ee700);
//#define MFDEC
DEFINE_REG_BANK(MFDEC_BKA415, 0xa41500);
//#define    X32_IOMMU_BYPASS_TABLE0_GPU             0x5dc200    //0x5dc200 ~ 0x5dc3ff
DEFINE_REG_BANK(GPU_MPU_BYPASS, 0x2ee100);
//#define    IOMMU_BYPASS_TABLE_CPU_0                0x400c00    //0x400c00 ~ 0x400dff
DEFINE_REG_BANK(CPU_MPU_BYPASS, 0x200600);
//#define    X32_SMI_CTRL                            0x33e000    //0x33e000 ~ 0x33e1ff
DEFINE_REG_BANK(X32_SMI_CTRL, 0x19f000);

DEFINE_REG_BANK(CKGEN1029, 0x102900);
DEFINE_REG_BANK(CKGEN1035, 0x103500);
DEFINE_REG_BANK(CKGEN1036, 0x103600);
DEFINE_REG_BANK(CKGEN1037, 0x103700);
DEFINE_REG_BANK(CKGEN103C, 0x103C00);

//clk_fnclk
//TOP_CKGEN
DEFINE_REG(CKGEN1035, ckg_g_xc_fn, 0x34, 0, 0);
DEFINE_REG(CKGEN1037, gate_xc_fn, 0x21, 0, 0);
DEFINE_REG(CKGEN1035, ckg_s_xc_fn, 0x34, 2, 3);
//SCFE_CKGEN
DEFINE_REG(CKGEN1035, ckg_g_xc_fn_scip, 0x4C, 0, 0);
DEFINE_REG(CKGEN103C, sw_en_xc_fn2scip, 0x65, 1, 1);
//clk_gpu_mfdec
//TOP_CKGEN
DEFINE_REG(CKGEN1029, ckg_g_disp_mfdec, 0x1A, 0, 0);
DEFINE_REG(CKGEN1029, ckg_s_disp_mfdec, 0x1A, 2, 3);
//SCFE_CKGEN
DEFINE_REG(CKGEN1036, ckg_g_xc_gpu_mfdec_scip, 0x30, 0, 0);
//SCFE_CKGEN
DEFINE_REG(CKGEN103C, sw_en_xc_gpu_mfdec2scip, 0x61, 0, 0);

// MPU bypass table
DEFINE_REG(GPU_MPU_BYPASS, gpu_table0,       0x0, 0, 15);
DEFINE_REG(CPU_MPU_BYPASS, cpu_table0,       0x0, 0, 15);

//define MIU
//ToDo: Check the following list
DEFINE_REG_BANK(MIU,       0x1bf400);
DEFINE_REG(MIU, out_of_area_start,           0xc, 0, 15);
DEFINE_REG(MIU, out_of_area_start_20_16,     0xd, 0, 4);
DEFINE_REG(MIU, out_of_area_end,             0xe, 0, 15);
DEFINE_REG(MIU, out_of_area_end_20_16,       0xf, 0, 4);

//#define    EMI
#if defined(CONFIG_MALI_DEBUG) && defined(MTK_DTV_ZEBU)
DEFINE_REG_BANK(EMI, 0x1a0000);
DEFINE_DW_REG(EMI, emi0_testc_0, 0xE8, 0, 31);
DEFINE_DW_REG(EMI, emi0_testc_1, 0xF0, 0, 31);
DEFINE_DW_REG(EMI, emi1_testc_0, 0x10E8, 0, 31);
DEFINE_DW_REG(EMI, emi1_testc_1, 0x10F0, 0, 31);
#endif

DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll, 0x0, 0, 0);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div1, 0x0, 4, 4);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div2, 0x0, 8, 8);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div3, 0x0, 12, 12);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div5, 0x1, 0, 0);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_postdiv, 0x1, 4, 4);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div30, 0x1, 8, 8);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_vco_div3, 0x2, 0, 0);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_occ_div128, 0x2, 4, 4);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_xtal, 0x2, 8, 8);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_test, 0x2, 12, 12);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_prdt, 0x3, 0, 0);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_rst, 0x3, 4, 4);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_input_div, 0x4, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_cp_sw, 0x5, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_ictrl, 0x5, 8, 10);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_output_div_first, 0x6, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_output_div, 0x6, 8, 10);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_loopdiv_first, 0x7, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_loopdiv_second, 0x8, 0, 7);
DEFINE_REG(GPUBRDGPLL, ro_gpubrdgpll_lock, 0xA, 0, 0);
DEFINE_REG(GPUBRDGPLL, test_gpubrdgpll, 0xE, 0, 15);
DEFINE_REG(GPUBRDGPLL, gpubrdgpll_dummy_0, 0xF, 0, 15);
DEFINE_REG(GPUBRDGPLL, gpubrdgpll_dummy_1, 0x10, 0, 15);

DEFINE_REG(SRAM_PD,       glb_sram_pd_reg_gpu_die,           0x110, 0,  0);
DEFINE_REG(SRAM_PD,       glb_sram_pd_reg_shader_core0,      0x111, 0,  0);
DEFINE_REG(SRAM_PD,       glb_sram_pd_reg_shader_core1,      0x112, 0,  0);

DEFINE_REG(X32_GPU,   riu_apb_en,                        0x66,  0,  0);
DEFINE_REG(X32_GPU,   miu0_start,                        0x50,  0,  15);
DEFINE_REG(X32_GPU,   miu0_end,                          0x51,  0,  15);
DEFINE_REG(X32_GPU,       mfdec_rreq_rd_len,                 0x41,  0,  2);
DEFINE_REG(TZPC_AID_0,    tzpc_page_table_walk_aid,          0x00,  0,  5);
DEFINE_REG(TZPC_AID_0,    tzpc_gpu_aid,                      0x35,  8, 13);
DEFINE_REG(TZPC_AID_0,    tzpc_gpu_protected_aid,            0x36,  0,  5);
DEFINE_REG(X32_GPU,       soft_reset,                        0x00,  0,  0);
DEFINE_REG(X32_GPU,       riu_legacy_en,                     0x7f,  0,  0);
DEFINE_REG(X32_GPU,   riu_legacy_die_en,                 0x7f,  1,  1);

DEFINE_REG(CKGEN00, ckg_i_gpu_gpu_par_gp, 0x32, 1, 1);
DEFINE_REG(CKGEN00, flow_ctrl_rate_gpu_par_gp, 0x33, 0, 4);
DEFINE_REG(CKGEN00, ckg_g_xtal_12m_gpu_par_gp, 0x9E, 10, 10);
DEFINE_REG(CKGEN00, ckg_i_xtal_12m_gpu_par_gp, 0x9E, 11, 11);
DEFINE_REG(CKGEN00, ckg_g_xtal_24m_gpu_par_gp, 0xA0, 10, 10);
DEFINE_REG(CKGEN00, ckg_i_xtal_24m_gpu_par_gp, 0xA0, 11, 11);
DEFINE_REG(CKGEN00, ckg_g_disp_mfdec_gpu_par_gp, 0x49A, 8, 8);
DEFINE_REG(CKGEN00, ckg_i_disp_mfdec_gpu_par_gp, 0x49A, 9, 9);
DEFINE_REG(CKGEN00, ckg_s_disp_mfdec_gpu_par_gp, 0x49A, 10, 11);
DEFINE_REG(CKGEN00, ckg_g_bist_gpu_par_gp, 0x4D6, 8, 8);
DEFINE_REG(CKGEN00, ckg_i_bist_gpu_par_gp, 0x4D6, 9, 9);
DEFINE_REG(CKGEN00, ckg_s_bist_gpu_par_gp, 0x4D6, 10, 12);
DEFINE_REG(CKGEN00, sw_en_gpu2gpu_par_gp, 0x511, 0, 0);
DEFINE_REG(CKGEN00, sw_en_gpu_dfs2gpu_par_gp, 0x511, 1, 1);
DEFINE_REG(CKGEN00, sw_en_xtal_12m2met, 0x513, 0, 0);
DEFINE_REG(CKGEN00, sw_en_xtal_24m2syscount, 0x514, 1, 1);
DEFINE_REG(CKGEN00, flow_ctrl_rate_gpu_par_gp_sld, 0x33, 0, 0);

DEFINE_REG(CKGEN01, ckg_g_mcu_nonpm_gpu_par_gp, 0x414, 14, 14);
DEFINE_REG(CKGEN01, ckg_i_mcu_nonpm_gpu_par_gp, 0x414, 15, 15);
DEFINE_REG(CKGEN01, sw_en_disp_mfdec2gpu_par_gp, 0x559, 0, 0);
DEFINE_REG(CKGEN01, sw_en_mcu_nonpm2gpu_par_gp, 0x6DD, 12, 12);
DEFINE_REG(CKGEN01, sw_en_xtal_24m2gpu_par_gp_mbist, 0x760, 13, 13);
DEFINE_REG(CKGEN01, gpu_par_gp_test_enable, 0x77E, 0, 0);
DEFINE_REG(CKGEN01, gpu_par_gp_test_div_sel, 0x77E, 4, 6);
DEFINE_REG(CKGEN01, gpu_par_gp_test_src_sel, 0x77E, 8, 15);
DEFINE_REG(CKGEN01, gate_inv_wlock_passwd, 0x7CE, 0, 15);
DEFINE_REG(CKGEN01, all_sw_en_passwd, 0x7CF, 0, 15);
DEFINE_REG(CKGEN01, gpu_par_gp_all_sw_en_overwrite, 0x7D3, 10, 10);
DEFINE_REG(CKGEN01, gpu_par_gp_all_sw_en_value, 0x7DB, 10, 10);

DEFINE_REG(X32_GPU, gpu_protect_mode, 0x5b, 0, 0);

DEFINE_REG(X32_GPU,   mfdec_off,                         0x66,  1,  1);
DEFINE_REG(X32_GPU,   mfdec_valid,                       0x52, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_divider_en,                  0x42, 14, 14);
DEFINE_REG(X32_GPU,   mfdec_linear_mode,                 0x43,  0,  0);

DEFINE_REG(X32_GPU,   mfdec_adr_idx,                     0x3a,  0,  3);
DEFINE_REG(X32_GPU,   video_pitch,                       0x53, 0,  14);
DEFINE_REG(X32_GPU,   mfdec_y_start_15_00,               0x18, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_y_start_21_16,               0x19,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_y_end_15_00,                 0x1a, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_y_end_21_16,                 0x1b,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_uv_start_15_00,              0x1c, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_uv_start_21_16,              0x1d,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_uv_end_15_00,                0x1e, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_uv_end_21_16,                0x1f,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_adr_update,                  0x3a,  4,  4);

DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_slv_slpprot_en,    0x8,  7,  7);
DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_mst_slpprot_en,    0x8,  5,  5);
DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_slv_slpprot_rdy,   0x23, 3,  3);
DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_mst_slpprot_rdy,   0x23, 2,  2);

// gpu bridge debug register
DEFINE_REG(X32_GPU, mfdec_bri_status_sel_0, 0x40, 1, 3);
DEFINE_REG(X32_GPU, mfdec_bri_status_sel_1, 0x40, 4, 6);
DEFINE_REG(X32_GPU, bridge_idle, 0x5e, 0, 15);
DEFINE_REG(X32_GPU, gpu_bridge_idle, 0x5E, 1, 1);
DEFINE_REG(X32_GPU, mfdec_status_0, 0x67, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_0_31_16, 0x68, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_1, 0x69, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_1_31_16, 0x6A, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_0, 0x6B, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_0_31_16, 0x6C, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_1, 0x6D, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_1_31_16, 0x6E, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_sel, 0x6F, 0, 2);

// MPU
DEFINE_REG(IOMMU_GLOBAL, mpu_table_base_addr, 0x2, 0, 15);
DEFINE_REG(IOMMU_GLOBAL, mpu_table_base_addr_19_16, 0x3, 0, 3);
DEFINE_REG(IOMMU_GLOBAL, mpu_area_0_start, 0x4, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_area_0_end, 0x5, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_area_1_start, 0x6, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, mpu_area_1_end, 0x7, 0, 13);
DEFINE_REG(IOMMU_GLOBAL, iommu_mpu_table_base_area_update, 0x8, 0, 0);
DEFINE_REG(IOMMU_GLOBAL, iommu_mpu_enable, 0x9, 0, 0);
DEFINE_REG(IOMMU_GLOBAL, mpu_tlb_invalid_mode, 0xD, 0, 0);
DEFINE_REG(IOMMU_GLOBAL, mpu_tlb_invalid_start, 0xE, 0, 15);
DEFINE_REG(IOMMU_GLOBAL, mpu_tlb_invalid_end, 0xF, 0, 15);
DEFINE_REG(IOMMU_GLOBAL, iommu_mpu_tlb_invalid_fire, 0x10, 0, 0);
DEFINE_REG(IOMMU_GLOBAL, mpu_cache_invalidate_ref_idle, 0x10, 8, 8);
DEFINE_REG(IOMMU_GLOBAL, iommu_mpu_dummy, 0x13, 0, 15);

// MPU Local
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_table_enable, 0x30, 1, 1);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_table_debug_enable, 0x30, 2, 2);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_table_entry_size, 0x30, 4, 5);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_sel, 0x31, 0, 10);
// Log Clean: clean interrupt (IRQ) & log
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_clean, 0x31, 15, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_info_addr_19_4, 0x32, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_info_addr_34_20, 0x33, 0, 14);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_sr_info_0, 0x33, 15, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_log_sr_info_3_1, 0x34, 0, 2);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_acpu_log_table_value, 0x34, 3, 3);
//reg_mpu_log_info = byp_table_debug_mode_info[36]
DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_byp_acpu_log_valid, 0x34, 4, 4);

DEFINE_REG(X32_IOMMU_LOCAL_GPU, bypass_cs_only_gpu, 0x45, 0, 0);

DEFINE_REG(X32_IOMMU_LOCAL_GPU, mpu_enable_local, 0x54, 0, 15);
//0: Fault log/TLB invalidation status/PMU from generic IOMMU/MPU version
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_log_sel, 0x55, 0, 0);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_debug_client_sel, 0x55, 8, 11);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_tlb_l1_invalid_status_local, 0x56, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_hit, 0x57, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_hit_31_16, 0x58, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_hit_41_32, 0x59, 0, 9);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_miss, 0x5A, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_miss_31_16, 0x5B, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_miss_41_32, 0x5C, 0, 9);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_total, 0x5D, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_total_31_16, 0x5E, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_total_41_32, 0x5F, 0, 9);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_out_mpu, 0x60, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_out_mpu_31_16, 0x61, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_out_mpu_41_32, 0x62, 0, 9);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_en, 0x63, 8, 8);
// toggle clear hit rate counter
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_clr, 0x63, 9, 9);
// toggle clear hit rate counter
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_clr_larb1, 0x3D, 9, 9);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_index, 0x63, 12, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_internal_debug_info, 0x64, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_internal_debug_info_31_16, 0x65, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_internal_debug_info_41_32, 0x66, 0, 15);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_fault_info_valid, 0x70, 0, 0);
// fault physical address[27:12]
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_fault_info_addr_27_12, 0x71, 0, 15);
// fault physical address[34:28]
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_fault_info_addr_34_28, 0x72, 0, 6);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_detect_target_srinfo, 0x72, 8, 12); // Log target srinfo
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_detect_srinfo_en, 0x72, 13, 13); // Log sr_info enable
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_fault_info_org, 0x73, 0, 4);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_fault_info_sr, 0x73, 8, 12);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_fault_info_en_status, 0x74, 0, 1);
// Write 0 then write 1 to clean
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_pmu_fault_info_clean, 0x74, 2, 2);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, dataram_mode, 0x74, 3, 4);
DEFINE_REG(X32_IOMMU_LOCAL_GPU, iommu_mpu_tlb_invalid_fire_local, 0x77, 3, 3);

#if MTK_DTV_GPU_MFDEC
//DEFINE_REG(CKGEN00, ckg_g_disp_mfdec, 0x49a, 0, 0);
DEFINE_REG(CKGEN00, sw_en_smi2scip, 0x53B, 0, 0); //Shared by B2R/B2R lite1/B2R lite2/GPU
DEFINE_REG(CKGEN01, sw_en_xc_disp_mfdec2scip, 0x661, 0, 0);
DEFINE_REG(CKGEN01, ckg_xc_disp_mfdec_scip, 0x330, 0, 0);

DEFINE_REG(CKGEN01, sw_en_xc_dc02scip, 0x65f, 0, 0);
DEFINE_REG(CKGEN01, ckg_xc_dc0_scip, 0x2c4, 0, 0);

DEFINE_REG(MFDEC_BKA415, disp_mfdec_clk_gate,     0x0, 12, 12);
DEFINE_REG(MFDEC_BKA415, mfdec_reset,             0x0, 0, 0);
DEFINE_REG(MFDEC_BKA415, yc_base_sep_en,          0x0, 2, 2);
DEFINE_REG(MFDEC_BKA415, mfdec_reset_sec,         0xae, 0, 0);
DEFINE_REG(MFDEC_BKA415, gpu_dec_sw_rst,          0x1, 10, 10);
DEFINE_REG(MFDEC_BKA415, vde_xpu_sel,             0x0, 6, 6);
DEFINE_REG(MFDEC_BKA415, dec_frame_start_xpu,     0x0, 8, 8);

DEFINE_REG(MFDEC_BKA415, mfdec_xpu_sel,           0x1,  0,  0);
DEFINE_REG(MFDEC_BKA415, gpu_mfdec_map,           0x1,  4,  4);
DEFINE_REG(MFDEC_BKA415, gpu_aid_rst,             0x2, 1, 1);

DEFINE_REG(MFDEC_BKA415, disp_mfdec_int_mask,     0x6, 0, 7);
DEFINE_REG(MFDEC_BKA415, disp_mfdec_int_en,       0x6, 8, 8);

DEFINE_REG(MFDEC_BKA415, ufod_reset_sel,          0x6, 10, 10);

// 0: gpu_sw_frame_start, 1: auto_start
DEFINE_REG(MFDEC_BKA415, gpu_main_ctrl_mode,      0xd0, 6, 7);

DEFINE_REG(MFDEC_BKA415, prg_fb_type,                   0x8,  0,  2);
DEFINE_REG(MFDEC_BKA415, prg_fb_idx,                    0x8,  4,  7);
DEFINE_REG(MFDEC_BKA415, fb_para_data_0,              0x9,  0,  15); // 64Byte unit
DEFINE_REG(MFDEC_BKA415, fb_para_data_1,             0xa,  0,  15); // 64Byte unit
//SW force mfdec cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, tagram_inv,                    0xe,  0,  0);
//SW run-time force cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, rt_tagram_inv,                 0xe,  1,  1);
//SW force mfdec2 cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, tagram_inv_2nd,                0xe,  2,  2);
//SW force mfdec cache tag ram invalidate for gpu path
DEFINE_REG(MFDEC_BKA415, tagram_inv_gpu,                0xe,  3,  3);
//SW force codec_iommu cache tag ram invalidate
DEFINE_REG(MFDEC_BKA415, vd_iommu_tagram_inv,           0xe,  4,  4);
DEFINE_REG(MFDEC_BKA415, mfd_l_cache_flush_timeout_lb,  0x12, 0,  5);
DEFINE_REG(MFDEC_BKA415, mfd_l_cache_flush_timeout_ub,  0x12, 8,  13);
//Offset DMA cache time-out enable
DEFINE_REG(MFDEC_BKA415, mfd_ofs_cache,                 0x16, 15, 15);
//Enable mfdec engine cpx data pre-fetch
DEFINE_REG(MFDEC_BKA415, mfd_cpx_pf_en,                 0x50, 12, 12);
//GPU engine idle for software reset &gpu frame end
DEFINE_REG(MFDEC_BKA415, gpu_idle,                      0xae, 6, 6);
//GPU engine active state for start transation
DEFINE_REG(MFDEC_BKA415, gpu_active,                    0xae, 7, 7);

// mfdec debug register
DEFINE_REG(MFDEC_BKA415, mfdec_dbus_l,               0x66, 0, 15);
DEFINE_REG(MFDEC_BKA415, mfdec_dbus_h,               0x67, 0, 7);
DEFINE_REG(MFDEC_BKA415, mfdec_dbus_sel,             0x67, 8, 15);
#endif
