/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 *
 * Copyright (c) 2024 MediaTek Inc.
 */

#include "mali_kbase_platform_mtk_dtv.h"
#ifdef CONFIG_DEBUG_FS
extern int mali_debug_property;
extern int mali_gpu_clock;
#endif

#ifdef MTK_DTV_DEVICE_TREE_PROBE
extern ptrdiff_t GPUBRDGPLL_vaddr;
extern ptrdiff_t CKGEN00_vaddr;
extern ptrdiff_t CKGEN01_vaddr;
extern ptrdiff_t SRAM_PD_vaddr;
extern ptrdiff_t TZPC_AID_0_vaddr;
extern ptrdiff_t X32_GPU_vaddr;
extern ptrdiff_t IOMPU_GLOBAL_vaddr;
extern ptrdiff_t IOMPU_GPU_vaddr;
extern ptrdiff_t PM_POR_vaddr;
extern ptrdiff_t TEST_CTRL_vaddr;
#if defined(CONFIG_MALI_DEBUG) && defined(MTK_DTV_ZEBU)
extern ptrdiff_t mtk_pm_vaddr; // for Zebu debugfs only
extern ptrdiff_t EMI_vaddr;
#endif
extern ptrdiff_t MFDEC_BKA415_vaddr;
extern ptrdiff_t MIU_vaddr;
extern ptrdiff_t GPU_MPU_BYPASS_vaddr;
extern ptrdiff_t CPU_MPU_BYPASS_vaddr;
extern ptrdiff_t X32_SMI_CTRL_vaddr;

extern ptrdiff_t CKGEN1029_vaddr;
extern ptrdiff_t CKGEN1035_vaddr;
extern ptrdiff_t CKGEN1036_vaddr;
extern ptrdiff_t CKGEN1037_vaddr;
extern ptrdiff_t CKGEN103A_vaddr;
extern ptrdiff_t CKGEN103C_vaddr;
extern ptrdiff_t CKGENA040_vaddr;
extern ptrdiff_t MFDEC_BKA432_vaddr;
extern ptrdiff_t MFDEC_BKA433_vaddr;
extern ptrdiff_t MFDEC_BKA412_vaddr;
extern ptrdiff_t MFDEC_BKA413_vaddr;
extern ptrdiff_t MFDEC_BKA414_vaddr;
#endif

/* Marcos to convert Mali frequency to register value */
#define GPU_CLOCK_STEP              24

/* Registers */
// c_riubase_for_cpu.h
//#define    GPUBRDGPLL                              0x200e00    //0x200e00 ~ 0x200eff
DEFINE_REG_BANK(GPUBRDGPLL, 0x100700);
//#define    CKGEN00                                 0x204000    //0x204000 ~ 0x205fff
DEFINE_REG_BANK(CKGEN00, 0x102000);
//#define    CKGEN01                                 0x206000    //0x206000 ~ 0x207fff
DEFINE_REG_BANK(CKGEN01, 0x103000);
//#define    SRAM_PD                                 0x220000    //0x220000 ~ 0x22ffff
DEFINE_REG_BANK(SRAM_PD, 0x110000);
//#define    TZPC_AID_0                              0x240600    //0x240600 ~ 0x2407ff
DEFINE_REG_BANK(TZPC_AID_0, 0x120300);
//#define    X32_GPU                                 0x5dd200    //0x5dd200 ~ 0x5dd3ff
DEFINE_REG_BANK(X32_GPU, 0x2ee900);

DEFINE_REG_BANK(IOMPU_GLOBAL, 0x1f9000);
DEFINE_REG_BANK(IOMPU_GPU, 0x1fb800);
//#define MFDEC
DEFINE_REG_BANK(MFDEC_BKA412, 0xa41200);
DEFINE_REG_BANK(MFDEC_BKA413, 0xa41300);
DEFINE_REG_BANK(MFDEC_BKA414, 0xa41400);
DEFINE_REG_BANK(MFDEC_BKA415, 0xa41500);
DEFINE_REG_BANK(MFDEC_BKA432, 0xa43200);
DEFINE_REG_BANK(MFDEC_BKA433, 0xa43300);

DEFINE_REG_BANK(GPU_MPU_BYPASS, 0x2ee100);
DEFINE_REG_BANK(CPU_MPU_BYPASS, 0x200600);
//#define    X32_SMI_CTRL                            0x33e000    //0x33e000 ~ 0x33e1ff
DEFINE_REG_BANK(X32_SMI_CTRL, 0x19f000);
DEFINE_REG_BANK(PM_POR, 0x10000);
DEFINE_REG_BANK(TEST_CTRL, 0x101100);

DEFINE_REG_BANK(CKGEN1029, 0x102900);
DEFINE_REG_BANK(CKGEN1035, 0x103500);
DEFINE_REG_BANK(CKGEN1036, 0x103600);
DEFINE_REG_BANK(CKGEN1037, 0x103700);
DEFINE_REG_BANK(CKGEN103A, 0x103A00);
DEFINE_REG_BANK(CKGEN103C, 0x103C00);
DEFINE_REG_BANK(CKGENA040, 0xA04000);


//clk_fnclk
//TOP_CKGEN
DEFINE_REG(CKGEN1035, ckg_g_xc_fn, 0x34, 0, 0);
DEFINE_REG(CKGEN1037, gate_xc_fn, 0x21, 0, 0);
DEFINE_REG(CKGEN1035, ckg_s_xc_fn, 0x34, 2, 3);
//SCFE_CKGEN
DEFINE_REG(CKGENA040, ckg_g_xc_fn_scip, 0x12, 8, 8);
DEFINE_REG(CKGENA040, sw_en_xc_fn2scip, 0x50, 10, 10);
//clk_gpu_mfdec
//TOP_CKGEN
DEFINE_REG(CKGEN1029, ckg_g_disp_mfdec, 0x1A, 0, 0);
DEFINE_REG(CKGEN1029, ckg_g_disp_mfdec_gpu, 0x1A, 12, 12);

//SCFE_CKGEN
DEFINE_REG(CKGENA040, ckg_g_xc_gpu_mfdec_scip, 0x17, 0, 0);
//SCFE_CKGEN
DEFINE_REG(CKGENA040, sw_en_xc_gpu_mfdec2scip, 0x50, 9, 9);

DEFINE_REG(CKGEN103A, sw_en_disp_mfdec2gpu_par_gp, 0x59, 0, 0);

DEFINE_REG(MFDEC_BKA432, gpu_plane_disable, 0x0, 1, 1);
DEFINE_REG(MFDEC_BKA432, gpu_protect_mode, 0x0, 2, 3);
DEFINE_REG(MFDEC_BKA432, gpu_force_8b, 0x0, 14, 14);
DEFINE_REG(MFDEC_BKA432, gpu_idle_cmd, 0xe, 3, 3);

DEFINE_REG(MFDEC_BKA432, gpu_y_base_low,     0x1, 0, 15);
DEFINE_REG(MFDEC_BKA432, gpu_y_base_high,     0x2, 0, 12);
DEFINE_REG(MFDEC_BKA432, gpu_c_base_low,     0x3, 0, 15);
DEFINE_REG(MFDEC_BKA432, gpu_c_base_high,     0x4, 0, 12);
DEFINE_REG(MFDEC_BKA432, gpu_bitlen_base_low,     0x5, 0, 15);
DEFINE_REG(MFDEC_BKA432, gpu_bitlen_base_high,     0x6, 0, 12);
DEFINE_REG(MFDEC_BKA432, gpu_pitch_base,     0x7, 0, 12);
DEFINE_REG(MFDEC_BKA432, gpu_format,        0x8, 0, 11);
DEFINE_REG(MFDEC_BKA432, gpu_cache_clr_trig,        0x9, 0, 0);
DEFINE_REG(MFDEC_BKA432, gpu_en,        0xd, 0, 15);
DEFINE_REG(MFDEC_BKA432, gpu_vsd_bypass,        0xd, 15, 15);

DEFINE_REG(MFDEC_BKA433, cfg_buf_qd,        0x1e, 0, 13);

DEFINE_REG(MFDEC_BKA412, smi_lb_share_mode,        0x1, 0, 1);
DEFINE_REG(MFDEC_BKA413, b2r_stream_on_check_1_8_9,        0x1, 8,9);
DEFINE_REG(MFDEC_BKA414, b2r_stream_on_check_3_0_0,        0x3, 0,0);


// MPU bypass table
DEFINE_REG(GPU_MPU_BYPASS, gpu_table0,       0x0, 0, 15);
DEFINE_REG(CPU_MPU_BYPASS, cpu_table0,       0x0, 0, 15);

//define MIU
//ToDo: Check the following list
DEFINE_REG_BANK(MIU,       0x1ac200);
DEFINE_DW_REG(MIU, out_of_area_start,           0x6, 0, 15);
DEFINE_DW_REG(MIU, out_of_area_start_20_16,     0x6, 16, 22);
DEFINE_DW_REG(MIU, out_of_area_end,             0x7, 0, 15);
DEFINE_DW_REG(MIU, out_of_area_end_20_16,       0x7, 16, 22);

//#define    EMI
#if defined(CONFIG_MALI_DEBUG) && defined(MTK_DTV_ZEBU)
DEFINE_REG_BANK(EMI, 0x1a0000);
#endif

DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll, 0x0, 0, 0);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div1, 0x0, 4, 4);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div2, 0x0, 8, 8);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div3, 0x0, 12, 12);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div5, 0x1, 0, 0);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_postdiv, 0x1, 4, 4);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div30, 0x1, 8, 8);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_vco_div3, 0x2, 0, 0);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_occ_div128, 0x2, 4, 4);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_xtal, 0x2, 8, 8);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_test, 0x2, 12, 12);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_prdt, 0x3, 0, 0);
DEFINE_REG(GPUBRDGPLL, en_gpubrdgpll_rst, 0x3, 4, 4);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_input_div, 0x4, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_cp_sw, 0x5, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_ictrl, 0x5, 8, 10);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_output_div_first, 0x6, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_output_div, 0x6, 8, 10);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_loopdiv_first, 0x7, 0, 1);
DEFINE_REG(GPUBRDGPLL, gc_gpubrdgpll_loopdiv_second, 0x8, 0, 7);
DEFINE_REG(GPUBRDGPLL, ro_gpubrdgpll_lock, 0xA, 0, 0);
DEFINE_REG(GPUBRDGPLL, test_gpubrdgpll, 0xE, 0, 15);
DEFINE_REG(GPUBRDGPLL, gpubrdgpll_dummy_0, 0xF, 0, 15);
DEFINE_REG(GPUBRDGPLL, gpubrdgpll_dummy_1, 0x10, 0, 15);
DEFINE_REG(GPUBRDGPLL, pd_gpubrdgpll_clk_div1_dig, 0x11, 0, 0);

DEFINE_REG(SRAM_PD,       glb_sram_pd_reg_gpu_die,           0x110, 0,  0);
DEFINE_REG(SRAM_PD,       glb_sram_pd_reg_shader_core0,      0x111, 0,  0);
DEFINE_REG(SRAM_PD,       glb_sram_pd_reg_shader_core1,      0x112, 0,  0);

DEFINE_REG(X32_GPU,   riu_apb_en,                        0x66,  0,  0);
DEFINE_REG(X32_GPU,   miu0_start,                        0x50,  0,  15);
DEFINE_REG(X32_GPU,   miu0_end,                          0x51,  0,  15);
DEFINE_REG(TZPC_AID_0,    tzpc_gpu_aid,                      0x30,  8, 15);
DEFINE_REG(TZPC_AID_0,    tzpc_page_table_walk_aid,          0x31,  0,  7);
DEFINE_REG(TZPC_AID_0,    tzpc_gpu_protected_aid,            0x31,  8,  15);

DEFINE_REG(X32_GPU,       mfdec_rreq_rd_len,                 0x41,  0,  2);
DEFINE_REG(X32_GPU,       soft_reset,                        0x00,  0,  0);
DEFINE_REG(X32_GPU,       riu_legacy_en,                     0x7f,  0,  0);
DEFINE_REG(X32_GPU,   riu_legacy_die_en,                 0x7f,  1,  1);

DEFINE_REG(CKGEN00, ckg_i_gpu_gpu_par_gp, 0x32, 1, 1);
DEFINE_REG(CKGEN00, flow_ctrl_rate_gpu_par_gp, 0x33, 0, 4);
DEFINE_REG(CKGEN00, ckg_g_xtal_12m_gpu_par_gp, 0x9E, 10, 10);
DEFINE_REG(CKGEN00, ckg_i_xtal_12m_gpu_par_gp, 0x9E, 11, 11);
DEFINE_REG(CKGEN00, ckg_g_xtal_24m_gpu_par_gp, 0xA0, 10, 10);
DEFINE_REG(CKGEN00, ckg_i_xtal_24m_gpu_par_gp, 0xA0, 11, 11);

DEFINE_REG(CKGEN00, ckg_g_disp_mfdec_gpu_par_gp, 0x49A, 8, 8);
DEFINE_REG(CKGEN00, ckg_i_disp_mfdec_gpu_par_gp, 0x49A, 9, 9);
DEFINE_REG(CKGEN00, ckg_s_disp_mfdec_gpu_par_gp, 0x49A, 10, 11);
DEFINE_REG(CKGEN00, ckg_g_bist_gpu_par_gp, 0x4D6, 8, 8);
DEFINE_REG(CKGEN00, ckg_i_bist_gpu_par_gp, 0x4D6, 9, 9);
DEFINE_REG(CKGEN00, ckg_s_bist_gpu_par_gp, 0x4D6, 10, 12);
DEFINE_REG(CKGEN00, sw_en_gpu2gpu_par_gp, 0x511, 0, 0);
DEFINE_REG(CKGEN00, sw_en_gpu_dfs2gpu_par_gp, 0x511, 1, 1);
DEFINE_REG(CKGEN00, sw_en_xtal_12m2met, 0x513, 0, 0);
DEFINE_REG(CKGEN00, sw_en_xtal_24m2syscount, 0x514, 1, 1);
DEFINE_REG(CKGEN00, flow_ctrl_rate_gpu_par_gp_sld, 0x33, 0, 0);


DEFINE_REG(CKGEN01, ckg_g_mcu_nonpm_gpu_par_gp, 0x414, 14, 14);
DEFINE_REG(CKGEN01, ckg_i_mcu_nonpm_gpu_par_gp, 0x414, 15, 15);
DEFINE_REG(CKGEN01, sw_en_disp_mfdec2gpu_par_gp, 0x559, 0, 0);
DEFINE_REG(CKGEN01, sw_en_mcu_nonpm2gpu_par_gp, 0x6DD, 12, 12);
DEFINE_REG(CKGEN01, sw_en_xtal_24m2gpu_par_gp_mbist, 0x760, 13, 13);
DEFINE_REG(CKGEN01, gpu_par_gp_test_enable, 0x77E, 0, 0);
DEFINE_REG(CKGEN01, gpu_par_gp_test_div_sel, 0x77E, 4, 6);
DEFINE_REG(CKGEN01, gpu_par_gp_test_src_sel, 0x77E, 8, 15);
DEFINE_REG(CKGEN01, gate_inv_wlock_passwd, 0x7CE, 0, 15);
DEFINE_REG(CKGEN01, all_sw_en_passwd, 0x7CF, 0, 15);
DEFINE_REG(CKGEN01, gpu_par_gp_all_sw_en_overwrite, 0x7D3, 10, 10);
DEFINE_REG(CKGEN01, gpu_par_gp_all_sw_en_value, 0x7DB, 10, 10);

DEFINE_REG(TEST_CTRL, clk_calc_src_sel, 0x30, 0, 6);
DEFINE_REG(TEST_CTRL, clk_calc_en, 0x31, 0, 0);
DEFINE_REG(TEST_CTRL, calc_cnt_report, 0x32, 0, 15);

DEFINE_REG(X32_GPU, gpu_protect_mode, 0x5b, 0, 0);

DEFINE_REG(X32_GPU,   mfdec_off,                         0x66,  1,  1);
DEFINE_REG(X32_GPU,   mfdec_valid,                       0x52, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_divider_en,                  0x42, 14, 14);
DEFINE_REG(X32_GPU,   mfdec_linear_mode,                 0x43,  0,  0);

DEFINE_REG(X32_GPU,   mfdec_adr_idx,                     0x3a,  0,  3);
DEFINE_REG(X32_GPU,   video_pitch,                       0x53, 0,  14);
DEFINE_REG(X32_GPU,   mfdec_y_start_15_00,               0x18, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_y_start_21_16,               0x19,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_y_end_15_00,                 0x1a, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_y_end_21_16,                 0x1b,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_uv_start_15_00,              0x1c, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_uv_start_21_16,              0x1d,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_uv_end_15_00,                0x1e, 0,  15);
DEFINE_REG(X32_GPU,   mfdec_uv_end_21_16,                0x1f,  0,  5);
DEFINE_REG(X32_GPU,   mfdec_adr_update,                  0x3a,  4,  4);

DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_mst_slpprot_en,    0xe,  9,  9);
DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_slv_slpprot_en,    0xe,  10,  10);
DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_mst_slpprot_rdy,   0x14, 11,  11);
DEFINE_REG(X32_SMI_CTRL,   reg_gpu02ip_wrap_gals_slv_slpprot_rdy,   0x14, 12,  12);

// gpu bridge debug register
DEFINE_REG(X32_GPU, mfdec_bri_status_sel_0, 0x40, 1, 3);
DEFINE_REG(X32_GPU, mfdec_bri_status_sel_1, 0x40, 4, 6);
DEFINE_REG(X32_GPU, bridge_idle, 0x5e, 0, 15);
DEFINE_REG(X32_GPU, gpu_bridge_idle, 0x5E, 1, 1);
DEFINE_REG(X32_GPU, mfdec_status_0, 0x67, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_0_31_16, 0x68, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_1, 0x69, 0, 15);
DEFINE_REG(X32_GPU, mfdec_status_1_31_16, 0x6A, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_0, 0x6B, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_0_31_16, 0x6C, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_1, 0x6D, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_1_31_16, 0x6E, 0, 15);
DEFINE_REG(X32_GPU, g3d_bri_status_sel, 0x6F, 0, 2);

// MPU
DEFINE_DW_REG(IOMPU_GPU, mpu_table_base_addr, 0x0, 0, 26);
DEFINE_DW_REG(IOMPU_GPU, mpu_area_0_start, 0x2, 0, 20);
DEFINE_DW_REG(IOMPU_GPU, mpu_area_0_end, 0x3, 0, 20);
DEFINE_DW_REG(IOMPU_GPU, mpu_area_1_start, 0x4, 0, 20);
DEFINE_DW_REG(IOMPU_GPU, mpu_area_1_end, 0x5, 0, 20);
DEFINE_DW_REG(IOMPU_GPU, mpu_table_base_area_update, 0xa, 4, 4);
DEFINE_DW_REG(IOMPU_GPU, mpu_enable, 0xa, 0, 0);

DEFINE_DW_REG(IOMPU_GPU, srinfo_mode, 0x13, 0, 0);
DEFINE_DW_REG(IOMPU_GPU, mpu_bypass_sel, 0x13, 4, 4);

DEFINE_DW_REG(IOMPU_GPU, detect_AID_value, 0x78, 0, 7);
DEFINE_DW_REG(IOMPU_GPU, detect_AID_enable, 0x76, 1, 1);
DEFINE_DW_REG(IOMPU_GPU, fault_latch_enable, 0x75, 0, 0);
DEFINE_DW_REG(IOMPU_GPU, detected_AID_reset, 0x75, 1, 1);
DEFINE_DW_REG(IOMPU_GPU, read_detected_AID, 0x74, 16, 23);


DEFINE_DW_REG(IOMPU_GLOBAL, mpu_invalide_start_addr, 0x6, 0, 21);
DEFINE_DW_REG(IOMPU_GLOBAL, mpu_invalide_end_addr, 0x7, 0, 21);
DEFINE_DW_REG(IOMPU_GLOBAL, mpu_trigger_invalidate, 0xa, 8, 8);
DEFINE_DW_REG(IOMPU_GLOBAL, mpu_cache_invalidate_idle_mode, 0xa, 12, 12);
DEFINE_DW_REG(IOMPU_GLOBAL, mpu_invalide_mode, 0xa, 20, 20);
DEFINE_DW_REG(IOMPU_GLOBAL, mpu_invalide_status, 0x25, 0, 0);

DEFINE_DW_REG(IOMPU_GPU, mpu_invalide_start_addr, 0x6, 0, 21);
DEFINE_DW_REG(IOMPU_GPU, mpu_invalide_end_addr, 0x7, 0, 21);
DEFINE_DW_REG(IOMPU_GPU, mpu_trigger_invalidate, 0xa, 8, 8);
DEFINE_DW_REG(IOMPU_GPU, mpu_cache_invalidate_idle_mode, 0xa, 12, 12);
DEFINE_DW_REG(IOMPU_GPU, mpu_invalide_mode, 0xa, 20, 20);
DEFINE_DW_REG(IOMPU_GPU, mpu_invalide_status, 0x35, 0, 0);

DEFINE_DW_REG(IOMPU_GPU, mpu_pmu_debug_client_sel, 0x34, 20, 23);
DEFINE_DW_REG(IOMPU_GPU, mpu_fault_info_valid, 0x3f, 0, 15);
DEFINE_DW_REG(IOMPU_GPU, mpu_fault_physical_address, 0x40, 0, 24);
DEFINE_DW_REG(IOMPU_GPU, mpu_fault_sr_info, 0x43, 0, 31);
DEFINE_DW_REG(IOMPU_GPU, mpu_state, 0x40, 27, 28);
DEFINE_DW_REG(IOMPU_GPU, mpu_clean_fault_information, 0x40, 26, 26);


DEFINE_DW_REG(IOMPU_GPU, mpu_log_sel, 0x1b, 24, 27);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_pa_60000000, 0x160, 0, 31);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_entry_size, 0x1b, 12, 14);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_gpu_table_enable, 0x1b, 8, 8);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_gpu_table_debug_enable, 0x1b, 10, 10);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_log_pa_0_31, 0x1c, 0, 31);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_log_pa_32_33, 0x1d, 0, 1);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_log_byp_value, 0x1d, 2, 2);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_log_valid_flag, 0x1d, 6, 6);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_log_sr_info, 0x1c, 0, 7);
DEFINE_DW_REG(IOMPU_GPU, mpu_byp_clean_fault_info, 0x1b, 28, 28);

DEFINE_DW_REG(IOMPU_GPU, mpu_byp_client_status_sel, 0x14, 12, 13);


#if MTK_DTV_GPU_MFDEC
//DEFINE_REG(CKGEN00, ckg_g_disp_mfdec, 0x49a, 0, 0);
DEFINE_REG(CKGEN00, sw_en_smi2scip, 0x53B, 0, 0); //Shared by B2R/B2R lite1/B2R lite2/GPU
DEFINE_REG(CKGEN01, sw_en_xc_disp_mfdec2scip, 0x661, 0, 0);
DEFINE_REG(CKGEN01, ckg_xc_disp_mfdec_scip, 0x330, 0, 0);

DEFINE_REG(CKGEN01, sw_en_xc_dc02scip, 0x65f, 0, 0);
DEFINE_REG(CKGEN01, ckg_xc_dc0_scip, 0x2c4, 0, 0);

//GPU IRQ debug
DEFINE_REG(X32_GPU, reg_0050_x32_gpu,               0x50, 0, 15);
DEFINE_REG(X32_GPU, reg_0054_x32_gpu,               0x54, 0, 7);
DEFINE_REG(X32_GPU, reg_0058_x32_gpu,               0x58, 0, 15);
DEFINE_REG(X32_GPU, reg_005C_x32_gpu,               0x5C, 0, 7);

//GPU WDT TEST
//WDT trigger_event
DEFINE_REG(X32_GPU, reg_007A_x32_gpu,               0x7A, 0, 15);

DEFINE_REG(PM_POR, reg_000D_pm_por,               0xd, 0, 15);
DEFINE_REG(PM_POR, reg_0022_pm_por,               0x22, 0, 15);
DEFINE_REG(PM_POR, reg_0023_pm_por,               0x23, 0, 15);

#endif
