/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define MODA1_V007 0x484600

//Page MODA1_V007
#define REG_0004_MODA1_V007 (MODA1_V007 + 0x004)
	#define REG_0004_MODA1_V007_REG_PD_MOD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0004_MODA1_V007_REG_EN_FULLRATE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0004_MODA1_V007_REG_EN_HSW_IB Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0004_MODA1_V007_REG_EN_CLK_BANK Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0008_MODA1_V007 (MODA1_V007 + 0x008)
	#define REG_0008_MODA1_V007_REG_BANK_CLK_SRC_SEL Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_000C_MODA1_V007 (MODA1_V007 + 0x00C)
	#define REG_000C_MODA1_V007_REG_REG_LEVEL Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_000C_MODA1_V007_REG_IMODE_SPEED_SEL Fld(2, 4, AC_MSKB0)//[5:4]
#define REG_0010_MODA1_V007 (MODA1_V007 + 0x010)
	#define REG_0010_MODA1_V007_REG_GCR_BIAS_CON Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_0014_MODA1_V007 (MODA1_V007 + 0x014)
	#define REG_0014_MODA1_V007_REG_REG_CTRL_CAS_LSH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0014_MODA1_V007_REG_REG_CTRL_REF Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0014_MODA1_V007_REG_REG_CTRL_REF_PAD Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0014_MODA1_V007_REG_SEL_SYNC_DIV Fld(3, 8, AC_MSKB1)//[10:8]
#define REG_0024_MODA1_V007 (MODA1_V007 + 0x024)
	#define REG_0024_MODA1_V007_REG_GCR_REG_LEVEL_GP1 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0024_MODA1_V007_REG_GCR_REG_LEVEL_GP2 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0024_MODA1_V007_REG_GCR_REG_LEVEL_GP3 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0024_MODA1_V007_REG_GCR_REG_LEVEL_GP4 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0028_MODA1_V007 (MODA1_V007 + 0x028)
	#define REG_0028_MODA1_V007_REG_GCR_REG_LEVEL_GP5 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0028_MODA1_V007_REG_GCR_REG_LEVEL_GP6 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0028_MODA1_V007_REG_GCR_REG_LEVEL_GP7 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0028_MODA1_V007_REG_GCR_REG_LEVEL_GP8 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_002C_MODA1_V007 (MODA1_V007 + 0x02C)
	#define REG_002C_MODA1_V007_REG_CK1X_DIG_PHSEL Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_002C_MODA1_V007_REG_CK1X_ANA_PHSEL Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_002C_MODA1_V007_REG_CK1X_DIG_PHSEL_PATH2 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_002C_MODA1_V007_REG_CK1X_ANA_PHSEL_PATH2 Fld(2, 6, AC_MSKB0)//[7:6]
#define REG_0030_MODA1_V007 (MODA1_V007 + 0x030)
	#define REG_0030_MODA1_V007_REG_GCR_EN_REG Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0030_MODA1_V007_REG_GCR_CKEN_PATH2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0030_MODA1_V007_REG_GCR_CKEN Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0030_MODA1_V007_REG_GCR_EN_PULL_L Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0030_MODA1_V007_REG_GCR_EN_VBY1_DIFF Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0030_MODA1_V007_REG_GCR_SEL_REF18 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_0034_MODA1_V007 (MODA1_V007 + 0x034)
	#define REG_0034_MODA1_V007_REG_PD_XTALRX Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0034_MODA1_V007_REG_EN_REG Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0034_MODA1_V007_REG_PD_IB Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0034_MODA1_V007_REG_TST_XTALRX_LV Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0034_MODA1_V007_REG_XTALRX_RTERM_LV Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0034_MODA1_V007_REG_GCR_VCM_SEL Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0038_MODA1_V007 (MODA1_V007 + 0x038)
	#define REG_0038_MODA1_V007_REG_GCR_EN_SKEW Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0038_MODA1_V007_REG_EN_MINI_SKEW Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0038_MODA1_V007_REG_GCR_EN_CML Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_003C_MODA1_V007 (MODA1_V007 + 0x03C)
	#define REG_003C_MODA1_V007_REG_SKEWCLK_SRC_SEL Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0058_MODA1_V007 (MODA1_V007 + 0x058)
	#define REG_0058_MODA1_V007_REG_TCON_PIN_MUX_SET Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0058_MODA1_V007_REG_TCON_PIN_ENABLE_SET Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0058_MODA1_V007_REG_TCON_PIN_MUX_SET_EXT Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0058_MODA1_V007_REG_TCON_PIN_SEL Fld(6, 8, AC_MSKB1)//[13:8]
	#define REG_0058_MODA1_V007_REG_TCON_PIN_WR Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_005C_MODA1_V007 (MODA1_V007 + 0x05C)
	#define REG_005C_MODA1_V007_REG_TCON_PIN_MUX_STATUS Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_005C_MODA1_V007_REG_TCON_PIN_ENABLE_STATUS Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_005C_MODA1_V007_REG_TCON_SFC_CNC_PATH Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0080_MODA1_V007 (MODA1_V007 + 0x080)
	#define REG_0080_MODA1_V007_REG_GCR_CAL_LEVEL Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0080_MODA1_V007_REG_KEEP_BIAS_CON_CAL_VALUE Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0080_MODA1_V007_REG_BIAS_CON_HW_CAL_ON Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0080_MODA1_V007_REG_C_CAL_OUT Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0080_MODA1_V007_REG_GCR_CAL_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0084_MODA1_V007 (MODA1_V007 + 0x084)
	#define REG_0084_MODA1_V007_REG_TOTAL_CAL_PAIR Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0084_MODA1_V007_REG_GCR_CAL_SRC Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0088_MODA1_V007 (MODA1_V007 + 0x088)
	#define REG_0088_MODA1_V007_REG_ICON_RESULT Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0088_MODA1_V007_REG_CAL_FAIL Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0088_MODA1_V007_REG_CAL_FINISH Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0088_MODA1_V007_REG_HW_CAL_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_008C_MODA1_V007 (MODA1_V007 + 0x08C)
	#define REG_008C_MODA1_V007_REG_CAL_TOG_TIME Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_008C_MODA1_V007_REG_HW_CAL_WAIT Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0090_MODA1_V007 (MODA1_V007 + 0x090)
	#define REG_0090_MODA1_V007_REG_1MS_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A8_MODA1_V007 (MODA1_V007 + 0x0A8)
	#define REG_00A8_MODA1_V007_REG_SKEW_CH_STATUS Fld(6, 0, AC_MSKB0)//[5:0]
#define REG_00AC_MODA1_V007 (MODA1_V007 + 0x0AC)
	#define REG_00AC_MODA1_V007_REG_SKEW_WR_VALUE Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00AC_MODA1_V007_REG_SKEW_CH_SEL Fld(6, 8, AC_MSKB1)//[13:8]
	#define REG_00AC_MODA1_V007_REG_SKEW_WR Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_00AC_MODA1_V007_REG_SKEW_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00CC_MODA1_V007 (MODA1_V007 + 0x0CC)
	#define REG_00CC_MODA1_V007_REG_SW_RSTZ Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00CC_MODA1_V007_REG_VBY1_LOCKN_HTPDN_SWAP_V1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00CC_MODA1_V007_REG_VBY1_LOCKN_HTPDN_SWAP_V2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00CC_MODA1_V007_REG_VBY1_LOCKN_HTPDN_SWAP_OSD Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_00CC_MODA1_V007_REG_VBY1_LOCKN_HTPDN_SEL_V1 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00CC_MODA1_V007_REG_VBY1_PAD_SEL_V1 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_00CC_MODA1_V007_REG_VBY1_LOCKN_HTPDN_SEL_V2 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_00CC_MODA1_V007_REG_VBY1_LOCKN_HTPDN_SEL_OSD Fld(3, 12, AC_MSKB1)//[14:12]
	#define REG_00CC_MODA1_V007_REG_VBY1_PAD_SEL_OSD Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00E8_MODA1_V007 (MODA1_V007 + 0x0E8)
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH00 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH01 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH02 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH03 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH04 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH05 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH06 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_00E8_MODA1_V007_REG_OUTCONF_CH07 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00EC_MODA1_V007 (MODA1_V007 + 0x0EC)
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH08 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH09 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH10 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH11 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH12 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH13 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH14 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_00EC_MODA1_V007_REG_OUTCONF_CH15 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00F0_MODA1_V007 (MODA1_V007 + 0x0F0)
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH16 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH17 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH18 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH19 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH20 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH21 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH22 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_00F0_MODA1_V007_REG_OUTCONF_CH23 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00F4_MODA1_V007 (MODA1_V007 + 0x0F4)
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH24 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH25 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH26 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH27 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH28 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH29 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH30 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_00F4_MODA1_V007_REG_OUTCONF_CH31 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00F8_MODA1_V007 (MODA1_V007 + 0x0F8)
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH32 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH33 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH34 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH35 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH36 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH37 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH38 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_00F8_MODA1_V007_REG_OUTCONF_CH39 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00FC_MODA1_V007 (MODA1_V007 + 0x0FC)
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH40 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH41 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH42 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH43 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH44 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH45 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH46 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_00FC_MODA1_V007_REG_OUTCONF_CH47 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0100_MODA1_V007 (MODA1_V007 + 0x100)
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH48 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH49 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH50 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH51 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH52 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH53 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH54 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0100_MODA1_V007_REG_OUTCONF_CH55 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0104_MODA1_V007 (MODA1_V007 + 0x104)
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH56 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH57 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH58 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH59 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH60 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH61 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH62 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0104_MODA1_V007_REG_OUTCONF_CH63 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0120_MODA1_V007 (MODA1_V007 + 0x120)
	#define REG_0120_MODA1_V007_REG_HW_RINT_TH Fld(15, 0, AC_MSKW10)//[14:0]
	#define REG_0120_MODA1_V007_REG_HW_RINT_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0124_MODA1_V007 (MODA1_V007 + 0x124)
	#define REG_0124_MODA1_V007_REG_HW_RINT_CNT_VALUE Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0128_MODA1_V007 (MODA1_V007 + 0x128)
	#define REG_0128_MODA1_V007_REG_GCR_EN_RINT_RD Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0180_MODA1_V007 (MODA1_V007 + 0x180)
	#define REG_0180_MODA1_V007_REG_V1_PRBS_DET_CH_SEL Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0180_MODA1_V007_REG_V2_PRBS_DET_CH_SEL Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0180_MODA1_V007_REG_OSD_PRBS_DET_CH_SEL Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_0184_MODA1_V007 (MODA1_V007 + 0x184)
	#define REG_0184_MODA1_V007_REG_V1_2_PRBS_DET_CH_SEL Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0184_MODA1_V007_REG_V1_TEST_PRBS_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0184_MODA1_V007_REG_V2_TEST_PRBS_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0184_MODA1_V007_REG_OSD_TEST_PRBS_EN Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0184_MODA1_V007_REG_V1_2_TEST_PRBS_EN Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_0188_MODA1_V007 (MODA1_V007 + 0x188)
	#define REG_0188_MODA1_V007_REG_V1_PRBS_BIT_ERROR_CNT Fld(14, 0, AC_MSKW10)//[13:0]
	#define REG_0188_MODA1_V007_REG_V1_PRBS_BIT_ERROR_CNT_CLR Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0188_MODA1_V007_REG_V1_PRBS_COMPARE_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_018C_MODA1_V007 (MODA1_V007 + 0x18C)
	#define REG_018C_MODA1_V007_REG_V2_PRBS_BIT_ERROR_CNT Fld(14, 0, AC_MSKW10)//[13:0]
	#define REG_018C_MODA1_V007_REG_V2_PRBS_BIT_ERROR_CNT_CLR Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_018C_MODA1_V007_REG_V2_PRBS_COMPARE_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0190_MODA1_V007 (MODA1_V007 + 0x190)
	#define REG_0190_MODA1_V007_REG_OSD_PRBS_BIT_ERROR_CNT Fld(14, 0, AC_MSKW10)//[13:0]
	#define REG_0190_MODA1_V007_REG_OSD_PRBS_BIT_ERROR_CNT_CLR Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0190_MODA1_V007_REG_OSD_PRBS_COMPARE_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0194_MODA1_V007 (MODA1_V007 + 0x194)
	#define REG_0194_MODA1_V007_REG_V1_2_PRBS_BIT_ERROR_CNT Fld(14, 0, AC_MSKW10)//[13:0]
	#define REG_0194_MODA1_V007_REG_V1_2_PRBS_BIT_ERROR_CNT_CLR Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0194_MODA1_V007_REG_V1_2_PRBS_COMPARE_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0198_MODA1_V007 (MODA1_V007 + 0x198)
	#define REG_0198_MODA1_V007_REG_ECLKDLYSEL Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0198_MODA1_V007_REG_CLKDLYSEL Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_019C_MODA1_V007 (MODA1_V007 + 0x19C)
	#define REG_019C_MODA1_V007_REG_CKG_MOD_SR_RCLK_V1 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_019C_MODA1_V007_REG_CKG_MOD_SR_RCLK_V2 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_019C_MODA1_V007_REG_CKG_MOD_SR_RCLK_OSD Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_01A0_MODA1_V007 (MODA1_V007 + 0x1A0)
	#define REG_01A0_MODA1_V007_REG_DCC_CAL_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01A0_MODA1_V007_REG_SW_FORCE_DCC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01A0_MODA1_V007_REG_DCC_BYPASS Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_01A0_MODA1_V007_REG_DCC_PRE_A Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_01A0_MODA1_V007_REG_DCC_PRE_B Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_01A0_MODA1_V007_REG_DCC_RIUP_INV Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_01A0_MODA1_V007_REG_DCC_RIUN_INV Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_01A0_MODA1_V007_REG_DCC_DBG_MUX Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_01A0_MODA1_V007_REG_DISP_MISC_A_DBG_MUX Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_01A4_MODA1_V007 (MODA1_V007 + 0x1A4)
	#define REG_01A4_MODA1_V007_REG_DCC_INTR_EN Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01A4_MODA1_V007_REG_DCC_DONE_INTR_CLR Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01A8_MODA1_V007 (MODA1_V007 + 0x1A8)
	#define REG_01A8_MODA1_V007_REG_RO_INTR_DCC_CAL_DONE Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01A8_MODA1_V007_REG_RO_DCC_CAL_DONE Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01AC_MODA1_V007 (MODA1_V007 + 0x1AC)
	#define REG_01AC_MODA1_V007_REG_EQ0_INIT_VAL Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_01B0_MODA1_V007 (MODA1_V007 + 0x1B0)
	#define REG_01B0_MODA1_V007_REG_EQ1_INIT_VAL Fld(11, 0, AC_MSKW10)//[10:0]
#define REG_01B4_MODA1_V007 (MODA1_V007 + 0x1B4)
	#define REG_01B4_MODA1_V007_REG_XTAL_1US_THRD Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01B4_MODA1_V007_REG_1US_SETTLE_THRD Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01B8_MODA1_V007 (MODA1_V007 + 0x1B8)
	#define REG_01B8_MODA1_V007_REG_TEST_MOD_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01BC_MODA1_V007 (MODA1_V007 + 0x1BC)
	#define REG_01BC_MODA1_V007_REG_TEST_MOD_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C0_MODA1_V007 (MODA1_V007 + 0x1C0)
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_00 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_01 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_02 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_03 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_04 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_05 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_06 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01C0_MODA1_V007_REG_TEST_DATA_SEL_07 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01C4_MODA1_V007 (MODA1_V007 + 0x1C4)
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_08 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_09 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_10 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_11 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_12 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_13 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_14 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01C4_MODA1_V007_REG_TEST_DATA_SEL_15 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01C8_MODA1_V007 (MODA1_V007 + 0x1C8)
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_16 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_17 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_18 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_19 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_20 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_21 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_22 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01C8_MODA1_V007_REG_TEST_DATA_SEL_23 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01CC_MODA1_V007 (MODA1_V007 + 0x1CC)
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_24 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_25 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_26 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_27 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_28 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_29 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_30 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01CC_MODA1_V007_REG_TEST_DATA_SEL_31 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01D0_MODA1_V007 (MODA1_V007 + 0x1D0)
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_32 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_33 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_34 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_35 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_36 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_37 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_38 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01D0_MODA1_V007_REG_TEST_DATA_SEL_39 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01D4_MODA1_V007 (MODA1_V007 + 0x1D4)
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_40 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_41 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_42 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_43 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_44 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_45 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_46 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01D4_MODA1_V007_REG_TEST_DATA_SEL_47 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01D8_MODA1_V007 (MODA1_V007 + 0x1D8)
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_48 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_49 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_50 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_51 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_52 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_53 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_54 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01D8_MODA1_V007_REG_TEST_DATA_SEL_55 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01DC_MODA1_V007 (MODA1_V007 + 0x1DC)
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_56 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_57 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_58 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_59 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_60 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_61 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_62 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01DC_MODA1_V007_REG_TEST_DATA_SEL_63 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01E4_MODA1_V007 (MODA1_V007 + 0x1E4)
	#define REG_01E4_MODA1_V007_REG_DATA_INV_BY_CLK Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_01E8_MODA1_V007 (MODA1_V007 + 0x1E8)
	#define REG_01E8_MODA1_V007_REG_FORCE_DATA1_15_00_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01EC_MODA1_V007 (MODA1_V007 + 0x1EC)
	#define REG_01EC_MODA1_V007_REG_FORCE_DATA1_15_00_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F0_MODA1_V007 (MODA1_V007 + 0x1F0)
	#define REG_01F0_MODA1_V007_REG_FORCE_DATA2_15_00_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F4_MODA1_V007 (MODA1_V007 + 0x1F4)
	#define REG_01F4_MODA1_V007_REG_FORCE_DATA2_15_00_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F8_MODA1_V007 (MODA1_V007 + 0x1F8)
	#define REG_01F8_MODA1_V007_REG_MODA_DUMMY1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01FC_MODA1_V007 (MODA1_V007 + 0x1FC)
	#define REG_01FC_MODA1_V007_REG_MODA_DUMMY2 Fld(16, 0, AC_FULLW10)//[15:0]
