// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * MediaTek Panel driver
 *
 * Copyright (c) 2020 MediaTek Inc.
 * Author Yu-Jen.Huang <yu-jen.huang@mediatek.com>
 */
//#define DEBUG
#include <common.h>
#include <dm.h>
#include <utility.h>
#include <debug_impl.h>
#include <system_impl.h>
#include <mtk_panel.h>
#include <dts_parser.h>
#include "coda/TGEN_MAIN_BKA3A0.h"
#include "coda/TGEN_FRAMELOCK_BKA3A2.h"
#include "coda/TGEN_VRR_BKA39F.h"
#include "coda/TRIGGER_GEN_BKA3A5.h"
#include "coda/DISP_LB_BKA326.h"
#include "coda/TGEN_REGEN_BKA39C.h"
#include "coda/DELTA_PATH_BKA35B.h"
#include "coda/PATGEN_SCALER_BKA404.h"
#include "coda/PATGEN_SCALER_BKA407.h"
#include "coda/PATGEN_SCALER_BKA409.h"
#include "coda/GOPG_HVSP4_BKA4DA.h"
#include "coda/ckgen00.h"
#include "coda/ckgen01.h"
#include "coda/CKGEN00_V004.h"
#include "coda/CKGEN01_V004.h"
#include "coda/modv11.h"
#include "coda/modv12.h"
#include "coda/modv13.h"
#include "coda/modv21.h"
#include "coda/modv22.h"
#include "coda/modd1.h"
#include "coda/moda1.h"
#include "coda/moda2.h"
#include "coda/moda3.h"
#include "coda/moda4.h"
#include "coda/modosd1.h"
#include "coda/modosd2.h"
#include "coda/lpll.h"
#include "coda/SCAID_BIND_BKA3AE.h"
#include "coda/PATGEN_SCALER_BKA401.h"
#include "coda/TRIGGER_GEN_BKA3A4.h"
#include "coda/GOP0_BKA4DE.h"
#include "coda/GOPG_BKA4D9.h"
#include "coda/IP2_M_BKA330.h"
#include "coda/SCTCON_MISC_BKA3E0.h"
#include "coda/TGEN_OUTPUT_BKA3A3.h"
#include "coda/reg_META_DATA_TRANSFER_BKA35A.h"
#include "coda/PAFRC_BKA324.h"
#include "coda/PAFRC_BKA324_V004.h"
#include "coda/DEMURA_BKA377_V004.h"
#include "coda/LINEOD_BKA3A8_V004.h"
#include "coda/PAT_DET_BKA37F_V004.h"
#include "coda/OD_1ST_BKA336_V004.h"
#include "coda/OD_2ND_BKA337_V004.h"
#include "coda/OD_3RD_BKA338_V004.h"
#include "coda/SCTCON_BKA4F7_V004.h"
#include "mtk_pnl_utility.h"
#include "mtk_tv_pnl.h"
#include "mtk_pnl_out_if_v007.h"
#include "coda/MODV11_V004.h"
#include "coda/MODV12_V004.h"
#include "coda/MODV13_V004.h"
#include "coda/MODD1_V004.h"
#include "coda/MODA1_V004.h"
#include "coda/MODA2_V004.h"
#include "coda/MODA3_V004.h"
#include "coda/MODA4_V004.h"
#include "coda/MODOSD1_V004.h"
#include "coda/MODOSD2_V004.h"
#include "coda/LPLL_V004.h"
#include "coda/DISP_MISC_V004.h"
#include "coda/DET_V004.h"
#include "coda/SCDISP_BKA4FA.h"
#include "mtk_pnl_autodownload.h"
#include "coda/CKGEN00_V005.h"
#include "coda/CKGEN01_V005.h"
#include "coda/MODV11_V005.h"
#include "coda/MODV12_V005.h"
#include "coda/MODD1_V005.h"
#include "coda/MODOSD1_V005.h"
#include "coda/MODOSD2_V005.h"
#include "coda/MODA1_V005.h"
#include "coda/MODA4_V005.h"
#include "coda/LPLL_V005.h"
#include "coda/disp_misc.h"
#include "mtk_tcon_common.h"
#include "mtk_pnl_out_if.h"
#include "mtk_tcon_out_if.h"
//#include "mtk_pnl_clk_ctrl.h"
#include "coda/FRCPLL.h"
#include "coda/SCTCON_MISC_BKA3E0_V005.h"
//#include "coda/XCPLL_REG_V005.h"
#include "coda/CKGEN00_V006.h"
#include "coda/CKGEN01_V006.h"
#include "coda/XCPLL_V006.h"
#include "coda/BLEND_TOP_BKA36B.h"
#include "coda/TCON_VCOM_PAT_V005.h"
#include "coda/OSDB_COLOV_BKA3ED.h"
#include "coda/TOP_CKGEN01_V007.h"
#include "coda/TOP_CKGEN00_V007.h"
#include "coda/META_DATA_TRANSFER_BKA35A_V007.h"
#include "coda/CLKGEN_FRC00.h"
#include "coda/CLKGEN_SC00.h"
#include "coda/CLKGEN_SC01.h"
#include "coda/CLKGEN_SC02.h"
#include "coda/TOP_XCPLL_V007.h"
#include "coda/TOP_XCBPLL.h"
#include "coda/MODA1_V007.h"
#include "coda/MODA2_V007.h"
#include "coda/LPLLA.h"
#include "coda/LPLLA_V007.h"
#include "coda/MODV11_V007.h"
#include "coda/MODV12_V007.h"
#include "coda/MODD1_V007.h"
#include "coda/SCDISP_BKA4FA_V007.h"
#include "coda/MODOSD2_V007.h"
#include "mtk_tv_edp.h"

//Only for HAPS
#define REG_HFRC_HAPS_BASE	(0x147F400)
#define REG_HFRC_HVSP_IP_BASE	(0x147F600)
#define REG_HFRC_HVSP_OP_BASE	(0x147E800)

#define TGEN_2P (2)
#define TGEN_4P (4)

#define MFT_P (8)

#define MOD_VER2 (2)
#define MOD_VER3 (3)
#define REG_ALL (0xFFFF)

#define FULL_BIT (16)
#define VBO_USE_LANE_NUM_64 64
#define VBO_USE_LANE_NUM_40 40
#define VBO_USE_LANE_NUM_32 32
#define VBO_USE_LANE_NUM_16 16
#define VBO_USE_LANE_NUM_8 8
#define VBO_USE_LANE_NUM_4 4

#define OUT_CONFIG_OFF (0x0000)
#define OUT_CONFIG_4K60_1_VER1 (0x5545)
#define OUT_CONFIG_4K60_2_VER1 (0x0010)
#define OUT_CONFIG_4K60_1_VER2 (0x5555)
#define OUT_CONFIG_4K60_2_VER2 (0x0000)

#define FRCPLL_CONFIG_SET_0_0014 (0xe6cc)
#define FRCPLL_CONFIG_SET_1_0018 (0x1f)
#define FRCPLL_CONFIG_STEP_0_001C (0x001e)
#define FRCPLL_CONFIG_SPAN_0_0024 (0x02a6)
#define FRCPLL_CONFIG_TEST_0000 (0x0012)
#define FRCPLL_CONFIG_LOOP_DIV_SECOND_000C (0x03)
#define FRCPLL_CONFIG_ICP_ICTRL_0010 (0x02)
#define FRCPLL_CONFIG_OUTPUT_DIV_000C (0x04)

#define FRCPLL_CONFIG_UDELAY (500)

#define VBY1_LOCK_PROTECT_EN true

//efuse for mod
#define EFUSE_BANK (0x252A0)	//bank 0x129_50(8bit) to switch sub-bank.
#define MOD_ATOP_SUBBANK (0x12)	// MOD_ATOP subbank is 0x12, addr[8:2]
#define MOD_ATOP_SUBBANK_VER004 (0x15)	// MOD_ATOP subbank is 0x12, addr[8:2]
#define MOD_ATOP_SUBBANK_VER005 (0x12)	// MOD_ATOP subbank is 0x12, addr[8:2]
#define MOD_ATOP_SUBBANK_0C (0x0C)
#define MOD_ATOP_SUBBANK_0D (0x0D)
#define MOD_ATOP_SUBBANK_13_VER005 (0x13)
#define MOD_ATOP_SUBBANK_14_VER005 (0x14)
#define EFUSE_PPM_REG_TABLE_1 (0x2E)	//bank 0x129_A0 (8bit)
#define EFUSE_PPM_REG_TABLE_1_TCON_DISABLE_BIT (1<<25)	//Bit25
#define MOD_ATOP_SUBBANK_64 (0x64)
#define MOD_ATOP_SUBBANK_65 (0x65)
#define MOD_ATOP_SUBBANK_66 (0x66)

#define EFUSE_VAL_LSB	(0x252B0)
#define EFUSE_VAL_MSB	(0x252B4)
#define TIME_OUT_CNT	(10)
#define RINT_THRESHOLD	(0x200)	// 12M:0x200, 24M:0x100
#define MOD_VOL_VX1_ACT_BIT_V007	(6)
#define MOD_CUR_SINGLE_LSB	(7)
#define MOD_CUR_SINGLE_MASK (0x7F)
#define MOD_CUR_SINGLE_ACT_BIT	(14)
#define MOD_CUR_SINGLE_ACT_BIT_VER2	(24)

#define MOD_CUR_DOUBLE_MASK_V007 (0x7F)
#define MOD_CUR_DOUBLE_MASK_VER5 (0x3F)
#define MOD_CUR_DOUBLE_LSB_V007	(7)
#define MOD_CUR_DOUBLE_LSB_VER5	(7)
#define MOD_CUR_DOUBLE_OFFSET	(15)
#define MOD_CUR_DOUBLE_ACT_BIT	(22)
#define MOD_CUR_DOUBLE_ACT_BIT_V007	(16)
#define MOD_RINT_OFFSET		(23)
#define MOD_RINT_ACT_BIT	(30)
#define LPLL_RETIME_CTRL	(25)
#define LPLL_DELAY_TIME_CTRL	(26)

//max/min/default for RCON setting for swing calibration
#define RCON_MAX_VAL	(25)
#define RCON_MIN_VAL	(6)
#define RCON_DEF_VAL	(16)

//max/min/default for BiasCon
#define BIASCON_SINGLE_MAX_VAL	(85)
#define BIASCON_SINGLE_MIN_VAL	(55)
#define BIASCON_DOUBLE_MAX_VAL	(85)
#define BIASCON_DOUBLE_MIN_VAL	(55)
#define BIASCON_DEF_VAL	(70)
#define DIV_2	(2)
#define DIV_4	(4)
#define DIV_8	(8)

#define CHIP_VERSION2 (2)
#define CHIP_VERSION3 (3)
#define CHIP_VERSION4 (4)

#define TIMING_4K_H_ACTIVE 3840
#define TIMING_4K_V_ACTIVE 2160

#define HEX_0 (0x0)
#define HEX_1 (0x1)
#define HEX_10 (0x10)
#define HEX_11 (0x11)
#define HEX_22 (0x22)
#define HEX_C (0xc)
#define HEX_D (0xd)
#define HEX_F (0xf)
#define HEX_FFFF (0xffff)
#define HEX_1010 (0x1010)

//MT5873 XCPLL PD_CLK
#define XCPLL_REG_0004_SET (0x0010)

//MT5877 XCPLL CLK
#define XCPLL_REG_0007_SET (0x0001)
#define XCBPLL_REG_0007_SET (0x1100)
#define XC_CLK_007_INFRA_CK (0x3)
#define XC_CLK_007_XC_FN (0x2)
#define XCPLL_REG_0007_SET_0 (0xd957)
#define XCPLL_REG_0007_SET_1 (0x70)
#define XCPLL_REG_0007_ICTRL (0x3)
#define XCPLL_REG_0007_LOOP_DIV_FIRST (0x3)
#define XCPLL_REG_0007_LOOP_DIV_SECOND (0x6)
#define XCBPLL_ICTRL (0x2)
#define XCBPLL_LOOPDIV_SECOND (0x3c)
#define TEST_XCBPLL (0x10)
#define XCPLL_DELAY_TIME (500)  //us
#define XCPLL_4 (4)
#define XCPLL_8 (8)
#define XCPLL_12 (12)

#ifdef MSOS_TYPE_LINUX_KERNEL
#define mst_atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0);
#else
#define mst_atoi(str) strtoul(((str != NULL) ? str : ""), NULL, 0);
#endif

#define MOD_BLOCKPATTERN_TBL_MAX_SIZE_V007       (0x60)
#define MOD_BLOCKPATTERN_TBL_LINE_SIZE_V007      (0x18)
#define MOD_BLOCKPATTERN_ADDR_STEP               (4)

//for QMS
#define QMS_TFR_MAX 14
#define QMS_OUT_MAX 2

#ifndef MAX
#define MAX(a, b)            (((a) > (b)) ? (a) : (b))
#endif
#define SHIFT_LEFT_8(n)     ((n) << 8)

static const struct mtk_qms_tfr_mapping_info qms_info[QMS_OUT_MAX][QMS_TFR_MAX] = {
	{
		//Tfr  vfreq ratio
		{0, 0, 0, 0},
		{1, 2397, 2, 4795},
		{2, 2400, 2, 4800},
		{3, 2500, 2, 5000},
		{4, 2997, 2, 5994},
		{5, 3000, 2, 6000},
		{6, 4795, 1, 4795},
		{7, 4800, 1, 4800},
		{8, 5000, 1, 5000},
		{9, 5994, 1, 5994},
		{10, 6000, 1, 6000},
		{11, 10000, 0, 0},
		{12, 11988, 0, 0},
		{13, 12000, 0, 0},
	},
	{
		{0, 0, 0, 0},
		{1, 2397, 5, 11989},
		{2, 2400, 5, 12000},
		{3, 2500, 4, 10000},
		{4, 2997, 4, 11989},
		{5, 3000, 4, 12000},
		{6, 4795, 2, 9589},
		{7, 4800, 2, 9600},
		{8, 5000, 2, 10000},
		{9, 5994, 2, 11989},
		{10, 6000, 2, 12000},
		{11, 10000, 1, 10000},
		{12, 11988, 1, 11988},
		{13, 12000, 1, 12000},
	},

};

#if (VBY1_LOCK_PROTECT_EN)
void _mtk_pnl_checkLockProtect_v007(void)
{
#define COUNTMAX 50
#define TOGGLE_DELAY 50		//us
#define CHECK_DELAY 2		//ms
	bool bLocknEn = true;
	uint8_t u8uLockCount = 0;
	uint8_t u8ResetCount = 0;

	bLocknEn = R2BYTEMSK(REG_0184_MODV12_V007, REG_0184_MODV12_V007_REG_VBY1_LOCK_VIDEO);
	u8uLockCount = R2BYTEMSK(REG_01F8_MODV12_V007, REG_01F8_MODV12_V007_REG_UNLOCK_CNT);

	while ((bLocknEn == true) || (u8uLockCount != 0)) {
		if (bLocknEn) {
			if (u8uLockCount == 0) {
				// toggle vby1 test en
				W2BYTEMSK(REG_018C_MODV12_V007, true, REG_018C_MODV12_V007_REG_VBY1_TEST_EN);
				udelay(TOGGLE_DELAY);
				W2BYTEMSK(REG_018C_MODV12_V007, false, REG_018C_MODV12_V007_REG_VBY1_TEST_EN);
				// clear unlock cnt before training
				W2BYTEMSK(REG_01F8_MODV12_V007, true,
					  REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
				udelay(TOGGLE_DELAY);
				W2BYTEMSK(REG_01F8_MODV12_V007, false,
					  REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
				mdelay(CHECK_DELAY);
			} else {
				// clear unlock cnt before training
				W2BYTEMSK(REG_01F8_MODV12_V007, true,
					  REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
				udelay(TOGGLE_DELAY);
				W2BYTEMSK(REG_01F8_MODV12_V007, false,
					  REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
				mdelay(CHECK_DELAY);
			}
		} else {
			// clear unlock cnt before training
			W2BYTEMSK(REG_01F8_MODV12_V007, true, REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
			udelay(TOGGLE_DELAY);
			W2BYTEMSK(REG_01F8_MODV12_V007, false, REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
			mdelay(CHECK_DELAY);
		}

		bLocknEn = R2BYTEMSK(REG_0184_MODV12_V007, REG_0184_MODV12_V007_REG_VBY1_LOCK_VIDEO);
		u8uLockCount = R2BYTEMSK(REG_01F8_MODV12_V007, REG_01F8_MODV12_V007_REG_UNLOCK_CNT);

		if ((u8ResetCount > COUNTMAX) || ((bLocknEn == false) && (u8uLockCount == 0))) {
			if (u8ResetCount > COUNTMAX)
				debug("[%s] u8ResetCount=%d \n", __func__, u8ResetCount);
			break;
		}
		u8ResetCount++;
	}
}
#endif

static void _mtk_pnl_edpout_en_v007(struct udevice *dev, bool en)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 u8lanecount;
	bool boutputconfigen[E_BOOT_PNL_OUTPUT_LANE_MAX] = { false };

	switch (priv->linktype) {
	case E_LINK_EDP_4LANE_2K60:
	case E_LINK_EDP_4LANE_4K30:
	case E_LINK_EDP_4LANE_4K60:
		for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
			 u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
			if ((priv->lane_info.def_layout[u8lanecount] <
				 E_BOOT_PNL_OUTPUT_LANE4) && en)
				boutputconfigen[u8lanecount] = true;
			else
				boutputconfigen[u8lanecount] = false;
		}
		break;
	case E_LINK_EDP_8LANE_4K120:
		for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
			 u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
			if ((priv->lane_info.def_layout[u8lanecount] <
				 E_BOOT_PNL_OUTPUT_LANE8) && en)
				boutputconfigen[u8lanecount] = true;
			else
				boutputconfigen[u8lanecount] = false;
		}
		break;
	case E_LINK_EDP_16LANE_4K144:
	case E_LINK_EDP_16LANE_4K165:
		for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
			 u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
			if ((priv->lane_info.def_layout[u8lanecount] <
				 E_BOOT_PNL_OUTPUT_LANE16) && en)
				boutputconfigen[u8lanecount] = true;
			else
				boutputconfigen[u8lanecount] = false;
		}
		break;
	default:
		UBOOT_ERROR("[%s][%d] Not support out_timing\n", __func__, __LINE__);
		break;
	}
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE0],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH00);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE1],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH01);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE2],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH02);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE3],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH03);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE4],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH04);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE5],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH05);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE6],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH06);
	W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE7],
		  REG_00E8_MODA1_V007_REG_OUTCONF_CH07);

	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE8],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH08);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE9],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH09);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE10],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH10);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE11],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH11);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE12],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH12);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE13],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH13);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE14],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH14);
	W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE15],
		  REG_00EC_MODA1_V007_REG_OUTCONF_CH15);

	if (en && IS_EDP_OUT(priv->linktype))
		mtk_edp_train_all();
}

void mtk_pnl_out_en_v007(struct udevice *dev, bool en)
{
#define TOGGLE_DELAY 50		//us
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 u8lanecount;
	u32 i = 0, u32Freq = 0, u32vfreq = 0;
	//uint8_t PortIdx = 0; //eDP usage
	//uint8_t eDPTrainingCount = 0; //eDP usage
	bool boutputconfigen[E_BOOT_PNL_OUTPUT_LANE_MAX] = { false };
	en_boot_pnl_output_lane_config eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE0;

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}
	UBOOT_DEBUG("[%s] enable panel output :%d\n", __func__, en);

	//Check lpll err: judge vfreq +/-3%, reint master lpll
	u32vfreq = priv->typ_dclk / priv->typ_vtt / priv->typ_htt;
	if (priv->ssc_info.ssc_en)
		W2BYTEMSK(REG_0030_LPLLA_V007, 0, REG_0030_LPLLA_V007_REG_LPLL_MASTER_SSC_MODE);

	do {
		u32Freq = (R2BYTEMSK(REG_0010_TGEN_MAIN_BKA3A0,
			REG_0010_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_0) << DEC_16) +
			R2BYTEMSK(REG_0014_TGEN_MAIN_BKA3A0, REG_0014_TGEN_MAIN_BKA3A0_REG_TGEN_DEBUG_READBACK_1) - 1;
		u32Freq = DEC_24000000 / u32Freq;

		if (u32Freq < (u32vfreq - (u32vfreq * DEC_3 / DEC_100)) ||
			u32Freq > (u32vfreq + (u32vfreq * DEC_3 / DEC_100))) {
			UBOOT_ERROR("For lpll debug, target value(%d):check output vFreq = %d\n", u32vfreq, u32Freq);
			UBOOT_ERROR("reint master_pll, reinit cnt = %d\n", ++i);
			W2BYTEMSK(REG_005C_LPLLA_V007, DEC_3, Fld(DEC_16, 0, AC_FULLW10));
			W2BYTEMSK(REG_005C_LPLLA_V007, 0x1, REG_005C_LPLLA_V007_REG_LPLL_MASTER_PWR_ON); //Master PLL power on
			dsb(); //DSB to make sure the operation is complete
			udelay(DEC_2); //delay 2us.
			W2BYTEMSK(REG_005C_LPLLA_V007, 0x0, REG_005C_LPLLA_V007_REG_LPLL_MASTER_ISO_EN); //Master PLL isolation en
			dsb();
			udelay(1); //delay 1us.
			W2BYTEMSK(REG_005C_LPLLA_V007, 0x0, REG_005C_LPLLA_V007_REG_LPLL_MASTER_PD); //Master power down release
			dsb();
			udelay(DEC_500); //delay 500us
		}

		if (i > DEC_10) {
			UBOOT_ERROR("Max reint cnt, break\n");
			break; //max time consumption: 5ms
		}
	} while (u32Freq < (u32vfreq - (u32vfreq * DEC_3 / DEC_100)) ||
		u32Freq > (u32vfreq + (u32vfreq * DEC_3 / DEC_100)));

	if (priv->ssc_info.ssc_en)
		W2BYTEMSK(REG_0030_LPLLA_V007, 1, REG_0030_LPLLA_V007_REG_LPLL_MASTER_SSC_MODE);

	if (priv->tcon_info.bUsingTCON) {
		if (is_tcon_sti_flow()) {
			//The order required by the general panel should be load pmic first
			//and then load tcon bin power on
			mtk_tcon_enable(dev, en);
			TCON_DEBUG("Tcon related output config settings are set in tcon bin.\n");
		} else {
			MHal_PNL_EnableTcon(dev);
		}
		return;
	}
	// clear unlock cnt before training
	W2BYTEMSK(REG_01F8_MODV12_V007, true, REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);
	udelay(TOGGLE_DELAY);
	W2BYTEMSK(REG_01F8_MODV12_V007, false, REG_01F8_MODV12_V007_REG_UNLOCK_CNT_CLR);

	if (en == true && priv->linktype == E_LINK_VB1) {
		W2BYTEMSK(REG_0184_MODV12_V007, 0xF, REG_0184_MODV12_V007_REG_VBY1_ALN_DE_CNT);
		W2BYTEMSK(REG_0184_MODV12_V007, 0x3F, REG_0184_MODV12_V007_REG_VBY1_ALN_PIX_CNT);
		//enable vby1 hw training.
		W2BYTEMSK(REG_0180_MODV12_V007, 0xAAE, Fld(16, 0, AC_FULLW10));
	}
	//video part. if use tcon bin, don't set outen here
	UBOOT_DEBUG("[%s][%d]linktype = %d, out_timing = %d\n", __func__, __LINE__, priv->linktype, priv->out_timing);
	switch (priv->linktype) {
	case E_LINK_EDP_4LANE_2K60:
	case E_LINK_EDP_4LANE_4K30:
	case E_LINK_EDP_4LANE_4K60:
	case E_LINK_EDP_8LANE_4K120:
	case E_LINK_EDP_16LANE_4K144:
	case E_LINK_EDP_16LANE_4K165:
		_mtk_pnl_edpout_en_v007(dev, en);
		break;
	case E_LINK_VB1:
		switch (priv->out_timing) {
		case E_FHD_60HZ:
			for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
				 u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
				if ((priv->lane_info.def_layout[u8lanecount] <
					 E_BOOT_PNL_OUTPUT_LANE2) && en)
					boutputconfigen[u8lanecount] = true;
				else
					boutputconfigen[u8lanecount] = false;
			}
			break;
		case E_FHD_120HZ:
		case E_4K2K_30HZ:
			for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
				 u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
				if ((priv->lane_info.def_layout[u8lanecount] <
					 E_BOOT_PNL_OUTPUT_LANE4) && en)
					boutputconfigen[u8lanecount] = true;
				else
					boutputconfigen[u8lanecount] = false;
			}
			break;
		case E_FHD_240HZ:
		case E_4K2K_60HZ:
		case E_4K1K_120HZ:
		case E_4K1K_144HZ:
			if (priv->lane_duplicate_en)
				eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE16;
			else
				eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE8;

			for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
				 u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
				if ((priv->lane_info.def_layout[u8lanecount] <
					 eOutputLaneEnNumber) && en)
					boutputconfigen[u8lanecount] = true;
				else
					boutputconfigen[u8lanecount] = false;
			}
			break;
		case E_4K2K_120HZ:
		case E_4K2K_144HZ:
		case E_4K2K_165HZ:
		case E_4K1K_240HZ:
		case E_4K1K_288HZ:
		case E_4K1K_330HZ:
		case E_5K2K_60HZ:
			for (u8lanecount = E_BOOT_PNL_OUTPUT_LANE0;
				u8lanecount < E_BOOT_PNL_OUTPUT_LANE16; u8lanecount++) {
				if ((priv->lane_info.def_layout[u8lanecount] <
					E_BOOT_PNL_OUTPUT_LANE16) && en)
					boutputconfigen[u8lanecount] = true;
				else
					boutputconfigen[u8lanecount] = false;
			}
			break;
		default:
			UBOOT_ERROR("[%s][%d] Not support out_timing\n", __func__, __LINE__);
			break;
		}

		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE0],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH00);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE1],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH01);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE2],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH02);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE3],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH03);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE4],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH04);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE5],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH05);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE6],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH06);
		W2BYTEMSK(REG_00E8_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE7],
			  REG_00E8_MODA1_V007_REG_OUTCONF_CH07);

		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE8],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH08);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE9],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH09);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE10],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH10);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE11],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH11);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE12],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH12);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE13],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH13);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE14],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH14);
		W2BYTEMSK(REG_00EC_MODA1_V007, boutputconfigen[E_BOOT_PNL_OUTPUT_LANE15],
			  REG_00EC_MODA1_V007_REG_OUTCONF_CH15);
		break;
	case E_LINK_LVDS:
	case E_LINK_HSLVDS_1CH:
	case E_LINK_HSLVDS_2CH:
		switch (priv->out_timing) {
		case E_HD_60HZ:
			W2BYTEMSK(REG_00E8_MODA1_V007, en ? HEX_0X5550 : 0x0,
				  Fld(DEC_16, 0, AC_FULLW10));
			W2BYTEMSK(REG_00EC_MODA1_V007, en ? 0x0000 : 0x0,
				  Fld(DEC_16, 0, AC_FULLW10));
			break;
		case E_FHD_60HZ:
		case E_HD_120HZ:
			W2BYTEMSK(REG_00E8_MODA1_V007, en ? HEX_0X5550 : 0x0,
				  Fld(DEC_16, 0, AC_FULLW10));
			W2BYTEMSK(REG_00EC_MODA1_V007, en ? HEX_0X0555 : 0x0,
				  Fld(DEC_16, 0, AC_FULLW10));
			break;
		default:
			UBOOT_ERROR("[%s][%d] Not support out_timing\n", __func__, __LINE__);
			break;
		}
		break;
	default:
		UBOOT_ERROR("[%s][%d] Not support link_type\n", __func__, __LINE__);
		break;
	}

#if (VBY1_LOCK_PROTECT_EN)
	if (en)
		_mtk_pnl_checkLockProtect_v007();
#endif
}

void mtk_pnl_mute_en_v007(struct udevice *dev, bool en)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u16 pixel_tbl[MOD_BLOCKPATTERN_TBL_MAX_SIZE_V007];
	u8 idx_num = 0;

	if (!priv) {
		printf("%s: priv is NULL\n", __func__);
		return;
	}

	UBOOT_TRACE("(%s): panel version: %d\n",
		    en ? "MUTE" : "UNMUTE",
		    priv->pnl_lib_version);
	// Vcom pattern
	for (idx_num = 0; idx_num < MOD_BLOCKPATTERN_TBL_MAX_SIZE_V007; idx_num++) {
	     pixel_tbl[idx_num] = 0x00;
	     idx_num++;
	     pixel_tbl[idx_num] = 0x00;
	     idx_num++;
	     pixel_tbl[idx_num] = 0x00;
	}

	if (en)	{
		if (mtk_pnl_set_mod_block_pattern_table_v007(pixel_tbl, MOD_BLOCKPATTERN_TBL_MAX_SIZE_V007, false)) {
			mtk_pnl_set_mod_block_pattern_enable_v007(true);
		} else {
			mtk_pnl_set_mod_block_pattern_enable_v007(false);
			UBOOT_DEBUG("set block pattern table fail!!\n");
		}
	} else {
		mtk_pnl_set_mod_block_pattern_enable_v007(false);
	}
}

void mtk_pnl_set_vby1_mft_hmirror_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv->cus_info.hmirror_en == true) {
		W2BYTEMSK(REG_0004_MODV11_V007, 1, REG_0004_MODV11_V007_REG_MFT_H_MIRROR);
		//W2BYTEMSK(REG_0004_MODV21, 1, REG_0004_MODV21_REG_MFT_H_MIRROR);
		//W2BYTEMSK(REG_0004_MODOSD1, 1, REG_0004_MODOSD1_REG_MFT_H_MIRROR);
	} else {
		W2BYTEMSK(REG_0004_MODV11_V007, 0, REG_0004_MODV11_V007_REG_MFT_H_MIRROR);
		//W2BYTEMSK(REG_0004_MODV21, 0, REG_0004_MODV21_REG_MFT_H_MIRROR);
		//W2BYTEMSK(REG_0004_MODOSD1, 0, REG_0004_MODOSD1_REG_MFT_H_MIRROR);
	}
}

void mtk_swing_level_setting_v007(struct udevice *dev)
{
	u16 swing_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	if (priv->tcon_info.bUsingTCON) {
		TCON_DEBUG("Tcon related swing settings are set in tcon bin.\n");
		return;
	}

	if (priv->swing_info.usr_swing_level) {
		//usr_swing_level : True , 0 is flase , >= 1 is True
		switch (priv->linktype) {
		case E_LINK_VB1:
		case E_LINK_EDP_4LANE_2K60:
		case E_LINK_EDP_4LANE_4K30:
		case E_LINK_EDP_4LANE_4K60:
		case E_LINK_EDP_8LANE_4K120:
		case E_LINK_EDP_16LANE_4K144:
		case E_LINK_EDP_16LANE_4K165:
			if (priv->swing_info.common_swing != 0) {
				//common_swing: True , 0 is flase , >= 1 is True
				UBOOT_DEBUG("[pnl]common swing value = %d, ctrl_lanes = %d\n",
					    priv->swing_info.swing_level[0],
					    priv->swing_info.ctrl_lanes);
				for (u32 i = 1; i < priv->swing_info.ctrl_lanes; i++)
					priv->swing_info.swing_level[i] = priv->swing_info.swing_level[0];
			}

			swing_val = (priv->swing_info.swing_level[DEC_3] & HEX_0XF) << DEC_12 |
			    (priv->swing_info.swing_level[DEC_2] & HEX_0XF) << DEC_8 |
			    (priv->swing_info.swing_level[1] & HEX_0XF) << DEC_4 |
			    (priv->swing_info.swing_level[0] & HEX_0XF);
			UBOOT_DEBUG("[pnl]swing value ch3~0 = %d\n", swing_val);
			W2BYTEMSK(REG_00E0_MODA2_V007, swing_val, Fld(DEC_16, 0, AC_FULLW10));	//ch0-ch3

			swing_val = (priv->swing_info.swing_level[DEC_7] & HEX_0XF) << DEC_12 |
			    (priv->swing_info.swing_level[DEC_6] & HEX_0XF) << DEC_8 |
			    (priv->swing_info.swing_level[DEC_5] & HEX_0XF) << DEC_4 |
			    (priv->swing_info.swing_level[DEC_4] & HEX_0XF);
			UBOOT_DEBUG("[pnl]swing value ch7~4 = %d\n", swing_val);
			W2BYTEMSK(REG_00E4_MODA2_V007, swing_val, Fld(DEC_16, 0, AC_FULLW10));	//ch4-ch7

			swing_val = (priv->swing_info.swing_level[DEC_11] & HEX_0XF) << DEC_12 |
			    (priv->swing_info.swing_level[DEC_10] & HEX_0XF) << DEC_8 |
			    (priv->swing_info.swing_level[DEC_9] & HEX_0XF) << DEC_4 |
			    (priv->swing_info.swing_level[DEC_8] & HEX_0XF);
			UBOOT_DEBUG("[pnl]swing value ch11~8 = %d\n", swing_val);
			W2BYTEMSK(REG_00E8_MODA2_V007, swing_val, Fld(DEC_16, 0, AC_FULLW10));	//ch8-ch11

			swing_val = (priv->swing_info.swing_level[DEC_15] & HEX_0XF) << DEC_12 |
			    (priv->swing_info.swing_level[DEC_14] & HEX_0XF) << DEC_8 |
			    (priv->swing_info.swing_level[DEC_13] & HEX_0XF) << DEC_4 |
			    (priv->swing_info.swing_level[DEC_12] & HEX_0XF);
			UBOOT_DEBUG("[pnl]swing value ch15~12 = %d\n", swing_val);
			W2BYTEMSK(REG_00EC_MODA2_V007, swing_val, Fld(DEC_16, 0, AC_FULLW10));	//ch12-ch15
			break;
		case E_LINK_LVDS:
		case E_LINK_HSLVDS_1CH:
		case E_LINK_HSLVDS_2CH:
			if (priv->swing_info.common_swing != 0) {
				//common_swing : True , 0 is flase , >= 1 is True
				UBOOT_DEBUG("[pnl]LVDS icon common swing value = %d, ctrl_lanes = %d\n",
					    priv->swing_info.swing_level[0],
					    priv->swing_info.ctrl_lanes);
				for (u32 i = 1; i < priv->swing_info.ctrl_lanes; i++)
					priv->swing_info.swing_level[i] = priv->swing_info.swing_level[0];
			} else {
				for (u32 i = 0; i < priv->swing_info.ctrl_lanes; i++)
					UBOOT_DEBUG("[pnl]LVDS_lane%d icon swing value = %d\n", i, priv->swing_info.swing_level[i]);
			}

			W2BYTEMSK(REG_0080_MODA2_V007, priv->swing_info.swing_level[0],
				REG_0080_MODA2_V007_REG_ICON_CH00);	//ch0
			W2BYTEMSK(REG_0084_MODA2_V007, priv->swing_info.swing_level[1],
				REG_0084_MODA2_V007_REG_ICON_CH01);	//ch1
			W2BYTEMSK(REG_0088_MODA2_V007, priv->swing_info.swing_level[DEC_2],
				REG_0088_MODA2_V007_REG_ICON_CH02);	//ch2
			W2BYTEMSK(REG_008C_MODA2_V007, priv->swing_info.swing_level[DEC_3],
				REG_008C_MODA2_V007_REG_ICON_CH03);	//ch3

			W2BYTEMSK(REG_0090_MODA2_V007, priv->swing_info.swing_level[DEC_4],
				REG_0090_MODA2_V007_REG_ICON_CH04);	//ch4
			W2BYTEMSK(REG_0094_MODA2_V007, priv->swing_info.swing_level[DEC_5],
				REG_0094_MODA2_V007_REG_ICON_CH05);	//ch5
			W2BYTEMSK(REG_0098_MODA2_V007, priv->swing_info.swing_level[DEC_6],
				REG_0098_MODA2_V007_REG_ICON_CH06);	//ch6
			W2BYTEMSK(REG_009C_MODA2_V007, priv->swing_info.swing_level[DEC_7],
				REG_009C_MODA2_V007_REG_ICON_CH07);	//ch7

			W2BYTEMSK(REG_00A0_MODA2_V007, priv->swing_info.swing_level[DEC_8],
				REG_00A0_MODA2_V007_REG_ICON_CH08);	//ch8
			W2BYTEMSK(REG_00A4_MODA2_V007, priv->swing_info.swing_level[DEC_9],
				REG_00A4_MODA2_V007_REG_ICON_CH09);	//ch9
			W2BYTEMSK(REG_00A8_MODA2_V007, priv->swing_info.swing_level[DEC_10],
				REG_00A8_MODA2_V007_REG_ICON_CH10); //ch10
			W2BYTEMSK(REG_00AC_MODA2_V007, priv->swing_info.swing_level[DEC_11],
				REG_00AC_MODA2_V007_REG_ICON_CH11); //ch11

			W2BYTEMSK(REG_00B0_MODA2_V007, priv->swing_info.swing_level[DEC_12],
				REG_00B0_MODA2_V007_REG_ICON_CH12); //ch12
			W2BYTEMSK(REG_00B4_MODA2_V007, priv->swing_info.swing_level[DEC_13],
				REG_00B4_MODA2_V007_REG_ICON_CH13); //ch13
			W2BYTEMSK(REG_00B8_MODA2_V007, priv->swing_info.swing_level[DEC_14],
				REG_00B8_MODA2_V007_REG_ICON_CH14); //ch14
			W2BYTEMSK(REG_00BC_MODA2_V007, priv->swing_info.swing_level[DEC_15],
				REG_00BC_MODA2_V007_REG_ICON_CH15); //ch15
			break;
		default:
			UBOOT_ERROR("Not support linktype\n");
			break;
		}
	} else {
		UBOOT_DEBUG("%s: use def hw swing value\n", __func__);
	}
}

void mtk_pre_emphasis_setting_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	if (priv->pe_info.pe_usr != 0) {
		if (priv->pe_info.ctrl_lanes <= DEC_16) {
			W2BYTEMSK(REG_003C_MODA2_V007, HEX_FFFF >> (DEC_16 - priv->pe_info.ctrl_lanes),
				  REG_003C_MODA2_V007_REG_EN_PE_CH15_00);
		} else {
			W2BYTEMSK(REG_003C_MODA2_V007, HEX_FFFF, REG_003C_MODA2_V007_REG_EN_PE_CH15_00);
		}
	}

	if (priv->pe_info.pe_usr != 0) {
		if (priv->pe_info.common_pe != 0) {
			//pe_usr:True and common_pe: True , 0 is flase , >= 1 is True
			for (u32 i = 1; i < priv->pe_info.ctrl_lanes; i++)
				priv->pe_info.pe_level[i] = priv->pe_info.pe_level[0];
		}
			W2BYTEMSK(REG_0040_MODA2_V007, priv->pe_info.pe_level[0],
				  REG_0040_MODA2_V007_REG_PE_ADJ_CH00);
			W2BYTEMSK(REG_0040_MODA2_V007, priv->pe_info.pe_level[1],
				  REG_0040_MODA2_V007_REG_PE_ADJ_CH01);
			W2BYTEMSK(REG_0044_MODA2_V007, priv->pe_info.pe_level[DEC_2],
				  REG_0044_MODA2_V007_REG_PE_ADJ_CH02);
			W2BYTEMSK(REG_0044_MODA2_V007, priv->pe_info.pe_level[DEC_3],
				  REG_0044_MODA2_V007_REG_PE_ADJ_CH03);
			W2BYTEMSK(REG_0048_MODA2_V007, priv->pe_info.pe_level[DEC_4],
				  REG_0048_MODA2_V007_REG_PE_ADJ_CH04);
			W2BYTEMSK(REG_0048_MODA2_V007, priv->pe_info.pe_level[DEC_5],
				  REG_0048_MODA2_V007_REG_PE_ADJ_CH05);
			W2BYTEMSK(REG_004C_MODA2_V007, priv->pe_info.pe_level[DEC_6],
				  REG_004C_MODA2_V007_REG_PE_ADJ_CH06);
			W2BYTEMSK(REG_004C_MODA2_V007, priv->pe_info.pe_level[DEC_7],
				  REG_004C_MODA2_V007_REG_PE_ADJ_CH07);
			W2BYTEMSK(REG_0050_MODA2_V007, priv->pe_info.pe_level[DEC_8],
				  REG_0050_MODA2_V007_REG_PE_ADJ_CH08);
			W2BYTEMSK(REG_0050_MODA2_V007, priv->pe_info.pe_level[DEC_9],
				  REG_0050_MODA2_V007_REG_PE_ADJ_CH09);
			W2BYTEMSK(REG_0054_MODA2_V007, priv->pe_info.pe_level[DEC_10],
				  REG_0054_MODA2_V007_REG_PE_ADJ_CH10);
			W2BYTEMSK(REG_0054_MODA2_V007, priv->pe_info.pe_level[DEC_11],
				  REG_0054_MODA2_V007_REG_PE_ADJ_CH11);
			W2BYTEMSK(REG_0058_MODA2_V007, priv->pe_info.pe_level[DEC_12],
				  REG_0058_MODA2_V007_REG_PE_ADJ_CH12);
			W2BYTEMSK(REG_0058_MODA2_V007, priv->pe_info.pe_level[DEC_13],
				  REG_0058_MODA2_V007_REG_PE_ADJ_CH13);
			W2BYTEMSK(REG_005C_MODA2_V007, priv->pe_info.pe_level[DEC_14],
				  REG_005C_MODA2_V007_REG_PE_ADJ_CH14);
			W2BYTEMSK(REG_005C_MODA2_V007, priv->pe_info.pe_level[DEC_15],
				  REG_005C_MODA2_V007_REG_PE_ADJ_CH15);
	} else {
		//use hw default value
		UBOOT_DEBUG("[%s,%5d] use hw def pre-emphasis setting\n", __func__, __LINE__);
	}
}

void mtk_SSC_control_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u64 tmp = 0;
	u64 lpll_set = 0;
	u64 lpll_set_slave = 0;
	u64 sdm_pcw = 0;
	u64 sdm_pcw_slave = 0;
	u32 ssc_span = 0;
	u32 ssc_delta = 0;
	u32 ssc_delta1 = 0;
	u32 ssc_delta_slave = 0;
	u32 ssc_delta1_slave = 0;
	u32 unit_align_vby1 = 1;
	st_out_ssc_ctrl stCtrl;

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	if (priv->tcon_info.bUsingTCON && priv->tcon_info.stPanelInfo.u32SSC_TconBinCtrl == 0) {
		unit_align_vby1 = 1;
		stCtrl.ssc_en = priv->tcon_info.stPanelInfo.u32SSCEnable;
		stCtrl.ssc_modulation = priv->tcon_info.stPanelInfo.u32SSC_Fmodulation;
		stCtrl.ssc_deviation = priv->tcon_info.stPanelInfo.u32SSC_Percentage;
		UBOOT_DEBUG("[%s,%5d] TCON control SSC value\n", __func__, __LINE__);
	} else {
		unit_align_vby1 = DEC_10;
		stCtrl.ssc_en = priv->ssc_info.ssc_en;
		stCtrl.ssc_modulation = priv->ssc_info.ssc_modulation;
		stCtrl.ssc_deviation = priv->ssc_info.ssc_deviation;
	}

	if (stCtrl.ssc_en) {
		lpll_set = (((uint64_t)R2BYTEMSK(REG_0044_LPLLA_V007,
									REG_0048_LPLLA_V007_REG_LPLL_MASTER_SDM_PCW_2)) << DEC_32);
		lpll_set |= (((uint64_t)R2BYTEMSK(REG_0044_LPLLA_V007,
									REG_0044_LPLLA_V007_REG_LPLL_MASTER_SDM_PCW_1)) << DEC_16);
		lpll_set |= (uint64_t)R2BYTEMSK(REG_0040_LPLLA_V007,
									REG_0040_LPLLA_V007_REG_LPLL_MASTER_SDM_PCW_0);
		lpll_set_slave |= (((uint64_t)R2BYTEMSK(REG_0084_LPLLA_V007,
									REG_0084_LPLLA_V007_REG_LPLL_SLAVE_SDM_PCW_1)) << DEC_16);
		lpll_set_slave |= (uint64_t)R2BYTEMSK(REG_0080_LPLLA_V007,
									REG_0080_LPLLA_V007_REG_LPLL_SLAVE_SDM_PCW_0);
		sdm_pcw = (lpll_set + (1 << DEC_23)) / (1 << DEC_24);
		sdm_pcw_slave = (lpll_set_slave + (1 << DEC_23)) / (1 << DEC_24);
		UBOOT_DEBUG("\n  SSC LPLL set value : 0x%llx\n", lpll_set);
		UBOOT_DEBUG("\n  SSC sdm_pcw value : 0x%llx\n", sdm_pcw);
		UBOOT_DEBUG("\n  SSC Slave LPLL set value : 0x%llx\n", lpll_set_slave);
		UBOOT_DEBUG("\n  SSC Slave sdm_pcw value : 0x%llx\n", sdm_pcw_slave);
		if (lpll_set == 0 || (IS_EDP_OUT(priv->linktype) && (lpll_set_slave == 0))) {
			UBOOT_ERROR("LPLL_SET is 0. Check NG\n");
			return;
		}
		//Cal modulation (ssc span)
		if (stCtrl.ssc_modulation != 0) {
			tmp = (uint64_t)MPLL_CLK_54MHZ * DEC_1000;
			ssc_span = (tmp + stCtrl.ssc_modulation) / (stCtrl.ssc_modulation * DEC_2);

			UBOOT_DEBUG("\n  SSC Span value : 0x%x\n", ssc_span);
			W2BYTEMSK(REG_0034_LPLLA_V007, ssc_span, REG_0034_LPLLA_V007_REG_LPLL_MASTER_SPAN);
			W2BYTEMSK(REG_006C_LPLLA_V007, ssc_span, REG_006C_LPLLA_V007_REG_LPLL_SLAVE_SPAN);
		}

		//ssc delta/delta1 (deviation)
		if (ssc_span != 0) {
			tmp = (uint64_t)sdm_pcw * stCtrl.ssc_deviation * (1 << DEC_18);
			UBOOT_DEBUG("\n  SSC tmp : %llx\n", tmp);
			ssc_delta1 = (tmp + (ssc_span * DEC_500 * unit_align_vby1)) / (ssc_span * DEC_1000 * unit_align_vby1);
			ssc_delta = ssc_delta1 * DEC_2;
			tmp = ((uint64_t)(tmp) * stCtrl.ssc_deviation);

			UBOOT_DEBUG("\n  SSC ssc_delta1 value : %x\n", ssc_delta1);
			UBOOT_DEBUG("\n  SSC ssc_delta value : %x\n", ssc_delta);
			W2BYTEMSK(REG_0050_LPLLA_V007, ssc_delta1, REG_0050_LPLLA_V007_REG_LPLL_MASTER_SDM_SSC_DELTA1);
			W2BYTEMSK(REG_004C_LPLLA_V007, ssc_delta, REG_004C_LPLLA_V007_REG_LPLL_MASTER_SDM_SSC_DELTA);

			tmp = (uint64_t)sdm_pcw_slave * stCtrl.ssc_deviation * (1 << DEC_18);
			UBOOT_DEBUG("\n  SSC Slave tmp : %llx\n", tmp);
			ssc_delta1_slave = (tmp + (ssc_span * DEC_500 * unit_align_vby1)) / (ssc_span * DEC_1000 * unit_align_vby1);
			ssc_delta_slave = ssc_delta1_slave * DEC_2;
			tmp = ((uint64_t)(tmp) * stCtrl.ssc_deviation);

			UBOOT_DEBUG("\n  SSC Slave ssc_delta1 value : %x\n", ssc_delta1_slave);
			UBOOT_DEBUG("\n  SSC Slave ssc_delta value : %x\n", ssc_delta_slave);
			W2BYTEMSK(REG_0090_LPLLA_V007, ssc_delta1_slave, REG_0090_LPLLA_V007_REG_LPLL_SLAVE_SDM_SSC_DELTA1);
			W2BYTEMSK(REG_008C_LPLLA_V007, ssc_delta_slave, REG_008C_LPLLA_V007_REG_LPLL_SLAVE_SDM_SSC_DELTA);
		}

		//ssc enable
		W2BYTEMSK(REG_0030_LPLLA_V007, stCtrl.ssc_en, REG_0030_LPLLA_V007_REG_LPLL_MASTER_SSC_MODE);
		if (IS_EDP_OUT(priv->linktype))
			W2BYTEMSK(REG_0070_LPLLA_V007, stCtrl.ssc_en, REG_0070_LPLLA_V007_REG_LPLL_SLAVE_SSC_MODE);
	} else {
		UBOOT_DEBUG("\n Panel SSC is disable\n");
	}
}

void mtk_skew_level_setting_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_DEBUG("get device private fail\n");
		return;
	}

	UBOOT_DEBUG("Panel skew enable : %d\n", priv->skew_info.bPanelSkewCtrlEN);
	UBOOT_DEBUG("Panel skew ctrl lanes : %d\n", priv->skew_info.SkewCtrlLanes);

	for (int i = 0; i < priv->skew_info.SkewCtrlLanes; i++)
		UBOOT_DEBUG("Panel skew_level_lanes[%d] : %d\n", i, priv->skew_info.SkewLevel[i]);

	if (priv->skew_info.bPanelSkewCtrlEN &&
		(priv->linktype == E_LINK_VB1 ||
		 priv->linktype == E_LINK_LVDS ||
		 priv->linktype == E_LINK_HSLVDS_1CH ||
		 priv->linktype == E_LINK_HSLVDS_2CH ||
		 IS_EDP_OUT(priv->linktype))) {
		if (priv->skew_info.SkewCtrlLanes <= DEC_16) {
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_0], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH00);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_1], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH01);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_2], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH02);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_3], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH03);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_4], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH04);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_5], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH05);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_6], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH06);
			W2BYTEMSK(REG_0034_MODA2_V007, priv->skew_info.SkewLevel[DEC_7], REG_0034_MODA2_V007_REG_FTUNE_SKEW_CH07);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_8], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH08);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_9], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH09);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_10], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH10);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_11], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH11);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_12], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH12);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_13], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH13);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_14], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH14);
			W2BYTEMSK(REG_0038_MODA2_V007, priv->skew_info.SkewLevel[DEC_15], REG_0038_MODA2_V007_REG_FTUNE_SKEW_CH15);
		}
	}
}

void mtk_pnl_controlbit_init_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	u16 metadata_low = 0, metadata_high = 0;

	//If CVRL_BIT_OFF OFF
	if (priv->cus_info.ctrl_bit_en != true) {
		UBOOT_DEBUG("ctrl_bit_en = 0x%x\n", priv->cus_info.ctrl_bit_en);
		return;
	}

	//Mdata V1
	W2BYTEMSK(REG_0020_MODV12, HEX_0X0201, Fld(DEC_16, 0, AC_FULLW10));
	//[11:8]reg_meta_delay_num
	//[3]reg_meta_delay_auto
	//[2]reg_meta_mode
	//[1]reg_meta_test_en
	//[0]reg_meta_data_en
	W2BYTEMSK(REG_0024_MODV12, HEX_0X0010, Fld(DEC_16, 0, AC_FULLW10));
	//[15:0]reg_meta_data_num
	W2BYTEMSK(REG_0028_MODV12, 0x0000, Fld(DEC_16, 0, AC_FULLW10));
	//[15:0]reg_meta_hs_sel

	metadata_low = HEX_0X0100;//VG Stable Flag(VGSF)=TRUE at boot stage
	metadata_high = 0x0;

	//v1 data lane 1~16
	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F40, Fld(DEC_16, 0, AC_FULLW10));
	//[4:0]v1_address [6]db_enable[12:8]out numnber
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F60, Fld(DEC_16, 0, AC_FULLW10));
	//[5]trig signal

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F41, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F61, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F42, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F62, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F43, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F63, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F44, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F64, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F45, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F65, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F46, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F66, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F47, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F67, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F48, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F60, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F49, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F69, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F4A, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F6A, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F4B, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F6B, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F4C, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F6C, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F4D, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F6D, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F4E, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F6E, Fld(DEC_16, 0, AC_FULLW10));

	W2BYTEMSK(REG_0004_META_DATA_TRANSFER_BKA35A_V007, metadata_low,
		REG_0004_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_0);//v1_dat lsb[15:0]
	W2BYTEMSK(REG_0008_META_DATA_TRANSFER_BKA35A_V007, metadata_high,
		REG_0008_META_DATA_TRANSFER_BKA35A_V007_REG_V1_MDATA_UPD_DAT_1);//v1_dat msb[7:0]
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F4F, Fld(DEC_16, 0, AC_FULLW10));
	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007, HEX_0X1F6F, Fld(DEC_16, 0, AC_FULLW10));


	W2BYTEMSK(REG_000C_META_DATA_TRANSFER_BKA35A_V007,  HEX_0X1FC0, Fld(DEC_16, 0, AC_FULLW10));//ouble buff trig
	W2BYTEMSK(REG_0028_META_DATA_TRANSFER_BKA35A_V007,  HEX_0X0040, Fld(DEC_16, 0, AC_FULLW10));//sw trig out
}


void mtk_out_if_hbkproch_protect_init_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	u8 u8H_minus_line = 0;

	u8 u8Meta_data_mode_shift_line = 0;
	u16 u16Hstart_div_lane = 0;
	u16 u16Hread_de_st_set = 0;
	u32 u32lanebackup = 0;

	if (priv->lanes == 1) {
	    UBOOT_DEBUG("[%s][PNL_LIB %d] HD case do not calculate hbkporch protect\n", __func__,
	    priv->pnl_lib_version);
	    return;
	}

	u32lanebackup = priv->lanes;
	if (IS_EDP_OUT(priv->linktype))
		priv->lanes = DEC_8; // eDP in MOD always 8p connect for hbkproch protect calculation

	W2BYTEMSK(REG_01E4_MODV11_V007, 0x1, REG_01E4_MODV11_V007_REG_HS_WID_ADJ_EN);


	if (priv->lanes >= VBO_USE_LANE_NUM_8)
	    W2BYTEMSK(REG_000C_MODV11_V007, (priv->lanes / DIV_8) - 1, REG_000C_MODV11_V007_REG_MFT_VLD_WRAP_FIX_HTT);

	if (priv->lanes == VBO_USE_LANE_NUM_8)
		u8H_minus_line = DEC_4;
	else if (priv->lanes == VBO_USE_LANE_NUM_16)
		u8H_minus_line = DEC_2;
	else
		u8H_minus_line = 0;

	if (R2BYTEMSK(REG_0020_MODV12_V007, REG_0020_MODV12_V007_REG_META_DATA_EN) == 0)
		u8Meta_data_mode_shift_line = 0;
	else
		u8Meta_data_mode_shift_line = DEC_5;

	if (priv->out_format == E_OUTPUT_YUV422 || priv->out_format == E_OUTPUT_YUV420)
		u16Hstart_div_lane = ((priv->de_hstart / DIV_2) / priv->lanes);
	else
		u16Hstart_div_lane = priv->de_hstart / priv->lanes;

	if ((u16Hstart_div_lane + u8Meta_data_mode_shift_line) >= (u8H_minus_line))
		u16Hread_de_st_set = u16Hstart_div_lane - u8H_minus_line + u8Meta_data_mode_shift_line;
	else
		u16Hread_de_st_set = 0;

	W2BYTEMSK(REG_003C_MODV11_V007, u16Hread_de_st_set, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);


	if ((priv->hsync_w / priv->lanes) == 0)
		W2BYTEMSK(REG_0014_MODV11_V007, 0, REG_0014_MODV11_V007_REG_HS_FP_DELAY_VALUE);
	else
		W2BYTEMSK(REG_0014_MODV11_V007, (priv->hsync_w / priv->lanes) - 1, REG_0014_MODV11_V007_REG_HS_FP_DELAY_VALUE);

	if (IS_EDP_OUT(priv->linktype))
		priv->lanes = u32lanebackup; // eDP in MOD always 8p connect for hbkproch protect calculation
}

void mtk_pnl_set_panel_SCDISP_Path_Sel_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	UBOOT_DEBUG("%s: priv->cus_info.scdisp_path_sel=%d\n", __func__,
		    priv->cus_info.scdisp_path_sel);
	W2BYTEMSK(REG_0100_SCDISP_BKA4FA_V007, priv->cus_info.scdisp_path_sel,
		  REG_0100_SCDISP_BKA4FA_V007_REG_SCDISP_PATH_SEL);
}

static uint32_t _mtk_get_efuse_val_v007(uint32_t hwVersion, uint16_t subBank)
{
	uint32_t efuse_val = 0;
	uint8_t count = 0;

	W2BYTEMSK(EFUSE_BANK, (subBank << 2), Fld(16, 0, AC_FULLW10));
	W2BYTEMSK(EFUSE_BANK, 1, Fld(1, 13, AC_MSKB1));

	while (R2BYTEMSK(EFUSE_BANK, Fld(1, 13, AC_MSKB1)) != 0) {
		mdelay(1);
		count++;
		if (count > TIME_OUT_CNT)
			break;
	}

	efuse_val =
	    (R2BYTEMSK(EFUSE_VAL_MSB, Fld(16, 0, AC_FULLW10)) << 16) | R2BYTEMSK(EFUSE_VAL_LSB,
										 Fld(16, 0,
										     AC_FULLW10));

	return efuse_val;
}

void efuse_set_lpllsetting_v007(uint32_t hwVersion)
{
	uint32_t efuse_sub0D_val = 0;

	if (hwVersion == BOOT_PNL_VERSION0203) {
		//sub bank 0D
		efuse_sub0D_val = _mtk_get_efuse_val_v007(hwVersion, MOD_ATOP_SUBBANK_0D);
		if ((efuse_sub0D_val & _BIT(LPLL_RETIME_CTRL)) == _BIT(LPLL_RETIME_CTRL)) {
			W2BYTEMSK(REG_00D8_LPLL, 1, Fld(1, 0, AC_MSKB0));
			W2BYTEMSK(REG_0110_LPLL, 1, Fld(1, 0, AC_MSKB0));
		} else {
			W2BYTEMSK(REG_00D8_LPLL, 0, Fld(1, 0, AC_MSKB0));
			W2BYTEMSK(REG_0110_LPLL, 0, Fld(1, 0, AC_MSKB0));
		}

		if ((efuse_sub0D_val & _BIT(LPLL_DELAY_TIME_CTRL)) == _BIT(LPLL_DELAY_TIME_CTRL)) {
			W2BYTEMSK(REG_00DC_LPLL, 1, Fld(1, 3, AC_MSKB0));
			W2BYTEMSK(REG_0114_LPLL, 1, Fld(1, 3, AC_MSKB0));
		} else {
			W2BYTEMSK(REG_00DC_LPLL, 0, Fld(1, 3, AC_MSKB0));
			W2BYTEMSK(REG_0114_LPLL, 0, Fld(1, 3, AC_MSKB0));
		}
	}
}

void _PATCH_INIT_XC_CLK_v007(void)
{
	u16 u16PLL_CLK = 0;

	//ckgen 00 mux clk
	// H49A[3:2],mfdec
	W2BYTEMSK(REG_1268_CKGEN00_V007, 0x0, REG_1268_CKGEN00_V007_REG_CKG_S_DISP_MFDEC);
	// H2c[3:2],infra tc sc
	W2BYTEMSK(REG_00B0_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00B0_CKGEN00_V007_REG_CKG_S_INFRA_TX_SC_CK);
	// H2e[3:2],infra rx sc scmw
	W2BYTEMSK(REG_00B8_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00B8_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCMW_CK);
	// H2f[3:2],infra rx sc scip
	W2BYTEMSK(REG_00BC_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00BC_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCIP_CK);
	// H30[3:2],infra rx sc scnr
	W2BYTEMSK(REG_00C0_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00C0_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCNR_CK);
	// H31[3:2],infra rx sc scace
	W2BYTEMSK(REG_00C4_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00C4_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCACE_CK);
	// H34[3:2],infra rx sc sctcon
	W2BYTEMSK(REG_00D0_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00D0_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCTCON_CK);
	// H35[3:2],infra rx sc scsr
	W2BYTEMSK(REG_00D4_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00D4_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCSR_CK);
	// H36[3:2],infra rx sc frc
	W2BYTEMSK(REG_00D8_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00D8_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_FRC_CK);

	//ckgen 01 mux clk
	// H3c0[2],vd
	W2BYTEMSK(REG_0F00_CKGEN01_V007, 0x0, REG_0F00_CKGEN01_V007_REG_CKG_S_VD);
	// H2b4[3:2],fn
	W2BYTEMSK(REG_0AD0_CKGEN01_V007, XC_CLK_007_XC_FN, REG_0AD0_CKGEN01_V007_REG_CKG_S_XC_FN);
	// H2ba[2],slow
	W2BYTEMSK(REG_0AE8_CKGEN01_V007, 0x1, REG_0AE8_CKGEN01_V007_REG_CKG_S_XC_SLOW);
	// H7A[3:2],frc fclk
	W2BYTEMSK(REG_01E8_CKGEN01_V007, 0x0, REG_01E8_CKGEN01_V007_REG_CKG_S_FRC_FCLK);
	// H7C[3:2],frc fclk 2x
	W2BYTEMSK(REG_01F0_CKGEN01_V007, 0x1, REG_01F0_CKGEN01_V007_REG_CKG_S_FRC_FCLK_2X);
	// H7E[3:2],frc fclk 2xplus
	W2BYTEMSK(REG_01F8_CKGEN01_V007, 0x1, REG_01F8_CKGEN01_V007_REG_CKG_S_FRC_FCLK_2XPLUS);

	// H3A1[0],fn clk gate
	W2BYTEMSK(REG_0E84_CKGEN01_V007, 0x0, REG_0E84_CKGEN01_V007_REG_GATE_XC_FN);

	//FRC00 mux clk
	// Hd[3:2],frc fclk 2x frccore1
	W2BYTEMSK(REG_0034_CLKGEN_FRC00, 0x0, REG_0034_CLKGEN_FRC00_REG_CKG_S_FRC_FCLK_2X_FRCCORE1);
	// Hd[11:10],frc fclk 2x frccore3
	W2BYTEMSK(REG_0034_CLKGEN_FRC00, 0x0, REG_0034_CLKGEN_FRC00_REG_CKG_S_FRC_FCLK_2X_FRCCORE3);

	//sc00 mux clk
	// H15[11:10],adc scip
	W2BYTEMSK(REG_0054_CLKGEN_SC00, 0x1, REG_0054_CLKGEN_SC00_REG_CKG_S_XC_ADC_SCIP);
	// H18[10],hdmi0 scip
	W2BYTEMSK(REG_0060_CLKGEN_SC00, 0x1, REG_0060_CLKGEN_SC00_REG_CKG_S_XC_HDMI0_SCIP);
	// H19[2],hdmi1 scip
	W2BYTEMSK(REG_0064_CLKGEN_SC00, 0x1, REG_0064_CLKGEN_SC00_REG_CKG_S_XC_HDMI1_SCIP);
	// H19[10],hdmi2 scip
	W2BYTEMSK(REG_0064_CLKGEN_SC00, 0x1, REG_0064_CLKGEN_SC00_REG_CKG_S_XC_HDMI2_SCIP);
	// H1a[2],hdmi3 scip
	W2BYTEMSK(REG_0068_CLKGEN_SC00, 0x1, REG_0068_CLKGEN_SC00_REG_CKG_S_XC_HDMI3_SCIP);
	// H23[2],dp0 scip
	W2BYTEMSK(REG_008C_CLKGEN_SC00, 0x1, REG_008C_CLKGEN_SC00_REG_CKG_S_XC_DP0_SCIP);
	// H23[10],dp1 scip
	W2BYTEMSK(REG_008C_CLKGEN_SC00, 0x1, REG_008C_CLKGEN_SC00_REG_CKG_S_XC_DP1_SCIP);
	// H24[2],dsc scip
	W2BYTEMSK(REG_0090_CLKGEN_SC00, 0x1, REG_0090_CLKGEN_SC00_REG_CKG_S_XC_DSC_SCIP);

	//sc02 mux clk
	// H66[2],ip aul clk merge
	W2BYTEMSK(REG_0198_CLKGEN_SC02, 0x0, REG_0198_CLKGEN_SC02_REG_CKG_S_XC_IP_AUL_CLK_MERGE_TMP);

	//sc02 odclk
	// H31[0],odclk
	W2BYTEMSK(REG_00C4_CLKGEN_SC02, 0x0, REG_00C4_CLKGEN_SC02_REG_V1_V2_O_ODCLK_FROM_MOD);
	// H31[1],odclk
	W2BYTEMSK(REG_00C4_CLKGEN_SC02, 0x0, REG_00C4_CLKGEN_SC02_REG_O_ODCLK_FROM_MOD);

	//FRC00 sw_en
	// H2c[0],frc fclk 2x2frccore1
	W2BYTEMSK(REG_00B0_CLKGEN_FRC00, 0x1, REG_00B0_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK_2X2FRCCORE1);
	// H2c[2],frc fclk 2x2frccore3
	W2BYTEMSK(REG_00B0_CLKGEN_FRC00, 0x1, REG_00B0_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK_2X2FRCCORE3);
	// H2d[0],frc fclk 2xplus2frccore1
	W2BYTEMSK(REG_00B4_CLKGEN_FRC00, 0x1, REG_00B4_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK_2XPLUS2FRCCORE1);
	// H2e[1],frc fclk 2x2frccore2
	W2BYTEMSK(REG_00B8_CLKGEN_FRC00, 0x1, REG_00B8_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK2FRCCORE2);
	// H32[0],xtal 12m2frcmisc
	W2BYTEMSK(REG_00C8_CLKGEN_FRC00, 0x1, REG_00C8_CLKGEN_FRC00_REG_SW_EN_XTAL_12M2FRCMISC);
	// H33[0],xtal 24m2frccore1
	W2BYTEMSK(REG_00CC_CLKGEN_FRC00, 0x1, REG_00CC_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRCCORE1);
	// H33[2],xtal 24m2frccore2
	W2BYTEMSK(REG_00CC_CLKGEN_FRC00, 0x1, REG_00CC_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRCCORE2);
	// H33[4],xtal 24m2frccore3
	W2BYTEMSK(REG_00CC_CLKGEN_FRC00, 0x1, REG_00CC_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRCCORE3);
	// H3d[8],xtal 24m2frc mbist
	W2BYTEMSK(REG_00F4_CLKGEN_FRC00, 0x1, REG_00F4_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRC_MBIST);

	//SC00 sw_en
	// H2[0],smi2scsr
	W2BYTEMSK(REG_0008_CLKGEN_SC00, 0x1, REG_0008_CLKGEN_SC00_REG_SW_EN_SMI2SCSR);
	// H6[0],smi2sctcon
	W2BYTEMSK(REG_0018_CLKGEN_SC00, 0x1, REG_0018_CLKGEN_SC00_REG_SW_EN_SMI2SCTCON);
	// H50[0],dbg2miu m2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DBG2MIU_M2SCIP);
	// H50[5],adc2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_ADC2SCIP);
	// H50[8],dbg2miu s2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DBG2MIU_S2SCIP);
	// H50[9],gpu mfdec2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_GPU_MFDEC2SCIP);
	// H50[10],fn2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_FN2SCIP);
	// H50[13],hdmi02scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI02SCIP);
	// H50[14],hdmi12scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI12SCIP);
	// H50[15],hdmi22scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI22SCIP);
	// H51[0],hdmi32scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_HDMI32SCIP);
	// H51[1],id02scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_ID02SCIP);
	// H51[2],id12scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_ID12SCIP);
	// H51[4],fn2xc_mfdec_cg_scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_MFDEC_CG_SCIP);
	// H51[6],sc2fpll2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_SC2FPLL2SCIP);
	// H51[7],slow2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_SLOW2SCIP);
	// H51[8],tgen win2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_TGEN_WIN2SCIP);
	// H51[9],vd2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_VD2SCIP);
	// H51[10],xtal 12m2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_12M2SCIP);
	// H51[11],xtal 24m2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCIP);
	// H51[12],xtal ip12scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_IP12SCIP);
	// H51[13],sidclk hd02scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD02SCIP);
	// H51[14],sidclk hd12scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD12SCIP);
	// H51[15],sidclk hd22scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD22SCIP);
	// H52[0],sidclk hd32scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD32SCIP);
	// H52[4],xtal 24m2scip mbist
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCIP_MBIST);
	// H52[9],sidclk dp02scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DP02SCIP);
	// H52[10],sidclk dp12scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DP12SCIP);
	// H52[11],sidclk dsc2scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DSC2SCIP);
	// H52[12],xc dp02scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DP02SCIP);
	// H52[13],xc dp12scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DP12SCIP);
	// H52[14],xc dsc2scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DSC2SCIP);
	// H53[0],fn2xc dc0 cg scip
	W2BYTEMSK(REG_014C_CLKGEN_SC00, 0x1, REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_DC0_CG_SCIP);
	// H53[1],fn2xc sub dc0 cg scip
	W2BYTEMSK(REG_014C_CLKGEN_SC00, 0x1, REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_SUB_DC0_CG_SCIP);
	// H53[2],fn2xc sub1 dc0 cg scip
	W2BYTEMSK(REG_014C_CLKGEN_SC00, 0x1, REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_SUB1_DC0_CG_SCIP);
	// H70[5], xtal 24m2scnr
	W2BYTEMSK(REG_01C0_CLKGEN_SC00, 0x1, REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCNR);
	// H70[7], xtal 24m2scnr
	W2BYTEMSK(REG_01C0_CLKGEN_SC00, 0x1, REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCNR_MBIST);
	// H70[8], xc fn2scnr
	W2BYTEMSK(REG_01C0_CLKGEN_SC00, 0x1, REG_01C0_CLKGEN_SC00_REG_SW_EN_XC_FN2SCNR);

	//SC01 sw_en
	// H38[0], xc gop2sctcon
	W2BYTEMSK(REG_00E0_CLKGEN_SC01, 0x1, REG_00E0_CLKGEN_SC01_REG_SW_EN_XC_GOP2SCTCON);
	// H39[0], xc od 1p2sctcon
	W2BYTEMSK(REG_00E4_CLKGEN_SC01, 0x1, REG_00E4_CLKGEN_SC01_REG_SW_EN_XC_OD_1P2SCTCON);
	// H3a[0], xc od b2p2sctcon
	W2BYTEMSK(REG_00E8_CLKGEN_SC01, 0x1, REG_00E8_CLKGEN_SC01_REG_SW_EN_XC_OD_B2P2SCTCON);
	// H43[0], xc od osd2sctcon
	W2BYTEMSK(REG_010C_CLKGEN_SC01, 0x1, REG_010C_CLKGEN_SC01_REG_SW_EN_XC_OD_OSD2SCTCON);
	// H74[9], xc fn2scsr
	W2BYTEMSK(REG_01D0_CLKGEN_SC01, 0x1, REG_01D0_CLKGEN_SC01_REG_SW_EN_XC_FN2SCSR);
	// H74[9], xc fn2sctcon
	W2BYTEMSK(REG_01D0_CLKGEN_SC01, 0x1, REG_01D0_CLKGEN_SC01_REG_SW_EN_XC_FN2SCTCON);

	//SC02 sw_en
	// H1[1], xc od2sctcon
	W2BYTEMSK(REG_0004_CLKGEN_SC02, 0x1, REG_0004_CLKGEN_SC02_REG_SW_EN_XC_OD2SCTCON);
	// Hb[7], xtal 24m2scsr
	W2BYTEMSK(REG_002C_CLKGEN_SC02, 0x1, REG_002C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCSR);
	// Hb[8], xtal 24m2sctcon
	W2BYTEMSK(REG_002C_CLKGEN_SC02, 0x1, REG_002C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCTCON);
	// H1a[0], xc od meta2sctcon
	W2BYTEMSK(REG_0068_CLKGEN_SC02, 0x1, REG_0068_CLKGEN_SC02_REG_SW_EN_XC_OD_META2SCTCON);
	// H1c[0], xc os osd meta2sctcon
	W2BYTEMSK(REG_0070_CLKGEN_SC02, 0x1, REG_0070_CLKGEN_SC02_REG_SW_EN_XC_OD_OSD_META2SCTCON);
	// H1f[3], mcu nonpm2scsr
	W2BYTEMSK(REG_007C_CLKGEN_SC02, 0x1, REG_007C_CLKGEN_SC02_REG_SW_EN_MCU_NONPM2SCSR);
	// H1f[4], mcu nonpm2sctcon
	W2BYTEMSK(REG_007C_CLKGEN_SC02, 0x1, REG_007C_CLKGEN_SC02_REG_SW_EN_MCU_NONPM2SCTCON);
	// H23[2], xtal 24m2scsr mbist
	W2BYTEMSK(REG_008C_CLKGEN_SC02, 0x1, REG_008C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCSR_MBIST);
	// H23[3], xtal 24m2sctcon mbist
	W2BYTEMSK(REG_008C_CLKGEN_SC02, 0x1, REG_008C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCTCON_MBIST);
	// H4a[0], xtal 24m2scace
	W2BYTEMSK(REG_0128_CLKGEN_SC02, 0x1, REG_0128_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCACE);
	// H4a[1], xtal 24m2scace mbist
	W2BYTEMSK(REG_0128_CLKGEN_SC02, 0x1, REG_0128_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCACE_MBIST);
	// H4d[0], smi2scace
	W2BYTEMSK(REG_0134_CLKGEN_SC02, 0x1, REG_0134_CLKGEN_SC02_REG_SW_EN_SMI2SCACE);
	// H4d[1], smi2scace gals
	W2BYTEMSK(REG_0134_CLKGEN_SC02, 0x1, REG_0134_CLKGEN_SC02_REG_SW_EN_SMI2SCACE_GALS);
	// H4f[0], xc fn2scace
	W2BYTEMSK(REG_013C_CLKGEN_SC02, 0x1, REG_013C_CLKGEN_SC02_REG_SW_EN_XC_FN2SCACE);
	// H50[0], frc fclk 2xplua2scace
	W2BYTEMSK(REG_0140_CLKGEN_SC02, 0x1, REG_0140_CLKGEN_SC02_REG_SW_EN_FRC_FCLK_2XPLUS2SCACE);
	// H52[0], xtal 24m2scmw
	W2BYTEMSK(REG_0148_CLKGEN_SC02, 0x1, REG_0148_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCMW);
	// H52[1], xtal 24m2scmw mbist
	W2BYTEMSK(REG_0148_CLKGEN_SC02, 0x1, REG_0148_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCMW_MBIST);
	// H55[0], smi2scmw
	W2BYTEMSK(REG_0154_CLKGEN_SC02, 0x1, REG_0154_CLKGEN_SC02_REG_SW_EN_SMI2SCMW);
	// H55[1], smi2scmw gals
	W2BYTEMSK(REG_0154_CLKGEN_SC02, 0x1, REG_0154_CLKGEN_SC02_REG_SW_EN_SMI2SCMW_GALS);
	// H57[0], xc fn2scmw
	W2BYTEMSK(REG_015C_CLKGEN_SC02, 0x1, REG_015C_CLKGEN_SC02_REG_SW_EN_XC_FN2SCMW);
	// H58[0], drc fclk 2xplua2scmw
	W2BYTEMSK(REG_0160_CLKGEN_SC02, 0x1, REG_0160_CLKGEN_SC02_REG_SW_EN_FRC_FCLK_2XPLUS2SCMW);
	// H5a[0], od b2p2scmw
	W2BYTEMSK(REG_0168_CLKGEN_SC02, 0x1, REG_0168_CLKGEN_SC02_REG_SW_EN_XC_OD_B2P2SCMW);
	// H5b[0], od 1p2scmw
	W2BYTEMSK(REG_016C_CLKGEN_SC02, 0x1, REG_016C_CLKGEN_SC02_REG_SW_EN_XC_OD_1P2SCMW);
	// H5c[0], dip02scmw
	W2BYTEMSK(REG_0170_CLKGEN_SC02, 0x1, REG_0170_CLKGEN_SC02_REG_SW_EN_XC_DIP02SCMW);
	// H5d[0], dip12scmw
	W2BYTEMSK(REG_0174_CLKGEN_SC02, 0x1, REG_0174_CLKGEN_SC02_REG_SW_EN_XC_DIP12SCMW);
	// H61[0], xtal 12m2scmw
	W2BYTEMSK(REG_0184_CLKGEN_SC02, 0x1, REG_0184_CLKGEN_SC02_REG_SW_EN_XTAL_12M2SCMW);
	// H64[0], dip22scmw
	W2BYTEMSK(REG_0190_CLKGEN_SC02, 0x1, REG_0190_CLKGEN_SC02_REG_SW_EN_XC_DIP22SCMW);
	// H67[0], ip aul clk merge2scace
	W2BYTEMSK(REG_019C_CLKGEN_SC02, 0x1, REG_019C_CLKGEN_SC02_REG_SW_EN_XC_IP_AUL_CLK_MERGE2SCACE_TMP);

	//XCPLL
	u16PLL_CLK = R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2_DIG)
			| (R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10_DIG) << XCPLL_4)
			| (R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12_DIG) << XCPLL_8)
			| (R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128_DIG) << XCPLL_12);

	if (u16PLL_CLK != XCPLL_REG_0007_SET) {
		//XCPLL Setting
		//BK100D_4a[7:0] = 0x00
		W2BYTEMSK(REG_0094_XCPLL_V007, 0x0, REG_0094_XCPLL_V007_REG_XCPLL_V007_SPAN_1);
		//BK100D_48[15:0] = 0x00
		W2BYTEMSK(REG_0090_XCPLL_V007, 0x0, REG_0090_XCPLL_V007_REG_XCPLL_V007_SPAN_0);
		//BK100D_46[7:0] = 0x00
		W2BYTEMSK(REG_008C_XCPLL_V007, 0x0, REG_008C_XCPLL_V007_REG_XCPLL_V007_STEP_1);
		//BK100D_44[15:0] = 0x0
		W2BYTEMSK(REG_0088_XCPLL_V007, 0x0, REG_0088_XCPLL_V007_REG_XCPLL_V007_STEP_0);
		//BK100D_42[7:0] = 0x70
		W2BYTEMSK(REG_0084_XCPLL_V007, XCPLL_REG_0007_SET_1, REG_0084_XCPLL_V007_REG_XCPLL_V007_SET_1);
		//BK100D_40[15:0] = 0xd957
		W2BYTEMSK(REG_0080_XCPLL_V007, XCPLL_REG_0007_SET_0, REG_0080_XCPLL_V007_REG_XCPLL_V007_SET_0);
		//BK100D_4e[0] = 1
		W2BYTEMSK(REG_009C_XCPLL_V007, 0x1, REG_009C_XCPLL_V007_REG_XCPLL_V007_SSC_SYNC);
		//BK100D_4e[4] = 0
		W2BYTEMSK(REG_009C_XCPLL_V007, 0x0, REG_009C_XCPLL_V007_REG_XCPLL_V007_SSC_MODE);
		//BK100D_5c[0] = 1
		W2BYTEMSK(REG_00B8_XCPLL_V007, 0x1, REG_00B8_XCPLL_V007_REG_XCPLL_V007_SLD);
		//BK100D_0e[2:0] = 0x3
		W2BYTEMSK(REG_001C_XCPLL_V007, XCPLL_REG_0007_ICTRL, REG_001C_XCPLL_V007_REG_XCPLL_V007_ICTRL);
		//BK100D_0e[8] = 0x0
		W2BYTEMSK(REG_001C_XCPLL_V007, 0x0, REG_001C_XCPLL_V007_REG_XCPLL_V007_ICTRL_SW);
		//BK100D_12[1:0] = 0x3
		W2BYTEMSK(REG_0024_XCPLL_V007,
				XCPLL_REG_0007_LOOP_DIV_FIRST,
				REG_0024_XCPLL_V007_REG_XCPLL_V007_LOOP_DIV_FIRST);
		//BK100D_14[7:0] = 0x6
		W2BYTEMSK(REG_0028_XCPLL_V007,
				XCPLL_REG_0007_LOOP_DIV_SECOND,
				REG_0028_XCPLL_V007_REG_XCPLL_V007_LOOP_DIV_SECOND);
		//BK100D_08[0] = 0x1
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x1, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2);
		//BK100D_08[4] = 0x0
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x0, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10);
		//BK100D_08[8] = 0x0
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x0, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12);
		//BK100D_08[12] = 0x0
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x0, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128);
		//BK100D_00[0] = 0x0
		W2BYTEMSK(REG_0000_XCPLL_V007, 0x0, REG_0000_XCPLL_V007_REG_XCPLL_V007_PD);
		//BK100D_00[4] = 0x1
		W2BYTEMSK(REG_0000_XCPLL_V007, 0x1, REG_0000_XCPLL_V007_REG_XCPLL_V007_PD_DROOP_BYPASS);
		//BK100D_00[8] = 0x0
		W2BYTEMSK(REG_0000_XCPLL_V007, 0x0, REG_0000_XCPLL_V007_REG_XCPLL_V007_PD_VRINGCMP);

		//Delay 500us
		udelay(XCPLL_DELAY_TIME);
		//BK100D_30[0] = 1
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x1, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2_DIG);
		//BK100D_30[4] = 0
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x0, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10_DIG);
		//BK100D_30[8] = 0
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x0, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12_DIG);
		//BK100D_30[12] = 0
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x0, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128_DIG);
	}

	//XCBPLL
	u16PLL_CLK =  (R2BYTEMSK(REG_0144_XCBPLL, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV1_DIG) << XCPLL_4)
			| (R2BYTEMSK(REG_0144_XCBPLL, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV2_DIG) << XCPLL_8)
			| (R2BYTEMSK(REG_0144_XCBPLL, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV3_DIG) << XCPLL_12);

	if (u16PLL_CLK != XCBPLL_REG_0007_SET) {
		//XCBPLL
		//BK100D_84[0] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_VCO_DIV3);
		//BK100D_84[4] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_OCC_DIV128);
		//BK100D_84[8] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_XTAL);
		//BK100D_84[12] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_TEST);
		//BK100D_86[0] = 0x0
		W2BYTEMSK(REG_010C_XCBPLL, 0x0, REG_010C_XCBPLL_REG_EN_XCBPLL_PRDT);
		//BK100D_86[4] = 0x0
		W2BYTEMSK(REG_010C_XCBPLL, 0x0, REG_010C_XCBPLL_REG_EN_XCBPLL_RST);
		//BK100D_88[1:0] = 0x0
		W2BYTEMSK(REG_0110_XCBPLL, 0x0, REG_0110_XCBPLL_REG_GC_XCBPLL_INPUT_DIV);
		//BK100D_8a[1:0] = 0x0
		W2BYTEMSK(REG_0114_XCBPLL, 0x0, REG_0114_XCBPLL_REG_GC_XCBPLL_CP_SW);
		//BK100D_8a[10:8] = 0x2
		W2BYTEMSK(REG_0114_XCBPLL, XCBPLL_ICTRL, REG_0114_XCBPLL_REG_GC_XCBPLL_ICTRL);
		//BK100D_8c[1:0] = 0x0
		W2BYTEMSK(REG_0118_XCBPLL, 0x0, REG_0118_XCBPLL_REG_GC_XCBPLL_OUTPUT_DIV_FIRST);
		//BK100D_8c[10:8] = 0x0
		W2BYTEMSK(REG_0118_XCBPLL, 0x0, REG_0118_XCBPLL_REG_GC_XCBPLL_OUTPUT_DIV);
		//BK100D_8e[1:0] = 0x0
		W2BYTEMSK(REG_011C_XCBPLL, 0x0, REG_011C_XCBPLL_REG_GC_XCBPLL_LOOPDIV_FIRST);
		//BK100D_90[7:0] = 0x3c
		W2BYTEMSK(REG_0120_XCBPLL, XCBPLL_LOOPDIV_SECOND, REG_0120_XCBPLL_REG_GC_XCBPLL_LOOPDIV_SECOND);
		//BK100D_9d[15:0] = 0x10
		W2BYTEMSK(REG_0138_XCBPLL, TEST_XCBPLL, REG_0138_XCBPLL_REG_TEST_XCBPLL);
		//BK100D_82[0] = 0x1
		W2BYTEMSK(REG_0104_XCBPLL, 0x1, REG_0104_XCBPLL_REG_PD_XCBPLL_CLK_DIV5);
		//BK100D_82[4] = 0x0
		W2BYTEMSK(REG_0104_XCBPLL, 0x0, REG_0104_XCBPLL_REG_PD_XCBPLL_POSTDIV);
		//BK100D_80[0] = 0x0
		W2BYTEMSK(REG_0100_XCBPLL, 0x0, REG_0100_XCBPLL_REG_PD_XCBPLL);
		//BK100D_80[4] = 0x0
		W2BYTEMSK(REG_0100_XCBPLL, 0x0, REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV1);
		//BK100D_80[8] = 0x1
		W2BYTEMSK(REG_0100_XCBPLL, 0x1, REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV2);
		//BK100D_80[12] = 0x1
		W2BYTEMSK(REG_0100_XCBPLL, 0x1, REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV3);

		//Delay 500us
		udelay(XCPLL_DELAY_TIME);
		//BK100D_a2[4] = 0x0
		W2BYTEMSK(REG_0144_XCBPLL, 0x0, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV1_DIG);
		//BK100D_a2[8] = 0x1
		W2BYTEMSK(REG_0144_XCBPLL, 0x1, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV2_DIG);
		//BK100D_a2[12] = 0x1
		W2BYTEMSK(REG_0144_XCBPLL, 0x1, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV3_DIG);
	}
}

static void _PATCH_TRIGGER_GEN_v007(struct mtk_panel_priv *priv)
{
	#define TG_GEN_SW_HCOUNT (20)
	u32 u32VTT = 0;
	u32 u32HTT = 0;
	u16 u16VFreq = 0;
	u64 u64OneLineOutputUsx10000 = 0;
	u64 u64OneLineTrigUsx10000 = 0;
	u32 u32Value = 0;

	if (!priv)
		return;

	u32VTT = priv->typ_vtt;
	u32HTT = priv->typ_htt;

	if (u32HTT == 0)
		u32HTT = 1;
	if (u32VTT == 0)
		u32VTT = 1;

	u16VFreq = priv->typ_dclk / u32HTT / u32VTT;

	u64OneLineOutputUsx10000 = (u64)1000000 * 10000 / u16VFreq / u32VTT;
	u64OneLineTrigUsx10000 = 10000 * TG_GEN_SW_HCOUNT / 24;

	//patch for Trigger Gen
	W2BYTEMSK(REG_0018_TRIGGER_GEN_BKA3A4, 0x55,
		  REG_0018_TRIGGER_GEN_BKA3A4_REG_SRC0_DMA_RD_TRIG_DLY_V);

	W2BYTEMSK((0x1474C00 + 0x0A8), 0x5, Fld(13, 0, AC_MSKW10));	//reg_tgen_dummy0_trig_dly_v=5
	W2BYTEMSK((0x1474C00 + 0x0AC), 0x5, Fld(13, 0, AC_MSKW10));	//reg_tgen_dummy1_trig_dly_v=5
	W2BYTEMSK(REG_0004_TRIGGER_GEN_BKA3A4, 0,
		  REG_0004_TRIGGER_GEN_BKA3A4_REG_SRC0_INPUT_SRC_SEL);

	W2BYTEMSK(REG_0084_TRIGGER_GEN_BKA3A4, 0x1,
		  REG_0084_TRIGGER_GEN_BKA3A4_REG_SRC1_INPUT_SRC_SEL);

	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A4, 0x0,
		  REG_0104_TRIGGER_GEN_BKA3A4_REG_B2R_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0004_TRIGGER_GEN_BKA3A5, 0x4,
		  REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0084_TRIGGER_GEN_BKA3A5, 0x4,
		  REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A5, 0x4,
		  REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0184_TRIGGER_GEN_BKA3A5, 0x4,
		  REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_INPUT_SRC_SEL);
	W2BYTEMSK((0x1474C00 + 0x04), 0x4, Fld(3, 0, AC_MSKB0));	//reg_frc2_input_src_sel=4
	W2BYTEMSK((0x1474C00 + 0x084), 0x2, Fld(3, 0, AC_MSKB0));	//reg_tgen_input_src_sel=0
	W2BYTEMSK((0x10A0800 + 0x004), 0x4, Fld(3, 0, AC_MSKB0));	//reg_frc14=4
	W2BYTEMSK((0x10A0400 + 0x184), 0x4, Fld(3, 0, AC_MSKB0));	//reg_frc15=4
	W2BYTEMSK((0x10A0600 + 0x084), 0x4, Fld(3, 0, AC_MSKB0));	//frc_stage_src_sel=4

	W2BYTEMSK(REG_0018_TRIGGER_GEN_BKA3A4, 0x9,
		  REG_0018_TRIGGER_GEN_BKA3A4_REG_SRC0_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0098_TRIGGER_GEN_BKA3A4, 0x9,
		  REG_0098_TRIGGER_GEN_BKA3A4_REG_SRC1_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0118_TRIGGER_GEN_BKA3A4, 0x9,
		  REG_0118_TRIGGER_GEN_BKA3A4_REG_B2R_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0198_TRIGGER_GEN_BKA3A4, 0x4,
		  REG_0198_TRIGGER_GEN_BKA3A4_REG_IP_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0018_TRIGGER_GEN_BKA3A5, 0x9,
		  REG_0018_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0098_TRIGGER_GEN_BKA3A5, 0x9,
		  REG_0098_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0198_TRIGGER_GEN_BKA3A5, 0x9,
		  REG_0198_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_DLY_V);
	// patch for gop trigger gen setting
	u32Value = 0;
	W2BYTEMSK(REG_0108_TRIGGER_GEN_BKA3A5, u32Value, REG_0108_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UP_TRIG_DLY_V);
	u32Value = (u32)(1 * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_010C_TRIGGER_GEN_BKA3A5, u32Value, REG_010C_TRIGGER_GEN_BKA3A5_REG_DISP_DS_TRIG_DLY_V);
	W2BYTEMSK(REG_0110_TRIGGER_GEN_BKA3A5, u32Value, REG_0110_TRIGGER_GEN_BKA3A5_REG_DISP_ML_TRIG_DLY_V);
	u32Value = (u32)(0x0D * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_0114_TRIGGER_GEN_BKA3A5, u32Value, REG_0114_TRIGGER_GEN_BKA3A5_REG_DISP_VS_TRIG_DLY_V);
	u32Value = (u32)(0x13 * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_0118_TRIGGER_GEN_BKA3A5, u32Value, REG_0118_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0170_TRIGGER_GEN_BKA3A5, (TG_GEN_SW_HCOUNT - 1), REG_0170_TRIGGER_GEN_BKA3A5_REG_DISP_SW_HTT_SIZE);
	W2BYTEMSK(REG_0174_TRIGGER_GEN_BKA3A5, 1, REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SW_H_USR_MD);
	W2BYTEMSK(REG_0174_TRIGGER_GEN_BKA3A5, 0, REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_VS_SW_TRIG);
	W2BYTEMSK(REG_0174_TRIGGER_GEN_BKA3A5, 0, REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SW_V_USR_MD);
	W2BYTEMSK(REG_0164_TRIGGER_GEN_BKA3A5, 1, REG_0164_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_OF_KEEP_EN);
	W2BYTEMSK(REG_0164_TRIGGER_GEN_BKA3A5, 8, REG_0164_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_UPD_MASK_RANGE);

	W2BYTEMSK((0x1474C00 + 0x018), 0x9, Fld(13, 0, AC_MSKW10));	//reg_frc2_dma_rd_trig_dly_v=9
	W2BYTEMSK((0x1474C00 + 0x098), 0x9, Fld(13, 0, AC_MSKW10));	//reg_tgen_dma_rd_trig_dly_v=9

	W2BYTEMSK(REG_0038_TRIGGER_GEN_BKA3A4, 0x1,
		  REG_0038_TRIGGER_GEN_BKA3A4_REG_SRC0_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_00B8_TRIGGER_GEN_BKA3A4, 0x1,
		  REG_00B8_TRIGGER_GEN_BKA3A4_REG_SRC1_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_0138_TRIGGER_GEN_BKA3A4, 0x1,
		  REG_0138_TRIGGER_GEN_BKA3A4_REG_B2R_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_01B8_TRIGGER_GEN_BKA3A4, 2,
		  REG_01B8_TRIGGER_GEN_BKA3A4_REG_IP_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_0038_TRIGGER_GEN_BKA3A5, 12,
		  REG_0038_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_00B8_TRIGGER_GEN_BKA3A5, 19,
		  REG_00B8_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_0138_TRIGGER_GEN_BKA3A5, 14,
		  REG_0138_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_01B8_TRIGGER_GEN_BKA3A5, 1,
		  REG_01B8_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UPD_TRIG_DLY_H);

	W2BYTEMSK((0x1474C00 + 0x038), 0x1, Fld(3, 0, AC_MSKB0));	//reg_frc2_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK((0x1474C00 + 0x0B8), 0x1, Fld(3, 0, AC_MSKB0));	//reg_tgen_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK((0x1474C00 + 0x138), 0x1, Fld(3, 0, AC_MSKB0));	//reg_b2r_lite0_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK((0x1474C00 + 0x1B8), 0x1, Fld(3, 0, AC_MSKB0));	//reg_b2r_lite1_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK(REG_0058_TRIGGER_GEN_BKA3A5, 1,
		  REG_0058_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_REP_INTERVAL);
	// patch for ldm usage
	u32Value = (u32)(0x12 * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_0124_TRIGGER_GEN_BKA3A5, u32Value, REG_0124_TRIGGER_GEN_BKA3A5_REG_DISP_PQ_IRQ_TRIG_DLY_V);
}

uint32_t _align_floor_v007(uint32_t input, uint8_t alignNum)
{
	if (alignNum > 0)
		input = (input / alignNum) * alignNum;
	return input;
}

uint32_t _tgen_target_vde_v007(uint32_t u32DtsVde)
{
	uint32_t u32TargetVTT = TGEN_VDE_ST_2160;

	if (u32DtsVde == TGEN_VDE_4320)
		u32TargetVTT = TGEN_VDE_ST_4320;
	else if (u32DtsVde == TGEN_VDE_2160)
		u32TargetVTT = TGEN_VDE_ST_2160;
	else if (u32DtsVde <= TGEN_VDE_1080)
		u32TargetVTT = u32DtsVde * 100 * TGEN_VDE_ST_1080 / 1080 / 100;
	else
		u32TargetVTT = TGEN_VDE_ST_2160;

	return u32TargetVTT;
}

static uint32_t _tgen_target_VTTVBuf_v007(uint32_t u32DtsVde)
{
	uint32_t u32TargetVTTBuf = TGEN_VDE_ST_2160;

	if (u32DtsVde == TGEN_VDE_4320)
		u32TargetVTTBuf = TGEN_VTTV_BUF_4320;
	else if (u32DtsVde == TGEN_VDE_2160)
		u32TargetVTTBuf = TGEN_VTTV_BUF_2160;
	else if (u32DtsVde <= TGEN_VDE_1080)
		u32TargetVTTBuf = TGEN_VTTV_BUF_1080;
	else
		u32TargetVTTBuf = TGEN_VTTV_BUF_2160;

	return u32TargetVTTBuf;
}

int _tgen_qms_related_setting_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 qms_table_idx = 0;
	u8 idx = 0;
	u16 vfrq = 0;
	u16 lock_vsync_msk_num = 1;
	u16 tgen_input_vtt[QMS_TFR_MAX];
	u32 qms_output_vfreq = 0;

	if (!priv) {
		printf("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}

	//QMS setting: TFR from delay sync
	W2BYTEMSK(REG_0080_TGEN_VRR_BKA39F, 0x1, REG_0080_TGEN_VRR_BKA39F_REG_TGEN_NEXT_TFR_SEL);

	vfrq = priv->typ_dclk / priv->typ_htt / priv->typ_vtt;
	if (!IS_VFREQ_60HZ_GROUP(vfrq))
		qms_table_idx = 1;

	for (idx = 0; idx < QMS_TFR_MAX; idx++) {
		qms_output_vfreq = qms_info[qms_table_idx][idx].output_vfrq;
		if (qms_output_vfreq == 0)
			tgen_input_vtt[idx] = 0;
		else
			tgen_input_vtt[idx] = priv->typ_vtt * vfrq * DEC_100 / qms_info[qms_table_idx][idx].input_vfrq;
	}

	idx = 1;
	W2BYTEMSK(REG_0140_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_0140_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_1);
	W2BYTEMSK(REG_0140_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0140_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_1);
	W2BYTEMSK(REG_00F0_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_00F0_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_1);
	idx++;

	W2BYTEMSK(REG_0140_TGEN_FRAMELOCK_BKA3A2, SHIFT_LEFT_8((MAX(lock_vsync_msk_num, 1) - 1)),
		  REG_0140_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_2);
	W2BYTEMSK(REG_0140_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0140_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_2);
	W2BYTEMSK(REG_00F4_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_00F4_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_2);
	idx++;

	W2BYTEMSK(REG_0144_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_0144_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_3);
	W2BYTEMSK(REG_0144_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0144_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_3);
	W2BYTEMSK(REG_00F8_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_00F8_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_3);
	idx++;

	W2BYTEMSK(REG_0144_TGEN_FRAMELOCK_BKA3A2, SHIFT_LEFT_8((MAX(lock_vsync_msk_num, 1) - 1)),
		  REG_0144_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_4);
	W2BYTEMSK(REG_0144_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0144_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_4);
	W2BYTEMSK(REG_00FC_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_00FC_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_4);
	idx++;

	W2BYTEMSK(REG_0148_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_0148_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_5);
	W2BYTEMSK(REG_0148_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0148_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_5);
	W2BYTEMSK(REG_0100_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0100_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_5);
	idx++;

	W2BYTEMSK(REG_0148_TGEN_FRAMELOCK_BKA3A2, SHIFT_LEFT_8((MAX(lock_vsync_msk_num, 1) - 1)),
		  REG_0148_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_6);
	W2BYTEMSK(REG_0148_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0148_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_6);
	W2BYTEMSK(REG_0104_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0104_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_6);
	idx++;

	W2BYTEMSK(REG_014C_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_014C_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_7);
	W2BYTEMSK(REG_014C_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_014C_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_7);
	W2BYTEMSK(REG_0108_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0108_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_7);
	idx++;

	W2BYTEMSK(REG_014C_TGEN_FRAMELOCK_BKA3A2, SHIFT_LEFT_8((MAX(lock_vsync_msk_num, 1) - 1)),
		  REG_014C_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_8);
	W2BYTEMSK(REG_014C_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_014C_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_8);
	W2BYTEMSK(REG_010C_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_010C_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_8);
	idx++;

	W2BYTEMSK(REG_0150_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_0150_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_9);
	W2BYTEMSK(REG_0150_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0150_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_9);
	W2BYTEMSK(REG_0110_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0110_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_9);
	idx++;

	W2BYTEMSK(REG_0150_TGEN_FRAMELOCK_BKA3A2, SHIFT_LEFT_8((MAX(lock_vsync_msk_num, 1) - 1)),
		  REG_0150_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_10);
	W2BYTEMSK(REG_0150_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0150_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_10);
	W2BYTEMSK(REG_0114_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0114_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_10);
	idx++;

	W2BYTEMSK(REG_0154_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_0154_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_11);
	W2BYTEMSK(REG_0154_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0154_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_11);
	W2BYTEMSK(REG_0118_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0118_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_11);
	idx++;

	W2BYTEMSK(REG_0154_TGEN_FRAMELOCK_BKA3A2, SHIFT_LEFT_8((MAX(lock_vsync_msk_num, 1) - 1)),
		  REG_0154_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_12);
	W2BYTEMSK(REG_0154_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0154_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_12);
	W2BYTEMSK(REG_011C_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_011C_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_12);
	idx++;

	W2BYTEMSK(REG_0158_TGEN_FRAMELOCK_BKA3A2, (MAX(lock_vsync_msk_num, 1) - 1),
		  REG_0158_TGEN_FRAMELOCK_BKA3A2_REG_QMS_IP_LOCK_VSYNC_MASK_NUM_13);
	W2BYTEMSK(REG_0158_TGEN_FRAMELOCK_BKA3A2, (MAX(qms_info[qms_table_idx][idx].ratio, 1) - 1),
		  REG_0158_TGEN_FRAMELOCK_BKA3A2_REG_QMS_LOCK_FREERUN_SWITCH_NUM_13);
	W2BYTEMSK(REG_0120_TGEN_FRAMELOCK_BKA3A2, (MAX(tgen_input_vtt[idx], 0)),
		  REG_0120_TGEN_FRAMELOCK_BKA3A2_REG_QMS_HW_SRC_LOCK_VTT_CHECK_13);

	return 0;
}

int mtk_tgen_init_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	uint8_t alignNum = 0;
	uint32_t u32TargetVdeStart = 0;
	uint32_t u32TargetVTTVBuf = 0;
	uint32_t u32DtsVbp = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}
	//HAPS test, need to enable this bit first.
	//Let tool can switch ch5 to read scaler bank.
	W2BYTEMSK(0x60041C, 0x4, Fld(4, 0, AC_MSKB0));

	// for video mute, enable render blending
	W2BYTEMSK(REG_0004_BLEND_TOP_BKA36B, 1, REG_0004_BLEND_TOP_BKA36B_REG_LAYER0_OFF);
	W2BYTEMSK(REG_000C_OSDB_COLOV_BKA3ED, 1, REG_000C_OSDB_COLOV_BKA3ED_REG_COLOV_SET_BLACK_DBF_EN);
	W2BYTEMSK(REG_0010_OSDB_COLOV_BKA3ED, 1, REG_0010_OSDB_COLOV_BKA3ED_REG_COLOV_SET_BLACK_MAIN_EN);


	//Patch for enable xc mcu clk.
	_PATCH_INIT_XC_CLK_v007();

//#ifdef CONFIG_HAPS
#if 0
	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_TS_MD);
	W2BYTEMSK(REG_004C_TGEN_MAIN_BKA3A0, 0x112F, REG_004C_TGEN_MAIN_BKA3A0_REG_HTT);
	W2BYTEMSK(REG_008C_TGEN_MAIN_BKA3A0, 0x8C9, REG_008C_TGEN_MAIN_BKA3A0_REG_VTT);
	W2BYTEMSK(REG_0050_TGEN_MAIN_BKA3A0, 0, REG_0050_TGEN_MAIN_BKA3A0_REG_HSYNC_ST);
	W2BYTEMSK(REG_0054_TGEN_MAIN_BKA3A0, 0x3, REG_0054_TGEN_MAIN_BKA3A0_REG_HSYNC_END);
	W2BYTEMSK(REG_0058_TGEN_MAIN_BKA3A0, 0x30, REG_0058_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_ST);
	W2BYTEMSK(REG_005C_TGEN_MAIN_BKA3A0, 0xF2F, REG_005C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_END);
	W2BYTEMSK(REG_0060_TGEN_MAIN_BKA3A0, 0x30, REG_0060_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_ST);
	W2BYTEMSK(REG_0064_TGEN_MAIN_BKA3A0, 0xF2F, REG_0064_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_END);
	W2BYTEMSK(REG_0068_TGEN_MAIN_BKA3A0, 0x30, REG_0068_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_ST);
	W2BYTEMSK(REG_006C_TGEN_MAIN_BKA3A0, 0xF2f, REG_006C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_END);
	W2BYTEMSK(REG_0090_TGEN_MAIN_BKA3A0, 0, REG_0090_TGEN_MAIN_BKA3A0_REG_VSYNC_ST);
	W2BYTEMSK(REG_0094_TGEN_MAIN_BKA3A0, 0x0, REG_0094_TGEN_MAIN_BKA3A0_REG_VSYNC_END);
	W2BYTEMSK(REG_0098_TGEN_MAIN_BKA3A0, 0x1E, REG_0098_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_ST);
	W2BYTEMSK(REG_009C_TGEN_MAIN_BKA3A0, 0x88D, REG_009C_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_END);
	W2BYTEMSK(REG_00A0_TGEN_MAIN_BKA3A0, 0x1E, REG_00A0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_ST);
	W2BYTEMSK(REG_00A4_TGEN_MAIN_BKA3A0, 0x88D, REG_00A4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_END);
	W2BYTEMSK(REG_00A8_TGEN_MAIN_BKA3A0, 0x1E, REG_00A8_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_ST);
	W2BYTEMSK(REG_00AC_TGEN_MAIN_BKA3A0, 0x88D, REG_00AC_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_END);
	W2BYTEMSK(REG_01F4_TGEN_MAIN_BKA3A0, 0, REG_01F4_TGEN_MAIN_BKA3A0_REG_M_DELTA);
	W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, 0,
		  REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END);
	W2BYTEMSK(REG_01F8_TGEN_MAIN_BKA3A0, 0, REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND);
	W2BYTEMSK(REG_01FC_TGEN_MAIN_BKA3A0, 0xFFFF,
		  REG_01FC_TGEN_MAIN_BKA3A0_REG_PANEL_UPPER_BOUND);
	W2BYTEMSK(REG_0084_TGEN_MAIN_BKA3A0, 1, REG_0084_TGEN_MAIN_BKA3A0_REG_EVEN_VTT_VCNT_EN);
	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_ODCLK);
	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_XTALI);
	W2BYTEMSK(REG_0008_TGEN_MAIN_BKA3A0, 1, REG_0008_TGEN_MAIN_BKA3A0_REG_TGEN_VIDEO_EN);
	W2BYTEMSK(REG_00C0_TGEN_MAIN_BKA3A0, 0x30, REG_00C0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_ST);
	W2BYTEMSK(REG_00C4_TGEN_MAIN_BKA3A0, 0xF2F, REG_00C4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_END);
	W2BYTEMSK(REG_0100_TGEN_MAIN_BKA3A0, 0x30, REG_0100_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_ST);
	W2BYTEMSK(REG_0104_TGEN_MAIN_BKA3A0, 0x88D, REG_0104_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_END);

	//set disp domain trigger gen setting, ref to tgen sync.
	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A5, 0x4,
		  REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL);
#else
	if (!priv->cus_info.moni_p_en) {
	//Vde start protect
		u32TargetVdeStart = _tgen_target_vde_v007(priv->de_height);
		u32TargetVTTVBuf = _tgen_target_VTTVBuf_v007(priv->de_height);

		if ((priv->de_width == TIMING_4K_H_ACTIVE && priv->de_height == TIMING_4K_V_ACTIVE) &&
			(priv->pnl_lib_version == BOOT_PNL_VERSION0400 || priv->pnl_lib_version == BOOT_PNL_VERSION0500))
			u32TargetVdeStart = u32TargetVdeStart - TGEN_PIXELSHIFT_BUF;

		if (u32TargetVdeStart > priv->de_vstart) {
			u32DtsVbp = priv->de_vstart - (priv->vsync_st+priv->vsync_w);
			priv->de_vstart = u32TargetVdeStart;
			priv->vsync_st = u32TargetVdeStart - priv->vsync_w - u32DtsVbp;
		}

		if (priv->de_vstart > (priv->typ_vtt - priv->de_height - u32TargetVTTVBuf)) {
			u32DtsVbp = priv->de_vstart - (priv->vsync_st + priv->vsync_w);
			priv->de_vstart = priv->typ_vtt - priv->de_height - u32TargetVTTVBuf;
			if (priv->de_vstart > (priv->vsync_w + u32DtsVbp))
				priv->vsync_st = priv->de_vstart - priv->vsync_w - u32DtsVbp;
			else
				priv->vsync_st = 0;
		}
	}

	UBOOT_DEBUG("Vde start protect\n");
	UBOOT_DEBUG("u32TargetVdeStart %d\n", u32TargetVdeStart);
	UBOOT_DEBUG("u32DtsVbp %d\n", u32DtsVbp);
	UBOOT_DEBUG("priv->de_vstart %d\n", priv->de_vstart);
	UBOOT_DEBUG("priv->vsync_st %d\n", priv->vsync_st);

	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_TS_MD);	//legacy mode.

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
		// 1p aligned
		alignNum = 1;
		priv->de_hstart = _align_floor_v007(priv->de_hstart, alignNum);
		priv->de_width = _align_floor_v007(priv->de_width, alignNum);
	}

	W2BYTEMSK(REG_004C_TGEN_MAIN_BKA3A0, priv->typ_htt - 1, REG_004C_TGEN_MAIN_BKA3A0_REG_HTT);
	W2BYTEMSK(REG_008C_TGEN_MAIN_BKA3A0, priv->typ_vtt - 1, REG_008C_TGEN_MAIN_BKA3A0_REG_VTT);

	W2BYTEMSK(REG_0050_TGEN_MAIN_BKA3A0, 0, REG_0050_TGEN_MAIN_BKA3A0_REG_HSYNC_ST);
	W2BYTEMSK(REG_0054_TGEN_MAIN_BKA3A0, priv->hsync_w - 1,
		  REG_0054_TGEN_MAIN_BKA3A0_REG_HSYNC_END);

	W2BYTEMSK(REG_0058_TGEN_MAIN_BKA3A0, priv->de_hstart,
		  REG_0058_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_ST);
	W2BYTEMSK(REG_005C_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1,
		  REG_005C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_END);
	W2BYTEMSK(REG_0060_TGEN_MAIN_BKA3A0, priv->de_hstart,
		  REG_0060_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_ST);
	W2BYTEMSK(REG_0064_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1,
		  REG_0064_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_END);

	//set tcon de for s company justscan orbit case
	//the value is equal to panel DE
	W2BYTEMSK(REG_0070_TGEN_MAIN_BKA3A0, priv->de_hstart,
		  REG_0070_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_TCON_ST);
	W2BYTEMSK(REG_0074_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1,
		  REG_0074_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_TCON_END);

	//GFX?
	W2BYTEMSK(REG_0068_TGEN_MAIN_BKA3A0, priv->de_hstart,
		  REG_0068_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_ST);
	W2BYTEMSK(REG_006C_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1,
		  REG_006C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_END);

	//disp lb Hsize
	W2BYTEMSK(REG_0018_DISP_LB_BKA326, priv->de_width, REG_0018_DISP_LB_BKA326_REG_DISP_HSIZE);

	W2BYTEMSK(REG_0090_TGEN_MAIN_BKA3A0, priv->vsync_st,
		  REG_0090_TGEN_MAIN_BKA3A0_REG_VSYNC_ST);
	W2BYTEMSK(REG_0014_TGEN_OUTPUT_BKA3A3, 0, REG_0014_TGEN_OUTPUT_BKA3A3_REG_TGEN_TO_TRIG_GEN_VSYNC_VCNT);	// to trigger gen vsync : same as vsync start

	W2BYTEMSK(REG_0094_TGEN_MAIN_BKA3A0, priv->vsync_st + priv->vsync_w - 1,
		  REG_0094_TGEN_MAIN_BKA3A0_REG_VSYNC_END);
	W2BYTEMSK(REG_0098_TGEN_MAIN_BKA3A0, priv->de_vstart,
		  REG_0098_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_ST);
	W2BYTEMSK(REG_009C_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1,
		  REG_009C_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_END);
	W2BYTEMSK(REG_00A0_TGEN_MAIN_BKA3A0, priv->de_vstart,
		  REG_00A0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_ST);
	W2BYTEMSK(REG_00A4_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1,
		  REG_00A4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_END);

	//set tcon de for s company justscan orbit case
	//the value is equal to panel DE
	W2BYTEMSK(REG_00B0_TGEN_MAIN_BKA3A0, priv->de_vstart,
		  REG_00B0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_TCON_ST);
	W2BYTEMSK(REG_00B4_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1,
		  REG_00B4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_TCON_END);

	//GFX?
	W2BYTEMSK(REG_00A8_TGEN_MAIN_BKA3A0, priv->de_vstart,
		  REG_00A8_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_ST);
	W2BYTEMSK(REG_00AC_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1,
		  REG_00AC_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_END);

	//disp lb Vsize
	W2BYTEMSK(REG_001C_DISP_LB_BKA326, priv->de_height, REG_001C_DISP_LB_BKA326_REG_DISP_VSIZE);

	W2BYTEMSK(REG_01F4_TGEN_MAIN_BKA3A0, 0xFFFF, REG_01F4_TGEN_MAIN_BKA3A0_REG_M_DELTA);	// m delta
	W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, priv->min_vtt_panelprotect, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END);	// protect v endi

	if ((priv->de_vstart + priv->de_height) > priv->min_vtt_panelprotect) {	//if Vde_end is after Vmin then use Vde_end as lower bound
		W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, priv->de_vstart + priv->de_height, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END);	// protect v end
		W2BYTEMSK(REG_01F8_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height,
			  REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND);
	} else {
		W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, priv->min_vtt_panelprotect, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END);	// protect v end
		W2BYTEMSK(REG_01F8_TGEN_MAIN_BKA3A0, priv->min_vtt_panelprotect,
			  REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND);
	}
	W2BYTEMSK(REG_01FC_TGEN_MAIN_BKA3A0, priv->max_vtt_panelprotect,
		  REG_01FC_TGEN_MAIN_BKA3A0_REG_PANEL_UPPER_BOUND);

	W2BYTEMSK(REG_0084_TGEN_MAIN_BKA3A0, 0, REG_0084_TGEN_MAIN_BKA3A0_REG_EVEN_VTT_VCNT_EN);

	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_XTALI);

	W2BYTEMSK(REG_0008_TGEN_MAIN_BKA3A0, 1, REG_0008_TGEN_MAIN_BKA3A0_REG_TGEN_VIDEO_EN);	// only enable window 0

	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_ODCLK);

	W2BYTEMSK(REG_00C0_TGEN_MAIN_BKA3A0, priv->de_hstart,
		  REG_00C0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_ST);
	W2BYTEMSK(REG_00C4_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1,
		  REG_00C4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_END);
	W2BYTEMSK(REG_0100_TGEN_MAIN_BKA3A0, priv->de_vstart,
		  REG_0100_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_ST);
	W2BYTEMSK(REG_0104_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1,
		  REG_0104_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_END);

	//set disp domain trigger gen setting, ref to tgen sync.
	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A5, 0x4,
		  REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL);

	//For main video_out 120hz, GFX 60HZ output case,
	//need to reset gfx every 2 vsync
	if (priv->out_timing == E_4K2K_120HZ || priv->out_timing == E_4K2K_144HZ ||
	    priv->out_timing == E_4K1K_240HZ || priv->out_timing == E_5K2K_60HZ)
		W2BYTEMSK(REG_004C_TGEN_OUTPUT_BKA3A3, 0x1,
			  REG_004C_TGEN_OUTPUT_BKA3A3_REG_TGEN_TO_GOP_REF_MASK_EN);

	//sw patch for reset gop-sc aid binding

	_PATCH_TRIGGER_GEN_v007(priv);

	_tgen_qms_related_setting_v007(dev);

#endif
	return 0;

}

static void _lvds_v_hd_60HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}
	// LVDS always 2p
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x3, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0x780, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_015C_MODD1_V007, 0x0, REG_015C_MODD1_V007_REG_SERI_FORMAT_V1);
	//REG_0038_MODA1_REG_GCR_BANK_CLK_SRC_SEL bit[0:0]
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1, 0, AC_MSKB0));
	W2BYTEMSK(REG_003C_MODV11_V007, 0x10, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_RSCLK_TESTMD);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_lvds_ti_mode, REG_00E0_MODD1_V007_REG_LVDS_TI);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_pdp_10bit, REG_00E0_MODD1_V007_REG_PDP_10BIT);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_LVDS_PLASMA);
	W2BYTEMSK(REG_00E0_MODD1_V007, (priv->lvds_info.panel_swap_lvds_pol), REG_00E0_MODD1_V007_REG_CH_POLARITY);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_swap_lvds_ch, REG_00E0_MODD1_V007_REG_PA_SWAP);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH4_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH4_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH3_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH3_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_MASK_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_MASK_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.ti_bit_mode, REG_00E0_MODD1_V007_REG_TI_BITMODE);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_LVDS_TESTERMD);
	UBOOT_DEBUG("[%s] LVDS HD_60 case\n", __func__);
}

static void _lvds_v_hd_120HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}
	// LVDS always 2p
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x3, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0x780, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_015C_MODD1_V007, 0x0, REG_015C_MODD1_V007_REG_SERI_FORMAT_V1);
	//REG_0038_MODA1_REG_GCR_BANK_CLK_SRC_SEL bit[0:0]
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1, 0, AC_MSKB0));
	W2BYTEMSK(REG_003C_MODV11_V007, 0x10, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_RSCLK_TESTMD);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_lvds_ti_mode, REG_00E0_MODD1_V007_REG_LVDS_TI);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_pdp_10bit, REG_00E0_MODD1_V007_REG_PDP_10BIT);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_LVDS_PLASMA);
	W2BYTEMSK(REG_00E0_MODD1_V007, (priv->lvds_info.panel_swap_lvds_pol), REG_00E0_MODD1_V007_REG_CH_POLARITY);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_swap_lvds_ch, REG_00E0_MODD1_V007_REG_PA_SWAP);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH4_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH4_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH3_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH3_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_MASK_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_MASK_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.ti_bit_mode, REG_00E0_MODD1_V007_REG_TI_BITMODE);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_LVDS_TESTERMD);
	UBOOT_DEBUG("[%s] LVDS HD_120 case\n", __func__);
}

static void _lvds_v_fhd_60HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	// LVDS always 2p
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x2, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0x780, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_015C_MODD1_V007, 0x0, REG_015C_MODD1_V007_REG_SERI_FORMAT_V1);
	//REG_0038_MODA1_REG_GCR_BANK_CLK_SRC_SEL bit[0:0]
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1, 0, AC_MSKB0));
	W2BYTEMSK(REG_003C_MODV11_V007, 0x10, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_RSCLK_TESTMD);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_lvds_ti_mode, REG_00E0_MODD1_V007_REG_LVDS_TI);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_pdp_10bit, REG_00E0_MODD1_V007_REG_PDP_10BIT);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_LVDS_PLASMA);
	W2BYTEMSK(REG_00E0_MODD1_V007, (priv->lvds_info.panel_swap_lvds_pol), REG_00E0_MODD1_V007_REG_CH_POLARITY);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.panel_swap_lvds_ch, REG_00E0_MODD1_V007_REG_PA_SWAP);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH4_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH4_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH3_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_CH3_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_MASK_SET);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_PDP_MASK_EN);
	W2BYTEMSK(REG_00E0_MODD1_V007, priv->lvds_info.ti_bit_mode, REG_00E0_MODD1_V007_REG_TI_BITMODE);
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x0, REG_00E0_MODD1_V007_REG_LVDS_TESTERMD);
	UBOOT_DEBUG("[%s] LVDS FHD_60 case\n", __func__);
}

static void _vby1_v_fhd_60HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x2, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0x780, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_003C_MODV11_V007, 0x10, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	UBOOT_DEBUG("[%s] VBY1 FHD_60 case\n", __func__);
}

static void _vby1_v_fhd_120HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x1, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0x780, REG_0040_MODV11_V007_REG_HSIZE); //move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_003C_MODV11_V007, HEX_10, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	UBOOT_DEBUG("[%s] VBY1 FHD_120 case\n", __func__);
}

static void _vby1_v_fhd_240HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x1, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0x780, REG_0040_MODV11_V007_REG_HSIZE); //move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_003C_MODV11_V007, HEX_10, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	UBOOT_DEBUG("[%s] VBY1 FHD_240 case\n", __func__);
}

static void _vby1_v_4k_30HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x1, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0xF00, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_003C_MODV11_V007, HEX_22, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	UBOOT_DEBUG("[%s] VBY1 4K_30 case\n", __func__);
}

static void _vby1_v_4k_60HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x0, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0xF00, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_003C_MODV11_V007, HEX_22, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	UBOOT_DEBUG("[%s] VBY1 4K_60 case\n", __func__);
}

static void _vby1_v_4k_120HZ_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, 0x0, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11_V007, 0xF00, REG_0040_MODV11_V007_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x0, REG_0004_MODV12_V007_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, 0x1, REG_0004_MODV12_V007_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12_V007, 0x0, REG_0008_MODV12_V007_REG_FORMAT_MAP);
	W2BYTEMSK(REG_003C_MODV11_V007, HEX_11, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	UBOOT_DEBUG("[%s] VBY1 4K_120 case\n", __func__);
}

static void _edp_v_common_timing_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}
	// eDP common setting
	W2BYTEMSK(REG_0140_MODV11_V007, HEX_0, REG_0140_MODV11_V007_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, HEX_1, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, HEX_1, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11_V007, HEX_0, REG_0140_MODV11_V007_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11_V007, HEX_0, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
	W2BYTEMSK(REG_015C_MODD1_V007, HEX_D, REG_015C_MODD1_V007_REG_SERI_FORMAT_V1);
	W2BYTEMSK(REG_003C_MODV11_V007, HEX_22, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
}

static void _vby1_set_byte_mode_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	en_vbo_bytemode vbo_byte = E_VBO_NO_LINK;

	if (priv == NULL) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	if (priv->linktype != E_LINK_VB1)
		return;

	vbo_byte = priv->vbo_byte;

	if (vbo_byte == E_VBO_5BYTE_MODE) {
		// 5 byte mode
		W2BYTEMSK(REG_0188_MODV12_V007, 1, REG_0188_MODV12_V007_REG_VBY1_BYTE_MODE);
		W2BYTEMSK(REG_015C_MODD1_V007, DEC_3, REG_015C_MODD1_V007_REG_SERI_FORMAT_V1);
		W2BYTEMSK(REG_0038_MODA1_V007, 0x1, Fld(1, 0, AC_MSKB0));
	} else {
		// 4 byte mode
		W2BYTEMSK(REG_0188_MODV12_V007, DEC_2, REG_0188_MODV12_V007_REG_VBY1_BYTE_MODE);
		W2BYTEMSK(REG_015C_MODD1_V007, 0x1, REG_015C_MODD1_V007_REG_SERI_FORMAT_V1);
		W2BYTEMSK(REG_0038_MODA1_V007, 0x0, Fld(1, 0, AC_MSKB0));
	}
}

static void _vby1_set_mft_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	uint8_t htt_slot = 0;

	if (priv->out_format == E_OUTPUT_YUV422)
		W2BYTEMSK(REG_0040_MODV11_V007, priv->de_width / 2, REG_0040_MODV11_V007_REG_HSIZE);
	else
		W2BYTEMSK(REG_0040_MODV11_V007, priv->de_width, REG_0040_MODV11_V007_REG_HSIZE);

	if (priv->linktype == E_LINK_VB1 || IS_EDP_OUT(priv->linktype)) {
		switch (priv->div_sec) {
		case 1:
			W2BYTEMSK(REG_0004_MODV11_V007, 0x1, REG_0004_MODV11_V007_REG_MFT_MODE);
			if (priv->out_format == E_OUTPUT_YUV422)
				W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width / 2,
					  REG_0044_MODV11_V007_REG_DIV_LEN);
			else
				W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width,
					  REG_0044_MODV11_V007_REG_DIV_LEN);

			W2BYTEMSK(REG_0048_MODV11_V007, 0x0, REG_0048_MODV11_V007_REG_BASE0_ADDR);
			break;

		case 2:
			W2BYTEMSK(REG_0004_MODV11_V007, 0x2, REG_0004_MODV11_V007_REG_MFT_MODE);
			if (priv->out_format == E_OUTPUT_YUV422)
				W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width / 4,
					  REG_0044_MODV11_V007_REG_DIV_LEN);
			else
				W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width / 2,
					  REG_0044_MODV11_V007_REG_DIV_LEN);

			W2BYTEMSK(REG_0048_MODV11_V007, 0x0, REG_0048_MODV11_V007_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV11_V007, priv->de_width / 2,
				  REG_004C_MODV11_V007_REG_BASE1_ADDR);
			break;

		case 4:
			W2BYTEMSK(REG_0004_MODV11_V007, 0x3, REG_0004_MODV11_V007_REG_MFT_MODE);
			W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width / 4, REG_0044_MODV11_V007_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV11_V007, 0x0, REG_0048_MODV11_V007_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV11_V007, priv->de_width / 4,
				  REG_004C_MODV11_V007_REG_BASE1_ADDR);
			W2BYTEMSK(REG_0050_MODV11_V007, priv->de_width / 2,
				  REG_0050_MODV11_V007_REG_BASE2_ADDR);
			W2BYTEMSK(REG_0054_MODV11_V007, priv->de_width * 3 / 4,
				  REG_0054_MODV11_V007_REG_BASE3_ADDR);
			break;

		case 8:
			W2BYTEMSK(REG_0004_MODV11_V007, 0x4, REG_0004_MODV11_V007_REG_MFT_MODE);
			W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width / 8, REG_0044_MODV11_V007_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV11_V007, 0x0, REG_0048_MODV11_V007_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV11_V007, priv->de_width / 8,
				  REG_004C_MODV11_V007_REG_BASE1_ADDR);
			W2BYTEMSK(REG_0050_MODV11_V007, priv->de_width / 4,
				  REG_0050_MODV11_V007_REG_BASE2_ADDR);
			W2BYTEMSK(REG_0054_MODV11_V007, priv->de_width * 3 / 8,
				  REG_0054_MODV11_V007_REG_BASE3_ADDR);
			W2BYTEMSK(REG_0058_MODV11_V007, priv->de_width / 2,
				  REG_0058_MODV11_V007_REG_BASE4_ADDR);
			W2BYTEMSK(REG_005C_MODV11_V007, priv->de_width * 5 / 8,
				  REG_005C_MODV11_V007_REG_BASE5_ADDR);
			W2BYTEMSK(REG_0060_MODV11_V007, priv->de_width * 6 / 8,
				  REG_0060_MODV11_V007_REG_BASE6_ADDR);
			W2BYTEMSK(REG_0064_MODV11_V007, priv->de_width * 7 / 8,
				  REG_0064_MODV11_V007_REG_BASE7_ADDR);
			break;

		default:
			debug("UNSUPPORT MFT Division\n");
			break;

		}

		if (priv->lanes / MFT_P > 0)
			htt_slot = priv->lanes / MFT_P - 1;
		else
			htt_slot = 0;

		W2BYTEMSK(REG_000C_MODV11_V007, htt_slot, REG_000C_MODV11_V007_REG_MFT_VLD_WRAP_FIX_HTT);
	}

	if (priv->linktype == E_LINK_LVDS) {
		//prepare for h mirror case
		W2BYTEMSK(REG_0004_MODV11_V007, 0x1, REG_0004_MODV11_V007_REG_MFT_MODE);
		W2BYTEMSK(REG_0044_MODV11_V007, priv->de_width, REG_0044_MODV11_V007_REG_DIV_LEN);
		W2BYTEMSK(REG_0048_MODV11_V007, 0x0, REG_0048_MODV11_V007_REG_BASE0_ADDR);
	}
#ifdef CONFIG_HAPS
	//if (priv->pnl_lib_version == BOOT_PNL_VERSION0500)
	{
		// HAPS case, bypass MFT
		W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_MOD_1PTO2P_EN);
		W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_MOD_2PTO4P_EN);
		W2BYTEMSK(REG_0140_MODV11_V007, 0x0, REG_0140_MODV11_V007_REG_MOD_4PTO8P_EN);
		W2BYTEMSK(REG_0004_MODV11_V007, 0x1, REG_0004_MODV11_V007_REG_DIV_PIX_MODE);
		W2BYTEMSK(REG_0004_MODV11_V007, 0xA, REG_0004_MODV11_V007_REG_MFT_MODE);

		W2BYTEMSK(REG_0008_MODV11_V007, 0x0, REG_0008_MODV11_V007_REG_MFT_KEEP_VB_DE_OUT);
		W2BYTEMSK(REG_0008_MODV11_V007, 0x0, REG_0008_MODV11_V007_REG_DE2TO1_ENABLE);
		W2BYTEMSK(REG_0008_MODV11_V007, 0x1, REG_0008_MODV11_V007_REG_MFT_VB_MASK_LB_RD);
		W2BYTEMSK(REG_0008_MODV11_V007, 0x1, REG_0008_MODV11_V007_REG_MFT_VB_MASK_LB_WR);
		W2BYTEMSK(REG_003C_MODV11_V007, 0x15, REG_003C_MODV11_V007_REG_MFT_READ_HDE_ST);
	}
#endif				//#ifdef CONFIG
}

static void _vby1_set_SCTCON_MISC_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->out_format == E_OUTPUT_YUV444) {
		W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 0,
			  REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL);
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 1,
			  REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_BYPASS);
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 0,
			  REG_0040_SCTCON_MISC_BKA3E0_REG_MOD_REORDER);
	} else if (priv->out_format == E_OUTPUT_YUV422) {
		W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 0, REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL);	//csc out bypass
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 0,
			  REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_BYPASS);
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 1,
			  REG_0040_SCTCON_MISC_BKA3E0_REG_MOD_REORDER);
	} else {
		W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 1, REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL);	//csc out bypass
	}
}

static void _vby1_seri_data_sel_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->lanes == 32)
		W2BYTEMSK(REG_00C0_MODD1_V007, 0x1, REG_00C0_MODD1_V007_REG_DATAX_SEL);

	if (priv->lanes == 16 || priv->lanes == 8)
		W2BYTEMSK(REG_00C0_MODD1_V007, 0x2, REG_00C0_MODD1_V007_REG_DATAX_SEL);

	if (priv->lanes == 64)
		W2BYTEMSK(REG_00C0_MODD1_V007, 0x3, REG_00C0_MODD1_V007_REG_DATAX_SEL);

	if (priv->linktype == E_LINK_LVDS)
		W2BYTEMSK(REG_00C0_MODD1_V007, 0x0, REG_00C0_MODD1_V007_REG_DATAX_SEL);

	if (IS_EDP_OUT(priv->linktype))
		W2BYTEMSK(REG_00C0_MODD1_V007, HEX_C, REG_00C0_MODD1_V007_REG_DATAX_SEL);
}

static void _pin_mapping_free_swap_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}
	//ping mapping free swap
	if (priv->linktype == E_LINK_LVDS) {
		W2BYTEMSK(REG_0044_MODD1_V007, 0x00, REG_0044_MODD1_V007_REG_FREE_CH02_SWAP);
		W2BYTEMSK(REG_0044_MODD1_V007, 0x01, REG_0044_MODD1_V007_REG_FREE_CH03_SWAP);
		W2BYTEMSK(REG_0048_MODD1_V007, DEC_2, REG_0048_MODD1_V007_REG_FREE_CH04_SWAP);
		W2BYTEMSK(REG_0048_MODD1_V007, DEC_3, REG_0048_MODD1_V007_REG_FREE_CH05_SWAP);
		W2BYTEMSK(REG_004C_MODD1_V007, DEC_4, REG_004C_MODD1_V007_REG_FREE_CH06_SWAP);
		W2BYTEMSK(REG_004C_MODD1_V007, DEC_5, REG_004C_MODD1_V007_REG_FREE_CH07_SWAP);
		W2BYTEMSK(REG_0080_MODD1_V007, DEC_6, REG_0080_MODD1_V007_REG_FREE_CH32_SWAP);
		W2BYTEMSK(REG_0080_MODD1_V007, DEC_7, REG_0080_MODD1_V007_REG_FREE_CH33_SWAP);
		W2BYTEMSK(REG_0084_MODD1_V007, DEC_8, REG_0084_MODD1_V007_REG_FREE_CH34_SWAP);
		W2BYTEMSK(REG_0084_MODD1_V007, DEC_9, REG_0084_MODD1_V007_REG_FREE_CH35_SWAP);
		W2BYTEMSK(REG_0088_MODD1_V007, DEC_10, REG_0088_MODD1_V007_REG_FREE_CH36_SWAP);
		W2BYTEMSK(REG_0088_MODD1_V007, DEC_11, REG_0088_MODD1_V007_REG_FREE_CH37_SWAP);
	}
	//TODO:EDP
	if (IS_EDP_OUT(priv->linktype)) {
		switch (priv->linktype) {
		case E_LINK_EDP_4LANE_2K60:
		case E_LINK_EDP_4LANE_4K30:
		case E_LINK_EDP_4LANE_4K60:
			W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[DEC_0], REG_0040_MODD1_V007_REG_FREE_CH00_SWAP);
			W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[DEC_1], REG_0040_MODD1_V007_REG_FREE_CH01_SWAP);
			W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_2], REG_0044_MODD1_V007_REG_FREE_CH02_SWAP);
			W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_3], REG_0044_MODD1_V007_REG_FREE_CH03_SWAP);
			break;

		case E_LINK_EDP_8LANE_4K120:
			W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[DEC_0], REG_0040_MODD1_V007_REG_FREE_CH00_SWAP);
			W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[DEC_1], REG_0040_MODD1_V007_REG_FREE_CH01_SWAP);
			W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_2], REG_0044_MODD1_V007_REG_FREE_CH02_SWAP);
			W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_3], REG_0044_MODD1_V007_REG_FREE_CH03_SWAP);
			W2BYTEMSK(REG_0048_MODD1_V007, priv->lane_info.def_layout[DEC_4], REG_0048_MODD1_V007_REG_FREE_CH04_SWAP);
			W2BYTEMSK(REG_0048_MODD1_V007, priv->lane_info.def_layout[DEC_5], REG_0048_MODD1_V007_REG_FREE_CH05_SWAP);
			W2BYTEMSK(REG_004C_MODD1_V007, priv->lane_info.def_layout[DEC_6], REG_004C_MODD1_V007_REG_FREE_CH06_SWAP);
			W2BYTEMSK(REG_004C_MODD1_V007, priv->lane_info.def_layout[DEC_7], REG_004C_MODD1_V007_REG_FREE_CH07_SWAP);
			break;

		case E_LINK_EDP_16LANE_4K144:
		case E_LINK_EDP_16LANE_4K165:
			W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[DEC_0], REG_0040_MODD1_V007_REG_FREE_CH00_SWAP);
			W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[DEC_1], REG_0040_MODD1_V007_REG_FREE_CH01_SWAP);
			W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_2], REG_0044_MODD1_V007_REG_FREE_CH02_SWAP);
			W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_3], REG_0044_MODD1_V007_REG_FREE_CH03_SWAP);
			W2BYTEMSK(REG_0048_MODD1_V007, priv->lane_info.def_layout[DEC_4], REG_0048_MODD1_V007_REG_FREE_CH04_SWAP);
			W2BYTEMSK(REG_0048_MODD1_V007, priv->lane_info.def_layout[DEC_5], REG_0048_MODD1_V007_REG_FREE_CH05_SWAP);
			W2BYTEMSK(REG_004C_MODD1_V007, priv->lane_info.def_layout[DEC_6], REG_004C_MODD1_V007_REG_FREE_CH06_SWAP);
			W2BYTEMSK(REG_004C_MODD1_V007, priv->lane_info.def_layout[DEC_7], REG_004C_MODD1_V007_REG_FREE_CH07_SWAP);
			W2BYTEMSK(REG_0050_MODD1_V007, priv->lane_info.def_layout[DEC_8], REG_0050_MODD1_V007_REG_FREE_CH08_SWAP);
			W2BYTEMSK(REG_0050_MODD1_V007, priv->lane_info.def_layout[DEC_9], REG_0050_MODD1_V007_REG_FREE_CH09_SWAP);
			W2BYTEMSK(REG_0054_MODD1_V007, priv->lane_info.def_layout[DEC_10], REG_0054_MODD1_V007_REG_FREE_CH10_SWAP);
			W2BYTEMSK(REG_0054_MODD1_V007, priv->lane_info.def_layout[DEC_11], REG_0054_MODD1_V007_REG_FREE_CH11_SWAP);
			W2BYTEMSK(REG_0058_MODD1_V007, priv->lane_info.def_layout[DEC_12], REG_0058_MODD1_V007_REG_FREE_CH12_SWAP);
			W2BYTEMSK(REG_0058_MODD1_V007, priv->lane_info.def_layout[DEC_13], REG_0058_MODD1_V007_REG_FREE_CH13_SWAP);
			W2BYTEMSK(REG_005C_MODD1_V007, priv->lane_info.def_layout[DEC_14], REG_005C_MODD1_V007_REG_FREE_CH14_SWAP);
			W2BYTEMSK(REG_005C_MODD1_V007, priv->lane_info.def_layout[DEC_15], REG_005C_MODD1_V007_REG_FREE_CH15_SWAP);
			break;
		default:
			UBOOT_DEBUG("Video OUTPUT TIMING Not Support\n");
			break;
		}
	}
	if (priv->linktype == E_LINK_VB1) {
		W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[0],
			  REG_0040_MODD1_V007_REG_FREE_CH00_SWAP);
		W2BYTEMSK(REG_0040_MODD1_V007, priv->lane_info.def_layout[1],
			  REG_0040_MODD1_V007_REG_FREE_CH01_SWAP);
		W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_2],
			  REG_0044_MODD1_V007_REG_FREE_CH02_SWAP);
		W2BYTEMSK(REG_0044_MODD1_V007, priv->lane_info.def_layout[DEC_3],
			  REG_0044_MODD1_V007_REG_FREE_CH03_SWAP);
		W2BYTEMSK(REG_0048_MODD1_V007, priv->lane_info.def_layout[DEC_4],
			  REG_0048_MODD1_V007_REG_FREE_CH04_SWAP);
		W2BYTEMSK(REG_0048_MODD1_V007, priv->lane_info.def_layout[DEC_5],
			  REG_0048_MODD1_V007_REG_FREE_CH05_SWAP);
		W2BYTEMSK(REG_004C_MODD1_V007, priv->lane_info.def_layout[DEC_6],
			  REG_004C_MODD1_V007_REG_FREE_CH06_SWAP);
		W2BYTEMSK(REG_004C_MODD1_V007, priv->lane_info.def_layout[DEC_7],
			  REG_004C_MODD1_V007_REG_FREE_CH07_SWAP);
		W2BYTEMSK(REG_0080_MODD1_V007, priv->lane_info.def_layout[DEC_8],
			  REG_0080_MODD1_V007_REG_FREE_CH32_SWAP);
		W2BYTEMSK(REG_0080_MODD1_V007, priv->lane_info.def_layout[DEC_9],
			  REG_0080_MODD1_V007_REG_FREE_CH33_SWAP);
		W2BYTEMSK(REG_0084_MODD1_V007, priv->lane_info.def_layout[DEC_10],
			  REG_0084_MODD1_V007_REG_FREE_CH34_SWAP);
		W2BYTEMSK(REG_0084_MODD1_V007, priv->lane_info.def_layout[DEC_11],
			  REG_0084_MODD1_V007_REG_FREE_CH35_SWAP);
		W2BYTEMSK(REG_0088_MODD1_V007, priv->lane_info.def_layout[DEC_12],
			  REG_0088_MODD1_V007_REG_FREE_CH36_SWAP);
		W2BYTEMSK(REG_0088_MODD1_V007, priv->lane_info.def_layout[DEC_13],
			  REG_0088_MODD1_V007_REG_FREE_CH37_SWAP);
		W2BYTEMSK(REG_008C_MODD1_V007, priv->lane_info.def_layout[DEC_14],
			  REG_008C_MODD1_V007_REG_FREE_CH38_SWAP);
		W2BYTEMSK(REG_008C_MODD1_V007, priv->lane_info.def_layout[DEC_15],
			  REG_008C_MODD1_V007_REG_FREE_CH39_SWAP);
	}
}

static void _usr_def_free_swap_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->linktype == E_LINK_VB1) {
		W2BYTEMSK(REG_01A0_MODV12_V007, priv->lane_info.lane_order[0],
			  REG_01A0_MODV12_V007_REG_VBY1_SWAP_CH00);
		W2BYTEMSK(REG_01A0_MODV12_V007, priv->lane_info.lane_order[1],
			  REG_01A0_MODV12_V007_REG_VBY1_SWAP_CH01);

		W2BYTEMSK(REG_01A4_MODV12_V007, priv->lane_info.lane_order[2],
			  REG_01A4_MODV12_V007_REG_VBY1_SWAP_CH02);
		W2BYTEMSK(REG_01A4_MODV12_V007, priv->lane_info.lane_order[3],
			  REG_01A4_MODV12_V007_REG_VBY1_SWAP_CH03);

		W2BYTEMSK(REG_01A8_MODV12_V007, priv->lane_info.lane_order[4],
			  REG_01A8_MODV12_V007_REG_VBY1_SWAP_CH04);
		W2BYTEMSK(REG_01A8_MODV12_V007, priv->lane_info.lane_order[5],
			  REG_01A8_MODV12_V007_REG_VBY1_SWAP_CH05);

		W2BYTEMSK(REG_01AC_MODV12_V007, priv->lane_info.lane_order[6],
			  REG_01AC_MODV12_V007_REG_VBY1_SWAP_CH06);
		W2BYTEMSK(REG_01AC_MODV12_V007, priv->lane_info.lane_order[7],
			  REG_01AC_MODV12_V007_REG_VBY1_SWAP_CH07);

		W2BYTEMSK(REG_01B0_MODV12_V007, priv->lane_info.lane_order[8],
			  REG_01B0_MODV12_V007_REG_VBY1_SWAP_CH08);
		W2BYTEMSK(REG_01B0_MODV12_V007, priv->lane_info.lane_order[9],
			  REG_01B0_MODV12_V007_REG_VBY1_SWAP_CH09);

		W2BYTEMSK(REG_01B4_MODV12_V007, priv->lane_info.lane_order[10],
			  REG_01B4_MODV12_V007_REG_VBY1_SWAP_CH10);
		W2BYTEMSK(REG_01B4_MODV12_V007, priv->lane_info.lane_order[11],
			  REG_01B4_MODV12_V007_REG_VBY1_SWAP_CH11);
		W2BYTEMSK(REG_01B8_MODV12_V007, priv->lane_info.lane_order[12],
			  REG_01B8_MODV12_V007_REG_VBY1_SWAP_CH12);
		W2BYTEMSK(REG_01B8_MODV12_V007, priv->lane_info.lane_order[13],
			  REG_01B8_MODV12_V007_REG_VBY1_SWAP_CH13);
		W2BYTEMSK(REG_01BC_MODV12_V007, priv->lane_info.lane_order[14],
			  REG_01BC_MODV12_V007_REG_VBY1_SWAP_CH14);
		W2BYTEMSK(REG_01BC_MODV12_V007, priv->lane_info.lane_order[15],
			  REG_01BC_MODV12_V007_REG_VBY1_SWAP_CH15);
		W2BYTEMSK(REG_01C0_MODV12_V007, priv->lane_info.lane_order[16],
			  REG_01C0_MODV12_V007_REG_VBY1_SWAP_CH16);
		W2BYTEMSK(REG_01C0_MODV12_V007, priv->lane_info.lane_order[17],
			  REG_01C0_MODV12_V007_REG_VBY1_SWAP_CH17);
		W2BYTEMSK(REG_01C4_MODV12_V007, priv->lane_info.lane_order[18],
			  REG_01C4_MODV12_V007_REG_VBY1_SWAP_CH18);
		W2BYTEMSK(REG_01C4_MODV12_V007, priv->lane_info.lane_order[19],
			  REG_01C4_MODV12_V007_REG_VBY1_SWAP_CH19);

		W2BYTEMSK(REG_01C8_MODV12_V007, priv->lane_info.lane_order[20],
			  REG_01C8_MODV12_V007_REG_VBY1_SWAP_CH20);
		W2BYTEMSK(REG_01C8_MODV12_V007, priv->lane_info.lane_order[21],
			  REG_01C8_MODV12_V007_REG_VBY1_SWAP_CH21);
		W2BYTEMSK(REG_01CC_MODV12_V007, priv->lane_info.lane_order[22],
			  REG_01CC_MODV12_V007_REG_VBY1_SWAP_CH22);
		W2BYTEMSK(REG_01CC_MODV12_V007, priv->lane_info.lane_order[23],
			  REG_01CC_MODV12_V007_REG_VBY1_SWAP_CH23);

		W2BYTEMSK(REG_01D0_MODV12_V007, priv->lane_info.lane_order[24],
			  REG_01D0_MODV12_V007_REG_VBY1_SWAP_CH24);
		W2BYTEMSK(REG_01D0_MODV12_V007, priv->lane_info.lane_order[25],
			  REG_01D0_MODV12_V007_REG_VBY1_SWAP_CH25);
		W2BYTEMSK(REG_01D4_MODV12_V007, priv->lane_info.lane_order[26],
			  REG_01D4_MODV12_V007_REG_VBY1_SWAP_CH26);
		W2BYTEMSK(REG_01D4_MODV12_V007, priv->lane_info.lane_order[27],
			  REG_01D4_MODV12_V007_REG_VBY1_SWAP_CH27);
		W2BYTEMSK(REG_01D8_MODV12_V007, priv->lane_info.lane_order[28],
			  REG_01D8_MODV12_V007_REG_VBY1_SWAP_CH28);
		W2BYTEMSK(REG_01D8_MODV12_V007, priv->lane_info.lane_order[29],
			  REG_01D8_MODV12_V007_REG_VBY1_SWAP_CH29);
		W2BYTEMSK(REG_01DC_MODV12_V007, priv->lane_info.lane_order[30],
			  REG_01DC_MODV12_V007_REG_VBY1_SWAP_CH30);
		W2BYTEMSK(REG_01DC_MODV12_V007, priv->lane_info.lane_order[31],
			  REG_01DC_MODV12_V007_REG_VBY1_SWAP_CH31);

		W2BYTEMSK(REG_01A0_MODOSD2_V007, priv->lane_info.lane_order[32],
			  REG_01A0_MODOSD2_V007_REG_VBY1_SWAP_CH00);
		W2BYTEMSK(REG_01A0_MODOSD2_V007, priv->lane_info.lane_order[33],
			  REG_01A0_MODOSD2_V007_REG_VBY1_SWAP_CH01);
		W2BYTEMSK(REG_01A4_MODOSD2_V007, priv->lane_info.lane_order[34],
			  REG_01A4_MODOSD2_V007_REG_VBY1_SWAP_CH02);
		W2BYTEMSK(REG_01A4_MODOSD2_V007, priv->lane_info.lane_order[35],
			  REG_01A4_MODOSD2_V007_REG_VBY1_SWAP_CH03);
		W2BYTEMSK(REG_01A8_MODOSD2_V007, priv->lane_info.lane_order[36],
			  REG_01A8_MODOSD2_V007_REG_VBY1_SWAP_CH04);
		W2BYTEMSK(REG_01A8_MODOSD2_V007, priv->lane_info.lane_order[37],
			  REG_01A8_MODOSD2_V007_REG_VBY1_SWAP_CH05);
		W2BYTEMSK(REG_01AC_MODOSD2_V007, priv->lane_info.lane_order[38],
			  REG_01AC_MODOSD2_V007_REG_VBY1_SWAP_CH06);
		W2BYTEMSK(REG_01AC_MODOSD2_V007, priv->lane_info.lane_order[39],
			  REG_01AC_MODOSD2_V007_REG_VBY1_SWAP_CH07);


	}
}

static void _vby1_8lane_def_free_swap_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}
	// 4K60Hz 8lane no need to change laneorder based on div_sec
	if (priv->div_sec) {
		W2BYTEMSK(REG_01A0_MODV12_V007, 0x0100, Fld(16, 0, AC_FULLW10));	//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12_V007, 0x0302, Fld(16, 0, AC_FULLW10));	//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12_V007, 0x0504, Fld(16, 0, AC_FULLW10));	//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12_V007, 0x0706, Fld(16, 0, AC_FULLW10));	//ch6-ch7
	}
}

static void _vby1_16lane_def_free_swap_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	UBOOT_DEBUG("[%s,%5d] div_sec = %d\n", __func__, __LINE__, priv->div_sec);
	if (priv->div_sec == DEC_2) {
		W2BYTEMSK(REG_01A0_MODV12_V007, HEX_0X0100, Fld(DEC_16, 0, AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12_V007, HEX_0X0302, Fld(DEC_16, 0, AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12_V007, HEX_0X0908, Fld(DEC_16, 0, AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12_V007, HEX_0X0B0A, Fld(DEC_16, 0, AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12_V007, HEX_0X0504, Fld(DEC_16, 0, AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12_V007, HEX_0X0706, Fld(DEC_16, 0, AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12_V007, HEX_0X0D0C, Fld(DEC_16, 0, AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12_V007, HEX_0X0F0E, Fld(DEC_16, 0, AC_FULLW10));//ch14-ch15
	}
	if (priv->div_sec == DEC_4) {
		W2BYTEMSK(REG_01A0_MODV12_V007, HEX_0X0100, Fld(DEC_16, 0, AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12_V007, HEX_0X0908, Fld(DEC_16, 0, AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12_V007, HEX_0X0302, Fld(DEC_16, 0, AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12_V007, HEX_0X0B0A, Fld(DEC_16, 0, AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12_V007, HEX_0X0504, Fld(DEC_16, 0, AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12_V007, HEX_0X0D0C, Fld(DEC_16, 0, AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12_V007, HEX_0X0706, Fld(DEC_16, 0, AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12_V007, HEX_0X0F0E, Fld(DEC_16, 0, AC_FULLW10));//ch14-ch15
	}
}

static void _default_free_swap_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->linktype != E_LINK_VB1) {
		printf("[%s] only support E_LINK_VB1\n", __func__);
		return;
	}

	switch (priv->lane_info.ctrl_lanes) {
	case VBO_USE_LANE_NUM_8:
		_vby1_8lane_def_free_swap_v007(dev);
		break;
	case VBO_USE_LANE_NUM_16:
	default:
		_vby1_16lane_def_free_swap_v007(dev);
		break;
	}

}

void _hfrc_setting_for_HAPS_v007(void)
{
	// Bank_a02f_fa: frc_haps
	//wriu -w 0xa02f02 0x0898 // tg_htt      = 16'h898, 16'd2200
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x4, 0x898, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f04 0x0000 // tg_hs_st    = 16'h000
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x8, 0x0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f06 0x000a // tg_hs_end   = 16'h00a
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xC, 0xA, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f08 0x0070 // tg_hfde_st  = 16'h070, 16'd112
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x10, 0x70, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f0a 0x042F // tg_hfde_end = 16'h42F, 16'd1071
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x14, 0x42F, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f0c 0x0070 // tg_hde_st   = 16'h070, 16'd112
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x18, 0x70, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f0e 0x042F // tg_hde_end  = 16'h42F, 16'd1071
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x1C, 0x42F, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f10 0x0465 // tg_vtt      = 16'h465, 16'd1125
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x20, 0x465, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f12 0x0000 // tg_vs_st    = 16'h000
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x24, 0x0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f14 0x0006 // tg_vs_end   = 16'h006
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x28, 0x6, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f16 0x0009 // tg_vfde_st  = 16'h9,   16'd9
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x2C, 0x9, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f18 0x0440 // tg_vfde_end = 16'h440, 16'd1088
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x30, 0x440, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f1a 0x0009 // tg_vde_st   = 16'h9,   16'd9
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x34, 0x9, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f1c 0x0440 // tg_vde_end  = 16'h440, 16'd1088
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x38, 0x440, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f24 0x0002 // tg_frc_vs_st   = 16'h002
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x48, 0x2, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f26 0x000a // tg_frc_vs_end  = 16'h00a
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0x4C, 0xA, Fld(16, 0, AC_FULLW10));

	//wriu -w 0xa02fAE 0x0001 // pure_color_en[12], ip_patgen_en[4], op_patgen_en[0]

	//wriu -w 0xa02f64 0x0800 // scmi_size  = 20'h 70800 (1280*720/2)
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xC8, 0x800, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f66 0x0007 // scmi_size  = 20'h 70800 (1280*720/2)
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xCC, 0x7, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f68 0x03c0 // lb_size    = 12'h 3c0   (960)
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xD0, 0x3C0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f6a 0x0800 // reg_2pto1p, reg1pto2p, fake444, 42to44_mode[1:0] = 16'h0800
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xD4, 0x800, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f76 0x0280 // scmi_hsize = 12'h 280   (640)
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xEC, 0x280, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f78 0x0780 // ip_hsize   = 12'h 780   (1920)
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xF0, 0x780, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f7a 0x03c0 // op_hsize   = 12'h 3c0   (960)
	W2BYTEMSK(REG_HFRC_HAPS_BASE + 0xF4, 0x3C0, Fld(16, 0, AC_FULLW10));


	//Bank_a02f_fb: frc_haps_hvsp_ip
	//wriu -w 0xa02f0e 0x0000 // reg_scale_factor_ho        = 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0x1C, 0x0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f10 0x0130 // reg_scale_ho_en=1, reg_scale_factor_ho  = 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0x20, 0x130, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f12 0x0000 // reg_scale_factor_ve        = 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0x24, 0x0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f14 0x0130 // reg_scale_ve_en=1, reg_scale_factor_ve  = 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0x28, 0x130, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f16 0x42c2 // op_mode
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0x2C, 0x42C2, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f50 0x8F00 // reg_h_size_usr_md[15] = 1'd1 , 1'd0, reg_h_size[13:0] = 14'hF00(3840)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0xA0, 0x8F00, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f52 0x8870 // reg_v_size_usr_md[15] = 1'd1 , 1'd0, reg_v_size[13:0] = 14'h870(2160)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0xA4, 0x8870, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f54 0x0500 // reg_scl_h_size = 13'h0500 (1280)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0xA8, 0x500, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f56 0x02d0 // reg_scl_v_size = 13'h02d0 (720)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0xAC, 0x2D0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02fc0 0x0000 // reg_bypass = 0
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE + 0x180, 0x0, Fld(16, 0, AC_FULLW10));


	//Bank_a02f_f4: frc_haps_hvsp_op
	//wriu -w 0xa02f0e 0xaaaa // reg_scale_factor_ho        = 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0x1C, 0xAAAA, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f10 0x010a // reg_scale_ho_en=1, reg_scale_factor_ho  = 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0x20, 0x10A, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f12 0xaaaa // reg_scale_factor_ve        = 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0x24, 0xAAAA, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f14 0x010a // reg_scale_ve_en=1, reg_scale_factor_ve  = 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0x28, 0x10A, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f16 0x42c2 // op_mode
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0x2C, 0x42C2, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f50 0x8500 // reg_h_size_usr_md[15] = 1'd1 , 1'd0, reg_h_size[13:0] = 14'h500(1280)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0xA0, 0x8500, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f52 0x82d0 // reg_v_size_usr_md[15] = 1'd1 , 1'd0, reg_v_size[13:0] = 14'h2d0(720)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0xA4, 0x82D0, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f54 0x0780 // reg_scl_h_size = 13'h0780 (1920)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0xA8, 0x780, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02f56 0x0438 // reg_scl_v_size = 13'h0438 (1080)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0xAC, 0x438, Fld(16, 0, AC_FULLW10));
	//wriu -w 0xa02fc0 0x0000 // reg_bypass = 0utt
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE + 0x180, 0x0, Fld(16, 0, AC_FULLW10));

}

void _vby1_lane_order_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}
	//ping mapping free swap
	_pin_mapping_free_swap_v007(dev);

	//read lane order from device tree
	if (priv->linktype != E_LINK_NONE) {
		UBOOT_DEBUG("[%s] User defined lane order = %d\n", __func__, priv->lane_info.usr_defined);

		if (priv->lane_info.usr_defined == 1)
			_usr_def_free_swap_v007(dev);
		else
			_default_free_swap_v007(dev);

	}
#if 0// HAPS v007 no need
	//polarity , ti mode
	W2BYTEMSK(REG_00E0_MODD1_V007, 0x2800, Fld(16, 0, AC_FULLW10));

	//free swap for a/b swap
	W2BYTEMSK(REG_0040_MODD1_V007, 0x0706, Fld(16, 0, AC_FULLW10));
	W2BYTEMSK(REG_0044_MODD1_V007, 0x0908, Fld(16, 0, AC_FULLW10));
	W2BYTEMSK(REG_0048_MODD1_V007, 0x0B0A, Fld(16, 0, AC_FULLW10));
	W2BYTEMSK(REG_004C_MODD1_V007, 0x0100, Fld(16, 0, AC_FULLW10));
	W2BYTEMSK(REG_0050_MODD1_V007, 0x0302, Fld(16, 0, AC_FULLW10));
	W2BYTEMSK(REG_0054_MODD1_V007, 0x0504, Fld(16, 0, AC_FULLW10));
#endif

}

int mtk_out_if_init_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	//uint8_t PortIdx = 0; //eDP usage

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}
	//clk setting
	//TODO : EDP
	if (priv->linktype == E_LINK_VB1) {
		switch (priv->out_timing) {

		case E_FHD_60HZ:
			_vby1_v_fhd_60HZ_v007(dev);
			break;
		case E_FHD_120HZ:
			_vby1_v_fhd_120HZ_v007(dev);
			break;
		case E_FHD_240HZ:
			_vby1_v_fhd_240HZ_v007(dev);
			break;
		case E_4K2K_30HZ:
			_vby1_v_4k_30HZ_v007(dev);
			break;
		case E_4K2K_60HZ:
		case E_4K1K_120HZ:
			_vby1_v_4k_60HZ_v007(dev);
			break;
		case E_4K2K_120HZ:
		case E_4K1K_240HZ:
		case E_4K2K_144HZ:
		case E_4K1K_288HZ:
		case E_4K2K_165HZ:
		case E_4K1K_330HZ:
		case E_5K2K_60HZ:
			_vby1_v_4k_120HZ_v007(dev);
			break;
		default:
			UBOOT_DEBUG("Video OUTPUT TIMING Not Support\n");
			return -EINVAL;
			break;
		}

		//ToDo:Add Fixed H-backporch code.
		//VBY1 byte-mode
		_vby1_set_byte_mode_v007(dev);
	}

	if (priv->linktype == E_LINK_LVDS) {
		switch (priv->out_timing) {
		case E_HD_60HZ:
			_lvds_v_hd_60HZ_v007(dev);
		break;
		case E_HD_120HZ:
			_lvds_v_hd_120HZ_v007(dev);
		break;
		case E_FHD_60HZ:
			_lvds_v_fhd_60HZ_v007(dev);
		break;
		default:
			UBOOT_DEBUG("Video OUTPUT TIMING Not Support\n");
			return -EINVAL;
		break;
		}
	}
	if (IS_EDP_OUT(priv->linktype)) {
		_edp_v_common_timing_v007(dev);
		mtk_edp_parameter_parse(dev);
		mtk_edp_poweron_all();
	}
	_vby1_set_mft_v007(dev);
	_vby1_set_SCTCON_MISC_v007(dev);

	//h/v sync polarity
	W2BYTEMSK(REG_0004_MODV12_V007, priv->hsync_pol, REG_0004_MODV12_V007_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12_V007, priv->vsync_pol, REG_0004_MODV12_V007_REG_VBY1_VS_INV);

	_vby1_seri_data_sel_v007(dev);

	//lane order setting
	_vby1_lane_order_v007(dev);

	//fifo reset (video path)
	W2BYTEMSK(REG_0150_MODD1_V007, 0x1, REG_0150_MODD1_V007_REG_V1_SW_FORCE_FIX_TRIG);
	W2BYTEMSK(REG_0150_MODD1_V007, 0x0, REG_0150_MODD1_V007_REG_V1_SW_FORCE_FIX_TRIG);

#if 0 //V007 haps no need
	UBOOT_DEBUG("!!!! HAPS case !!!!!!\n");
	_hfrc_setting_for_HAPS_v007();
#endif

	return 0;
}

static void _efuse_set_biascon_offset_v007(struct udevice *dev, u32 value, u32 value1, u32 value2)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	bool biascon_offset_en = false;
	u32 cal_value = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	// hw support or not
	if ((value2 & _BIT(MOD_CUR_DOUBLE_ACT_BIT_V007)) == _BIT(MOD_CUR_DOUBLE_ACT_BIT_V007))
		biascon_offset_en = true;
	else
		biascon_offset_en = false;

	//write reg
	if (biascon_offset_en) {
		cal_value = (value >> 14) & 0xf;
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH00);
		cal_value = (value >> 18) & 0xf;
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH01);
		cal_value = (value >> 22) & 0xf;
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH02);
		cal_value = (value >> 26) & 0xf;
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH03);
		cal_value = (value1 >> 0) & 0xf;
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH04);
		cal_value = (value1 >> 4) & 0xf;
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH05);
		cal_value = (value1 >> 8) & 0xf;
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH06);
		cal_value = (value1 >> 12) & 0xf;
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH07);
		cal_value = (value1 >> 16) & 0xf;
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH08);
		cal_value = (value1 >> 20) & 0xf;
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH09);
		cal_value = (value1 >> 24) & 0xf;
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH10);
		cal_value = (value1 >> 28) & 0xf;
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH11);
		cal_value = (value2 >> 0) & 0xf;
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH12);
		cal_value = (value2 >> 4) & 0xf;
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH13);
		cal_value = (value2 >> 8) & 0xf;
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH14);
		cal_value = (value2 >> 12) & 0xf;
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH15);
	} else {
		cal_value = 0;
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH00);
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH01);
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH02);
		W2BYTEMSK(REG_0110_MODA2_V007, cal_value, REG_0110_MODA2_V007_REG_BIAS_CON_OFFSET_CH03);
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH04);
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH05);
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH06);
		W2BYTEMSK(REG_0114_MODA2_V007, cal_value, REG_0114_MODA2_V007_REG_BIAS_CON_OFFSET_CH07);
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH08);
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH09);
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH10);
		W2BYTEMSK(REG_0118_MODA2_V007, cal_value, REG_0118_MODA2_V007_REG_BIAS_CON_OFFSET_CH11);
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH12);
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH13);
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH14);
		W2BYTEMSK(REG_011C_MODA2_V007, cal_value, REG_011C_MODA2_V007_REG_BIAS_CON_OFFSET_CH15);
	}
}

static void _efuse_set_rcon_v007(struct udevice *dev, uint32_t value)
{
	u16 rcon_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	bool rcon_en = 0;
	u32 rcon_max = 0;
	u32 rcon_min = 0;
	u32 rcon_default_value = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	rcon_en = priv->hw_info.rcon_enable;
	rcon_max = priv->hw_info.rcon_max;
	rcon_min = priv->hw_info.rcon_min;
	rcon_default_value = priv->hw_info.rcon_value;

	//check act bit is enabled
	if (value & _BIT(MOD_VOL_VX1_ACT_BIT_V007)) {

		rcon_val = value & 0x3F; //bit[5:0]

		UBOOT_DEBUG("rcon value read from efuse is %d\n", rcon_val);

		//check if out of boundary
		if (rcon_en) {
			if (rcon_val > rcon_max || rcon_val < rcon_min)
				rcon_val = rcon_default_value;
		} else {
			rcon_val = rcon_default_value;
		}
	} else {
		rcon_val = rcon_default_value;
		UBOOT_DEBUG("RCON act value is set to default value [%d]\n", RCON_DEF_VAL);
	}

	W2BYTEMSK(REG_00C0_MODA2_V007, rcon_val, REG_00C0_MODA2_V007_REG_RCON_CH00);
	W2BYTEMSK(REG_00C0_MODA2_V007, rcon_val, REG_00C0_MODA2_V007_REG_RCON_CH01);
	W2BYTEMSK(REG_00C4_MODA2_V007, rcon_val, REG_00C4_MODA2_V007_REG_RCON_CH02);
	W2BYTEMSK(REG_00C4_MODA2_V007, rcon_val, REG_00C4_MODA2_V007_REG_RCON_CH03);
	W2BYTEMSK(REG_00C8_MODA2_V007, rcon_val, REG_00C8_MODA2_V007_REG_RCON_CH04);
	W2BYTEMSK(REG_00C8_MODA2_V007, rcon_val, REG_00C8_MODA2_V007_REG_RCON_CH05);
	W2BYTEMSK(REG_00CC_MODA2_V007, rcon_val, REG_00CC_MODA2_V007_REG_RCON_CH06);
	W2BYTEMSK(REG_00CC_MODA2_V007, rcon_val, REG_00CC_MODA2_V007_REG_RCON_CH07);
	W2BYTEMSK(REG_00D0_MODA2_V007, rcon_val, REG_00D0_MODA2_V007_REG_RCON_CH08);
	W2BYTEMSK(REG_00D0_MODA2_V007, rcon_val, REG_00D0_MODA2_V007_REG_RCON_CH09);
	W2BYTEMSK(REG_00D4_MODA2_V007, rcon_val, REG_00D4_MODA2_V007_REG_RCON_CH10);
	W2BYTEMSK(REG_00D4_MODA2_V007, rcon_val, REG_00D4_MODA2_V007_REG_RCON_CH11);
	W2BYTEMSK(REG_00D8_MODA2_V007, rcon_val, REG_00D8_MODA2_V007_REG_RCON_CH12);
	W2BYTEMSK(REG_00D8_MODA2_V007, rcon_val, REG_00D8_MODA2_V007_REG_RCON_CH13);
	W2BYTEMSK(REG_00DC_MODA2_V007, rcon_val, REG_00DC_MODA2_V007_REG_RCON_CH14);
	W2BYTEMSK(REG_00DC_MODA2_V007, rcon_val, REG_00DC_MODA2_V007_REG_RCON_CH15);
}

static void _efuse_set_biascon_v007(struct udevice *dev, uint32_t value, uint32_t value1,
				    uint32_t value2)
{
	//for vby1 case, default read double term

	bool bSingleterm = false;
	//uint16_t SingleActBitPosition = 0;
	//uint16_t SingleBiasConMask = 0;
	uint16_t DoubleActBitPosition = 0;
	//uint16_t DoubleBiasConMask = 0;
	uint16_t cur_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	//uint32_t bias_single_max = 0;
	//uint32_t bias_single_min = 0;
	//uint32_t bias_single_default_val = 0;
	uint32_t bias_double_max = 0;
	uint32_t bias_double_min = 0;
	uint32_t bias_double_default_val = 0;
	bool efuseActive = false;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	//bias_single_max = priv->hw_info.biascon_single_max;
	//bias_single_min = priv->hw_info.biascon_single_min;
	//bias_single_default_val = priv->hw_info.biascon_single_value;

	bias_double_max = priv->hw_info.biascon_double_max;
	bias_double_min = priv->hw_info.biascon_double_min;
	bias_double_default_val = priv->hw_info.biascon_double_value;

	bSingleterm = false;

	UBOOT_DEBUG("Current mode is %s\n", bSingleterm ? "Single Term" : "Double Term");

	DoubleActBitPosition = MOD_CUR_DOUBLE_ACT_BIT_V007;	//sub 66 bit[16]
	//DoubleBiasConMask = MOD_CUR_DOUBLE_MASK_VER5;
	if ((value2 & _BIT(DoubleActBitPosition)) == _BIT(DoubleActBitPosition))
		efuseActive = true;
	else
		efuseActive = false;

	UBOOT_DEBUG("Active=%d BitPosition=%d bias_max=%d bias_min=%d bias_default=%d\n",
		    efuseActive, DoubleActBitPosition, bias_double_max, bias_double_min,
		    bias_double_default_val);

	if (efuseActive) {
		cur_val = (value >> MOD_CUR_DOUBLE_LSB_V007) & MOD_CUR_DOUBLE_MASK_V007;	//sub 64 bit[13:7]
		UBOOT_DEBUG("Dump double term biasCon = %d from efuse\n", cur_val);
		if (cur_val > bias_double_max || cur_val < bias_double_min)
			cur_val = bias_double_default_val;
	} else {
		cur_val = bias_double_default_val;
		UBOOT_DEBUG("MOD CUR DOUBLE ACT is 0, set default value\n");
	}

	W2BYTEMSK(REG_0010_MODA1_V007, cur_val, REG_0010_MODA1_V007_REG_GCR_BIAS_CON);

	//set biascon offset
	_efuse_set_biascon_offset_v007(dev, value, value1, value2);
}

void mtk_dump_mod_efuse_v007(struct udevice *dev)
{
	u32 efuse_sub64_val = 0;
	u32 efuse_sub65_val = 0;
	u32 efuse_sub66_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	efuse_sub64_val = _mtk_get_efuse_val_v007(priv->pnl_lib_version, MOD_ATOP_SUBBANK_64);
	//sub bank 13
	efuse_sub65_val = _mtk_get_efuse_val_v007(priv->pnl_lib_version, MOD_ATOP_SUBBANK_65);
	//sub bank 14
	efuse_sub66_val = _mtk_get_efuse_val_v007(priv->pnl_lib_version, MOD_ATOP_SUBBANK_66);

	UBOOT_DEBUG("Efuse value 64 = 0x%x\n", efuse_sub64_val);
	UBOOT_DEBUG("Efuse value 65 = 0x%x\n", efuse_sub65_val);
	UBOOT_DEBUG("Efuse value 66 = 0x%x\n", efuse_sub66_val);

	//dump setting from efuse
	_efuse_set_rcon_v007(dev, efuse_sub64_val);
	_efuse_set_biascon_v007(dev, efuse_sub64_val, efuse_sub65_val, efuse_sub66_val);
}

static void _mtk_dither_depth_setting_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}
	if (priv->dither_info.dither_capability == 0)	//input 10bit case
		switch (priv->dither_info.dither_depth) {
		case E_DITHER_DEPTH_6:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);	//dither 4 bit (10to6 case)
			break;
		case E_DITHER_DEPTH_8:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);	//dither 2 bit (10to8 case)
			break;
		case E_DITHER_DEPTH_10:
			//means by pass(10to10 case)
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			break;
		case E_DITHER_DEPTH_12:
		default:
			// To avoid dither pattern works in not support case, force bypass mode
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			debug("[%s] dither depth not support\n", __func__);
			break;
	} else if (priv->dither_info.dither_capability == 1) {	//input 12bit case
		switch (priv->dither_info.dither_depth) {
		case E_DITHER_DEPTH_6:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);	//dither 4 bit (12to6 case)
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0,
				  REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		case E_DITHER_DEPTH_8:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);	//dither 4 bit (12to8 case)
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1,
				  REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		case E_DITHER_DEPTH_10:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);	//dither 2 bit (12to10 case)
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1,
				  REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		case E_DITHER_DEPTH_12:
			//means by pass(12to12 case)
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			break;
		default:
			// To avoid dither pattern works in not support case, force bypass mode
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			debug("[%s] dither depth not support\n", __func__);
			break;
		}

	} else {
		debug("[%s] dither capability not support\n", __func__);
	}

}

static void _mtk_dither_12bit_setting_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_BOOST_EN);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_DITHER_BIT_1);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_LSB_ALIGNMENT_SEL);

	if ((priv->dither_info.dither_depth == E_DITHER_DEPTH_12)
	    || (priv->dither_info.dither_pattern == E_DITHER_BYPASS)) {
		W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_BYPASS_MODE);
	} else {
		W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_BYPASS_MODE);
	}

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_13B);

	W2BYTEMSK(REG_012C_PAFRC_BKA324, 0x0, REG_012C_PAFRC_BKA324_REG_13B_CLAMP_MODE);

}

static void _mtk_dither_common_setting_v007(void)
{
	//setting here means different dither pattern use the same setting

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_POL_TYPE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_G_V_SWAP);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_G_H_SWAP);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_B_D_SWAP);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FR_SW);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX4X4_FR_SW);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX8X8_ROT_UNIT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_ROTATE_EN);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_TOP_BOX_UNIT_FLAG);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_SHRINK);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_FR_C2_BIT);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_C2X2_ROT_B_DIR_S);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_D2X2_ROT_B_DIR_S);

	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_A2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_B2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_R_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_R_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_A2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_B2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_G_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_G_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_A2X2_ROT_B_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_B2X2_ROT_B_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_B_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_B_DIR);

	W2BYTEMSK(REG_0108_PAFRC_BKA324, 0x9c, REG_0108_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ1);
	W2BYTEMSK(REG_0108_PAFRC_BKA324, 0xc9, REG_0108_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ2);

	W2BYTEMSK(REG_010C_PAFRC_BKA324, 0x9c, REG_010C_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ3);
	W2BYTEMSK(REG_010C_PAFRC_BKA324, 0xc9, REG_010C_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ4);

	W2BYTEMSK(REG_0110_PAFRC_BKA324, 0xaa, REG_0110_PAFRC_BKA324_REG_TOP_BOX_FR_C2_SEQ12);
	W2BYTEMSK(REG_0110_PAFRC_BKA324, 0xaa, REG_0110_PAFRC_BKA324_REG_TOP_BOX_FR_C2_SEQ34);

	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_00);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x2, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_01);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_10);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x2, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_11);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX_A_ROT_DIR);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x1, REG_0114_PAFRC_BKA324_REG_BOX_B_ROT_DIR);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX_C_ROT_DIR);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x1, REG_0114_PAFRC_BKA324_REG_BOX_D_ROT_DIR);
}

static void _mtk_dither_entity_same_setting_v007(void)
{
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_LD_10);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_LD_10);

	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_LD_10);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_LD_10);

	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_LD_10_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_LD_10_S);

	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_LD_10);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_LD_10);

	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_LD_10);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_LD_10);
}

static void _mtk_dither_bypass_setting_v007(void)
{

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting_v007();
	_mtk_dither_entity_same_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_FRC_ON);

}

static void _mtk_dither_truncate_setting_v007(void)
{

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);	//only diff with bypass

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting_v007();
	_mtk_dither_entity_same_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_round_setting_v007(void)
{

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting_v007();
	_mtk_dither_entity_same_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);	//only diff with truncate

}


static void _mtk_dither_entity_diff_setting_v007(void)
{
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x3, REG_0118_PAFRC_BKA324_REG_A_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x1, REG_0118_PAFRC_BKA324_REG_A_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x0, REG_0118_PAFRC_BKA324_REG_A_LD_10);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x3, REG_0118_PAFRC_BKA324_REG_B_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x1, REG_0118_PAFRC_BKA324_REG_B_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x0, REG_0118_PAFRC_BKA324_REG_B_LD_10);

	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x1, REG_011C_PAFRC_BKA324_REG_C_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x3, REG_011C_PAFRC_BKA324_REG_C_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x0, REG_011C_PAFRC_BKA324_REG_C_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_LD_10);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x1, REG_011C_PAFRC_BKA324_REG_D_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x3, REG_011C_PAFRC_BKA324_REG_D_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x0, REG_011C_PAFRC_BKA324_REG_D_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_LD_10);

	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x0, REG_0120_PAFRC_BKA324_REG_C_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x3, REG_0120_PAFRC_BKA324_REG_C_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x1, REG_0120_PAFRC_BKA324_REG_C_LD_10_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x0, REG_0120_PAFRC_BKA324_REG_D_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x3, REG_0120_PAFRC_BKA324_REG_D_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x1, REG_0120_PAFRC_BKA324_REG_D_LD_10_S);

	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x3, REG_0124_PAFRC_BKA324_REG_BOX_A_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x1, REG_0124_PAFRC_BKA324_REG_BOX_A_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x0, REG_0124_PAFRC_BKA324_REG_BOX_A_LD_10);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x0, REG_0124_PAFRC_BKA324_REG_BOX_B_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x1, REG_0124_PAFRC_BKA324_REG_BOX_B_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x3, REG_0124_PAFRC_BKA324_REG_BOX_B_LD_10);

	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x0, REG_0128_PAFRC_BKA324_REG_BOX_C_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x3, REG_0128_PAFRC_BKA324_REG_BOX_C_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x1, REG_0128_PAFRC_BKA324_REG_BOX_C_LD_10);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x1, REG_0128_PAFRC_BKA324_REG_BOX_D_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x3, REG_0128_PAFRC_BKA324_REG_BOX_D_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x0, REG_0128_PAFRC_BKA324_REG_BOX_D_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_LD_10);


}

static void _mtk_dither_random_static_setting_v007(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting_v007();
	_mtk_dither_entity_diff_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_random_dynamic_setting_v007(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);	//diff with random static

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);	//diff with random static

	_mtk_dither_common_setting_v007();

	_mtk_dither_entity_diff_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_pattern_table_static_setting_v007(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);	//diff with random
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting_v007();
	_mtk_dither_entity_diff_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_pattern_table_dynamic_setting_v007(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);	//diff with random
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);	//diff with random static

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);	//diff with random static
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_SHRINK);
	_mtk_dither_common_setting_v007();
	_mtk_dither_entity_diff_setting_v007();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);
}

void mtk_dither_setting_v007(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	_mtk_dither_depth_setting_v007(dev);

	if (priv->dither_info.dither_capability == 1) {
		_mtk_dither_12bit_setting_v007(dev);
	}

	switch (priv->dither_info.dither_pattern) {
	case E_DITHER_BYPASS:
		_mtk_dither_bypass_setting_v007();
		break;
	case E_DITHER_TRUNCATION:
		_mtk_dither_truncate_setting_v007();
		break;
	case E_DITHER_ROUND:
		_mtk_dither_round_setting_v007();
		break;
	case E_DITHER_PATTERN_TABLE_DYNAMIC:
		_mtk_dither_pattern_table_dynamic_setting_v007();
		break;
	case E_DITHER_PATTERN_TABLE_STATIC:
		_mtk_dither_pattern_table_static_setting_v007();
		break;
	case E_DITHER_RANDOM_DYNAMIC:
		_mtk_dither_random_dynamic_setting_v007();
		break;
	case E_DITHER_RANDOM_STATIC:
		_mtk_dither_random_static_setting_v007();
		break;
	default:
		UBOOT_DEBUG("dither pattern fail\n");
		break;
	}
}

bool mtk_pnl_set_mod_block_pattern_enable_v007(bool en)
{
	W2BYTEMSK(REG_0004_TCON_VCOM_PAT_V005, (en << 0), REG_0004_TCON_VCOM_PAT_V005_REG_BLOCK_TEST_EN_0004);
	return true;
}

bool mtk_pnl_set_mod_block_pattern_table_v007(u16 *pixel_tbl, u32 table_size, bool is_epi)
{
	u16 vcom_tbl[table_size];
	u32 table_addr_1 = 0;
	u32 table_addr_2 = 0;
	u32 table_addr = 0;
	u16 table_temp[table_size];

	memset(vcom_tbl, 0, sizeof(u16) * table_size);
	if (!pixel_tbl)
		return false;

	memcpy(vcom_tbl, pixel_tbl, sizeof(u16) * table_size);
	memset(table_temp, 0, sizeof(u16) * table_size);
	memcpy(table_temp, pixel_tbl, sizeof(u16) * table_size);
	if (is_epi) {
		for (table_addr_1 = 0; table_addr_1 < table_size; table_addr_1++) {
			table_addr_2 = table_addr_1 + MOD_BLOCKPATTERN_TBL_LINE_SIZE_V007;
			while (table_addr_2 >= table_size)
				table_addr_2 = table_addr_2 - table_size;

			vcom_tbl[table_addr_2] = table_temp[table_addr_1];
		}
	}

	if (table_size == MOD_BLOCKPATTERN_TBL_MAX_SIZE_V007) {
		for (table_addr = 0; table_addr < table_size; table_addr++) {
			// reg_detect_table, masks are same so keep
			W2BYTEMSK(REG_0020_TCON_VCOM_PAT_V005 + table_addr * MOD_BLOCKPATTERN_ADDR_STEP,
			vcom_tbl[table_addr],
			REG_0020_TCON_VCOM_PAT_V005_REG_LINE0_SUBP00_0020);
		}
		return true;
	} else {
		return false;
	}
}

