/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define TOP_CKGEN01_V007 0x00206000

//Page TOP_CKGEN01_V007
#define REG_0000_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x000)
	#define REG_0000_CKGEN01_V007_REG_CKG_G_ADC2MIU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0000_CKGEN01_V007_REG_CKG_I_ADC2MIU Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0000_CKGEN01_V007_REG_CKG_S_ADC2MIU Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0008_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x008)
	#define REG_0008_CKGEN01_V007_REG_CKG_G_ADC2MIUSC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0008_CKGEN01_V007_REG_CKG_I_ADC2MIUSC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0008_CKGEN01_V007_REG_CKG_S_ADC2MIUSC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0010_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x010)
	#define REG_0010_CKGEN01_V007_REG_CKG_G_ADC2SC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0010_CKGEN01_V007_REG_CKG_I_ADC2SC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0010_CKGEN01_V007_REG_CKG_S_ADC2SC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0018_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x018)
	#define REG_0018_CKGEN01_V007_REG_CKG_G_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0018_CKGEN01_V007_REG_CKG_I_ADC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0018_CKGEN01_V007_REG_CKG_S_ADC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0020_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x020)
	#define REG_0020_CKGEN01_V007_REG_CKG_G_ADCPLL200 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0020_CKGEN01_V007_REG_CKG_I_ADCPLL200 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0028_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x028)
	#define REG_0028_CKGEN01_V007_REG_CKG_G_ADCPLL400 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0028_CKGEN01_V007_REG_CKG_I_ADCPLL400 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0030_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x030)
	#define REG_0030_CKGEN01_V007_REG_CKG_G_ADCPLLB_MPLL_216M Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0030_CKGEN01_V007_REG_CKG_I_ADCPLLB_MPLL_216M Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0038_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x038)
	#define REG_0038_CKGEN01_V007_REG_CKG_G_B_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0038_CKGEN01_V007_REG_CKG_I_B_ADC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0038_CKGEN01_V007_REG_CKG_S_B_ADC Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0040_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x040)
	#define REG_0040_CKGEN01_V007_REG_CKG_G_B_INT Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0040_CKGEN01_V007_REG_CKG_I_B_INT Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0040_CKGEN01_V007_REG_CKG_S_B_INT Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0058_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x058)
	#define REG_0058_CKGEN01_V007_REG_CKG_G_CLKD_ADC_P Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0058_CKGEN01_V007_REG_CKG_I_CLKD_ADC_P Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0058_CKGEN01_V007_REG_CKG_S_CLKD_ADC_P Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_005C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x05C)
	#define REG_005C_CKGEN01_V007_REG_CKG_G_MSDCPLL_SYN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_005C_CKGEN01_V007_REG_CKG_I_MSDCPLL_SYN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_005C_CKGEN01_V007_REG_CKG_S_MSDCPLL_SYN Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0060_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x060)
	#define REG_0060_CKGEN01_V007_REG_CKG_G_CLKD_ATOP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0060_CKGEN01_V007_REG_CKG_I_CLKD_ATOP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0060_CKGEN01_V007_REG_CKG_S_CLKD_ATOP Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0064_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x064)
	#define REG_0064_CKGEN01_V007_REG_SW_EN_MSDCPLL_SYN2MSDCPLL Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0068_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x068)
	#define REG_0068_CKGEN01_V007_REG_CKG_G_CLKD_ATOP_INTERNAL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0068_CKGEN01_V007_REG_CKG_I_CLKD_ATOP_INTERNAL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0068_CKGEN01_V007_REG_CKG_S_CLKD_ATOP_INTERNAL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_006C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x06C)
	#define REG_006C_CKGEN01_V007_REG_MSDCPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_006C_CKGEN01_V007_REG_MSDCPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_006C_CKGEN01_V007_REG_MSDCPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0070_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x070)
	#define REG_0070_CKGEN01_V007_REG_CKG_G_CLKPLL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0070_CKGEN01_V007_REG_CKG_I_CLKPLL Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0074_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x074)
	#define REG_0074_CKGEN01_V007_REG_MSDCPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0078_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x078)
	#define REG_0078_CKGEN01_V007_REG_CKG_G_CVBS_DAC_A_DIGITAL0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0078_CKGEN01_V007_REG_CKG_I_CVBS_DAC_A_DIGITAL0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0078_CKGEN01_V007_REG_CKG_S_CVBS_DAC_A_DIGITAL0 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_007C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x07C)
	#define REG_007C_CKGEN01_V007_REG_MSDCPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0080_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x080)
	#define REG_0080_CKGEN01_V007_REG_CKG_G_CVBS_DAC_A_DIGITAL0_MUX Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0080_CKGEN01_V007_REG_CKG_I_CVBS_DAC_A_DIGITAL0_MUX Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0080_CKGEN01_V007_REG_CKG_S_CVBS_DAC_A_DIGITAL0_MUX Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0088_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x088)
	#define REG_0088_CKGEN01_V007_REG_CKG_G_CVBS_DAC_A_DIGITAL1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0088_CKGEN01_V007_REG_CKG_I_CVBS_DAC_A_DIGITAL1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0088_CKGEN01_V007_REG_CKG_S_CVBS_DAC_A_DIGITAL1 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0090_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x090)
	#define REG_0090_CKGEN01_V007_REG_CKG_G_DIG_108 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0090_CKGEN01_V007_REG_CKG_I_DIG_108 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0098_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x098)
	#define REG_0098_CKGEN01_V007_REG_CKG_G_DIG_216 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0098_CKGEN01_V007_REG_CKG_I_DIG_216 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0A0)
	#define REG_00A0_CKGEN01_V007_REG_CKG_G_FBLANK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A0_CKGEN01_V007_REG_CKG_I_FBLANK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00A0_CKGEN01_V007_REG_CKG_S_FBLANK Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_00A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0A8)
	#define REG_00A8_CKGEN01_V007_REG_CKG_G_FSC_VD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A8_CKGEN01_V007_REG_CKG_I_FSC_VD Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0B0)
	#define REG_00B0_CKGEN01_V007_REG_CKG_G_FSCX2_FB2ATOP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00B0_CKGEN01_V007_REG_CKG_I_FSCX2_FB2ATOP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00B0_CKGEN01_V007_REG_CKG_S_FSCX2_FB2ATOP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_00B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0B8)
	#define REG_00B8_CKGEN01_V007_REG_CKG_G_G_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00B8_CKGEN01_V007_REG_CKG_I_G_ADC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00B8_CKGEN01_V007_REG_CKG_S_G_ADC Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_00C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0C0)
	#define REG_00C0_CKGEN01_V007_REG_CKG_G_G_INT Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00C0_CKGEN01_V007_REG_CKG_I_G_INT Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00C0_CKGEN01_V007_REG_CKG_S_G_INT Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_00C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0C4)
	#define REG_00C4_CKGEN01_V007_REG_CKG_G_V1_DET_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00C4_CKGEN01_V007_REG_CKG_I_V1_DET_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00C4_CKGEN01_V007_REG_CKG_S_V1_DET_ODCLK Fld(5, 2, AC_MSKB0)//[6:2]
#define REG_00C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0C8)
	#define REG_00C8_CKGEN01_V007_REG_CKG_G_ICLAMP_RGB Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00C8_CKGEN01_V007_REG_CKG_I_ICLAMP_RGB Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00C8_CKGEN01_V007_REG_CKG_S_ICLAMP_RGB Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_00D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0D0)
	#define REG_00D0_CKGEN01_V007_REG_CKG_G_ISOG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00D0_CKGEN01_V007_REG_CKG_I_ISOG Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0E0)
	#define REG_00E0_CKGEN01_V007_REG_CKG_G_NCO_CLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00E0_CKGEN01_V007_REG_CKG_I_NCO_CLK Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0EC)
	#define REG_00EC_CKGEN01_V007_REG_XCBPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00EC_CKGEN01_V007_REG_XCBPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00EC_CKGEN01_V007_REG_XCBPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0F0)
	#define REG_00F0_CKGEN01_V007_REG_CKG_G_R_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00F0_CKGEN01_V007_REG_CKG_I_R_ADC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00F0_CKGEN01_V007_REG_CKG_S_R_ADC Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_00F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0F4)
	#define REG_00F4_CKGEN01_V007_REG_XCBPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_00F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0F8)
	#define REG_00F8_CKGEN01_V007_REG_CKG_G_R_INT Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00F8_CKGEN01_V007_REG_CKG_I_R_INT Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00F8_CKGEN01_V007_REG_CKG_S_R_INT Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_00FC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x0FC)
	#define REG_00FC_CKGEN01_V007_REG_XCBPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0108_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x108)
	#define REG_0108_CKGEN01_V007_REG_CKG_G_VD_ICLAMP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0108_CKGEN01_V007_REG_CKG_I_VD_ICLAMP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0110_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x110)
	#define REG_0110_CKGEN01_V007_REG_CKG_G_VD_ADCPLL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0110_CKGEN01_V007_REG_CKG_I_VD_ADCPLL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0110_CKGEN01_V007_REG_CKG_S_VD_ADCPLL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0118_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x118)
	#define REG_0118_CKGEN01_V007_REG_CKG_G_VD_NCO_CLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0118_CKGEN01_V007_REG_CKG_I_VD_NCO_CLK Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0120_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x120)
	#define REG_0120_CKGEN01_V007_REG_CKG_G_VDPLL400 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0120_CKGEN01_V007_REG_CKG_I_VDPLL400 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0128_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x128)
	#define REG_0128_CKGEN01_V007_REG_CKG_G_XTAL12_4INTERRUPT Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0128_CKGEN01_V007_REG_CKG_I_XTAL12_4INTERRUPT Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0130_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x130)
	#define REG_0130_CKGEN01_V007_REG_CKG_G_XTAL12_4PLUGDET Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0130_CKGEN01_V007_REG_CKG_I_XTAL12_4PLUGDET Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0138_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x138)
	#define REG_0138_CKGEN01_V007_REG_CKG_G_XTAL12 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0138_CKGEN01_V007_REG_CKG_I_XTAL12 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0140_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x140)
	#define REG_0140_CKGEN01_V007_REG_CKG_G_XTAL24 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0140_CKGEN01_V007_REG_CKG_I_XTAL24 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0148_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x148)
	#define REG_0148_CKGEN01_V007_REG_CKG_G_Y_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0148_CKGEN01_V007_REG_CKG_I_Y_ADC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0148_CKGEN01_V007_REG_CKG_S_Y_ADC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0150_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x150)
	#define REG_0150_CKGEN01_V007_REG_CKG_G_Y_INT Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0150_CKGEN01_V007_REG_CKG_I_Y_INT Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0150_CKGEN01_V007_REG_CKG_S_Y_INT Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0158_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x158)
	#define REG_0158_CKGEN01_V007_REG_CKG_G_YUV_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0158_CKGEN01_V007_REG_CKG_I_YUV_ADC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0158_CKGEN01_V007_REG_CKG_S_YUV_ADC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0168_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x168)
	#define REG_0168_CKGEN01_V007_REG_CKG_G_GPO_00 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0168_CKGEN01_V007_REG_CKG_I_GPO_00 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0168_CKGEN01_V007_REG_CKG_S_GPO_00 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0168_CKGEN01_V007_REG_CKG_G_GPO_01 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0168_CKGEN01_V007_REG_CKG_I_GPO_01 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0168_CKGEN01_V007_REG_CKG_S_GPO_01 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0168_CKGEN01_V007_REG_CKG_G_GPO_02 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0168_CKGEN01_V007_REG_CKG_I_GPO_02 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0168_CKGEN01_V007_REG_CKG_S_GPO_02 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0168_CKGEN01_V007_REG_CKG_G_GPO_03 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0168_CKGEN01_V007_REG_CKG_I_GPO_03 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0168_CKGEN01_V007_REG_CKG_S_GPO_03 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0170_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x170)
	#define REG_0170_CKGEN01_V007_REG_CKG_G_GPO_04 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0170_CKGEN01_V007_REG_CKG_I_GPO_04 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0170_CKGEN01_V007_REG_CKG_S_GPO_04 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0170_CKGEN01_V007_REG_CKG_G_GPO_05 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0170_CKGEN01_V007_REG_CKG_I_GPO_05 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0170_CKGEN01_V007_REG_CKG_S_GPO_05 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0170_CKGEN01_V007_REG_CKG_G_GPO_06 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0170_CKGEN01_V007_REG_CKG_I_GPO_06 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0170_CKGEN01_V007_REG_CKG_S_GPO_06 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0170_CKGEN01_V007_REG_CKG_G_GPO_07 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0170_CKGEN01_V007_REG_CKG_I_GPO_07 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0170_CKGEN01_V007_REG_CKG_S_GPO_07 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0178_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x178)
	#define REG_0178_CKGEN01_V007_REG_CKG_G_GPO_08 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0178_CKGEN01_V007_REG_CKG_I_GPO_08 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0178_CKGEN01_V007_REG_CKG_S_GPO_08 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0178_CKGEN01_V007_REG_CKG_G_GPO_09 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0178_CKGEN01_V007_REG_CKG_I_GPO_09 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0178_CKGEN01_V007_REG_CKG_S_GPO_09 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0178_CKGEN01_V007_REG_CKG_G_GPO_10 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0178_CKGEN01_V007_REG_CKG_I_GPO_10 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0178_CKGEN01_V007_REG_CKG_S_GPO_10 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0178_CKGEN01_V007_REG_CKG_G_GPO_11 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0178_CKGEN01_V007_REG_CKG_I_GPO_11 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0178_CKGEN01_V007_REG_CKG_S_GPO_11 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0180_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x180)
	#define REG_0180_CKGEN01_V007_REG_CKG_G_GPO_12 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0180_CKGEN01_V007_REG_CKG_I_GPO_12 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0180_CKGEN01_V007_REG_CKG_S_GPO_12 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0180_CKGEN01_V007_REG_CKG_G_GPO_13 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0180_CKGEN01_V007_REG_CKG_I_GPO_13 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0180_CKGEN01_V007_REG_CKG_S_GPO_13 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0180_CKGEN01_V007_REG_CKG_G_GPO_14 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0180_CKGEN01_V007_REG_CKG_I_GPO_14 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0180_CKGEN01_V007_REG_CKG_S_GPO_14 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0180_CKGEN01_V007_REG_CKG_G_GPO_15 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0180_CKGEN01_V007_REG_CKG_I_GPO_15 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0180_CKGEN01_V007_REG_CKG_S_GPO_15 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0188_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x188)
	#define REG_0188_CKGEN01_V007_REG_CKG_G_GPO_16 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0188_CKGEN01_V007_REG_CKG_I_GPO_16 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0188_CKGEN01_V007_REG_CKG_S_GPO_16 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0188_CKGEN01_V007_REG_CKG_G_GPO_17 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0188_CKGEN01_V007_REG_CKG_I_GPO_17 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0188_CKGEN01_V007_REG_CKG_S_GPO_17 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0188_CKGEN01_V007_REG_CKG_G_GPO_18 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0188_CKGEN01_V007_REG_CKG_I_GPO_18 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0188_CKGEN01_V007_REG_CKG_S_GPO_18 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0188_CKGEN01_V007_REG_CKG_G_GPO_19 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0188_CKGEN01_V007_REG_CKG_I_GPO_19 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0188_CKGEN01_V007_REG_CKG_S_GPO_19 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0190_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x190)
	#define REG_0190_CKGEN01_V007_REG_CKG_G_GPO_20 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0190_CKGEN01_V007_REG_CKG_I_GPO_20 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0190_CKGEN01_V007_REG_CKG_S_GPO_20 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0190_CKGEN01_V007_REG_CKG_G_GPO_21 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0190_CKGEN01_V007_REG_CKG_I_GPO_21 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0190_CKGEN01_V007_REG_CKG_S_GPO_21 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0190_CKGEN01_V007_REG_CKG_G_GPO_22 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0190_CKGEN01_V007_REG_CKG_I_GPO_22 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0190_CKGEN01_V007_REG_CKG_S_GPO_22 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0190_CKGEN01_V007_REG_CKG_G_GPO_23 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0190_CKGEN01_V007_REG_CKG_I_GPO_23 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0190_CKGEN01_V007_REG_CKG_S_GPO_23 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0198_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x198)
	#define REG_0198_CKGEN01_V007_REG_CKG_G_GPO_ZONE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0198_CKGEN01_V007_REG_CKG_I_GPO_ZONE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0198_CKGEN01_V007_REG_CKG_S_GPO_ZONE Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0198_CKGEN01_V007_REG_CKG_G_PWM_DAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0198_CKGEN01_V007_REG_CKG_I_PWM_DAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0198_CKGEN01_V007_REG_CKG_S_PWM_DAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0198_CKGEN01_V007_REG_CKG_S_GPO Fld(3, 8, AC_MSKB1)//[10:8]
#define REG_01C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C0)
	#define REG_01C0_CKGEN01_V007_REG_DSC_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01C0_CKGEN01_V007_REG_DSC_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_01C0_CKGEN01_V007_REG_DSC_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C4)
	#define REG_01C4_CKGEN01_V007_REG_DSC_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C8)
	#define REG_01C8_CKGEN01_V007_REG_DSC_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CC)
	#define REG_01CC_CKGEN01_V007_REG_CKG_G_XTAL_24_DSC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01CC_CKGEN01_V007_REG_CKG_I_XTAL_24_DSC Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_01D8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1D8)
	#define REG_01D8_CKGEN01_V007_REG_CKG_G_CLK_SRC0_DSC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01D8_CKGEN01_V007_REG_CKG_I_CLK_SRC0_DSC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01D8_CKGEN01_V007_REG_CKG_SRC0_DSC_USER_MD_DSC_CKGEN Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_01D8_CKGEN01_V007_REG_CKG_SRC0_DSC_USER_MD_EN_DSC_CKGEN Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_01DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DC)
	#define REG_01DC_CKGEN01_V007_REG_CKG_G_CLK_DST0_DSC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01DC_CKGEN01_V007_REG_CKG_I_CLK_DST0_DSC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01DC_CKGEN01_V007_REG_CKG_DST0_DSC_USER_MD_DSC_CKGEN Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_01DC_CKGEN01_V007_REG_CKG_DST0_DSC_USER_MD_EN_DSC_CKGEN Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_01E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E0)
	#define REG_01E0_CKGEN01_V007_REG_CKG_RV55AUDIO_DAP Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_01E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E4)
	#define REG_01E4_CKGEN01_V007_REG_CKG_G_CLK_DSC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01E4_CKGEN01_V007_REG_CKG_I_CLK_DSC Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_01E8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E8)
	#define REG_01E8_CKGEN01_V007_REG_CKG_G_FRC_FCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01E8_CKGEN01_V007_REG_CKG_I_FRC_FCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01E8_CKGEN01_V007_REG_CKG_S_FRC_FCLK Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_01EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EC)
	#define REG_01EC_CKGEN01_V007_REG_SW_EN_CLK_DST02DSC_DST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01EC_CKGEN01_V007_REG_SW_EN_CLK_SRC02DSC_SRC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01EC_CKGEN01_V007_REG_SW_EN_CLK_XTAL_242DSC_MBIST Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_01EC_CKGEN01_V007_REG_SW_EN_CLK_XTAL_242XTAL Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_01EC_CKGEN01_V007_REG_SW_EN_CLK_DSC02DSC Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_01F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F0)
	#define REG_01F0_CKGEN01_V007_REG_CKG_G_FRC_FCLK_2X Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01F0_CKGEN01_V007_REG_CKG_I_FRC_FCLK_2X Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01F0_CKGEN01_V007_REG_CKG_S_FRC_FCLK_2X Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_01F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F8)
	#define REG_01F8_CKGEN01_V007_REG_CKG_G_FRC_FCLK_2XPLUS Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01F8_CKGEN01_V007_REG_CKG_I_FRC_FCLK_2XPLUS Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01F8_CKGEN01_V007_REG_CKG_S_FRC_FCLK_2XPLUS Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0208_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x208)
	#define REG_0208_CKGEN01_V007_REG_CKG_RV55FRC Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0220_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x220)
	#define REG_0220_CKGEN01_V007_REG_CKG_RV55PQU Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_02A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2A0)
	#define REG_02A0_CKGEN01_V007_REG_CKG_G_GE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02A0_CKGEN01_V007_REG_CKG_I_GE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_02A0_CKGEN01_V007_REG_CKG_S_GE Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_02B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2B0)
	#define REG_02B0_CKGEN01_V007_REG_CKG_G_HDMI_R2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02B0_CKGEN01_V007_REG_CKG_I_HDMI_R2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_02B0_CKGEN01_V007_REG_CKG_S_HDMI_R2 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_02B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2B8)
	#define REG_02B8_CKGEN01_V007_REG_CKG_G_HDMIRX_TIMESTAMP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02B8_CKGEN01_V007_REG_CKG_I_HDMIRX_TIMESTAMP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_02C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2C4)
	#define REG_02C4_CKGEN01_V007_REG_CKG_G_RV_PQU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02C4_CKGEN01_V007_REG_CKG_I_RV_PQU Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_02C4_CKGEN01_V007_REG_CKG_S_RV_PQU Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_02DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2DC)
	#define REG_02DC_CKGEN01_V007_REG_CKG_G_TCK_PQU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02DC_CKGEN01_V007_REG_CKG_I_TCK_PQU Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_02E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2E4)
	#define REG_02E4_CKGEN01_V007_REG_SW_EN_RV_PQU2PQU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02E4_CKGEN01_V007_REG_SW_EN_RV_PQU2PQUDFS Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_02F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x2F4)
	#define REG_02F4_CKGEN01_V007_REG_SW_EN_AU_INFRA_RX2RV55HWDBG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_02F4_CKGEN01_V007_REG_SW_EN_TOP_INFRA_RX2RV55HWDBG Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0304_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x304)
	#define REG_0304_CKGEN01_V007_REG_CKG_G_AU_UART0_AURV55 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0304_CKGEN01_V007_REG_CKG_I_AU_UART0_AURV55 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_030C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x30C)
	#define REG_030C_CKGEN01_V007_REG_CKG_G_AU_UART1_AURV55 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_030C_CKGEN01_V007_REG_CKG_I_AU_UART1_AURV55 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0314_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x314)
	#define REG_0314_CKGEN01_V007_REG_CKG_G_AU_UART2_AURV55 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0314_CKGEN01_V007_REG_CKG_I_AU_UART2_AURV55 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_031C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x31C)
	#define REG_031C_CKGEN01_V007_REG_SW_EN_AU_UART02AU_UART0 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0324_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x324)
	#define REG_0324_CKGEN01_V007_REG_SW_EN_AU_UART12AU_UART1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_032C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x32C)
	#define REG_032C_CKGEN01_V007_REG_SW_EN_AU_UART22AU_UART2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_033C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x33C)
	#define REG_033C_CKGEN01_V007_REG_DP_TV_RX_MAC_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_033C_CKGEN01_V007_REG_DP_TV_RX_MAC_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_033C_CKGEN01_V007_REG_DP_TV_RX_MAC_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0344_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x344)
	#define REG_0344_CKGEN01_V007_REG_DP_TV_RX_MAC_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_034C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x34C)
	#define REG_034C_CKGEN01_V007_REG_DP_TV_RX_MAC_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0354_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x354)
	#define REG_0354_CKGEN01_V007_REG_XTAL_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0354_CKGEN01_V007_REG_XTAL_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_035C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x35C)
	#define REG_035C_CKGEN01_V007_REG_MCU_RECEIVER_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_035C_CKGEN01_V007_REG_MCU_RECEIVER_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0364_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x364)
	#define REG_0364_CKGEN01_V007_REG_DPRX_LS0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0364_CKGEN01_V007_REG_DPRX_LS0_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0364_CKGEN01_V007_REG_DPRX_LS0_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_036C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x36C)
	#define REG_036C_CKGEN01_V007_REG_DPRX_LS1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_036C_CKGEN01_V007_REG_DPRX_LS1_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_036C_CKGEN01_V007_REG_DPRX_LS1_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0374_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x374)
	#define REG_0374_CKGEN01_V007_REG_AUDIO_LS_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0374_CKGEN01_V007_REG_AUDIO_LS_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0374_CKGEN01_V007_REG_AUDIO_LS_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0378_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x378)
	#define REG_0378_CKGEN01_V007_REG_DSC_LS_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0378_CKGEN01_V007_REG_DSC_LS_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0378_CKGEN01_V007_REG_DSC_LS_P0_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_037C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x37C)
	#define REG_037C_CKGEN01_V007_REG_DSC_LS_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_037C_CKGEN01_V007_REG_DSC_LS_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_037C_CKGEN01_V007_REG_DSC_LS_P1_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0380_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x380)
	#define REG_0380_CKGEN01_V007_REG_FSYNC_ODCLK_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0380_CKGEN01_V007_REG_FSYNC_ODCLK_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0384_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x384)
	#define REG_0384_CKGEN01_V007_REG_FSYNC_ODCLK_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0384_CKGEN01_V007_REG_FSYNC_ODCLK_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0388_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x388)
	#define REG_0388_CKGEN01_V007_REG_PIX_4P_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0388_CKGEN01_V007_REG_PIX_4P_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_038C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x38C)
	#define REG_038C_CKGEN01_V007_REG_PIX_4P_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_038C_CKGEN01_V007_REG_PIX_4P_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0390_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x390)
	#define REG_0390_CKGEN01_V007_REG_AUDIO_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0390_CKGEN01_V007_REG_AUDIO_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0394_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x394)
	#define REG_0394_CKGEN01_V007_REG_I2S_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0394_CKGEN01_V007_REG_I2S_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0394_CKGEN01_V007_REG_I2S_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_039C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x39C)
	#define REG_039C_CKGEN01_V007_REG_FSYNC_IDCLK_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_039C_CKGEN01_V007_REG_FSYNC_IDCLK_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_039C_CKGEN01_V007_REG_FSYNC_IDCLK_P0_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_03A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3A4)
	#define REG_03A4_CKGEN01_V007_REG_FSYNC_IDCLK_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03A4_CKGEN01_V007_REG_FSYNC_IDCLK_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03A4_CKGEN01_V007_REG_FSYNC_IDCLK_P1_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_03AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3AC)
	#define REG_03AC_CKGEN01_V007_REG_PIX_SC_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03AC_CKGEN01_V007_REG_PIX_SC_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03AC_CKGEN01_V007_REG_PIX_SC_P0_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_03B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3B0)
	#define REG_03B0_CKGEN01_V007_REG_PIX_SC_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03B0_CKGEN01_V007_REG_PIX_SC_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03B0_CKGEN01_V007_REG_PIX_SC_P1_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_03B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3B4)
	#define REG_03B4_CKGEN01_V007_REG_DMA_LS_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03B4_CKGEN01_V007_REG_DMA_LS_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03B4_CKGEN01_V007_REG_DMA_LS_P0_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_03B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3B8)
	#define REG_03B8_CKGEN01_V007_REG_DMA_LS_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03B8_CKGEN01_V007_REG_DMA_LS_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03B8_CKGEN01_V007_REG_DMA_LS_P1_SEL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_03BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3BC)
	#define REG_03BC_CKGEN01_V007_REG_SW_EN_XTAL_MBIST2DPRX_XTAL_MBIST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03BC_CKGEN01_V007_REG_SW_EN_XTAL2DPRX_XTAL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03BC_CKGEN01_V007_REG_SW_EN_APB_RX2DPRX_APB Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03BC_CKGEN01_V007_REG_SW_EN_MCU2DPRX_MCU Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03BC_CKGEN01_V007_REG_SW_EN_MCU_RECEIVER2DPRX_MCU_RECV0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03BC_CKGEN01_V007_REG_SW_EN_MCU_RECEIVER2DPRX_MCU_RECV1 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_03C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3C0)
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L0_DESKEW Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L1_DESKEW Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L2_DESKEW Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L3_DESKEW Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_DESCRM Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_HDCP0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_HDCP1 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_03C0_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_HDCP2 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_03C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3C4)
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L0_FEC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L1_FEC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L2_FEC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L3_FEC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L0_FEC_GATED Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L1_FEC_GATED Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L2_FEC_GATED Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_03C4_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_RECV0_LS_L3_FEC_GATED Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_03C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3C8)
	#define REG_03C8_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_DEC0_LS_ORG_DEC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03C8_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_DEC0_LS_DEC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03C8_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_DEC0_LS_VIDEO Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03C8_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_DEC0_LS_SDP Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03C8_CKGEN01_V007_REG_SW_EN_DPRX_LS02DPRX_DEC0_LS_AUD Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_03CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3CC)
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L0_DESKEW Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L1_DESKEW Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L2_DESKEW Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L3_DESKEW Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_DESCRM Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_HDCP0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_HDCP1 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_03CC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_HDCP2 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_03D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3D4)
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L0_FEC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L1_FEC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L2_FEC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L3_FEC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L0_FEC_GATED Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L1_FEC_GATED Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L2_FEC_GATED Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_03D4_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_RECV1_LS_L3_FEC_GATED Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_03DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3DC)
	#define REG_03DC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_DEC1_LS_ORG_DEC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03DC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_DEC1_LS_DEC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03DC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_DEC1_LS_VIDEO Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03DC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_DEC1_LS_SDP Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03DC_CKGEN01_V007_REG_SW_EN_DPRX_LS12DPRX_DEC1_LS_AUD Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_03E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3E4)
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_FSYNC_SYNTH2DPRX_SYNTH0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_FSYNC_SYNTH2DPRX_SYNTH1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_FSYNC_ODCLK_P02DPRX_ODCLK0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_FSYNC_ODCLK_P12DPRX_ODCLK1 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_PIX_4P_P02DPRX_PIX0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_PIX_4P_P12DPRX_PIX1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_03E4_CKGEN01_V007_REG_SW_EN_AUDIO2DPRX_AUDIO Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_03EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3EC)
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_AUDIO_LS2DPRX_LS_AUD_HDMI Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_AUDIO_LS2DPRX_LS_AUD_VIDEO Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_DSC_LS_P02DSC_LS0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_DSC_LS_P12DSC_LS1 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_I2S2DPRX_I2S Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_FSYNC_IDCLK_P02DPRX_IDCLK0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_FSYNC_IDCLK_P12DPRX_IDCLK1 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_PIX_SC_P02SC_PIX0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_PIX_SC_P12SC_PIX1 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_DMA_LS_P02SC_DMA0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_DMA_LS_P12SC_DMA1 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_DMA_SWAP_LS_P02SC_DMA0_SWAP Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_03EC_CKGEN01_V007_REG_SW_EN_DMA_SWAP_LS_P12SC_DMA1_SWAP Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_03F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3F4)
	#define REG_03F4_CKGEN01_V007_REG_DMA_SWAP_LS_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03F4_CKGEN01_V007_REG_DMA_SWAP_LS_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03F4_CKGEN01_V007_REG_DMA_SWAP_LS_P0_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_03FC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x3FC)
	#define REG_03FC_CKGEN01_V007_REG_DMA_SWAP_LS_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_03FC_CKGEN01_V007_REG_DMA_SWAP_LS_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_03FC_CKGEN01_V007_REG_DMA_SWAP_LS_P1_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0614_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x614)
	#define REG_0614_CKGEN01_V007_REG_EDP12_TV_TX_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0614_CKGEN01_V007_REG_EDP12_TV_TX_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0614_CKGEN01_V007_REG_EDP12_TV_TX_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_061C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x61C)
	#define REG_061C_CKGEN01_V007_REG_EDP12_TV_TX_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0624_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x624)
	#define REG_0624_CKGEN01_V007_REG_EDP12_TV_TX_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_062C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x62C)
	#define REG_062C_CKGEN01_V007_REG_SW_EN_DP_TX_AUX_PWR_GATED2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0630_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x630)
	#define REG_0630_CKGEN01_V007_REG_SW_EN_DP_TX_LS_PWR_GATED2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0634_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x634)
	#define REG_0634_CKGEN01_V007_REG_SW_EN_DP_TX_LS_RX_PWR_GATED2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_063C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x63C)
	#define REG_063C_CKGEN01_V007_REG_SW_EN_DP_TX_REF_PWR_GATED2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0644_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x644)
	#define REG_0644_CKGEN01_V007_REG_SW_EN_DP_TX_VIDEO_INTF_PWR_GATED2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_064C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x64C)
	#define REG_064C_CKGEN01_V007_REG_SW_EN_DP_TX_VIDEO_PWR_GATED2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0654_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x654)
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_AUX2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_AUX_MUX_DATA2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_AUX_MUX_VALID2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_ENCODER_L02MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_ENCODER_L12MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_ENCODER_L22MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_ENCODER_L32MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_RX_DIV42MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_FEC_IN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_FEC_OUT2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_ICG2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_L12MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_L22MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_L32MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0654_CKGEN01_V007_REG_SW_EN_P0_LS_TX_ORG2MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_065C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x65C)
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_LS_TX_PHY_PATGEN2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_LS_TX_SDP2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_LS_TX_TPS2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_LS_VSC_W2MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_ALIVE2MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_CRC2MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_DSC2MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_DSC_BYPASS2MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_FOR_MN_GEN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_FRAMESYNC2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_IN2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_PATGEN2MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_VIDEO_L02MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_VIDEO_L12MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_065C_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_VIDEO_L22MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0664_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x664)
	#define REG_0664_CKGEN01_V007_REG_SW_EN_P0_PIX_TX_VIDEO_L32MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0664_CKGEN01_V007_REG_SW_EN_P0_XTAL2MAC Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_066C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x66C)
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_AUX2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_AUX_MUX_DATA2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_AUX_MUX_VALID2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_ENCODER_L02MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_ENCODER_L12MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_ENCODER_L22MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_ENCODER_L32MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_RX_DIV42MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_FEC_IN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_FEC_OUT2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_ICG2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_L12MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_L22MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_L32MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_066C_CKGEN01_V007_REG_SW_EN_P1_LS_TX_ORG2MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0674_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x674)
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_LS_TX_PHY_PATGEN2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_LS_TX_SDP2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_LS_TX_TPS2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_LS_VSC_W2MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_ALIVE2MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_CRC2MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_DSC2MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_DSC_BYPASS2MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_FOR_MN_GEN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_FRAMESYNC2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_IN2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_PATGEN2MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_VIDEO_L02MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_VIDEO_L12MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0674_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_VIDEO_L22MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_067C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x67C)
	#define REG_067C_CKGEN01_V007_REG_SW_EN_P1_PIX_TX_VIDEO_L32MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_067C_CKGEN01_V007_REG_SW_EN_P1_XTAL2MAC Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0684_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x684)
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_AUX2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_AUX_MUX_DATA2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_AUX_MUX_VALID2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_ENCODER_L02MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_ENCODER_L12MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_ENCODER_L22MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_ENCODER_L32MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_RX_DIV42MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_FEC_IN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_FEC_OUT2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_ICG2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_L12MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_L22MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_L32MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0684_CKGEN01_V007_REG_SW_EN_P2_LS_TX_ORG2MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_068C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x68C)
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_LS_TX_PHY_PATGEN2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_LS_TX_SDP2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_LS_TX_TPS2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_LS_VSC_W2MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_ALIVE2MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_CRC2MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_DSC2MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_DSC_BYPASS2MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_FOR_MN_GEN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_FRAMESYNC2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_IN2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_PATGEN2MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_VIDEO_L02MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_VIDEO_L12MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_068C_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_VIDEO_L22MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0694_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x694)
	#define REG_0694_CKGEN01_V007_REG_SW_EN_P2_PIX_TX_VIDEO_L32MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0694_CKGEN01_V007_REG_SW_EN_P2_XTAL2MAC Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_069C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x69C)
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_AUX2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_AUX_MUX_DATA2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_AUX_MUX_VALID2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_ENCODER_L02MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_ENCODER_L12MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_ENCODER_L22MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_ENCODER_L32MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_RX_DIV42MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_FEC_IN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_FEC_OUT2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_ICG2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_L12MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_L22MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_L32MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_069C_CKGEN01_V007_REG_SW_EN_P3_LS_TX_ORG2MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_06A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6A4)
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_LS_TX_PHY_PATGEN2MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_LS_TX_SDP2MAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_LS_TX_TPS2MAC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_LS_VSC_W2MAC Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_ALIVE2MAC Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_CRC2MAC Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_DSC2MAC Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_DSC_BYPASS2MAC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_FOR_MN_GEN2MAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_FRAMESYNC2MAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_IN2MAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_L02MAC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_PATGEN2MAC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_VIDEO_L02MAC Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_VIDEO_L12MAC Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_06A4_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_VIDEO_L22MAC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_06AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6AC)
	#define REG_06AC_CKGEN01_V007_REG_SW_EN_P3_PIX_TX_VIDEO_L32MAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06AC_CKGEN01_V007_REG_SW_EN_P3_XTAL2MAC Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6B4)
	#define REG_06B4_CKGEN01_V007_REG_DPTX_AUX_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06B4_CKGEN01_V007_REG_DPTX_AUX_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6BC)
	#define REG_06BC_CKGEN01_V007_REG_DPTX_LS_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06BC_CKGEN01_V007_REG_DPTX_LS_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6C4)
	#define REG_06C4_CKGEN01_V007_REG_DPTX_LS_RX_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06C4_CKGEN01_V007_REG_DPTX_LS_RX_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6CC)
	#define REG_06CC_CKGEN01_V007_REG_DPTX_REF_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06CC_CKGEN01_V007_REG_DPTX_REF_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6D4)
	#define REG_06D4_CKGEN01_V007_REG_DPTX_VIDEO_INTF_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06D4_CKGEN01_V007_REG_DPTX_VIDEO_INTF_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6DC)
	#define REG_06DC_CKGEN01_V007_REG_DPTX_VIDEO_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06DC_CKGEN01_V007_REG_DPTX_VIDEO_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6E4)
	#define REG_06E4_CKGEN01_V007_REG_AUX_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06E4_CKGEN01_V007_REG_AUX_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6EC)
	#define REG_06EC_CKGEN01_V007_REG_AUX_MUX_DATA_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06EC_CKGEN01_V007_REG_AUX_MUX_DATA_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6F4)
	#define REG_06F4_CKGEN01_V007_REG_AUX_MUX_VALID_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06F4_CKGEN01_V007_REG_AUX_MUX_VALID_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_06FC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x6FC)
	#define REG_06FC_CKGEN01_V007_REG_LS_ENCODER_L0_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_06FC_CKGEN01_V007_REG_LS_ENCODER_L0_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0704_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x704)
	#define REG_0704_CKGEN01_V007_REG_LS_ENCODER_L1_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0704_CKGEN01_V007_REG_LS_ENCODER_L1_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_070C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x70C)
	#define REG_070C_CKGEN01_V007_REG_LS_ENCODER_L2_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_070C_CKGEN01_V007_REG_LS_ENCODER_L2_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0710_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x710)
	#define REG_0710_CKGEN01_V007_REG_LS_ENCODER_L3_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0710_CKGEN01_V007_REG_LS_ENCODER_L3_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0714_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x714)
	#define REG_0714_CKGEN01_V007_REG_LS_RX_ORG_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0714_CKGEN01_V007_REG_LS_RX_ORG_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_071C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x71C)
	#define REG_071C_CKGEN01_V007_REG_LS_TX_FEC_IN_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_071C_CKGEN01_V007_REG_LS_TX_FEC_IN_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0724_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x724)
	#define REG_0724_CKGEN01_V007_REG_LS_TX_FEC_OUT_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0724_CKGEN01_V007_REG_LS_TX_FEC_OUT_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_072C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x72C)
	#define REG_072C_CKGEN01_V007_REG_LS_TX_ICG_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_072C_CKGEN01_V007_REG_LS_TX_ICG_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0734_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x734)
	#define REG_0734_CKGEN01_V007_REG_LS_TX_L0_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0734_CKGEN01_V007_REG_LS_TX_L0_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_073C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x73C)
	#define REG_073C_CKGEN01_V007_REG_LS_TX_L1_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_073C_CKGEN01_V007_REG_LS_TX_L1_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0744_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x744)
	#define REG_0744_CKGEN01_V007_REG_LS_TX_L2_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0744_CKGEN01_V007_REG_LS_TX_L2_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_074C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x74C)
	#define REG_074C_CKGEN01_V007_REG_LS_TX_L3_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_074C_CKGEN01_V007_REG_LS_TX_L3_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0754_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x754)
	#define REG_0754_CKGEN01_V007_REG_LS_TX_ORG_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0754_CKGEN01_V007_REG_LS_TX_ORG_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_075C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x75C)
	#define REG_075C_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_075C_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0764_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x764)
	#define REG_0764_CKGEN01_V007_REG_LS_TX_SDP_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0764_CKGEN01_V007_REG_LS_TX_SDP_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_076C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x76C)
	#define REG_076C_CKGEN01_V007_REG_LS_TX_TPS_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_076C_CKGEN01_V007_REG_LS_TX_TPS_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0774_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x774)
	#define REG_0774_CKGEN01_V007_REG_LS_VSC_W_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0774_CKGEN01_V007_REG_LS_VSC_W_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_077C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x77C)
	#define REG_077C_CKGEN01_V007_REG_PIX_TX_ALIVE_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_077C_CKGEN01_V007_REG_PIX_TX_ALIVE_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0784_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x784)
	#define REG_0784_CKGEN01_V007_REG_PIX_TX_CRC_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0784_CKGEN01_V007_REG_PIX_TX_CRC_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_078C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x78C)
	#define REG_078C_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_078C_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0794_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x794)
	#define REG_0794_CKGEN01_V007_REG_PIX_TX_DSC_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0794_CKGEN01_V007_REG_PIX_TX_DSC_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_079C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x79C)
	#define REG_079C_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_079C_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7A4)
	#define REG_07A4_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07A4_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7AC)
	#define REG_07AC_CKGEN01_V007_REG_PIX_TX_IN_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07AC_CKGEN01_V007_REG_PIX_TX_IN_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7B4)
	#define REG_07B4_CKGEN01_V007_REG_PIX_TX_L0_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07B4_CKGEN01_V007_REG_PIX_TX_L0_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7BC)
	#define REG_07BC_CKGEN01_V007_REG_PIX_TX_PATGEN_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07BC_CKGEN01_V007_REG_PIX_TX_PATGEN_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7C4)
	#define REG_07C4_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07C4_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7CC)
	#define REG_07CC_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07CC_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7D4)
	#define REG_07D4_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07D4_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7DC)
	#define REG_07DC_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07DC_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7E4)
	#define REG_07E4_CKGEN01_V007_REG_XTAL_P0_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07E4_CKGEN01_V007_REG_XTAL_P0_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7EC)
	#define REG_07EC_CKGEN01_V007_REG_AUX_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07EC_CKGEN01_V007_REG_AUX_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7F4)
	#define REG_07F4_CKGEN01_V007_REG_AUX_MUX_DATA_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07F4_CKGEN01_V007_REG_AUX_MUX_DATA_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_07FC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x7FC)
	#define REG_07FC_CKGEN01_V007_REG_AUX_MUX_VALID_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_07FC_CKGEN01_V007_REG_AUX_MUX_VALID_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0804_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x804)
	#define REG_0804_CKGEN01_V007_REG_LS_ENCODER_L0_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0804_CKGEN01_V007_REG_LS_ENCODER_L0_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_080C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x80C)
	#define REG_080C_CKGEN01_V007_REG_LS_ENCODER_L1_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_080C_CKGEN01_V007_REG_LS_ENCODER_L1_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0814_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x814)
	#define REG_0814_CKGEN01_V007_REG_LS_ENCODER_L2_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0814_CKGEN01_V007_REG_LS_ENCODER_L2_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_081C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x81C)
	#define REG_081C_CKGEN01_V007_REG_LS_ENCODER_L3_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_081C_CKGEN01_V007_REG_LS_ENCODER_L3_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0824_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x824)
	#define REG_0824_CKGEN01_V007_REG_LS_RX_ORG_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0824_CKGEN01_V007_REG_LS_RX_ORG_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_082C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x82C)
	#define REG_082C_CKGEN01_V007_REG_LS_TX_FEC_IN_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_082C_CKGEN01_V007_REG_LS_TX_FEC_IN_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0838_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x838)
	#define REG_0838_CKGEN01_V007_REG_LS_TX_FEC_OUT_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0838_CKGEN01_V007_REG_LS_TX_FEC_OUT_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_083C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x83C)
	#define REG_083C_CKGEN01_V007_REG_LS_TX_ICG_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_083C_CKGEN01_V007_REG_LS_TX_ICG_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0840_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x840)
	#define REG_0840_CKGEN01_V007_REG_LS_TX_L0_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0840_CKGEN01_V007_REG_LS_TX_L0_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0844_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x844)
	#define REG_0844_CKGEN01_V007_REG_LS_TX_L1_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0844_CKGEN01_V007_REG_LS_TX_L1_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0848_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x848)
	#define REG_0848_CKGEN01_V007_REG_LS_TX_L2_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0848_CKGEN01_V007_REG_LS_TX_L2_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_084C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x84C)
	#define REG_084C_CKGEN01_V007_REG_LS_TX_L3_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_084C_CKGEN01_V007_REG_LS_TX_L3_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0850_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x850)
	#define REG_0850_CKGEN01_V007_REG_LS_TX_ORG_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0850_CKGEN01_V007_REG_LS_TX_ORG_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0854_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x854)
	#define REG_0854_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0854_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0858_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x858)
	#define REG_0858_CKGEN01_V007_REG_LS_TX_SDP_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0858_CKGEN01_V007_REG_LS_TX_SDP_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_085C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x85C)
	#define REG_085C_CKGEN01_V007_REG_LS_TX_TPS_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_085C_CKGEN01_V007_REG_LS_TX_TPS_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0860_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x860)
	#define REG_0860_CKGEN01_V007_REG_LS_VSC_W_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0860_CKGEN01_V007_REG_LS_VSC_W_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0864_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x864)
	#define REG_0864_CKGEN01_V007_REG_PIX_TX_ALIVE_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0864_CKGEN01_V007_REG_PIX_TX_ALIVE_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0868_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x868)
	#define REG_0868_CKGEN01_V007_REG_PIX_TX_CRC_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0868_CKGEN01_V007_REG_PIX_TX_CRC_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_086C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x86C)
	#define REG_086C_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_086C_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0870_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x870)
	#define REG_0870_CKGEN01_V007_REG_PIX_TX_DSC_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0870_CKGEN01_V007_REG_PIX_TX_DSC_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0874_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x874)
	#define REG_0874_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0874_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0878_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x878)
	#define REG_0878_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0878_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_087C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x87C)
	#define REG_087C_CKGEN01_V007_REG_PIX_TX_IN_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_087C_CKGEN01_V007_REG_PIX_TX_IN_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0880_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x880)
	#define REG_0880_CKGEN01_V007_REG_PIX_TX_L0_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0880_CKGEN01_V007_REG_PIX_TX_L0_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0884_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x884)
	#define REG_0884_CKGEN01_V007_REG_PIX_TX_PATGEN_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0884_CKGEN01_V007_REG_PIX_TX_PATGEN_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0888_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x888)
	#define REG_0888_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0888_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_088C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x88C)
	#define REG_088C_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_088C_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0890_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x890)
	#define REG_0890_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0890_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0894_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x894)
	#define REG_0894_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0894_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0898_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x898)
	#define REG_0898_CKGEN01_V007_REG_XTAL_P1_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0898_CKGEN01_V007_REG_XTAL_P1_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_089C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x89C)
	#define REG_089C_CKGEN01_V007_REG_AUX_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_089C_CKGEN01_V007_REG_AUX_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8A0)
	#define REG_08A0_CKGEN01_V007_REG_AUX_MUX_DATA_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08A0_CKGEN01_V007_REG_AUX_MUX_DATA_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8A4)
	#define REG_08A4_CKGEN01_V007_REG_AUX_MUX_VALID_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08A4_CKGEN01_V007_REG_AUX_MUX_VALID_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8A8)
	#define REG_08A8_CKGEN01_V007_REG_LS_ENCODER_L0_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08A8_CKGEN01_V007_REG_LS_ENCODER_L0_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8AC)
	#define REG_08AC_CKGEN01_V007_REG_LS_ENCODER_L1_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08AC_CKGEN01_V007_REG_LS_ENCODER_L1_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8B0)
	#define REG_08B0_CKGEN01_V007_REG_LS_ENCODER_L2_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08B0_CKGEN01_V007_REG_LS_ENCODER_L2_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8B4)
	#define REG_08B4_CKGEN01_V007_REG_LS_ENCODER_L3_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08B4_CKGEN01_V007_REG_LS_ENCODER_L3_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8B8)
	#define REG_08B8_CKGEN01_V007_REG_LS_RX_ORG_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08B8_CKGEN01_V007_REG_LS_RX_ORG_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8BC)
	#define REG_08BC_CKGEN01_V007_REG_LS_TX_FEC_IN_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08BC_CKGEN01_V007_REG_LS_TX_FEC_IN_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8C0)
	#define REG_08C0_CKGEN01_V007_REG_LS_TX_FEC_OUT_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08C0_CKGEN01_V007_REG_LS_TX_FEC_OUT_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8C4)
	#define REG_08C4_CKGEN01_V007_REG_LS_TX_ICG_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08C4_CKGEN01_V007_REG_LS_TX_ICG_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8C8)
	#define REG_08C8_CKGEN01_V007_REG_LS_TX_L0_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08C8_CKGEN01_V007_REG_LS_TX_L0_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8CC)
	#define REG_08CC_CKGEN01_V007_REG_LS_TX_L1_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08CC_CKGEN01_V007_REG_LS_TX_L1_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8D0)
	#define REG_08D0_CKGEN01_V007_REG_LS_TX_L2_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08D0_CKGEN01_V007_REG_LS_TX_L2_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8D4)
	#define REG_08D4_CKGEN01_V007_REG_LS_TX_L3_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08D4_CKGEN01_V007_REG_LS_TX_L3_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08D8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8D8)
	#define REG_08D8_CKGEN01_V007_REG_LS_TX_ORG_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08D8_CKGEN01_V007_REG_LS_TX_ORG_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8DC)
	#define REG_08DC_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08DC_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8E0)
	#define REG_08E0_CKGEN01_V007_REG_CKG_G_DET_RCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08E0_CKGEN01_V007_REG_CKG_I_DET_RCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_08E0_CKGEN01_V007_REG_CKG_S_DET_RCLK Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_08E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8E4)
	#define REG_08E4_CKGEN01_V007_REG_LS_TX_SDP_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08E4_CKGEN01_V007_REG_LS_TX_SDP_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08E8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8E8)
	#define REG_08E8_CKGEN01_V007_REG_CKG_G_DET_WCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08E8_CKGEN01_V007_REG_CKG_I_DET_WCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_08E8_CKGEN01_V007_REG_CKG_S_DET_WCLK Fld(5, 2, AC_MSKB0)//[6:2]
#define REG_08EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8EC)
	#define REG_08EC_CKGEN01_V007_REG_LS_TX_TPS_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08EC_CKGEN01_V007_REG_LS_TX_TPS_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_08F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8F0)
	#define REG_08F0_CKGEN01_V007_REG_CKG_G_LPLL_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08F0_CKGEN01_V007_REG_CKG_I_LPLL_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_08F0_CKGEN01_V007_REG_CKG_S_LPLL_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_08F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x8F8)
	#define REG_08F8_CKGEN01_V007_REG_CKG_G_LPLL_ODCLK_NODIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_08F8_CKGEN01_V007_REG_CKG_I_LPLL_ODCLK_NODIV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0900_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x900)
	#define REG_0900_CKGEN01_V007_REG_CKG_G_LPLL_SYN_432 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0900_CKGEN01_V007_REG_CKG_I_LPLL_SYN_432 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0900_CKGEN01_V007_REG_CKG_S_LPLL_SYN_432 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0904_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x904)
	#define REG_0904_CKGEN01_V007_REG_LS_VSC_W_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0904_CKGEN01_V007_REG_LS_VSC_W_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0908_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x908)
	#define REG_0908_CKGEN01_V007_REG_PIX_TX_ALIVE_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0908_CKGEN01_V007_REG_PIX_TX_ALIVE_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_090C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x90C)
	#define REG_090C_CKGEN01_V007_REG_PIX_TX_CRC_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_090C_CKGEN01_V007_REG_PIX_TX_CRC_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0910_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x910)
	#define REG_0910_CKGEN01_V007_REG_CKG_G_MOD_A_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0910_CKGEN01_V007_REG_CKG_I_MOD_A_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0910_CKGEN01_V007_REG_CKG_S_MOD_A_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0914_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x914)
	#define REG_0914_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0914_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0918_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x918)
	#define REG_0918_CKGEN01_V007_REG_CKG_G_MOD_D_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0918_CKGEN01_V007_REG_CKG_I_MOD_D_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0918_CKGEN01_V007_REG_CKG_S_MOD_D_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
	#define REG_0918_CKGEN01_V007_REG_CKG_MOD_D_ODCLK Fld(6, 0, AC_MSKB0)//[5:0]
#define REG_091C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x91C)
	#define REG_091C_CKGEN01_V007_REG_CKG_G_MOD_O_SR_WCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_091C_CKGEN01_V007_REG_CKG_I_MOD_O_SR_WCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_091C_CKGEN01_V007_REG_CKG_S_MOD_O_SR_WCLK Fld(4, 2, AC_MSKB0)//[5:2]
	#define REG_091C_CKGEN01_V007_REG_CKG_MOD_O_SR_WCLK Fld(6, 0, AC_MSKB0)//[5:0]
#define REG_0920_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x920)
	#define REG_0920_CKGEN01_V007_REG_CKG_G_MOD_V1_SR_WCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0920_CKGEN01_V007_REG_CKG_I_MOD_V1_SR_WCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0920_CKGEN01_V007_REG_CKG_S_MOD_V1_SR_WCLK Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_0920_CKGEN01_V007_REG_CKG_MOD_V1_SR_WCLK Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_0924_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x924)
	#define REG_0924_CKGEN01_V007_REG_CKG_G_MOD_V2_SR_WCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0924_CKGEN01_V007_REG_CKG_I_MOD_V2_SR_WCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0924_CKGEN01_V007_REG_CKG_S_MOD_V2_SR_WCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0928_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x928)
	#define REG_0928_CKGEN01_V007_REG_CKG_G_O_MOD_SR_RCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0928_CKGEN01_V007_REG_CKG_I_O_MOD_SR_RCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0928_CKGEN01_V007_REG_CKG_S_O_MOD_SR_RCLK Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0928_CKGEN01_V007_REG_CKG_O_MOD_SR_RCLK Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_092C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x92C)
	#define REG_092C_CKGEN01_V007_REG_PIX_TX_DSC_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_092C_CKGEN01_V007_REG_PIX_TX_DSC_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0930_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x930)
	#define REG_0930_CKGEN01_V007_REG_CKG_G_O_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0930_CKGEN01_V007_REG_CKG_I_O_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0930_CKGEN01_V007_REG_CKG_S_O_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0934_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x934)
	#define REG_0934_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0934_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0938_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x938)
	#define REG_0938_CKGEN01_V007_REG_CKG_G_O_ODCLK_STG1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0938_CKGEN01_V007_REG_CKG_I_O_ODCLK_STG1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0938_CKGEN01_V007_REG_CKG_S_O_ODCLK_STG1 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_093C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x93C)
	#define REG_093C_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_093C_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0940_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x940)
	#define REG_0940_CKGEN01_V007_REG_CKG_G_O_ODCLK_STG2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0940_CKGEN01_V007_REG_CKG_I_O_ODCLK_STG2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0940_CKGEN01_V007_REG_CKG_S_O_ODCLK_STG2 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0944_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x944)
	#define REG_0944_CKGEN01_V007_REG_PIX_TX_IN_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0944_CKGEN01_V007_REG_PIX_TX_IN_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0948_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x948)
	#define REG_0948_CKGEN01_V007_REG_CKG_G_O_ODCLK_STG3 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0948_CKGEN01_V007_REG_CKG_I_O_ODCLK_STG3 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0948_CKGEN01_V007_REG_CKG_S_O_ODCLK_STG3 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_094C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x94C)
	#define REG_094C_CKGEN01_V007_REG_PIX_TX_L0_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_094C_CKGEN01_V007_REG_PIX_TX_L0_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0950_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x950)
	#define REG_0950_CKGEN01_V007_REG_CKG_G_O_ODCLK_STG4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0950_CKGEN01_V007_REG_CKG_I_O_ODCLK_STG4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0950_CKGEN01_V007_REG_CKG_S_O_ODCLK_STG4 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0954_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x954)
	#define REG_0954_CKGEN01_V007_REG_PIX_TX_PATGEN_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0954_CKGEN01_V007_REG_PIX_TX_PATGEN_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0958_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x958)
	#define REG_0958_CKGEN01_V007_REG_CKG_G_O_ODCLK_STG5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0958_CKGEN01_V007_REG_CKG_I_O_ODCLK_STG5 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0958_CKGEN01_V007_REG_CKG_S_O_ODCLK_STG5 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_095C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x95C)
	#define REG_095C_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_095C_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0960_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x960)
	#define REG_0960_CKGEN01_V007_REG_CKG_G_O_ODCLK_STG6 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0960_CKGEN01_V007_REG_CKG_I_O_ODCLK_STG6 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0960_CKGEN01_V007_REG_CKG_S_O_ODCLK_STG6 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0964_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x964)
	#define REG_0964_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0964_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0968_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x968)
	#define REG_0968_CKGEN01_V007_REG_CKG_G_PWM Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0968_CKGEN01_V007_REG_CKG_I_PWM Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0968_CKGEN01_V007_REG_CKG_S_PWM Fld(5, 2, AC_MSKB0)//[6:2]
#define REG_096C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x96C)
	#define REG_096C_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_096C_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0970_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x970)
	#define REG_0970_CKGEN01_V007_REG_CKG_G_V1_MOD_SR_RCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0970_CKGEN01_V007_REG_CKG_I_V1_MOD_SR_RCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0970_CKGEN01_V007_REG_CKG_S_V1_MOD_SR_RCLK Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0970_CKGEN01_V007_REG_CKG_V1_MOD_SR_RCLK Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_0974_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x974)
	#define REG_0974_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0974_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0978_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x978)
	#define REG_0978_CKGEN01_V007_REG_CKG_G_V1_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0978_CKGEN01_V007_REG_CKG_I_V1_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0978_CKGEN01_V007_REG_CKG_S_V1_ODCLK Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_0978_CKGEN01_V007_REG_CKG_V1_ODCLK Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_097C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x97C)
	#define REG_097C_CKGEN01_V007_REG_XTAL_P2_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_097C_CKGEN01_V007_REG_XTAL_P2_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0980_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x980)
	#define REG_0980_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0980_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0980_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG1 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_0980_CKGEN01_V007_REG_CKG_V1_ODCLK_STG1 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_0984_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x984)
	#define REG_0984_CKGEN01_V007_REG_AUX_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0984_CKGEN01_V007_REG_AUX_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0988_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x988)
	#define REG_0988_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0988_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0988_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG2 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_0988_CKGEN01_V007_REG_CKG_V1_ODCLK_STG2 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_098C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x98C)
	#define REG_098C_CKGEN01_V007_REG_AUX_MUX_DATA_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_098C_CKGEN01_V007_REG_AUX_MUX_DATA_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0990_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x990)
	#define REG_0990_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG3 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0990_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG3 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0990_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG3 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_0990_CKGEN01_V007_REG_CKG_V1_ODCLK_STG3 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_0994_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x994)
	#define REG_0994_CKGEN01_V007_REG_AUX_MUX_VALID_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0994_CKGEN01_V007_REG_AUX_MUX_VALID_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0998_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x998)
	#define REG_0998_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0998_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0998_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG4 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_0998_CKGEN01_V007_REG_CKG_V1_ODCLK_STG4 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_099C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x99C)
	#define REG_099C_CKGEN01_V007_REG_LS_ENCODER_L0_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_099C_CKGEN01_V007_REG_LS_ENCODER_L0_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9A0)
	#define REG_09A0_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09A0_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG5 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09A0_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG5 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_09A0_CKGEN01_V007_REG_CKG_V1_ODCLK_STG5 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_09A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9A4)
	#define REG_09A4_CKGEN01_V007_REG_LS_ENCODER_L1_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09A4_CKGEN01_V007_REG_LS_ENCODER_L1_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9A8)
	#define REG_09A8_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG6 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09A8_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG6 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09A8_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG6 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_09A8_CKGEN01_V007_REG_CKG_V1_ODCLK_STG6 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_09AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9AC)
	#define REG_09AC_CKGEN01_V007_REG_LS_ENCODER_L2_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09AC_CKGEN01_V007_REG_LS_ENCODER_L2_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9B0)
	#define REG_09B0_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG7 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09B0_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG7 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09B0_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG7 Fld(5, 2, AC_MSKB0)//[6:2]
	#define REG_09B0_CKGEN01_V007_REG_CKG_V1_ODCLK_STG7 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_09B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9B4)
	#define REG_09B4_CKGEN01_V007_REG_LS_ENCODER_L3_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09B4_CKGEN01_V007_REG_LS_ENCODER_L3_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9B8)
	#define REG_09B8_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG8 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09B8_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG8 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09B8_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG8 Fld(4, 2, AC_MSKB0)//[5:2]
	#define REG_09B8_CKGEN01_V007_REG_CKG_V1_ODCLK_STG8 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_09BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9BC)
	#define REG_09BC_CKGEN01_V007_REG_LS_RX_ORG_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09BC_CKGEN01_V007_REG_LS_RX_ORG_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9C0)
	#define REG_09C0_CKGEN01_V007_REG_CKG_G_V2_MOD_SR_RCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09C0_CKGEN01_V007_REG_CKG_I_V2_MOD_SR_RCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09C0_CKGEN01_V007_REG_CKG_S_V2_MOD_SR_RCLK Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_09C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9C4)
	#define REG_09C4_CKGEN01_V007_REG_LS_TX_FEC_IN_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09C4_CKGEN01_V007_REG_LS_TX_FEC_IN_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9C8)
	#define REG_09C8_CKGEN01_V007_REG_CKG_G_V2_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09C8_CKGEN01_V007_REG_CKG_I_V2_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09C8_CKGEN01_V007_REG_CKG_S_V2_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9CC)
	#define REG_09CC_CKGEN01_V007_REG_LS_TX_FEC_OUT_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09CC_CKGEN01_V007_REG_LS_TX_FEC_OUT_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9D0)
	#define REG_09D0_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09D0_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09D0_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG1 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9D4)
	#define REG_09D4_CKGEN01_V007_REG_LS_TX_ICG_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09D4_CKGEN01_V007_REG_LS_TX_ICG_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09D8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9D8)
	#define REG_09D8_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09D8_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09D8_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG2 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9DC)
	#define REG_09DC_CKGEN01_V007_REG_LS_TX_L0_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09DC_CKGEN01_V007_REG_LS_TX_L0_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9E0)
	#define REG_09E0_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG3 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09E0_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG3 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09E0_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG3 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9E4)
	#define REG_09E4_CKGEN01_V007_REG_LS_TX_L1_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09E4_CKGEN01_V007_REG_LS_TX_L1_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09E8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9E8)
	#define REG_09E8_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09E8_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09E8_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG4 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9EC)
	#define REG_09EC_CKGEN01_V007_REG_LS_TX_L2_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09EC_CKGEN01_V007_REG_LS_TX_L2_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9F0)
	#define REG_09F0_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09F0_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG5 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09F0_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG5 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9F4)
	#define REG_09F4_CKGEN01_V007_REG_LS_TX_L3_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09F4_CKGEN01_V007_REG_LS_TX_L3_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_09F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9F8)
	#define REG_09F8_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG6 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09F8_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG6 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_09F8_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG6 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_09FC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x9FC)
	#define REG_09FC_CKGEN01_V007_REG_LS_TX_ORG_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_09FC_CKGEN01_V007_REG_LS_TX_ORG_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A00_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA00)
	#define REG_0A00_CKGEN01_V007_REG_CKG_G_V2_ODCLK_STG7 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A00_CKGEN01_V007_REG_CKG_I_V2_ODCLK_STG7 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A00_CKGEN01_V007_REG_CKG_S_V2_ODCLK_STG7 Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_0A04_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA04)
	#define REG_0A04_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A04_CKGEN01_V007_REG_LS_TX_PHY_PATGEN_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A08_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA08)
	#define REG_0A08_CKGEN01_V007_REG_CKG_G_O_MOD_SR_RCLK_FINIAL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A08_CKGEN01_V007_REG_CKG_I_O_MOD_SR_RCLK_FINIAL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A08_CKGEN01_V007_REG_CKG_S_O_MOD_SR_RCLK_FINIAL Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0A08_CKGEN01_V007_REG_CKG_O_MOD_SR_RCLK_FINIAL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0A0C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA0C)
	#define REG_0A0C_CKGEN01_V007_REG_LS_TX_SDP_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A0C_CKGEN01_V007_REG_LS_TX_SDP_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A10_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA10)
	#define REG_0A10_CKGEN01_V007_REG_CKG_G_O_MOD_SR_RCLK_PRE0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A10_CKGEN01_V007_REG_CKG_I_O_MOD_SR_RCLK_PRE0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A10_CKGEN01_V007_REG_CKG_S_O_MOD_SR_RCLK_PRE0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0A10_CKGEN01_V007_REG_CKG_O_MOD_SR_RCLK_PRE0 Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0A14_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA14)
	#define REG_0A14_CKGEN01_V007_REG_LS_TX_TPS_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A14_CKGEN01_V007_REG_LS_TX_TPS_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A18_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA18)
	#define REG_0A18_CKGEN01_V007_REG_CKG_G_O_MOD_SR_RCLK_PRE1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A18_CKGEN01_V007_REG_CKG_I_O_MOD_SR_RCLK_PRE1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A18_CKGEN01_V007_REG_CKG_S_O_MOD_SR_RCLK_PRE1 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0A18_CKGEN01_V007_REG_CKG_O_MOD_SR_RCLK_PRE1 Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0A1C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA1C)
	#define REG_0A1C_CKGEN01_V007_REG_LS_VSC_W_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A1C_CKGEN01_V007_REG_LS_VSC_W_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A20_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA20)
	#define REG_0A20_CKGEN01_V007_REG_CKG_G_V1_MOD_SR_RCLK_FINIAL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A20_CKGEN01_V007_REG_CKG_I_V1_MOD_SR_RCLK_FINIAL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A20_CKGEN01_V007_REG_CKG_S_V1_MOD_SR_RCLK_FINIAL Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0A20_CKGEN01_V007_REG_CKG_V1_MOD_SR_RCLK_FINIAL Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0A24_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA24)
	#define REG_0A24_CKGEN01_V007_REG_PIX_TX_ALIVE_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A24_CKGEN01_V007_REG_PIX_TX_ALIVE_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A28_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA28)
	#define REG_0A28_CKGEN01_V007_REG_CKG_G_V1_MOD_SR_RCLK_PRE0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A28_CKGEN01_V007_REG_CKG_I_V1_MOD_SR_RCLK_PRE0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A28_CKGEN01_V007_REG_CKG_S_V1_MOD_SR_RCLK_PRE0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0A28_CKGEN01_V007_REG_CKG_V1_MOD_SR_RCLK_PRE0  Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0A2C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA2C)
	#define REG_0A2C_CKGEN01_V007_REG_PIX_TX_CRC_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A2C_CKGEN01_V007_REG_PIX_TX_CRC_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A30_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA30)
	#define REG_0A30_CKGEN01_V007_REG_CKG_G_V1_MOD_SR_RCLK_PRE1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A30_CKGEN01_V007_REG_CKG_I_V1_MOD_SR_RCLK_PRE1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A30_CKGEN01_V007_REG_CKG_S_V1_MOD_SR_RCLK_PRE1 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0A30_CKGEN01_V007_REG_CKG_V1_MOD_SR_RCLK_PRE1 Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0A34_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA34)
	#define REG_0A34_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A34_CKGEN01_V007_REG_PIX_TX_DSC_BYPASS_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A38_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA38)
	#define REG_0A38_CKGEN01_V007_REG_CKG_G_V2_MOD_SR_RCLK_FINIAL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A38_CKGEN01_V007_REG_CKG_I_V2_MOD_SR_RCLK_FINIAL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A38_CKGEN01_V007_REG_CKG_S_V2_MOD_SR_RCLK_FINIAL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0A3C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA3C)
	#define REG_0A3C_CKGEN01_V007_REG_PIX_TX_DSC_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A3C_CKGEN01_V007_REG_PIX_TX_DSC_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A40_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA40)
	#define REG_0A40_CKGEN01_V007_REG_CKG_G_V2_MOD_SR_RCLK_PRE0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A40_CKGEN01_V007_REG_CKG_I_V2_MOD_SR_RCLK_PRE0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A40_CKGEN01_V007_REG_CKG_S_V2_MOD_SR_RCLK_PRE0 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0A44_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA44)
	#define REG_0A44_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A44_CKGEN01_V007_REG_PIX_TX_FOR_MN_GEN_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A48_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA48)
	#define REG_0A48_CKGEN01_V007_REG_CKG_G_V2_MOD_SR_RCLK_PRE1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A48_CKGEN01_V007_REG_CKG_I_V2_MOD_SR_RCLK_PRE1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A48_CKGEN01_V007_REG_CKG_S_V2_MOD_SR_RCLK_PRE1 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0A4C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA4C)
	#define REG_0A4C_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A4C_CKGEN01_V007_REG_PIX_TX_FRAMESYNC_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A50_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA50)
	#define REG_0A50_CKGEN01_V007_REG_CKG_G_IDCLK_MOD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A50_CKGEN01_V007_REG_CKG_I_IDCLK_MOD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A50_CKGEN01_V007_REG_CKG_S_IDCLK_MOD Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0A54_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA54)
	#define REG_0A54_CKGEN01_V007_REG_PIX_TX_IN_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A54_CKGEN01_V007_REG_PIX_TX_IN_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A58_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA58)
	#define REG_0A58_CKGEN01_V007_REG_CKG_G_V1_ODCLK_STG9 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A58_CKGEN01_V007_REG_CKG_I_V1_ODCLK_STG9 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0A58_CKGEN01_V007_REG_CKG_S_V1_ODCLK_STG9 Fld(4, 2, AC_MSKB0)//[5:2]
	#define REG_0A58_CKGEN01_V007_REG_CKG_V1_ODCLK_STG9 Fld(6, 0, AC_MSKB0)//[5:0]
#define REG_0A5C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA5C)
	#define REG_0A5C_CKGEN01_V007_REG_PIX_TX_L0_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A5C_CKGEN01_V007_REG_PIX_TX_L0_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A60_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA60)
	#define REG_0A60_CKGEN01_V007_REG_CKG_G_XTAL_12M_MOD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A60_CKGEN01_V007_REG_CKG_I_XTAL_12M_MOD Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A64_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA64)
	#define REG_0A64_CKGEN01_V007_REG_PIX_TX_PATGEN_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A64_CKGEN01_V007_REG_PIX_TX_PATGEN_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A68_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA68)
	#define REG_0A68_CKGEN01_V007_REG_CKG_G_XTAL_24M_MOD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A68_CKGEN01_V007_REG_CKG_I_XTAL_24M_MOD Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0A74_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xA74)
	#define REG_0A74_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0A74_CKGEN01_V007_REG_PIX_TX_VIDEO_L0_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0AA0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAA0)
	#define REG_0AA0_CKGEN01_V007_REG_CKG_G_XC_DC0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AA0_CKGEN01_V007_REG_CKG_I_XC_DC0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AA0_CKGEN01_V007_REG_CKG_S_XC_DC0 Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_0AA4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAA4)
	#define REG_0AA4_CKGEN01_V007_REG_CKG_G_XC_SUB1_DC0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AA4_CKGEN01_V007_REG_CKG_I_XC_SUB1_DC0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AA4_CKGEN01_V007_REG_CKG_S_XC_SUB1_DC0 Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_0AA8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAA8)
	#define REG_0AA8_CKGEN01_V007_REG_CKG_G_XC_SUB_DC0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AA8_CKGEN01_V007_REG_CKG_I_XC_SUB_DC0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AA8_CKGEN01_V007_REG_CKG_S_XC_SUB_DC0 Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_0AB0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAB0)
	#define REG_0AB0_CKGEN01_V007_REG_CKG_G_XC_B2R Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AB0_CKGEN01_V007_REG_CKG_I_XC_B2R Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AB0_CKGEN01_V007_REG_CKG_S_XC_B2R Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0AB8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAB8)
	#define REG_0AB8_CKGEN01_V007_REG_CKG_G_XC_B2R_SUB Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AB8_CKGEN01_V007_REG_CKG_I_XC_B2R_SUB Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AB8_CKGEN01_V007_REG_CKG_S_XC_B2R_SUB Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0AC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAC0)
	#define REG_0AC0_CKGEN01_V007_REG_CKG_G_XC_ED Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AC0_CKGEN01_V007_REG_CKG_I_XC_ED Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AC0_CKGEN01_V007_REG_CKG_S_XC_ED Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0AC8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAC8)
	#define REG_0AC8_CKGEN01_V007_REG_CKG_G_XC_FD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AC8_CKGEN01_V007_REG_CKG_I_XC_FD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AC8_CKGEN01_V007_REG_CKG_S_XC_FD Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0AD0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAD0)
	#define REG_0AD0_CKGEN01_V007_REG_CKG_G_XC_FN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AD0_CKGEN01_V007_REG_CKG_I_XC_FN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AD0_CKGEN01_V007_REG_CKG_S_XC_FN Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0AD8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAD8)
	#define REG_0AD8_CKGEN01_V007_REG_CKG_G_XC_FS Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AD8_CKGEN01_V007_REG_CKG_I_XC_FS Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AD8_CKGEN01_V007_REG_CKG_S_XC_FS Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0AE0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAE0)
	#define REG_0AE0_CKGEN01_V007_REG_CKG_G_XC_OD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AE0_CKGEN01_V007_REG_CKG_I_XC_OD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AE0_CKGEN01_V007_REG_CKG_S_XC_OD Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0AE8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAE8)
	#define REG_0AE8_CKGEN01_V007_REG_CKG_G_XC_SLOW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AE8_CKGEN01_V007_REG_CKG_I_XC_SLOW Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AE8_CKGEN01_V007_REG_CKG_S_XC_SLOW Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0AEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAEC)
	#define REG_0AEC_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AEC_CKGEN01_V007_REG_PIX_TX_VIDEO_L1_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0AF0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAF0)
	#define REG_0AF0_CKGEN01_V007_REG_CKG_G_XC_SRS Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AF0_CKGEN01_V007_REG_CKG_I_XC_SRS Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0AF0_CKGEN01_V007_REG_CKG_S_XC_SRS Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0AF4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xAF4)
	#define REG_0AF4_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0AF4_CKGEN01_V007_REG_PIX_TX_VIDEO_L2_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0B00_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xB00)
	#define REG_0B00_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0B00_CKGEN01_V007_REG_PIX_TX_VIDEO_L3_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0B04_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xB04)
	#define REG_0B04_CKGEN01_V007_REG_XTAL_P3_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0B04_CKGEN01_V007_REG_XTAL_P3_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0B08_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xB08)
	#define REG_0B08_CKGEN01_V007_REG_DPTX_24M_XTAL_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0B08_CKGEN01_V007_REG_DPTX_24M_XTAL_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0B0C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xB0C)
	#define REG_0B0C_CKGEN01_V007_REG_SW_EN_DP_TX_24M_XTAL2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0B10_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xB10)
	#define REG_0B10_CKGEN01_V007_REG_DPTX_MOD_DIV_GATE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0B10_CKGEN01_V007_REG_DPTX_MOD_DIV_INV Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0B14_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xB14)
	#define REG_0B14_CKGEN01_V007_REG_SW_EN_DP_TX_MOD_DIV2MAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0C1C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xC1C)
	#define REG_0C1C_CKGEN01_V007_REG_CKG_S_LZMA_MHEG5 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0C24_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xC24)
	#define REG_0C24_CKGEN01_V007_REG_CKG_G_VD_R2_MHEG5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0C24_CKGEN01_V007_REG_CKG_I_VD_R2_MHEG5 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0C24_CKGEN01_V007_REG_CKG_G_MIIC5_MHEG5 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0C24_CKGEN01_V007_REG_CKG_I_MIIC5_MHEG5 Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_0C28_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xC28)
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_CPUM2CPUM Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_CPUM_PIPE2CPUM Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_VD_R22MCU_VD_R2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_XTAL_24M2CPUM2AXI Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_MCU_NONPM2LZMA Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_MIIC52MCU_MIIC5 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_SMI2MCU_MIIC5 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_SMI2VD_R2 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_XTAL_12M2VD_R2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MIIC5 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_XTAL_12M2MCU_MIIC5 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0C28_CKGEN01_V007_REG_SW_EN_VENC2SMI Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_0C40_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xC40)
	#define REG_0C40_CKGEN01_V007_REG_CKG_G_XCPLL_SYN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0C40_CKGEN01_V007_REG_CKG_I_XCPLL_SYN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0C40_CKGEN01_V007_REG_CKG_S_XCPLL_SYN Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0E54_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE54)
	#define REG_0E54_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_ED Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0E54_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_ED_SLD Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0E58_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE58)
	#define REG_0E58_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_FN Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0E58_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_FN_SLD Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0E5C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE5C)
	#define REG_0E5C_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_FS Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0E5C_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_FS_SLD Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0E60_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE60)
	#define REG_0E60_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_FD Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0E60_CKGEN01_V007_REG_FLOW_CTRL_RATE_XC_FD_SLD Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0E80_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE80)
	#define REG_0E80_CKGEN01_V007_REG_GATE_XC_ED Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0E84_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE84)
	#define REG_0E84_CKGEN01_V007_REG_GATE_XC_FN Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0E88_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE88)
	#define REG_0E88_CKGEN01_V007_REG_GATE_XC_FS Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0E8C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xE8C)
	#define REG_0E8C_CKGEN01_V007_REG_GATE_XC_FD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0ED8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xED8)
	#define REG_0ED8_CKGEN01_V007_REG_CKG_G_IRS_MHEG5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0ED8_CKGEN01_V007_REG_CKG_I_IRS_MHEG5 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0EE0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xEE0)
	#define REG_0EE0_CKGEN01_V007_REG_CKG_G_MCU_MAIL0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0EE0_CKGEN01_V007_REG_CKG_I_MCU_MAIL0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0EE0_CKGEN01_V007_REG_CKG_S_MCU_MAIL0 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0EE8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xEE8)
	#define REG_0EE8_CKGEN01_V007_REG_CKG_G_MCU_MAIL1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0EE8_CKGEN01_V007_REG_CKG_I_MCU_MAIL1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0EE8_CKGEN01_V007_REG_CKG_S_MCU_MAIL1 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0EF0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xEF0)
	#define REG_0EF0_CKGEN01_V007_REG_CKG_G_VD2X Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0EF0_CKGEN01_V007_REG_CKG_I_VD2X Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0EF0_CKGEN01_V007_REG_CKG_S_VD2X Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0EF0_CKGEN01_V007_REG_CKG_G_VD2X_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0EF0_CKGEN01_V007_REG_CKG_I_VD2X_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0EF8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xEF8)
	#define REG_0EF8_CKGEN01_V007_REG_CKG_G_VD_32FSC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0EF8_CKGEN01_V007_REG_CKG_I_VD_32FSC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0EF8_CKGEN01_V007_REG_CKG_S_VD_32FSC Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0EF8_CKGEN01_V007_REG_CKG_G_VD_32FSC_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0EF8_CKGEN01_V007_REG_CKG_I_VD_32FSC_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0F00_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF00)
	#define REG_0F00_CKGEN01_V007_REG_CKG_G_VD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F00_CKGEN01_V007_REG_CKG_I_VD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F00_CKGEN01_V007_REG_CKG_S_VD Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0F00_CKGEN01_V007_REG_CKG_G_VD_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0F00_CKGEN01_V007_REG_CKG_I_VD_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0F08_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF08)
	#define REG_0F08_CKGEN01_V007_REG_CKG_G_CMBAI Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F08_CKGEN01_V007_REG_CKG_I_CMBAI Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0F10_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF10)
	#define REG_0F10_CKGEN01_V007_REG_CKG_G_CMBAO Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F10_CKGEN01_V007_REG_CKG_I_CMBAO Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0F18_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF18)
	#define REG_0F18_CKGEN01_V007_REG_CKG_G_CMBBI Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F18_CKGEN01_V007_REG_CKG_I_CMBBI Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0F20_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF20)
	#define REG_0F20_CKGEN01_V007_REG_CKG_G_CMBBO Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F20_CKGEN01_V007_REG_CKG_I_CMBBO Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0F40_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF40)
	#define REG_0F40_CKGEN01_V007_REG_CKG_G_VE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F40_CKGEN01_V007_REG_CKG_I_VE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F40_CKGEN01_V007_REG_CKG_S_VE Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0F48_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF48)
	#define REG_0F48_CKGEN01_V007_REG_CKG_G_VEDAC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F48_CKGEN01_V007_REG_CKG_I_VEDAC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F48_CKGEN01_V007_REG_CKG_S_VEDAC Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_0F50_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF50)
	#define REG_0F50_CKGEN01_V007_REG_CKG_G_VENC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F50_CKGEN01_V007_REG_CKG_I_VENC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F50_CKGEN01_V007_REG_CKG_S_VENC Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0F50_CKGEN01_V007_REG_CKG_G_VENC_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0F50_CKGEN01_V007_REG_CKG_I_VENC_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0F70_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF70)
	#define REG_0F70_CKGEN01_V007_REG_CKG_G_ECC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F70_CKGEN01_V007_REG_CKG_I_ECC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F70_CKGEN01_V007_REG_CKG_S_ECC Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_0F70_CKGEN01_V007_REG_CKG_G_ECC_TSP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0F70_CKGEN01_V007_REG_CKG_I_ECC_TSP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0F78_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF78)
	#define REG_0F78_CKGEN01_V007_REG_CKG_G_FCIE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F78_CKGEN01_V007_REG_CKG_I_FCIE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F78_CKGEN01_V007_REG_CKG_S_FCIE Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_0F80_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF80)
	#define REG_0F80_CKGEN01_V007_REG_CKG_S_FCIE_SYN Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0F90_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF90)
	#define REG_0F90_CKGEN01_V007_REG_CKG_G_GMAC_AHB Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0F90_CKGEN01_V007_REG_CKG_I_GMAC_AHB Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0F90_CKGEN01_V007_REG_CKG_S_GMAC_AHB Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0F90_CKGEN01_V007_REG_CKG_G_GMAC_AHB_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0F90_CKGEN01_V007_REG_CKG_I_GMAC_AHB_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0F98_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xF98)
	#define REG_0F98_CKGEN01_V007_REG_CKG_G_GMAC_RX_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0F98_CKGEN01_V007_REG_CKG_I_GMAC_RX_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0FA0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFA0)
	#define REG_0FA0_CKGEN01_V007_REG_CKG_G_GMAC_TX_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0FA0_CKGEN01_V007_REG_CKG_I_GMAC_TX_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0FC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFC0)
	#define REG_0FC0_CKGEN01_V007_REG_CKG_PEXTP_TL Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_0FC4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFC4)
	#define REG_0FC4_CKGEN01_V007_REG_CKG_G_SSUSB_USB20_PHY_CLK_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FC4_CKGEN01_V007_REG_CKG_I_SSUSB_USB20_PHY_CLK_TSP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0FC4_CKGEN01_V007_REG_CKG_S_SSUSB_USB20_PHY_CLK_TSP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0FC8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFC8)
	#define REG_0FC8_CKGEN01_V007_REG_CKG_G_SSUSB_USB20_PHY_CLK_1P_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FC8_CKGEN01_V007_REG_CKG_I_SSUSB_USB20_PHY_CLK_1P_TSP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0FC8_CKGEN01_V007_REG_CKG_S_SSUSB_USB20_PHY_CLK_1P_TSP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0FCC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFCC)
	#define REG_0FCC_CKGEN01_V007_REG_CKG_G_SSUSB_USB20_PHY_CLK_2P_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FCC_CKGEN01_V007_REG_CKG_I_SSUSB_USB20_PHY_CLK_2P_TSP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0FCC_CKGEN01_V007_REG_CKG_S_SSUSB_USB20_PHY_CLK_2P_TSP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0FD0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFD0)
	#define REG_0FD0_CKGEN01_V007_REG_CKG_G_SSUSB_FRMCNT_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FD0_CKGEN01_V007_REG_CKG_I_SSUSB_FRMCNT_TSP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0FD0_CKGEN01_V007_REG_CKG_S_SSUSB_FRMCNT_TSP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0FD0_CKGEN01_V007_REG_CKG_G_SSUSB_MISC_48M_TSP Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0FD0_CKGEN01_V007_REG_CKG_I_SSUSB_MISC_48M_TSP Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_0FD4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFD4)
	#define REG_0FD4_CKGEN01_V007_REG_CKG_G_SSUSB_PCLK_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FD4_CKGEN01_V007_REG_CKG_I_SSUSB_PCLK_TSP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0FD4_CKGEN01_V007_REG_CKG_S_SSUSB_PCLK_TSP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0FE8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFE8)
	#define REG_0FE8_CKGEN01_V007_REG_CKG_G_SSUSB_SYS_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FE8_CKGEN01_V007_REG_CKG_I_SSUSB_SYS_TSP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0FEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0xFEC)
	#define REG_0FEC_CKGEN01_V007_REG_CKG_G_SSUSB_XHCI_TSP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0FEC_CKGEN01_V007_REG_CKG_I_SSUSB_XHCI_TSP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1000_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1000)
	#define REG_1000_CKGEN01_V007_REG_CKG_UFS Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_1008_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1008)
	#define REG_1008_CKGEN01_V007_REG_CKG_UFS_AES Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_1018_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1018)
	#define REG_1018_CKGEN01_V007_REG_CKG_UFS_UNIPRO_CG_SYN Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_1028_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1028)
	#define REG_1028_CKGEN01_V007_REG_CKG_S_SMI_TSP_SEL Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1028_CKGEN01_V007_REG_CKG_G_SMI_SSUSB_SEL Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1028_CKGEN01_V007_REG_CKG_I_SMI_SSUSB_SEL Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1038_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1038)
	#define REG_1038_CKGEN01_V007_REG_CKG_G_FRC_R2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1038_CKGEN01_V007_REG_CKG_I_FRC_R2 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1038_CKGEN01_V007_REG_CKG_S_FRC_R2 Fld(2, 10, AC_MSKB1)//[11:10]
#define REG_1040_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1040)
	#define REG_1040_CKGEN01_V007_REG_CKG_G_MCU_NONPM Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1040_CKGEN01_V007_REG_CKG_I_MCU_NONPM Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1040_CKGEN01_V007_REG_CKG_S_MCU_NONPM Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_1040_CKGEN01_V007_REG_CKG_G_MCU_NONPM_DEMOD0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1040_CKGEN01_V007_REG_CKG_I_MCU_NONPM_DEMOD0 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1050_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1050)
	#define REG_1050_CKGEN01_V007_REG_CKG_G_MCU_NONPM_AIA Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1050_CKGEN01_V007_REG_CKG_I_MCU_NONPM_AIA Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1050_CKGEN01_V007_REG_CKG_G_MCU_NONPM_MHEG5 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1050_CKGEN01_V007_REG_CKG_I_MCU_NONPM_MHEG5 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_1058_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1058)
	#define REG_1058_CKGEN01_V007_REG_CKG_G_MCU_NONPM_EMI_TOP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1058_CKGEN01_V007_REG_CKG_I_MCU_NONPM_EMI_TOP Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1058_CKGEN01_V007_REG_CKG_G_MCU_NONPM_TSP Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1058_CKGEN01_V007_REG_CKG_I_MCU_NONPM_TSP Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_105C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x105C)
	#define REG_105C_CKGEN01_V007_REG_CKG_G_MCU_DB_BUS Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_105C_CKGEN01_V007_REG_CKG_I_MCU_DB_BUS Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_10E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x10E0)
	#define REG_10E0_CKGEN01_V007_REG_CKG_G_MCU_AU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_10E0_CKGEN01_V007_REG_CKG_I_MCU_AU Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_10E0_CKGEN01_V007_REG_CKG_S_MCU_AU Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_10F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x10F8)
	#define REG_10F8_CKGEN01_V007_REG_CKG_G_MCU_CODEC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_10F8_CKGEN01_V007_REG_CKG_I_MCU_CODEC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_10F8_CKGEN01_V007_REG_CKG_S_MCU_CODEC Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1110_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1110)
	#define REG_1110_CKGEN01_V007_REG_CKG_G_MCU_DMD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1110_CKGEN01_V007_REG_CKG_I_MCU_DMD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1110_CKGEN01_V007_REG_CKG_S_MCU_DMD Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_1110_CKGEN01_V007_REG_CKG_G_MCU_DMD_DEMOD0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1110_CKGEN01_V007_REG_CKG_I_MCU_DMD_DEMOD0 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1128_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1128)
	#define REG_1128_CKGEN01_V007_REG_CKG_G_MCU_FRC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1128_CKGEN01_V007_REG_CKG_I_MCU_FRC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1128_CKGEN01_V007_REG_CKG_S_MCU_FRC Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1140_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1140)
	#define REG_1140_CKGEN01_V007_REG_CKG_G_MCU_HDMI Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1140_CKGEN01_V007_REG_CKG_I_MCU_HDMI Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1140_CKGEN01_V007_REG_CKG_S_MCU_HDMI Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1170_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1170)
	#define REG_1170_CKGEN01_V007_REG_CKG_G_MCU_SC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1170_CKGEN01_V007_REG_CKG_I_MCU_SC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1170_CKGEN01_V007_REG_CKG_S_MCU_SC Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_11A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x11A0)
	#define REG_11A0_CKGEN01_V007_REG_CKG_G_MCU_VD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_11A0_CKGEN01_V007_REG_CKG_I_MCU_VD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_11A0_CKGEN01_V007_REG_CKG_S_MCU_VD Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_11A0_CKGEN01_V007_REG_CKG_G_MCU_VD_MHEG5 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_11A0_CKGEN01_V007_REG_CKG_I_MCU_VD_MHEG5 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_11B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x11B8)
	#define REG_11B8_CKGEN01_V007_REG_CKG_G_MCU_BUS Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_11B8_CKGEN01_V007_REG_CKG_I_MCU_BUS Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_11B8_CKGEN01_V007_REG_CKG_S_MCU_BUS Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_11C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x11C0)
	#define REG_11C0_CKGEN01_V007_REG_CKG_G_MCU_BUS_DEMOD0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_11C0_CKGEN01_V007_REG_CKG_I_MCU_BUS_DEMOD0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_11C0_CKGEN01_V007_REG_CKG_G_MCU_BUS_MHEG5 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_11C0_CKGEN01_V007_REG_CKG_I_MCU_BUS_MHEG5 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_11C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x11C4)
	#define REG_11C4_CKGEN01_V007_REG_CKG_G_MCU_BUS_TSP Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_11C4_CKGEN01_V007_REG_CKG_I_MCU_BUS_TSP Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_11F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x11F0)
	#define REG_11F0_CKGEN01_V007_REG_CKG_G_MIIC0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_11F0_CKGEN01_V007_REG_CKG_I_MIIC0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_11F0_CKGEN01_V007_REG_CKG_S_MIIC0 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_11F0_CKGEN01_V007_REG_CKG_G_MIIC0_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_11F0_CKGEN01_V007_REG_CKG_I_MIIC0_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_11F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x11F8)
	#define REG_11F8_CKGEN01_V007_REG_CKG_G_MIIC1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_11F8_CKGEN01_V007_REG_CKG_I_MIIC1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_11F8_CKGEN01_V007_REG_CKG_S_MIIC1 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_11F8_CKGEN01_V007_REG_CKG_G_MIIC1_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_11F8_CKGEN01_V007_REG_CKG_I_MIIC1_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1200_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1200)
	#define REG_1200_CKGEN01_V007_REG_CKG_G_MIIC2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1200_CKGEN01_V007_REG_CKG_I_MIIC2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1200_CKGEN01_V007_REG_CKG_S_MIIC2 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1200_CKGEN01_V007_REG_CKG_G_MIIC2_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1200_CKGEN01_V007_REG_CKG_I_MIIC2_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1208_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1208)
	#define REG_1208_CKGEN01_V007_REG_CKG_G_MIIC3 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1208_CKGEN01_V007_REG_CKG_I_MIIC3 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1208_CKGEN01_V007_REG_CKG_S_MIIC3 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1208_CKGEN01_V007_REG_CKG_G_MIIC3_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1208_CKGEN01_V007_REG_CKG_I_MIIC3_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1210_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1210)
	#define REG_1210_CKGEN01_V007_REG_CKG_G_MIIC4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1210_CKGEN01_V007_REG_CKG_I_MIIC4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1210_CKGEN01_V007_REG_CKG_S_MIIC4 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1210_CKGEN01_V007_REG_CKG_G_MIIC4_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1210_CKGEN01_V007_REG_CKG_I_MIIC4_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1214_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1214)
	#define REG_1214_CKGEN01_V007_REG_CKG_G_MIIC5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1214_CKGEN01_V007_REG_CKG_I_MIIC5 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1214_CKGEN01_V007_REG_CKG_S_MIIC5 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_1218_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1218)
	#define REG_1218_CKGEN01_V007_REG_CKG_G_PCM Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1218_CKGEN01_V007_REG_CKG_I_PCM Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1218_CKGEN01_V007_REG_CKG_S_PCM Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1218_CKGEN01_V007_REG_CKG_G_PCM_TSP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1218_CKGEN01_V007_REG_CKG_I_PCM_TSP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1220_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1220)
	#define REG_1220_CKGEN01_V007_REG_CKG_S_KG1 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_1230_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1230)
	#define REG_1230_CKGEN01_V007_REG_CKG_G_MSPI_CILINK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1230_CKGEN01_V007_REG_CKG_I_MSPI_CILINK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1230_CKGEN01_V007_REG_CKG_S_MSPI_CILINK Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1230_CKGEN01_V007_REG_CKG_G_MSPI_CILINK_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1230_CKGEN01_V007_REG_CKG_I_MSPI_CILINK_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1238_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1238)
	#define REG_1238_CKGEN01_V007_REG_CKG_G_MSPI_CILINK_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1238_CKGEN01_V007_REG_CKG_I_MSPI_CILINK_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1238_CKGEN01_V007_REG_CKG_S_MSPI_CILINK_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1240_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1240)
	#define REG_1240_CKGEN01_V007_REG_CKG_G_MSPI0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1240_CKGEN01_V007_REG_CKG_I_MSPI0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1240_CKGEN01_V007_REG_CKG_S_MSPI0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1240_CKGEN01_V007_REG_CKG_G_MSPI0_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1240_CKGEN01_V007_REG_CKG_I_MSPI0_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1248_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1248)
	#define REG_1248_CKGEN01_V007_REG_CKG_G_MSPI0_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1248_CKGEN01_V007_REG_CKG_I_MSPI0_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1248_CKGEN01_V007_REG_CKG_S_MSPI0_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1250_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1250)
	#define REG_1250_CKGEN01_V007_REG_CKG_G_MSPI1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1250_CKGEN01_V007_REG_CKG_I_MSPI1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1250_CKGEN01_V007_REG_CKG_S_MSPI1 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1250_CKGEN01_V007_REG_CKG_G_MSPI1_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1250_CKGEN01_V007_REG_CKG_I_MSPI1_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1258_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1258)
	#define REG_1258_CKGEN01_V007_REG_CKG_G_MSPI1_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1258_CKGEN01_V007_REG_CKG_I_MSPI1_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1258_CKGEN01_V007_REG_CKG_S_MSPI1_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1260_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1260)
	#define REG_1260_CKGEN01_V007_REG_CKG_G_MSPI2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1260_CKGEN01_V007_REG_CKG_I_MSPI2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1260_CKGEN01_V007_REG_CKG_S_MSPI2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1260_CKGEN01_V007_REG_CKG_G_MSPI2_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1260_CKGEN01_V007_REG_CKG_I_MSPI2_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1268_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1268)
	#define REG_1268_CKGEN01_V007_REG_CKG_G_MSPI2_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1268_CKGEN01_V007_REG_CKG_I_MSPI2_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1268_CKGEN01_V007_REG_CKG_S_MSPI2_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1270_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1270)
	#define REG_1270_CKGEN01_V007_REG_CKG_G_MSPI3 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1270_CKGEN01_V007_REG_CKG_I_MSPI3 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1270_CKGEN01_V007_REG_CKG_S_MSPI3 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1270_CKGEN01_V007_REG_CKG_G_MSPI3_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1270_CKGEN01_V007_REG_CKG_I_MSPI3_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1278_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1278)
	#define REG_1278_CKGEN01_V007_REG_CKG_G_MSPI3_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1278_CKGEN01_V007_REG_CKG_I_MSPI3_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1278_CKGEN01_V007_REG_CKG_S_MSPI3_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1280_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1280)
	#define REG_1280_CKGEN01_V007_REG_CKG_G_MSPI4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1280_CKGEN01_V007_REG_CKG_I_MSPI4 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1280_CKGEN01_V007_REG_CKG_S_MSPI4 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1280_CKGEN01_V007_REG_CKG_G_MSPI4_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1280_CKGEN01_V007_REG_CKG_I_MSPI4_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1288_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1288)
	#define REG_1288_CKGEN01_V007_REG_CKG_G_MSPI4_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1288_CKGEN01_V007_REG_CKG_I_MSPI4_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1288_CKGEN01_V007_REG_CKG_S_MSPI4_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_1290_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1290)
	#define REG_1290_CKGEN01_V007_REG_CKG_G_MSPI5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1290_CKGEN01_V007_REG_CKG_I_MSPI5 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1290_CKGEN01_V007_REG_CKG_S_MSPI5 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1290_CKGEN01_V007_REG_CKG_G_MSPI5_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1290_CKGEN01_V007_REG_CKG_I_MSPI5_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1298_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1298)
	#define REG_1298_CKGEN01_V007_REG_CKG_G_MSPI5_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1298_CKGEN01_V007_REG_CKG_I_MSPI5_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1298_CKGEN01_V007_REG_CKG_S_MSPI5_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_12A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12A0)
	#define REG_12A0_CKGEN01_V007_REG_CKG_G_MSPI6 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12A0_CKGEN01_V007_REG_CKG_I_MSPI6 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12A0_CKGEN01_V007_REG_CKG_S_MSPI6 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_12A0_CKGEN01_V007_REG_CKG_G_MSPI6_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_12A0_CKGEN01_V007_REG_CKG_I_MSPI6_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_12A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12A8)
	#define REG_12A8_CKGEN01_V007_REG_CKG_G_MSPI6_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12A8_CKGEN01_V007_REG_CKG_I_MSPI6_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12A8_CKGEN01_V007_REG_CKG_S_MSPI6_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_12B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12B0)
	#define REG_12B0_CKGEN01_V007_REG_CKG_G_MSPI7 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12B0_CKGEN01_V007_REG_CKG_I_MSPI7 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12B0_CKGEN01_V007_REG_CKG_S_MSPI7 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_12B0_CKGEN01_V007_REG_CKG_G_MSPI7_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_12B0_CKGEN01_V007_REG_CKG_I_MSPI7_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_12B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12B8)
	#define REG_12B8_CKGEN01_V007_REG_CKG_G_MSPI7_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12B8_CKGEN01_V007_REG_CKG_I_MSPI7_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12B8_CKGEN01_V007_REG_CKG_S_MSPI7_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_12C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12C0)
	#define REG_12C0_CKGEN01_V007_REG_CKG_G_FRC_MSPI0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12C0_CKGEN01_V007_REG_CKG_I_FRC_MSPI0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12C0_CKGEN01_V007_REG_CKG_S_FRC_MSPI0 Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_12D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12D0)
	#define REG_12D0_CKGEN01_V007_REG_CKG_G_FRC_MSPI0_DIV Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12D0_CKGEN01_V007_REG_CKG_I_FRC_MSPI0_DIV Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12D0_CKGEN01_V007_REG_CKG_S_FRC_MSPI0_DIV Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_12E8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12E8)
	#define REG_12E8_CKGEN01_V007_REG_CKG_G_SPI Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12E8_CKGEN01_V007_REG_CKG_I_SPI Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12E8_CKGEN01_V007_REG_CKG_S_SPI Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_12E8_CKGEN01_V007_REG_CKG_G_SPI_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_12E8_CKGEN01_V007_REG_CKG_I_SPI_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_12F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x12F0)
	#define REG_12F0_CKGEN01_V007_REG_CKG_G_FRCPLL_SYN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_12F0_CKGEN01_V007_REG_CKG_I_FRCPLL_SYN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_12F0_CKGEN01_V007_REG_CKG_S_FRCPLL_SYN Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_1368_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1368)
	#define REG_1368_CKGEN01_V007_REG_CKG_G_UART0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1368_CKGEN01_V007_REG_CKG_I_UART0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1368_CKGEN01_V007_REG_CKG_S_UART0 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1368_CKGEN01_V007_REG_CKG_G_UART0_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1368_CKGEN01_V007_REG_CKG_I_UART0_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1370_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1370)
	#define REG_1370_CKGEN01_V007_REG_CKG_G_UART0_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1370_CKGEN01_V007_REG_CKG_I_UART0_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1370_CKGEN01_V007_REG_CKG_S_UART0_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_1378_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1378)
	#define REG_1378_CKGEN01_V007_REG_CKG_G_UART1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1378_CKGEN01_V007_REG_CKG_I_UART1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1378_CKGEN01_V007_REG_CKG_S_UART1 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1378_CKGEN01_V007_REG_CKG_G_UART1_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1378_CKGEN01_V007_REG_CKG_I_UART1_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1380_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1380)
	#define REG_1380_CKGEN01_V007_REG_CKG_G_UART1_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1380_CKGEN01_V007_REG_CKG_I_UART1_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1380_CKGEN01_V007_REG_CKG_S_UART1_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_1388_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1388)
	#define REG_1388_CKGEN01_V007_REG_CKG_G_UART2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1388_CKGEN01_V007_REG_CKG_I_UART2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1388_CKGEN01_V007_REG_CKG_S_UART2 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1388_CKGEN01_V007_REG_CKG_G_UART2_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1388_CKGEN01_V007_REG_CKG_I_UART2_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1390_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1390)
	#define REG_1390_CKGEN01_V007_REG_CKG_G_UART2_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1390_CKGEN01_V007_REG_CKG_I_UART2_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1390_CKGEN01_V007_REG_CKG_S_UART2_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_1398_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1398)
	#define REG_1398_CKGEN01_V007_REG_CKG_G_FRC_UART0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1398_CKGEN01_V007_REG_CKG_I_FRC_UART0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1398_CKGEN01_V007_REG_CKG_S_FRC_UART0 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13A0)
	#define REG_13A0_CKGEN01_V007_REG_CKG_G_FRC_UART0_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13A0_CKGEN01_V007_REG_CKG_I_FRC_UART0_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13A0_CKGEN01_V007_REG_CKG_S_FRC_UART0_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13A8)
	#define REG_13A8_CKGEN01_V007_REG_CKG_G_FRC_UART1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13A8_CKGEN01_V007_REG_CKG_I_FRC_UART1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13A8_CKGEN01_V007_REG_CKG_S_FRC_UART1 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13B0)
	#define REG_13B0_CKGEN01_V007_REG_CKG_G_FRC_UART1_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13B0_CKGEN01_V007_REG_CKG_I_FRC_UART1_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13B0_CKGEN01_V007_REG_CKG_S_FRC_UART1_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13B8)
	#define REG_13B8_CKGEN01_V007_REG_CKG_G_FUART0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13B8_CKGEN01_V007_REG_CKG_I_FUART0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13B8_CKGEN01_V007_REG_CKG_S_FUART0 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_13B8_CKGEN01_V007_REG_CKG_G_FUART0_MHEG5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_13B8_CKGEN01_V007_REG_CKG_I_FUART0_MHEG5 Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_13C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13C0)
	#define REG_13C0_CKGEN01_V007_REG_CKG_G_FUART0_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13C0_CKGEN01_V007_REG_CKG_I_FUART0_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13C0_CKGEN01_V007_REG_CKG_S_FUART0_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13C8)
	#define REG_13C8_CKGEN01_V007_REG_CKG_G_AU_UART0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13C8_CKGEN01_V007_REG_CKG_I_AU_UART0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13C8_CKGEN01_V007_REG_CKG_S_AU_UART0 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_13C8_CKGEN01_V007_REG_CKG_G_AU_UART1 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_13C8_CKGEN01_V007_REG_CKG_I_AU_UART1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_13C8_CKGEN01_V007_REG_CKG_S_AU_UART1 Fld(2, 6, AC_MSKB0)//[7:6]
#define REG_13CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13CC)
	#define REG_13CC_CKGEN01_V007_REG_CKG_G_AU_UART2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13CC_CKGEN01_V007_REG_CKG_I_AU_UART2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13CC_CKGEN01_V007_REG_CKG_S_AU_UART2 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13D0)
	#define REG_13D0_CKGEN01_V007_REG_CKG_G_AU_UART0_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13D0_CKGEN01_V007_REG_CKG_I_AU_UART0_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13D0_CKGEN01_V007_REG_CKG_S_AU_UART0_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_13D0_CKGEN01_V007_REG_CKG_G_AU_UART1_SYNTH Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_13D0_CKGEN01_V007_REG_CKG_I_AU_UART1_SYNTH Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_13D0_CKGEN01_V007_REG_CKG_S_AU_UART1_SYNTH Fld(2, 6, AC_MSKB0)//[7:6]
#define REG_13D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13D4)
	#define REG_13D4_CKGEN01_V007_REG_CKG_G_AU_UART2_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13D4_CKGEN01_V007_REG_CKG_I_AU_UART2_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13D4_CKGEN01_V007_REG_CKG_S_AU_UART2_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13D8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13D8)
	#define REG_13D8_CKGEN01_V007_REG_CKG_G_FRC_FUART0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13D8_CKGEN01_V007_REG_CKG_I_FRC_FUART0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13D8_CKGEN01_V007_REG_CKG_S_FRC_FUART0 Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_13E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x13E0)
	#define REG_13E0_CKGEN01_V007_REG_CKG_G_FRC_FUART0_SYNTH Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_13E0_CKGEN01_V007_REG_CKG_I_FRC_FUART0_SYNTH Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_13E0_CKGEN01_V007_REG_CKG_S_FRC_FUART0_SYNTH Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_1498_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1498)
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_002GPO Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_012GPO Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_022GPO Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_032GPO Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_042GPO Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_052GPO Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_062GPO Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_072GPO Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_082GPO Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_092GPO Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_102GPO Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_112GPO Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_122GPO Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_132GPO Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_142GPO Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1498_CKGEN01_V007_REG_SW_EN_GPO_152GPO Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_14A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14A0)
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_162GPO Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_172GPO Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_182GPO Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_192GPO Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_202GPO Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_212GPO Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_222GPO Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_232GPO Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_GPO_ZONE2GPO Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_MOD_V1_SR_WCLK2TCON Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_PWM_DAC2PWM_DAC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG72TCON Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_XTAL_12M2TCON Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_14A0_CKGEN01_V007_REG_SW_EN_V1_DET_ODCLK2DET Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_14A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14A4)
	#define REG_14A4_CKGEN01_V007_REG_SW_EN_CLKD_ADC2DACA2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14A8)
	#define REG_14A8_CKGEN01_V007_REG_SW_EN_CLKD_ADC2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14AC)
	#define REG_14AC_CKGEN01_V007_REG_SW_EN_CLKD_ADC2GEMIU2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14B0)
	#define REG_14B0_CKGEN01_V007_REG_SW_EN_CLKD_ADC2SC2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14B4)
	#define REG_14B4_CKGEN01_V007_REG_SW_EN_CLKD_FBLANK2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14B8)
	#define REG_14B8_CKGEN01_V007_REG_SW_EN_CLKD_VD2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14BC)
	#define REG_14BC_CKGEN01_V007_REG_SW_EN_CLKFSCX2_VD2ADC_TOP_DATA Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14C0)
	#define REG_14C0_CKGEN01_V007_REG_SW_EN_ADC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14C4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14C4)
	#define REG_14C4_CKGEN01_V007_REG_SW_EN_ADC2MIU2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14C8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14C8)
	#define REG_14C8_CKGEN01_V007_REG_SW_EN_ADC2MIUSC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14CC)
	#define REG_14CC_CKGEN01_V007_REG_SW_EN_ADC2SC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14D0)
	#define REG_14D0_CKGEN01_V007_REG_SW_EN_OCC_SLOW2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14D4)
	#define REG_14D4_CKGEN01_V007_REG_SW_EN_ADCPLL4002ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14D8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14D8)
	#define REG_14D8_CKGEN01_V007_REG_SW_EN_B_ADC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14DC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14DC)
	#define REG_14DC_CKGEN01_V007_REG_SW_EN_B_INT2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14E0)
	#define REG_14E0_CKGEN01_V007_REG_SW_EN_CLKPLL2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14E4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14E4)
	#define REG_14E4_CKGEN01_V007_REG_SW_EN_CVBS_DAC_A_DIGITAL0_MUX2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14E8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14E8)
	#define REG_14E8_CKGEN01_V007_REG_SW_EN_CVBS_DAC_A_DIGITAL02ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14EC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14EC)
	#define REG_14EC_CKGEN01_V007_REG_SW_EN_CVBS_DAC_A_DIGITAL12ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14F0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14F0)
	#define REG_14F0_CKGEN01_V007_REG_SW_EN_DIG_2162ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14F4)
	#define REG_14F4_CKGEN01_V007_REG_SW_EN_FBLANK2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_14F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x14F8)
	#define REG_14F8_CKGEN01_V007_REG_SW_EN_FSC_VD2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1500_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1500)
	#define REG_1500_CKGEN01_V007_REG_SW_EN_G_ADC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1504_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1504)
	#define REG_1504_CKGEN01_V007_REG_SW_EN_G_INT2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1508_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1508)
	#define REG_1508_CKGEN01_V007_REG_SW_EN_ISOG2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1510_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1510)
	#define REG_1510_CKGEN01_V007_REG_SW_EN_NCO_CLK2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1518_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1518)
	#define REG_1518_CKGEN01_V007_REG_SW_EN_R_ADC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_151C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x151C)
	#define REG_151C_CKGEN01_V007_REG_SW_EN_R_INT2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1520_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1520)
	#define REG_1520_CKGEN01_V007_REG_SW_EN_VD_ICLAMP2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1524_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1524)
	#define REG_1524_CKGEN01_V007_REG_SW_EN_VD_ICLAMP2VIDEO_ATOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1528_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1528)
	#define REG_1528_CKGEN01_V007_REG_SW_EN_VD_NCO_CLK2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_152C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x152C)
	#define REG_152C_CKGEN01_V007_REG_SW_EN_VD2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1530_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1530)
	#define REG_1530_CKGEN01_V007_REG_SW_EN_VDPLL4002ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1534_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1534)
	#define REG_1534_CKGEN01_V007_REG_SW_EN_XTAL12_4INTERRUPT2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1538_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1538)
	#define REG_1538_CKGEN01_V007_REG_SW_EN_XTAL12_4PLUGDET2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_153C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x153C)
	#define REG_153C_CKGEN01_V007_REG_SW_EN_XTAL122ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1540_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1540)
	#define REG_1540_CKGEN01_V007_REG_SW_EN_XTAL242ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1544_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1544)
	#define REG_1544_CKGEN01_V007_REG_SW_EN_Y_ADC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1548_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1548)
	#define REG_1548_CKGEN01_V007_REG_SW_EN_Y_INT2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_154C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x154C)
	#define REG_154C_CKGEN01_V007_REG_SW_EN_YUV_ADC2ADC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1554_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1554)
	#define REG_1554_CKGEN01_V007_REG_SW_EN_GCE_F26M2GCE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1554_CKGEN01_V007_REG_SW_EN_SMI_GCE2GCE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1554_CKGEN01_V007_REG_SW_EN_VDEC_SYS_F2CORE0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1554_CKGEN01_V007_REG_SW_EN_VDEC_SYS_S2CORE0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1554_CKGEN01_V007_REG_SW_EN_XIU_GCE2GCE Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_1558_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1558)
	#define REG_1558_CKGEN01_V007_REG_SW_EN_SMI2CORE0_MERGE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1558_CKGEN01_V007_REG_SW_EN_VDEC_SYS_F2CORE0_MERGE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1558_CKGEN01_V007_REG_SW_EN_VDEC_SYS_S2CORE0_MERGE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1558_CKGEN01_V007_REG_SW_EN_VDEC_BUS2CORE0_MERGE Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_1564_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1564)
	#define REG_1564_CKGEN01_V007_REG_SW_EN_DISP_MFDEC2GPU_PAR_GP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15A8)
	#define REG_15A8_CKGEN01_V007_REG_SW_EN_XTAL2TIMER Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15AC)
	#define REG_15AC_CKGEN01_V007_REG_SW_EN_XTAL2PQU Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15B0)
	#define REG_15B0_CKGEN01_V007_REG_SW_EN_XTAL2AURV55MBIST Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15B8)
	#define REG_15B8_CKGEN01_V007_REG_SW_EN_XTAL2AUDEC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15BC)
	#define REG_15BC_CKGEN01_V007_REG_SW_EN_XTAL2AUSND Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15CC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15CC)
	#define REG_15CC_CKGEN01_V007_REG_SW_EN_GE_FIFO_R2GE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15D0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15D0)
	#define REG_15D0_CKGEN01_V007_REG_SW_EN_GE_FIFO_W2GE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15D4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15D4)
	#define REG_15D4_CKGEN01_V007_REG_SW_EN_GE_PSRAM2GE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15D8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15D8)
	#define REG_15D8_CKGEN01_V007_REG_SW_EN_GE2GE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_15E0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x15E0)
	#define REG_15E0_CKGEN01_V007_REG_SW_EN_XTAL_24M2SEC_R2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_17F4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x17F4)
	#define REG_17F4_CKGEN01_V007_REG_SW_EN_DET_RCLK2DET Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_17F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x17F8)
	#define REG_17F8_CKGEN01_V007_REG_SW_EN_DET_WCLK2DET Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_17FC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x17FC)
	#define REG_17FC_CKGEN01_V007_REG_SW_EN_IDCLK2FPLL Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1800_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1800)
	#define REG_1800_CKGEN01_V007_REG_SW_EN_LPLL_ODCLK_NODIV2FPLL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1800_CKGEN01_V007_REG_SW_EN_LPLL_ODCLK_NODIV2TTL Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1804_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1804)
	#define REG_1804_CKGEN01_V007_REG_SW_EN_LPLL_ODCLK2FPLL Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1808_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1808)
	#define REG_1808_CKGEN01_V007_REG_SW_EN_LPLL_SYN_4322FPLL Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1810_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1810)
	#define REG_1810_CKGEN01_V007_REG_SW_EN_MOD_A_ODCLK2MOD_A Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1814_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1814)
	#define REG_1814_CKGEN01_V007_REG_SW_EN_MOD_D_ODCLK2MOD_D Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1814_CKGEN01_V007_REG_SW_EN_MOD_D_ODCLK2LVDS Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1814_CKGEN01_V007_REG_SW_EN_MOD_D_ODCLK2TTL Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_1818_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1818)
	#define REG_1818_CKGEN01_V007_REG_SW_EN_MOD_O_SR_WCLK2O Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1818_CKGEN01_V007_REG_SW_EN_MOD_O_SR_WCLK2VBY1_O Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_181C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x181C)
	#define REG_181C_CKGEN01_V007_REG_SW_EN_MOD_V1_SR_WCLK2V1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_181C_CKGEN01_V007_REG_SW_EN_MOD_V1_SR_WCLK2VBY1_V1 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1820_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1820)
	#define REG_1820_CKGEN01_V007_REG_SW_EN_MOD_V2_SR_WCLK2V2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1820_CKGEN01_V007_REG_SW_EN_MOD_V2_SR_WCLK2VBY1_V2 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1824_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1824)
	#define REG_1824_CKGEN01_V007_REG_SW_EN_O_MOD_SR_RCLK2O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1828_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1828)
	#define REG_1828_CKGEN01_V007_REG_SW_EN_O_ODCLK_STG12O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_182C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x182C)
	#define REG_182C_CKGEN01_V007_REG_SW_EN_O_ODCLK_STG22O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1830_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1830)
	#define REG_1830_CKGEN01_V007_REG_SW_EN_O_ODCLK_STG32O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1834_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1834)
	#define REG_1834_CKGEN01_V007_REG_SW_EN_O_ODCLK_STG42O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1838_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1838)
	#define REG_1838_CKGEN01_V007_REG_SW_EN_O_ODCLK_STG52O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_183C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x183C)
	#define REG_183C_CKGEN01_V007_REG_SW_EN_O_ODCLK_STG62O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1840_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1840)
	#define REG_1840_CKGEN01_V007_REG_SW_EN_O_ODCLK2O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1844_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1844)
	#define REG_1844_CKGEN01_V007_REG_SW_EN_PWM2PWM Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1848_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1848)
	#define REG_1848_CKGEN01_V007_REG_SW_EN_V1_MOD_SR_RCLK2V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_184C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x184C)
	#define REG_184C_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG12V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1850_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1850)
	#define REG_1850_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG22V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1854_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1854)
	#define REG_1854_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG32V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1858_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1858)
	#define REG_1858_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG42V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_185C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x185C)
	#define REG_185C_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG52V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1860_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1860)
	#define REG_1860_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG62V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1864_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1864)
	#define REG_1864_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG72V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1868_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1868)
	#define REG_1868_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG82V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_186C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x186C)
	#define REG_186C_CKGEN01_V007_REG_SW_EN_V1_ODCLK2V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1870_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1870)
	#define REG_1870_CKGEN01_V007_REG_SW_EN_V2_MOD_SR_RCLK2V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1874_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1874)
	#define REG_1874_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG12V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1878_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1878)
	#define REG_1878_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG22V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_187C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x187C)
	#define REG_187C_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG32V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1880_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1880)
	#define REG_1880_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG42V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1884_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1884)
	#define REG_1884_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG52V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1888_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1888)
	#define REG_1888_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG62V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_188C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x188C)
	#define REG_188C_CKGEN01_V007_REG_SW_EN_V2_ODCLK_STG72V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1890_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1890)
	#define REG_1890_CKGEN01_V007_REG_SW_EN_V2_ODCLK2V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1894_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1894)
	#define REG_1894_CKGEN01_V007_REG_SW_EN_XTAL_12M2MOD_A Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1894_CKGEN01_V007_REG_SW_EN_XTAL_12M2PWM Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1898_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1898)
	#define REG_1898_CKGEN01_V007_REG_SW_EN_XTAL_24M2FPLL Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_189C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x189C)
	#define REG_189C_CKGEN01_V007_REG_SW_EN_O_MOD_SR_RCLK_FINIAL2O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18A0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18A0)
	#define REG_18A0_CKGEN01_V007_REG_SW_EN_O_MOD_SR_RCLK_PRE02O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18A4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18A4)
	#define REG_18A4_CKGEN01_V007_REG_SW_EN_O_MOD_SR_RCLK_PRE12O Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18A8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18A8)
	#define REG_18A8_CKGEN01_V007_REG_SW_EN_V1_MOD_SR_RCLK_FINIAL2V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18AC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18AC)
	#define REG_18AC_CKGEN01_V007_REG_SW_EN_V1_MOD_SR_RCLK_PRE02V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18B0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18B0)
	#define REG_18B0_CKGEN01_V007_REG_SW_EN_V1_MOD_SR_RCLK_PRE12V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18B4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18B4)
	#define REG_18B4_CKGEN01_V007_REG_SW_EN_V2_MOD_SR_RCLK_FINIAL2V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18B8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18B8)
	#define REG_18B8_CKGEN01_V007_REG_SW_EN_V2_MOD_SR_RCLK_PRE02V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18BC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18BC)
	#define REG_18BC_CKGEN01_V007_REG_SW_EN_V2_MOD_SR_RCLK_PRE12V2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_18C0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x18C0)
	#define REG_18C0_CKGEN01_V007_REG_SW_EN_V1_ODCLK_STG92V1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_192C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x192C)
	#define REG_192C_CKGEN01_V007_REG_CKG_G_APUPLL_SYN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_192C_CKGEN01_V007_REG_CKG_I_APUPLL_SYN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_192C_CKGEN01_V007_REG_CKG_S_APUPLL_SYN Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_196C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x196C)
	#define REG_196C_CKGEN01_V007_REG_SW_EN_APUPLL_SYN2APUPLL Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1978_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1978)
	#define REG_1978_CKGEN01_V007_REG_APUPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1978_CKGEN01_V007_REG_APUPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1978_CKGEN01_V007_REG_APUPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_197C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x197C)
	#define REG_197C_CKGEN01_V007_REG_APUPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_19E8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x19E8)
	#define REG_19E8_CKGEN01_V007_REG_SW_EN_XCPLL_SYN2XCPLL_DMACRO Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_19F8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x19F8)
	#define REG_19F8_CKGEN01_V007_REG_APUPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A2C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A2C)
	#define REG_1A2C_CKGEN01_V007_REG_SW_EN_CMBAI2VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A30_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A30)
	#define REG_1A30_CKGEN01_V007_REG_SW_EN_CMBAO2VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A34_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A34)
	#define REG_1A34_CKGEN01_V007_REG_SW_EN_CMBBI2VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A38_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A38)
	#define REG_1A38_CKGEN01_V007_REG_SW_EN_CMBBO2VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A3C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A3C)
	#define REG_1A3C_CKGEN01_V007_REG_SW_EN_MCU_MAIL02VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A40_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A40)
	#define REG_1A40_CKGEN01_V007_REG_SW_EN_MCU_MAIL12VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A44_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A44)
	#define REG_1A44_CKGEN01_V007_REG_SW_EN_VD_32FSC2VD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1A48_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A48)
	#define REG_1A48_CKGEN01_V007_REG_SW_EN_VD2MHEG5_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1A48_CKGEN01_V007_REG_SW_EN_VD2VD Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1A4C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A4C)
	#define REG_1A4C_CKGEN01_V007_REG_SW_EN_VD2X2MHEG5_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1A4C_CKGEN01_V007_REG_SW_EN_VD2X2VD Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1A58_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1A58)
	#define REG_1A58_CKGEN01_V007_REG_SW_EN_VENC2VENC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1A58_CKGEN01_V007_REG_SW_EN_VENC2VENC_IP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1AAC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AAC)
	#define REG_1AAC_CKGEN01_V007_REG_SW_EN_GMAC_AHB2GMAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AB0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AB0)
	#define REG_1AB0_CKGEN01_V007_REG_SW_EN_GMAC_REF2GMAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AB4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AB4)
	#define REG_1AB4_CKGEN01_V007_REG_SW_EN_GMAC_RX2GMAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AB8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AB8)
	#define REG_1AB8_CKGEN01_V007_REG_SW_EN_GMAC_TX2GMAC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1ACC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1ACC)
	#define REG_1ACC_CKGEN01_V007_REG_SW_EN_AU_UART0_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1ACC_CKGEN01_V007_REG_SW_EN_AU_UART1_SYNTH2MCU_CKCTRL_TOP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1ACC_CKGEN01_V007_REG_SW_EN_AU_UART2_SYNTH2MCU_CKCTRL_TOP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_1AD4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AD4)
	#define REG_1AD4_CKGEN01_V007_REG_SW_EN_FRC_FUART0_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1ADC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1ADC)
	#define REG_1ADC_CKGEN01_V007_REG_SW_EN_FRC_MSPI0_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AE4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AE4)
	#define REG_1AE4_CKGEN01_V007_REG_SW_EN_FRC_UART0_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AEC)
	#define REG_1AEC_CKGEN01_V007_REG_SW_EN_FRC_UART1_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AF4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AF4)
	#define REG_1AF4_CKGEN01_V007_REG_SW_EN_FUART0_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AF8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AF8)
	#define REG_1AF8_CKGEN01_V007_REG_SW_EN_FUART02MCU_FUART0 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1AFC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1AFC)
	#define REG_1AFC_CKGEN01_V007_REG_SW_EN_UART0_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B00_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B00)
	#define REG_1B00_CKGEN01_V007_REG_SW_EN_UART02MCU_UART0 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B04_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B04)
	#define REG_1B04_CKGEN01_V007_REG_SW_EN_UART1_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B08_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B08)
	#define REG_1B08_CKGEN01_V007_REG_SW_EN_UART12MCU_UART1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B0C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B0C)
	#define REG_1B0C_CKGEN01_V007_REG_SW_EN_UART2_SYNTH2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B10_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B10)
	#define REG_1B10_CKGEN01_V007_REG_SW_EN_UART22MCU_UART2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B18_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B18)
	#define REG_1B18_CKGEN01_V007_REG_SW_EN_FRCPLL_SYN2FRCPLL Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1B24_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B24)
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_DVBT2_INNER4X_SRD0P5X Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_DVBT2_INNER4X_SRD0P5X Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_DVBT2_INNER8X Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_DVBT2_INNER8X Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_DVBTM_SRAM_T12X_T28X Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_DVBTM_SRAM_T12X_T28X Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_DVBTM_SRAM_T12X_T28X_SRD1X Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_DVBTM_SRAM_T12X_T28X_SRD1X Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_DVBTM_SRAM_T14X_T28X_SRD1X_VIFDAC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_DVBTM_SRAM_T14X_T28X_SRD1X_VIFDAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_DVBTM_SRAM_T14X_T28X_SRD1X_VIFSSC Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_DVBTM_SRAM_T14X_T28X_SRD1X_VIFSSC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_01 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_01 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B24_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_02 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1B24_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_02 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B28_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B28)
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_03 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_03 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_04 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_04 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_06_07 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_06_07 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_104_105_106 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_104_105_106 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_107_108 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_107_108 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_112_TO_119 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_112_TO_119 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_120_121_122_123 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_120_121_122_123 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B28_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_124_125 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1B28_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_124_125 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B2C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B2C)
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_126_127 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_126_127 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_149_150_151_152 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_149_150_151_152 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_155 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_155 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_156_R Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_156_R Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_156_W Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_156_W Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_157_R Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_157_R Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_157_W Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_157_W Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_16_17 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1B2C_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_16_17 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B30_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B30)
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_24_25 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_24_25 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_29_30_31_32_33 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_29_30_31_32_33 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_34_35_36_38 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_34_35_36_38 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_37_39_40_41 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_37_39_40_41 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_42_43_44 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_42_43_44 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_45_46 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_45_46 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_47_48_49 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_47_48_49 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B30_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_50_51_52_53 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1B30_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_50_51_52_53 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B34_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B34)
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_54 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_54 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_55 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_55 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_68_0_69_0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_68_0_69_0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_68_1 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_68_1 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_68_2_69_2_70_2_71_2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_68_2_69_2_70_2_71_2 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_68_3_69_3_70_3_71_3 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_68_3_69_3_70_3_71_3 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_69_1 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_69_1 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B34_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_70_0_70_0 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1B34_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_70_0_71_0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B38_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B38)
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_70_1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_70_1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_71_1 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_71_1 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_87_88 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_87_88 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_89_90 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_89_90 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_94_95 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_94_95 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_96_97 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_96_97 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B38_CKGEN01_V007_REG_CKG_G_SRAM_SHARE_99_100_101_102 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B38_CKGEN01_V007_REG_CKG_I_SRAM_SHARE_99_100_101_102 Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_1B4C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B4C)
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_BUS2DEMOD0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_BUS2MCU_M2MCU Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_BUS2MCU_NONPM_RIU_BRIDGE Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_BUS2MCU_CODEC_RIU_BRIDGE Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_BUS2MCUSYS_XIU_BRIDGE Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_BUS2BLK Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B4C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2SEC_R2 Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_1B54_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B54)
	#define REG_1B54_CKGEN01_V007_REG_SW_EN_MCU_CODEC2MCU_CODEC_RIU_BRIDGE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B54_CKGEN01_V007_REG_SW_EN_MCU_CODEC2SECURE_TOP_CODEC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_1B5C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B5C)
	#define REG_1B5C_CKGEN01_V007_REG_SW_EN_MCU_DMD2DEMOD0 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1B74_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B74)
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2CHIP_REG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2CMDQ Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2DEMOD0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2DSCRMB Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2FCIE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2PAD_TOP Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_BDMA_VDEC Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2GE Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2GMAC Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2GPD Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2INTR_CTRL_TOP_WP Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B74_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_BDMA Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B78_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B78)
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_DEMURA Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_FUART Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MAILBOX0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MAILBOX1 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MAILBOX2 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MAILBOX3 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MAILBOX4 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MAILBOX5 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MCUIF Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MIIC0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MIIC1 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MIIC2 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MIIC3 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MSPI_ALL Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_FMLY_ROM Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1B78_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_NONPM_RIU_BRIDGE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B7C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B7C)
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_UART0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_UART1 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_UART2 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_XD2MIU Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCUSYS_XIU_BRIDGE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MHEG5_SMI Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2PEXTP Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B7C_CKGEN01_V007_REG_SW_EN_MCU_NONPM2PREARB2PM_RIU_TOP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_1B80_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B80)
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2SMART0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2SMART1 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2SSUSB Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2TSP Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2TSP_SMI Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2UFS Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1B80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2USB20 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1B84_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B84)
	#define REG_1B84_CKGEN01_V007_REG_SW_EN_MCU_NONPM2VD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B84_CKGEN01_V007_REG_SW_EN_MCU_NONPM2VENC Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B84_CKGEN01_V007_REG_SW_EN_MCU_NONPM2XIU2APB Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1B84_CKGEN01_V007_REG_SW_EN_MCU_NONPM2EMI_TOP Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_1B88_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1B88)
	#define REG_1B88_CKGEN01_V007_REG_SW_EN_EMI22XPU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1B88_CKGEN01_V007_REG_SW_EN_INFRA_RX2AIATOP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1B88_CKGEN01_V007_REG_SW_EN_MCU_NONPM2AIA_SMI Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1B88_CKGEN01_V007_REG_SW_EN_SMI2AIA_SMI Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_1BAC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BAC)
	#define REG_1BAC_CKGEN01_V007_REG_SW_EN_MCU_VD2MCU_M2MCU Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1BAC_CKGEN01_V007_REG_SW_EN_MCU_VD2MCU_MCUIF Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1BAC_CKGEN01_V007_REG_SW_EN_MCU_VD2VD Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_1BB8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BB8)
	#define REG_1BB8_CKGEN01_V007_REG_SW_EN_IRS2IRS Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BBC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BBC)
	#define REG_1BBC_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_IRS Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BC0)
	#define REG_1BC0_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MCU_MIIC4 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BC4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BC4)
	#define REG_1BC4_CKGEN01_V007_REG_SW_EN_MIIC02MCU_MIIC0 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BC8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BC8)
	#define REG_1BC8_CKGEN01_V007_REG_SW_EN_MIIC12MCU_MIIC1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BCC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BCC)
	#define REG_1BCC_CKGEN01_V007_REG_SW_EN_MIIC22MCU_MIIC2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BD0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BD0)
	#define REG_1BD0_CKGEN01_V007_REG_SW_EN_MIIC32MCU_MIIC3 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BD4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BD4)
	#define REG_1BD4_CKGEN01_V007_REG_SW_EN_MIIC42MCU_MIIC4 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BD8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BD8)
	#define REG_1BD8_CKGEN01_V007_REG_SW_EN_PCM2PIU Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BDC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BDC)
	#define REG_1BDC_CKGEN01_V007_REG_SW_EN_SMI2MCU_MIIC4 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BE0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BE0)
	#define REG_1BE0_CKGEN01_V007_REG_SW_EN_XTAL_12M2MCU_MIIC4 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BE4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BE4)
	#define REG_1BE4_CKGEN01_V007_REG_SW_EN_MSPI12MCU_MSPI1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BE8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BE8)
	#define REG_1BE8_CKGEN01_V007_REG_SW_EN_MSPI22MCU_MSPI2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BEC)
	#define REG_1BEC_CKGEN01_V007_REG_SW_EN_MSPI32MCU_MSPI3 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BF0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BF0)
	#define REG_1BF0_CKGEN01_V007_REG_SW_EN_MSPI42MCU_MSPI4 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BF4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BF4)
	#define REG_1BF4_CKGEN01_V007_REG_SW_EN_MSPI52MCU_MSPI5 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BF8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BF8)
	#define REG_1BF8_CKGEN01_V007_REG_SW_EN_MSPI62MCU_MSPI6 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1BFC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1BFC)
	#define REG_1BFC_CKGEN01_V007_REG_SW_EN_MSPI72MCU_MSPI7 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C00_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C00)
	#define REG_1C00_CKGEN01_V007_REG_SW_EN_MSPI_CILINK_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C04_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C04)
	#define REG_1C04_CKGEN01_V007_REG_SW_EN_MSPI_CILINK2MCU_MSPI_CILINK Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C08_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C08)
	#define REG_1C08_CKGEN01_V007_REG_SW_EN_MSPI0_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C0C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C0C)
	#define REG_1C0C_CKGEN01_V007_REG_SW_EN_MSPI1_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C10_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C10)
	#define REG_1C10_CKGEN01_V007_REG_SW_EN_MSPI2_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C14_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C14)
	#define REG_1C14_CKGEN01_V007_REG_SW_EN_MSPI02MCU_MSPI0 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C18_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C18)
	#define REG_1C18_CKGEN01_V007_REG_SW_EN_MSPI3_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C1C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C1C)
	#define REG_1C1C_CKGEN01_V007_REG_SW_EN_MSPI4_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C20_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C20)
	#define REG_1C20_CKGEN01_V007_REG_SW_EN_MSPI5_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C24_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C24)
	#define REG_1C24_CKGEN01_V007_REG_SW_EN_MSPI6_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C28_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C28)
	#define REG_1C28_CKGEN01_V007_REG_SW_EN_MSPI7_DIV2MCU_CKCTRL_TOP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1C34_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C34)
	#define REG_1C34_CKGEN01_V007_REG_SW_EN_SPI2MCU_SPI Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1C34_CKGEN01_V007_REG_SW_EN_SPI2MCUSYS_XIU_BRIDGE Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1C7C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1C7C)
	#define REG_1C7C_CKGEN01_V007_REG_SW_EN_UFS_AHB2UFS Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CB0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CB0)
	#define REG_1CB0_CKGEN01_V007_REG_SW_EN_XTAL_12M2MCU_BDMA_VDEC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CC0)
	#define REG_1CC0_CKGEN01_V007_REG_SW_EN_SSUSB_FRMCNT2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CC4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CC4)
	#define REG_1CC4_CKGEN01_V007_REG_SW_EN_SSUSB_PCLK_1P2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CC8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CC8)
	#define REG_1CC8_CKGEN01_V007_REG_SW_EN_SSUSB_PCLK2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CCC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CCC)
	#define REG_1CCC_CKGEN01_V007_REG_SW_EN_SSUSB_SCL2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CD0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CD0)
	#define REG_1CD0_CKGEN01_V007_REG_SW_EN_SSUSB_SDIN2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CD4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CD4)
	#define REG_1CD4_CKGEN01_V007_REG_SW_EN_SSUSB_SYS2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CD8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CD8)
	#define REG_1CD8_CKGEN01_V007_REG_SW_EN_SSUSB_USB20_PHY_CLK_1P2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CDC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CDC)
	#define REG_1CDC_CKGEN01_V007_REG_SW_EN_SSUSB_USB20_PHY_CLK_2P2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CE0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CE0)
	#define REG_1CE0_CKGEN01_V007_REG_SW_EN_SSUSB_USB20_PHY_CLK2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CE4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CE4)
	#define REG_1CE4_CKGEN01_V007_REG_SW_EN_SSUSB_XHCI2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CF4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CF4)
	#define REG_1CF4_CKGEN01_V007_REG_SW_EN_SSUSB_MISC_48M2SSUSB Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1CF8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1CF8)
	#define REG_1CF8_CKGEN01_V007_REG_SW_EN_SMI2SEC_R2 Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_1D80_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1D80)
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2MHEG5_MBIST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2TSP_MBIST Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2DEMOD0_MBIST Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2DEMOD1_MBIST Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2VDEC_CORE0_MBIST Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2AIA_MBIST Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1D80_CKGEN01_V007_REG_SW_EN_XTAL_24M2GPU_PAR_GP_MBIST Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_1D84_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1D84)
	#define REG_1D84_CKGEN01_V007_REG_SW_EN_XTAL_24M2MCUSYS_MBIST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1D84_CKGEN01_V007_REG_SW_EN_XTAL_24M2MOD_MBIST Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1D84_CKGEN01_V007_REG_SW_EN_VIVA_XTAL_24M2VIVALDI9_MBIST Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_1D88_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1D88)
	#define REG_1D88_CKGEN01_V007_REG_SW_EN_XTAL_24M2VDEC_CORE0_MERGE_MBIST Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_1DBC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DBC)
	#define REG_1DBC_CKGEN01_V007_REG_VDEC_CORE0_MERGE_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DBC_CKGEN01_V007_REG_VDEC_CORE0_MERGE_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DBC_CKGEN01_V007_REG_VDEC_CORE0_MERGE_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DC0)
	#define REG_1DC0_CKGEN01_V007_REG_ADCPLL_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DC0_CKGEN01_V007_REG_ADCPLL_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DC0_CKGEN01_V007_REG_ADCPLL_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DC4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DC4)
	#define REG_1DC4_CKGEN01_V007_REG_AIA_TOP_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DC4_CKGEN01_V007_REG_AIA_TOP_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DC4_CKGEN01_V007_REG_AIA_TOP_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DC8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DC8)
	#define REG_1DC8_CKGEN01_V007_REG_DEMOD0_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DC8_CKGEN01_V007_REG_DEMOD0_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DC8_CKGEN01_V007_REG_DEMOD0_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DCC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DCC)
	#define REG_1DCC_CKGEN01_V007_REG_DEMOD1_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DCC_CKGEN01_V007_REG_DEMOD1_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DCC_CKGEN01_V007_REG_DEMOD1_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DD4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DD4)
	#define REG_1DD4_CKGEN01_V007_REG_VDEC_CORE0_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DD4_CKGEN01_V007_REG_VDEC_CORE0_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DD4_CKGEN01_V007_REG_VDEC_CORE0_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DEC)
	#define REG_1DEC_CKGEN01_V007_REG_TOP_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DEC_CKGEN01_V007_REG_TOP_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DEC_CKGEN01_V007_REG_TOP_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DF0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DF0)
	#define REG_1DF0_CKGEN01_V007_REG_MHEG5_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DF0_CKGEN01_V007_REG_MHEG5_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DF0_CKGEN01_V007_REG_MHEG5_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1DF8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1DF8)
	#define REG_1DF8_CKGEN01_V007_REG_GPU_PAR_GP_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1DF8_CKGEN01_V007_REG_GPU_PAR_GP_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1DF8_CKGEN01_V007_REG_GPU_PAR_GP_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E04_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E04)
	#define REG_1E04_CKGEN01_V007_REG_EMI_TOP_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E04_CKGEN01_V007_REG_EMI_TOP_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E04_CKGEN01_V007_REG_EMI_TOP_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E08_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E08)
	#define REG_1E08_CKGEN01_V007_REG_MCUSYS_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E08_CKGEN01_V007_REG_MCUSYS_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E08_CKGEN01_V007_REG_MCUSYS_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E0C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E0C)
	#define REG_1E0C_CKGEN01_V007_REG_MOD_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E0C_CKGEN01_V007_REG_MOD_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E0C_CKGEN01_V007_REG_MOD_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E10_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E10)
	#define REG_1E10_CKGEN01_V007_REG_MOD_DOT_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E10_CKGEN01_V007_REG_MOD_DOT_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E10_CKGEN01_V007_REG_MOD_DOT_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E18_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E18)
	#define REG_1E18_CKGEN01_V007_REG_VIVALDI9_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E18_CKGEN01_V007_REG_VIVALDI9_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E18_CKGEN01_V007_REG_VIVALDI9_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E24_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E24)
	#define REG_1E24_CKGEN01_V007_REG_TSP_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E24_CKGEN01_V007_REG_TSP_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E24_CKGEN01_V007_REG_TSP_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E64_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E64)
	#define REG_1E64_CKGEN01_V007_REG_HDMIRX_DPHY_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E64_CKGEN01_V007_REG_HDMIRX_DPHY_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E64_CKGEN01_V007_REG_HDMIRX_DPHY_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E68_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E68)
	#define REG_1E68_CKGEN01_V007_REG_HDMIRX_APHY_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E68_CKGEN01_V007_REG_HDMIRX_APHY_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E68_CKGEN01_V007_REG_HDMIRX_APHY_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E6C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E6C)
	#define REG_1E6C_CKGEN01_V007_REG_AUSDM_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E6C_CKGEN01_V007_REG_AUSDM_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E6C_CKGEN01_V007_REG_AUSDM_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E78_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E78)
	#define REG_1E78_CKGEN01_V007_REG_MCUSYS_DIE_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E78_CKGEN01_V007_REG_MCUSYS_DIE_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E78_CKGEN01_V007_REG_MCUSYS_DIE_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E7C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E7C)
	#define REG_1E7C_CKGEN01_V007_REG_DMD_ANA_MISC_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E7C_CKGEN01_V007_REG_DMD_ANA_MISC_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E7C_CKGEN01_V007_REG_DMD_ANA_MISC_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1E80_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1E80)
	#define REG_1E80_CKGEN01_V007_REG_ARMPLL_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1E80_CKGEN01_V007_REG_ARMPLL_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1E80_CKGEN01_V007_REG_ARMPLL_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EB0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EB0)
	#define REG_1EB0_CKGEN01_V007_REG_VDECPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EB0_CKGEN01_V007_REG_VDECPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EB0_CKGEN01_V007_REG_VDECPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EB4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EB4)
	#define REG_1EB4_CKGEN01_V007_REG_SYS0PLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EB4_CKGEN01_V007_REG_SYS0PLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EB4_CKGEN01_V007_REG_SYS0PLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EB8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EB8)
	#define REG_1EB8_CKGEN01_V007_REG_SYS1PLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EB8_CKGEN01_V007_REG_SYS1PLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EB8_CKGEN01_V007_REG_SYS1PLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EBC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EBC)
	#define REG_1EBC_CKGEN01_V007_REG_SYS2PLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EBC_CKGEN01_V007_REG_SYS2PLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EBC_CKGEN01_V007_REG_SYS2PLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EC0)
	#define REG_1EC0_CKGEN01_V007_REG_RV55FRCPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EC0_CKGEN01_V007_REG_RV55FRCPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EC0_CKGEN01_V007_REG_RV55FRCPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EC4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EC4)
	#define REG_1EC4_CKGEN01_V007_REG_XCPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EC4_CKGEN01_V007_REG_XCPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EC4_CKGEN01_V007_REG_XCPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1ECC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1ECC)
	#define REG_1ECC_CKGEN01_V007_REG_SMIPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1ECC_CKGEN01_V007_REG_SMIPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1ECC_CKGEN01_V007_REG_SMIPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1ED0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1ED0)
	#define REG_1ED0_CKGEN01_V007_REG_GPUBRDGPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1ED0_CKGEN01_V007_REG_GPUBRDGPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1ED0_CKGEN01_V007_REG_GPUBRDGPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1ED8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1ED8)
	#define REG_1ED8_CKGEN01_V007_REG_AURV55_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1ED8_CKGEN01_V007_REG_AURV55_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1ED8_CKGEN01_V007_REG_AURV55_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1EEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1EEC)
	#define REG_1EEC_CKGEN01_V007_REG_DISP_MFDEC_BRG_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1EEC_CKGEN01_V007_REG_DISP_MFDEC_BRG_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1EEC_CKGEN01_V007_REG_DISP_MFDEC_BRG_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1F18_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F18)
	#define REG_1F18_CKGEN01_V007_REG_FRCPLL_DMACRO_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F18_CKGEN01_V007_REG_FRCPLL_DMACRO_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1F18_CKGEN01_V007_REG_FRCPLL_DMACRO_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1F38_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F38)
	#define REG_1F38_CKGEN01_V007_REG_GATE_INV_WLOCK_PASSWD Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_1F3C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F3C)
	#define REG_1F3C_CKGEN01_V007_REG_ALL_SW_EN_PASSWD Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_1F40_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F40)
	#define REG_1F40_CKGEN01_V007_REG_XCPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F40_CKGEN01_V007_REG_VDECPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F40_CKGEN01_V007_REG_SYS0PLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1F40_CKGEN01_V007_REG_SYS1PLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1F40_CKGEN01_V007_REG_SYS2PLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1F40_CKGEN01_V007_REG_SMIPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1F40_CKGEN01_V007_REG_ARMPLL_ALL_SW_EN_OVERWRITE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F40_CKGEN01_V007_REG_ARM2PLL_ALL_SW_EN_OVERWRITE Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1F40_CKGEN01_V007_REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1F40_CKGEN01_V007_REG_RV55FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1F40_CKGEN01_V007_REG_DMD_ANA_MISC_ALL_SW_EN_OVERWRITE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1F40_CKGEN01_V007_REG_ADCPLL_ALL_SW_EN_OVERWRITE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F44_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F44)
	#define REG_1F44_CKGEN01_V007_REG_AUSDM_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F44_CKGEN01_V007_REG_DEMOD1_ALL_SW_EN_OVERWRITE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F44_CKGEN01_V007_REG_HDMIRX_APHY_ALL_SW_EN_OVERWRITE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F44_CKGEN01_V007_REG_HDMIRX_DPHY_ALL_SW_EN_OVERWRITE Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1F44_CKGEN01_V007_REG_EMI_TOP_ALL_SW_EN_OVERWRITE Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1F44_CKGEN01_V007_REG_MHEG5_ALL_SW_EN_OVERWRITE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1F44_CKGEN01_V007_REG_MOD_DOT_ALL_SW_EN_OVERWRITE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F48_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F48)
	#define REG_1F48_CKGEN01_V007_REG_VDEC_CORE0_ALL_SW_EN_OVERWRITE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F48_CKGEN01_V007_REG_DEMOD0_ALL_SW_EN_OVERWRITE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F48_CKGEN01_V007_REG_TOP_ALL_SW_EN_OVERWRITE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1F48_CKGEN01_V007_REG_AIA_TOP_ALL_SW_EN_OVERWRITE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1F48_CKGEN01_V007_REG_VDEC_CORE0_MERGE_ALL_SW_EN_OVERWRITE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1F48_CKGEN01_V007_REG_MCUSYS_ALL_SW_EN_OVERWRITE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F48_CKGEN01_V007_REG_DISP_MFDEC_BRG_ALL_SW_EN_OVERWRITE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1F48_CKGEN01_V007_REG_MOD_ALL_SW_EN_OVERWRITE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F4C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F4C)
	#define REG_1F4C_CKGEN01_V007_REG_TSP_ALL_SW_EN_OVERWRITE Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1F4C_CKGEN01_V007_REG_GPU_PAR_GP_ALL_SW_EN_OVERWRITE Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1F4C_CKGEN01_V007_REG_VIVALDI9_ALL_SW_EN_OVERWRITE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F50_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F50)
	#define REG_1F50_CKGEN01_V007_REG_AURV55_ALL_SW_EN_OVERWRITE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F50_CKGEN01_V007_REG_FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_1F60_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F60)
	#define REG_1F60_CKGEN01_V007_REG_XCPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F60_CKGEN01_V007_REG_VDECPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F60_CKGEN01_V007_REG_SYS0PLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1F60_CKGEN01_V007_REG_SYS1PLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1F60_CKGEN01_V007_REG_SYS2PLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1F60_CKGEN01_V007_REG_SMIPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1F60_CKGEN01_V007_REG_ARMPLL_ALL_SW_EN_VALUE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F60_CKGEN01_V007_REG_ARM2PLL_ALL_SW_EN_VALUE Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1F60_CKGEN01_V007_REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1F60_CKGEN01_V007_REG_RV55FRCPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1F60_CKGEN01_V007_REG_DMD_ANA_MISC_ALL_SW_EN_VALUE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1F60_CKGEN01_V007_REG_ADCPLL_ALL_SW_EN_VALUE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F64_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F64)
	#define REG_1F64_CKGEN01_V007_REG_AUSDM_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F64_CKGEN01_V007_REG_DEMOD1_ALL_SW_EN_VALUE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F64_CKGEN01_V007_REG_HDMIRX_APHY_ALL_SW_EN_VALUE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F64_CKGEN01_V007_REG_HDMIRX_DPHY_ALL_SW_EN_VALUE Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1F64_CKGEN01_V007_REG_EMI_TOP_ALL_SW_EN_VALUE Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1F64_CKGEN01_V007_REG_MHEG5_ALL_SW_EN_VALUE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1F64_CKGEN01_V007_REG_MOD_DOT_ALL_SW_EN_VALUE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F68_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F68)
	#define REG_1F68_CKGEN01_V007_REG_VDEC_CORE0_ALL_SW_EN_VALUE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F68_CKGEN01_V007_REG_DEMOD0_ALL_SW_EN_VALUE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F68_CKGEN01_V007_REG_TOP_ALL_SW_EN_VALUE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1F68_CKGEN01_V007_REG_AIA_TOP_ALL_SW_EN_VALUE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1F68_CKGEN01_V007_REG_VDEC_CORE0_MERGE_ALL_SW_EN_VALUE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1F68_CKGEN01_V007_REG_MCUSYS_ALL_SW_EN_VALUE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1F68_CKGEN01_V007_REG_DISP_MFDEC_BRG_ALL_SW_EN_VALUE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1F68_CKGEN01_V007_REG_MOD_ALL_SW_EN_VALUE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F6C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F6C)
	#define REG_1F6C_CKGEN01_V007_REG_TSP_ALL_SW_EN_VALUE Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1F6C_CKGEN01_V007_REG_GPU_PAR_GP_ALL_SW_EN_VALUE Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1F6C_CKGEN01_V007_REG_VIVALDI9_ALL_SW_EN_VALUE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1F70_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F70)
	#define REG_1F70_CKGEN01_V007_REG_AURV55_ALL_SW_EN_VALUE Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_1F74_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F74)
	#define REG_1F74_CKGEN01_V007_REG_FRCPLL_DMACRO_ALL_SW_EN_VALUE Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_1F78_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F78)
	#define REG_1F78_CKGEN01_V007_REG_SW_EN_PARSER2MAD_PARSER_TOP_WP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1F7C_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F7C)
	#define REG_1F7C_CKGEN01_V007_REG_SW_EN_SMI2MAD_PARSER_TOP_WP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1F80_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F80)
	#define REG_1F80_CKGEN01_V007_REG_SW_EN_MSDC0_AXI2MSDC0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F80_CKGEN01_V007_REG_SW_EN_MSDC0_HCLK2MSDC0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1F80_CKGEN01_V007_REG_SW_EN_MSDC0_SRC2MSDC0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1F80_CKGEN01_V007_REG_SW_EN_MCU_NONPM2MSDC0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1F80_CKGEN01_V007_REG_SW_EN_XTAL_24M2MSDC0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1F80_CKGEN01_V007_REG_SW_EN_SMI2MSDC0 Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_1F84_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F84)
	#define REG_1F84_CKGEN01_V007_REG_CKG_S_MSDC0_HCLK_TSP Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_1F84_CKGEN01_V007_REG_CKG_S_MSDC0_SRC_SEL Fld(3, 4, AC_MSKB0)//[6:4]
#define REG_1F88_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F88)
	#define REG_1F88_CKGEN01_V007_REG_SW_EN_CALC2TEST_CLK_CALCULATE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1F90_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F90)
	#define REG_1F90_CKGEN01_V007_REG_SW_EN_RIU_DMD2RIU_DFT_DEMOD1 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1F98_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1F98)
	#define REG_1F98_CKGEN01_V007_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1F98_CKGEN01_V007_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_1FA4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FA4)
	#define REG_1FA4_CKGEN01_V007_REG_ARM2PLL_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1FA4_CKGEN01_V007_REG_ARM2PLL_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_1FA4_CKGEN01_V007_REG_ARM2PLL_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_1FC0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FC0)
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_INFRA_RX_SARADCPLL2APB_DFT_ADC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_AIA Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD1 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_INFRA2INFRA_DFT_VDEC_CORE0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_INFRA2INFRA_DFT_VDEC_CORE0_MERGE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_MHEG5 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1FC0_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_MCUSYS Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1FC4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FC4)
	#define REG_1FC4_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_MOD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1FC8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FC8)
	#define REG_1FC8_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1FC8_CKGEN01_V007_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_1FCC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FCC)
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_DVBT2_INNER4X_SRD0P5X2DEMOD0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_DVBT2_INNER8X2DEMOD0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_DVBTM_SRAM_T12X_T28X2DEMOD0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_DVBTM_SRAM_T12X_T28X_SRD1X2DEMOD0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_DVBTM_SRAM_T14X_T28X_SRD1X_VIFDAC2DEMOD0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_DVBTM_SRAM_T14X_T28X_SRD1X_VIFSSC2DEMOD0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_012DEMOD0 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_022DEMOD0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_032DEMOD0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_042DEMOD0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_06_072DEMOD0 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_104_105_1062DEMOD0 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_107_1082DEMOD0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_112_TO_1192DEMOD0 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_120_121_122_1232DEMOD0 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1FCC_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_124_1252DEMOD0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1FD0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FD0)
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_126_1272DEMOD0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_149_150_151_1522DEMOD0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_1552DEMOD0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_156_R2DEMOD0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_156_W2DEMOD0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_157_R2DEMOD0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_157_W2DEMOD0 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_16_172DEMOD0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_24_252DEMOD0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_29_30_31_32_332DEMOD0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_34_35_36_382DEMOD0 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_37_39_40_412DEMOD0 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_42_43_442DEMOD0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_45_462DEMOD0 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_47_48_492DEMOD0 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_1FD0_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_50_51_52_532DEMOD0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_1FD4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FD4)
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_542DEMOD0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_552DEMOD0 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_68_0_69_02DEMOD0 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_68_12DEMOD0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_68_2_69_2_70_2_71_22DEMOD0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_68_3_69_3_70_3_71_32DEMOD0 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_69_12DEMOD0 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_70_0_71_02DEMOD0 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_70_12DEMOD0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_71_12DEMOD0 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_87_882DEMOD0 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_89_902DEMOD0 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_94_952DEMOD0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_96_972DEMOD0 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_1FD4_CKGEN01_V007_REG_SW_EN_SRAM_SHARE_99_100_101_1022DEMOD0 Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_1FDC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FDC)
	#define REG_1FDC_CKGEN01_V007_REG_SW_EN_SMI2ZDEC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1FE0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FE0)
	#define REG_1FE0_CKGEN01_V007_REG_SW_EN_SMI2MCU_BDMA_VDEC Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1FE8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FE8)
	#define REG_1FE8_CKGEN01_V007_REG_CKG_OCC_SRC_FOR_TEST_DIV Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_1FEC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FEC)
	#define REG_1FEC_CKGEN01_V007_REG_SW_EN_OCC_SRC_FOR_TEST_DIV2TEST_CTRL_WP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_1FF0_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FF0)
	#define REG_1FF0_CKGEN01_V007_REG_CKGEN01_V007_DUMMY0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_1FF4_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FF4)
	#define REG_1FF4_CKGEN01_V007_REG_CKGEN01_V007_DUMMY1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_1FF8_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FF8)
	#define REG_1FF8_CKGEN01_V007_REG_CKGEN01_V007_DUMMY2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_1FFC_CKGEN01_V007 (TOP_CKGEN01_V007 + 0x1FFC)
	#define REG_1FFC_CKGEN01_V007_REG_CKGEN01_V007_DUMMY3 Fld(16, 0, AC_FULLW10)//[15:0]
