/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define MODD1_V007 0x484400

//Page MODD1_V007
#define REG_0000_MODD1_V007 (MODD1_V007 + 0x000)
	#define REG_0000_MODD1_V007_REG_SW_RST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0000_MODD1_V007_REG_INFO2PWM_SEL Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0000_MODD1_V007_REG_PWM_SRC_SEL Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0000_MODD1_V007_REG_V2_SEL Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0004_MODD1_V007 (MODD1_V007 + 0x004)
	#define REG_0004_MODD1_V007_REG_DEBUG_OUT_SEL Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0004_MODD1_V007_REG_MOD_DEBUG_OUT_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0004_MODD1_V007_REG_INV_3D_FLAG_OSD Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_001C_MODD1_V007 (MODD1_V007 + 0x01C)
	#define REG_001C_MODD1_V007_REG_TTL_CLK_BITMAP Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_001C_MODD1_V007_REG_TTL_CLK_WRAP Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_001C_MODD1_V007_REG_CKPOL Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0020_MODD1_V007 (MODD1_V007 + 0x020)
	#define REG_0020_MODD1_V007_REG_CHANNEL_SEL Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0020_MODD1_V007_REG_CRC_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0020_MODD1_V007_REG_CRC_CLR Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0020_MODD1_V007_REG_CRC_ERROR Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0024_MODD1_V007 (MODD1_V007 + 0x024)
	#define REG_0024_MODD1_V007_REG_CRC_OUT Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0040_MODD1_V007 (MODD1_V007 + 0x040)
	#define REG_0040_MODD1_V007_REG_FREE_CH00_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0040_MODD1_V007_REG_FREE_CH01_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0044_MODD1_V007 (MODD1_V007 + 0x044)
	#define REG_0044_MODD1_V007_REG_FREE_CH02_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0044_MODD1_V007_REG_FREE_CH03_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0048_MODD1_V007 (MODD1_V007 + 0x048)
	#define REG_0048_MODD1_V007_REG_FREE_CH04_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0048_MODD1_V007_REG_FREE_CH05_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_004C_MODD1_V007 (MODD1_V007 + 0x04C)
	#define REG_004C_MODD1_V007_REG_FREE_CH06_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_004C_MODD1_V007_REG_FREE_CH07_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0050_MODD1_V007 (MODD1_V007 + 0x050)
	#define REG_0050_MODD1_V007_REG_FREE_CH08_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0050_MODD1_V007_REG_FREE_CH09_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0054_MODD1_V007 (MODD1_V007 + 0x054)
	#define REG_0054_MODD1_V007_REG_FREE_CH10_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0054_MODD1_V007_REG_FREE_CH11_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0058_MODD1_V007 (MODD1_V007 + 0x058)
	#define REG_0058_MODD1_V007_REG_FREE_CH12_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0058_MODD1_V007_REG_FREE_CH13_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_005C_MODD1_V007 (MODD1_V007 + 0x05C)
	#define REG_005C_MODD1_V007_REG_FREE_CH14_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_005C_MODD1_V007_REG_FREE_CH15_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0060_MODD1_V007 (MODD1_V007 + 0x060)
	#define REG_0060_MODD1_V007_REG_FREE_CH16_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0060_MODD1_V007_REG_FREE_CH17_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0064_MODD1_V007 (MODD1_V007 + 0x064)
	#define REG_0064_MODD1_V007_REG_FREE_CH18_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0064_MODD1_V007_REG_FREE_CH19_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0068_MODD1_V007 (MODD1_V007 + 0x068)
	#define REG_0068_MODD1_V007_REG_FREE_CH20_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0068_MODD1_V007_REG_FREE_CH21_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_006C_MODD1_V007 (MODD1_V007 + 0x06C)
	#define REG_006C_MODD1_V007_REG_FREE_CH22_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_006C_MODD1_V007_REG_FREE_CH23_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0070_MODD1_V007 (MODD1_V007 + 0x070)
	#define REG_0070_MODD1_V007_REG_FREE_CH24_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0070_MODD1_V007_REG_FREE_CH25_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0074_MODD1_V007 (MODD1_V007 + 0x074)
	#define REG_0074_MODD1_V007_REG_FREE_CH26_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0074_MODD1_V007_REG_FREE_CH27_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0078_MODD1_V007 (MODD1_V007 + 0x078)
	#define REG_0078_MODD1_V007_REG_FREE_CH28_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0078_MODD1_V007_REG_FREE_CH29_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_007C_MODD1_V007 (MODD1_V007 + 0x07C)
	#define REG_007C_MODD1_V007_REG_FREE_CH30_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_007C_MODD1_V007_REG_FREE_CH31_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0080_MODD1_V007 (MODD1_V007 + 0x080)
	#define REG_0080_MODD1_V007_REG_FREE_CH32_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0080_MODD1_V007_REG_FREE_CH33_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0084_MODD1_V007 (MODD1_V007 + 0x084)
	#define REG_0084_MODD1_V007_REG_FREE_CH34_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0084_MODD1_V007_REG_FREE_CH35_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0088_MODD1_V007 (MODD1_V007 + 0x088)
	#define REG_0088_MODD1_V007_REG_FREE_CH36_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0088_MODD1_V007_REG_FREE_CH37_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_008C_MODD1_V007 (MODD1_V007 + 0x08C)
	#define REG_008C_MODD1_V007_REG_FREE_CH38_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_008C_MODD1_V007_REG_FREE_CH39_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0090_MODD1_V007 (MODD1_V007 + 0x090)
	#define REG_0090_MODD1_V007_REG_FREE_CH40_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0090_MODD1_V007_REG_FREE_CH41_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0094_MODD1_V007 (MODD1_V007 + 0x094)
	#define REG_0094_MODD1_V007_REG_FREE_CH42_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0094_MODD1_V007_REG_FREE_CH43_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0098_MODD1_V007 (MODD1_V007 + 0x098)
	#define REG_0098_MODD1_V007_REG_FREE_CH44_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0098_MODD1_V007_REG_FREE_CH45_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_009C_MODD1_V007 (MODD1_V007 + 0x09C)
	#define REG_009C_MODD1_V007_REG_FREE_CH46_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_009C_MODD1_V007_REG_FREE_CH47_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00A0_MODD1_V007 (MODD1_V007 + 0x0A0)
	#define REG_00A0_MODD1_V007_REG_FREE_CH48_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00A0_MODD1_V007_REG_FREE_CH49_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00A4_MODD1_V007 (MODD1_V007 + 0x0A4)
	#define REG_00A4_MODD1_V007_REG_FREE_CH50_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00A4_MODD1_V007_REG_FREE_CH51_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00A8_MODD1_V007 (MODD1_V007 + 0x0A8)
	#define REG_00A8_MODD1_V007_REG_FREE_CH52_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00A8_MODD1_V007_REG_FREE_CH53_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00AC_MODD1_V007 (MODD1_V007 + 0x0AC)
	#define REG_00AC_MODD1_V007_REG_FREE_CH54_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00AC_MODD1_V007_REG_FREE_CH55_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00B0_MODD1_V007 (MODD1_V007 + 0x0B0)
	#define REG_00B0_MODD1_V007_REG_FREE_CH56_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00B0_MODD1_V007_REG_FREE_CH57_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00B4_MODD1_V007 (MODD1_V007 + 0x0B4)
	#define REG_00B4_MODD1_V007_REG_FREE_CH58_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00B4_MODD1_V007_REG_FREE_CH59_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00B8_MODD1_V007 (MODD1_V007 + 0x0B8)
	#define REG_00B8_MODD1_V007_REG_FREE_CH60_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00B8_MODD1_V007_REG_FREE_CH61_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00BC_MODD1_V007 (MODD1_V007 + 0x0BC)
	#define REG_00BC_MODD1_V007_REG_FREE_CH62_SWAP Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_00BC_MODD1_V007_REG_FREE_CH63_SWAP Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_00C0_MODD1_V007 (MODD1_V007 + 0x0C0)
	#define REG_00C0_MODD1_V007_REG_DATAX_SEL Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_00E0_MODD1_V007 (MODD1_V007 + 0x0E0)
	#define REG_00E0_MODD1_V007_REG_LVDS_TESTERMD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00E0_MODD1_V007_REG_FPGA_OD_LVDS Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00E0_MODD1_V007_REG_TI_BITMODE Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00E0_MODD1_V007_REG_PDP_MASK_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00E0_MODD1_V007_REG_PDP_MASK_SET Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_00E0_MODD1_V007_REG_PDP_CH3_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_00E0_MODD1_V007_REG_PDP_CH3_SET Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_00E0_MODD1_V007_REG_PDP_CH4_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00E0_MODD1_V007_REG_PDP_CH4_SET Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_00E0_MODD1_V007_REG_PA_SWAP Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_00E0_MODD1_V007_REG_CH_POLARITY Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_00E0_MODD1_V007_REG_LVDS_PLASMA Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_00E0_MODD1_V007_REG_PDP_10BIT Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_00E0_MODD1_V007_REG_LVDS_TI Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_00E0_MODD1_V007_REG_RSCLK_TESTMD Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00E4_MODD1_V007 (MODD1_V007 + 0x0E4)
	#define REG_00E4_MODD1_V007_REG_TESTER_PIX Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_00E4_MODD1_V007_REG_TEST_CH Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_00E4_MODD1_V007_REG_3D_CH4_EN_B Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_00E4_MODD1_V007_REG_3D_CH3_EN_B Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_00E4_MODD1_V007_REG_3D_CH4_EN_A Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_00E4_MODD1_V007_REG_3D_CH3_EN_A Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0140_MODD1_V007 (MODD1_V007 + 0x140)
	#define REG_0140_MODD1_V007_REG_SERI_ENABLE_V1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0140_MODD1_V007_REG_SERI_ENABLE_V2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0140_MODD1_V007_REG_SERI_ENABLE_OSD Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0140_MODD1_V007_REG_SERI_AUTO_FIX_V1 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0140_MODD1_V007_REG_SERI_AUTO_FIX_V2 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0140_MODD1_V007_REG_SERI_AUTO_FIX_OSD Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0140_MODD1_V007_REG_V1_FIX_CNT_CLR Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0140_MODD1_V007_REG_V2_FIX_CNT_CLR Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0140_MODD1_V007_REG_OSD_FIX_CNT_CLR Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0140_MODD1_V007_REG_DBG_STATUS_SEL Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0144_MODD1_V007 (MODD1_V007 + 0x144)
	#define REG_0144_MODD1_V007_REG_SERI_V2_MODE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0144_MODD1_V007_REG_SERI_OSD_MODE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0144_MODD1_V007_REG_SERI_TEST_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0148_MODD1_V007 (MODD1_V007 + 0x148)
	#define REG_0148_MODD1_V007_REG_SERI_TEST_DATA_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_014C_MODD1_V007 (MODD1_V007 + 0x14C)
	#define REG_014C_MODD1_V007_REG_SERI_TEST_DATA_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0150_MODD1_V007 (MODD1_V007 + 0x150)
	#define REG_0150_MODD1_V007_REG_V1_SW_RPTR_FIX_LO_TH Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0150_MODD1_V007_REG_V1_SW_RPTR_FIX_HI_TH Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0150_MODD1_V007_REG_V1_SW_RPTR_FIX_INI Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0150_MODD1_V007_REG_V1_SW_WPTR_CHECK Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0150_MODD1_V007_REG_V1_SW_FORCE_FIX_TRIG Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0150_MODD1_V007_REG_V1_SW_RPTR_FIX_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0154_MODD1_V007 (MODD1_V007 + 0x154)
	#define REG_0154_MODD1_V007_REG_V2_SW_RPTR_FIX_LO_TH Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0154_MODD1_V007_REG_V2_SW_RPTR_FIX_HI_TH Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0154_MODD1_V007_REG_V2_SW_RPTR_FIX_INI Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0154_MODD1_V007_REG_V2_SW_WPTR_CHECK Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0154_MODD1_V007_REG_V2_SW_FORCE_FIX_TRIG Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0154_MODD1_V007_REG_V2_SW_RPTR_FIX_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0158_MODD1_V007 (MODD1_V007 + 0x158)
	#define REG_0158_MODD1_V007_REG_OSD_SW_RPTR_FIX_LO_TH Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0158_MODD1_V007_REG_OSD_SW_RPTR_FIX_HI_TH Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0158_MODD1_V007_REG_OSD_SW_RPTR_FIX_INI Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0158_MODD1_V007_REG_OSD_SW_WPTR_CHECK Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0158_MODD1_V007_REG_OSD_SW_FORCE_FIX_TRIG Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0158_MODD1_V007_REG_OSD_SW_RPTR_FIX_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_015C_MODD1_V007 (MODD1_V007 + 0x15C)
	#define REG_015C_MODD1_V007_REG_SERI_FORMAT_V1 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_015C_MODD1_V007_REG_SERI_FORMAT_V2 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_015C_MODD1_V007_REG_SERI_FORMAT_OSD Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_0160_MODD1_V007 (MODD1_V007 + 0x160)
	#define REG_0160_MODD1_V007_REG_DBG_V1_STATUS Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0164_MODD1_V007 (MODD1_V007 + 0x164)
	#define REG_0164_MODD1_V007_REG_DBG_V2_STATUS Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0168_MODD1_V007 (MODD1_V007 + 0x168)
	#define REG_0168_MODD1_V007_REG_DBG_OSD_STATUS Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0180_MODD1_V007 (MODD1_V007 + 0x180)
	#define REG_0180_MODD1_V007_REG_PACKET_CRC_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0180_MODD1_V007_REG_PACKET_CRC_CLR Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0180_MODD1_V007_REG_PACKET_CRC_ALL_CLR Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0180_MODD1_V007_REG_PACKET_CRC_DATA_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0180_MODD1_V007_REG_PACKET_CRC_DATA_EN_DLY_SEL Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0180_MODD1_V007_REG_PACKET_CRC_ERROR Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0184_MODD1_V007 (MODD1_V007 + 0x184)
	#define REG_0184_MODD1_V007_REG_PACKET_CRC_VALUE Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A0_MODD1_V007 (MODD1_V007 + 0x1A0)
	#define REG_01A0_MODD1_V007_REG_SRAM_USAGE Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01A0_MODD1_V007_REG_PAD_LOCK_BY_LINE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_01A0_MODD1_V007_REG_EXT_PAD_OEN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_01A0_MODD1_V007_REG_SFC_CNC_SEL Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_01C0_MODD1_V007 (MODD1_V007 + 0x1C0)
	#define REG_01C0_MODD1_V007_REG_WORD_SKEW_RELOAD Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01C4_MODD1_V007 (MODD1_V007 + 0x1C4)
	#define REG_01C4_MODD1_V007_REG_WORD_SKEW_CH00 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01C4_MODD1_V007_REG_WORD_SKEW_CH01 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01C8_MODD1_V007 (MODD1_V007 + 0x1C8)
	#define REG_01C8_MODD1_V007_REG_WORD_SKEW_CH02 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01C8_MODD1_V007_REG_WORD_SKEW_CH03 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01CC_MODD1_V007 (MODD1_V007 + 0x1CC)
	#define REG_01CC_MODD1_V007_REG_WORD_SKEW_CH04 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01CC_MODD1_V007_REG_WORD_SKEW_CH05 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01D0_MODD1_V007 (MODD1_V007 + 0x1D0)
	#define REG_01D0_MODD1_V007_REG_WORD_SKEW_CH06 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01D0_MODD1_V007_REG_WORD_SKEW_CH07 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01D4_MODD1_V007 (MODD1_V007 + 0x1D4)
	#define REG_01D4_MODD1_V007_REG_WORD_SKEW_CH08 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01D4_MODD1_V007_REG_WORD_SKEW_CH09 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01D8_MODD1_V007 (MODD1_V007 + 0x1D8)
	#define REG_01D8_MODD1_V007_REG_WORD_SKEW_CH10 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01D8_MODD1_V007_REG_WORD_SKEW_CH11 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01DC_MODD1_V007 (MODD1_V007 + 0x1DC)
	#define REG_01DC_MODD1_V007_REG_WORD_SKEW_CH12 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01DC_MODD1_V007_REG_WORD_SKEW_CH13 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01E0_MODD1_V007 (MODD1_V007 + 0x1E0)
	#define REG_01E0_MODD1_V007_REG_WORD_SKEW_CH14 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01E0_MODD1_V007_REG_WORD_SKEW_CH15 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01E4_MODD1_V007 (MODD1_V007 + 0x1E4)
	#define REG_01E4_MODD1_V007_REG_WORD_SKEW_CH32 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01E4_MODD1_V007_REG_WORD_SKEW_CH33 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01E8_MODD1_V007 (MODD1_V007 + 0x1E8)
	#define REG_01E8_MODD1_V007_REG_WORD_SKEW_CH34 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01E8_MODD1_V007_REG_WORD_SKEW_CH35 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01EC_MODD1_V007 (MODD1_V007 + 0x1EC)
	#define REG_01EC_MODD1_V007_REG_WORD_SKEW_CH36 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01EC_MODD1_V007_REG_WORD_SKEW_CH37 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01F0_MODD1_V007 (MODD1_V007 + 0x1F0)
	#define REG_01F0_MODD1_V007_REG_WORD_SKEW_CH38 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01F0_MODD1_V007_REG_WORD_SKEW_CH39 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_01FC_MODD1_V007 (MODD1_V007 + 0x1FC)
	#define REG_01FC_MODD1_V007_REG_MOD_D_DUMMY0 Fld(16, 0, AC_FULLW10)//[15:0]
