/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define CLKGEN_SC00 0x1408000

//Page CLKGEN_SC00
#define REG_0004_CLKGEN_SC00 (CLKGEN_SC00 + 0x004)
	#define REG_0004_CLKGEN_SC00_REG_CKG_G_SMI_SCSR Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0004_CLKGEN_SC00_REG_CKG_I_SMI_SCSR Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0008_CLKGEN_SC00 (CLKGEN_SC00 + 0x008)
	#define REG_0008_CLKGEN_SC00_REG_SW_EN_SMI2SCSR Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_000C_CLKGEN_SC00 (CLKGEN_SC00 + 0x00C)
	#define REG_000C_CLKGEN_SC00_REG_CKG_G_XC_FN_SCSR Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_000C_CLKGEN_SC00_REG_CKG_I_XC_FN_SCSR Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0010_CLKGEN_SC00 (CLKGEN_SC00 + 0x010)
	#define REG_0010_CLKGEN_SC00_REG_CKG_G_XTAL_24M_SCSR Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0010_CLKGEN_SC00_REG_CKG_I_XTAL_24M_SCSR Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0014_CLKGEN_SC00 (CLKGEN_SC00 + 0x014)
	#define REG_0014_CLKGEN_SC00_REG_CKG_G_SMI_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0014_CLKGEN_SC00_REG_CKG_I_SMI_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0018_CLKGEN_SC00 (CLKGEN_SC00 + 0x018)
	#define REG_0018_CLKGEN_SC00_REG_SW_EN_SMI2SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_001C_CLKGEN_SC00 (CLKGEN_SC00 + 0x01C)
	#define REG_001C_CLKGEN_SC00_REG_CKG_G_XC_FN_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_001C_CLKGEN_SC00_REG_CKG_I_XC_FN_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0020_CLKGEN_SC00 (CLKGEN_SC00 + 0x020)
	#define REG_0020_CLKGEN_SC00_REG_CKG_G_XC_OD_1P_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0020_CLKGEN_SC00_REG_CKG_I_XC_OD_1P_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0024_CLKGEN_SC00 (CLKGEN_SC00 + 0x024)
	#define REG_0024_CLKGEN_SC00_REG_CKG_G_XC_OD_B2P_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0024_CLKGEN_SC00_REG_CKG_I_XC_OD_B2P_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0028_CLKGEN_SC00 (CLKGEN_SC00 + 0x028)
	#define REG_0028_CLKGEN_SC00_REG_CKG_G_O_ODCLK_SCTCON_TMP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0028_CLKGEN_SC00_REG_CKG_I_O_ODCLK_SCTCON_TMP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0028_CLKGEN_SC00_REG_CKG_S_O_ODCLK_SCTCON_TMP Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_002C_CLKGEN_SC00 (CLKGEN_SC00 + 0x02C)
	#define REG_002C_CLKGEN_SC00_REG_CKG_G_XTAL_24M_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_002C_CLKGEN_SC00_REG_CKG_I_XTAL_24M_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0030_CLKGEN_SC00 (CLKGEN_SC00 + 0x030)
	#define REG_0030_CLKGEN_SC00_REG_CKG_G_XC_OD_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0030_CLKGEN_SC00_REG_CKG_I_XC_OD_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0034_CLKGEN_SC00 (CLKGEN_SC00 + 0x034)
	#define REG_0034_CLKGEN_SC00_REG_CKG_G_XC_OD_META_SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0034_CLKGEN_SC00_REG_CKG_I_XC_OD_META_SCTCON Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0044_CLKGEN_SC00 (CLKGEN_SC00 + 0x044)
	#define REG_0044_CLKGEN_SC00_REG_CKG_G_XC_DC0_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0044_CLKGEN_SC00_REG_CKG_I_XC_DC0_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0048_CLKGEN_SC00 (CLKGEN_SC00 + 0x048)
	#define REG_0048_CLKGEN_SC00_REG_CKG_G_XC_DBG2MIU_M_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0048_CLKGEN_SC00_REG_CKG_I_XC_DBG2MIU_M_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0048_CLKGEN_SC00_REG_CKG_S_XC_DBG2MIU_M_SCIP Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0048_CLKGEN_SC00_REG_CKG_G_XC_FN_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0048_CLKGEN_SC00_REG_CKG_I_XC_FN_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_004C_CLKGEN_SC00 (CLKGEN_SC00 + 0x04C)
	#define REG_004C_CLKGEN_SC00_REG_CKG_G_XC_ID0_PRE1_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_004C_CLKGEN_SC00_REG_CKG_I_XC_ID0_PRE1_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_004C_CLKGEN_SC00_REG_CKG_S_XC_ID0_PRE1_SCIP Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_0050_CLKGEN_SC00 (CLKGEN_SC00 + 0x050)
	#define REG_0050_CLKGEN_SC00_REG_CKG_G_XTAL_24M_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0050_CLKGEN_SC00_REG_CKG_I_XTAL_24M_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0050_CLKGEN_SC00_REG_CKG_G_XTAL_12M_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0050_CLKGEN_SC00_REG_CKG_I_XTAL_12M_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0054_CLKGEN_SC00 (CLKGEN_SC00 + 0x054)
	#define REG_0054_CLKGEN_SC00_REG_CKG_G_XTAL_IP1_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0054_CLKGEN_SC00_REG_CKG_I_XTAL_IP1_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0054_CLKGEN_SC00_REG_CKG_S_XTAL_IP1_SCIP Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0054_CLKGEN_SC00_REG_CKG_G_XC_ADC_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0054_CLKGEN_SC00_REG_CKG_I_XC_ADC_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0054_CLKGEN_SC00_REG_CKG_S_XC_ADC_SCIP Fld(2, 10, AC_MSKB1)//[11:10]
#define REG_0058_CLKGEN_SC00 (CLKGEN_SC00 + 0x058)
	#define REG_0058_CLKGEN_SC00_REG_CKG_G_XC_SUB_DC0_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0058_CLKGEN_SC00_REG_CKG_I_XC_SUB_DC0_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0058_CLKGEN_SC00_REG_CKG_G_XC_SUB1_DC0_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0058_CLKGEN_SC00_REG_CKG_I_XC_SUB1_DC0_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_005C_CLKGEN_SC00 (CLKGEN_SC00 + 0x05C)
	#define REG_005C_CLKGEN_SC00_REG_CKG_G_XC_GPU_MFDEC_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_005C_CLKGEN_SC00_REG_CKG_I_XC_GPU_MFDEC_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0060_CLKGEN_SC00 (CLKGEN_SC00 + 0x060)
	#define REG_0060_CLKGEN_SC00_REG_CKG_G_XC_HDMI0_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0060_CLKGEN_SC00_REG_CKG_I_XC_HDMI0_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0060_CLKGEN_SC00_REG_CKG_S_XC_HDMI0_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0064_CLKGEN_SC00 (CLKGEN_SC00 + 0x064)
	#define REG_0064_CLKGEN_SC00_REG_CKG_G_XC_HDMI1_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0064_CLKGEN_SC00_REG_CKG_I_XC_HDMI1_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0064_CLKGEN_SC00_REG_CKG_S_XC_HDMI1_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0064_CLKGEN_SC00_REG_CKG_G_XC_HDMI2_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0064_CLKGEN_SC00_REG_CKG_I_XC_HDMI2_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0064_CLKGEN_SC00_REG_CKG_S_XC_HDMI2_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0068_CLKGEN_SC00 (CLKGEN_SC00 + 0x068)
	#define REG_0068_CLKGEN_SC00_REG_CKG_G_XC_HDMI3_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0068_CLKGEN_SC00_REG_CKG_I_XC_HDMI3_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0068_CLKGEN_SC00_REG_CKG_S_XC_HDMI3_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0068_CLKGEN_SC00_REG_CKG_G_XC_SLOW_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0068_CLKGEN_SC00_REG_CKG_I_XC_SLOW_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_006C_CLKGEN_SC00 (CLKGEN_SC00 + 0x06C)
	#define REG_006C_CLKGEN_SC00_REG_CKG_G_XC_TGEN_WIN_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_006C_CLKGEN_SC00_REG_CKG_I_XC_TGEN_WIN_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_006C_CLKGEN_SC00_REG_CKG_S_XC_TGEN_WIN_SCIP Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_006C_CLKGEN_SC00_REG_CKG_G_XC_VD_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_006C_CLKGEN_SC00_REG_CKG_I_XC_VD_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0070_CLKGEN_SC00 (CLKGEN_SC00 + 0x070)
	#define REG_0070_CLKGEN_SC00_REG_CKG_G_XC_DBG2MIU_S_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0070_CLKGEN_SC00_REG_CKG_I_XC_DBG2MIU_S_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0070_CLKGEN_SC00_REG_CKG_S_XC_DBG2MIU_S_SCIP Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0074_CLKGEN_SC00 (CLKGEN_SC00 + 0x074)
	#define REG_0074_CLKGEN_SC00_REG_CKG_G_SIDCLK_HD0_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0074_CLKGEN_SC00_REG_CKG_I_SIDCLK_HD0_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0074_CLKGEN_SC00_REG_CKG_S_SIDCLK_HD0_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0074_CLKGEN_SC00_REG_CKG_G_SIDCLK_HD1_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0074_CLKGEN_SC00_REG_CKG_I_SIDCLK_HD1_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0074_CLKGEN_SC00_REG_CKG_S_SIDCLK_HD1_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0078_CLKGEN_SC00 (CLKGEN_SC00 + 0x078)
	#define REG_0078_CLKGEN_SC00_REG_CKG_G_SIDCLK_HD2_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0078_CLKGEN_SC00_REG_CKG_I_SIDCLK_HD2_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0078_CLKGEN_SC00_REG_CKG_S_SIDCLK_HD2_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0078_CLKGEN_SC00_REG_CKG_G_SIDCLK_HD3_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0078_CLKGEN_SC00_REG_CKG_I_SIDCLK_HD3_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0078_CLKGEN_SC00_REG_CKG_S_SIDCLK_HD3_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_007C_CLKGEN_SC00 (CLKGEN_SC00 + 0x07C)
	#define REG_007C_CLKGEN_SC00_REG_CKG_G_XC_SC2FPLL_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_007C_CLKGEN_SC00_REG_CKG_I_XC_SC2FPLL_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_007C_CLKGEN_SC00_REG_CKG_S_XC_SC2FPLL_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0080_CLKGEN_SC00 (CLKGEN_SC00 + 0x080)
	#define REG_0080_CLKGEN_SC00_REG_CKG_G_MCU_NONPM_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0080_CLKGEN_SC00_REG_CKG_I_MCU_NONPM_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0084_CLKGEN_SC00 (CLKGEN_SC00 + 0x084)
	#define REG_0084_CLKGEN_SC00_REG_CKG_G_SIDCLK_DP0_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0084_CLKGEN_SC00_REG_CKG_I_SIDCLK_DP0_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0084_CLKGEN_SC00_REG_CKG_S_SIDCLK_DP0_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0084_CLKGEN_SC00_REG_CKG_G_SIDCLK_DP1_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0084_CLKGEN_SC00_REG_CKG_I_SIDCLK_DP1_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0084_CLKGEN_SC00_REG_CKG_S_SIDCLK_DP1_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0088_CLKGEN_SC00 (CLKGEN_SC00 + 0x088)
	#define REG_0088_CLKGEN_SC00_REG_CKG_G_SIDCLK_DSC_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0088_CLKGEN_SC00_REG_CKG_I_SIDCLK_DSC_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0088_CLKGEN_SC00_REG_CKG_S_SIDCLK_DSC_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_008C_CLKGEN_SC00 (CLKGEN_SC00 + 0x08C)
	#define REG_008C_CLKGEN_SC00_REG_CKG_G_XC_DP0_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_008C_CLKGEN_SC00_REG_CKG_I_XC_DP0_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_008C_CLKGEN_SC00_REG_CKG_S_XC_DP0_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_008C_CLKGEN_SC00_REG_CKG_G_XC_DP1_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_008C_CLKGEN_SC00_REG_CKG_I_XC_DP1_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_008C_CLKGEN_SC00_REG_CKG_S_XC_DP1_SCIP Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0090_CLKGEN_SC00 (CLKGEN_SC00 + 0x090)
	#define REG_0090_CLKGEN_SC00_REG_CKG_G_XC_DSC_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0090_CLKGEN_SC00_REG_CKG_I_XC_DSC_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0090_CLKGEN_SC00_REG_CKG_S_XC_DSC_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0094_CLKGEN_SC00 (CLKGEN_SC00 + 0x094)
	#define REG_0094_CLKGEN_SC00_REG_CKG_G_XC_SC2FPLL_PRE1_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0094_CLKGEN_SC00_REG_CKG_I_XC_SC2FPLL_PRE1_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0094_CLKGEN_SC00_REG_CKG_S_XC_SC2FPLL_PRE1_SCIP Fld(3, 2, AC_MSKB0)//[4:2]
	#define REG_0094_CLKGEN_SC00_REG_CKG_G_XC_SC2FPLL_PRE2_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0094_CLKGEN_SC00_REG_CKG_I_XC_SC2FPLL_PRE2_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0094_CLKGEN_SC00_REG_CKG_S_XC_SC2FPLL_PRE2_SCIP Fld(2, 10, AC_MSKB1)//[11:10]
#define REG_00A0_CLKGEN_SC00 (CLKGEN_SC00 + 0x0A0)
	#define REG_00A0_CLKGEN_SC00_REG_CKG_G_XC_ID1_PRE1_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A0_CLKGEN_SC00_REG_CKG_I_XC_ID1_PRE1_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00A0_CLKGEN_SC00_REG_CKG_S_XC_ID1_PRE1_SCIP Fld(3, 2, AC_MSKB0)//[4:2]
#define REG_00A4_CLKGEN_SC00 (CLKGEN_SC00 + 0x0A4)
	#define REG_00A4_CLKGEN_SC00_REG_CKG_G_XC_ID0_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A4_CLKGEN_SC00_REG_CKG_I_XC_ID0_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00A4_CLKGEN_SC00_REG_CKG_S_XC_ID0_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00A4_CLKGEN_SC00_REG_CKG_G_XC_ID0_PRE2_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00A4_CLKGEN_SC00_REG_CKG_I_XC_ID0_PRE2_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_00A4_CLKGEN_SC00_REG_CKG_S_XC_ID0_PRE2_SCIP Fld(2, 10, AC_MSKB1)//[11:10]
#define REG_00A8_CLKGEN_SC00 (CLKGEN_SC00 + 0x0A8)
	#define REG_00A8_CLKGEN_SC00_REG_CKG_G_XC_ID1_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A8_CLKGEN_SC00_REG_CKG_I_XC_ID1_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00A8_CLKGEN_SC00_REG_CKG_S_XC_ID1_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00A8_CLKGEN_SC00_REG_CKG_G_XC_ID1_PRE2_SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00A8_CLKGEN_SC00_REG_CKG_I_XC_ID1_PRE2_SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_00A8_CLKGEN_SC00_REG_CKG_S_XC_ID1_PRE2_SCIP Fld(2, 10, AC_MSKB1)//[11:10]
#define REG_0140_CLKGEN_SC00 (CLKGEN_SC00 + 0x140)
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DBG2MIU_M2SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_ADC2SCIP Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_SUB_DC02SCIP Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DC02SCIP Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DBG2MIU_S2SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_GPU_MFDEC2SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_FN2SCIP Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI02SCIP Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI12SCIP Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI22SCIP Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0144_CLKGEN_SC00 (CLKGEN_SC00 + 0x144)
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_HDMI32SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_ID02SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_ID12SCIP Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_IP2_SRC2SCIP Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_MFDEC_CG_SCIP Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_SC2FPLL2SCIP Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_SLOW2SCIP Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_TGEN_WIN2SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XC_VD2SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_12M2SCIP Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCIP Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_IP12SCIP Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD02SCIP Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD12SCIP Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD22SCIP Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0148_CLKGEN_SC00 (CLKGEN_SC00 + 0x148)
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD32SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCIP_MBIST Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCIP Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCIP Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_MCU_NONPM2SCIP Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DP02SCIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DP12SCIP Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DSC2SCIP Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DP02SCIP Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DP12SCIP Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DSC2SCIP Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_014C_CLKGEN_SC00 (CLKGEN_SC00 + 0x14C)
	#define REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_DC0_CG_SCIP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_SUB_DC0_CG_SCIP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_SUB1_DC0_CG_SCIP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_017C_CLKGEN_SC00 (CLKGEN_SC00 + 0x17C)
	#define REG_017C_CLKGEN_SC00_REG_SCIP_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_017C_CLKGEN_SC00_REG_SCIP_TEST_DIV_SEL Fld(3, 1, AC_MSKB0)//[3:1]
	#define REG_017C_CLKGEN_SC00_REG_SCIP_TEST_SRC_SEL Fld(8, 4, AC_MSKW10)//[11:4]
	#define REG_017C_CLKGEN_SC00_REG_SCIP_ALL_SW_EN_OVERWRITE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_017C_CLKGEN_SC00_REG_SCIP_ALL_SW_EN_VALUE Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_0180_CLKGEN_SC00 (CLKGEN_SC00 + 0x180)
	#define REG_0180_CLKGEN_SC00_REG_CKG_G_MCU_NONPM_SCNR Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0180_CLKGEN_SC00_REG_CKG_I_MCU_NONPM_SCNR Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0180_CLKGEN_SC00_REG_CKG_G_XTAL_24M_SCNR Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0180_CLKGEN_SC00_REG_CKG_I_XTAL_24M_SCNR Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0184_CLKGEN_SC00 (CLKGEN_SC00 + 0x184)
	#define REG_0184_CLKGEN_SC00_REG_CKG_G_XC_FN_SCNR Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0184_CLKGEN_SC00_REG_CKG_I_XC_FN_SCNR Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_01C0_CLKGEN_SC00 (CLKGEN_SC00 + 0x1C0)
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCNR Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCNR Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_MCU_NONPM2SCNR Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_12M2SCNR Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCNR Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCNR_MBIST Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_01C0_CLKGEN_SC00_REG_SW_EN_XC_FN2SCNR Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_01FC_CLKGEN_SC00 (CLKGEN_SC00 + 0x1FC)
	#define REG_01FC_CLKGEN_SC00_REG_SCNR_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01FC_CLKGEN_SC00_REG_SCNR_TEST_DIV_SEL Fld(3, 1, AC_MSKB0)//[3:1]
	#define REG_01FC_CLKGEN_SC00_REG_SCNR_TEST_SRC_SEL Fld(8, 4, AC_MSKW10)//[11:4]
	#define REG_01FC_CLKGEN_SC00_REG_SCNR_ALL_SW_EN_OVERWRITE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_01FC_CLKGEN_SC00_REG_SCNR_ALL_SW_EN_VALUE Fld(1, 13, AC_MSKB1)//[13:13]
