/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define TOP_XCBPLL 0x00201a00

//Page TOP_XCBPLL
#define REG_0100_XCBPLL (TOP_XCBPLL + 0x100)
	#define REG_0100_XCBPLL_REG_PD_XCBPLL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV1 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV3 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0104_XCBPLL (TOP_XCBPLL + 0x104)
	#define REG_0104_XCBPLL_REG_PD_XCBPLL_CLK_DIV5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0104_XCBPLL_REG_PD_XCBPLL_POSTDIV Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_0108_XCBPLL (TOP_XCBPLL + 0x108)
	#define REG_0108_XCBPLL_REG_EN_XCBPLL_VCO_DIV3 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0108_XCBPLL_REG_EN_XCBPLL_OCC_DIV128 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0108_XCBPLL_REG_EN_XCBPLL_XTAL Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0108_XCBPLL_REG_EN_XCBPLL_TEST Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_010C_XCBPLL (TOP_XCBPLL + 0x10C)
	#define REG_010C_XCBPLL_REG_EN_XCBPLL_PRDT Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_010C_XCBPLL_REG_EN_XCBPLL_RST Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_0110_XCBPLL (TOP_XCBPLL + 0x110)
	#define REG_0110_XCBPLL_REG_GC_XCBPLL_INPUT_DIV Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0114_XCBPLL (TOP_XCBPLL + 0x114)
	#define REG_0114_XCBPLL_REG_GC_XCBPLL_CP_SW Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0114_XCBPLL_REG_GC_XCBPLL_ICTRL Fld(3, 8, AC_MSKB1)//[10:8]
#define REG_0118_XCBPLL (TOP_XCBPLL + 0x118)
	#define REG_0118_XCBPLL_REG_GC_XCBPLL_OUTPUT_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0118_XCBPLL_REG_GC_XCBPLL_OUTPUT_DIV Fld(3, 8, AC_MSKB1)//[10:8]
#define REG_011C_XCBPLL (TOP_XCBPLL + 0x11C)
	#define REG_011C_XCBPLL_REG_GC_XCBPLL_LOOPDIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0120_XCBPLL (TOP_XCBPLL + 0x120)
	#define REG_0120_XCBPLL_REG_GC_XCBPLL_LOOPDIV_SECOND Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0128_XCBPLL (TOP_XCBPLL + 0x128)
	#define REG_0128_XCBPLL_REG_RO_XCBPLL_LOCK Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0138_XCBPLL (TOP_XCBPLL + 0x138)
	#define REG_0138_XCBPLL_REG_TEST_XCBPLL Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_013C_XCBPLL (TOP_XCBPLL + 0x13C)
	#define REG_013C_XCBPLL_REG_XCBPLL_DUMMY_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0140_XCBPLL (TOP_XCBPLL + 0x140)
	#define REG_0140_XCBPLL_REG_XCBPLL_DUMMY_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0144_XCBPLL (TOP_XCBPLL + 0x144)
	#define REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV1_DIG Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV2_DIG Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV3_DIG Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0148_XCBPLL (TOP_XCBPLL + 0x148)
	#define REG_0148_XCBPLL_REG_PD_XCBPLL_CLK_DIV5_DIG Fld(1, 0, AC_MSKB0)//[0:0]
