#ifndef _TGEN_VRR_BK_H
#define _TGEN_VRR_BK_H

#define TGEN_VRR_BKA39F 0x01473E00

//Page TGEN_VRR_BKA39F
#define REG_0004_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x004)
    #define REG_0004_TGEN_VRR_BKA39F_REG_ST_NVRR_WAIT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_TGEN_VRR_BKA39F_REG_ST_NVRR_COND_PASS_NC2V Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0004_TGEN_VRR_BKA39F_REG_ST_NVRR_COND_PASS_NV2C Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0004_TGEN_VRR_BKA39F_REG_USR_ST_NVRR_NX_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0004_TGEN_VRR_BKA39F_REG_USR_ST_NVRR_NX Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0004_TGEN_VRR_BKA39F_REG_ST_VRR_WAIT Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0004_TGEN_VRR_BKA39F_REG_ST_VRR_COND_PASS_CV2N Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0004_TGEN_VRR_BKA39F_REG_ST_VRR_COND_PASS_NV2C Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0004_TGEN_VRR_BKA39F_REG_USR_ST_VRR_NX_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0004_TGEN_VRR_BKA39F_REG_USR_ST_VRR_NX Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0008_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x008)
    #define REG_0008_TGEN_VRR_BKA39F_REG_ST_CVRR_WAIT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0008_TGEN_VRR_BKA39F_REG_ST_CVRR_COND_PASS_NC2V Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0008_TGEN_VRR_BKA39F_REG_ST_CVRR_COND_PASS_CV2N Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0008_TGEN_VRR_BKA39F_REG_USR_ST_CVRR_NX_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0008_TGEN_VRR_BKA39F_REG_USR_ST_CVRR_NX Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0008_TGEN_VRR_BKA39F_REG_ST_NC2V_P1_WAIT Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0008_TGEN_VRR_BKA39F_REG_ST_NC2V_P1_COND_PASS Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0008_TGEN_VRR_BKA39F_REG_USR_ST_NC2V_P1_NX_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0008_TGEN_VRR_BKA39F_REG_USR_ST_NC2V_P1_NX Fld(4,12,AC_MSKB1)//[15:12]
#define REG_000C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x00C)
    #define REG_000C_TGEN_VRR_BKA39F_REG_ST_NC2V_P2_WAIT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_000C_TGEN_VRR_BKA39F_REG_ST_NC2V_P2_COND_PASS Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_000C_TGEN_VRR_BKA39F_REG_USR_ST_NC2V_P2_NX_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_000C_TGEN_VRR_BKA39F_REG_USR_ST_NC2V_P2_NX Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_000C_TGEN_VRR_BKA39F_REG_ST_NV2C_P1_WAIT Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_000C_TGEN_VRR_BKA39F_REG_ST_NV2C_P1_COND_PASS Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_000C_TGEN_VRR_BKA39F_REG_USR_ST_NV2C_P1_NX_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_000C_TGEN_VRR_BKA39F_REG_USR_ST_NV2C_P1_NX Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0010_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x010)
    #define REG_0010_TGEN_VRR_BKA39F_REG_ST_NV2C_P2_WAIT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0010_TGEN_VRR_BKA39F_REG_ST_NV2C_P2_COND_PASS Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0010_TGEN_VRR_BKA39F_REG_USR_ST_NV2C_P2_NX_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0010_TGEN_VRR_BKA39F_REG_USR_ST_NV2C_P2_NX Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0010_TGEN_VRR_BKA39F_REG_ST_NV2C_P3_WAIT Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0010_TGEN_VRR_BKA39F_REG_ST_NV2C_P3_COND_PASS Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0010_TGEN_VRR_BKA39F_REG_USR_ST_NV2C_P3_NX_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0010_TGEN_VRR_BKA39F_REG_USR_ST_NV2C_P3_NX Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0014_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x014)
    #define REG_0014_TGEN_VRR_BKA39F_REG_ST_CV2N_P1_WAIT Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0014_TGEN_VRR_BKA39F_REG_ST_CV2N_P1_COND_PASS Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0014_TGEN_VRR_BKA39F_REG_USR_ST_CV2N_P1_NX_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0014_TGEN_VRR_BKA39F_REG_USR_ST_CV2N_P1_NX Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0014_TGEN_VRR_BKA39F_REG_ST_CV2N_P2_WAIT Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0014_TGEN_VRR_BKA39F_REG_ST_CV2N_P2_COND_PASS Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0014_TGEN_VRR_BKA39F_REG_USR_ST_CV2N_P2_NX_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0014_TGEN_VRR_BKA39F_REG_USR_ST_CV2N_P2_NX Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0018_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x018)
    #define REG_0018_TGEN_VRR_BKA39F_REG_USR_ST_EMPTY0_NX_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0018_TGEN_VRR_BKA39F_REG_USR_ST_EMPTY1_NX_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0018_TGEN_VRR_BKA39F_REG_USR_ST_EMPTY2_NX_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0018_TGEN_VRR_BKA39F_REG_USR_ST_EMPTY0_NX Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0018_TGEN_VRR_BKA39F_REG_USR_ST_EMPTY1_NX Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0018_TGEN_VRR_BKA39F_REG_USR_ST_EMPTY2_NX Fld(4,12,AC_MSKB1)//[15:12]
#define REG_001C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x01C)
    #define REG_001C_TGEN_VRR_BKA39F_REG_ST_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_001C_TGEN_VRR_BKA39F_REG_ST_SW_INI Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_001C_TGEN_VRR_BKA39F_REG_VRR_ST_CD_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_001C_TGEN_VRR_BKA39F_REG_VRR_CD_SW_RST Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_001C_TGEN_VRR_BKA39F_REG_VRR_CD_SW_MD Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_001C_TGEN_VRR_BKA39F_REG_VRR_CTRL_ST Fld(3,13,AC_MSKB1)//[15:13]
#define REG_0020_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x020)
    #define REG_0020_TGEN_VRR_BKA39F_REG_M_CONST_HDMI_MASK Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0020_TGEN_VRR_BKA39F_REG_M_CONST_IP1_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR_EN_HDMI_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR_EN_IP1_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0020_TGEN_VRR_BKA39F_REG_ML_SERV_BUSY_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR2ML_RST_P Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR_SCRWD_DONE_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR_FRCRWD_DONE_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR2SCMI_RBK_STOP_FORCE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR2SCMI_RBK_STOP_FORCE_VAL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR2SCMI_RBK_STOP_FRM_NUM Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0020_TGEN_VRR_BKA39F_REG_TGEN2VRR_VS_EDGE_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0020_TGEN_VRR_BKA39F_REG_IP12VRR_VSYNC_EDGE_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0020_TGEN_VRR_BKA39F_REG_VRR_LOC_RSTZ Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0024_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x024)
    #define REG_0024_TGEN_VRR_BKA39F_REG_VRR2NV2C_P1_PLOCK_TGEN_LOCK_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0024_TGEN_VRR_BKA39F_REG_VRR2NV2C_P1_TGEN_SELF_PROT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0024_TGEN_VRR_BKA39F_REG_VRR2NV2C_P1_VRR_ST_VRRMIN_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0024_TGEN_VRR_BKA39F_REG_NV2C_P12NC2V_P1_VRR_ST_VRRMIN_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0024_TGEN_VRR_BKA39F_REG_NVRR_M_CONST_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0024_TGEN_VRR_BKA39F_REG_NV2C_P1_DIR_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0024_TGEN_VRR_BKA39F_REG_FORCE_VRR_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0024_TGEN_VRR_BKA39F_REG_FORCE_VRR_EN_VAL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0024_TGEN_VRR_BKA39F_REG_FORCE_M_CONST Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0024_TGEN_VRR_BKA39F_REG_FORCE_M_CONST_VAL Fld(1,11,AC_MSKB1)//[11:11]
#define REG_0028_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x028)
    #define REG_0028_TGEN_VRR_BKA39F_REG_VRR2FRC_RW_DIFF Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0028_TGEN_VRR_BKA39F_REG_VRR2FRC_RW_DIFF_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0028_TGEN_VRR_BKA39F_REG_VRR2FRC_ML_EN Fld(1,7,AC_MSKB0)//[7:7]
#define REG_002C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x02C)
    #define REG_002C_TGEN_VRR_BKA39F_REG_VRR_CD_PERIOD_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0030_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x030)
    #define REG_0030_TGEN_VRR_BKA39F_REG_VRR_CD_PERIOD_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0034_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x034)
    #define REG_0034_TGEN_VRR_BKA39F_REG_FLAG_EQ_RST_SRC_IS_STABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0034_TGEN_VRR_BKA39F_REG_FLAG_EQ_RST_LOW_FRAME_RATE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0034_TGEN_VRR_BKA39F_REG_FLAG_EQ_RST_TGEN_SELF_PROT Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0034_TGEN_VRR_BKA39F_REG_FLAG_EQ_RISE_FRAME_NUM_SRC_IS_STABLE Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0034_TGEN_VRR_BKA39F_REG_FLAG_EQ_RISE_FRAME_NUM_LOW_FRAME_RATE Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0034_TGEN_VRR_BKA39F_REG_FLAG_EQ_RISE_FRAME_NUM_TGEN_SELF_PROT Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0040_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x040)
    #define REG_0040_TGEN_VRR_BKA39F_REG_VRR_IRQ_CLR Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x044)
    #define REG_0044_TGEN_VRR_BKA39F_REG_VRR_IRQ_FORCE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x048)
    #define REG_0048_TGEN_VRR_BKA39F_REG_VRR_IRQ_MASK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_004C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x04C)
    #define REG_004C_TGEN_VRR_BKA39F_REG_VRR_IRQ_FIN_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x050)
    #define REG_0050_TGEN_VRR_BKA39F_REG_VRR_IRQ_RAW_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x054)
    #define REG_0054_TGEN_VRR_BKA39F_REG_VRR_DEBUG_ST_REC_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0054_TGEN_VRR_BKA39F_REG_VRR_DEBUG_ST_REC_MD Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0054_TGEN_VRR_BKA39F_REG_VRR_DEBUG_ST_REC_RPT_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0054_TGEN_VRR_BKA39F_REG_VRR_DEBUG_ST_REC_START_ST Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0054_TGEN_VRR_BKA39F_REG_VRR_DEBUG_ST_REC_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0054_TGEN_VRR_BKA39F_REG_VRR_DEBUG_ST_REC_RPT Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0058_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x058)
    #define REG_0058_TGEN_VRR_BKA39F_REG_VRR_TESTBUS_SEL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0058_TGEN_VRR_BKA39F_REG_VRR_TESTBUS_RD_0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_005C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x05C)
    #define REG_005C_TGEN_VRR_BKA39F_REG_VRR_TESTBUS_RD_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x060)
    #define REG_0060_TGEN_VRR_BKA39F_REG_VRR2ML_BASE_ADDR_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x064)
    #define REG_0064_TGEN_VRR_BKA39F_REG_VRR2ML_BASE_ADDR_1 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0068_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x068)
    #define REG_0068_TGEN_VRR_BKA39F_REG_VRR2ML_DEPTH Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0070_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x070)
    #define REG_0070_TGEN_VRR_BKA39F_REG_VRR_DUMMY0_TIE0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x074)
    #define REG_0074_TGEN_VRR_BKA39F_REG_VRR_DUMMY1_TIE0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0078_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x078)
    #define REG_0078_TGEN_VRR_BKA39F_REG_VRR_DUMMY0_TIE1 Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_0078_TGEN_VRR_BKA39F_REG_VRR_CTRL_ST_READ Fld(4,12,AC_MSKB1)//[15:12]
#define REG_007C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x07C)
    #define REG_007C_TGEN_VRR_BKA39F_REG_VRR_DUMMY1_TIE1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0080_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x080)
    #define REG_0080_TGEN_VRR_BKA39F_REG_TGEN_SRC_LOCK_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0080_TGEN_VRR_BKA39F_REG_TGEN_NEXT_TFR_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_ML_TRIG_FLAG_CLR Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_ML_TRIG_FLAG Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_ML_CNT_TRIG Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0080_TGEN_VRR_BKA39F_REG_SRC_COMMON_TRIG_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0080_TGEN_VRR_BKA39F_REG_SC_SRC_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_EN_DELAY_READBACK Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_MODE_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_SW_RST_ODCLK Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_SW_RST_XTALI Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0080_TGEN_VRR_BKA39F_REG_DELAY_SYNC_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0084_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x084)
    #define REG_0084_TGEN_VRR_BKA39F_REG_SCMI_RW_DIFF Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0084_TGEN_VRR_BKA39F_REG_FRC_BANK_NUM Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_0084_TGEN_VRR_BKA39F_REG_DELAY_DMA_SRC_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0088_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x088)
    #define REG_0088_TGEN_VRR_BKA39F_REG_MAX_DELAY_XTALI_CNT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_008C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x08C)
    #define REG_008C_TGEN_VRR_BKA39F_REG_MAX_DELAY_XTALI_CNT_1 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0090_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x090)
    #define REG_0090_TGEN_VRR_BKA39F_REG_ENG2TGEN_SRC_LOCK_TRIG_DLY Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0094_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x094)
    #define REG_0094_TGEN_VRR_BKA39F_REG_DELAY_SYNC_NEXT_TFR_IN_READBACK Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0094_TGEN_VRR_BKA39F_REG_DELAY_SYNC_NEXT_TFR_OUT_READBACK Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0098_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x098)
    #define REG_0098_TGEN_VRR_BKA39F_REG_DELAY_SYNC_RBANK_IN_READBACK Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0098_TGEN_VRR_BKA39F_REG_DELAY_SYNC_RBANK_OUT_READBACK Fld(5,8,AC_MSKB1)//[12:8]
#define REG_009C_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x09C)
    #define REG_009C_TGEN_VRR_BKA39F_REG_DELAY_SYNC_NEXT_TFR_IN_USR_MD Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_009C_TGEN_VRR_BKA39F_REG_DELAY_SYNC_NEXT_TFR_IN_USR_MD_EN Fld(1,7,AC_MSKB0)//[7:7]
#define REG_00A0_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x0A0)
    #define REG_00A0_TGEN_VRR_BKA39F_REG_CNT_REPORT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x0A4)
    #define REG_00A4_TGEN_VRR_BKA39F_REG_CNT_REPORT_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00A4_TGEN_VRR_BKA39F_REG_CNT_REPORT_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00A4_TGEN_VRR_BKA39F_REG_DELAY_FIFO_OUT_STATUS Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_00A4_TGEN_VRR_BKA39F_REG_DELAY_FIFO_FULL_FLAG_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_00A4_TGEN_VRR_BKA39F_REG_DELAY_FIFO_FULL_FLAG Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_00A4_TGEN_VRR_BKA39F_REG_DELAY_SYNC_CNT_STATUS Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00A4_TGEN_VRR_BKA39F_REG_CNT_REPORT_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00A8_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x0A8)
    #define REG_00A8_TGEN_VRR_BKA39F_REG_PHASE_CNT_REPORT_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00AC_TGEN_VRR_BKA39F (TGEN_VRR_BKA39F + 0x0AC)
    #define REG_00AC_TGEN_VRR_BKA39F_REG_PHASE_CNT_REPORT_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00AC_TGEN_VRR_BKA39F_REG_PHASE_CNT_REPORT_RST Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00AC_TGEN_VRR_BKA39F_REG_PHASE_CNT_ENABLE Fld(1,15,AC_MSKB1)//[15:15]

#endif
