#ifndef _TCON_ADL_CRC_BKA369_V004_H
#define _TCON_ADL_CRC_BKA369_V004_H
#define TCON_ADL_CRC_BKA369_V004 0x146D200

//Page TCON_ADL_CRC_BKA369_V004
#define REG_0004_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x004)
	#define REG_0004_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_CLR_0004 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0008_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x008)
	#define REG_0008_TCON_ADL_CRC_BKA369_V004_REG_CRC_ADL_DONE_0008 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0018_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x018)
	#define REG_0018_TCON_ADL_CRC_BKA369_V004_REG_CHK_SUM_OUT_SEL_0018 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_001C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x01C)
	#define REG_001C_TCON_ADL_CRC_BKA369_V004_REG_CRC_CHK_SUM_OUT_001C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x020)
	#define REG_0020_TCON_ADL_CRC_BKA369_V004_REG_FAKE_ACTIVE_EN_0_0020 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x024)
	#define REG_0024_TCON_ADL_CRC_BKA369_V004_REG_FAKE_ACTIVE_EN_1_0024 Fld(10,0,AC_MSKW10)//[9:0]
#define REG_0028_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x028)
	#define REG_0028_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_FINAL_IRQ_0_0028 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x02C)
	#define REG_002C_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_FINAL_IRQ_1_002C Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0030_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x030)
	#define REG_0030_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_RAW_IRQ_0_0030 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x034)
	#define REG_0034_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_RAW_IRQ_1_0034 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0038_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x038)
	#define REG_0038_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_IRQ_FORCE_0_0038 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_003C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x03C)
	#define REG_003C_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_IRQ_FORCE_1_003C Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0040_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x040)
	#define REG_0040_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_IRQ_MASK_0_0040 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x044)
	#define REG_0044_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_IRQ_MASK_1_0044 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0048_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x048)
	#define REG_0048_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_IRQ_CLR_0_0048 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_004C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x04C)
	#define REG_004C_TCON_ADL_CRC_BKA369_V004_REG_ADL_DONE_IRQ_CLR_1_004C Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0050_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x050)
	#define REG_0050_TCON_ADL_CRC_BKA369_V004_REG_CLIENT_CLR_DONE_0_0050 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x054)
	#define REG_0054_TCON_ADL_CRC_BKA369_V004_REG_CLIENT_CLR_DONE_1_0054 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0058_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x058)
	#define REG_0058_TCON_ADL_CRC_BKA369_V004_REG_CLIENT_SET_DONE_0_0058 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_005C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x05C)
	#define REG_005C_TCON_ADL_CRC_BKA369_V004_REG_CLIENT_SET_DONE_1_005C Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0100_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x100)
	#define REG_0100_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_EN_0100 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0100_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_TRIG_MODE_0100 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0100_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_CLK_GATE_EN_0100 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0104_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x104)
	#define REG_0104_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_BASEADR_0_0104 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0108_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x108)
	#define REG_0108_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_BASEADR_1_0108 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_010C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x10C)
	#define REG_010C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_DEPTH_010C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0110_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x110)
	#define REG_0110_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_REQ_LEN_0110 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0114_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x114)
	#define REG_0114_TCON_ADL_CRC_BKA369_V004_REG_CLIENTJ_INI_ADDR_0114 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0118_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x118)
	#define REG_0118_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_EN_0118 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0118_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_TRIG_MODE_0118 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0118_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_CLK_GATE_EN_0118 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_011C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x11C)
	#define REG_011C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_BASEADR_0_011C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0120_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x120)
	#define REG_0120_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_BASEADR_1_0120 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0124_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x124)
	#define REG_0124_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_DEPTH_0124 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0128_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x128)
	#define REG_0128_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_REQ_LEN_0128 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_012C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x12C)
	#define REG_012C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTK_INI_ADDR_012C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0130_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x130)
	#define REG_0130_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_EN_0130 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0130_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_TRIG_MODE_0130 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0130_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_CLK_GATE_EN_0130 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0134_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x134)
	#define REG_0134_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_BASEADR_0_0134 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0138_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x138)
	#define REG_0138_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_BASEADR_1_0138 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_013C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x13C)
	#define REG_013C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_DEPTH_013C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0140_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x140)
	#define REG_0140_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_REQ_LEN_0140 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0144_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x144)
	#define REG_0144_TCON_ADL_CRC_BKA369_V004_REG_CLIENTL_INI_ADDR_0144 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0148_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x148)
	#define REG_0148_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_EN_0148 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0148_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_TRIG_MODE_0148 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0148_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_CLK_GATE_EN_0148 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_014C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x14C)
	#define REG_014C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_BASEADR_0_014C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0150_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x150)
	#define REG_0150_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_BASEADR_1_0150 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0154_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x154)
	#define REG_0154_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_DEPTH_0154 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0158_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x158)
	#define REG_0158_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_REQ_LEN_0158 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_015C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x15C)
	#define REG_015C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTM_INI_ADDR_015C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0160_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x160)
	#define REG_0160_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_EN_0160 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0160_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_TRIG_MODE_0160 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0160_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_CLK_GATE_EN_0160 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0164_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x164)
	#define REG_0164_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_BASEADR_0_0164 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0168_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x168)
	#define REG_0168_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_BASEADR_1_0168 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_016C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x16C)
	#define REG_016C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_DEPTH_016C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0170_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x170)
	#define REG_0170_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_REQ_LEN_0170 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0174_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x174)
	#define REG_0174_TCON_ADL_CRC_BKA369_V004_REG_CLIENTN_INI_ADDR_0174 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0178_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x178)
	#define REG_0178_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_EN_0178 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0178_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_TRIG_MODE_0178 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0178_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_CLK_GATE_EN_0178 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_017C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x17C)
	#define REG_017C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_BASEADR_0_017C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0180_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x180)
	#define REG_0180_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_BASEADR_1_0180 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0184_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x184)
	#define REG_0184_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_DEPTH_0184 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x188)
	#define REG_0188_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_REQ_LEN_0188 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_018C_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x18C)
	#define REG_018C_TCON_ADL_CRC_BKA369_V004_REG_CLIENTO_INI_ADDR_018C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A8_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1A8)
	#define REG_01A8_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_EN_01A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01A8_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_TRIG_MODE_01A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01A8_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_CLK_GATE_EN_01A8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_01AC_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1AC)
	#define REG_01AC_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_BASEADR_0_01AC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B0_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1B0)
	#define REG_01B0_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_BASEADR_1_01B0 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01B4_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1B4)
	#define REG_01B4_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_DEPTH_01B4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B8_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1B8)
	#define REG_01B8_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_REQ_LEN_01B8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01BC_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1BC)
	#define REG_01BC_TCON_ADL_CRC_BKA369_V004_REG_CLIENTI_INI_ADDR_01BC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C0_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1C0)
	#define REG_01C0_TCON_ADL_CRC_BKA369_V004_REG_ADL_STATUS_1_01C0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C4_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1C4)
	#define REG_01C4_TCON_ADL_CRC_BKA369_V004_REG_ADL_STATUS_2_01C4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1C8)
	#define REG_01C8_TCON_ADL_CRC_BKA369_V004_REG_ADL_STATUS_3_01C8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1CC)
	#define REG_01CC_TCON_ADL_CRC_BKA369_V004_REG_ADL_STATUS_4_01CC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D0_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1D0)
	#define REG_01D0_TCON_ADL_CRC_BKA369_V004_REG_DMA_FIFO_DEPTH_01D0 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_01D0_TCON_ADL_CRC_BKA369_V004_REG_REQ_TH_01D0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01D4_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1D4)
	#define REG_01D4_TCON_ADL_CRC_BKA369_V004_REG_MIU_ULTRA_MASK_01D4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01D4_TCON_ADL_CRC_BKA369_V004_REG_MIU_PREULTRA_TH_01D4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01D8_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1D8)
	#define REG_01D8_TCON_ADL_CRC_BKA369_V004_REG_MIU_ULTRA_TH_01D8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01DC_TCON_ADL_CRC_BKA369_V004 (TCON_ADL_CRC_BKA369_V004 + 0x1DC)
	#define REG_01DC_TCON_ADL_CRC_BKA369_V004_REG_MIU_URGENT_TH_01DC Fld(8,8,AC_FULLB1)//[15:8]
#endif