/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define DISP_MISC_V007 0x484200

//Page DISP_MISC_V007
#define REG_0100_DISP_MISC_V007 (DISP_MISC_V007 + 0x100)
	#define REG_0100_DISP_MISC_V007_REG_ODCLK_ROOT_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0100_DISP_MISC_V007_REG_PD_MOD_CK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0100_DISP_MISC_V007_REG_PD_LPLL_CK Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0100_DISP_MISC_V007_REG_V1_MOD_SR_WCLK_GATE_DISABLE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0100_DISP_MISC_V007_REG_MOD_CH40TO63_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0104_DISP_MISC_V007 (DISP_MISC_V007 + 0x104)
	#define REG_0104_DISP_MISC_V007_REG_CLK_SHIFT Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0108_DISP_MISC_V007 (DISP_MISC_V007 + 0x108)
	#define REG_0108_DISP_MISC_V007_REG_SERI_CH_CKEN_BITMAP_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_010C_DISP_MISC_V007 (DISP_MISC_V007 + 0x10C)
	#define REG_010C_DISP_MISC_V007_REG_SERI_CH_CKEN_BITMAP_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0110_DISP_MISC_V007 (DISP_MISC_V007 + 0x110)
	#define REG_0110_DISP_MISC_V007_REG_SERI_CH_CKEN_BITMAP_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0114_DISP_MISC_V007 (DISP_MISC_V007 + 0x114)
	#define REG_0114_DISP_MISC_V007_REG_SERI_CH_CKEN_BITMAP_3 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0140_DISP_MISC_V007 (DISP_MISC_V007 + 0x140)
	#define REG_0140_DISP_MISC_V007_REG_TCON_CLKEN_BITMAP Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01E0_DISP_MISC_V007 (DISP_MISC_V007 + 0x1E0)
	#define REG_01E0_DISP_MISC_V007_REG_TESTBUS_MUX Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_01E4_DISP_MISC_V007 (DISP_MISC_V007 + 0x1E4)
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL00 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL01 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL02 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL03 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL04 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL05 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL06 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01E4_DISP_MISC_V007_REG_TESTBUS_BIT_SEL07 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01E8_DISP_MISC_V007 (DISP_MISC_V007 + 0x1E8)
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL08 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL09 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL10 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL11 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL12 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL13 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL14 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01E8_DISP_MISC_V007_REG_TESTBUS_BIT_SEL15 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01EC_DISP_MISC_V007 (DISP_MISC_V007 + 0x1EC)
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL16 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL17 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL18 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL19 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL20 Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL21 Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL22 Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01EC_DISP_MISC_V007_REG_TESTBUS_BIT_SEL23 Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_01F0_DISP_MISC_V007 (DISP_MISC_V007 + 0x1F0)
	#define REG_01F0_DISP_MISC_V007_REG_TESTBUS_CONT_DE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01F4_DISP_MISC_V007 (DISP_MISC_V007 + 0x1F4)
	#define REG_01F4_DISP_MISC_V007_REG_P2P_RX_CLOCK_CG_EN Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01FC_DISP_MISC_V007 (DISP_MISC_V007 + 0x1FC)
	#define REG_01FC_DISP_MISC_V007_REG_DISP_MISC_V007_DUMMY Fld(16, 0, AC_FULLW10)//[15:0]
