/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
 * Copyright (C) 2023 MediaTek Inc.
 */

#ifndef _MTK_MMU_
#define _MTK_MMU_

#define MEM_MAP_NUM             15
#define MEM_MAP_CACHE_BASE      10
#define MEM_MAP_DEF_BLOCK_NUM   3
#define MMU_PAGE_SIZE           4096
#define RIU_PM_BASE             0x1C000000UL
#define RIU_PM_MAP_LEN          0x200000UL
#define RIU_NONPM_BASE          0x1C200000UL
#define RIU_NONPM_MAP_LEN       0x600000UL
#define RIU_DMD_BASE            0x1CE00000UL
#define RIU_DMD_MAP_LEN         0x200000UL
#define RIU_FRC_BASE            0x1D000000UL
#define RIU_FRC_MAP_LEN         0x200000UL
#define RIU_AU_BASE             0x1D200000UL
#define RIU_AU_MAP_LEN          0x200000UL
#define RIU_SCALAR_BASE         0x1D400000UL
#define RIU_SCALAR_MAP_LEN      0x400000UL
#define RIU_CODEC_BASE          0x1D800000UL
#define RIU_CODEC_MAP_LEN       0x200000UL
#define RIU_HDMI_BASE           0x1DC00000UL
#define RIU_HDMI_MAP_LEN        0x200000UL
#define SPI_BASE                0x14000000UL
#define SPI_MAP_LEN             0x01000000UL
#define MIU_CACHE_BUS_BASE1     ((unsigned long)CONFIG_BUSADDR_START)
#define MIU_CACHE_MAP_LEN1      0x40000000UL
#define MIU_CACHE_BUS_BASE2     (MIU_CACHE_BUS_BASE1 + MIU_CACHE_MAP_LEN1)
#define MIU_CACHE_MAP_LEN2      0xA0000000UL
#define MIU_CACHE_64BUS_BASE    ((unsigned long)CONFIG_BUSADDR_START + 0xE0000000)
#define MIU_NC_MAP_LEN          0x200000UL
#define MIU0_BUS_BASE           MIU_CACHE_BUS_BASE1

void init_mem_map(void);
void set_nc_start_address(unsigned long long addr);
#endif
