#define GOP0_HVSP_BKA4E1 0x0149C200

//Page GOP0_HVSP_BKA4E1
#define REG_0004_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x004)
    #define REG_0004_GOP0_HVSP_BKA4E1_REG_INI_FACTOR_HO_0_0004 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0008_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x008)
    #define REG_0008_GOP0_HVSP_BKA4E1_REG_INI_FACTOR_HO_1_0008 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_000C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x00C)
    #define REG_000C_GOP0_HVSP_BKA4E1_REG_INI_FACTOR_VE_0_000C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0010_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x010)
    #define REG_0010_GOP0_HVSP_BKA4E1_REG_INI_FACTOR_VE_1_0010 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_001C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x01C)
    #define REG_001C_GOP0_HVSP_BKA4E1_REG_SCALE_FACTOR_HO_0_001C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x020)
    #define REG_0020_GOP0_HVSP_BKA4E1_REG_SCALE_FACTOR_HO_1_0020 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0020_GOP0_HVSP_BKA4E1_REG_SCALE_FACTOR_HO_MSB_0020 Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_0020_GOP0_HVSP_BKA4E1_REG_SCALE_HO_EN_0020 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0020_GOP0_HVSP_BKA4E1_REG_H_SHIFT_MODE_EN_0020 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0024_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x024)
    #define REG_0024_GOP0_HVSP_BKA4E1_REG_SCALE_FACTOR_VE_0_0024 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x028)
    #define REG_0028_GOP0_HVSP_BKA4E1_REG_SCALE_FACTOR_VE_1_0028 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0028_GOP0_HVSP_BKA4E1_REG_SCALE_VE_EN_0028 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0028_GOP0_HVSP_BKA4E1_REG_V_SHIFT_MODE_EN_0028 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_002C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x02C)
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_MODE_Y_HO_002C Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_MODE_C_HO_002C Fld(2,1,AC_MSKB0)//[2:1]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_MODE_A_HO_002C Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_C_RAM_EN_HO_002C Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_Y_RAM_EN_HO_002C Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_MODE_Y_VE_002C Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_MODE_C_VE_002C Fld(2,9,AC_MSKB1)//[10:9]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_MODE_A_VE_002C Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_C_RAM_EN_VE_002C Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_002C_GOP0_HVSP_BKA4E1_REG_Y_RAM_EN_VE_002C Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0030_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x030)
    #define REG_0030_GOP0_HVSP_BKA4E1_REG_HSP_DITH_EN_0030 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0030_GOP0_HVSP_BKA4E1_REG_VSP_DITH_EN_0030 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0030_GOP0_HVSP_BKA4E1_REG_HSP_CORING_EN_C_0030 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0030_GOP0_HVSP_BKA4E1_REG_HSP_CORING_EN_Y_0030 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0030_GOP0_HVSP_BKA4E1_REG_VSP_CORING_EN_C_0030 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0030_GOP0_HVSP_BKA4E1_REG_VSP_CORING_EN_Y_0030 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_0034_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x034)
    #define REG_0034_GOP0_HVSP_BKA4E1_REG_HSP_CORING_TH_C_0034 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0034_GOP0_HVSP_BKA4E1_REG_HSP_CORING_TH_Y_0034 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0038_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x038)
    #define REG_0038_GOP0_HVSP_BKA4E1_REG_VSP_CORING_TH_C_0038 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0038_GOP0_HVSP_BKA4E1_REG_VSP_CORING_TH_Y_0038 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_003C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x03C)
    #define REG_003C_GOP0_HVSP_BKA4E1_REG_VSP_ALPHA_BLD_A_EN_003C Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_003C_GOP0_HVSP_BKA4E1_REG_VSP_ALPHA_BLD_RGB_EN_003C Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_003C_GOP0_HVSP_BKA4E1_REG_HSP_ALPHA_BLD_A_EN_003C Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_003C_GOP0_HVSP_BKA4E1_REG_HSP_ALPHA_BLD_RGB_EN_003C Fld(1,3,AC_MSKB0)//[3:3]
#define REG_004C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x04C)
    #define REG_004C_GOP0_HVSP_BKA4E1_REG_12LB_EN_004C Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0050_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x050)
    #define REG_0050_GOP0_HVSP_BKA4E1_REG_COEF0_00_Y_H_0050 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0054_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x054)
    #define REG_0054_GOP0_HVSP_BKA4E1_REG_COEF1_00_Y_H_0054 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0058_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x058)
    #define REG_0058_GOP0_HVSP_BKA4E1_REG_COEF0_25_Y_H_0058 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_005C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x05C)
    #define REG_005C_GOP0_HVSP_BKA4E1_REG_COEF1_25_Y_H_005C Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0060_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x060)
    #define REG_0060_GOP0_HVSP_BKA4E1_REG_COEF2_25_Y_H_0060 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0064_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x064)
    #define REG_0064_GOP0_HVSP_BKA4E1_REG_COEF3_25_Y_H_0064 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0068_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x068)
    #define REG_0068_GOP0_HVSP_BKA4E1_REG_COEF0_50_Y_H_0068 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_006C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x06C)
    #define REG_006C_GOP0_HVSP_BKA4E1_REG_COEF1_50_Y_H_006C Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00A0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0A0)
    #define REG_00A0_GOP0_HVSP_BKA4E1_REG_H_SIZE_00A0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0A4)
    #define REG_00A4_GOP0_HVSP_BKA4E1_REG_V_SIZE_00A4 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0A8)
    #define REG_00A8_GOP0_HVSP_BKA4E1_REG_SCL_H_SIZE_00A8 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00AC_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0AC)
    #define REG_00AC_GOP0_HVSP_BKA4E1_REG_SCL_V_SIZE_00AC Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00B0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0B0)
    #define REG_00B0_GOP0_HVSP_BKA4E1_REG_DEBUG_CLR_00B0 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_00B0_GOP0_HVSP_BKA4E1_REG_H_SIZE_RPT_00B0 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00B4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0B4)
    #define REG_00B4_GOP0_HVSP_BKA4E1_REG_V_SIZE_RPT_00B4 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00B8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0B8)
    #define REG_00B8_GOP0_HVSP_BKA4E1_REG_SCL_H_SIZE_RPT_00B8 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00BC_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0BC)
    #define REG_00BC_GOP0_HVSP_BKA4E1_REG_SCL_V_SIZE_RPT_00BC Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00C0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0C0)
    #define REG_00C0_GOP0_HVSP_BKA4E1_REG_COEF0_00_C_H_00C0 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00C4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0C4)
    #define REG_00C4_GOP0_HVSP_BKA4E1_REG_COEF1_00_C_H_00C4 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00C8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0C8)
    #define REG_00C8_GOP0_HVSP_BKA4E1_REG_COEF0_25_C_H_00C8 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00CC_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0CC)
    #define REG_00CC_GOP0_HVSP_BKA4E1_REG_COEF1_25_C_H_00CC Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00D0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0D0)
    #define REG_00D0_GOP0_HVSP_BKA4E1_REG_COEF2_25_C_H_00D0 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00D4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0D4)
    #define REG_00D4_GOP0_HVSP_BKA4E1_REG_COEF3_25_C_H_00D4 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00D8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0D8)
    #define REG_00D8_GOP0_HVSP_BKA4E1_REG_COEF0_50_C_H_00D8 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00DC_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0DC)
    #define REG_00DC_GOP0_HVSP_BKA4E1_REG_COEF1_50_C_H_00DC Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00E0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0E0)
    #define REG_00E0_GOP0_HVSP_BKA4E1_REG_COEF0_00_Y_V_00E0 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00E4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0E4)
    #define REG_00E4_GOP0_HVSP_BKA4E1_REG_COEF1_00_Y_V_00E4 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00E8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0E8)
    #define REG_00E8_GOP0_HVSP_BKA4E1_REG_COEF0_25_Y_V_00E8 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00EC_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0EC)
    #define REG_00EC_GOP0_HVSP_BKA4E1_REG_COEF1_25_Y_V_00EC Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00F0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0F0)
    #define REG_00F0_GOP0_HVSP_BKA4E1_REG_COEF2_25_Y_V_00F0 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_00F4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0F4)
    #define REG_00F4_GOP0_HVSP_BKA4E1_REG_COEF3_25_Y_V_00F4 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00F8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0F8)
    #define REG_00F8_GOP0_HVSP_BKA4E1_REG_COEF0_50_Y_V_00F8 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_00FC_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x0FC)
    #define REG_00FC_GOP0_HVSP_BKA4E1_REG_COEF1_50_Y_V_00FC Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0100_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x100)
    #define REG_0100_GOP0_HVSP_BKA4E1_REG_COEF0_00_C_V_0100 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0104_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x104)
    #define REG_0104_GOP0_HVSP_BKA4E1_REG_COEF1_00_C_V_0104 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0108_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x108)
    #define REG_0108_GOP0_HVSP_BKA4E1_REG_COEF0_25_C_V_0108 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_010C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x10C)
    #define REG_010C_GOP0_HVSP_BKA4E1_REG_COEF1_25_C_V_010C Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0110_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x110)
    #define REG_0110_GOP0_HVSP_BKA4E1_REG_COEF2_25_C_V_0110 Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0114_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x114)
    #define REG_0114_GOP0_HVSP_BKA4E1_REG_COEF3_25_C_V_0114 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0118_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x118)
    #define REG_0118_GOP0_HVSP_BKA4E1_REG_COEF0_50_C_V_0118 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_011C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x11C)
    #define REG_011C_GOP0_HVSP_BKA4E1_REG_COEF1_50_C_V_011C Fld(11,0,AC_MSKW10)//[10:0]
#define REG_0144_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x144)
    #define REG_0144_GOP0_HVSP_BKA4E1_REG_PSEUDO_VCLR_EN_0144 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0144_GOP0_HVSP_BKA4E1_REG_PSEUDO_VCLR_NO_0144 Fld(2,1,AC_MSKB0)//[2:1]
#define REG_014C_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x14C)
    #define REG_014C_GOP0_HVSP_BKA4E1_REG_MERGE_ADR_014C Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0180_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x180)
    #define REG_0180_GOP0_HVSP_BKA4E1_REG_HVSP_BYPASS_0180 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0180_GOP0_HVSP_BKA4E1_REG_HVSP_BUFFER_MD_0180 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0180_GOP0_HVSP_BKA4E1_REG_HVSP_ORDER_SEL_0180 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0180_GOP0_HVSP_BKA4E1_REG_HVSP_USR_MD_0180 Fld(1,4,AC_MSKB0)//[4:4]
#define REG_01C0_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x1C0)
    #define REG_01C0_GOP0_HVSP_BKA4E1_REG_VSP_EFFECT_MODE_01C0 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01C0_GOP0_HVSP_BKA4E1_REG_VSP_OVER_SHOOT_01C0 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01C0_GOP0_HVSP_BKA4E1_REG_VSP_UNDER_SHOOT_01C0 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01C4_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x1C4)
    #define REG_01C4_GOP0_HVSP_BKA4E1_REG_HSP_EFFECT_MODE_01C4 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01C4_GOP0_HVSP_BKA4E1_REG_HSP_OVER_SHOOT_01C4 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01C4_GOP0_HVSP_BKA4E1_REG_HSP_UNDER_SHOOT_01C4 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01F8_GOP0_HVSP_BKA4E1 (GOP0_HVSP_BKA4E1 + 0x1F8)
    #define REG_01F8_GOP0_HVSP_BKA4E1_REG_HVSP_SW_TRIG_P_01F8 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01F8_GOP0_HVSP_BKA4E1_REG_HVSP_SW_TRIG_MODE_01F8 Fld(1,1,AC_MSKB0)//[1:1]

