/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */
#define EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 0x6E2000

//Page EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0
#define REG_0000_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x000)
	#define REG_0000_DP_TRANS_P0_REG_PRE_MISC_LANE0_MUX Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0000_DP_TRANS_P0_REG_PRE_MISC_LANE1_MUX Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0000_DP_TRANS_P0_REG_PRE_MISC_LANE2_MUX Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0000_DP_TRANS_P0_REG_PRE_MISC_LANE3_MUX Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0000_DP_TRANS_P0_REG_PRE_MISC_PORT_MUX Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0000_DP_TRANS_P0_REG_HDCP_SEL Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0000_DP_TRANS_P0_REG_PATTERN1_EN Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0000_DP_TRANS_P0_REG_PATTERN2_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0000_DP_TRANS_P0_REG_PATTERN3_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0000_DP_TRANS_P0_REG_PATTERN4_EN Fld(1, 15, AC_MSKB1)//[15:15]
	#define REG_0000_DP_TRANS_P0_REG_PATTERN_EN Fld(4,  12,  AC_MSKB1)//[15:12]
#define REG_0004_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x004)
	#define REG_0004_DP_TRANS_P0_REG_DP_SCR_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0004_DP_TRANS_P0_REG_ALTER_SCRAMBLER_RESET_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0004_DP_TRANS_P0_REG_SCRAMB_BYPASS_IN_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0004_DP_TRANS_P0_REG_SCRAMB_BYPASS_MASK Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0004_DP_TRANS_P0_REG_INDEX_SCR_MODE Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0004_DP_TRANS_P0_REG_PAT_INIT_DISPARITY Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0004_DP_TRANS_P0_REG_TPS_DISPARITY_RESET Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_0008_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x008)
	#define REG_0008_DP_TRANS_P0_REG_LANE_SKEW_SEL_LANE0 Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0008_DP_TRANS_P0_REG_LANE_SKEW_SEL_LANE1 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0008_DP_TRANS_P0_REG_LANE_SKEW_SEL_LANE2 Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0008_DP_TRANS_P0_REG_LANE_SKEW_SEL_LANE3 Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0008_DP_TRANS_P0_REG_POST_MISC_LANE0_MUX Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_0008_DP_TRANS_P0_REG_POST_MISC_LANE1_MUX Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_0008_DP_TRANS_P0_REG_POST_MISC_LANE2_MUX Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_0008_DP_TRANS_P0_REG_POST_MISC_LANE3_MUX Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_000C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x00C)
	#define REG_000C_DP_TRANS_P0_REG_TOP_RESET_SW Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_000C_DP_TRANS_P0_REG_LANE0_RESET_SW Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_000C_DP_TRANS_P0_REG_LANE1_RESET_SW Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_000C_DP_TRANS_P0_REG_LANE2_RESET_SW Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_000C_DP_TRANS_P0_REG_LANE3_RESET_SW Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_000C_DP_TRANS_P0_REG_DP_TX_TRANSMITTER_4P_RESET_SW Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_000C_DP_TRANS_P0_REG_HDCP13_RST_SW Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_000C_DP_TRANS_P0_REG_HDCP22_RST_SW Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0018_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x018)
	#define REG_0018_DP_TRANS_P0_REG_IRQ_CLR Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0018_DP_TRANS_P0_REG_IRQ_MASK Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0018_DP_TRANS_P0_REG_IRQ_FORCE Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0018_DP_TRANS_P0_REG_IRQ_STATUS Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_001C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x01C)
	#define REG_001C_DP_TRANS_P0_REG_IRQ_CLR_51 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_001C_DP_TRANS_P0_REG_IRQ_MASK_51 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_001C_DP_TRANS_P0_REG_IRQ_FORCE_51 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_001C_DP_TRANS_P0_REG_IRQ_STATUS_51 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0028_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x028)
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_BIT_REVERSE_EN_LANE0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_BIT_REVERSE_EN_LANE1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_BIT_REVERSE_EN_LANE2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_BIT_REVERSE_EN_LANE3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_PN_SWAP_EN_LANE0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_PN_SWAP_EN_LANE1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_PN_SWAP_EN_LANE2 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_PN_SWAP_EN_LANE3 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_DATA_SWAP_EN_LANE0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_DATA_SWAP_EN_LANE1 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_DATA_SWAP_EN_LANE2 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0028_DP_TRANS_P0_REG_POST_MISC_DATA_SWAP_EN_LANE3 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_0034_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x034)
	#define REG_0034_DP_TRANS_P0_REG_OUT_ADAPTER_MODE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0034_DP_TRANS_P0_REG_IN_ADAPTER_MODE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0034_DP_TRANS_P0_REG_MST_OV_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0034_DP_TRANS_P0_REG_LANE_NUM_OV_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0034_DP_TRANS_P0_REG_TRAINING_PATTERN_OV_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0034_DP_TRANS_P0_REG_HDCP_TX_KCODE_EN Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0034_DP_TRANS_P0_REG_CPBS_STATE_DET Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_0040_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x040)
	#define REG_0040_DP_TRANS_P0_REG_PGM_PAT_EN Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0040_DP_TRANS_P0_REG_PGM_PAT_SEL_L0 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0040_DP_TRANS_P0_REG_PGM_PAT_SEL_L1 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0040_DP_TRANS_P0_REG_PGM_PAT_SEL_L2 Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_0044_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x044)
	#define REG_0044_DP_TRANS_P0_REG_PGM_PAT_SEL_L3 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0044_DP_TRANS_P0_REG_PRBS_EN Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_0048_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x048)
	#define REG_0048_DP_TRANS_P0_REG_PGM_PAT_L0_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_004C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x04C)
	#define REG_004C_DP_TRANS_P0_REG_PGM_PAT_L0_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x050)
	#define REG_0050_DP_TRANS_P0_REG_PGM_PAT_L0_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0054_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x054)
	#define REG_0054_DP_TRANS_P0_REG_PGM_PAT_L1_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0058_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x058)
	#define REG_0058_DP_TRANS_P0_REG_PGM_PAT_L1_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_005C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x05C)
	#define REG_005C_DP_TRANS_P0_REG_PGM_PAT_L1_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0060_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x060)
	#define REG_0060_DP_TRANS_P0_REG_PGM_PAT_L2_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0064_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x064)
	#define REG_0064_DP_TRANS_P0_REG_PGM_PAT_L2_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x068)
	#define REG_0068_DP_TRANS_P0_REG_PGM_PAT_L2_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_006C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x06C)
	#define REG_006C_DP_TRANS_P0_REG_PGM_PAT_L3_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0070_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x070)
	#define REG_0070_DP_TRANS_P0_REG_PGM_PAT_L3_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0074_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x074)
	#define REG_0074_DP_TRANS_P0_REG_PGM_PAT_L3_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0078_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x078)
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN2 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_KCODE_ERROR_LANE0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_KCODE_ERROR_LANE1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_KCODE_ERROR_LANE2 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_KCODE_ERROR_LANE3 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_DCODE_ERROR_LANE0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_DCODE_ERROR_LANE1 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_DCODE_ERROR_LANE2 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0078_DP_TRANS_P0_REG_CP2520_PATTERN1_DCODE_ERROR_LANE3 Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_007C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x07C)
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_KCODE_ERROR_LANE0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_KCODE_ERROR_LANE1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_KCODE_ERROR_LANE2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_KCODE_ERROR_LANE3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_DCODE_ERROR_LANE0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_DCODE_ERROR_LANE1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_DCODE_ERROR_LANE2 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN2_DCODE_ERROR_LANE3 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_KCODE_ERROR_LANE0 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_KCODE_ERROR_LANE1 Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_KCODE_ERROR_LANE2 Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_KCODE_ERROR_LANE3 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_DCODE_ERROR_LANE0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_DCODE_ERROR_LANE1 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_DCODE_ERROR_LANE2 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_007C_DP_TRANS_P0_REG_CP2520_PATTERN3_DCODE_ERROR_LANE3 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0080_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x080)
	#define REG_0080_DP_TRANS_P0_REG_DP_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0080_DP_TRANS_P0_REG_SELECT_INTERNAL_AN Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0080_DP_TRANS_P0_REG_AN_FREERUN Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0080_DP_TRANS_P0_REG_KM_GENERATED Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0080_DP_TRANS_P0_REG_HDCP_MST_TYPE_UPDATE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0080_DP_TRANS_P0_REG_HDCP_MST_TIMESLOT_UPDATE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0080_DP_TRANS_P0_REG_HDCP_MST_TIMESLOT_BIT0_UPDATE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0080_DP_TRANS_P0_REG_MST_FORCE_CPBS_CPSR_SR_DET Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0080_DP_TRANS_P0_REG_SYMBOL_DATA_SEL Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0080_DP_TRANS_P0_REG_HDCP_1LANE_SEL Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0080_DP_TRANS_P0_REG_HDCP_24LANE_SEL Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0080_DP_TRANS_P0_REG_MST_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00A4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0A4)
	#define REG_00A4_DP_TRANS_P0_REG_EN_COPY_2LANE_MSA Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A4_DP_TRANS_P0_REG_EN_COPY_4LANE_MSA Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00A4_DP_TRANS_P0_REG_LANE_NUM Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00A4_DP_TRANS_P0_REG_HDCP22_AUTH_DONE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00A4_DP_TRANS_P0_REG_DISCARD_UNUSED_CIPHER Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_00A4_DP_TRANS_P0_REG_HDCP22_CIPHER_REVERSE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_00A4_DP_TRANS_P0_REG_MST_DELAY_CYCLE_FLAG_SEL Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_00A4_DP_TRANS_P0_REG_TEST_CONFIG_HDCP22 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_00A4_DP_TRANS_P0_REG_R0_AVAILABLE Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_00A4_DP_TRANS_P0_REG_DPES_TX_HDCP22 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_00A4_DP_TRANS_P0_REG_DP_AES_OUT_RDY_L Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_00A4_DP_TRANS_P0_REG_REPEATER_I Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00A8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0A8)
	#define REG_00A8_DP_TRANS_P0_REG_TEST_CONFIG_HDCP13 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00D0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0D0)
	#define REG_00D0_DP_TRANS_P0_REG_TX_HDCP22_TYPE Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00D4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0D4)
	#define REG_00D4_DP_TRANS_P0_REG_DP_AES_INCTR_L_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00D8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0D8)
	#define REG_00D8_DP_TRANS_P0_REG_DP_AES_INCTR_L_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00DC_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0DC)
	#define REG_00DC_DP_TRANS_P0_REG_DP_AES_INCTR_L_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0E0)
	#define REG_00E0_DP_TRANS_P0_REG_DP_AES_INCTR_L_3 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0E4)
	#define REG_00E4_DP_TRANS_P0_REG_HDCP_TYPE_TX_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00E8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0E8)
	#define REG_00E8_DP_TRANS_P0_REG_HDCP_TYPE_TX_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00EC_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0EC)
	#define REG_00EC_DP_TRANS_P0_REG_HDCP_TYPE_TX_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00F0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0F0)
	#define REG_00F0_DP_TRANS_P0_REG_HDCP_TYPE_TX_3 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00F4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0F4)
	#define REG_00F4_DP_TRANS_P0_REG_SST_HDCP_TYPE_TX Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00F8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0F8)
	#define REG_00F8_DP_TRANS_P0_REG_DP_AES_OUT_RDY_H Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_00FC_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x0FC)
	#define REG_00FC_DP_TRANS_P0_REG_HDCP_4P_TO_2P_FIFO_RST_CHK Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_00FC_DP_TRANS_P0_REG_HDCP_2P_TO_4P_FIFO_RST_CHK Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0100_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x100)
	#define REG_0100_DP_TRANS_P0_REG_DP_AES_INCTR_H_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0104_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x104)
	#define REG_0104_DP_TRANS_P0_REG_DP_AES_INCTR_H_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0108_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x108)
	#define REG_0108_DP_TRANS_P0_REG_DP_AES_INCTR_H_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_010C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x10C)
	#define REG_010C_DP_TRANS_P0_REG_DP_AES_INCTR_H_3 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0110_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x110)
	#define REG_0110_DP_TRANS_P0_REG_HDCP22_TYPE Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0114_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x114)
	#define REG_0114_DP_TRANS_P0_REG_PSR1_TIME Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0114_DP_TRANS_P0_REG_PSR2_TIME Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0114_DP_TRANS_P0_REG_PR_TIME Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0114_DP_TRANS_P0_REG_PSR1_TIME_FEC Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0118_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x118)
	#define REG_0118_DP_TRANS_P0_REG_PSR2_TIME_FEC Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0118_DP_TRANS_P0_REG_PR_TIME_FEC Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0118_DP_TRANS_P0_REG_PSR1_SCRB_TIME Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0118_DP_TRANS_P0_REG_PSR2_SCRB_TIME Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_011C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x11C)
	#define REG_011C_DP_TRANS_P0_REG_PR_SCRB_TIME Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_0120_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x120)
	#define REG_0120_DP_TRANS_P0_REG_SLEEP_KCODE_1 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0120_DP_TRANS_P0_REG_SLEEP_KCODE_2 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0124_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x124)
	#define REG_0124_DP_TRANS_P0_REG_SLEEP_KCODE_3 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0124_DP_TRANS_P0_REG_SLEEP_KCODE_4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0128_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x128)
	#define REG_0128_DP_TRANS_P0_REG_SLEEP_KCODE_5 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0128_DP_TRANS_P0_REG_SLEEP_KCODE_6 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_012C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x12C)
	#define REG_012C_DP_TRANS_P0_REG_SLEEP_KCODE_7 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_012C_DP_TRANS_P0_REG_SLEEP_KCODE_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0130_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x130)
	#define REG_0130_DP_TRANS_P0_REG_STANDBY_KCODE_1 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0130_DP_TRANS_P0_REG_STANDBY_KCODE_2 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0134_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x134)
	#define REG_0134_DP_TRANS_P0_REG_STANDBY_KCODE_3 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0134_DP_TRANS_P0_REG_STANDBY_KCODE_4 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0138_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x138)
	#define REG_0138_DP_TRANS_P0_REG_STANDBY_KCODE_5 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0138_DP_TRANS_P0_REG_STANDBY_KCODE_6 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_013C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x13C)
	#define REG_013C_DP_TRANS_P0_REG_STANDBY_KCODE_7 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_013C_DP_TRANS_P0_REG_STANDBY_KCODE_8 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0140_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x140)
	#define REG_0140_DP_TRANS_P0_REG_FEC_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0140_DP_TRANS_P0_REG_FEC_END_MODE Fld(2, 1, AC_MSKB0)//[2:1]
	#define REG_0140_DP_TRANS_P0_REG_FEC_CLOCK_EN_MODE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0140_DP_TRANS_P0_REG_FEC_FIFO_READ_START Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0140_DP_TRANS_P0_REG_FEC_FIFO_UNDER_POINT Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0140_DP_TRANS_P0_REG_FEC_FIFO_OVER_POINT Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0144_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x144)
	#define REG_0144_DP_TRANS_P0_REG_FEC_FIFO_RST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0144_DP_TRANS_P0_REG_FEC_SUPPORT Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0144_DP_TRANS_P0_REG_FEC_PATTERN_NEW Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0144_DP_TRANS_P0_REG_FEC_INSERT_FIFO_EMPTY Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0144_DP_TRANS_P0_REG_FEC_INSERT_FIFO_EMPTY_CLR Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0144_DP_TRANS_P0_REG_FEC_INSERT_FIFO_FULL Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0144_DP_TRANS_P0_REG_FEC_INSERT_FIFO_FULL_CLR Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0144_DP_TRANS_P0_REG_PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0144_DP_TRANS_P0_REG_PAT_INIT_DISPARITY_FEC Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0144_DP_TRANS_P0_REG_FEC_PARITY_DATA_LANE_SWAP Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0144_DP_TRANS_P0_REG_FEC_CLOCK_UNDER_MASK Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0144_DP_TRANS_P0_REG_FEC_FORCE_MODE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0144_DP_TRANS_P0_REG_FEC_ENABLE_FLAG Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0148_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x148)
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_CNT_LANE0 Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_LANE0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_CNT_LANE1 Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_LANE1 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_CNT_LANE2 Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_LANE2 Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_CNT_LANE3 Fld(3, 12, AC_MSKB1)//[14:12]
	#define REG_0148_DP_TRANS_P0_REG_FEC_INSERT_SYMBOL_ERROR_LANE3 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_014C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x14C)
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_HIT_LANE0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_HIT_LANE1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_HIT_LANE2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_HIT_LANE3 Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_HIT_CLR Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_014C_DP_TRANS_P0_REG_FEC_FIFO_READ_START_BIT4 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_014C_DP_TRANS_P0_REG_FEC_FIFO_UNDER_POINT_BIT4 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_014C_DP_TRANS_P0_REG_FEC_FIFO_OVER_POINT_BIT4 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_014C_DP_TRANS_P0_REG_FEC_ENCODE_TOP_TESTBUS_SEL Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_014C_DP_TRANS_P0_REG_FEC_INSERT_TOP_TESTBUS_SEL Fld(2, 10, AC_MSKB1)//[11:10]
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_REPLACE_SEL Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_014C_DP_TRANS_P0_REG_FEC_CP_REPLACE_EN Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_0150_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x150)
	#define REG_0150_DP_TRANS_P0_REG_FEC_INSERT_FIFO_WCNT Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0150_DP_TRANS_P0_REG_FEC_INSERT_FIFO_RCNT Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0154_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x154)
	#define REG_0154_DP_TRANS_P0_REG_FEC_CLK_GATE_DATA_CNT_0 Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_0158_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x158)
	#define REG_0158_DP_TRANS_P0_REG_FEC_CLK_GATE_DATA_CNT_1_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_015C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x15C)
	#define REG_015C_DP_TRANS_P0_REG_FEC_CLK_GATE_DATA_CNT_1_1 Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0160_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x160)
	#define REG_0160_DP_TRANS_P0_REG_FEC_EN_SW_MODE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0160_DP_TRANS_P0_REG_FEC_STATE_RST Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0160_DP_TRANS_P0_REG_POST_CNT_TIME Fld(8, 2, AC_MSKW10)//[9:2]
	#define REG_0160_DP_TRANS_P0_REG_PSR_TPS_OFF Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0160_DP_TRANS_P0_REG_PSR1_TPS234_SEL Fld(2, 11, AC_MSKB1)//[12:11]
#define REG_0164_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x164)
	#define REG_0164_DP_TRANS_P0_REG_VBID_DATA Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0164_DP_TRANS_P0_REG_DUMMY_DATA Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0168_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x168)
	#define REG_0168_DP_TRANS_P0_REG_AUDIO_M_CODE Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0168_DP_TRANS_P0_REG_VIDEO_M_CODE Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_016C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x16C)
	#define REG_016C_DP_TRANS_P0_REG_SR_GEN_THRD Fld(9, 0, AC_MSKW10)//[8:0]
	#define REG_016C_DP_TRANS_P0_REG_SR_GEN_CNT_RST Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_016C_DP_TRANS_P0_REG_VIDEO_MUTE_CNT_RST Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0170_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x170)
	#define REG_0170_DP_TRANS_P0_REG_SST_VIDEO_MUTE_CNT_THRD Fld(14, 0, AC_MSKW10)//[13:0]
#define REG_0174_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x174)
	#define REG_0174_DP_TRANS_P0_REG_PSR2_SLEEP_TIMEOUT_VALUE Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0178_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x178)
	#define REG_0178_DP_TRANS_P0_REG_ALPM_PAT_OW_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0178_DP_TRANS_P0_REG_ALPM_PAT_OW_VALUE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0178_DP_TRANS_P0_REG_IDLE_PAT_OW_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0178_DP_TRANS_P0_REG_IDLE_PAT_OW_VALUE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0178_DP_TRANS_P0_REG_DUMMY_TIME Fld(8, 4, AC_MSKW10)//[11:4]
#define REG_017C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x17C)
	#define REG_017C_DP_TRANS_P0_REG_PSR_FEC_DELAY Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_017C_DP_TRANS_P0_REG_PSR2_ALPM_TIMEOUT_MODE Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0180_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x180)
	#define REG_0180_DP_TRANS_P0_REG_DP_TX_TRANS_TESTBUS_SEL Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0180_DP_TRANS_P0_REG_POST_MISC_DATA_LANE0_OV Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0180_DP_TRANS_P0_REG_POST_MISC_DATA_LANE1_OV Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0180_DP_TRANS_P0_REG_POST_MISC_DATA_LANE2_OV Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0180_DP_TRANS_P0_REG_POST_MISC_DATA_LANE3_OV Fld(1, 11, AC_MSKB1)//[11:11]
#define REG_0184_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x184)
	#define REG_0184_DP_TRANS_P0_REG_POST_MISC_DATA_LANE0_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0188_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x188)
	#define REG_0188_DP_TRANS_P0_REG_POST_MISC_DATA_LANE0_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_018C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x18C)
	#define REG_018C_DP_TRANS_P0_REG_POST_MISC_DATA_LANE0_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0190_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x190)
	#define REG_0190_DP_TRANS_P0_REG_POST_MISC_DATA_LANE1_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0194_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x194)
	#define REG_0194_DP_TRANS_P0_REG_POST_MISC_DATA_LANE1_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0198_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x198)
	#define REG_0198_DP_TRANS_P0_REG_POST_MISC_DATA_LANE1_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_019C_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x19C)
	#define REG_019C_DP_TRANS_P0_REG_POST_MISC_DATA_LANE2_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1A0)
	#define REG_01A0_DP_TRANS_P0_REG_POST_MISC_DATA_LANE2_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1A4)
	#define REG_01A4_DP_TRANS_P0_REG_POST_MISC_DATA_LANE2_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_01A8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1A8)
	#define REG_01A8_DP_TRANS_P0_REG_POST_MISC_DATA_LANE3_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01AC_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1AC)
	#define REG_01AC_DP_TRANS_P0_REG_POST_MISC_DATA_LANE3_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01B0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1B0)
	#define REG_01B0_DP_TRANS_P0_REG_POST_MISC_DATA_LANE3_2 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_01B4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1B4)
	#define REG_01B4_DP_TRANS_P0_REG_FEC_OUT_ADAPTER_TESTBUS_MUX Fld(4, 0, AC_MSKB0)//[3:0]
#define REG_01C0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1C0)
	#define REG_01C0_DP_TRANS_P0_REG_SW_IRQ_SRC Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1C4)
	#define REG_01C4_DP_TRANS_P0_REG_SW_IRQ_MASK Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1C8)
	#define REG_01C8_DP_TRANS_P0_REG_SW_IRQ_CLR Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01CC_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1CC)
	#define REG_01CC_DP_TRANS_P0_REG_SW_IRQ_STATUS Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1D0)
	#define REG_01D0_DP_TRANS_P0_REG_SW_IRQ_FINAL_STATUS Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1D4)
	#define REG_01D4_DP_TRANS_P0_REG_SW_IRQ_RAW_STATUS Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1D8)
	#define REG_01D8_DP_TRANS_P0_REG_SW_IRQ_FORCE Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F0_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1F0)
	#define REG_0008_DP_TRANS_P0_REG_DP_TRANSMITTER_DUMMY_RW_0_LANE_SETTING  Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_01F0_DP_TRANS_P0_REG_DP_TRANSMITTER_DUMMY_RW_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F4_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1F4)
	#define REG_01F4_DP_TRANS_P0_REG_DP_TRANSMITTER_DUMMY_RW_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F8_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1F8)
	#define REG_01F8_DP_TRANS_P0_REG_DP_TRANSMITTER_DUMMY_R_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01FC_DP_TRANS_P0 (EDP12_TV_TX_PAR_WRAP_EDPTX_TRANS_P0 + 0x1FC)
	#define REG_01FC_DP_TRANS_P0_REG_DP_TRANSMITTER_DUMMY_R_1 Fld(16, 0, AC_FULLW10)//[15:0]
