#define LPLL_V005 0x486000

//Page LPLL_V005
#define REG_0004_LPLL_V005 (LPLL_V005 + 0x004)
	#define REG_0004_LPLL_V005_REG_LPLL_V0051_LOOP_DIV_FIRST_0004 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0004_LPLL_V005_REG_LPLL_V0051_LOOP_DIV_SECOND_0004 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0008_LPLL_V005 (LPLL_V005 + 0x008)
	#define REG_0008_LPLL_V005_REG_LPLL_V0051_SCALAR_DIV_FIRST_0008 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0008_LPLL_V005_REG_LPLL_V0051_SCALAR_DIV_SECOND_0008 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_000C_LPLL_V005 (LPLL_V005 + 0x00C)
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_ICP_ICTRL_000C Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_IBIAS_ICTRL_000C Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_PD_000C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_2CHIP_SYN_EN_000C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_EN_DDR_000C Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_ENFRUNZ_000C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_EN_SKEW_DIVIDER_000C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_SDIV2P5_EN_000C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_FIFO_DIV5_EN_000C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_TEST_EN_SDIV_000C Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_TEST_EN_FIFO_000C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_LOCK_000C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_000C_LPLL_V005_REG_LPLL_V0051_HIGH_FLAG_000C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0010_LPLL_V005 (LPLL_V005 + 0x010)
	#define REG_0010_LPLL_V005_REG_LPLL_V0051_SKEW_CLK1_PHASE_SEL_0010 Fld(5,0,AC_MSKB0)//[4:0]
	#define REG_0010_LPLL_V005_REG_LPLL_V0051_SKEW_CLK2_PHASE_SEL_0010 Fld(5,8,AC_MSKB1)//[12:8]
	#define REG_0010_LPLL_V005_REG_LPLL_V0051_SDIV3P5_EN_0010 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0010_LPLL_V005_REG_PRD_STABLE_THRESEL_0010 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0014_LPLL_V005 (LPLL_V005 + 0x014)
	#define REG_0014_LPLL_V005_REG_PRD_STABLE_THRESH_0014 Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_0014_LPLL_V005_REG_PRD_LOCK_THRESH_0014 Fld(4,4,AC_MSKB0)//[7:4]
	#define REG_0014_LPLL_V005_REG_PHASE_LOCK_THRESH_0014 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0018_LPLL_V005 (LPLL_V005 + 0x018)
	#define REG_0018_LPLL_V005_REG_LIMIT_D5D6D7_0_0018 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_LPLL_V005 (LPLL_V005 + 0x01C)
	#define REG_001C_LPLL_V005_REG_LIMIT_D5D6D7_1_001C Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0020_LPLL_V005 (LPLL_V005 + 0x020)
	#define REG_0020_LPLL_V005_REG_LIMIT_D5D6D7_RK_0_0020 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_LPLL_V005 (LPLL_V005 + 0x024)
	#define REG_0024_LPLL_V005_REG_LIMIT_D5D6D7_RK_1_0024 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0028_LPLL_V005 (LPLL_V005 + 0x028)
	#define REG_0028_LPLL_V005_REG_LIMIT_LPLL_V005_OFFSET_0028 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_LPLL_V005 (LPLL_V005 + 0x02C)
	#define REG_002C_LPLL_V005_REG_I_GAIN_PRD_002C Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_002C_LPLL_V005_REG_P_GAIN_PRD_002C Fld(4,4,AC_MSKB0)//[7:4]
	#define REG_002C_LPLL_V005_REG_I_GAIN_PHASE_002C Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_002C_LPLL_V005_REG_P_GAIN_PHASE_002C Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0030_LPLL_V005 (LPLL_V005 + 0x030)
	#define REG_0030_LPLL_V005_REG_FPLL_MODE_0030 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0030_LPLL_V005_REG_FRAME_LPLL_V005_EN_0030 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0030_LPLL_V005_REG_I_GAIN_PRD_ZERO_0030 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0030_LPLL_V005_REG_P_GAIN_PRD_ZERO_0030 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0030_LPLL_V005_REG_I_GAIN_PHASE_ZERO_0030 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0030_LPLL_V005_REG_P_GAIN_PHASE_ZERO_0030 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_0030_LPLL_V005_REG_IVS_FRAME_DIV_0030 Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_0030_LPLL_V005_REG_OVS_FRAME_DIV_0030 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0034_LPLL_V005 (LPLL_V005 + 0x034)
	#define REG_0034_LPLL_V005_REG_FORCE_PRD_STABLE_0034 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0034_LPLL_V005_REG_FORCE_PRD_LOCK_DONE_0034 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0034_LPLL_V005_REG_FORCE_PHASE_REDUCE_DONE_0034 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0034_LPLL_V005_REG_FORCE_PHASE_CLOSE_DONE_0034 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0034_LPLL_V005_REG_EN_2_LIMIT_0034 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0034_LPLL_V005_REG_NO_SIGNAL_EN_0034 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0034_LPLL_V005_REG_NON_STABLE_EN_0034 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0034_LPLL_V005_REG_SSC_EN_0034 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_0034_LPLL_V005_REG_SYNTH_CLK_DIV2_SEL_0034 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0038_LPLL_V005 (LPLL_V005 + 0x038)
	#define REG_0038_LPLL_V005_REG_EXT_IVS_FRAME_DIV_0038 Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_0038_LPLL_V005_REG_EXT_OVS_FRAME_DIV_0038 Fld(4,4,AC_MSKB0)//[7:4]
#define REG_003C_LPLL_V005 (LPLL_V005 + 0x03C)
	#define REG_003C_LPLL_V005_REG_PLL_SET_0_003C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_LPLL_V005 (LPLL_V005 + 0x040)
	#define REG_0040_LPLL_V005_REG_PLL_SET_1_0040 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0044_LPLL_V005 (LPLL_V005 + 0x044)
	#define REG_0044_LPLL_V005_REG_PHASE_DIF_0044 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_LPLL_V005 (LPLL_V005 + 0x048)
	#define REG_0048_LPLL_V005_REG_PHASE_UP_0048 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_004C_LPLL_V005 (LPLL_V005 + 0x04C)
	#define REG_004C_LPLL_V005_REG_PRD_DIF_004C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_LPLL_V005 (LPLL_V005 + 0x050)
	#define REG_0050_LPLL_V005_REG_PRD_UP_0050 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0054_LPLL_V005 (LPLL_V005 + 0x054)
	#define REG_0054_LPLL_V005_REG_LPLL_V0051_INPUT_DIV_FIRST_0054 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0054_LPLL_V005_REG_LPLL_V0051_INPUT_DIV_SECOND_0054 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0058_LPLL_V005 (LPLL_V005 + 0x058)
	#define REG_0058_LPLL_V005_REG_LPLL_V005_TESTD_A_0058 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_0058_LPLL_V005_REG_LPLL_V005_TESTD_0058 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_005C_LPLL_V005 (LPLL_V005 + 0x05C)
	#define REG_005C_LPLL_V005_REG_LPLL_V005_STEP_005C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_LPLL_V005 (LPLL_V005 + 0x060)
	#define REG_0060_LPLL_V005_REG_LPLL_V005_SPAN_0060 Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0064_LPLL_V005 (LPLL_V005 + 0x064)
	#define REG_0064_LPLL_V005_REG_IDCLK_DIV_0_0064 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_LPLL_V005 (LPLL_V005 + 0x068)
	#define REG_0068_LPLL_V005_REG_IDCLK_DIV_1_0068 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_006C_LPLL_V005 (LPLL_V005 + 0x06C)
	#define REG_006C_LPLL_V005_REG_ODCLK_DIV_0_006C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_LPLL_V005 (LPLL_V005 + 0x070)
	#define REG_0070_LPLL_V005_REG_ODCLK_DIV_1_0070 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_0074_LPLL_V005 (LPLL_V005 + 0x074)
	#define REG_0074_LPLL_V005_REG_DEC_V_LIMIT_0074 Fld(13,0,AC_MSKW10)//[12:0]
	#define REG_0074_LPLL_V005_REG_FIX_DEC_EN_0074 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0078_LPLL_V005 (LPLL_V005 + 0x078)
	#define REG_0078_LPLL_V005_REG_INC_V_LIMIT_0078 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_007C_LPLL_V005 (LPLL_V005 + 0x07C)
	#define REG_007C_LPLL_V005_REG_PHASE_CLOSE_THRESH_007C Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_007C_LPLL_V005_REG_REDUCE_DONE_THRESH_007C Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0080_LPLL_V005 (LPLL_V005 + 0x080)
	#define REG_0080_LPLL_V005_REG_HIS_CNT_LOW_THRESH_0080 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0080_LPLL_V005_REG_HIS_CNT_HIGH_THRESH_0080 Fld(3,4,AC_MSKB0)//[6:4]
#define REG_0084_LPLL_V005 (LPLL_V005 + 0x084)
	#define REG_0084_LPLL_V005_REG_IVS_PRD_VALUE_0_0084 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_LPLL_V005 (LPLL_V005 + 0x088)
	#define REG_0088_LPLL_V005_REG_IVS_PRD_VALUE_1_0088 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_008C_LPLL_V005 (LPLL_V005 + 0x08C)
	#define REG_008C_LPLL_V005_REG_OVS_PRD_VALUE_0_008C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_LPLL_V005 (LPLL_V005 + 0x090)
	#define REG_0090_LPLL_V005_REG_OVS_PRD_VALUE_1_0090 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0098_LPLL_V005 (LPLL_V005 + 0x098)
	#define REG_0098_LPLL_V005_REG_FIX_V_TOTAL_0098 Fld(13,0,AC_MSKW10)//[12:0]
	#define REG_0098_LPLL_V005_REG_FIX_V_DEC_0098 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_009C_LPLL_V005 (LPLL_V005 + 0x09C)
	#define REG_009C_LPLL_V005_REG_FIX_H_TOTAL_009C Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00A0_LPLL_V005 (LPLL_V005 + 0x0A0)
	#define REG_00A0_LPLL_V005_REG_PLL_SET_USING_0_00A0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_LPLL_V005 (LPLL_V005 + 0x0A4)
	#define REG_00A4_LPLL_V005_REG_PLL_SET_USING_1_00A4 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_00A8_LPLL_V005 (LPLL_V005 + 0x0A8)
	#define REG_00A8_LPLL_V005_REG_CS_STATE_00A8 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_00A8_LPLL_V005_REG_OVS_PRD_STABLE_00A8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_00A8_LPLL_V005_REG_IVS_PRD_STABLE_00A8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00A8_LPLL_V005_REG_PRD_LOCK_DONE_00A8 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00A8_LPLL_V005_REG_PHASE_REDUCE_DONE_00A8 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_00A8_LPLL_V005_REG_PHASE_LOCK_DONE_00A8 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_00AC_LPLL_V005 (LPLL_V005 + 0x0AC)
	#define REG_00AC_LPLL_V005_REG_LPLL_V005_SYN_CLK_SEL_00AC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00AC_LPLL_V005_REG_LPLL_V0051_VFB_SEL_00AC Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_00AC_LPLL_V005_REG_LPLL_V0051_MODE_SEL_00AC Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_00AC_LPLL_V005_REG_LPLL_V0051_VREF_SEL_00AC Fld(2,14,AC_MSKB1)//[15:14]
#define REG_00B0_LPLL_V005 (LPLL_V005 + 0x0B0)
	#define REG_00B0_LPLL_V005_REG_LPLL_V005_LOOP_DIV_00B0 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_00B0_LPLL_V005_REG_LPLL_V005_LOOP_GAIN_00B0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B8_LPLL_V005 (LPLL_V005 + 0x0B8)
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_FIFO_DIV_00B8 Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_EN_SCALAR_00B8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_VCO_SEL_00B8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_EN_FIFO_00B8 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_EN_VBY1_DIFF_00B8 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_EN_FIX_CLK_00B8 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_EN_SKEW_CLK_00B8 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_EN_MINI_00B8 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_00B8_LPLL_V005_REG_LPLL_V0051_DUAP_LP_EN_00B8 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00BC_LPLL_V005 (LPLL_V005 + 0x0BC)
	#define REG_00BC_LPLL_V005_REG_PD_MPLL_TEST_CLKD_00BC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00BC_LPLL_V005_REG_PD_LPLL_V005_SCALAR_00BC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00BC_LPLL_V005_REG_PD_LPLL_V005_FIFO_00BC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_00BC_LPLL_V005_REG_PD_LPLL_V005_SYN432_00BC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_00BC_LPLL_V005_REG_PD_LPLL_V005_MASTER_TEST_CLK_00BC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_00BC_LPLL_V005_REG_PD_LPLL_V005_SLAVE_TEST_CLK_00BC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00BC_LPLL_V005_REG_PD_LPLL_V005_OSD_TEST_CLK_00BC Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00BC_LPLL_V005_REG_LPLL_V0051_MASTER_SLAVE_DIV_FIRST_00BC Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_00BC_LPLL_V005_REG_LPLL_V0051_MASTER_SLAVE_DIV5_EN_00BC Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_00BC_LPLL_V005_REG_LPLL_V0051_MASTER_SLAVE_EN_00BC Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_00BC_LPLL_V005_REG_LPLL_V0051_MASTER_SLAVE_DIV3_EN_00BC Fld(1,12,AC_MSKB1)//[12:12]
#define REG_00C0_LPLL_V005 (LPLL_V005 + 0x0C0)
	#define REG_00C0_LPLL_V005_REG_LPLL_V0052_INPUT_DIV_00C0 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_00C0_LPLL_V005_REG_LPLL_V0052_INPUT_DIV_SECOND_00C0 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_LPLL_V005 (LPLL_V005 + 0x0C4)
	#define REG_00C4_LPLL_V005_REG_LPLL_V0052_LOOP_DIV_FIRST_00C4 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_00C4_LPLL_V005_REG_LPLL_V0052_SYN2_EN_00C4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_00C4_LPLL_V005_REG_LPLL_V0052_LOOP_DIV_SECOND_00C4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C8_LPLL_V005 (LPLL_V005 + 0x0C8)
	#define REG_00C8_LPLL_V005_REG_LPLL_V0052_POST_DIV_00C8 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_00C8_LPLL_V005_REG_LPLL_V0052_POST_DIV_SECOND_00C8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_LPLL_V005 (LPLL_V005 + 0x0CC)
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_ICP_ICTRL_00CC Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_PD_00CC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_PORST_00CC Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_DIV14_EN_00CC Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_ENFRUNZ_00CC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_IBIAS_CTRL_00CC Fld(4,9,AC_MSKB1)//[12:9]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_IBIAS_CTRL_EXTRA_00CC Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_LOCK_00CC Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_00CC_LPLL_V005_REG_LPLL_V0052_HIGH_FLAG_00CC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00D0_LPLL_V005 (LPLL_V005 + 0x0D0)
	#define REG_00D0_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL1_00D0 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_00D0_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL2_00D0 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00D4_LPLL_V005 (LPLL_V005 + 0x0D4)
	#define REG_00D4_LPLL_V005_REG_LPLL_V005_2CHIP_CLKOUT_SEL_00D4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00D4_LPLL_V005_REG_LPLL_V005_2CHIP_FBIN_SEL_00D4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00D4_LPLL_V005_REG_LPLL_V005_2CHIP_REFIN_SEL_00D4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_00D4_LPLL_V005_REG_LPLL_V005_2NDPLL_CLK_SEL_00D4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00D4_LPLL_V005_REG_LPLL_V0051_EN_2CHIP_SEL_00D4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00D4_LPLL_V005_REG_LPLL_V0051_EN_CLKREF_FROM_OTHER_CHIP_00D4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_00D4_LPLL_V005_REG_LPLL_V0051_PD_PHDAC_00D4 Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_00D4_LPLL_V005_REG_LPLL_V0051_SKEW_DIV_00D4 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_00D8_LPLL_V005 (LPLL_V005 + 0x0D8)
	#define REG_00D8_LPLL_V005_REG_LPLL_V0051_TEST_0_00D8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_LPLL_V005 (LPLL_V005 + 0x0DC)
	#define REG_00DC_LPLL_V005_REG_LPLL_V0051_TEST_1_00DC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_LPLL_V005 (LPLL_V005 + 0x0E0)
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_NCO_RETIME_SEL_00E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_SKEW1_DELAY1T_00E0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_SKEW2_DELAY1T_00E0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_SKEW3_DELAY1T_00E0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_SKEW4_DELAY1T_00E0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_SCALAR2FIFO_DIV2_00E0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_00E0_LPLL_V005_REG_LPLL_V0051_SCALAR2FIFO_EN_00E0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_00E4_LPLL_V005 (LPLL_V005 + 0x0E4)
	#define REG_00E4_LPLL_V005_REG_LPLL_V0052_TEST_00E4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_LPLL_V005 (LPLL_V005 + 0x0E8)
	#define REG_00E8_LPLL_V005_REG_LPLL_V0051_CLKIN_SEL_00E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00E8_LPLL_V005_REG_LPLL_V0051_RX_CLKFB_SEL_00E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00E8_LPLL_V005_REG_LPLL_V005_2CHIP_SCALAR_FB_DIV_00E8 Fld(4,4,AC_MSKB0)//[7:4]
#define REG_00EC_LPLL_V005 (LPLL_V005 + 0x0EC)
	#define REG_00EC_LPLL_V005_REG_FORCE_DISABLE_FPLL_00EC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_00EC_LPLL_V005_REG_AUTO_DISABLE_FPLL_EN_00EC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_00EC_LPLL_V005_REG_LPLL_V005_DUMMY0_00EC Fld(14,2,AC_MSKW10)//[15:2]
#define REG_00F0_LPLL_V005 (LPLL_V005 + 0x0F0)
	#define REG_00F0_LPLL_V005_REG_LPLL_V005_DUMMY1_00F0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_LPLL_V005 (LPLL_V005 + 0x0F4)
	#define REG_00F4_LPLL_V005_REG_IVS_OVS_PHASE_DIF_0_00F4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_LPLL_V005 (LPLL_V005 + 0x0F8)
	#define REG_00F8_LPLL_V005_REG_IVS_OVS_PHASE_DIF_1_00F8 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_00FC_LPLL_V005 (LPLL_V005 + 0x0FC)
	#define REG_00FC_LPLL_V005_REG_IVS_OVS_PHASE_UP_00FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0100_LPLL_V005 (LPLL_V005 + 0x100)
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_EN_DDR_0100 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_EN_FIFO_0100 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_EN_MINI_0100 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_EN_SCALAR_0100 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_DUAL_LP_EN_0100 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_FIFO_DIV5_EN_0100 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SCALAR2FIFO_EN_0100 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SDIV2P5_EN_0100 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SDIV3P5_EN_0100 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SKEW_EN_FIXCLK_0100 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SKEW_EN_SKEWCLK_0100 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_TEST_EN_SDIV_0100 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_TEST_FIFO_EN_0100 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_PD_0100 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SEL_SKEW1_DELAY1T_0100 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0100_LPLL_V005_REG_LPLL_V005O_SEL_SKEW2_DELAY1T_0100 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0104_LPLL_V005 (LPLL_V005 + 0x104)
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_ICTRL_0104 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_INPUT_DIV_FIRST_0104 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_SCALAR_DIV_FIRST_0104 Fld(2,6,AC_MSKB0)//[7:6]
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_SCALAR_DIV_SECOND_0104 Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_LOOP_DIV_FIRST_0104 Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_LOCK_0104 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0104_LPLL_V005_REG_LPLL_V005O_HIGH_FLAG_0104 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0108_LPLL_V005 (LPLL_V005 + 0x108)
	#define REG_0108_LPLL_V005_REG_LPLL_V005O_LOOP_DIV_SECOND_0108 Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_0108_LPLL_V005_REG_LPLL_V005O_FIFO_DIV_0108 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0108_LPLL_V005_REG_LPLL_V005O_SKEW_DIV_0108 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0108_LPLL_V005_REG_LPLL_V005O_SKEW1_FINE_0108 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_010C_LPLL_V005 (LPLL_V005 + 0x10C)
	#define REG_010C_LPLL_V005_REG_LPLL_V005O_SKEW2_FINE_010C Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_010C_LPLL_V005_REG_LPLL_V005O_SKEW1_COARSE_010C Fld(4,4,AC_MSKB0)//[7:4]
	#define REG_010C_LPLL_V005_REG_LPLL_V005O_SKEW2_COARSE_010C Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_010C_LPLL_V005_REG_LPLL_V005O_SCALAR2FIFO_DIV2_010C Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_010C_LPLL_V005_REG_LPLL_V005O_EN_VBY1_HS_010C Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0110_LPLL_V005 (LPLL_V005 + 0x110)
	#define REG_0110_LPLL_V005_REG_LPLL_V005O_TEST_0_0110 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0114_LPLL_V005 (LPLL_V005 + 0x114)
	#define REG_0114_LPLL_V005_REG_LPLL_V005O_TEST_1_0114 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0128_LPLL_V005 (LPLL_V005 + 0x128)
	#define REG_0128_LPLL_V005_REG_PLL_SET_USING_FPLL_0_0128 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_012C_LPLL_V005 (LPLL_V005 + 0x12C)
	#define REG_012C_LPLL_V005_REG_PLL_SET_USING_FPLL_1_012C Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0130_LPLL_V005 (LPLL_V005 + 0x130)
	#define REG_0130_LPLL_V005_REG_TGEN2PLL_VTT_FINAL_0130 Fld(13,0,AC_MSKW10)//[12:0]
	#define REG_0130_LPLL_V005_REG_TGEN2PLL_VTT_UPDATE_0130 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0134_LPLL_V005 (LPLL_V005 + 0x134)
	#define REG_0134_LPLL_V005_REG_TGEN2PLL_VTT_TARGET_0134 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0138_LPLL_V005 (LPLL_V005 + 0x138)
	#define REG_0138_LPLL_V005_REG_TGEN2PLL_VTT_RPT_0138 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_013C_LPLL_V005 (LPLL_V005 + 0x13C)
	#define REG_013C_LPLL_V005_REG_VTT2SET_MODE_013C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0140_LPLL_V005 (LPLL_V005 + 0x140)
	#define REG_0140_LPLL_V005_REG_PLL_SET_AGE_0_0140 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0144_LPLL_V005 (LPLL_V005 + 0x144)
	#define REG_0144_LPLL_V005_REG_PLL_SET_AGE_1_0144 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0148_LPLL_V005 (LPLL_V005 + 0x148)
	#define REG_0148_LPLL_V005_REG_AGE_LOCK_CNT_NUM_0_0148 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_014C_LPLL_V005 (LPLL_V005 + 0x14C)
	#define REG_014C_LPLL_V005_REG_AGE_LOCK_CNT_NUM_1_014C Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_014C_LPLL_V005_REG_AGE_VCNT_FREEZE_EN_014C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_014C_LPLL_V005_REG_AGE_LOCK_CLK_SEL_014C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_014C_LPLL_V005_REG_AGE_LOCK_MODE_EN_014C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0150_LPLL_V005 (LPLL_V005 + 0x150)
	#define REG_0150_LPLL_V005_REG_AGE_OVS_DELAY_SW_VALUE_0_0150 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0154_LPLL_V005 (LPLL_V005 + 0x154)
	#define REG_0154_LPLL_V005_REG_AGE_OVS_DELAY_SW_VALUE_1_0154 Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_0154_LPLL_V005_REG_AGE_OVS_DELAY_SW_EN_0154 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0158_LPLL_V005 (LPLL_V005 + 0x158)
	#define REG_0158_LPLL_V005_REG_AGE_OVS_DELAY_HW_VALUE_0_0158 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_015C_LPLL_V005 (LPLL_V005 + 0x15C)
	#define REG_015C_LPLL_V005_REG_AGE_OVS_DELAY_HW_VALUE_1_015C Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_015C_LPLL_V005_REG_LPLL_V005_INTR_CLR_015C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_015C_LPLL_V005_REG_LPLL_V005_INTR_015C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0160_LPLL_V005 (LPLL_V005 + 0x160)
	#define REG_0160_LPLL_V005_REG_CLKEN_BITMAP_0160 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0164_LPLL_V005 (LPLL_V005 + 0x164)
	#define REG_0164_LPLL_V005_REG_DUMMY_ANA_0164 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0168_LPLL_V005 (LPLL_V005 + 0x168)
	#define REG_0168_LPLL_V005_REG_SYNTH_SSC_SPAN_SUB_DIV_RX_0168 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0168_LPLL_V005_REG_SYNTH_SSC_SPAN_SUB_DIV_0168 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0168_LPLL_V005_REG_SYN864_SW_RST_0168 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_017C_LPLL_V005 (LPLL_V005 + 0x17C)
	#define REG_017C_LPLL_V005_REG_OVS_PRD_MAXMIN_CLR_017C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_017C_LPLL_V005_REG_OVS_PRD_MAXMIN_SEL_017C Fld(2,1,AC_MSKB0)//[2:1]
#define REG_0180_LPLL_V005 (LPLL_V005 + 0x180)
	#define REG_0180_LPLL_V005_REG_LPLL_V0051_VBYONE_DIV_0180 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0180_LPLL_V005_REG_LPLL_V0051_PD_PHDAC_EXT_0180 Fld(4,4,AC_MSKB0)//[7:4]
	#define REG_0180_LPLL_V005_REG_LPLL_V0051_EN_VBYONE_0180 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_LPLL_V005 (LPLL_V005 + 0x184)
	#define REG_0184_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL3_0184 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0184_LPLL_V005_REG_LPLL_V0051_SKEW_CLK3_PHASE_SEL_0184 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0188_LPLL_V005 (LPLL_V005 + 0x188)
	#define REG_0188_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL4_0188 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0188_LPLL_V005_REG_LPLL_V0051_SKEW_CLK4_PHASE_SEL_0188 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_018C_LPLL_V005 (LPLL_V005 + 0x18C)
	#define REG_018C_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL5_018C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_018C_LPLL_V005_REG_LPLL_V0051_SKEW_CLK5_PHASE_SEL_018C Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0190_LPLL_V005 (LPLL_V005 + 0x190)
	#define REG_0190_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL6_0190 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0190_LPLL_V005_REG_LPLL_V0051_SKEW_CLK6_PHASE_SEL_0190 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0194_LPLL_V005 (LPLL_V005 + 0x194)
	#define REG_0194_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL7_0194 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0194_LPLL_V005_REG_LPLL_V0051_SKEW_CLK7_PHASE_SEL_0194 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0198_LPLL_V005 (LPLL_V005 + 0x198)
	#define REG_0198_LPLL_V005_REG_LPLL_V0051_FINE_PHSEL8_0198 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0198_LPLL_V005_REG_LPLL_V0051_SKEW_CLK8_PHASE_SEL_0198 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_019C_LPLL_V005 (LPLL_V005 + 0x19C)
	#define REG_019C_LPLL_V005_REG_LPLL_V0051_COARSE_PHSEL1_019C Fld(4,0,AC_MSKB0)//[3:0]
	#define REG_019C_LPLL_V005_REG_LPLL_V0051_COARSE_PHSEL2_019C Fld(4,4,AC_MSKB0)//[7:4]
	#define REG_019C_LPLL_V005_REG_LPLL_V0051_COARSE_PHSEL3_019C Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_019C_LPLL_V005_REG_LPLL_V0051_COARSE_PHSEL4_019C Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01A0_LPLL_V005 (LPLL_V005 + 0x1A0)
	#define REG_01A0_LPLL_V005_REG_LPLL_V0051_EN_VBY1_HS_01A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01A0_LPLL_V005_REG_EN_CLKREF_FROM_OTHER_CHIP_01A0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01A0_LPLL_V005_REG_EN_2CHIP_SEL_01A0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_01A0_LPLL_V005_REG_EN_VBY1_DIFF_LPLL_V005_01A0 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_01A8_LPLL_V005 (LPLL_V005 + 0x1A8)
	#define REG_01A8_LPLL_V005_REG_PD_VCO_864M_DIV5_01A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01A8_LPLL_V005_REG_MPLL_CP_HBW_01A8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01A8_LPLL_V005_REG_MPLL_VCO_BYPASS_01A8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_01AC_LPLL_V005 (LPLL_V005 + 0x1AC)
	#define REG_01AC_LPLL_V005_REG_EN_MPLL_AMUX_01AC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01AC_LPLL_V005_REG_EN_MPLL_SW_LPLL_V005_CLK_01AC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01AC_LPLL_V005_REG_PD_CLK_CVBS_01AC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_01AC_LPLL_V005_REG_PD_CLK_DVI_01AC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01AC_LPLL_V005_REG_PD_DIGCLK_01AC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01AC_LPLL_V005_REG_PD_DVB_864M_DIV2_01AC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01AC_LPLL_V005_REG_PD_DVB_864M_DIV3_01AC Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_01AC_LPLL_V005_REG_PD_DVB_864M_DIV3P5_01AC Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_01AC_LPLL_V005_REG_PD_DVB_864M_DIV5_01AC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01AC_LPLL_V005_REG_PD_DVB_864M_DIV7_01AC Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01AC_LPLL_V005_REG_PD_DVB_864M_DIV10_01AC Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_01AC_LPLL_V005_REG_PD_VCO_864M_01AC Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_01AC_LPLL_V005_REG_PD_VCO_864M_DIV2_01AC Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01AC_LPLL_V005_REG_PD_VCO_864M_DIV2P5_01AC Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_01AC_LPLL_V005_REG_PD_VCO_864M_DIV3_01AC Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01AC_LPLL_V005_REG_PD_VCO_864M_DIV3P5_01AC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01B0_LPLL_V005 (LPLL_V005 + 0x1B0)
	#define REG_01B0_LPLL_V005_REG_PD_MPLL_01B0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01B0_LPLL_V005_REG_PD_MPLL_CLK_ADC_VCO_DIV2_01B0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01B0_LPLL_V005_REG_MPLL_IN_SELECT_01B0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01B0_LPLL_V005_REG_MPLL_LOCK_01B0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_01B0_LPLL_V005_REG_MPLL_HIGH_FLAG_01B0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_01B0_LPLL_V005_REG_EN_MPLL_TEST_01B0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01B0_LPLL_V005_REG_PD3_MPLL_CLK_ADC_VCO_DIV2_01B0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01B0_LPLL_V005_REG_MPLL_FRUN_EN_01B0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_01B0_LPLL_V005_REG_MPLL_VCO_DIV2_DISABLE_01B0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_01B0_LPLL_V005_REG_PD2_MPLL_CLK_ADC_VCO_DIV2_01B0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01B0_LPLL_V005_REG_MPLL_XTAL_EN_01B0 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_01B0_LPLL_V005_REG_EN_MPLL_RST_01B0 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01B0_LPLL_V005_REG_MPLL_DISC_EN_01B0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01B4_LPLL_V005 (LPLL_V005 + 0x1B4)
	#define REG_01B4_LPLL_V005_REG_GCR_MPLL_INPUT_DIV_01B4 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_01B4_LPLL_V005_REG_MPLL_OUTPUT_DIV_FIRST_01B4 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01B4_LPLL_V005_REG_GCR_MPLL_LOOP_DIV_FIRST_01B4 Fld(2,6,AC_MSKB0)//[7:6]
	#define REG_01B4_LPLL_V005_REG_GCR_MPLL_LOOP_DIV_SECOND_01B4 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01B8_LPLL_V005 (LPLL_V005 + 0x1B8)
	#define REG_01B8_LPLL_V005_REG_MPLL_TEST_01B8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01BC_LPLL_V005 (LPLL_V005 + 0x1BC)
	#define REG_01BC_LPLL_V005_REG_GCR_MPLL_OUTPUT_DIV_01BC Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_01BC_LPLL_V005_REG_MPLL_OV_CP_SW_01BC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01BC_LPLL_V005_REG_EN_MPLL_PRDT_01BC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01BC_LPLL_V005_REG_MPLL_CP_SW_01BC Fld(2,5,AC_MSKB0)//[6:5]
	#define REG_01BC_LPLL_V005_REG_MPLL_DIS_SW_01BC Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_01BC_LPLL_V005_REG_PD_MPLL_DIGCLK_01BC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01BC_LPLL_V005_REG_MPLL_OCC_01BC Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01BC_LPLL_V005_REG_GCR_MPLL_ICTRL_01BC Fld(4,12,AC_MSKB1)//[15:12]
#define REG_01C0_LPLL_V005 (LPLL_V005 + 0x1C0)
	#define REG_01C0_LPLL_V005_REG_FSYNC_RESET_THRESH_01C0 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_01C0_LPLL_V005_REG_FSYNC_RESET_2T_FLAG_01C0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01C0_LPLL_V005_REG_CLR_FSYNC_RESET_2T_FLAG_01C0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01C0_LPLL_V005_REG_EN_PLL_FSYNC_RESET_01C0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_01C0_LPLL_V005_REG_PRD_LOCK_THRESH_SEL_01C0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01C0_LPLL_V005_REG_VTT_PLL_EN_01C0 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01C0_LPLL_V005_REG_EN_CLK_DIV_01C0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01C4_LPLL_V005 (LPLL_V005 + 0x1C4)
	#define REG_01C4_LPLL_V005_REG_LPLL_V0051_TEST_V2_01C4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_LPLL_V005 (LPLL_V005 + 0x1C8)
	#define REG_01C8_LPLL_V005_REG_IDCLK_DIV_PRD_0_01C8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_LPLL_V005 (LPLL_V005 + 0x1CC)
	#define REG_01CC_LPLL_V005_REG_IDCLK_DIV_PRD_1_01CC Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01D0_LPLL_V005 (LPLL_V005 + 0x1D0)
	#define REG_01D0_LPLL_V005_REG_ODCLK_DIV_PRD_0_01D0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_LPLL_V005 (LPLL_V005 + 0x1D4)
	#define REG_01D4_LPLL_V005_REG_ODCLK_DIV_PRD_1_01D4 Fld(9,0,AC_MSKW10)//[8:0]
#define REG_01D8_LPLL_V005 (LPLL_V005 + 0x1D8)
	#define REG_01D8_LPLL_V005_REG_OVS_SPREAD_REM_01D8 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01DC_LPLL_V005 (LPLL_V005 + 0x1DC)
	#define REG_01DC_LPLL_V005_REG_SPREAD_REM_01DC Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01E0_LPLL_V005 (LPLL_V005 + 0x1E0)
	#define REG_01E0_LPLL_V005_REG_LOC_VTT_FIX_CAL_EN_01E0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_01E0_LPLL_V005_REG_IVS_THRESH_EN_01E0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01E0_LPLL_V005_REG_V_OFFSET_EN_01E0 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_01E0_LPLL_V005_REG_OVS_PH_HALF_ORG_DIS_01E0 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01E4_LPLL_V005 (LPLL_V005 + 0x1E4)
	#define REG_01E4_LPLL_V005_REG_OVS_SPREAD_NUM_01E4 Fld(13,0,AC_MSKW10)//[12:0]
	#define REG_01E4_LPLL_V005_REG_OVS_SPREADER_EN_01E4 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E8_LPLL_V005 (LPLL_V005 + 0x1E8)
	#define REG_01E8_LPLL_V005_REG_SPREAD_NUM_01E8 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01EC_LPLL_V005 (LPLL_V005 + 0x1EC)
	#define REG_01EC_LPLL_V005_REG_SELF_DET_TH_01EC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F0_LPLL_V005 (LPLL_V005 + 0x1F0)
	#define REG_01F0_LPLL_V005_REG_IVS_PRD_RPT_0_01F0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_LPLL_V005 (LPLL_V005 + 0x1F4)
	#define REG_01F4_LPLL_V005_REG_IVS_PRD_RPT_1_01F4 Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_01F4_LPLL_V005_REG_IVS_PRD_RPT_RESET_AUTO_01F4 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01F4_LPLL_V005_REG_VS_PRD_RPT_SEL_01F4 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_01F4_LPLL_V005_REG_IVS_PRD_IDCLK_RPT_EN_01F4 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01F4_LPLL_V005_REG_FPLL_GAT_EN_01F4 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01F8_LPLL_V005 (LPLL_V005 + 0x1F8)
	#define REG_01F8_LPLL_V005_REG_F_RPT_CNT_01F8 Fld(12,0,AC_MSKW10)//[11:0]
	#define REG_01F8_LPLL_V005_REG_PHASE_LOCK_THRESH_SEL_01F8 Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_01F8_LPLL_V005_REG_F_RPT_EN_01F8 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01F8_LPLL_V005_REG_SPREADER_EN_01F8 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01FC_LPLL_V005 (LPLL_V005 + 0x1FC)
	#define REG_01FC_LPLL_V005_REG_DB_EN_01FC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01FC_LPLL_V005_REG_SW_TRIG_DB_LOAD_01FC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01FC_LPLL_V005_REG_SW_TRIG_CLR_FIX_VTT_01FC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_01FC_LPLL_V005_REG_FIX_POSI_LD_01FC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01FC_LPLL_V005_REG_TGEN_SRC_SEL_01FC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01FC_LPLL_V005_REG_EXT_SYNTH_CLK_SRC_EN_1_01FC Fld(1,9,AC_MSKB1)//[9:9]
