/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020-2024 MediaTek Inc.
 */

#define GOP0_UDMA_BKA4DF 0x149BE00

//Page GOP0_UDMA_BKA4DF
#define REG_0040_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x040)
    #define REG_0040_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MIN_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0044_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x044)
    #define REG_0044_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MIN_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0048_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x048)
    #define REG_0048_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MAX_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_004C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x04C)
    #define REG_004C_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MAX_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x050)
    #define REG_0050_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_EN Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_0050_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_FLAG_CLR Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_0050_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MIN_HIT Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_0050_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MAX_HIT Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_0050_GOP0_UDMA_BKA4DF_REG_PRIORITY_SOF_MASK_LV_SEL Fld(3, 12, AC_MSKB1)//[14:12]
    #define REG_0050_GOP0_UDMA_BKA4DF_REG_PRIORITY_EOF_MASK_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0054_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x054)
    #define REG_0054_GOP0_UDMA_BKA4DF_REG_REQ_PREULTRA_RISE_LV Fld(7, 0, AC_MSKB0)//[6:0]
    #define REG_0054_GOP0_UDMA_BKA4DF_REG_REQ_PREULTRA_FORCE_HIGH Fld(1, 7, AC_MSKB0)//[7:7]
    #define REG_0054_GOP0_UDMA_BKA4DF_REG_REQ_PREULTRA_FALL_LV Fld(7, 8, AC_MSKB1)//[14:8]
    #define REG_0054_GOP0_UDMA_BKA4DF_REG_REQ_PREULTRA_MASK Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0058_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x058)
    #define REG_0058_GOP0_UDMA_BKA4DF_REG_REQ_ULTRA_RISE_LV Fld(7, 0, AC_MSKB0)//[6:0]
    #define REG_0058_GOP0_UDMA_BKA4DF_REG_REQ_ULTRA_FORCE_HIGH Fld(1, 7, AC_MSKB0)//[7:7]
    #define REG_0058_GOP0_UDMA_BKA4DF_REG_REQ_ULTRA_FALL_LV Fld(7, 8, AC_MSKB1)//[14:8]
    #define REG_0058_GOP0_UDMA_BKA4DF_REG_REQ_ULTRA_MASK Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_005C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x05C)
    #define REG_005C_GOP0_UDMA_BKA4DF_REG_REQ_URGENT_RISE_LV Fld(7, 0, AC_MSKB0)//[6:0]
    #define REG_005C_GOP0_UDMA_BKA4DF_REG_REQ_URGENT_FORCE_HIGH Fld(1, 7, AC_MSKB0)//[7:7]
    #define REG_005C_GOP0_UDMA_BKA4DF_REG_REQ_URGENT_FALL_LV Fld(7, 8, AC_MSKB1)//[14:8]
    #define REG_005C_GOP0_UDMA_BKA4DF_REG_REQ_URGENT_MASK Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_006C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x06C)
    #define REG_006C_GOP0_UDMA_BKA4DF_REG_REQ_STASH_LEAD_CNT Fld(4, 0, AC_MSKB0)//[3:0]
    #define REG_006C_GOP0_UDMA_BKA4DF_REG_REQ_CMD_RESERVE_CNT Fld(4, 4, AC_MSKB0)//[7:4]
    #define REG_006C_GOP0_UDMA_BKA4DF_REG_REQ_STASH_EN Fld(1, 8, AC_MSKB1)//[8:8]
    #define REG_006C_GOP0_UDMA_BKA4DF_REG_REQ_CMD_RESERVE_EN Fld(1, 9, AC_MSKB1)//[9:9]
    #define REG_006C_GOP0_UDMA_BKA4DF_REG_REQ_CMD_RESERVE_SEL Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0074_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x074)
    #define REG_0074_GOP0_UDMA_BKA4DF_REG_CFG_RID_BIT Fld(2, 0, AC_MSKB0)//[1:0]
    #define REG_0074_GOP0_UDMA_BKA4DF_REG_RID_INIT_INTL_EN Fld(1, 4, AC_MSKB0)//[4:4]
    #define REG_0074_GOP0_UDMA_BKA4DF_REG_REQ_PORT_DISPATCH_MODE Fld(1, 8, AC_MSKB1)//[8:8]
    #define REG_0074_GOP0_UDMA_BKA4DF_REG_FRAME_CMD_MODE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0078_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x078)
    #define REG_0078_GOP0_UDMA_BKA4DF_REG_CFG_BUF_QD Fld(14, 0, AC_MSKW10)//[13:0]
#define REG_007C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x07C)
    #define REG_007C_GOP0_UDMA_BKA4DF_REG_RB_BUF_MAX_QD Fld(14, 0, AC_MSKW10)//[13:0]
#define REG_0080_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x080)
    #define REG_0080_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_SEL Fld(1, 8, AC_MSKB1)//[8:8]
    #define REG_0080_GOP0_UDMA_BKA4DF_REG_ADR_PRIORITY_SEL Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0084_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x084)
    #define REG_0084_GOP0_UDMA_BKA4DF_REG_CROP_BYPASS Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0088_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x088)
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_ADR_ARB_LBL_MODE Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_DAT_ARB_LBL_MODE Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_ADR_ARB_RR_MODE Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_DAT_ARB_RR_MODE Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_ADR_FSM_MODE_EN Fld(1, 13, AC_MSKB1)//[13:13]
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_FSM_MODE_EN Fld(1, 14, AC_MSKB1)//[14:14]
    #define REG_0088_GOP0_UDMA_BKA4DF_REG_SUM_CNT_MASK_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_008C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x08C)
    #define REG_008C_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_0 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_008C_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_1 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0090_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x090)
    #define REG_0090_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_2 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_0090_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_3 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0094_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x094)
    #define REG_0094_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_4 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_0094_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_5 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0098_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x098)
    #define REG_0098_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_6 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_0098_GOP0_UDMA_BKA4DF_REG_PLN_PRIORITY_7 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00B0_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x0B0)
    #define REG_00B0_GOP0_UDMA_BKA4DF_REG_PATGEN_HSIZE Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B4_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x0B4)
    #define REG_00B4_GOP0_UDMA_BKA4DF_REG_PATGEN_VSIZE Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B8_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x0B8)
    #define REG_00B8_GOP0_UDMA_BKA4DF_REG_PATGEN_EN Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_00B8_GOP0_UDMA_BKA4DF_REG_PATGEN_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00BC_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x0BC)
    #define REG_00BC_GOP0_UDMA_BKA4DF_REG_PATGEN_STEP Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_00BC_GOP0_UDMA_BKA4DF_REG_PATGEN_TIMING_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00C0_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x0C0)
    #define REG_00C0_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MIN_MSB Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00C4_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x0C4)
    #define REG_00C4_GOP0_UDMA_BKA4DF_REG_RANGE_LIMIT_MAX_MSB Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0100_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x100)
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_SW_RST Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_SW_RST_F Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_SW_RST_M Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_USR_SW_RST_MASK Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_UDMA_HW_CLK_GATING_OFF Fld(1, 4, AC_MSKB0)//[4:4]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_UDMA_REQ_CLK_PROT_OFF Fld(1, 5, AC_MSKB0)//[5:5]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_SW_RST_PRTCL_PROT Fld(1, 6, AC_MSKB0)//[6:6]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_PRTCL_PROT_OFF Fld(1, 7, AC_MSKB0)//[7:7]
    #define REG_0100_GOP0_UDMA_BKA4DF_REG_PRTCL_PROT_MASK_MODE Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0120_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x120)
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_USR2CORE_CMD_RDY Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_CORE2USR_CMD_ACK Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_USR2CORE_ACK Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_CORE2USR_RDY Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_CORE2USR_READ_DONE Fld(1, 4, AC_MSKB0)//[4:4]
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_AUDL_MODE_MULTI_TRANS Fld(1, 5, AC_MSKB0)//[5:5]
    #define REG_0120_GOP0_UDMA_BKA4DF_REG_RB_SEQ_ERR Fld(1, 6, AC_MSKB0)//[6:6]
#define REG_0124_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x124)
    #define REG_0124_GOP0_UDMA_BKA4DF_REG_RB_PLANE_DISABLE Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_012C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x12C)
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_RID_CUR_ST Fld(2, 0, AC_MSKB0)//[1:0]
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_RID_PROT_OCCUR Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_RID_MULTI_PROT_OCCUR Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_CUR_ST Fld(2, 8, AC_MSKB1)//[9:8]
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_PROT_OCCUR Fld(1, 10, AC_MSKB1)//[10:10]
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_MULTI_PROT_OCCUR Fld(1, 11, AC_MSKB1)//[11:11]
    #define REG_012C_GOP0_UDMA_BKA4DF_REG_RB_PP_MAX_PROT_OCCUR Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0130_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x130)
    #define REG_0130_GOP0_UDMA_BKA4DF_REG_RB_PP_PROT_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0134_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x134)
    #define REG_0134_GOP0_UDMA_BKA4DF_REG_RB_PP_OSTD_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0138_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x138)
    #define REG_0138_GOP0_UDMA_BKA4DF_REG_RB_PP_RID_PROT_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_013C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x13C)
    #define REG_013C_GOP0_UDMA_BKA4DF_REG_RB_PP_RID_OSTD_CNT Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0180_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x180)
    #define REG_0180_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0184_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x184)
    #define REG_0184_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0188_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x188)
    #define REG_0188_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_018C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x18C)
    #define REG_018C_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_3 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0190_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x190)
    #define REG_0190_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0194_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x194)
    #define REG_0194_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_5 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0198_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x198)
    #define REG_0198_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_6 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_019C_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x19C)
    #define REG_019C_GOP0_UDMA_BKA4DF_REG_RB_ADDR_V_DEAL_NUM_7 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A0_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1A0)
    #define REG_01A0_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A4_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1A4)
    #define REG_01A4_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01A8_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1A8)
    #define REG_01A8_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01AC_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1AC)
    #define REG_01AC_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_3 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01B0_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1B0)
    #define REG_01B0_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_4 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01B4_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1B4)
    #define REG_01B4_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_5 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01B8_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1B8)
    #define REG_01B8_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_6 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01BC_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1BC)
    #define REG_01BC_GOP0_UDMA_BKA4DF_REG_RB_DAT_V_DEAL_NUM_7 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01C0_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1C0)
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_RB_EN Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_RB_LATCH_PULSE Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_REQ_FORCE_OFF Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_REQ_FAKE_EN Fld(1, 3, AC_MSKB0)//[3:3]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_RB_BUF_SMI_SEL Fld(2, 4, AC_MSKB0)//[5:4]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_RB_MODE Fld(2, 6, AC_MSKB0)//[7:6]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_RB_LOG_ID_SEL Fld(3, 8, AC_MSKB1)//[10:8]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_RB_ERR_CLR Fld(1, 11, AC_MSKB1)//[11:11]
    #define REG_01C0_GOP0_UDMA_BKA4DF_REG_REQ_FAKE_RD_PAT Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_01C4_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1C4)
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_REQ2MI_RDY Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_MI2REQ_RDY Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_MI2REQ_RD_LAT Fld(1, 2, AC_MSKB0)//[2:2]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_REQ2MI_PREULTRA Fld(1, 4, AC_MSKB0)//[4:4]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_REQ2MI_ULTRA Fld(1, 5, AC_MSKB0)//[5:5]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_REQ2MI_URGENT Fld(1, 6, AC_MSKB0)//[6:6]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_REQ2MI_ID Fld(2, 8, AC_MSKB1)//[9:8]
    #define REG_01C4_GOP0_UDMA_BKA4DF_REG_RB_MI2REQ_RID Fld(2, 12, AC_MSKB1)//[13:12]
#define REG_01C8_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1C8)
    #define REG_01C8_GOP0_UDMA_BKA4DF_REG_RB_RANGE_LIMIT_MAX_HIT Fld(1, 0, AC_MSKB0)//[0:0]
    #define REG_01C8_GOP0_UDMA_BKA4DF_REG_RB_RANGE_LIMIT_MIN_HIT Fld(1, 1, AC_MSKB0)//[1:1]
    #define REG_01C8_GOP0_UDMA_BKA4DF_REG_RB_NOT_DONE_AT_VSYNC Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_01CC_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1CC)
    #define REG_01CC_GOP0_UDMA_BKA4DF_REG_RB_REQ2MI_LINE_NUM Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D4_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1D4)
    #define REG_01D4_GOP0_UDMA_BKA4DF_REG_RB_BUF_LV Fld(14, 0, AC_MSKW10)//[13:0]
    #define REG_01D4_GOP0_UDMA_BKA4DF_REG_RB_BUF_FULL Fld(1, 14, AC_MSKB1)//[14:14]
    #define REG_01D4_GOP0_UDMA_BKA4DF_REG_RB_BUF_EMPTY Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01D8_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1D8)
    #define REG_01D8_GOP0_UDMA_BKA4DF_REG_RB_UDMA_IRQ Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01DC_GOP0_UDMA_BKA4DF (GOP0_UDMA_BKA4DF + 0x1DC)
    #define REG_01DC_GOP0_UDMA_BKA4DF_REG_DUMMY_0 Fld(8, 0, AC_FULLB0)//[7:0]
    #define REG_01DC_GOP0_UDMA_BKA4DF_REG_DUMMY_1 Fld(8, 8, AC_FULLB1)//[15:8]
