/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define LPLL_V007 0x486000

//Page LPLL_V007
#define REG_0010_LPLL_V007 (LPLL_V007 + 0x010)
	#define REG_0010_LPLL_V007_REG_PRD_STABLE_THRESEL Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_0014_LPLL_V007 (LPLL_V007 + 0x014)
	#define REG_0014_LPLL_V007_REG_PRD_STABLE_THRESH Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0014_LPLL_V007_REG_PRD_LOCK_THRESH Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0014_LPLL_V007_REG_PHASE_LOCK_THRESH Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0018_LPLL_V007 (LPLL_V007 + 0x018)
	#define REG_0018_LPLL_V007_REG_LIMIT_D5D6D7_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_001C_LPLL_V007 (LPLL_V007 + 0x01C)
	#define REG_001C_LPLL_V007_REG_LIMIT_D5D6D7_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0020_LPLL_V007 (LPLL_V007 + 0x020)
	#define REG_0020_LPLL_V007_REG_LIMIT_D5D6D7_RK_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0024_LPLL_V007 (LPLL_V007 + 0x024)
	#define REG_0024_LPLL_V007_REG_LIMIT_D5D6D7_RK_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0028_LPLL_V007 (LPLL_V007 + 0x028)
	#define REG_0028_LPLL_V007_REG_LIMIT_LPLL_V007_OFFSET Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_002C_LPLL_V007 (LPLL_V007 + 0x02C)
	#define REG_002C_LPLL_V007_REG_I_GAIN_PRD Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_002C_LPLL_V007_REG_P_GAIN_PRD Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_002C_LPLL_V007_REG_I_GAIN_PHASE Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_002C_LPLL_V007_REG_P_GAIN_PHASE Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0030_LPLL_V007 (LPLL_V007 + 0x030)
	#define REG_0030_LPLL_V007_REG_FPLL_MODE Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0030_LPLL_V007_REG_FRAME_LPLL_V007_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0030_LPLL_V007_REG_I_GAIN_PRD_ZERO Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0030_LPLL_V007_REG_P_GAIN_PRD_ZERO Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0030_LPLL_V007_REG_I_GAIN_PHASE_ZERO Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0030_LPLL_V007_REG_P_GAIN_PHASE_ZERO Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0030_LPLL_V007_REG_IVS_FRAME_DIV Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0030_LPLL_V007_REG_OVS_FRAME_DIV Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0034_LPLL_V007 (LPLL_V007 + 0x034)
	#define REG_0034_LPLL_V007_REG_FORCE_PRD_STABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0034_LPLL_V007_REG_FORCE_PRD_LOCK_DONE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0034_LPLL_V007_REG_FORCE_PHASE_REDUCE_DONE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0034_LPLL_V007_REG_FORCE_PHASE_CLOSE_DONE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0034_LPLL_V007_REG_EN_2_LIMIT Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0034_LPLL_V007_REG_NO_SIGNAL_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0034_LPLL_V007_REG_NON_STABLE_EN Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0038_LPLL_V007 (LPLL_V007 + 0x038)
	#define REG_0038_LPLL_V007_REG_EXT_IVS_FRAME_DIV Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0038_LPLL_V007_REG_EXT_OVS_FRAME_DIV Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0038_LPLL_V007_REG_PLL_SET_0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_003C_LPLL_V007 (LPLL_V007 + 0x03C)
	#define REG_003C_LPLL_V007_REG_PLL_SET_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0040_LPLL_V007 (LPLL_V007 + 0x040)
	#define REG_0040_LPLL_V007_REG_PLL_SET_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0044_LPLL_V007 (LPLL_V007 + 0x044)
	#define REG_0044_LPLL_V007_REG_PHASE_DIF Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0048_LPLL_V007 (LPLL_V007 + 0x048)
	#define REG_0048_LPLL_V007_REG_PHASE_UP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_004C_LPLL_V007 (LPLL_V007 + 0x04C)
	#define REG_004C_LPLL_V007_REG_PRD_DIF Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_LPLL_V007 (LPLL_V007 + 0x050)
	#define REG_0050_LPLL_V007_REG_PRD_UP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0058_LPLL_V007 (LPLL_V007 + 0x058)
	#define REG_0058_LPLL_V007_REG_LPLL_V007_TESTD Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_0064_LPLL_V007 (LPLL_V007 + 0x064)
	#define REG_0064_LPLL_V007_REG_IDCLK_DIV_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0068_LPLL_V007 (LPLL_V007 + 0x068)
	#define REG_0068_LPLL_V007_REG_IDCLK_DIV_1 Fld(9, 0, AC_MSKW10)//[8:0]
#define REG_006C_LPLL_V007 (LPLL_V007 + 0x06C)
	#define REG_006C_LPLL_V007_REG_ODCLK_DIV_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0070_LPLL_V007 (LPLL_V007 + 0x070)
	#define REG_0070_LPLL_V007_REG_ODCLK_DIV_1 Fld(9, 0, AC_MSKW10)//[8:0]
#define REG_0074_LPLL_V007 (LPLL_V007 + 0x074)
	#define REG_0074_LPLL_V007_REG_DEC_V_LIMIT Fld(13, 0, AC_MSKW10)//[12:0]
	#define REG_0074_LPLL_V007_REG_FIX_DEC_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0078_LPLL_V007 (LPLL_V007 + 0x078)
	#define REG_0078_LPLL_V007_REG_INC_V_LIMIT Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_007C_LPLL_V007 (LPLL_V007 + 0x07C)
	#define REG_007C_LPLL_V007_REG_PHASE_CLOSE_THRESH Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_007C_LPLL_V007_REG_REDUCE_DONE_THRESH Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0080_LPLL_V007 (LPLL_V007 + 0x080)
	#define REG_0080_LPLL_V007_REG_HIS_CNT_LOW_THRESH Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0080_LPLL_V007_REG_HIS_CNT_HIGH_THRESH Fld(3, 4, AC_MSKB0)//[6:4]
#define REG_0084_LPLL_V007 (LPLL_V007 + 0x084)
	#define REG_0084_LPLL_V007_REG_IVS_PRD_VALUE_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0088_LPLL_V007 (LPLL_V007 + 0x088)
	#define REG_0088_LPLL_V007_REG_IVS_PRD_VALUE_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_008C_LPLL_V007 (LPLL_V007 + 0x08C)
	#define REG_008C_LPLL_V007_REG_OVS_PRD_VALUE_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0090_LPLL_V007 (LPLL_V007 + 0x090)
	#define REG_0090_LPLL_V007_REG_OVS_PRD_VALUE_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0098_LPLL_V007 (LPLL_V007 + 0x098)
	#define REG_0098_LPLL_V007_REG_FIX_V_TOTAL Fld(13, 0, AC_MSKW10)//[12:0]
	#define REG_0098_LPLL_V007_REG_FIX_V_DEC Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_009C_LPLL_V007 (LPLL_V007 + 0x09C)
	#define REG_009C_LPLL_V007_REG_FIX_H_TOTAL Fld(14, 0, AC_MSKW10)//[13:0]
	#define REG_009C_LPLL_V007_REG_PLL_SET_USING_0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00A0_LPLL_V007 (LPLL_V007 + 0x0A0)
	#define REG_00A0_LPLL_V007_REG_PLL_SET_USING_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A4_LPLL_V007 (LPLL_V007 + 0x0A4)
	#define REG_00A4_LPLL_V007_REG_PLL_SET_USING_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A8_LPLL_V007 (LPLL_V007 + 0x0A8)
	#define REG_00A8_LPLL_V007_REG_CS_STATE Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_00A8_LPLL_V007_REG_OVS_PRD_STABLE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00A8_LPLL_V007_REG_IVS_PRD_STABLE Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_00A8_LPLL_V007_REG_PRD_LOCK_DONE Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_00A8_LPLL_V007_REG_PHASE_REDUCE_DONE Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_00A8_LPLL_V007_REG_PHASE_LOCK_DONE Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_00EC_LPLL_V007 (LPLL_V007 + 0x0EC)
	#define REG_00EC_LPLL_V007_REG_FORCE_DISABLE_FPLL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00EC_LPLL_V007_REG_AUTO_DISABLE_FPLL_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00EC_LPLL_V007_REG_LPLL_V007_DUMMY0 Fld(14, 2, AC_MSKW10)//[15:2]
#define REG_00F0_LPLL_V007 (LPLL_V007 + 0x0F0)
	#define REG_00F0_LPLL_V007_REG_LPLL_V007_DUMMY1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00F4_LPLL_V007 (LPLL_V007 + 0x0F4)
	#define REG_00F4_LPLL_V007_REG_IVS_OVS_PHASE_DIF_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00F8_LPLL_V007 (LPLL_V007 + 0x0F8)
	#define REG_00F8_LPLL_V007_REG_IVS_OVS_PHASE_DIF_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00FC_LPLL_V007 (LPLL_V007 + 0x0FC)
	#define REG_00FC_LPLL_V007_REG_IVS_OVS_PHASE_UP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0124_LPLL_V007 (LPLL_V007 + 0x124)
	#define REG_0124_LPLL_V007_REG_GAIN_MUX Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0124_LPLL_V007_REG_SDM_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0124_LPLL_V007_REG_CLKDIV_REPLACE_FDIV_EN Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0124_LPLL_V007_REG_PLL_SET_USING_FPLL_0 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0128_LPLL_V007 (LPLL_V007 + 0x128)
	#define REG_0128_LPLL_V007_REG_PLL_SET_USING_FPLL_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_012C_LPLL_V007 (LPLL_V007 + 0x12C)
	#define REG_012C_LPLL_V007_REG_PLL_SET_USING_FPLL_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0130_LPLL_V007 (LPLL_V007 + 0x130)
	#define REG_0130_LPLL_V007_REG_TGEN2PLL_VTT_FINAL Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0134_LPLL_V007 (LPLL_V007 + 0x134)
	#define REG_0134_LPLL_V007_REG_TGEN2PLL_VTT_TARGET Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0138_LPLL_V007 (LPLL_V007 + 0x138)
	#define REG_0138_LPLL_V007_REG_TGEN2PLL_VTT_RPT Fld(15, 0, AC_MSKW10)//[14:0]
	#define REG_0138_LPLL_V007_REG_TGEN2PLL_VTT_UPDATE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_013C_LPLL_V007 (LPLL_V007 + 0x13C)
	#define REG_013C_LPLL_V007_REG_VTT2SET_MODE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0140_LPLL_V007 (LPLL_V007 + 0x140)
	#define REG_0140_LPLL_V007_REG_PLL_SET_AGE_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0144_LPLL_V007 (LPLL_V007 + 0x144)
	#define REG_0144_LPLL_V007_REG_PLL_SET_AGE_1 Fld(12, 0, AC_MSKW10)//[11:0]
#define REG_0148_LPLL_V007 (LPLL_V007 + 0x148)
	#define REG_0148_LPLL_V007_REG_AGE_LOCK_CNT_NUM_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_014C_LPLL_V007 (LPLL_V007 + 0x14C)
	#define REG_014C_LPLL_V007_REG_AGE_LOCK_CNT_NUM_1 Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_014C_LPLL_V007_REG_AGE_VCNT_FREEZE_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_014C_LPLL_V007_REG_AGE_LOCK_CLK_SEL Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_014C_LPLL_V007_REG_AGE_LOCK_MODE_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0150_LPLL_V007 (LPLL_V007 + 0x150)
	#define REG_0150_LPLL_V007_REG_AGE_OVS_DELAY_SW_VALUE_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0154_LPLL_V007 (LPLL_V007 + 0x154)
	#define REG_0154_LPLL_V007_REG_AGE_OVS_DELAY_SW_VALUE_1 Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_0154_LPLL_V007_REG_AGE_OVS_DELAY_SW_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0158_LPLL_V007 (LPLL_V007 + 0x158)
	#define REG_0158_LPLL_V007_REG_AGE_OVS_DELAY_HW_VALUE_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_015C_LPLL_V007 (LPLL_V007 + 0x15C)
	#define REG_015C_LPLL_V007_REG_AGE_OVS_DELAY_HW_VALUE_1 Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_015C_LPLL_V007_REG_LPLL_V007_INTR_CLR Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_015C_LPLL_V007_REG_LPLL_V007_INTR Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0160_LPLL_V007 (LPLL_V007 + 0x160)
	#define REG_0160_LPLL_V007_REG_CLKEN_BITMAP Fld(5, 0, AC_MSKB0)//[4:0]
#define REG_0174_LPLL_V007 (LPLL_V007 + 0x174)
	#define REG_0174_LPLL_V007_REG_ODPLL_LPLL_V007_MUX_SEL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0174_LPLL_V007_REG_FPLL_ODPLL_MODE_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_017C_LPLL_V007 (LPLL_V007 + 0x17C)
	#define REG_017C_LPLL_V007_REG_OVS_PRD_MAXMIN_CLR Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_017C_LPLL_V007_REG_OVS_PRD_MAXMIN_SEL Fld(2, 1, AC_MSKB0)//[2:1]
#define REG_01C0_LPLL_V007 (LPLL_V007 + 0x1C0)
	#define REG_01C0_LPLL_V007_REG_FSYNC_RESET_THRESH Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_01C0_LPLL_V007_REG_FSYNC_RESET_2T_FLAG Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_01C0_LPLL_V007_REG_CLR_FSYNC_RESET_2T_FLAG Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_01C0_LPLL_V007_REG_EN_PLL_FSYNC_RESET Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_01C0_LPLL_V007_REG_PRD_LOCK_THRESH_SEL Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_01C0_LPLL_V007_REG_VTT_PLL_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_01C0_LPLL_V007_REG_EN_CLK_DIV Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01C8_LPLL_V007 (LPLL_V007 + 0x1C8)
	#define REG_01C8_LPLL_V007_REG_IDCLK_DIV_PRD_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01CC_LPLL_V007 (LPLL_V007 + 0x1CC)
	#define REG_01CC_LPLL_V007_REG_IDCLK_DIV_PRD_1 Fld(9, 0, AC_MSKW10)//[8:0]
#define REG_01D0_LPLL_V007 (LPLL_V007 + 0x1D0)
	#define REG_01D0_LPLL_V007_REG_ODCLK_DIV_PRD_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01D4_LPLL_V007 (LPLL_V007 + 0x1D4)
	#define REG_01D4_LPLL_V007_REG_ODCLK_DIV_PRD_1 Fld(9, 0, AC_MSKW10)//[8:0]
#define REG_01D8_LPLL_V007 (LPLL_V007 + 0x1D8)
	#define REG_01D8_LPLL_V007_REG_OVS_SPREAD_REM Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_01DC_LPLL_V007 (LPLL_V007 + 0x1DC)
	#define REG_01DC_LPLL_V007_REG_SPREAD_REM Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_01E0_LPLL_V007 (LPLL_V007 + 0x1E0)
	#define REG_01E0_LPLL_V007_REG_LOC_VTT_FIX_CAL_EN Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_01E0_LPLL_V007_REG_IVS_THRESH_EN Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_01E0_LPLL_V007_REG_V_OFFSET_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_01E0_LPLL_V007_REG_OVS_PH_HALF_ORG_DIS Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_01E4_LPLL_V007 (LPLL_V007 + 0x1E4)
	#define REG_01E4_LPLL_V007_REG_OVS_SPREAD_NUM Fld(13, 0, AC_MSKW10)//[12:0]
	#define REG_01E4_LPLL_V007_REG_OVS_SPREADER_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01E8_LPLL_V007 (LPLL_V007 + 0x1E8)
	#define REG_01E8_LPLL_V007_REG_SPREAD_NUM Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_01EC_LPLL_V007 (LPLL_V007 + 0x1EC)
	#define REG_01EC_LPLL_V007_REG_SELF_DET_TH Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F0_LPLL_V007 (LPLL_V007 + 0x1F0)
	#define REG_01F0_LPLL_V007_REG_IVS_PRD_RPT_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01F4_LPLL_V007 (LPLL_V007 + 0x1F4)
	#define REG_01F4_LPLL_V007_REG_IVS_PRD_RPT_1 Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_01F4_LPLL_V007_REG_IVS_PRD_RPT_RESET_AUTO Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_01F4_LPLL_V007_REG_VS_PRD_RPT_SEL Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_01F4_LPLL_V007_REG_IVS_PRD_IDCLK_RPT_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_01F4_LPLL_V007_REG_FPLL_GAT_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01F8_LPLL_V007 (LPLL_V007 + 0x1F8)
	#define REG_01F8_LPLL_V007_REG_F_RPT_CNT Fld(12, 0, AC_MSKW10)//[11:0]
	#define REG_01F8_LPLL_V007_REG_PHASE_LOCK_THRESH_SEL Fld(2, 12, AC_MSKB1)//[13:12]
	#define REG_01F8_LPLL_V007_REG_F_RPT_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_01F8_LPLL_V007_REG_SPREADER_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_01FC_LPLL_V007 (LPLL_V007 + 0x1FC)
	#define REG_01FC_LPLL_V007_REG_DB_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_01FC_LPLL_V007_REG_SW_TRIG_DB_LOAD Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_01FC_LPLL_V007_REG_SW_TRIG_CLR_FIX_VTT Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_01FC_LPLL_V007_REG_FIX_POSI_LD Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_01FC_LPLL_V007_REG_TGEN_SRC_SEL Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_01FC_LPLL_V007_REG_EXT_SYNTH_CLK_SRC_EN_1 Fld(1, 9, AC_MSKB1)//[9:9]
