/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG 0x702000

//Page EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG
#define DP_TX_TOP_PWR_STATE (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x0)
	#define DP_TX_TOP_PWR_STATE_RG_DP_PWR_STATE Fld(2, 0, AC_MSKB0)//[1:0]
	#define DP_TX_TOP_PWR_STATE_RG_DP_SCRAMB_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define DP_TX_TOP_PWR_STATE_RG_DP_DISP_RST Fld(1, 3, AC_MSKB0)//[3:3]
#define DP_TX_TOP_SWING_EMP (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x4)
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX0_VOLT_SWING Fld(2, 0, AC_MSKB0)//[1:0]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX0_PRE_EMPH Fld(2, 2, AC_MSKB0)//[3:2]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX0_DATAK Fld(4, 4, AC_MSKB0)//[7:4]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX1_VOLT_SWING Fld(2, 8, AC_MSKB1)//[9:8]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX1_PRE_EMPH Fld(2, 10, AC_MSKB1)//[11:10]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX1_DATAK Fld(4, 12, AC_MSKB1)//[15:12]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX2_VOLT_SWING Fld(2, 16, AC_MSKB2)//[17:16]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX2_PRE_EMPH Fld(2, 18, AC_MSKB2)//[19:18]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX2_DATAK Fld(4, 20, AC_MSKB2)//[23:20]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX3_VOLT_SWING Fld(2, 24, AC_MSKB3)//[25:24]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX3_PRE_EMPH Fld(2, 26, AC_MSKB3)//[27:26]
	#define DP_TX_TOP_SWING_EMP_RG_DP_TX3_DATAK Fld(4, 28, AC_MSKB3)//[31:28]
#define DP_TX_TOP_CLOCK_EN (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x8)
	#define DP_TX_TOP_CLOCK_EN_REG_DPTX_CKEN_P0 Fld(16, 0, AC_FULLW10)//[15:0]
#define DP_TX_TOP_SW2_RESET (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xc)
	#define DP_TX_TOP_SW2_RESET_RG_SW2_RST_B_P0 Fld(16, 0, AC_FULLW10)//[15:0]
#define DP_TX_TOP_APB_WSTRB (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x10)
	#define DP_TX_TOP_APB_WSTRB_RG_APB_WSTRB Fld(4, 0, AC_MSKB0)//[3:0]
	#define DP_TX_TOP_APB_WSTRB_RG_APB_WSTRB_EN Fld(1, 4, AC_MSKB0)//[4:4]
#define DP_TX_TOP_RESERVED (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x14)
	#define DP_TX_TOP_RESERVED_RG_RESERVED Fld(32, 0, AC_FULLDW)//[31:0]
#define DP_TX_TOP_RESET_AND_PROBE (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x18)
	#define DP_TX_TOP_RESET_AND_PROBE_RG_SW_RST_B_P0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define DP_TX_TOP_RESET_AND_PROBE_RG_PROBE_LOW_SEL Fld(4, 16, AC_MSKB2)//[19:16]
	#define DP_TX_TOP_RESET_AND_PROBE_RG_PROBE_HIGH_SEL Fld(4, 20, AC_MSKB2)//[23:20]
	#define DP_TX_TOP_RESET_AND_PROBE_RG_PROBE_LOW_HIGH_SWAP Fld(1, 24, AC_MSKB3)//[24:24]
#define DP_TX_TOP_SOFT_PROBE (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x1c)
	#define DP_TX_TOP_SOFT_PROBE_RG_SW_PROBE_VALUE Fld(32, 0, AC_FULLDW)//[31:0]
#define DP_TX_TOP_IRQ_STATUS (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x20)
	#define DP_TX_TOP_IRQ_STATUS_RGS_IRQ_STATUS_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define DP_TX_TOP_IRQ_STATUS_RGS_IRQ_STATUS_1 Fld(8, 8, AC_FULLB1)//[15:8]
#define DP_TX_TOP_IRQ_MASK (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x24)
	#define DP_TX_TOP_IRQ_MASK_RG_IRQ_MASK_0 Fld(8, 0, AC_FULLB0)//[7:0]
	#define DP_TX_TOP_IRQ_MASK_RG_IRQ_MASK_1 Fld(8, 8, AC_FULLB1)//[15:8]
	#define DP_TX_TOP_IRQ_MASK_RG_IRQ_OUT_HIGH_ACTIVE Fld(1, 16, AC_MSKB2)//[16:16]
#define DP_TX_TOP_BLACK_SCREEN (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x28)
	#define DP_TX_TOP_BLACK_SCREEN_RG_BLACK_SCREEN_ENABLE_P0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define DP_TX_TOP_BLACK_SCREEN_RG_BLACK_SCREEN_ENABLE_P1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define DP_TX_TOP_BLACK_SCREEN_RG_BLACK_SCREEN_ENABLE_P2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define DP_TX_TOP_BLACK_SCREEN_RG_BLACK_SCREEN_ENABLE_P3 Fld(1, 3, AC_MSKB0)//[3:3]
#define DP_TX_TOP_MEM_PD (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x2c)
	#define DP_TX_TOP_MEM_PD_RG_MEM_ISO_EN_P0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define DP_TX_TOP_MEM_PD_RG_MEM_PD Fld(1, 1, AC_MSKB0)//[1:1]
	#define DP_TX_TOP_MEM_PD_RG_FUSE_SEL Fld(1, 2, AC_MSKB0)//[2:2]
	#define DP_TX_TOP_MEM_PD_RG_LOAD_PREFUSE_P0 Fld(1, 3, AC_MSKB0)//[3:3]
	#define DP_TX_TOP_MEM_PD_RG_MEM_ISO_EN_P1 Fld(1, 4, AC_MSKB0)//[4:4]
	#define DP_TX_TOP_MEM_PD_RG_LOAD_PREFUSE_P1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define DP_TX_TOP_MEM_PD_RG_MEM_ISO_EN_P2 Fld(1, 6, AC_MSKB0)//[6:6]
	#define DP_TX_TOP_MEM_PD_RG_LOAD_PREFUSE_P2 Fld(1, 7, AC_MSKB0)//[7:7]
	#define DP_TX_TOP_MEM_PD_RG_MEM_ISO_EN_P3 Fld(1, 8, AC_MSKB1)//[8:8]
	#define DP_TX_TOP_MEM_PD_RG_LOAD_PREFUSE_P3 Fld(1, 9, AC_MSKB1)//[9:9]
#define DP_TX_TOP_MBIST_PREFUSE_P0 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x30)
	#define DP_TX_TOP_MBIST_PREFUSE_P0_RGS_PREFUSE_P0 Fld(32, 0, AC_FULLDW)//[31:0]
#define DP_TX_TOP_MEM_DELSEL_0 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x34)
	#define DP_TX_TOP_MEM_DELSEL_0_RG_DELSEL_0 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_0_RG_USE_DEFAULT_DELSEL_0 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x38)
	#define DP_TX_TOP_MEM_DELSEL_1_RG_DELSEL_1 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_1_RG_USE_DEFAULT_DELSEL_1 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_2 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x3c)
	#define DP_TX_TOP_MEM_DELSEL_2_RG_DELSEL_2 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_2_RG_USE_DEFAULT_DELSEL_2 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_3 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x40)
	#define DP_TX_TOP_MEM_DELSEL_3_RG_DELSEL_3 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_3_RG_USE_DEFAULT_DELSEL_3 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_4 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x44)
	#define DP_TX_TOP_MEM_DELSEL_4_RG_DELSEL_4 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_4_RG_USE_DEFAULT_DELSEL_4 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_5 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x48)
	#define DP_TX_TOP_MEM_DELSEL_5_RG_DELSEL_5 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_5_RG_USE_DEFAULT_DELSEL_5 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_6 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x4c)
	#define DP_TX_TOP_MEM_DELSEL_6_RG_DELSEL_6 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_6_RG_USE_DEFAULT_DELSEL_6 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_7 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x50)
	#define DP_TX_TOP_MEM_DELSEL_7_RG_DELSEL_7 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_7_RG_USE_DEFAULT_DELSEL_7 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_8 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x54)
	#define DP_TX_TOP_MEM_DELSEL_8_RG_DELSEL_8 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_8_RG_USE_DEFAULT_DELSEL_8 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_9 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x58)
	#define DP_TX_TOP_MEM_DELSEL_9_RG_DELSEL_9 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_9_RG_USE_DEFAULT_DELSEL_9 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_10 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x5c)
	#define DP_TX_TOP_MEM_DELSEL_10_RG_DELSEL_10 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_10_RG_USE_DEFAULT_DELSEL_10 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_11 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x60)
	#define DP_TX_TOP_MEM_DELSEL_11_RG_DELSEL_11 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_11_RG_USE_DEFAULT_DELSEL_11 Fld(1, 20, AC_MSKB2)//[20:20]
#define DP_TX_TOP_MEM_DELSEL_12 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x64)
	#define DP_TX_TOP_MEM_DELSEL_12_RG_DELSEL_12 Fld(20, 0, AC_MSKW10)//[19:0]
	#define DP_TX_TOP_MEM_DELSEL_12_RG_USE_DEFAULT_DELSEL_12 Fld(1, 20, AC_MSKB2)//[20:20]
#define EDP_TX_TOP_CLKGEN_0_P0 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x68)
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_AUX_P0_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_AUX_MUX_DATA_P0_CKEN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_AUX_MUX_VALID_P0_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_XTAL_P0_CKEN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_VSC_W_P0_CKEN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_ENCODER_L0_P0_CKEN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_ENCODER_L1_P0_CKEN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_ENCODER_L2_P0_CKEN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_ENCODER_L3_P0_CKEN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_SDP_P0_CKEN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_ICG_P0_CKEN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_L0_P0_CKEN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_L1_P0_CKEN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_L2_P0_CKEN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_L3_P0_CKEN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_TPS_P0_CKEN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_FEC_OUT_P0_CKEN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_FEC_IN_P0_CKEN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_PHY_PATGEN_P0_CKEN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_LS_TX_ORG_P0_CKEN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_IN_P0_CKEN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_FRAMESYNC_P0_CKEN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_ALIVE_P0_CKEN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_PATGEN_P0_CKEN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_L0_P0_CKEN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_VIDEO_L0_P0_CKEN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_VIDEO_L1_P0_CKEN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_VIDEO_L2_P0_CKEN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_VIDEO_L3_P0_CKEN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_DSC_P0_CKEN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_CRC_P0_CKEN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_0_P0_REG_PIX_TX_FOR_MN_GEN_P0_CKEN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_1_P0 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x6c)
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_AUX_P0_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_AUX_MUX_DATA_P0_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_AUX_MUX_VALID_P0_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_XTAL_P0_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_VSC_W_P0_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_ENCODER_L0_P0_EN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_ENCODER_L1_P0_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_ENCODER_L2_P0_EN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_ENCODER_L3_P0_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_SDP_P0_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_ICG_P0_EN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_L0_P0_EN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_L1_P0_EN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_L2_P0_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_L3_P0_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_TPS_P0_EN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_FEC_OUT_P0_EN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_FEC_IN_P0_EN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_PHY_PATGEN_P0_EN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_LS_TX_ORG_P0_EN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_IN_P0_EN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_FRAMESYNC_P0_EN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_ALIVE_P0_EN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_PATGEN_P0_EN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_L0_P0_EN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_VIDEO_L0_P0_EN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_VIDEO_L1_P0_EN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_VIDEO_L2_P0_EN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_VIDEO_L3_P0_EN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_DSC_P0_EN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_CRC_P0_EN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_1_P0_REG_PIX_TX_FOR_MN_GEN_P0_EN Fld(1, 31, AC_MSKB3)//[31:31]
#define DP_TX_TOP_PWR_ACK (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x70)
	#define DP_TX_TOP_PWR_ACK_RGS_DP_TX_PWR_ACK Fld(1, 0, AC_MSKB0)//[0:0]
	#define DP_TX_TOP_PWR_ACK_RGS_DP_TX_PWR_ACK_2ND Fld(1, 1, AC_MSKB0)//[1:1]
#define DP_TX_TOP_PHYD_CLK (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x74)
	#define DP_TX_TOP_PHYD_CLK_REG_DPTX_LSO_CLK_DIS Fld(1, 0, AC_MSKB0)//[0:0]
	#define DP_TX_TOP_PHYD_CLK_REG_DPTX_AUXO_CLK_DIS Fld(1, 1, AC_MSKB0)//[1:1]
#define DPTX_TOP_REMOVE_RESET_FLOW (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x78)
	#define DPTX_TOP_REMOVE_RESET_FLOW_REG_DPTX_REMOVE_RESET_FLOW Fld(4, 0, AC_MSKB0)//[3:0]
#define DPTX_VIDEO_SHADOW_MODE (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x7c)
	#define DPTX_VIDEO_SHADOW_MODE_REG_VIDEO_SHADOW_MODE Fld(2, 0, AC_MSKB0)//[1:0]
#define EDP_TX_TOP_CLKGEN_2_P0 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x80)
	#define EDP_TX_TOP_CLKGEN_2_P0_REG_PIX_TX_DSC_BYPASS_P0_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_2_P0_REG_PIX_TX_DSC_BYPASS_P0_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_2_P0_REG_LS_RX_ORG_P0_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_2_P0_REG_LS_RX_ORG_P0_EN Fld(1, 3, AC_MSKB0)//[3:3]
#define DP_TX_TOP_CLOCK_EN_1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x84)
	#define DP_TX_TOP_CLOCK_EN_1_REG_DPTX_CKEN_P2 Fld(16, 0, AC_FULLW10)//[15:0]
#define DP_TX_TOP_SW2_RESET_1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x88)
	#define DP_TX_TOP_SW2_RESET_1_RG_SW2_RST_B_P2 Fld(16, 0, AC_FULLW10)//[15:0]
#define DP_TX_TOP_RESET_AND_PROBE_1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x8c)
	#define DP_TX_TOP_RESET_AND_PROBE_1_RG_SW_RST_B_P1 Fld(8, 0, AC_FULLB0)//[7:0]
	#define DP_TX_TOP_RESET_AND_PROBE_1_RG_SW_RST_B_P2 Fld(8, 8, AC_FULLB1)//[15:8]
	#define DP_TX_TOP_RESET_AND_PROBE_1_RG_SW_RST_B_P3 Fld(8, 16, AC_FULLB2)//[23:16]
#define EDP_TX_TOP_CLKGEN_0_P1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x90)
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_AUX_P1_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_AUX_MUX_DATA_P1_CKEN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_AUX_MUX_VALID_P1_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_XTAL_P1_CKEN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_VSC_W_P1_CKEN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_ENCODER_L0_P1_CKEN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_ENCODER_L1_P1_CKEN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_ENCODER_L2_P1_CKEN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_ENCODER_L3_P1_CKEN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_SDP_P1_CKEN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_ICG_P1_CKEN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_L0_P1_CKEN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_L1_P1_CKEN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_L2_P1_CKEN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_L3_P1_CKEN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_TPS_P1_CKEN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_FEC_OUT_P1_CKEN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_FEC_IN_P1_CKEN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_PHY_PATGEN_P1_CKEN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_LS_TX_ORG_P1_CKEN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_IN_P1_CKEN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_FRAMESYNC_P1_CKEN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_ALIVE_P1_CKEN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_PATGEN_P1_CKEN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_L0_P1_CKEN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_VIDEO_L0_P1_CKEN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_VIDEO_L1_P1_CKEN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_VIDEO_L2_P1_CKEN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_VIDEO_L3_P1_CKEN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_DSC_P1_CKEN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_CRC_P1_CKEN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_0_P1_REG_PIX_TX_FOR_MN_GEN_P1_CKEN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_1_P1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x94)
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_AUX_P1_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_AUX_MUX_DATA_P1_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_AUX_MUX_VALID_P1_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_XTAL_P1_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_VSC_W_P1_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_ENCODER_L0_P1_EN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_ENCODER_L1_P1_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_ENCODER_L2_P1_EN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_ENCODER_L3_P1_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_SDP_P1_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_ICG_P1_EN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_L0_P1_EN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_L1_P1_EN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_L2_P1_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_L3_P1_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_TPS_P1_EN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_FEC_OUT_P1_EN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_FEC_IN_P1_EN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_PHY_PATGEN_P1_EN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_LS_TX_ORG_P1_EN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_IN_P1_EN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_FRAMESYNC_P1_EN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_ALIVE_P1_EN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_PATGEN_P1_EN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_L0_P1_EN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_VIDEO_L0_P1_EN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_VIDEO_L1_P1_EN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_VIDEO_L2_P1_EN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_VIDEO_L3_P1_EN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_DSC_P1_EN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_CRC_P1_EN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_1_P1_REG_PIX_TX_FOR_MN_GEN_P1_EN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_2_P1 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x98)
	#define EDP_TX_TOP_CLKGEN_2_P1_REG_PIX_TX_DSC_BYPASS_P1_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_2_P1_REG_PIX_TX_DSC_BYPASS_P1_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_2_P1_REG_LS_RX_ORG_P1_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_2_P1_REG_LS_RX_ORG_P1_EN Fld(1, 3, AC_MSKB0)//[3:3]
#define EDP_TX_TOP_CLKGEN_0_P2 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0x9c)
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_AUX_P2_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_AUX_MUX_DATA_P2_CKEN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_AUX_MUX_VALID_P2_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_XTAL_P2_CKEN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_VSC_W_P2_CKEN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_ENCODER_L0_P2_CKEN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_ENCODER_L1_P2_CKEN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_ENCODER_L2_P2_CKEN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_ENCODER_L3_P2_CKEN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_SDP_P2_CKEN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_ICG_P2_CKEN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_L0_P2_CKEN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_L1_P2_CKEN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_L2_P2_CKEN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_L3_P2_CKEN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_TPS_P2_CKEN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_FEC_OUT_P2_CKEN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_FEC_IN_P2_CKEN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_PHY_PATGEN_P2_CKEN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_LS_TX_ORG_P2_CKEN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_IN_P2_CKEN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_FRAMESYNC_P2_CKEN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_ALIVE_P2_CKEN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_PATGEN_P2_CKEN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_L0_P2_CKEN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_VIDEO_L0_P2_CKEN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_VIDEO_L1_P2_CKEN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_VIDEO_L2_P2_CKEN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_VIDEO_L3_P2_CKEN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_DSC_P2_CKEN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_CRC_P2_CKEN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_0_P2_REG_PIX_TX_FOR_MN_GEN_P2_CKEN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_1_P2 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xA0)
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_AUX_P2_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_AUX_MUX_DATA_P2_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_AUX_MUX_VALID_P2_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_XTAL_P2_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_VSC_W_P2_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_ENCODER_L0_P2_EN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_ENCODER_L1_P2_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_ENCODER_L2_P2_EN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_ENCODER_L3_P2_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_SDP_P2_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_ICG_P2_EN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_L0_P2_EN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_L1_P2_EN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_L2_P2_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_L3_P2_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_TPS_P2_EN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_FEC_OUT_P2_EN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_FEC_IN_P2_EN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_PHY_PATGEN_P2_EN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_LS_TX_ORG_P2_EN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_IN_P2_EN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_FRAMESYNC_P2_EN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_ALIVE_P2_EN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_PATGEN_P2_EN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_L0_P2_EN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_VIDEO_L0_P2_EN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_VIDEO_L1_P2_EN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_VIDEO_L2_P2_EN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_VIDEO_L3_P2_EN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_DSC_P2_EN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_CRC_P2_EN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_1_P2_REG_PIX_TX_FOR_MN_GEN_P2_EN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_2_P2 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xA4)
	#define EDP_TX_TOP_CLKGEN_2_P2_REG_PIX_TX_DSC_BYPASS_P2_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_2_P2_REG_PIX_TX_DSC_BYPASS_P2_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_2_P2_REG_LS_RX_ORG_P2_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_2_P2_REG_LS_RX_ORG_P2_EN Fld(1, 3, AC_MSKB0)//[3:3]
#define EDP_TX_TOP_CLKGEN_0_P3 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xA8)
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_AUX_P3_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_AUX_MUX_DATA_P3_CKEN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_AUX_MUX_VALID_P3_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_XTAL_P3_CKEN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_VSC_W_P3_CKEN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_ENCODER_L0_P3_CKEN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_ENCODER_L1_P3_CKEN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_ENCODER_L2_P3_CKEN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_ENCODER_L3_P3_CKEN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_SDP_P3_CKEN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_ICG_P3_CKEN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_L0_P3_CKEN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_L1_P3_CKEN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_L2_P3_CKEN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_L3_P3_CKEN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_TPS_P3_CKEN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_FEC_OUT_P3_CKEN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_FEC_IN_P3_CKEN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_PHY_PATGEN_P3_CKEN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_LS_TX_ORG_P3_CKEN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_IN_P3_CKEN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_FRAMESYNC_P3_CKEN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_ALIVE_P3_CKEN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_PATGEN_P3_CKEN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_L0_P3_CKEN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_VIDEO_L0_P3_CKEN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_VIDEO_L1_P3_CKEN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_VIDEO_L2_P3_CKEN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_VIDEO_L3_P3_CKEN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_DSC_P3_CKEN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_CRC_P3_CKEN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_0_P3_REG_PIX_TX_FOR_MN_GEN_P3_CKEN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_1_P3 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xAC)
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_AUX_P3_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_AUX_MUX_DATA_P3_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_AUX_MUX_VALID_P3_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_XTAL_P3_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_VSC_W_P3_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_ENCODER_L0_P3_EN Fld(1, 5, AC_MSKB0)//[5:5]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_ENCODER_L1_P3_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_ENCODER_L2_P3_EN Fld(1, 7, AC_MSKB0)//[7:7]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_ENCODER_L3_P3_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_SDP_P3_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_ICG_P3_EN Fld(1, 10, AC_MSKB1)//[10:10]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_L0_P3_EN Fld(1, 11, AC_MSKB1)//[11:11]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_L1_P3_EN Fld(1, 12, AC_MSKB1)//[12:12]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_L2_P3_EN Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_L3_P3_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_TPS_P3_EN Fld(1, 15, AC_MSKB1)//[15:15]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_FEC_OUT_P3_EN Fld(1, 16, AC_MSKB2)//[16:16]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_FEC_IN_P3_EN Fld(1, 17, AC_MSKB2)//[17:17]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_PHY_PATGEN_P3_EN Fld(1, 18, AC_MSKB2)//[18:18]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_LS_TX_ORG_P3_EN Fld(1, 19, AC_MSKB2)//[19:19]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_IN_P3_EN Fld(1, 20, AC_MSKB2)//[20:20]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_FRAMESYNC_P3_EN Fld(1, 21, AC_MSKB2)//[21:21]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_ALIVE_P3_EN Fld(1, 22, AC_MSKB2)//[22:22]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_PATGEN_P3_EN Fld(1, 23, AC_MSKB2)//[23:23]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_L0_P3_EN Fld(1, 24, AC_MSKB3)//[24:24]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_VIDEO_L0_P3_EN Fld(1, 25, AC_MSKB3)//[25:25]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_VIDEO_L1_P3_EN Fld(1, 26, AC_MSKB3)//[26:26]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_VIDEO_L2_P3_EN Fld(1, 27, AC_MSKB3)//[27:27]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_VIDEO_L3_P3_EN Fld(1, 28, AC_MSKB3)//[28:28]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_DSC_P3_EN Fld(1, 29, AC_MSKB3)//[29:29]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_CRC_P3_EN Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_CLKGEN_1_P3_REG_PIX_TX_FOR_MN_GEN_P3_EN Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_CLKGEN_2_P3 (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xB0)
	#define EDP_TX_TOP_CLKGEN_2_P3_REG_PIX_TX_DSC_BYPASS_P3_CKEN Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_CLKGEN_2_P3_REG_PIX_TX_DSC_BYPASS_P3_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define EDP_TX_TOP_CLKGEN_2_P3_REG_LS_RX_ORG_P3_CKEN Fld(1, 2, AC_MSKB0)//[2:2]
	#define EDP_TX_TOP_CLKGEN_2_P3_REG_LS_RX_ORG_P3_EN Fld(1, 3, AC_MSKB0)//[3:3]
#define EDP_TX_TOP_PIX_CLK_SEL (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xB4)
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_TX_VIDEO_MOD_CLK_SEL Fld(3, 0, AC_MSKB0)//[2:0]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_SEL Fld(3, 3, AC_MSKB0)//[5:3]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_2_SEL Fld(2, 6, AC_MSKB0)//[7:6]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_4_SEL Fld(2, 8, AC_MSKB1)//[9:8]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_8_SEL Fld(2, 10, AC_MSKB1)//[11:10]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_16_SEL Fld(2, 12, AC_MSKB1)//[13:12]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_32_SEL Fld(2, 14, AC_MSKB1)//[15:14]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_64_SEL Fld(2, 16, AC_MSKB2)//[17:16]
	#define EDP_TX_TOP_PIX_CLK_SEL_REG_PIX_CLK_ORI_SEL Fld(2, 18, AC_MSKB2)//[19:18]
#define EDP_TX_TOP_PIX_DATA_SEL (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xB8)
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX0IN_SEL Fld(3, 0, AC_MSKB0)//[2:0]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX1IN_SEL Fld(3, 3, AC_MSKB0)//[5:3]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX2IN_SEL Fld(3, 6, AC_MSKW10)//[8:6]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX3IN_SEL Fld(3, 9, AC_MSKB1)//[11:9]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX4IN_SEL Fld(3, 12, AC_MSKB1)//[14:12]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX5IN_SEL Fld(3, 15, AC_MSKB1)//[17:15]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX6IN_SEL Fld(3, 18, AC_MSKB2)//[20:18]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PIX7IN_SEL Fld(3, 21, AC_MSKB2)//[23:21]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_PORT_SELECT Fld(2, 24, AC_MSKB3)//[25:24]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_START_READ_NUMBER Fld(4, 26, AC_MSKB3)//[29:26]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_WPTR_CLEAR Fld(1, 30, AC_MSKB3)//[30:30]
	#define EDP_TX_TOP_PIX_DATA_SEL_REG_RPTR_CLEAR Fld(1, 31, AC_MSKB3)//[31:31]
#define EDP_TX_TOP_PIX_DATA_CONTROL (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xBC)
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_LAST_BYTE_4P Fld(1, 0, AC_MSKB0)//[0:0]
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_ENC0_SEL Fld(3, 1, AC_MSKB0)//[3:1]
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_ENC1_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_ENC2_SEL Fld(3, 7, AC_MSKW10)//[9:7]
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_ENC3_SEL Fld(3, 10, AC_MSKB1)//[12:10]
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_IRQ_FULL_CLEAR Fld(1, 13, AC_MSKB1)//[13:13]
	#define EDP_TX_TOP_PIX_DATA_CONTROL_REG_IRQ_EMPTY_CLEAR Fld(1, 14, AC_MSKB1)//[14:14]
#define DP_TX_TOP_FIFO_POINTER_STATUS (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xC0)
	#define DP_TX_TOP_FIFO_POINTER_STATUS_RGS_EDP12_WRITE_POINTER Fld(5, 0, AC_MSKB0)//[4:0]
	#define DP_TX_TOP_FIFO_POINTER_STATUS_RGS_EDP12_READ_POINTER Fld(5, 5, AC_MSKW10)//[9:5]
#define DP_TX_TOP_MISC (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xC4)
	#define DP_TX_TOP_MISC_REG_DUMMY_FOR_CG0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define DP_TX_TOP_MISC_REG_DUMMY_FOR_CG1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define DP_TX_TOP_MISC_REG_DUMMY_FOR_CG2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define DP_TX_TOP_MISC_REG_DUMMY_FOR_CG3 Fld(1, 3, AC_MSKB0)//[3:3]
#define DP_TX_TOP_MBIST_PREFUSE_P2_DUMMY (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xC8)
	#define DP_TX_TOP_MBIST_PREFUSE_P2_DUMMY_RGS_PREFUSE_P2 Fld(32, 0, AC_FULLDW)//[31:0]
#define DP_TX_TOP_MBIST_PREFUSE_P3_DUMMY (EDP12_TV_TX_PAR_WRAP_X32_EDPTX_MAC_REG + 0xcc)
	#define DP_TX_TOP_MBIST_PREFUSE_P3_DUMMY_RGS_PREFUSE_P3 Fld(32, 0, AC_FULLDW)//[31:0]
