// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * MediaTek Panel driver
 *
 * Copyright (c) 2020 MediaTek Inc.
 * Author Yu-Jen.Huang <yu-jen.huang@mediatek.com>
 */
//#define DEBUG
#include <common.h>
#include <dm.h>
#include <utility.h>
#include <debug_impl.h>
#include <system_impl.h>
#include <mtk_panel.h>
#include <dts_parser.h>
#include "coda/TGEN_MAIN_BKA3A0.h"
#include "coda/TGEN_FRAMELOCK_BKA3A2.h"
#include "coda/TRIGGER_GEN_BKA3A5.h"
#include "coda/DISP_LB_BKA326.h"
#include "coda/TGEN_REGEN_BKA39C.h"
#include "coda/DELTA_PATH_BKA35B.h"
#include "coda/PATGEN_SCALER_BKA404.h"
#include "coda/PATGEN_SCALER_BKA407.h"
#include "coda/PATGEN_SCALER_BKA409.h"
#include "coda/GOPG_HVSP4_BKA4DA.h"
#include "coda/ckgen00.h"
#include "coda/ckgen01.h"
#include "coda/CKGEN00_V004.h"
#include "coda/CKGEN01_V004.h"
#include "coda/TCON_VCOM_PAT_V005.h"
#include "coda/modv11.h"
#include "coda/modv12.h"
#include "coda/modv13.h"
#include "coda/modv21.h"
#include "coda/modv22.h"
#include "coda/modd1.h"
#include "coda/moda1.h"
#include "coda/moda2.h"
#include "coda/moda3.h"
#include "coda/moda4.h"
#include "coda/modosd1.h"
#include "coda/modosd2.h"
#include "coda/lpll.h"
#include "coda/SCAID_BIND_BKA3AE.h"
#include "coda/PATGEN_SCALER_BKA401.h"
#include "coda/TRIGGER_GEN_BKA3A4.h"
#include "coda/GOP0_BKA4DE.h"
#include "coda/GOPG_BKA4D9.h"
#include "coda/IP2_M_BKA330.h"
#include "coda/SCTCON_MISC_BKA3E0.h"
#include "coda/TGEN_OUTPUT_BKA3A3.h"
#include "coda/reg_META_DATA_TRANSFER_BKA35A.h"
#include "coda/PAFRC_BKA324.h"
#include "coda/PAFRC_BKA324_V004.h"
#include "coda/DEMURA_BKA377_V004.h"
#include "coda/LINEOD_BKA3A8_V004.h"
#include "coda/PAT_DET_BKA37F_V004.h"
#include "coda/OD_1ST_BKA336_V004.h"
#include "coda/OD_2ND_BKA337_V004.h"
#include "coda/OD_3RD_BKA338_V004.h"
#include "coda/SCTCON_BKA4F7_V004.h"
#include "mtk_pnl_utility.h"
#include "mtk_tv_pnl.h"
#include "coda/MODV11_V004.h"
#include "coda/MODV12_V004.h"
#include "coda/MODV13_V004.h"
#include "coda/MODD1_V004.h"
#include "coda/MODA1_V004.h"
#include "coda/MODA2_V004.h"
#include "coda/MODA3_V004.h"
#include "coda/MODA4_V004.h"
#include "coda/MODOSD1_V004.h"
#include "coda/MODOSD2_V004.h"
#include "coda/LPLL_V004.h"
#include "coda/DISP_MISC_V004.h"
#include "coda/DET_V004.h"
#include "coda/SCDISP_BKA4FA.h"
#include "mtk_pnl_autodownload.h"
#include "coda/CKGEN00_V005.h"
#include "coda/CKGEN01_V005.h"
#include "coda/MODV11_V005.h"
#include "coda/MODV12_V005.h"
#include "coda/MODD1_V005.h"
#include "coda/MODOSD1_V005.h"
#include "coda/MODOSD2_V005.h"
#include "coda/MODA1_V005.h"
#include "coda/MODA4_V005.h"
#include "coda/LPLL_V005.h"
#include "coda/disp_misc.h"
#include "mtk_tcon_common.h"
#include "mtk_tcon_out_if.h"
#include "mtk_pnl_out_if.h"
#include "mtk_pnl_clk_ctrl.h"
#include "coda/FRCPLL.h"
#include "coda/SCTCON_MISC_BKA3E0_V005.h"
#include "coda/XCPLL_REG_V005.h"
#include "coda/CKGEN00_V006.h"
#include "coda/CKGEN01_V006.h"
#include "coda/XCPLL_V006.h"
#include "coda/TCON_SET_V005.h"
#include "coda/BLEND_TOP_BKA36B.h"
#include "coda/TCON_4K.h"
#include "coda/OSDB_COLOV_BKA3ED.h"
#include <asm/io.h>
#include "coda/TOP_CKGEN01_V007.h"
#include "coda/TOP_CKGEN00_V007.h"
#include "coda/CLKGEN_FRC00.h"
#include "coda/CLKGEN_SC00.h"
#include "coda/CLKGEN_SC01.h"
#include "coda/CLKGEN_SC02.h"
#include "coda/TOP_XCPLL_V007.h"
#include "coda/TOP_XCBPLL.h"

//Only for HAPS
#define REG_HFRC_HAPS_BASE 	(0x147F400)
#define REG_HFRC_HVSP_IP_BASE	(0x147F600)
#define REG_HFRC_HVSP_OP_BASE	(0x147E800)

#define TGEN_2P (2)
#define TGEN_4P (4)

#define MFT_P (8)

#define MOD_VER2 (2)
#define MOD_VER3 (3)
#define REG_ALL (0xFFFF)
#define REG_0000 (0x0000)
#define REG_0001 (0x0001)
#define REG_0870 (0x0870)
#define REG_01FF (0x01FF)
#define REG_03FF (0x03FF)
#define REG_0F00 (0x0F00)

#define DELAY10 (10)


#define FULL_BIT (16)
#define VBO_USE_LANE_NUM_64 64
#define VBO_USE_LANE_NUM_40 40
#define VBO_USE_LANE_NUM_32 32
#define VBO_USE_LANE_NUM_16 16
#define VBO_USE_LANE_NUM_8 8
#define VBO_USE_LANE_NUM_4 4
#define VBO_USE_LANE_NUM_2 2

#define OUT_CONFIG_OFF (0x0000)
#define OUT_CONFIG_4K60_1_VER1 (0x5545)
#define OUT_CONFIG_4K60_2_VER1 (0x0010)
#define OUT_CONFIG_4K60_1_VER2 (0x5555)
#define OUT_CONFIG_4K60_2_VER2 (0x0000)

#define FRCPLL_CONFIG_SET_0_0014 (0xe6cc)
#define FRCPLL_CONFIG_SET_1_0018 (0x1f)
#define FRCPLL_CONFIG_STEP_0_001C (0x001e)
#define FRCPLL_CONFIG_SPAN_0_0024 (0x02a6)
#define FRCPLL_CONFIG_TEST_0000 (0x0012)
#define FRCPLL_CONFIG_LOOP_DIV_SECOND_000C (0x03)
#define FRCPLL_CONFIG_ICP_ICTRL_0010 (0x02)
#define FRCPLL_CONFIG_OUTPUT_DIV_000C (0x04)

#define FRCPLL_CONFIG_UDELAY (500)

#define VBY1_LOCK_PROTECT_EN true

//efuse for mod
#define EFUSE_BANK (0x252A0) //bank 0x129_50(8bit) to switch sub-bank.
#define MOD_ATOP_SUBBANK (0x12) // MOD_ATOP subbank is 0x12, addr[8:2]
#define MOD_ATOP_SUBBANK_VER004 (0x15) // MOD_ATOP subbank is 0x12, addr[8:2]
#define MOD_ATOP_SUBBANK_VER005 (0x12) // MOD_ATOP subbank is 0x12, addr[8:2]
#define MOD_ATOP_SUBBANK_0C (0x0C)
#define MOD_ATOP_SUBBANK_0D (0x0D)
#define MOD_ATOP_SUBBANK_13_VER005 (0x13)
#define MOD_ATOP_SUBBANK_14_VER005 (0x14)
#define EFUSE_PPM_REG_TABLE_1 (0x2E) //bank 0x129_A0 (8bit)
#define EFUSE_PPM_REG_TABLE_1_TCON_DISABLE_BIT (1<<25)	//Bit25


#define EFUSE_VAL_LSB	(0x252B0)
#define EFUSE_VAL_MSB	(0x252B4)
#define TIME_OUT_CNT	(10)
#define RINT_THRESHOLD	(0x200)// 12M:0x200, 24M:0x100
#define MOD_VOL_VX1_ACT_BIT	(6)
#define MOD_CUR_SINGLE_LSB	(7)
#define MOD_CUR_SINGLE_MASK (0x7F)
#define MOD_CUR_SINGLE_ACT_BIT	(14)
#define MOD_CUR_SINGLE_ACT_BIT_VER2	(24)

#define MOD_CUR_DOUBLE_MASK (0x7F)
#define MOD_CUR_DOUBLE_MASK_VER5 (0x3F)
#define MOD_CUR_DOUBLE_LSB	(15)
#define MOD_CUR_DOUBLE_LSB_VER5	(7)
#define MOD_CUR_DOUBLE_OFFSET	(15)
#define MOD_CUR_DOUBLE_ACT_BIT	(22)
#define MOD_CUR_DOUBLE_ACT_BIT_VER5	(16)
#define MOD_RINT_OFFSET		(23)
#define MOD_RINT_ACT_BIT	(30)
#define LPLL_RETIME_CTRL	(25)
#define LPLL_DELAY_TIME_CTRL	(26)

//max/min/default for RCON setting for swing calibration
#define RCON_MAX_VAL	(25)
#define RCON_MIN_VAL	(6)
#define RCON_DEF_VAL	(16)

//max/min/default for BiasCon
#define BIASCON_SINGLE_MAX_VAL	(85)
#define BIASCON_SINGLE_MIN_VAL	(55)
#define BIASCON_DOUBLE_MAX_VAL	(85)
#define BIASCON_DOUBLE_MIN_VAL	(55)
#define BIASCON_DEF_VAL	(70)
#define DIV_2	(2)
#define DIV_4	(4)
#define DIV_8	(8)

#define DEC_0 (0)
#define DEC_1 (1)
#define DEC_2 (2)
#define DEC_3 (3)
#define DEC_4 (4)
#define DEC_5 (5)
#define DEC_6 (6)
#define DEC_7 (7)
#define DEC_8 (8)
#define DEC_9 (9)
#define DEC_10 (10)
#define DEC_11 (11)
#define DEC_12 (12)
#define DEC_13 (13)
#define DEC_14 (14)
#define DEC_15 (15)
#define DEC_16 (16)
#define DEC_19 (19)

#define HEX_F (0xf)
#define HEX_FFFF (0xffff)
#define HEX_1010 (0x1010)

#define CHIP_VERSION2 (2)
#define CHIP_VERSION3 (3)
#define CHIP_VERSION4 (4)

#define TIMING_4K_H_ACTIVE 3840
#define TIMING_4K_V_ACTIVE 2160

//MT5877 XCPLL CLK
#define XCPLL_REG_0007_SET (0x0001)
#define XCBPLL_REG_0007_SET (0x1100)
#define XC_CLK_007_INFRA_CK (0x3)
#define XC_CLK_007_XC_FN (0x2)
#define XCPLL_REG_0007_SET_0 (0xd957)
#define XCPLL_REG_0007_SET_1 (0x70)
#define XCPLL_REG_0007_ICTRL (0x3)
#define XCPLL_REG_0007_LOOP_DIV_FIRST (0x3)
#define XCPLL_REG_0007_LOOP_DIV_SECOND (0x6)
#define XCBPLL_ICTRL (0x2)
#define XCBPLL_LOOPDIV_SECOND (0x3c)
#define TEST_XCBPLL (0x10)
#define XCPLL_DELAY_TIME (500)  //us
#define XCPLL_4 (4)
#define XCPLL_8 (8)
#define XCPLL_12 (12)

#define MOD_BLOCKPATTERN_TBL_MAX_SIZE       (0x60)
#define MOD_BLOCKPATTERN_TBL_LINE_SIZE      (0x18)
#define MOD_BLOCKPATTERN_ADDR_STEP               (4)

#ifdef MSOS_TYPE_LINUX_KERNEL
#define mst_atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0);
#else
#define mst_atoi(str) strtoul(((str != NULL) ? str : ""), NULL, 0);
#endif

bool MApi_PNL_TCONMAP_DumpTable(struct udevice *dev, uint8_t* pTCONTable, uint8_t* pEVATable, uint8_t uint8_tTcontype);

static void _vby1_gfx_4kARGB8888_60HZ(void)
{
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_ARGB_MODE);

	//mft mode
	W2BYTEMSK(REG_0004_MODOSD1, 0x1, REG_0004_MODOSD1_REG_MFT_MODE);
	W2BYTEMSK(REG_0004_MODOSD1, 0x0, REG_0004_MODOSD1_REG_DIV_PIX_MODE);
	W2BYTEMSK(REG_0040_MODOSD1, 0xF00, REG_0040_MODOSD1_REG_HSIZE);
	W2BYTEMSK(REG_0044_MODOSD1, 0xF00, REG_0044_MODOSD1_REG_DIV_LEN);
	W2BYTEMSK(REG_0048_MODOSD1, 0x0, REG_0048_MODOSD1_REG_BASE0_ADDR);

	// mode 0 /mode 1 switch case usage?
	// W2BYTEMSK(REG_0008_MODOSD2, 0x2, REG_0008_MODOSD2_REG_FORMAT_MAP);

	W2BYTEMSK(REG_0188_MODOSD2, 0x2, REG_0188_MODOSD2_REG_VBY1_BYTE_MODE);
	W2BYTEMSK(REG_015C_MODD1, 0x1, REG_015C_MODD1_REG_SERI_FORMAT_OSD);
	W2BYTEMSK(REG_0144_MODD1, 0x1, REG_0144_MODD1_REG_SERI_OSD_MODE);
	//bit 2
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,2,AC_MSKB0));
	W2BYTEMSK(REG_003C_MODOSD1, 0x22, REG_003C_MODOSD1_REG_MFT_READ_HDE_ST);
}

static void _vby1_gfx_4kARGB8101010_60HZ(void)
{
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_ARGB_MODE);

	//mft mode
	W2BYTEMSK(REG_0004_MODOSD1, 0x1, REG_0004_MODOSD1_REG_MFT_MODE);
	W2BYTEMSK(REG_0004_MODOSD1, 0x0, REG_0004_MODOSD1_REG_DIV_PIX_MODE);
	W2BYTEMSK(REG_0040_MODOSD1, 0xF00, REG_0040_MODOSD1_REG_HSIZE);
	W2BYTEMSK(REG_0044_MODOSD1, 0xF00, REG_0044_MODOSD1_REG_DIV_LEN);
	W2BYTEMSK(REG_0048_MODOSD1, 0x0, REG_0048_MODOSD1_REG_BASE0_ADDR);

	W2BYTEMSK(REG_0008_MODOSD2, 0x2, REG_0008_MODOSD2_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0188_MODOSD2, 0x1, REG_0188_MODOSD2_REG_VBY1_BYTE_MODE);
	W2BYTEMSK(REG_015C_MODD1, 0x3, REG_015C_MODD1_REG_SERI_FORMAT_OSD);

	W2BYTEMSK(REG_0144_MODD1, 0x1, REG_0144_MODD1_REG_SERI_OSD_MODE);
	W2BYTEMSK(REG_0038_MODA1, 0x1, Fld(1,2,AC_MSKB0)); // bit2, 5byte mode
	W2BYTEMSK(REG_003C_MODOSD1, 0x22, REG_003C_MODOSD1_REG_MFT_READ_HDE_ST);
}

static void _vby1_gfx_4k_30HZ(void)
{
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODOSD1, 0x1, REG_0140_MODOSD1_REG_ARGB_MODE);

	//mft mode
	W2BYTEMSK(REG_0004_MODOSD1, 0x1, REG_0004_MODOSD1_REG_MFT_MODE);
	W2BYTEMSK(REG_0004_MODOSD1, 0x1, REG_0004_MODOSD1_REG_DIV_PIX_MODE);
	W2BYTEMSK(REG_0040_MODOSD1, 0xF00, REG_0040_MODOSD1_REG_HSIZE);
	W2BYTEMSK(REG_0044_MODOSD1, 0xF00, REG_0044_MODOSD1_REG_DIV_LEN);
	W2BYTEMSK(REG_0048_MODOSD1, 0x0, REG_0048_MODOSD1_REG_BASE0_ADDR);

	W2BYTEMSK(REG_0008_MODOSD2, 0x2, REG_0008_MODOSD2_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0188_MODOSD2, 0x2, REG_0188_MODOSD2_REG_VBY1_BYTE_MODE);
	W2BYTEMSK(REG_015C_MODD1, 0x1, REG_015C_MODD1_REG_SERI_FORMAT_OSD);
	W2BYTEMSK(REG_0144_MODD1, 0x1, REG_0144_MODD1_REG_SERI_OSD_MODE);
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,2,AC_MSKB0)); // bit2
	W2BYTEMSK(REG_003C_MODOSD1, 0x22, REG_003C_MODOSD1_REG_MFT_READ_HDE_ST);

}

static void _vby1_extv_4k_60HZ(void)
{
	W2BYTEMSK(REG_0000_MODD1, 0x0, REG_0000_MODD1_REG_V2_SEL);
	W2BYTEMSK(REG_0140_MODV21, 0x1, REG_0140_MODV21_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODV21, 0x1, REG_0140_MODV21_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV21, 0x1, REG_0140_MODV21_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0004_MODV22, 0x0, REG_0004_MODV22_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0008_MODV22, 0x0, REG_0008_MODV22_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0188_MODV22, 0x2, REG_0188_MODV22_REG_VBY1_BYTE_MODE);
	W2BYTEMSK(REG_015C_MODD1, 0x1, REG_015C_MODD1_REG_SERI_FORMAT_V2);
	W2BYTEMSK(REG_0144_MODD1, 0x1, REG_0144_MODD1_REG_SERI_V2_MODE);
	//bit[1:1]
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,1,AC_MSKB0));
	W2BYTEMSK(REG_003C_MODV21, 0x22, REG_003C_MODV21_REG_MFT_READ_HDE_ST);
}

static void _vby1_extv_4k_120HZ(void)
{
	W2BYTEMSK(REG_0000_MODD1, 0x1, REG_0000_MODD1_REG_V2_SEL);
	W2BYTEMSK(REG_0140_MODV21, 0x0, REG_0140_MODV21_REG_MOD_1PTO2P_EN);
	W2BYTEMSK(REG_0140_MODV21, 0x0, REG_0140_MODV21_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV21, 0x1, REG_0140_MODV21_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0004_MODV22, 0x1, REG_0004_MODV22_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0008_MODV22, 0x0, REG_0008_MODV22_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0188_MODV22, 0x2, REG_0188_MODV22_REG_VBY1_BYTE_MODE);
	W2BYTEMSK(REG_015C_MODD1, 0x1, REG_015C_MODD1_REG_SERI_FORMAT_V2);
	W2BYTEMSK(REG_0144_MODD1, 0x1, REG_0144_MODD1_REG_SERI_V2_MODE);
	//bit[1:1]
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,1,AC_MSKB0));
	W2BYTEMSK(REG_003C_MODV21, 0x10, REG_003C_MODV21_REG_MFT_READ_HDE_ST);
}

static void _lvds_v_fhd_60HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	// LVDS always 2p
	if (priv->pnl_lib_version != BOOT_PNL_VERSION0400 &&
		priv->pnl_lib_version != BOOT_PNL_VERSION0500) {
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203) {
			W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_1PTO2P_EN);
			W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
			W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
		} else {
			W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
			if (priv->pnl_lib_version == BOOT_PNL_VERSION0300)
				W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
			else
				W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
		}
	}
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x2, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0x780, REG_0040_MODV11_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);
	W2BYTEMSK(REG_015C_MODD1, 0x0, REG_015C_MODD1_REG_SERI_FORMAT_V1);
	//REG_0038_MODA1_REG_GCR_BANK_CLK_SRC_SEL bit[0:0]
	W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,0,AC_MSKB0));
	W2BYTEMSK(REG_003C_MODV11, 0x10, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_RSCLK_TESTMD);
	W2BYTEMSK(REG_00E0_MODD1, priv->lvds_info.panel_lvds_ti_mode, REG_00E0_MODD1_REG_LVDS_TI);
	W2BYTEMSK(REG_00E0_MODD1, priv->lvds_info.panel_pdp_10bit, REG_00E0_MODD1_REG_PDP_10BIT);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_LVDS_PLASMA);
	W2BYTEMSK(REG_00E0_MODD1, (priv->lvds_info.panel_swap_lvds_pol), REG_00E0_MODD1_REG_CH_POLARITY);
	W2BYTEMSK(REG_00E0_MODD1, priv->lvds_info.panel_swap_lvds_ch, REG_00E0_MODD1_REG_PA_SWAP);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_PDP_CH4_SET);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_PDP_CH4_EN);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_PDP_CH3_SET);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_PDP_CH3_EN);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_PDP_MASK_SET);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_PDP_MASK_EN);
	W2BYTEMSK(REG_00E0_MODD1, priv->lvds_info.ti_bit_mode, REG_00E0_MODD1_REG_TI_BITMODE);
	W2BYTEMSK(REG_00E0_MODD1, 0x0, REG_00E0_MODD1_REG_LVDS_TESTERMD);
}

static void _vby1_v_fhd_60HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->pnl_lib_version != BOOT_PNL_VERSION0400 &&
		priv->pnl_lib_version != BOOT_PNL_VERSION0500 &&
		priv->pnl_lib_version != BOOT_PNL_VERSION0600) {
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203)
			W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
		else
			W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0300)
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x2, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0x780, REG_0040_MODV11_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		W2BYTEMSK(REG_003C_MODV11, 0x6, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
	else
		W2BYTEMSK(REG_003C_MODV11, 0x10, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}

static void _vby1_v_fhd_120HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);

	if (priv->pnl_lib_version == CHIP_VERSION3)
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x1, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0x780, REG_0040_MODV11_REG_HSIZE); //move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);

	W2BYTEMSK(REG_003C_MODV11, 0x10, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}

static void _vby1_v_4k_60HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0300)
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0xF00, REG_0040_MODV11_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);

	W2BYTEMSK(REG_003C_MODV11, 0x22, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}

static void _vby1_v_4k_120HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0300)
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0xF00, REG_0040_MODV11_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_004C_MODV11, 0x0, REG_004C_MODV11_REG_BASE1_ADDR);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);

	W2BYTEMSK(REG_003C_MODV11, 0x10, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}

static void _vby1_v_8k422_60HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0300) {
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	} else {
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	}
	W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0xF00, REG_0040_MODV11_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x0, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_FORMAT_MAP);

	W2BYTEMSK(REG_003C_MODV11, 0x10, REG_003C_MODV11_REG_MFT_READ_HDE_ST);

	//scton bypass for yuv422 output
	//W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 0x0, REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL);
}

static void _vby1_v_8k_60HZ(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	if (priv->pnl_lib_version == BOOT_PNL_VERSION0300)
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	else
		W2BYTEMSK(REG_0140_MODV11, 0x1, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
	//W2BYTEMSK(REG_0040_MODV11, 0x1E00, REG_0040_MODV11_REG_HSIZE); // move into _vby1_set_mft()
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0004_MODV21, 0x1, REG_0004_MODV21_REG_SRAM_EXT_EN);

	W2BYTEMSK(REG_003C_MODV11, 0x10, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}

static void _vby1_v_8k_120HZ(void)
{
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
	W2BYTEMSK(REG_0040_MODV11, 0x1E00, REG_0040_MODV11_REG_HSIZE);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_32PTO64P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0004_MODV21, 0x1, REG_0004_MODV21_REG_SRAM_EXT_EN);
	W2BYTEMSK(REG_0004_MODV21, 0x1, REG_0004_MODV21_REG_8P_OE_IN_EN);
	W2BYTEMSK(REG_0184_MODV12, 0x1, REG_0184_MODV12_REG_VBY1_LOCK_VIDEO);
	W2BYTEMSK(REG_0100_DISP_MISC, 0x1, REG_0100_DISP_MISC_REG_ODCLK_ROOT_EN);
	W2BYTEMSK(0x484300, 0x1, Fld(1,15,AC_MSKB1));

	W2BYTEMSK(REG_003C_MODV11, 0x07, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}

static void _vby1_v_8k_144HZ(void)
{
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
	W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_YUV_422_MODE);
	W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
	W2BYTEMSK(REG_0040_MODV11, 0x1E00, REG_0040_MODV11_REG_HSIZE);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_8PTO16P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_16PTO32P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_32PTO64P_EN);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, 0x1, REG_0004_MODV12_REG_VBY1_VS_INV);
	W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_FORMAT_MAP);
	W2BYTEMSK(REG_0004_MODV21, 0x1, REG_0004_MODV21_REG_SRAM_EXT_EN);
	W2BYTEMSK(REG_0004_MODV21, 0x1, REG_0004_MODV21_REG_8P_OE_IN_EN);
	W2BYTEMSK(REG_0184_MODV12, 0x1, REG_0184_MODV12_REG_VBY1_LOCK_VIDEO);
	W2BYTEMSK(REG_0100_DISP_MISC, 0x1, REG_0100_DISP_MISC_REG_ODCLK_ROOT_EN);
	W2BYTEMSK(0x484300, 0x1, Fld(1,15,AC_MSKB1));

	W2BYTEMSK(REG_003C_MODV11, 0x07, REG_003C_MODV11_REG_MFT_READ_HDE_ST);
}


static void _vby1_seri_data_sel(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->lanes == 32)
		W2BYTEMSK(REG_00C0_MODD1, 0x1, REG_00C0_MODD1_REG_DATAX_SEL);

	if (priv->lanes == 16 || priv->lanes == 8)
		W2BYTEMSK(REG_00C0_MODD1, 0x2, REG_00C0_MODD1_REG_DATAX_SEL);

	if (priv->lanes == 64)
		W2BYTEMSK(REG_00C0_MODD1, 0x3, REG_00C0_MODD1_REG_DATAX_SEL);

	if (priv->linktype == E_LINK_LVDS)
		W2BYTEMSK(REG_00C0_MODD1, 0x0, REG_00C0_MODD1_REG_DATAX_SEL);

}

static void _pin_mapping_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}
	//ping mapping free swap
	if (priv->linktype == E_LINK_LVDS) {
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
			W2BYTEMSK(REG_0044_MODD1, 0x00, REG_0044_MODD1_REG_FREE_CH02_SWAP);
			W2BYTEMSK(REG_0044_MODD1, 0x01, REG_0044_MODD1_REG_FREE_CH03_SWAP);
			W2BYTEMSK(REG_0048_MODD1, 0x02, REG_0048_MODD1_REG_FREE_CH04_SWAP);
			W2BYTEMSK(REG_0048_MODD1, 0x03, REG_0048_MODD1_REG_FREE_CH05_SWAP);
			W2BYTEMSK(REG_004C_MODD1, 0x04, REG_004C_MODD1_REG_FREE_CH06_SWAP);
			W2BYTEMSK(REG_004C_MODD1, 0x05, REG_004C_MODD1_REG_FREE_CH07_SWAP);
			W2BYTEMSK(REG_0050_MODD1, 0x06, REG_0050_MODD1_REG_FREE_CH08_SWAP);
			W2BYTEMSK(REG_0050_MODD1, 0x07, REG_0050_MODD1_REG_FREE_CH09_SWAP);
			W2BYTEMSK(REG_0054_MODD1, 0x08, REG_0054_MODD1_REG_FREE_CH10_SWAP);
			W2BYTEMSK(REG_0054_MODD1, 0x09, REG_0054_MODD1_REG_FREE_CH11_SWAP);
			W2BYTEMSK(REG_0058_MODD1, 0x0A, REG_0058_MODD1_REG_FREE_CH12_SWAP);
			W2BYTEMSK(REG_0058_MODD1, 0x0B, REG_0058_MODD1_REG_FREE_CH13_SWAP);
		}
	}

	if (priv->linktype == E_LINK_VB1) {
		if (priv->lane_info.sup_lanes == 20 || priv->lane_info.sup_lanes == 40 || priv->lane_info.sup_lanes == 64) {
			W2BYTEMSK(REG_0040_MODD1, priv->lane_info.def_layout[0], REG_0040_MODD1_REG_FREE_CH00_SWAP);
			W2BYTEMSK(REG_0040_MODD1, priv->lane_info.def_layout[1], REG_0040_MODD1_REG_FREE_CH01_SWAP);
			W2BYTEMSK(REG_0044_MODD1, priv->lane_info.def_layout[2], REG_0044_MODD1_REG_FREE_CH02_SWAP);
			W2BYTEMSK(REG_0044_MODD1, priv->lane_info.def_layout[3], REG_0044_MODD1_REG_FREE_CH03_SWAP);
			W2BYTEMSK(REG_0048_MODD1, priv->lane_info.def_layout[4], REG_0048_MODD1_REG_FREE_CH04_SWAP);
			W2BYTEMSK(REG_0048_MODD1, priv->lane_info.def_layout[5], REG_0048_MODD1_REG_FREE_CH05_SWAP);
			W2BYTEMSK(REG_004C_MODD1, priv->lane_info.def_layout[6], REG_004C_MODD1_REG_FREE_CH06_SWAP);
			W2BYTEMSK(REG_004C_MODD1, priv->lane_info.def_layout[7], REG_004C_MODD1_REG_FREE_CH07_SWAP);
			W2BYTEMSK(REG_0050_MODD1, priv->lane_info.def_layout[8], REG_0050_MODD1_REG_FREE_CH08_SWAP);
			W2BYTEMSK(REG_0050_MODD1, priv->lane_info.def_layout[9], REG_0050_MODD1_REG_FREE_CH09_SWAP);
			W2BYTEMSK(REG_0054_MODD1, priv->lane_info.def_layout[10], REG_0054_MODD1_REG_FREE_CH10_SWAP);
			W2BYTEMSK(REG_0054_MODD1, priv->lane_info.def_layout[11], REG_0054_MODD1_REG_FREE_CH11_SWAP);
			W2BYTEMSK(REG_0058_MODD1, priv->lane_info.def_layout[12], REG_0058_MODD1_REG_FREE_CH12_SWAP);
			W2BYTEMSK(REG_0058_MODD1, priv->lane_info.def_layout[13], REG_0058_MODD1_REG_FREE_CH13_SWAP);
			W2BYTEMSK(REG_005C_MODD1, priv->lane_info.def_layout[14], REG_005C_MODD1_REG_FREE_CH14_SWAP);
			W2BYTEMSK(REG_005C_MODD1, priv->lane_info.def_layout[15], REG_005C_MODD1_REG_FREE_CH15_SWAP);
			W2BYTEMSK(REG_0060_MODD1, priv->lane_info.def_layout[16], REG_0060_MODD1_REG_FREE_CH16_SWAP);
			W2BYTEMSK(REG_0060_MODD1, priv->lane_info.def_layout[17], REG_0060_MODD1_REG_FREE_CH17_SWAP);
			W2BYTEMSK(REG_0064_MODD1, priv->lane_info.def_layout[18], REG_0064_MODD1_REG_FREE_CH18_SWAP);
			W2BYTEMSK(REG_0064_MODD1, priv->lane_info.def_layout[19], REG_0064_MODD1_REG_FREE_CH19_SWAP);
			if ((priv->lane_info.sup_lanes == 40)|| (priv->lane_info.sup_lanes == 64)) {
				W2BYTEMSK(REG_0068_MODD1, priv->lane_info.def_layout[20], REG_0068_MODD1_REG_FREE_CH20_SWAP);
				W2BYTEMSK(REG_0068_MODD1, priv->lane_info.def_layout[21], REG_0068_MODD1_REG_FREE_CH21_SWAP);
				W2BYTEMSK(REG_006C_MODD1, priv->lane_info.def_layout[22], REG_006C_MODD1_REG_FREE_CH22_SWAP);
				W2BYTEMSK(REG_006C_MODD1, priv->lane_info.def_layout[23], REG_006C_MODD1_REG_FREE_CH23_SWAP);
				W2BYTEMSK(REG_0070_MODD1, priv->lane_info.def_layout[24], REG_0070_MODD1_REG_FREE_CH24_SWAP);
				W2BYTEMSK(REG_0070_MODD1, priv->lane_info.def_layout[25], REG_0070_MODD1_REG_FREE_CH25_SWAP);
				W2BYTEMSK(REG_0074_MODD1, priv->lane_info.def_layout[26], REG_0074_MODD1_REG_FREE_CH26_SWAP);
				W2BYTEMSK(REG_0074_MODD1, priv->lane_info.def_layout[27], REG_0074_MODD1_REG_FREE_CH27_SWAP);
				W2BYTEMSK(REG_0078_MODD1, priv->lane_info.def_layout[28], REG_0078_MODD1_REG_FREE_CH28_SWAP);
				W2BYTEMSK(REG_0078_MODD1, priv->lane_info.def_layout[29], REG_0078_MODD1_REG_FREE_CH29_SWAP);
				W2BYTEMSK(REG_007C_MODD1, priv->lane_info.def_layout[30], REG_007C_MODD1_REG_FREE_CH30_SWAP);
				W2BYTEMSK(REG_007C_MODD1, priv->lane_info.def_layout[31], REG_007C_MODD1_REG_FREE_CH31_SWAP);
				W2BYTEMSK(REG_0080_MODD1, priv->lane_info.def_layout[32], REG_0080_MODD1_REG_FREE_CH32_SWAP);
				W2BYTEMSK(REG_0080_MODD1, priv->lane_info.def_layout[33], REG_0080_MODD1_REG_FREE_CH33_SWAP);
				W2BYTEMSK(REG_0084_MODD1, priv->lane_info.def_layout[34], REG_0084_MODD1_REG_FREE_CH34_SWAP);
				W2BYTEMSK(REG_0084_MODD1, priv->lane_info.def_layout[35], REG_0084_MODD1_REG_FREE_CH35_SWAP);
				W2BYTEMSK(REG_0088_MODD1, priv->lane_info.def_layout[36], REG_0088_MODD1_REG_FREE_CH36_SWAP);
				W2BYTEMSK(REG_0088_MODD1, priv->lane_info.def_layout[37], REG_0088_MODD1_REG_FREE_CH37_SWAP);
				W2BYTEMSK(REG_008C_MODD1, priv->lane_info.def_layout[38], REG_008C_MODD1_REG_FREE_CH38_SWAP);
				W2BYTEMSK(REG_008C_MODD1, priv->lane_info.def_layout[39], REG_008C_MODD1_REG_FREE_CH39_SWAP);
			}
			if (priv->lane_info.sup_lanes == 64) {
				W2BYTEMSK(REG_0090_MODD1, priv->lane_info.def_layout[40], REG_0090_MODD1_REG_FREE_CH40_SWAP);
				W2BYTEMSK(REG_0090_MODD1, priv->lane_info.def_layout[41], REG_0090_MODD1_REG_FREE_CH41_SWAP);
				W2BYTEMSK(REG_0094_MODD1, priv->lane_info.def_layout[42], REG_0094_MODD1_REG_FREE_CH42_SWAP);
				W2BYTEMSK(REG_0094_MODD1, priv->lane_info.def_layout[43], REG_0094_MODD1_REG_FREE_CH43_SWAP);
				W2BYTEMSK(REG_0098_MODD1, priv->lane_info.def_layout[44], REG_0098_MODD1_REG_FREE_CH44_SWAP);
				W2BYTEMSK(REG_0098_MODD1, priv->lane_info.def_layout[45], REG_0098_MODD1_REG_FREE_CH45_SWAP);
				W2BYTEMSK(REG_009C_MODD1, priv->lane_info.def_layout[46], REG_009C_MODD1_REG_FREE_CH46_SWAP);
				W2BYTEMSK(REG_009C_MODD1, priv->lane_info.def_layout[47], REG_009C_MODD1_REG_FREE_CH47_SWAP);
				W2BYTEMSK(REG_00A0_MODD1, priv->lane_info.def_layout[48], REG_00A0_MODD1_REG_FREE_CH48_SWAP);
				W2BYTEMSK(REG_00A0_MODD1, priv->lane_info.def_layout[49], REG_00A0_MODD1_REG_FREE_CH49_SWAP);
				W2BYTEMSK(REG_00A4_MODD1, priv->lane_info.def_layout[50], REG_00A4_MODD1_REG_FREE_CH50_SWAP);
				W2BYTEMSK(REG_00A4_MODD1, priv->lane_info.def_layout[51], REG_00A4_MODD1_REG_FREE_CH51_SWAP);
				W2BYTEMSK(REG_00A8_MODD1, priv->lane_info.def_layout[52], REG_00A8_MODD1_REG_FREE_CH52_SWAP);
				W2BYTEMSK(REG_00A8_MODD1, priv->lane_info.def_layout[53], REG_00A8_MODD1_REG_FREE_CH53_SWAP);
				W2BYTEMSK(REG_00AC_MODD1, priv->lane_info.def_layout[54], REG_00AC_MODD1_REG_FREE_CH54_SWAP);
				W2BYTEMSK(REG_00AC_MODD1, priv->lane_info.def_layout[55], REG_00AC_MODD1_REG_FREE_CH55_SWAP);
				W2BYTEMSK(REG_00B0_MODD1, priv->lane_info.def_layout[56], REG_00B0_MODD1_REG_FREE_CH56_SWAP);
				W2BYTEMSK(REG_00B0_MODD1, priv->lane_info.def_layout[57], REG_00B0_MODD1_REG_FREE_CH57_SWAP);
				W2BYTEMSK(REG_00B4_MODD1, priv->lane_info.def_layout[58], REG_00B4_MODD1_REG_FREE_CH58_SWAP);
				W2BYTEMSK(REG_00B4_MODD1, priv->lane_info.def_layout[59], REG_00B4_MODD1_REG_FREE_CH59_SWAP);
				W2BYTEMSK(REG_00B8_MODD1, priv->lane_info.def_layout[60], REG_00B8_MODD1_REG_FREE_CH60_SWAP);
				W2BYTEMSK(REG_00B8_MODD1, priv->lane_info.def_layout[61], REG_00B8_MODD1_REG_FREE_CH61_SWAP);
				W2BYTEMSK(REG_00BC_MODD1, priv->lane_info.def_layout[62], REG_00BC_MODD1_REG_FREE_CH62_SWAP);
				W2BYTEMSK(REG_00BC_MODD1, priv->lane_info.def_layout[63], REG_00BC_MODD1_REG_FREE_CH63_SWAP);
			}
		}
	}
}

static void _vby1_64lane_def_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	switch (priv->div_sec) {
	case DIV_2:
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x1B1A, Fld(16,0,AC_FULLW10));//ch14-ch15
		W2BYTEMSK(REG_01C0_MODV12, 0x2120, Fld(16,0,AC_FULLW10));//ch16-ch17
		W2BYTEMSK(REG_01C4_MODV12, 0x2322, Fld(16,0,AC_FULLW10));//ch18-ch19
		W2BYTEMSK(REG_01C8_MODV12, 0x2928, Fld(16,0,AC_FULLW10));//ch20-ch21
		W2BYTEMSK(REG_01CC_MODV12, 0x2b2a, Fld(16,0,AC_FULLW10));//ch22-ch23
		W2BYTEMSK(REG_01D0_MODV12, 0x3130, Fld(16,0,AC_FULLW10));//ch24-ch25
		W2BYTEMSK(REG_01D4_MODV12, 0x3332, Fld(16,0,AC_FULLW10));//ch26-ch27
		W2BYTEMSK(REG_01D8_MODV12, 0x3938, Fld(16,0,AC_FULLW10));//ch28-ch29
		W2BYTEMSK(REG_01DC_MODV12, 0x3b3a, Fld(16,0,AC_FULLW10));//ch30-ch31
		W2BYTEMSK(REG_01A0_MODV13, 0x0504, Fld(16,0,AC_FULLW10));//ch32-ch33
		W2BYTEMSK(REG_01A4_MODV13, 0x0706, Fld(16,0,AC_FULLW10));//ch34-ch35
		W2BYTEMSK(REG_01A8_MODV13, 0x0d0c, Fld(16,0,AC_FULLW10));//ch36-ch37
		W2BYTEMSK(REG_01AC_MODV13, 0x0f0e, Fld(16,0,AC_FULLW10));//ch38-ch39
		W2BYTEMSK(REG_01B0_MODV13, 0x1514, Fld(16,0,AC_FULLW10));//ch40-ch41
		W2BYTEMSK(REG_01B4_MODV13, 0x1716, Fld(16,0,AC_FULLW10));//ch42-ch43
		W2BYTEMSK(REG_01B8_MODV13, 0x1d1c, Fld(16,0,AC_FULLW10));//ch44-ch45
		W2BYTEMSK(REG_01BC_MODV13, 0x1f1e, Fld(16,0,AC_FULLW10));//ch46-ch47
		W2BYTEMSK(REG_01C0_MODV13, 0x2524, Fld(16,0,AC_FULLW10));//ch48-ch49
		W2BYTEMSK(REG_01C4_MODV13, 0x2726, Fld(16,0,AC_FULLW10));//ch50-ch51
		W2BYTEMSK(REG_01C8_MODV13, 0x2d2c, Fld(16,0,AC_FULLW10));//ch52-ch53
		W2BYTEMSK(REG_01CC_MODV13, 0x2f2e, Fld(16,0,AC_FULLW10));//ch54-ch55
		W2BYTEMSK(REG_01D0_MODV13, 0x3534, Fld(16,0,AC_FULLW10));//ch56-ch57
		W2BYTEMSK(REG_01D4_MODV13, 0x3736, Fld(16,0,AC_FULLW10));//ch58-ch59
		W2BYTEMSK(REG_01D8_MODV13, 0x3d3c, Fld(16,0,AC_FULLW10));//ch60-ch61
		W2BYTEMSK(REG_01DC_MODV13, 0x3f3e, Fld(16,0,AC_FULLW10));//ch62-ch63
	break;
	case DIV_4:
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x2120, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x2928, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x3130, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x3938, Fld(16,0,AC_FULLW10));//ch14-ch15
		W2BYTEMSK(REG_01C0_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch16-ch17
		W2BYTEMSK(REG_01C4_MODV12, 0x0b0a, Fld(16,0,AC_FULLW10));//ch18-ch19
		W2BYTEMSK(REG_01C8_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch20-ch21
		W2BYTEMSK(REG_01CC_MODV12, 0x1b1a, Fld(16,0,AC_FULLW10));//ch22-ch23
		W2BYTEMSK(REG_01D0_MODV12, 0x2322, Fld(16,0,AC_FULLW10));//ch24-ch25
		W2BYTEMSK(REG_01D4_MODV12, 0x2b2a, Fld(16,0,AC_FULLW10));//ch26-ch27
		W2BYTEMSK(REG_01D8_MODV12, 0x3332, Fld(16,0,AC_FULLW10));//ch28-ch29
		W2BYTEMSK(REG_01DC_MODV12, 0x3b3a, Fld(16,0,AC_FULLW10));//ch30-ch31
		W2BYTEMSK(REG_01A0_MODV13, 0x0504, Fld(16,0,AC_FULLW10));//ch32-ch33
		W2BYTEMSK(REG_01A4_MODV13, 0x0d0c, Fld(16,0,AC_FULLW10));//ch34-ch35
		W2BYTEMSK(REG_01A8_MODV13, 0x1514, Fld(16,0,AC_FULLW10));//ch36-ch37
		W2BYTEMSK(REG_01AC_MODV13, 0x1d1c, Fld(16,0,AC_FULLW10));//ch38-ch39
		W2BYTEMSK(REG_01B0_MODV13, 0x2524, Fld(16,0,AC_FULLW10));//ch40-ch41
		W2BYTEMSK(REG_01B4_MODV13, 0x2d2c, Fld(16,0,AC_FULLW10));//ch42-ch43
		W2BYTEMSK(REG_01B8_MODV13, 0x3534, Fld(16,0,AC_FULLW10));//ch44-ch45
		W2BYTEMSK(REG_01BC_MODV13, 0x3d3c, Fld(16,0,AC_FULLW10));//ch46-ch47
		W2BYTEMSK(REG_01C0_MODV13, 0x0706, Fld(16,0,AC_FULLW10));//ch48-ch49
		W2BYTEMSK(REG_01C4_MODV13, 0x0f0e, Fld(16,0,AC_FULLW10));//ch50-ch51
		W2BYTEMSK(REG_01C8_MODV13, 0x1716, Fld(16,0,AC_FULLW10));//ch52-ch53
		W2BYTEMSK(REG_01CC_MODV13, 0x1f1e, Fld(16,0,AC_FULLW10));//ch54-ch55
		W2BYTEMSK(REG_01D0_MODV13, 0x2726, Fld(16,0,AC_FULLW10));//ch56-ch57
		W2BYTEMSK(REG_01D4_MODV13, 0x2f2e, Fld(16,0,AC_FULLW10));//ch58-ch59
		W2BYTEMSK(REG_01D8_MODV13, 0x3736, Fld(16,0,AC_FULLW10));//ch60-ch61
		W2BYTEMSK(REG_01DC_MODV13, 0x3f3e, Fld(16,0,AC_FULLW10));//ch62-ch63
	break;
	case DIV_8:
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x2120, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x3130, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x2322, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x3332, Fld(16,0,AC_FULLW10));//ch14-ch15
		W2BYTEMSK(REG_01C0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch16-ch17
		W2BYTEMSK(REG_01C4_MODV12, 0x1514, Fld(16,0,AC_FULLW10));//ch18-ch19
		W2BYTEMSK(REG_01C8_MODV12, 0x2524, Fld(16,0,AC_FULLW10));//ch20-ch21
		W2BYTEMSK(REG_01CC_MODV12, 0x3534, Fld(16,0,AC_FULLW10));//ch22-ch23
		W2BYTEMSK(REG_01D0_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch24-ch25
		W2BYTEMSK(REG_01D4_MODV12, 0x1716, Fld(16,0,AC_FULLW10));//ch26-ch27
		W2BYTEMSK(REG_01D8_MODV12, 0x2726, Fld(16,0,AC_FULLW10));//ch28-ch29
		W2BYTEMSK(REG_01DC_MODV12, 0x3736, Fld(16,0,AC_FULLW10));//ch30-ch31
		W2BYTEMSK(REG_01A0_MODV13, 0x0908, Fld(16,0,AC_FULLW10));//ch32-ch33
		W2BYTEMSK(REG_01A4_MODV13, 0x1918, Fld(16,0,AC_FULLW10));//ch34-ch35
		W2BYTEMSK(REG_01A8_MODV13, 0x2928, Fld(16,0,AC_FULLW10));//ch36-ch37
		W2BYTEMSK(REG_01AC_MODV13, 0x3938, Fld(16,0,AC_FULLW10));//ch38-ch39
		W2BYTEMSK(REG_01B0_MODV13, 0x0b0a, Fld(16,0,AC_FULLW10));//ch40-ch41
		W2BYTEMSK(REG_01B4_MODV13, 0x1b1a, Fld(16,0,AC_FULLW10));//ch42-ch43
		W2BYTEMSK(REG_01B8_MODV13, 0x2b2a, Fld(16,0,AC_FULLW10));//ch44-ch45
		W2BYTEMSK(REG_01BC_MODV13, 0x3b3a, Fld(16,0,AC_FULLW10));//ch46-ch47
		W2BYTEMSK(REG_01C0_MODV13, 0x0d0c, Fld(16,0,AC_FULLW10));//ch48-ch49
		W2BYTEMSK(REG_01C4_MODV13, 0x1d1c, Fld(16,0,AC_FULLW10));//ch50-ch51
		W2BYTEMSK(REG_01C8_MODV13, 0x2d2c, Fld(16,0,AC_FULLW10));//ch52-ch53
		W2BYTEMSK(REG_01CC_MODV13, 0x3d3c, Fld(16,0,AC_FULLW10));//ch54-ch55
		W2BYTEMSK(REG_01D0_MODV13, 0x0f0e, Fld(16,0,AC_FULLW10));//ch56-ch57
		W2BYTEMSK(REG_01D4_MODV13, 0x1f1e, Fld(16,0,AC_FULLW10));//ch58-ch59
		W2BYTEMSK(REG_01D8_MODV13, 0x2f2e, Fld(16,0,AC_FULLW10));//ch60-ch61
		W2BYTEMSK(REG_01DC_MODV13, 0x3f3e, Fld(16,0,AC_FULLW10));//ch62-ch63
	break;
	default:
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x2120, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x2928, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x3130, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x3938, Fld(16,0,AC_FULLW10));//ch14-ch15
		W2BYTEMSK(REG_01C0_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch16-ch17
		W2BYTEMSK(REG_01C4_MODV12, 0x0b0a, Fld(16,0,AC_FULLW10));//ch18-ch19
		W2BYTEMSK(REG_01C8_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch20-ch21
		W2BYTEMSK(REG_01CC_MODV12, 0x1b1a, Fld(16,0,AC_FULLW10));//ch22-ch23
		W2BYTEMSK(REG_01D0_MODV12, 0x2322, Fld(16,0,AC_FULLW10));//ch24-ch25
		W2BYTEMSK(REG_01D4_MODV12, 0x2b2a, Fld(16,0,AC_FULLW10));//ch26-ch27
		W2BYTEMSK(REG_01D8_MODV12, 0x3332, Fld(16,0,AC_FULLW10));//ch28-ch29
		W2BYTEMSK(REG_01DC_MODV12, 0x3b3a, Fld(16,0,AC_FULLW10));//ch30-ch31
		W2BYTEMSK(REG_01A0_MODV13, 0x0504, Fld(16,0,AC_FULLW10));//ch32-ch33
		W2BYTEMSK(REG_01A4_MODV13, 0x0d0c, Fld(16,0,AC_FULLW10));//ch34-ch35
		W2BYTEMSK(REG_01A8_MODV13, 0x1514, Fld(16,0,AC_FULLW10));//ch36-ch37
		W2BYTEMSK(REG_01AC_MODV13, 0x1d1c, Fld(16,0,AC_FULLW10));//ch38-ch39
		W2BYTEMSK(REG_01B0_MODV13, 0x2524, Fld(16,0,AC_FULLW10));//ch40-ch41
		W2BYTEMSK(REG_01B4_MODV13, 0x2d2c, Fld(16,0,AC_FULLW10));//ch42-ch43
		W2BYTEMSK(REG_01B8_MODV13, 0x3534, Fld(16,0,AC_FULLW10));//ch44-ch45
		W2BYTEMSK(REG_01BC_MODV13, 0x3d3c, Fld(16,0,AC_FULLW10));//ch46-ch47
		W2BYTEMSK(REG_01C0_MODV13, 0x0706, Fld(16,0,AC_FULLW10));//ch48-ch49
		W2BYTEMSK(REG_01C4_MODV13, 0x0f0e, Fld(16,0,AC_FULLW10));//ch50-ch51
		W2BYTEMSK(REG_01C8_MODV13, 0x1716, Fld(16,0,AC_FULLW10));//ch52-ch53
		W2BYTEMSK(REG_01CC_MODV13, 0x1f1e, Fld(16,0,AC_FULLW10));//ch54-ch55
		W2BYTEMSK(REG_01D0_MODV13, 0x2726, Fld(16,0,AC_FULLW10));//ch56-ch57
		W2BYTEMSK(REG_01D4_MODV13, 0x2f2e, Fld(16,0,AC_FULLW10));//ch58-ch59
		W2BYTEMSK(REG_01D8_MODV13, 0x3736, Fld(16,0,AC_FULLW10));//ch60-ch61
		W2BYTEMSK(REG_01DC_MODV13, 0x3f3e, Fld(16,0,AC_FULLW10));//ch62-ch63
	break;
	}
}

static void _vby1_40lane_def_free_swap(struct udevice *dev)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);
    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return;
    }

    if (priv->div_sec == 2) {
        W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
        W2BYTEMSK(REG_01A4_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch2-ch3
        W2BYTEMSK(REG_01A8_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch4-ch5
        W2BYTEMSK(REG_01AC_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch6-ch7
        W2BYTEMSK(REG_01B0_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch8-ch9
        W2BYTEMSK(REG_01B4_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch10-ch11
        W2BYTEMSK(REG_01B8_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch12-ch13
        W2BYTEMSK(REG_01BC_MODV12, 0x1B1A, Fld(16,0,AC_FULLW10));//ch14-ch15
        W2BYTEMSK(REG_01C0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch16-ch17
        W2BYTEMSK(REG_01C4_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch18-ch19
        W2BYTEMSK(REG_01C8_MODV12, 0x0D0C, Fld(16,0,AC_FULLW10));//ch20-ch21
        W2BYTEMSK(REG_01CC_MODV12, 0x0F0E, Fld(16,0,AC_FULLW10));//ch22-ch23
        W2BYTEMSK(REG_01D0_MODV12, 0x1514, Fld(16,0,AC_FULLW10));//ch24-ch25
        W2BYTEMSK(REG_01D4_MODV12, 0x1716, Fld(16,0,AC_FULLW10));//ch26-ch27
        W2BYTEMSK(REG_01D8_MODV12, 0x1D1C, Fld(16,0,AC_FULLW10));//ch28-ch29
        W2BYTEMSK(REG_01DC_MODV12, 0x1F1E, Fld(16,0,AC_FULLW10));//ch30-ch31
    }

    if (priv->div_sec == 4) {
        W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
        W2BYTEMSK(REG_01A4_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch2-ch3
        W2BYTEMSK(REG_01A8_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch4-ch5
        W2BYTEMSK(REG_01AC_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch6-ch7
        W2BYTEMSK(REG_01B0_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch8-ch9
        W2BYTEMSK(REG_01B4_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch10-ch11
        W2BYTEMSK(REG_01B8_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch12-ch13
        W2BYTEMSK(REG_01BC_MODV12, 0x1B1A, Fld(16,0,AC_FULLW10));//ch14-ch15
        W2BYTEMSK(REG_01C0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch16-ch17
        W2BYTEMSK(REG_01C4_MODV12, 0x0D0C, Fld(16,0,AC_FULLW10));//ch18-ch19
        W2BYTEMSK(REG_01C8_MODV12, 0x1514, Fld(16,0,AC_FULLW10));//ch20-ch21
        W2BYTEMSK(REG_01CC_MODV12, 0x1D1C, Fld(16,0,AC_FULLW10));//ch22-ch23
        W2BYTEMSK(REG_01D0_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch24-ch25
        W2BYTEMSK(REG_01D4_MODV12, 0x0F0E, Fld(16,0,AC_FULLW10));//ch26-ch27
        W2BYTEMSK(REG_01D8_MODV12, 0x1716, Fld(16,0,AC_FULLW10));//ch28-ch29
        W2BYTEMSK(REG_01DC_MODV12, 0x1F1E, Fld(16,0,AC_FULLW10));//ch30-ch31
    }

    W2BYTEMSK(REG_01A0_MODOSD2, 0x400, Fld(16,0,AC_FULLW10));//osd ch0-ch1
    W2BYTEMSK(REG_01A4_MODOSD2, 0x602, Fld(16,0,AC_FULLW10));//osd ch2-ch3
    W2BYTEMSK(REG_01A8_MODOSD2, 0x501, Fld(16,0,AC_FULLW10));//osd ch4-ch5
    W2BYTEMSK(REG_01AC_MODOSD2, 0x703, Fld(16,0,AC_FULLW10));//osd ch6-ch7

}

static void _vby1_32lane_def_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->div_sec == 2) {
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x1B1A, Fld(16,0,AC_FULLW10));//ch14-ch15
		W2BYTEMSK(REG_01C0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch16-ch17
		W2BYTEMSK(REG_01C4_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch18-ch19
		W2BYTEMSK(REG_01C8_MODV12, 0x0D0C, Fld(16,0,AC_FULLW10));//ch20-ch21
		W2BYTEMSK(REG_01CC_MODV12, 0x0F0E, Fld(16,0,AC_FULLW10));//ch22-ch23
		W2BYTEMSK(REG_01D0_MODV12, 0x1514, Fld(16,0,AC_FULLW10));//ch24-ch25
		W2BYTEMSK(REG_01D4_MODV12, 0x1716, Fld(16,0,AC_FULLW10));//ch26-ch27
		W2BYTEMSK(REG_01D8_MODV12, 0x1D1C, Fld(16,0,AC_FULLW10));//ch28-ch29
		W2BYTEMSK(REG_01DC_MODV12, 0x1F1E, Fld(16,0,AC_FULLW10));//ch30-ch31
	}

	if (priv->div_sec == 4) {
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x1110, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x1918, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x1312, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x1B1A, Fld(16,0,AC_FULLW10));//ch14-ch15
		W2BYTEMSK(REG_01C0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch16-ch17
		W2BYTEMSK(REG_01C4_MODV12, 0x0D0C, Fld(16,0,AC_FULLW10));//ch18-ch19
		W2BYTEMSK(REG_01C8_MODV12, 0x1514, Fld(16,0,AC_FULLW10));//ch20-ch21
		W2BYTEMSK(REG_01CC_MODV12, 0x1D1C, Fld(16,0,AC_FULLW10));//ch22-ch23
		W2BYTEMSK(REG_01D0_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch24-ch25
		W2BYTEMSK(REG_01D4_MODV12, 0x0F0E, Fld(16,0,AC_FULLW10));//ch26-ch27
		W2BYTEMSK(REG_01D8_MODV12, 0x1716, Fld(16,0,AC_FULLW10));//ch28-ch29
		W2BYTEMSK(REG_01DC_MODV12, 0x1F1E, Fld(16,0,AC_FULLW10));//ch30-ch31
	}

}

static void _vby1_16lane_def_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->div_sec == 2) {
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x0D0C, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x0F0E, Fld(16,0,AC_FULLW10));//ch14-ch15
	}
	if (priv->div_sec == 4) {
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0908, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x0B0A, Fld(16,0,AC_FULLW10));//ch6-ch7
		W2BYTEMSK(REG_01B0_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch8-ch9
		W2BYTEMSK(REG_01B4_MODV12, 0x0D0C, Fld(16,0,AC_FULLW10));//ch10-ch11
		W2BYTEMSK(REG_01B8_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch12-ch13
		W2BYTEMSK(REG_01BC_MODV12, 0x0F0E, Fld(16,0,AC_FULLW10));//ch14-ch15
	}

}

static void _vby1_8lane_def_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	// 4K60Hz 8lane no need to change laneorder based on div_sec
	if (priv->div_sec) {
		W2BYTEMSK(REG_01A0_MODV12, 0x0100, Fld(16,0,AC_FULLW10));//ch0-ch1
		W2BYTEMSK(REG_01A4_MODV12, 0x0302, Fld(16,0,AC_FULLW10));//ch2-ch3
		W2BYTEMSK(REG_01A8_MODV12, 0x0504, Fld(16,0,AC_FULLW10));//ch4-ch5
		W2BYTEMSK(REG_01AC_MODV12, 0x0706, Fld(16,0,AC_FULLW10));//ch6-ch7
	}
}


static void _usr_def_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->linktype == E_LINK_VB1) {
		W2BYTEMSK(REG_01A0_MODV12, priv->lane_info.lane_order[0], REG_01A0_MODV12_REG_VBY1_SWAP_CH00);
		W2BYTEMSK(REG_01A0_MODV12, priv->lane_info.lane_order[1], REG_01A0_MODV12_REG_VBY1_SWAP_CH01);

		W2BYTEMSK(REG_01A4_MODV12, priv->lane_info.lane_order[2], REG_01A4_MODV12_REG_VBY1_SWAP_CH02);
		W2BYTEMSK(REG_01A4_MODV12, priv->lane_info.lane_order[3], REG_01A4_MODV12_REG_VBY1_SWAP_CH03);

		W2BYTEMSK(REG_01A8_MODV12, priv->lane_info.lane_order[4], REG_01A8_MODV12_REG_VBY1_SWAP_CH04);
		W2BYTEMSK(REG_01A8_MODV12, priv->lane_info.lane_order[5], REG_01A8_MODV12_REG_VBY1_SWAP_CH05);

		W2BYTEMSK(REG_01AC_MODV12, priv->lane_info.lane_order[6], REG_01AC_MODV12_REG_VBY1_SWAP_CH06);
		W2BYTEMSK(REG_01AC_MODV12, priv->lane_info.lane_order[7], REG_01AC_MODV12_REG_VBY1_SWAP_CH07);

		W2BYTEMSK(REG_01B0_MODV12, priv->lane_info.lane_order[8], REG_01B0_MODV12_REG_VBY1_SWAP_CH08);
		W2BYTEMSK(REG_01B0_MODV12, priv->lane_info.lane_order[9], REG_01B0_MODV12_REG_VBY1_SWAP_CH09);

		W2BYTEMSK(REG_01B4_MODV12, priv->lane_info.lane_order[10], REG_01B4_MODV12_REG_VBY1_SWAP_CH10);
		W2BYTEMSK(REG_01B4_MODV12, priv->lane_info.lane_order[11], REG_01B4_MODV12_REG_VBY1_SWAP_CH11);
		W2BYTEMSK(REG_01B8_MODV12, priv->lane_info.lane_order[12], REG_01B8_MODV12_REG_VBY1_SWAP_CH12);
		W2BYTEMSK(REG_01B8_MODV12, priv->lane_info.lane_order[13], REG_01B8_MODV12_REG_VBY1_SWAP_CH13);
		W2BYTEMSK(REG_01BC_MODV12, priv->lane_info.lane_order[14], REG_01BC_MODV12_REG_VBY1_SWAP_CH14);
		W2BYTEMSK(REG_01BC_MODV12, priv->lane_info.lane_order[15], REG_01BC_MODV12_REG_VBY1_SWAP_CH15);
		W2BYTEMSK(REG_01C0_MODV12, priv->lane_info.lane_order[16], REG_01C0_MODV12_REG_VBY1_SWAP_CH16);
		W2BYTEMSK(REG_01C0_MODV12, priv->lane_info.lane_order[17], REG_01C0_MODV12_REG_VBY1_SWAP_CH17);
		W2BYTEMSK(REG_01C4_MODV12, priv->lane_info.lane_order[18], REG_01C4_MODV12_REG_VBY1_SWAP_CH18);
		W2BYTEMSK(REG_01C4_MODV12, priv->lane_info.lane_order[19], REG_01C4_MODV12_REG_VBY1_SWAP_CH19);

		W2BYTEMSK(REG_01C8_MODV12, priv->lane_info.lane_order[20], REG_01C8_MODV12_REG_VBY1_SWAP_CH20);
		W2BYTEMSK(REG_01C8_MODV12, priv->lane_info.lane_order[21], REG_01C8_MODV12_REG_VBY1_SWAP_CH21);
		W2BYTEMSK(REG_01CC_MODV12, priv->lane_info.lane_order[22], REG_01CC_MODV12_REG_VBY1_SWAP_CH22);
		W2BYTEMSK(REG_01CC_MODV12, priv->lane_info.lane_order[23], REG_01CC_MODV12_REG_VBY1_SWAP_CH23);

		W2BYTEMSK(REG_01D0_MODV12, priv->lane_info.lane_order[24], REG_01D0_MODV12_REG_VBY1_SWAP_CH24);
		W2BYTEMSK(REG_01D0_MODV12, priv->lane_info.lane_order[25], REG_01D0_MODV12_REG_VBY1_SWAP_CH25);
		W2BYTEMSK(REG_01D4_MODV12, priv->lane_info.lane_order[26], REG_01D4_MODV12_REG_VBY1_SWAP_CH26);
		W2BYTEMSK(REG_01D4_MODV12, priv->lane_info.lane_order[27], REG_01D4_MODV12_REG_VBY1_SWAP_CH27);
		W2BYTEMSK(REG_01D8_MODV12, priv->lane_info.lane_order[28], REG_01D8_MODV12_REG_VBY1_SWAP_CH28);
		W2BYTEMSK(REG_01D8_MODV12, priv->lane_info.lane_order[29], REG_01D8_MODV12_REG_VBY1_SWAP_CH29);
		W2BYTEMSK(REG_01DC_MODV12, priv->lane_info.lane_order[30], REG_01DC_MODV12_REG_VBY1_SWAP_CH30);
		W2BYTEMSK(REG_01DC_MODV12, priv->lane_info.lane_order[31], REG_01DC_MODV12_REG_VBY1_SWAP_CH31);

		W2BYTEMSK(REG_01A0_MODOSD2, priv->lane_info.lane_order[32], REG_01A0_MODOSD2_REG_VBY1_SWAP_CH00);
		W2BYTEMSK(REG_01A0_MODOSD2, priv->lane_info.lane_order[33], REG_01A0_MODOSD2_REG_VBY1_SWAP_CH01);
		W2BYTEMSK(REG_01A4_MODOSD2, priv->lane_info.lane_order[34], REG_01A4_MODOSD2_REG_VBY1_SWAP_CH02);
		W2BYTEMSK(REG_01A4_MODOSD2, priv->lane_info.lane_order[35], REG_01A4_MODOSD2_REG_VBY1_SWAP_CH03);
		W2BYTEMSK(REG_01A8_MODOSD2, priv->lane_info.lane_order[36], REG_01A8_MODOSD2_REG_VBY1_SWAP_CH04);
		W2BYTEMSK(REG_01A8_MODOSD2, priv->lane_info.lane_order[37], REG_01A8_MODOSD2_REG_VBY1_SWAP_CH05);
		W2BYTEMSK(REG_01AC_MODOSD2, priv->lane_info.lane_order[38], REG_01AC_MODOSD2_REG_VBY1_SWAP_CH06);
		W2BYTEMSK(REG_01AC_MODOSD2, priv->lane_info.lane_order[39], REG_01AC_MODOSD2_REG_VBY1_SWAP_CH07);


	}
}

static void _default_free_swap(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->linktype != E_LINK_VB1) {
		printf("[%s] only support E_LINK_VB1\n", __func__);
		return;
	}

	switch (priv->lane_info.ctrl_lanes) {
	case VBO_USE_LANE_NUM_64:
		_vby1_64lane_def_free_swap(dev);
		break;
	case VBO_USE_LANE_NUM_40:
		_vby1_40lane_def_free_swap(dev);
		break;
	case VBO_USE_LANE_NUM_32:
		_vby1_32lane_def_free_swap(dev);
		break;
	case VBO_USE_LANE_NUM_16:
		_vby1_16lane_def_free_swap(dev);
		break;
	case VBO_USE_LANE_NUM_8:
		_vby1_8lane_def_free_swap(dev);
		break;
	default:
		_vby1_32lane_def_free_swap(dev);
		break;
	}
}

static void _setAll_pe_value(u16 value)
{
	value = value&0xFFFF;

	W2BYTEMSK(REG_0080_MODA1, value, Fld(16,0,AC_FULLW10));//ch0-ch1
	W2BYTEMSK(REG_0084_MODA1, value, Fld(16,0,AC_FULLW10));//ch2-ch3
	W2BYTEMSK(REG_0088_MODA1, value, Fld(16,0,AC_FULLW10));//ch4-ch5
	W2BYTEMSK(REG_008C_MODA1, value, Fld(16,0,AC_FULLW10));//ch6-ch7
	W2BYTEMSK(REG_0090_MODA1, value, Fld(16,0,AC_FULLW10));//ch8-ch9
	W2BYTEMSK(REG_0094_MODA1, value, Fld(16,0,AC_FULLW10));//ch10-ch11
	W2BYTEMSK(REG_0098_MODA1, value, Fld(16,0,AC_FULLW10));//ch12-ch13
	W2BYTEMSK(REG_009C_MODA1, value, Fld(16,0,AC_FULLW10));//ch14-ch15
	W2BYTEMSK(REG_00A0_MODA1, value, Fld(16,0,AC_FULLW10));//ch16-ch17
	W2BYTEMSK(REG_00A4_MODA1, value, Fld(16,0,AC_FULLW10));//ch18-ch19
	W2BYTEMSK(REG_0080_MODA2, value, Fld(16,0,AC_FULLW10));//ch20-ch21
	W2BYTEMSK(REG_0084_MODA2, value, Fld(16,0,AC_FULLW10));//ch22-ch23
	W2BYTEMSK(REG_0088_MODA2, value, Fld(16,0,AC_FULLW10));//ch24-ch25
	W2BYTEMSK(REG_008C_MODA2, value, Fld(16,0,AC_FULLW10));//ch26-ch27
	W2BYTEMSK(REG_0090_MODA2, value, Fld(16,0,AC_FULLW10));//ch28-ch29
	W2BYTEMSK(REG_0094_MODA2, value, Fld(16,0,AC_FULLW10));//ch30-ch31

	W2BYTEMSK(REG_0098_MODA2, value, Fld(16,0,AC_FULLW10));//ch32-ch33
	W2BYTEMSK(REG_009C_MODA2, value, Fld(16,0,AC_FULLW10));//ch34-ch35
	W2BYTEMSK(REG_00A0_MODA2, value, Fld(16,0,AC_FULLW10));//ch36-ch37
	W2BYTEMSK(REG_00A4_MODA2, value, Fld(16,0,AC_FULLW10));//ch38-ch39

	//W2BYTEMSK(REG_0080_MODA3, value, Fld(16,0,AC_FULLW10));//ch40-ch41
	//W2BYTEMSK(REG_0084_MODA3, value, Fld(16,0,AC_FULLW10));//ch42-ch43
	//W2BYTEMSK(REG_0088_MODA3, value, Fld(16,0,AC_FULLW10));//ch44-ch45
	//W2BYTEMSK(REG_008C_MODA3, value, Fld(16,0,AC_FULLW10));//ch46-ch47
	//W2BYTEMSK(REG_0090_MODA3, value, Fld(16,0,AC_FULLW10));//ch48-ch49
	//W2BYTEMSK(REG_0094_MODA3, value, Fld(16,0,AC_FULLW10));//ch50-ch51
	//W2BYTEMSK(REG_0098_MODA3, value, Fld(16,0,AC_FULLW10));//ch52-ch53
	//W2BYTEMSK(REG_009C_MODA3, value, Fld(16,0,AC_FULLW10));//ch54-ch55
	//W2BYTEMSK(REG_00A0_MODA3, value, Fld(16,0,AC_FULLW10));//ch56-ch57
	//W2BYTEMSK(REG_00A4_MODA3, value, Fld(16,0,AC_FULLW10));//ch58-ch59
	//W2BYTEMSK(REG_0080_MODA4, value, Fld(16,0,AC_FULLW10));//ch60-ch61
	//W2BYTEMSK(REG_0084_MODA4, value, Fld(16,0,AC_FULLW10));//ch62-ch63
}

void _vby1_lane_order(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	//ping mapping free swap
	_pin_mapping_free_swap(dev);

	//read lane order from device tree
	if (priv->linktype != E_LINK_NONE) {
		if (priv->out_timing == E_FHD_60HZ)
			W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		else if (priv->out_timing == E_FHD_120HZ)
			W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		else if (priv->out_timing == E_4K2K_60HZ ||
			 priv->out_timing == E_4K1K_120HZ)
			W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		else if (priv->out_timing == E_4K2K_120HZ ||
			priv->out_timing == E_4K2K_144HZ ||
			priv->out_timing == E_4K1K_240HZ ||
			priv->out_timing == E_5K2K_60HZ)
			W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		else if ((priv->out_timing == E_8K4K_60HZ || priv->out_timing == E_5K2K_120HZ) &&
			 priv->out_format == E_OUTPUT_YUV422)
			W2BYTEMSK(REG_0008_MODV12, 0x0, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		else if (priv->out_timing == E_8K4K_60HZ || priv->out_timing == E_5K2K_120HZ) {
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_47_32);
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		} else if (priv->out_timing == E_8K4K_120HZ) {
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_63_48);
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_47_32);
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		} else if (priv->out_timing == E_8K4K_144HZ) {
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_63_48);
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_47_32);
			W2BYTEMSK(REG_0008_MODV12, 0x1, REG_0008_MODV12_REG_VBY1_16CH_CKEN_31_16);
		} else {
			debug("[%s] OUTPUT TIMING Not Support\n", __func__);
		}
		debug("[%s] User defined lane order = %d\n", __func__, priv->lane_info.usr_defined);

		if (priv->lane_info.usr_defined == 1)
			_usr_def_free_swap(dev);
		else
			_default_free_swap(dev);

	}

#ifdef CONFIG_HAPS
       //polarity , ti mode
       W2BYTEMSK(REG_00E0_MODD1, 0x2800, Fld(16,0,AC_FULLW10));

       //free swap for a/b swap
       W2BYTEMSK(REG_0040_MODD1, 0x0706, Fld(16,0,AC_FULLW10));
       W2BYTEMSK(REG_0044_MODD1, 0x0908, Fld(16,0,AC_FULLW10));
       W2BYTEMSK(REG_0048_MODD1, 0x0B0A, Fld(16,0,AC_FULLW10));
       W2BYTEMSK(REG_004C_MODD1, 0x0100, Fld(16,0,AC_FULLW10));
       W2BYTEMSK(REG_0050_MODD1, 0x0302, Fld(16,0,AC_FULLW10));
       W2BYTEMSK(REG_0054_MODD1, 0x0504, Fld(16,0,AC_FULLW10));
#endif

}

void _vby1_extv_lane_order(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->div_sec == 1) {
		if (priv->lanes == VBO_USE_LANE_NUM_16) {
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01A0_MODV22_REG_VBY1_SWAP_CH00);
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01A0_MODV22_REG_VBY1_SWAP_CH01);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01A4_MODV22_REG_VBY1_SWAP_CH02);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01A4_MODV22_REG_VBY1_SWAP_CH03);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01A8_MODV22_REG_VBY1_SWAP_CH04);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01A8_MODV22_REG_VBY1_SWAP_CH05);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01AC_MODV22_REG_VBY1_SWAP_CH06);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01AC_MODV22_REG_VBY1_SWAP_CH07);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE8, REG_01B0_MODV22_REG_VBY1_SWAP_CH08);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE9, REG_01B0_MODV22_REG_VBY1_SWAP_CH09);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE10, REG_01B4_MODV22_REG_VBY1_SWAP_CH10);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE11, REG_01B4_MODV22_REG_VBY1_SWAP_CH11);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE12, REG_01B8_MODV22_REG_VBY1_SWAP_CH12);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE13, REG_01B8_MODV22_REG_VBY1_SWAP_CH13);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE14, REG_01BC_MODV22_REG_VBY1_SWAP_CH14);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE15, REG_01BC_MODV22_REG_VBY1_SWAP_CH15);
		}
		else {
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01A0_MODV22_REG_VBY1_SWAP_CH00);
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01A0_MODV22_REG_VBY1_SWAP_CH01);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01A4_MODV22_REG_VBY1_SWAP_CH02);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01A4_MODV22_REG_VBY1_SWAP_CH03);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01A8_MODV22_REG_VBY1_SWAP_CH04);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01A8_MODV22_REG_VBY1_SWAP_CH05);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01AC_MODV22_REG_VBY1_SWAP_CH06);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01AC_MODV22_REG_VBY1_SWAP_CH07);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01B0_MODV22_REG_VBY1_SWAP_CH08);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01B0_MODV22_REG_VBY1_SWAP_CH09);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01B4_MODV22_REG_VBY1_SWAP_CH10);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01B4_MODV22_REG_VBY1_SWAP_CH11);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01B8_MODV22_REG_VBY1_SWAP_CH12);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01B8_MODV22_REG_VBY1_SWAP_CH13);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01BC_MODV22_REG_VBY1_SWAP_CH14);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01BC_MODV22_REG_VBY1_SWAP_CH15);
		}
	} else if (priv->div_sec == 2) {
		if (priv->lanes == VBO_USE_LANE_NUM_16) {
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01A0_MODV22_REG_VBY1_SWAP_CH00);
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01A0_MODV22_REG_VBY1_SWAP_CH01);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01A4_MODV22_REG_VBY1_SWAP_CH02);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01A4_MODV22_REG_VBY1_SWAP_CH03);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE8, REG_01A8_MODV22_REG_VBY1_SWAP_CH04);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE9, REG_01A8_MODV22_REG_VBY1_SWAP_CH05);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE10, REG_01AC_MODV22_REG_VBY1_SWAP_CH06);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE11, REG_01AC_MODV22_REG_VBY1_SWAP_CH07);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01B0_MODV22_REG_VBY1_SWAP_CH08);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01B0_MODV22_REG_VBY1_SWAP_CH09);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01B4_MODV22_REG_VBY1_SWAP_CH10);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01B4_MODV22_REG_VBY1_SWAP_CH11);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE12, REG_01B8_MODV22_REG_VBY1_SWAP_CH12);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE13, REG_01B8_MODV22_REG_VBY1_SWAP_CH13);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE14, REG_01BC_MODV22_REG_VBY1_SWAP_CH14);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE15, REG_01BC_MODV22_REG_VBY1_SWAP_CH15);
		}
		else {
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01A0_MODV22_REG_VBY1_SWAP_CH00);
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01A0_MODV22_REG_VBY1_SWAP_CH01);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01A4_MODV22_REG_VBY1_SWAP_CH02);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01A4_MODV22_REG_VBY1_SWAP_CH03);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01A8_MODV22_REG_VBY1_SWAP_CH04);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01A8_MODV22_REG_VBY1_SWAP_CH05);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01AC_MODV22_REG_VBY1_SWAP_CH06);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01AC_MODV22_REG_VBY1_SWAP_CH07);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01B0_MODV22_REG_VBY1_SWAP_CH08);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01B0_MODV22_REG_VBY1_SWAP_CH09);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01B4_MODV22_REG_VBY1_SWAP_CH10);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01B4_MODV22_REG_VBY1_SWAP_CH11);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01B8_MODV22_REG_VBY1_SWAP_CH12);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01B8_MODV22_REG_VBY1_SWAP_CH13);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01BC_MODV22_REG_VBY1_SWAP_CH14);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01BC_MODV22_REG_VBY1_SWAP_CH15);
		}
	} else if (priv->div_sec == 4) {
		if (priv->lanes == VBO_USE_LANE_NUM_16) {
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE0, REG_01A0_MODV22_REG_VBY1_SWAP_CH00);
			W2BYTEMSK(REG_01A0_MODV22, E_BOOT_PNL_OUTPUT_LANE1, REG_01A0_MODV22_REG_VBY1_SWAP_CH01);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE8, REG_01A4_MODV22_REG_VBY1_SWAP_CH02);
			W2BYTEMSK(REG_01A4_MODV22, E_BOOT_PNL_OUTPUT_LANE9, REG_01A4_MODV22_REG_VBY1_SWAP_CH03);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE2, REG_01A8_MODV22_REG_VBY1_SWAP_CH04);
			W2BYTEMSK(REG_01A8_MODV22, E_BOOT_PNL_OUTPUT_LANE3, REG_01A8_MODV22_REG_VBY1_SWAP_CH05);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE10, REG_01AC_MODV22_REG_VBY1_SWAP_CH06);
			W2BYTEMSK(REG_01AC_MODV22, E_BOOT_PNL_OUTPUT_LANE11, REG_01AC_MODV22_REG_VBY1_SWAP_CH07);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE4, REG_01B0_MODV22_REG_VBY1_SWAP_CH08);
			W2BYTEMSK(REG_01B0_MODV22, E_BOOT_PNL_OUTPUT_LANE5, REG_01B0_MODV22_REG_VBY1_SWAP_CH09);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE12, REG_01B4_MODV22_REG_VBY1_SWAP_CH10);
			W2BYTEMSK(REG_01B4_MODV22, E_BOOT_PNL_OUTPUT_LANE13, REG_01B4_MODV22_REG_VBY1_SWAP_CH11);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE6, REG_01B8_MODV22_REG_VBY1_SWAP_CH12);
			W2BYTEMSK(REG_01B8_MODV22, E_BOOT_PNL_OUTPUT_LANE7, REG_01B8_MODV22_REG_VBY1_SWAP_CH13);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE14, REG_01BC_MODV22_REG_VBY1_SWAP_CH14);
			W2BYTEMSK(REG_01BC_MODV22, E_BOOT_PNL_OUTPUT_LANE15, REG_01BC_MODV22_REG_VBY1_SWAP_CH15);
		}
	} else {
		debug("[%s] Unsupport MFT mode\n", __func__);
	}
}
#ifdef CONFIG_HAPS

static void _hfrc_setting_for_HAPS(void)
{
	// Bank_a02f_fa: frc_haps
	//wriu -w 0xa02f02 0x0898 // tg_htt      = 16'h898, 16'd2200
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x4, 0x898, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f04 0x0000 // tg_hs_st    = 16'h000
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x8, 0x0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f06 0x000a // tg_hs_end   = 16'h00a
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xC, 0xA, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f08 0x0070 // tg_hfde_st  = 16'h070, 16'd112
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x10, 0x70, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f0a 0x042F // tg_hfde_end = 16'h42F, 16'd1071
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x14, 0x42F, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f0c 0x0070 // tg_hde_st   = 16'h070, 16'd112
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x18, 0x70, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f0e 0x042F // tg_hde_end  = 16'h42F, 16'd1071
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x1C, 0x42F, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f10 0x0465 // tg_vtt      = 16'h465, 16'd1125
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x20, 0x465, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f12 0x0000 // tg_vs_st    = 16'h000
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x24, 0x0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f14 0x0006 // tg_vs_end   = 16'h006
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x28, 0x6, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f16 0x0009 // tg_vfde_st  = 16'h9,   16'd9
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x2C, 0x9, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f18 0x0440 // tg_vfde_end = 16'h440, 16'd1088
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x30, 0x440, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f1a 0x0009 // tg_vde_st   = 16'h9,   16'd9
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x34, 0x9, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f1c 0x0440 // tg_vde_end  = 16'h440, 16'd1088
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x38, 0x440, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f24 0x0002 // tg_frc_vs_st   = 16'h002
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x48, 0x2, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f26 0x000a // tg_frc_vs_end  = 16'h00a
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0x4C, 0xA, Fld(16,0,AC_FULLW10));

	//wriu -w 0xa02fAE 0x0001 // pure_color_en[12], ip_patgen_en[4], op_patgen_en[0]

	//wriu -w 0xa02f64 0x0800 // scmi_size	= 20'h 70800 (1280*720/2)
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xC8, 0x800, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f66 0x0007 // scmi_size	= 20'h 70800 (1280*720/2)
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xCC, 0x7, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f68 0x03c0 // lb_size	= 12'h 3c0   (960)
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xD0, 0x3C0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f6a 0x0800 // reg_2pto1p, reg1pto2p, fake444, 42to44_mode[1:0] = 16'h0800
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xD4, 0x800, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f76 0x0280 // scmi_hsize	= 12'h 280   (640)
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xEC, 0x280, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f78 0x0780 // ip_hsize	= 12'h 780   (1920)
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xF0, 0x780, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f7a 0x03c0 // op_hsize	= 12'h 3c0   (960)
	W2BYTEMSK(REG_HFRC_HAPS_BASE+0xF4, 0x3C0, Fld(16,0,AC_FULLW10));


	//Bank_a02f_fb: frc_haps_hvsp_ip
	//wriu -w 0xa02f0e 0x0000 // reg_scale_factor_ho	= 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0x1C, 0x0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f10 0x0130 // reg_scale_ho_en=1, reg_scale_factor_ho  = 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0x20, 0x130, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f12 0x0000 // reg_scale_factor_ve	= 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0x24, 0x0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f14 0x0130 // reg_scale_ve_en=1, reg_scale_factor_ve  = 24'h300000
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0x28, 0x130, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f16 0x42c2 // op_mode
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0x2C, 0x42C2, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f50 0x8F00 // reg_h_size_usr_md[15] = 1'd1 , 1'd0, reg_h_size[13:0] = 14'hF00(3840)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0xA0, 0x8F00, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f52 0x8870 // reg_v_size_usr_md[15] = 1'd1 , 1'd0, reg_v_size[13:0] = 14'h870(2160)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0xA4, 0x8870, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f54 0x0500 // reg_scl_h_size = 13'h0500 (1280)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0xA8, 0x500, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f56 0x02d0 // reg_scl_v_size = 13'h02d0 (720)
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0xAC, 0x2D0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02fc0 0x0000 // reg_bypass = 0
	W2BYTEMSK(REG_HFRC_HVSP_IP_BASE+0x180, 0x0, Fld(16,0,AC_FULLW10));


	//Bank_a02f_f4: frc_haps_hvsp_op
	//wriu -w 0xa02f0e 0xaaaa // reg_scale_factor_ho	= 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0x1C, 0xAAAA, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f10 0x010a // reg_scale_ho_en=1, reg_scale_factor_ho  = 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0x20, 0x10A, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f12 0xaaaa // reg_scale_factor_ve	= 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0x24, 0xAAAA, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f14 0x010a // reg_scale_ve_en=1, reg_scale_factor_ve  = 24'h0AAAAA
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0x28, 0x10A, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f16 0x42c2 // op_mode
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0x2C, 0x42C2, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f50 0x8500 // reg_h_size_usr_md[15] = 1'd1 , 1'd0, reg_h_size[13:0] = 14'h500(1280)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0xA0, 0x8500, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f52 0x82d0 // reg_v_size_usr_md[15] = 1'd1 , 1'd0, reg_v_size[13:0] = 14'h2d0(720)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0xA4, 0x82D0, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f54 0x0780 // reg_scl_h_size = 13'h0780 (1920)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0xA8, 0x780, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02f56 0x0438 // reg_scl_v_size = 13'h0438 (1080)
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0xAC, 0x438, Fld(16,0,AC_FULLW10));
	//wriu -w 0xa02fc0 0x0000 // reg_bypass = 0utt
	W2BYTEMSK(REG_HFRC_HVSP_OP_BASE+0x180, 0x0, Fld(16,0,AC_FULLW10));

}

#if 0
static void _mod_tgen_setting_for_HAPS(void)
{
	//output 4k timing
	W2BYTEMSK(REG_01C0_MODV11, 0x898, REG_01C0_MODV11_REG_TGEN_HTT);
	W2BYTEMSK(REG_01C4_MODV11, 0xC, REG_01C4_MODV11_REG_TGEN_HSYNC_WIDTH);
	W2BYTEMSK(REG_01C8_MODV11, 0x3C, REG_01C8_MODV11_REG_TGEN_HDE_ST);
	W2BYTEMSK(REG_01CC_MODV11, 0x780, REG_01CC_MODV11_REG_TGEN_HDE_WIDTH);
	W2BYTEMSK(REG_01D0_MODV11, 0x465, REG_01D0_MODV11_REG_TGEN_VTT);
	W2BYTEMSK(REG_01D4_MODV11, 0x2, REG_01D4_MODV11_REG_TGEN_VSYNC_WIDTH);
	W2BYTEMSK(REG_01D8_MODV11, 0x6, REG_01D8_MODV11_REG_TGEN_VDE_ST);
	W2BYTEMSK(REG_01DC_MODV11, 0x438, REG_01DC_MODV11_REG_TGEN_VDE_WIDTH);
	W2BYTEMSK(REG_01E0_MODV11, 0x0, Fld(16,0,AC_FULLW10));

	//mod test
	//W2BYTEMSK(REG_0180_MODV11, 0x1, REG_0180_MODV11_REG_TEST_MODE); // mod pattern enable
	W2BYTEMSK(REG_0180_MODV11, 0x2, REG_0180_MODV11_REG_TEST_ENGINE);

	W2BYTEMSK(REG_0184_MODV11, 0x1, REG_0184_MODV11_REG_TEST_H_LINE_ST);
	W2BYTEMSK(REG_0188_MODV11, 0x1DFE, REG_0188_MODV11_REG_TEST_H_LINE_END);

	W2BYTEMSK(REG_018C_MODV11, 0x1, REG_018C_MODV11_REG_TEST_V_LINE_ST);
	W2BYTEMSK(REG_0190_MODV11, 0x6, REG_0190_MODV11_REG_TEST_V_LINE_END);

	W2BYTEMSK(REG_0194_MODV11, 0, REG_0194_MODV11_REG_TEST_COLOR_A);
	W2BYTEMSK(REG_0198_MODV11, 0, REG_0198_MODV11_REG_TEST_COLOR_R);
	W2BYTEMSK(REG_019C_MODV11, 0xFFF, REG_019C_MODV11_REG_TEST_COLOR_G);
	W2BYTEMSK(REG_01A0_MODV11, 0xFFF, REG_01A0_MODV11_REG_TEST_COLOR_B);

	W2BYTEMSK(REG_01A4_MODV11, 0, REG_01A4_MODV11_REG_TEST2_COLOR_A);
	W2BYTEMSK(REG_01A8_MODV11, 0x0155, REG_01A8_MODV11_REG_TEST2_COLOR_R);
	W2BYTEMSK(REG_01AC_MODV11, 0x02BC, REG_01AC_MODV11_REG_TEST2_COLOR_G);
	W2BYTEMSK(REG_01B0_MODV11, 0x038A, REG_01B0_MODV11_REG_TEST2_COLOR_B);

}
#endif
#endif

static void _vby1_set_byte_mode(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	en_vbo_bytemode vbo_byte = E_VBO_NO_LINK;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->linktype != E_LINK_VB1)
		return;

	vbo_byte = priv->vbo_byte;

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
		if (vbo_byte == E_VBO_5BYTE_MODE) {
			// 5 byte mode
			W2BYTEMSK(REG_0188_MODV12, 1, REG_0188_MODV12_REG_VBY1_BYTE_MODE);
			W2BYTEMSK(REG_015C_MODD1, 0x3, REG_015C_MODD1_REG_SERI_FORMAT_V1);
			W2BYTEMSK(REG_0038_MODA1, 0x1, Fld(1,0,AC_MSKB0));
		} else {
			// 4 byte mode
			W2BYTEMSK(REG_0188_MODV12, 2, REG_0188_MODV12_REG_VBY1_BYTE_MODE);
			W2BYTEMSK(REG_015C_MODD1, 0x1, REG_015C_MODD1_REG_SERI_FORMAT_V1);
			W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,0,AC_MSKB0));
		}
	} else {
		if ((priv->out_timing == E_8K4K_60HZ || priv->out_timing == E_5K2K_120HZ) &&
		    priv->out_format == E_OUTPUT_YUV422) {
			// 5 byte mode
			W2BYTEMSK(REG_0188_MODV12, 1, REG_0188_MODV12_REG_VBY1_BYTE_MODE);
			W2BYTEMSK(REG_015C_MODD1, 0x3, REG_015C_MODD1_REG_SERI_FORMAT_V1);
			W2BYTEMSK(REG_0038_MODA1, 0x1, Fld(1,0,AC_MSKB0));
		} else {
			// 4 byte mode
			W2BYTEMSK(REG_0188_MODV12, 2, REG_0188_MODV12_REG_VBY1_BYTE_MODE);
			W2BYTEMSK(REG_015C_MODD1, 0x1, REG_015C_MODD1_REG_SERI_FORMAT_V1);
			W2BYTEMSK(REG_0038_MODA1, 0x0, Fld(1,0,AC_MSKB0));
		}
	}
}

void vby1_set_pn_swap(u32 pnl_lib_version)
{
	if (pnl_lib_version == BOOT_PNL_VERSION0100) {
		//Currently, rcon value should read from efuse, and can not be modified by customer.
		//For ES1 PN Swap.
		W2BYTEMSK(REG_00E0_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch0
		W2BYTEMSK(REG_00E0_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch1
		W2BYTEMSK(REG_00E4_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch2
		W2BYTEMSK(REG_00E4_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch3
		W2BYTEMSK(REG_00E8_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch4
		W2BYTEMSK(REG_00E8_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch5
		W2BYTEMSK(REG_00EC_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch6
		W2BYTEMSK(REG_00EC_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch7
		W2BYTEMSK(REG_00F0_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch8
		W2BYTEMSK(REG_00F0_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch9
		W2BYTEMSK(REG_00F4_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch10
		W2BYTEMSK(REG_00F4_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch11
		W2BYTEMSK(REG_00F8_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch12
		W2BYTEMSK(REG_00F8_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch13
		W2BYTEMSK(REG_00FC_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch14
		W2BYTEMSK(REG_00FC_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch15
		W2BYTEMSK(REG_0100_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch16
		W2BYTEMSK(REG_0100_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch17
		W2BYTEMSK(REG_0104_MODA1, 0x1, Fld(1,5,AC_MSKB0));//ch18
		W2BYTEMSK(REG_0104_MODA1, 0x1, Fld(1,13,AC_MSKB1));//ch19
		W2BYTEMSK(REG_00E0_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch20
		W2BYTEMSK(REG_00E0_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch21
		W2BYTEMSK(REG_00E4_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch22
		W2BYTEMSK(REG_00E4_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch23
		W2BYTEMSK(REG_00E8_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch24
		W2BYTEMSK(REG_00E8_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch25
		W2BYTEMSK(REG_00EC_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch26
		W2BYTEMSK(REG_00EC_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch27
		W2BYTEMSK(REG_00F0_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch28
		W2BYTEMSK(REG_00F0_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch29
		W2BYTEMSK(REG_00F4_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch30
		W2BYTEMSK(REG_00F4_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch31
		W2BYTEMSK(REG_00F8_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch32
		W2BYTEMSK(REG_00F8_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch33
		W2BYTEMSK(REG_00FC_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch34
		W2BYTEMSK(REG_00FC_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch35
		W2BYTEMSK(REG_0100_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch36
		W2BYTEMSK(REG_0100_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch37
		W2BYTEMSK(REG_0104_MODA2, 0x1, Fld(1,5,AC_MSKB0));//ch38
		W2BYTEMSK(REG_0104_MODA2, 0x1, Fld(1,13,AC_MSKB1));//ch39
	} else if (pnl_lib_version >= BOOT_PNL_VERSION0200) {
		if ((pnl_lib_version == BOOT_PNL_VERSION0200) ||
			(pnl_lib_version == BOOT_PNL_VERSION0203) ||
			(pnl_lib_version == BOOT_PNL_VERSION0300)) {
			W2BYTEMSK(REG_0008_MODA1, REG_ALL, REG_0008_MODA1_REG_GCR_DS_POL_CH_19_00_0);
			W2BYTEMSK(REG_000C_MODA1, REG_ALL, REG_000C_MODA1_REG_GCR_DS_POL_CH_19_00_1);
			W2BYTEMSK(REG_0008_MODA2, REG_ALL, REG_0008_MODA2_REG_GCR_DS_POL_CH_39_20_0);
			W2BYTEMSK(REG_000C_MODA2, REG_ALL, REG_000C_MODA2_REG_GCR_DS_POL_CH_39_20_1);
			if (pnl_lib_version == BOOT_PNL_VERSION0300) {
				W2BYTEMSK(REG_0008_MODA3, REG_ALL, REG_0008_MODA3_REG_GCR_DS_POL_CH_59_40_0);
				W2BYTEMSK(REG_000C_MODA3, REG_ALL, REG_000C_MODA3_REG_GCR_DS_POL_CH_59_40_1);
				W2BYTEMSK(REG_0008_MODA4, REG_ALL, REG_0008_MODA4_REG_GCR_DS_POL_CH_63_60);
			}
		}

		if (pnl_lib_version == BOOT_PNL_VERSION0400 ||
			pnl_lib_version == BOOT_PNL_VERSION0500 ||
			pnl_lib_version == BOOT_PNL_VERSION0600)
			W2BYTEMSK(REG_0008_MODA1, 0xFFF, REG_0008_MODA1_REG_GCR_DS_POL_CH_19_00_0);
	}
}

static void _vby1_set_SCTCON_MISC(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->out_format == E_OUTPUT_YUV444) {
		W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 0, REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL);
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 1, REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_BYPASS);
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 0, REG_0040_SCTCON_MISC_BKA3E0_REG_MOD_REORDER );
	} else if (priv->out_format == E_OUTPUT_YUV422) {
		W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 0, REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL); //csc out bypass
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 0, REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_BYPASS);
		W2BYTEMSK(REG_0040_SCTCON_MISC_BKA3E0, 1, REG_0040_SCTCON_MISC_BKA3E0_REG_MOD_REORDER );
	} else {
		W2BYTEMSK(REG_0004_SCTCON_MISC_BKA3E0, 1, REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL); //csc out bypass
	}
}


static void _vby1_set_mft(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	u8 htt_slot = 0;

	if(priv->out_format == E_OUTPUT_YUV422)
		W2BYTEMSK(REG_0040_MODV11, priv->de_width/2, REG_0040_MODV11_REG_HSIZE);
	else
		W2BYTEMSK(REG_0040_MODV11, priv->de_width, REG_0040_MODV11_REG_HSIZE);

	if (priv->linktype == E_LINK_VB1) {
		switch(priv->div_sec) {
		case 1:
			W2BYTEMSK(REG_0004_MODV11, 0x1, REG_0004_MODV11_REG_MFT_MODE);
			if (priv->out_format == E_OUTPUT_YUV422)
				W2BYTEMSK(REG_0044_MODV11, priv->de_width/2, REG_0044_MODV11_REG_DIV_LEN);
			else
				W2BYTEMSK(REG_0044_MODV11, priv->de_width, REG_0044_MODV11_REG_DIV_LEN);

			W2BYTEMSK(REG_0048_MODV11, 0x0, REG_0048_MODV11_REG_BASE0_ADDR);
		break;

		case 2:
			W2BYTEMSK(REG_0004_MODV11, 0x2, REG_0004_MODV11_REG_MFT_MODE);
			if (priv->out_format == E_OUTPUT_YUV422)
				W2BYTEMSK(REG_0044_MODV11, priv->de_width/4, REG_0044_MODV11_REG_DIV_LEN);
			else
				W2BYTEMSK(REG_0044_MODV11, priv->de_width/2, REG_0044_MODV11_REG_DIV_LEN);

			W2BYTEMSK(REG_0048_MODV11, 0x0, REG_0048_MODV11_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV11, priv->de_width/2, REG_004C_MODV11_REG_BASE1_ADDR);
		break;

		case 4:
			W2BYTEMSK(REG_0004_MODV11, 0x3, REG_0004_MODV11_REG_MFT_MODE);
			W2BYTEMSK(REG_0044_MODV11, priv->de_width/4, REG_0044_MODV11_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV11, 0x0, REG_0048_MODV11_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV11, priv->de_width/4, REG_004C_MODV11_REG_BASE1_ADDR);
			W2BYTEMSK(REG_0050_MODV11, priv->de_width/2, REG_0050_MODV11_REG_BASE2_ADDR);
			W2BYTEMSK(REG_0054_MODV11, priv->de_width*3/4, REG_0054_MODV11_REG_BASE3_ADDR);
		break;

		case 8:
			W2BYTEMSK(REG_0004_MODV11, 0x4, REG_0004_MODV11_REG_MFT_MODE);
			W2BYTEMSK(REG_0044_MODV11, priv->de_width/8, REG_0044_MODV11_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV11, 0x0, REG_0048_MODV11_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV11, priv->de_width/8, REG_004C_MODV11_REG_BASE1_ADDR);
			W2BYTEMSK(REG_0050_MODV11, priv->de_width/4, REG_0050_MODV11_REG_BASE2_ADDR);
			W2BYTEMSK(REG_0054_MODV11, priv->de_width*3/8, REG_0054_MODV11_REG_BASE3_ADDR);
			W2BYTEMSK(REG_0058_MODV11, priv->de_width/2, REG_0058_MODV11_REG_BASE4_ADDR);
			W2BYTEMSK(REG_005C_MODV11, priv->de_width*5/8, REG_005C_MODV11_REG_BASE5_ADDR);
			W2BYTEMSK(REG_0060_MODV11, priv->de_width*6/8, REG_0060_MODV11_REG_BASE6_ADDR);
			W2BYTEMSK(REG_0064_MODV11, priv->de_width*7/8, REG_0064_MODV11_REG_BASE7_ADDR);
		break;

		default:
			debug("UNSUPPORT MFT Division\n");
		break;

		}

		if (priv->lanes/MFT_P > 0)
			htt_slot = priv->lanes/MFT_P -1;
		else
			htt_slot = 0;

		W2BYTEMSK(REG_000C_MODV11, htt_slot, REG_000C_MODV11_REG_MFT_VLD_WRAP_FIX_HTT);
	}

	if (priv->linktype == E_LINK_LVDS) {
		//prepare for h mirror case
		W2BYTEMSK(REG_0004_MODV11, 0x1, REG_0004_MODV11_REG_MFT_MODE);
		W2BYTEMSK(REG_0044_MODV11, 0x780, REG_0044_MODV11_REG_DIV_LEN);
		W2BYTEMSK(REG_0048_MODV11, 0x0, REG_0048_MODV11_REG_BASE0_ADDR);
	}
#ifdef CONFIG_HAPS
	//if (priv->pnl_lib_version == BOOT_PNL_VERSION0500)
	{
		// HAPS case, bypass MFT
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_1PTO2P_EN);
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_2PTO4P_EN);
		W2BYTEMSK(REG_0140_MODV11, 0x0, REG_0140_MODV11_REG_MOD_4PTO8P_EN);
		W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_DIV_PIX_MODE);
		W2BYTEMSK(REG_0004_MODV11, 0x0, REG_0004_MODV11_REG_MFT_MODE);
	}
#endif  //#ifdef CONFIG
}

static void _vby1_extv_set_mft(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}
	u8 htt_slot = 0;

	if (IS_VB1_OUT(priv->linktype)) {

		if (priv->div_sec == 1) {
			W2BYTEMSK(REG_0004_MODV21, 0x1, REG_0004_MODV21_REG_MFT_MODE);
			W2BYTEMSK(REG_0004_MODV21, 0x0, REG_0004_MODV21_REG_DIV_PIX_MODE);
			W2BYTEMSK(REG_0040_MODV21, priv->de_width, REG_0040_MODV21_REG_HSIZE);
			W2BYTEMSK(REG_0044_MODV21, priv->de_width, REG_0044_MODV21_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV21, 0x0, REG_0048_MODV21_REG_BASE0_ADDR);
		} else if (priv->div_sec == 2) {
			W2BYTEMSK(REG_0004_MODV21, 0x2, REG_0004_MODV21_REG_MFT_MODE);
			W2BYTEMSK(REG_0004_MODV21, 0x0, REG_0004_MODV21_REG_DIV_PIX_MODE);
			W2BYTEMSK(REG_0040_MODV21, priv->de_width, REG_0040_MODV21_REG_HSIZE);
			W2BYTEMSK(REG_0044_MODV21, priv->de_width/2, REG_0044_MODV21_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV21, 0x0, REG_0048_MODV21_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODV21, priv->de_width/2, REG_004C_MODV21_REG_BASE1_ADDR);
		} else if (priv->div_sec == 4) {
			W2BYTEMSK(REG_0004_MODV21, 0x3, REG_0004_MODV21_REG_MFT_MODE);
			W2BYTEMSK(REG_0044_MODV21, priv->de_width/4, REG_0044_MODV21_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODV21, 0x0, REG_0048_MODV21_REG_BASE0_ADDR);
                        W2BYTEMSK(REG_004C_MODV21, priv->de_width/4, REG_004C_MODV21_REG_BASE1_ADDR);
			W2BYTEMSK(REG_0050_MODV21, priv->de_width/2, REG_0050_MODV21_REG_BASE2_ADDR);
			W2BYTEMSK(REG_0054_MODV21, priv->de_width*3/4, REG_0054_MODV21_REG_BASE3_ADDR);
		} else {
			debug("[%s] Unsupport MFT mode\n", __func__);
		}
	}

	if (priv->lanes/MFT_P > 0)
		htt_slot = priv->lanes/MFT_P -1;
	else
		htt_slot = 0;

	W2BYTEMSK(REG_000C_MODV21, htt_slot, REG_000C_MODV21_REG_MFT_VLD_WRAP_FIX_HTT);

}

static void _vby1_gfx_set_mft(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}
	u8 htt_slot = 0;

	if (IS_VB1_OUT(priv->linktype)) {

		if (priv->div_sec == 1) {
			W2BYTEMSK(REG_0004_MODOSD1, 0x1, REG_0004_MODOSD1_REG_MFT_MODE);
			W2BYTEMSK(REG_0004_MODOSD1, 0x0, REG_0004_MODOSD1_REG_DIV_PIX_MODE);
			W2BYTEMSK(REG_0040_MODOSD1, priv->de_width, REG_0040_MODOSD1_REG_HSIZE);
			W2BYTEMSK(REG_0044_MODOSD1, priv->de_width, REG_0044_MODOSD1_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODOSD1, 0x0, REG_0048_MODOSD1_REG_BASE0_ADDR);
		} else if (priv->div_sec == 2) {
			W2BYTEMSK(REG_0004_MODOSD1, 0x2, REG_0004_MODOSD1_REG_MFT_MODE);
			W2BYTEMSK(REG_0004_MODOSD1, 0x0, REG_0004_MODOSD1_REG_DIV_PIX_MODE);
			W2BYTEMSK(REG_0040_MODOSD1, priv->de_width, REG_0040_MODOSD1_REG_HSIZE);
			W2BYTEMSK(REG_0044_MODOSD1, priv->de_width/2, REG_0044_MODOSD1_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODOSD1, 0x0, REG_0048_MODOSD1_REG_BASE0_ADDR);
			W2BYTEMSK(REG_004C_MODOSD1, priv->de_width/2, REG_004C_MODOSD1_REG_BASE1_ADDR);
		} else if (priv->div_sec == 4) {
			W2BYTEMSK(REG_0004_MODOSD1, 0x3, REG_0004_MODOSD1_REG_MFT_MODE);
			W2BYTEMSK(REG_0044_MODOSD1, priv->de_width/4, REG_0044_MODOSD1_REG_DIV_LEN);
			W2BYTEMSK(REG_0048_MODOSD1, 0x0, REG_0048_MODOSD1_REG_BASE0_ADDR);
                        W2BYTEMSK(REG_004C_MODOSD1, priv->de_width/4, REG_004C_MODOSD1_REG_BASE1_ADDR);
			W2BYTEMSK(REG_0050_MODOSD1, priv->de_width/2, REG_0050_MODOSD1_REG_BASE2_ADDR);
			W2BYTEMSK(REG_0054_MODOSD1, priv->de_width*3/4, REG_0054_MODOSD1_REG_BASE3_ADDR);
		} else {
			debug("[%s] Unsupport MFT mode\n", __func__);
		}
	}

	if (priv->lanes/MFT_P > 0)
		htt_slot = priv->lanes/MFT_P -1;
	else
		htt_slot = 0;

	W2BYTEMSK(REG_000C_MODOSD1, htt_slot, REG_000C_MODOSD1_REG_MFT_VLD_WRAP_FIX_HTT);

}

static void _PATCH_INIT_XC_CLK(void)
{
	W2BYTEMSK(REG_18E4_CKGEN01, 0x1, REG_18E4_CKGEN01_REG_SW_EN_DELTA_B2P2_SRAM2SCACE);
	W2BYTEMSK(REG_1900_CKGEN01, 0x1, REG_1900_CKGEN01_REG_SW_EN_GUCD_18_LUT2_SRAM2SCACE);
	W2BYTEMSK(REG_1908_CKGEN01, 0x1, REG_1908_CKGEN01_REG_SW_EN_GUCD_256_LUT2_SRAM2SCACE);
	W2BYTEMSK(REG_1914_CKGEN01, 0x1, REG_1914_CKGEN01_REG_SW_EN_HSY_8P3_SRAM2SCACE);
	W2BYTEMSK(REG_1910_CKGEN01, 0x1, REG_1910_CKGEN01_REG_SW_EN_HSY_8P_SRAM2SCACE);
	W2BYTEMSK(REG_1928_CKGEN01, 0x1, REG_1928_CKGEN01_REG_SW_EN_LCE_ACE_SRAM2SCACE);
	W2BYTEMSK(REG_1968_CKGEN01, 0x1, REG_1968_CKGEN01_REG_SW_EN_VIP_ACE_SRAM2SCACE);
	W2BYTEMSK(REG_1998_CKGEN01, 0x1, REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCACE_HSY);
	W2BYTEMSK(REG_1998_CKGEN01, 0x1, REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCACE_VIP);
	W2BYTEMSK(REG_19EC_CKGEN01, 0x1, REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCACE);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCACE);
	W2BYTEMSK(REG_18EC_CKGEN01, 0x1, REG_18EC_CKGEN01_REG_SW_EN_DV_HW5_SRAM2SCDV);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN_22SCDV);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCDV);
	W2BYTEMSK(REG_19EC_CKGEN01, 0x1, REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCDV);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCDV);
	W2BYTEMSK(REG_18D8_CKGEN01, 0x1, REG_18D8_CKGEN01_REG_SW_EN_DC0_SRAM2SCIP);
	W2BYTEMSK(REG_157C_CKGEN01, 0x1, REG_157C_CKGEN01_REG_SW_EN_FRC_FCLK_2XPLUS2SCIP);
	W2BYTEMSK(REG_1A00_CKGEN01, 0x1, REG_1A00_CKGEN01_REG_SW_EN_SIDCLK_HD02SCIP);
	W2BYTEMSK(REG_1A04_CKGEN01, 0x1, REG_1A04_CKGEN01_REG_SW_EN_SIDCLK_HD12SCIP);
	W2BYTEMSK(REG_1A08_CKGEN01, 0x1, REG_1A08_CKGEN01_REG_SW_EN_SIDCLK_HD22SCIP);
	W2BYTEMSK(REG_1A0C_CKGEN01, 0x1, REG_1A0C_CKGEN01_REG_SW_EN_SIDCLK_HD32SCIP);
	W2BYTEMSK(REG_1960_CKGEN01, 0x1, REG_1960_CKGEN01_REG_SW_EN_UCD_ST_SRAM2SCIP);
	W2BYTEMSK(REG_1970_CKGEN01, 0x1, REG_1970_CKGEN01_REG_SW_EN_XC_ADC2SCIP);
	W2BYTEMSK(REG_1980_CKGEN01, 0x1, REG_1980_CKGEN01_REG_SW_EN_XC_DBG2MIU2SCIP);
	W2BYTEMSK(REG_197C_CKGEN01, 0x1, REG_197C_CKGEN01_REG_SW_EN_XC_DC02SCIP);
	W2BYTEMSK(REG_1A10_CKGEN01, 0x1, REG_1A10_CKGEN01_REG_SW_EN_XC_DIP02SCIP);
	W2BYTEMSK(REG_1A14_CKGEN01, 0x1, REG_1A14_CKGEN01_REG_SW_EN_XC_DIP12SCIP);
	W2BYTEMSK(REG_1A18_CKGEN01, 0x1, REG_1A18_CKGEN01_REG_SW_EN_XC_DIP22SCIP);
	W2BYTEMSK(REG_1984_CKGEN01, 0x1, REG_1984_CKGEN01_REG_SW_EN_XC_DISP_MFDEC2SCIP);
	W2BYTEMSK(REG_1988_CKGEN01, 0x1, REG_1988_CKGEN01_REG_SW_EN_XC_ED02SCIP);
	W2BYTEMSK(REG_198C_CKGEN01, 0x1, REG_198C_CKGEN01_REG_SW_EN_XC_ED12SCIP);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCIP);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCIP);
	W2BYTEMSK(REG_1998_CKGEN01, 0x1, REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCIP);
	W2BYTEMSK(REG_199C_CKGEN01, 0x1, REG_199C_CKGEN01_REG_SW_EN_XC_HD2MIU_M2SCIP);
	W2BYTEMSK(REG_19A0_CKGEN01, 0x1, REG_19A0_CKGEN01_REG_SW_EN_XC_HD2MIU_S2SCIP);
	W2BYTEMSK(REG_19A4_CKGEN01, 0x1, REG_19A4_CKGEN01_REG_SW_EN_XC_HDMI02SCIP);
	W2BYTEMSK(REG_19A8_CKGEN01, 0x1, REG_19A8_CKGEN01_REG_SW_EN_XC_HDMI12SCIP);
	W2BYTEMSK(REG_19AC_CKGEN01, 0x1, REG_19AC_CKGEN01_REG_SW_EN_XC_HDMI22SCIP);
	W2BYTEMSK(REG_19B0_CKGEN01, 0x1, REG_19B0_CKGEN01_REG_SW_EN_XC_HDMI32SCIP);
	W2BYTEMSK(REG_19B4_CKGEN01, 0x1, REG_19B4_CKGEN01_REG_SW_EN_XC_ID02SCIP);
	W2BYTEMSK(REG_19B8_CKGEN01, 0x1, REG_19B8_CKGEN01_REG_SW_EN_XC_ID12SCIP);
	W2BYTEMSK(REG_19BC_CKGEN01, 0x1, REG_19BC_CKGEN01_REG_SW_EN_XC_IP2_SRC2SCIP);
	W2BYTEMSK(REG_17E0_CKGEN01, 0x1, REG_17E0_CKGEN01_REG_SW_EN_XC_OD_DELTA2SCIP);
	W2BYTEMSK(REG_19C4_CKGEN01, 0x1, REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCIP);
	W2BYTEMSK(REG_19C8_CKGEN01, 0x1, REG_19C8_CKGEN01_REG_SW_EN_XC_SLOW2SCIP);
	//CODA Mapping abnormal
	//W2BYTEMSK(REG_19F8_CKGEN01, 0x1, REG_19F8_CKGEN01_REG_SW_EN_XC_SUB1_DC02SCIP);
	W2BYTEMSK(REG_1978_CKGEN01, 0x1, REG_1978_CKGEN01_REG_SW_EN_XC_SUB_DC02SCIP);
	W2BYTEMSK(REG_19D8_CKGEN01, 0x1, REG_19D8_CKGEN01_REG_SW_EN_XC_TGEN_WIN2SCIP);
	W2BYTEMSK(REG_19DC_CKGEN01, 0x1, REG_19DC_CKGEN01_REG_SW_EN_XC_UCD_STAT2SCIP);
	W2BYTEMSK(REG_19E0_CKGEN01, 0x1, REG_19E0_CKGEN01_REG_SW_EN_XC_VD2SCIP);
	W2BYTEMSK(REG_19E4_CKGEN01, 0x1, REG_19E4_CKGEN01_REG_SW_EN_XC_VE2SCIP);
	W2BYTEMSK(REG_1A1C_CKGEN01, 0x1, REG_1A1C_CKGEN01_REG_SW_EN_XC_VEDAC2SCIP);
	W2BYTEMSK(REG_1A20_CKGEN01, 0x1, REG_1A20_CKGEN01_REG_SW_EN_XC_VEIN2SCIP);
	W2BYTEMSK(REG_19EC_CKGEN01, 0x1, REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCIP);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCIP);
	W2BYTEMSK(REG_19F4_CKGEN01, 0x1, REG_19F4_CKGEN01_REG_SW_EN_XTAL_IP12SCIP);
	W2BYTEMSK(REG_1A24_CKGEN01, 0x1, REG_1A24_CKGEN01_REG_SW_EN_DIP1_HVSP_SRAM2SCMW);
	W2BYTEMSK(REG_1A28_CKGEN01, 0x1, REG_1A28_CKGEN01_REG_SW_EN_DIP1_XVYCC_SRAM2SCMW);
	W2BYTEMSK(REG_157C_CKGEN01, 0x1, REG_157C_CKGEN01_REG_SW_EN_FRC_FCLK_2XPLUS2SCMW);
	W2BYTEMSK(REG_1914_CKGEN01, 0x1, REG_1914_CKGEN01_REG_SW_EN_HSY_8P3_SRAM2SCMW);
	W2BYTEMSK(REG_1910_CKGEN01, 0x1, REG_1910_CKGEN01_REG_SW_EN_HSY_8P_SRAM2SCMW);
	W2BYTEMSK(REG_1950_CKGEN01, 0x1, REG_1950_CKGEN01_REG_SW_EN_PQ_GAMMA_SRAM2SCMW);
	W2BYTEMSK(REG_1954_CKGEN01, 0x1, REG_1954_CKGEN01_REG_SW_EN_RGB_3DLUT_SRAM2SCMW);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCMW);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCMW);
	W2BYTEMSK(REG_1998_CKGEN01, 0x1, REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCMW);
	W2BYTEMSK(REG_19C4_CKGEN01, 0x1, REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCMW);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCMW);
	W2BYTEMSK(REG_19FC_CKGEN01, 0x1, REG_19FC_CKGEN01_REG_SW_EN_XVYCC_SRAM2SCMW);
	W2BYTEMSK(REG_1564_CKGEN01, 0x1, REG_1564_CKGEN01_REG_SW_EN_DISP_MFDEC2SCNR);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCNR);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCNR);
	W2BYTEMSK(REG_18DC_CKGEN01, 0x1, REG_18DC_CKGEN01_REG_SW_EN_DBK_HW_SRAM2SCPQ);
	W2BYTEMSK(REG_1958_CKGEN01, 0x1, REG_1958_CKGEN01_REG_SW_EN_SCNR_HDR_SRAM2SCPQ);
	W2BYTEMSK(REG_195C_CKGEN01, 0x1, REG_195C_CKGEN01_REG_SW_EN_SPF_HDBK_SRAM2SCPQ);
	W2BYTEMSK(REG_1964_CKGEN01, 0x1, REG_1964_CKGEN01_REG_SW_EN_VDBK_SRAM2SCPQ);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCPQ_SPF);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCPQ_DOLBY);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCPQ);
	W2BYTEMSK(REG_18E0_CKGEN01, 0x1, REG_18E0_CKGEN01_REG_SW_EN_DELTA_B2P_SRAM2SCSCL);
	W2BYTEMSK(REG_1904_CKGEN01, 0x1, REG_1904_CKGEN01_REG_SW_EN_GUCD_18_SRAM2SCSCL);
	W2BYTEMSK(REG_190C_CKGEN01, 0x1, REG_190C_CKGEN01_REG_SW_EN_GUCD_256_SRAM2SCSCL);
	W2BYTEMSK(REG_191C_CKGEN01, 0x1, REG_191C_CKGEN01_REG_SW_EN_HSY_SP3_SRAM2SCSCL);
	W2BYTEMSK(REG_1918_CKGEN01, 0x1, REG_1918_CKGEN01_REG_SW_EN_HSY_SP_SRAM2SCSCL);
	W2BYTEMSK(REG_1920_CKGEN01, 0x1, REG_1920_CKGEN01_REG_SW_EN_HVSP_STP1_SRAM2SCSCL);
	W2BYTEMSK(REG_1924_CKGEN01, 0x1, REG_1924_CKGEN01_REG_SW_EN_HVSP_STP2_SRAM2SCSCL);
	W2BYTEMSK(REG_192C_CKGEN01, 0x1, REG_192C_CKGEN01_REG_SW_EN_LCE_SCL_SRAM2SCSCL);
	W2BYTEMSK(REG_196C_CKGEN01, 0x1, REG_196C_CKGEN01_REG_SW_EN_VIP_PQ_SRAM2SCSCL);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCSCL);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCSCL);
	W2BYTEMSK(REG_1998_CKGEN01, 0x1, REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCSCL);
	W2BYTEMSK(REG_17E0_CKGEN01, 0x1, REG_17E0_CKGEN01_REG_SW_EN_XC_OD_DELTA2SCSCL);
	W2BYTEMSK(REG_19C4_CKGEN01, 0x1, REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCSCL);
	W2BYTEMSK(REG_19EC_CKGEN01, 0x1, REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCSCL);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCSCL);
	W2BYTEMSK(REG_18C8_CKGEN01, 0x1, REG_18C8_CKGEN01_REG_SW_EN_AISR_HVSP_SRAM2SCSR);
	W2BYTEMSK(REG_18D4_CKGEN01, 0x1, REG_18D4_CKGEN01_REG_SW_EN_AISR_SRAM2SCSR);
	W2BYTEMSK(REG_18D4_CKGEN01, 0x1, REG_18D4_CKGEN01_REG_SW_EN_AISR_SRAM_PH_12SCSR);
	W2BYTEMSK(REG_1974_CKGEN01, 0x1, REG_1974_CKGEN01_REG_SW_EN_XC_AISR2SCSR);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCSR);
	W2BYTEMSK(REG_1998_CKGEN01, 0x1, REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCSR);
	W2BYTEMSK(REG_19CC_CKGEN01, 0x1, REG_19CC_CKGEN01_REG_SW_EN_XC_SR_ALAI2SCSR);
	W2BYTEMSK(REG_19D0_CKGEN01, 0x1, REG_19D0_CKGEN01_REG_SW_EN_XC_SR_SRAM_SHARE2SCSR);
	W2BYTEMSK(REG_19D4_CKGEN01, 0x1, REG_19D4_CKGEN01_REG_SW_EN_XC_SRS2SCSR);
	W2BYTEMSK(REG_19EC_CKGEN01, 0x1, REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCSR);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCSR);
	W2BYTEMSK(REG_18E8_CKGEN01, 0x1, REG_18E8_CKGEN01_REG_SW_EN_DEMURA_SRAM2SCTCON);
	W2BYTEMSK(REG_18F0_CKGEN01, 0x1, REG_18F0_CKGEN01_REG_SW_EN_GOP0_SRAM2SCTCON);
	W2BYTEMSK(REG_18F4_CKGEN01, 0x1, REG_18F4_CKGEN01_REG_SW_EN_GOP1_SRAM2SCTCON);
	W2BYTEMSK(REG_18F8_CKGEN01, 0x1, REG_18F8_CKGEN01_REG_SW_EN_GOP2_SRAM2SCTCON);
	W2BYTEMSK(REG_18FC_CKGEN01, 0x1, REG_18FC_CKGEN01_REG_SW_EN_GOP3_SRAM2SCTCON);
	W2BYTEMSK(REG_1930_CKGEN01, 0x1, REG_1930_CKGEN01_REG_SW_EN_LD_EDGE2D_SRAM2SCTCON);
	W2BYTEMSK(REG_1934_CKGEN01, 0x1, REG_1934_CKGEN01_REG_SW_EN_LDCOMP_SRAM2SCTCON);
	W2BYTEMSK(REG_1938_CKGEN01, 0x1, REG_1938_CKGEN01_REG_SW_EN_LDM_GA_SRAM2SCTCON);
	W2BYTEMSK(REG_193C_CKGEN01, 0x1, REG_193C_CKGEN01_REG_SW_EN_LDMCG_SRAM2SCTCON);
	W2BYTEMSK(REG_1940_CKGEN01, 0x1, REG_1940_CKGEN01_REG_SW_EN_LPQ_PA_SRAM2SCTCON);
	W2BYTEMSK(REG_1944_CKGEN01, 0x1, REG_1944_CKGEN01_REG_SW_EN_OSD_DV_HW5_SRAM2SCTCON);
	W2BYTEMSK(REG_1948_CKGEN01, 0x1, REG_1948_CKGEN01_REG_SW_EN_PADJ_SRAM2SCTCON);
	W2BYTEMSK(REG_194C_CKGEN01, 0x1, REG_194C_CKGEN01_REG_SW_EN_PANEL_GA_SRAM2SCTCON);
	W2BYTEMSK(REG_17C8_CKGEN01, 0x1, REG_17C8_CKGEN01_REG_SW_EN_XC_AFBC2SCTCON);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD_ABF2SCTCON);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD_DV2SCTCON);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD_GOP02SCTCON);
	W2BYTEMSK(REG_1990_CKGEN01, 0x1, REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCTCON);
	W2BYTEMSK(REG_1994_CKGEN01, 0x1, REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCTCON);
	W2BYTEMSK(REG_18CC_CKGEN01, 0x1, REG_18CC_CKGEN01_REG_SW_EN_XC_FS2SCTCON);
	W2BYTEMSK(REG_17CC_CKGEN01, 0x1, REG_17CC_CKGEN01_REG_SW_EN_XC_GOP0_DST2SCTCON);
	W2BYTEMSK(REG_17D4_CKGEN01, 0x1, REG_17D4_CKGEN01_REG_SW_EN_XC_GOP2SCTCON);
	W2BYTEMSK(REG_17D0_CKGEN01, 0x1, REG_17D0_CKGEN01_REG_SW_EN_XC_GOP_SCL2SCTCON);
	W2BYTEMSK(REG_17D8_CKGEN01, 0x1, REG_17D8_CKGEN01_REG_SW_EN_XC_GOPC_DST2SCTCON);
	W2BYTEMSK(REG_17DC_CKGEN01, 0x1, REG_17DC_CKGEN01_REG_SW_EN_XC_GOPG_DST2SCTCON);
	W2BYTEMSK(REG_17E0_CKGEN01, 0x1, REG_17E0_CKGEN01_REG_SW_EN_XC_OD_DELTA2SCTCON);
	W2BYTEMSK(REG_1A54_CKGEN01, 0x1, REG_1A54_CKGEN01_REG_SW_EN_XC_OD_DELTA_META2SCTCON);
	W2BYTEMSK(REG_17E4_CKGEN01, 0x1, REG_17E4_CKGEN01_REG_SW_EN_XC_OD_DIV22SCTCON);
	W2BYTEMSK(REG_17E8_CKGEN01, 0x1, REG_17E8_CKGEN01_REG_SW_EN_XC_OD_DIV42SCTCON);
	W2BYTEMSK(REG_19C4_CKGEN01, 0x1, REG_19C4_CKGEN01_REG_SW_EN_XC_OD_EDGE2SCTCON);
	W2BYTEMSK(REG_19C4_CKGEN01, 0x1, REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCTCON);
	W2BYTEMSK(REG_1A50_CKGEN01, 0x1, REG_1A50_CKGEN01_REG_SW_EN_XC_OD_META2SCTCON);
	W2BYTEMSK(REG_18D0_CKGEN01, 0x1, REG_18D0_CKGEN01_REG_SW_EN_XC_OD_OSD2SCTCON);
	W2BYTEMSK(REG_1A5C_CKGEN01, 0x1, REG_1A5C_CKGEN01_REG_SW_EN_XC_OD_OSD_META2SCTCON);
	W2BYTEMSK(REG_19EC_CKGEN01, 0x1, REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCTCON);
	W2BYTEMSK(REG_19F0_CKGEN01, 0x1, REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCTCON);
	W2BYTEMSK(REG_14E8_CKGEN00, 0x1, REG_14E8_CKGEN00_REG_SW_EN_SMI2SCACE);
	W2BYTEMSK(REG_14E8_CKGEN00, 0x1, REG_14E8_CKGEN00_REG_SW_EN_SMI2SCDV);
	W2BYTEMSK(REG_14EC_CKGEN00, 0x1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCMW);
	W2BYTEMSK(REG_14EC_CKGEN00, 0x1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCPQ);
	W2BYTEMSK(REG_14EC_CKGEN00, 0x1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCSCL);
	W2BYTEMSK(REG_14EC_CKGEN00, 0x1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCSR);
}

void _PATCH_INIT_XC_CLK_v2(void)
{
	/*ckgen00*/
	W2BYTEMSK(REG_14EC_CKGEN00, 1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCM);
	W2BYTEMSK(REG_14EC_CKGEN00, 1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCMO);

	/*ckgen01*/
	W2BYTEMSK(REG_1570_CKGEN01, 0x1, REG_1570_CKGEN01_REG_SW_EN_DAP2FRCIOPM);
	W2BYTEMSK(REG_1578_CKGEN01, 0x1, REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2DEFLICKER);
	W2BYTEMSK(REG_1578_CKGEN01, 0x1, REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2FRCIOPM);
	W2BYTEMSK(REG_157C_CKGEN01, 0x1, REG_157C_CKGEN01_REG_SW_EN_FRC_FCLK_2XPLUS2FRCIOPMRV55);
	W2BYTEMSK(REG_1580_CKGEN01, 0x1, REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCIOPM);
	W2BYTEMSK(REG_159C_CKGEN01, 0x1, REG_159C_CKGEN01_REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPM);
	W2BYTEMSK(REG_15B4_CKGEN01, 0x1, REG_15B4_CKGEN01_REG_SW_EN_XTAL_12M2FRCIOPM);
	W2BYTEMSK(REG_15C0_CKGEN01, 0x1, REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCIOPM);
	W2BYTEMSK(REG_15C0_CKGEN01, 0x1, REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCMEHALO);
	W2BYTEMSK(REG_15C0_CKGEN01, 0x1, REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCMI);
	W2BYTEMSK(REG_1AD8_CKGEN01, 0x1, REG_1AD8_CKGEN01_REG_SW_EN_FRC_FUART02FRCIOPM);
	W2BYTEMSK(REG_1AE0_CKGEN01, 0x1, REG_1AE0_CKGEN01_REG_SW_EN_FRC_MSPI02FRCIOPM);
	W2BYTEMSK(REG_1AE8_CKGEN01, 0x1, REG_1AE8_CKGEN01_REG_SW_EN_FRC_UART02FRCIOPM);
	W2BYTEMSK(REG_1AF0_CKGEN01, 0x1, REG_1AF0_CKGEN01_REG_SW_EN_FRC_UART12FRCIOPM);

	/*clock gate*/
	W2BYTEMSK(REG_0E80_CKGEN01, 0x0, REG_0E80_CKGEN01_REG_GATE_XC_ED_0E80);
	W2BYTEMSK(REG_0E84_CKGEN01, 0x0, REG_0E84_CKGEN01_REG_GATE_XC_FN_0E84);
	W2BYTEMSK(REG_0E88_CKGEN01, 0x0, REG_0E88_CKGEN01_REG_GATE_XC_FS_0E88);
	W2BYTEMSK(REG_0E8C_CKGEN01, 0x0, REG_0E8C_CKGEN01_REG_GATE_XC_FD_0E8C);
}

void _PATCH_INIT_XC_CLK_v3(void)
{
	/*ckgen00*/
	W2BYTEMSK(REG_14E4_CKGEN00, 1, REG_14E4_CKGEN00_REG_SW_EN_SMI2FRCIOPMRV55);
	W2BYTEMSK(REG_14E4_CKGEN00, 1, REG_14E4_CKGEN00_REG_SW_EN_SMI2FRCMEHALO);
	W2BYTEMSK(REG_14EC_CKGEN00, 1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCIP);
	W2BYTEMSK(REG_14EC_CKGEN00, 1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCNR);
	W2BYTEMSK(REG_14EC_CKGEN00, 1, REG_14EC_CKGEN00_REG_SW_EN_SMI2SCTCON);
	W2BYTEMSK(REG_14F4_CKGEN00, 1, REG_14F4_CKGEN00_REG_SW_EN_SMI2SCDISP_14F4);
	W2BYTEMSK(REG_14F0_CKGEN00, 1, REG_14F0_CKGEN00_REG_SW_EN_SMI2SMI_LARB_SCMW);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SMI_LARB_SCIP);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SMI_LARB_SCNR);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SCTCON_LARB);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2SCDISP_LARB);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2FRCIOPMRV55_LARB);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2FRCMEHALO_LARB);
	W2BYTEMSK(REG_14F8_CKGEN00, 1, V3_REG_14F8_CKGEN00_REG_SW_EN_SMI2FRCMI_GALS_SLICE);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SMI_GALS_SCMW);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SMI_GALS_SCIP);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SMI_GALS_SCNR);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SCTCON_GALS);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2SCDISP_GALS);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2FRCIOPMRV55_GALS);
	W2BYTEMSK(REG_1500_CKGEN00, 1, V3_REG_1500_CKGEN00_REG_SW_EN_SMI2FRCMEHALO_GALS);
}

void _PATCH_INIT_XC_CLK_v4(void)
{
	//ckgen 00
	W2BYTEMSK(REG_14EC_CKGEN00_V004, 0x1, REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCIP_14EC); //h53b[0]
	W2BYTEMSK(REG_14EC_CKGEN00_V004, 0x1, REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCM_14EC); //h53b[1]
	W2BYTEMSK(REG_14EC_CKGEN00_V004, 0x1, REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCMO_14EC); //h53b[2]
	W2BYTEMSK(REG_14EC_CKGEN00_V004, 0x1, REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCNR_14EC); //h53b[4]
	W2BYTEMSK(REG_1504_CKGEN00_V004, 0x1, REG_1504_CKGEN00_V004_REG_SW_EN_SMI2SCFE_GALS_1504); //h541[2]
	W2BYTEMSK(REG_14EC_CKGEN00_V004, 0x1, REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCBE_14EC); //h53b[5]
	W2BYTEMSK(REG_1504_CKGEN00_V004, 0x1, REG_1504_CKGEN00_V004_REG_SW_EN_SMI2SCBE_GALS_1504); //h541[1]
	W2BYTEMSK(REG_14EC_CKGEN00_V004, 0x1, REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCTC_14EC); //h53b[8]
	W2BYTEMSK(REG_1504_CKGEN00_V004, 0x1, REG_1504_CKGEN00_V004_REG_SW_EN_SMI2SCTC_GALS_1504); //h541[3]
	//W2BYTEMSK(REG_14F4_CKGEN00_V004, 0x1, REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCCORE1_14F4); //h53d[10]
	//W2BYTEMSK(REG_14F4_CKGEN00_V004, 0x1, REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCCORE2_14F4); //h53d[11]
	//W2BYTEMSK(REG_14F4_CKGEN00_V004, 0x1, REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCCORE3_14F4); //h53d[12]
	//W2BYTEMSK(REG_14F4_CKGEN00_V004, 0x1, REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCMISC_14F4); //h53d[13]
	W2BYTEMSK(REG_14F8_CKGEN00_V004, 0x1, REG_14F8_CKGEN00_V004_REG_SW_EN_SMI2SMI_FRCCORE1_14F8); //h53e[0]
	W2BYTEMSK(REG_1504_CKGEN00_V004, 0x1, REG_1504_CKGEN00_V004_REG_SW_EN_SMI2FRC_GALS_1504); //h541[0]
	//W2BYTEMSK(REG_1508_CKGEN00_V004, 0x1, REG_1508_CKGEN00_V004_REG_SW_EN_SMI2FRC_EMI_1508); //h542[2]
	W2BYTEMSK(REG_1508_CKGEN00_V004, 0x1, REG_1508_CKGEN00_V004_REG_SW_EN_SMI2FRC_R2_1508); //h542[3]

	//ckgen 01
	W2BYTEMSK(REG_0B18_CKGEN01_V004, 0x1, REG_0B18_CKGEN01_V004_REG_CKG_S_XC_DBG2MIU_SCIP_0B18);	// hdmi
	W2BYTEMSK(REG_1570_CKGEN01_V004, 0x1, REG_1570_CKGEN01_V004_REG_SW_EN_DAP2FRCMISC_1570); //h55c[0]
	//W2BYTEMSK(REG_1578_CKGEN01_V004, 0x1, REG_1578_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2X2FRCCORE1_1578); //h55e[0]
	//W2BYTEMSK(REG_1578_CKGEN01_V004, 0x1, REG_1578_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2X2FRCCORE3_1578); //h55e[2]
	//W2BYTEMSK(REG_157C_CKGEN01_V004, 0x1, REG_157C_CKGEN01_V004_REG_SW_EN_FRC_FCLK_2XPLUS2FRCCORE1_157C); //h55f[0]
	//W2BYTEMSK(REG_1580_CKGEN01_V004, 0x1, REG_1580_CKGEN01_V004_REG_SW_EN_FRC_FCLK2FRCCORE2_1580); //h560[1]
	W2BYTEMSK(REG_1588_CKGEN01_V004, 0x1, REG_1588_CKGEN01_V004_REG_SW_EN_R2_FRC2FRCMISC_1588); //h562[0]
	W2BYTEMSK(REG_159C_CKGEN01_V004, 0x1, REG_159C_CKGEN01_V004_REG_SW_EN_RV55DAP_JTAG_TCK2FRCMISC_159C); //h567[0]
	W2BYTEMSK(REG_15B4_CKGEN01_V004, 0x1, REG_15B4_CKGEN01_V004_REG_SW_EN_XTAL_12M2FRCMISC_15B4); //h56d[0]
	//W2BYTEMSK(REG_15C0_CKGEN01_V004, 0x1, REG_15C0_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRCCORE1_15C0); //h570[0]
	//W2BYTEMSK(REG_15C0_CKGEN01_V004, 0x1, REG_15C0_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRCCORE2_15C0); //h570[2]
	//W2BYTEMSK(REG_15C0_CKGEN01_V004, 0x1, REG_15C0_CKGEN01_V004_REG_SW_EN_XTAL_24M2FRCCORE3_15C0); //h570[4]
	W2BYTEMSK(REG_1938_CKGEN01_V004, 0x1, REG_1938_CKGEN01_V004_REG_SW_EN_LDM_GA_SRAM2SCTC_1938); //h64e[0]
	W2BYTEMSK(REG_1940_CKGEN01_V004, 0x1, REG_1940_CKGEN01_V004_REG_SW_EN_LPQ_PA_SRAM2SCTC_1940); //h650[0]
	W2BYTEMSK(REG_1990_CKGEN01_V004, 0x1, REG_1990_CKGEN01_V004_REG_SW_EN_XC_FD_DV2SCTC_1990); //h664[6]
	W2BYTEMSK(REG_19C4_CKGEN01_V004, 0x1, REG_19C4_CKGEN01_V004_REG_SW_EN_XC_OD_EDGE2SCTC_19C4); //h671[4]
	W2BYTEMSK(REG_1AD8_CKGEN01_V004, 0x1, REG_1AD8_CKGEN01_V004_REG_SW_EN_FRC_FUART02FRCMISC_1AD8); //h6b6[0]
	W2BYTEMSK(REG_1AE0_CKGEN01_V004, 0x1, REG_1AE0_CKGEN01_V004_REG_SW_EN_FRC_MSPI02FRCMISC_1AE0); //h6b8[0]
	W2BYTEMSK(REG_1AE8_CKGEN01_V004, 0x1, REG_1AE8_CKGEN01_V004_REG_SW_EN_FRC_UART02FRCMISC_1AE8); //h6ba[0]
	W2BYTEMSK(REG_1AF0_CKGEN01_V004, 0x1, REG_1AF0_CKGEN01_V004_REG_SW_EN_FRC_UART12FRCMISC_1AF0); //h6bc[0]

	W2BYTEMSK(REG_0AD0_CKGEN01_V004, 0x1, REG_0AD0_CKGEN01_V004_REG_CKG_S_XC_FN_0AD0); //h2b4[3:2], fn clk select, pqdd control
	W2BYTEMSK(REG_0AF0_CKGEN01_V004, 0x1, REG_0AF0_CKGEN01_V004_REG_CKG_S_XC_SRS_0AF0); //h2bc[2], srs clk select, pqdd control
	W2BYTEMSK(REG_0E84_CKGEN01_V004, 0, REG_0E84_CKGEN01_V004_REG_GATE_XC_FN_0E84); //h3a1[0], fn clk gate, pqdd control
	W2BYTEMSK(REG_1170_CKGEN01_V004, 0x1, REG_1170_CKGEN01_V004_REG_CKG_S_MCU_SC_1170); //h3a1[0], mcu sc clk select
	W2BYTEMSK(REG_11B8_CKGEN01_V004, 0x1, REG_11B8_CKGEN01_V004_REG_CKG_S_MCU_BUS_11B8); //h3a1[0], mcu sc clk bus
}

void _PATCH_INIT_XC_CLK_v5(void)
{
	//ckgen 00
	W2BYTEMSK(REG_14EC_CKGEN00_V005, 0x1, REG_14EC_CKGEN00_V005_REG_SW_EN_SMI2SCIP_14EC); //h53b[0]
	W2BYTEMSK(REG_14EC_CKGEN00_V005, 0x1, REG_14EC_CKGEN00_V005_REG_SW_EN_SMI2SCM_14EC); //h53b[1]
	W2BYTEMSK(REG_14EC_CKGEN00_V005, 0x1, REG_14EC_CKGEN00_V005_REG_SW_EN_SMI2SCMO_14EC); //h53b[2]
	W2BYTEMSK(REG_14EC_CKGEN00_V005, 0x1, REG_14EC_CKGEN00_V005_REG_SW_EN_SMI2SCNR_14EC); //h53b[4]
	W2BYTEMSK(REG_1504_CKGEN00_V005, 0x1, REG_1504_CKGEN00_V005_REG_SW_EN_SMI2SCFE_GALS_1504); //h541[2]
	W2BYTEMSK(REG_14EC_CKGEN00_V005, 0x1, REG_14EC_CKGEN00_V005_REG_SW_EN_SMI2SCBE_14EC); //h53b[5]
	W2BYTEMSK(REG_1504_CKGEN00_V005, 0x1, REG_1504_CKGEN00_V005_REG_SW_EN_SMI2SCBE_GALS_1504); //h541[1]
	W2BYTEMSK(REG_14EC_CKGEN00_V005, 0x1, REG_14EC_CKGEN00_V005_REG_SW_EN_SMI2SCTC_14EC); //h53b[8]
	W2BYTEMSK(REG_1504_CKGEN00_V005, 0x1, REG_1504_CKGEN00_V005_REG_SW_EN_SMI2SCTC_GALS_1504); //h541[3]
	//W2BYTEMSK(REG_14F4_CKGEN00_V005, 0x1, REG_14F4_CKGEN00_V005_REG_SW_EN_SMI2FRCCORE1_14F4); //h53d[10]
	//W2BYTEMSK(REG_14F4_CKGEN00_V005, 0x1, REG_14F4_CKGEN00_V005_REG_SW_EN_SMI2FRCCORE2_14F4); //h53d[11]
	//W2BYTEMSK(REG_14F4_CKGEN00_V005, 0x1, REG_14F4_CKGEN00_V005_REG_SW_EN_SMI2FRCCORE3_14F4); //h53d[12]
	//W2BYTEMSK(REG_14F4_CKGEN00_V005, 0x1, REG_14F4_CKGEN00_V005_REG_SW_EN_SMI2FRCMISC_14F4); //h53d[13]
	W2BYTEMSK(REG_14F8_CKGEN00_V005, 0x1, REG_14F8_CKGEN00_V005_REG_SW_EN_SMI2SMI_FRCCORE1_14F8); //h53e[0]
	W2BYTEMSK(REG_1504_CKGEN00_V005, 0x1, REG_1504_CKGEN00_V005_REG_SW_EN_SMI2FRC_GALS_1504); //h541[0]
	W2BYTEMSK(REG_1508_CKGEN00_V005, 0x1, REG_1508_CKGEN00_V005_REG_SW_EN_SMI2SCFE_EMI_1508); //h542[0]
	W2BYTEMSK(REG_1508_CKGEN00_V005, 0x1, REG_1508_CKGEN00_V005_REG_SW_EN_SMI2SCFE_SMI_IP_1508); //h542[1]
	//W2BYTEMSK(REG_1508_CKGEN00_V005, 0x1, REG_1508_CKGEN00_V005_REG_SW_EN_SMI2FRC_EMI_1508); //h542[2]
	W2BYTEMSK(REG_1508_CKGEN00_V005, 0x1, REG_1508_CKGEN00_V005_REG_SW_EN_SMI2FRC_R2_1508); //h542[3]

	W2BYTEMSK(REG_01D8_CKGEN00_V005, 0x1, REG_01D8_CKGEN00_V005_REG_CKG_S_SMI_01D8); //h76[3:2] smi clk select
	W2BYTEMSK(REG_1268_CKGEN00_V005, 0x0, REG_1268_CKGEN00_V005_REG_CKG_S_DISP_MFDEC_1268); //h49a[3:2] disp mfdec clk select
	//ckgen 01
	W2BYTEMSK(REG_0B18_CKGEN01_V005, 0x1, REG_0B18_CKGEN01_V005_REG_CKG_S_XC_DBG2MIU_SCIP_0B18);	// hdmi
	W2BYTEMSK(REG_1570_CKGEN01_V005, 0x1, REG_1570_CKGEN01_V005_REG_SW_EN_DAP2FRCMISC_1570); //h55c[0]
	//W2BYTEMSK(REG_1578_CKGEN01_V005, 0x1, REG_1578_CKGEN01_V005_REG_SW_EN_FRC_FCLK_2X2FRCCORE1_1578); //h55e[0]
	//W2BYTEMSK(REG_1578_CKGEN01_V005, 0x1, REG_1578_CKGEN01_V005_REG_SW_EN_FRC_FCLK_2X2FRCCORE3_1578); //h55e[2]
	//W2BYTEMSK(REG_157C_CKGEN01_V005, 0x1, REG_157C_CKGEN01_V005_REG_SW_EN_FRC_FCLK_2XPLUS2FRCCORE1_157C); //h55f[0]
	//W2BYTEMSK(REG_1580_CKGEN01_V005, 0x1, REG_1580_CKGEN01_V005_REG_SW_EN_FRC_FCLK2FRCCORE2_1580); //h560[1]
	W2BYTEMSK(REG_1588_CKGEN01_V005, 0x1, REG_1588_CKGEN01_V005_REG_SW_EN_R2_FRC2FRCMISC_1588); //h562[0]
	W2BYTEMSK(REG_15B4_CKGEN01_V005, 0x1, REG_15B4_CKGEN01_V005_REG_SW_EN_XTAL_12M2FRCMISC_15B4); //h56d[0]
	//W2BYTEMSK(REG_15C0_CKGEN01_V005, 0x1, REG_15C0_CKGEN01_V005_REG_SW_EN_XTAL_24M2FRCCORE1_15C0); //h570[0]
	//W2BYTEMSK(REG_15C0_CKGEN01_V005, 0x1, REG_15C0_CKGEN01_V005_REG_SW_EN_XTAL_24M2FRCCORE2_15C0); //h570[2]
	//W2BYTEMSK(REG_15C0_CKGEN01_V005, 0x1, REG_15C0_CKGEN01_V005_REG_SW_EN_XTAL_24M2FRCCORE3_15C0); //h570[4]
	W2BYTEMSK(REG_1B84_CKGEN01_V005, 0x1, REG_1B84_CKGEN01_V005_REG_SW_EN_MCU_NONPM2FRCCORE1_1B84); //h6e1[7]
	W2BYTEMSK(REG_1B84_CKGEN01_V005, 0x1, REG_1B84_CKGEN01_V005_REG_SW_EN_MCU_NONPM2FRCCORE2_1B84); //h6e1[8]
	W2BYTEMSK(REG_1B84_CKGEN01_V005, 0x1, REG_1B84_CKGEN01_V005_REG_SW_EN_MCU_NONPM2FRCCORE3_1B84); //h6e1[9]
	W2BYTEMSK(REG_1B84_CKGEN01_V005, 0x1, REG_1B84_CKGEN01_V005_REG_SW_EN_MCU_NONPM2FRCMISC_1B84); //h6e1[10]
	W2BYTEMSK(REG_1D88_CKGEN01_V005, 0x1, REG_1D88_CKGEN01_V005_REG_SW_EN_XTAL_24M2FRC_MBIST_1D88); //h762[8]

	W2BYTEMSK(REG_01E8_CKGEN01_V005, 0x0, REG_01E8_CKGEN01_V005_REG_CKG_S_FRC_FCLK_01E8); //h7a[3:2], frc fclk select
	W2BYTEMSK(REG_01F0_CKGEN01_V005, 0x1, REG_01F0_CKGEN01_V005_REG_CKG_S_FRC_FCLK_2X_01F0); //h7c[3:2], frc fclk_2x select
	W2BYTEMSK(REG_01F8_CKGEN01_V005, 0x1, REG_01F8_CKGEN01_V005_REG_CKG_S_FRC_FCLK_2XPLUS_01F8); //h7e[3:2], frc fclk_2xplus select
	W2BYTEMSK(REG_0AA0_CKGEN01_V005, 0x0, REG_0AA0_CKGEN01_V005_REG_CKG_S_XC_DC0_0AA0); //h2a8[4:2], xc_dc0 select
	W2BYTEMSK(REG_0AD0_CKGEN01_V005, 0x1, REG_0AD0_CKGEN01_V005_REG_CKG_S_XC_FN_0AD0); //h2b4[3:2], fn clk select
	W2BYTEMSK(REG_0E84_CKGEN01_V005, 0x0, REG_0E84_CKGEN01_V005_REG_GATE_XC_FN_0E84); //h3a1[0], fn clk gate
	W2BYTEMSK(REG_0F00_CKGEN01_V005, 0x0, REG_0F00_CKGEN01_V005_REG_CKG_S_VD_0F00); //h3c0[0], vd clk gate
	W2BYTEMSK(REG_1040_CKGEN01_V005, 0x1, REG_1040_CKGEN01_V005_REG_CKG_S_MCU_NONPM_1040); //h410[4:2], mcu nonpm select
	W2BYTEMSK(REG_1170_CKGEN01_V005, 0x1, REG_1170_CKGEN01_V005_REG_CKG_S_MCU_SC_1170); //h45c[0], mcu sc clk
	W2BYTEMSK(REG_11B8_CKGEN01_V005, 0x1, REG_11B8_CKGEN01_V005_REG_CKG_S_MCU_BUS_11B8); //h46e[0], mcu sc clk bus

	// CKGEN setup
	W2BYTEMSK(REG_12F0_CKGEN01_V005, 0x00, REG_12F0_CKGEN01_V005_REG_CKG_G_FRCPLL_SYN_12F0); // bit[0] = 0
	W2BYTEMSK(REG_12F0_CKGEN01_V005, 0x00, REG_12F0_CKGEN01_V005_REG_CKG_I_FRCPLL_SYN_12F0); // bit[1] = 0
	W2BYTEMSK(REG_12F0_CKGEN01_V005, 0x00, REG_12F0_CKGEN01_V005_REG_CKG_S_FRCPLL_SYN_12F0); // bit[3:2] = 0

	// FRCPLL setup, read only value defaul = 0, don't write value defaul = 0
    W2BYTEMSK(REG_0014_FRCPLL, FRCPLL_CONFIG_SET_0_0014,  REG_0014_FRCPLL_REG_FRCPLL_SET_0_0014);       // 0x100b_0a = 0xcc, 0x100b_0b = 0xe6 => low, Hight,8 bit
    W2BYTEMSK(REG_0018_FRCPLL, FRCPLL_CONFIG_SET_1_0018,  REG_0018_FRCPLL_REG_FRCPLL_SET_1_0018);       // 0x100b_0c = 0x1f => bit[7:0] = 0x1f, 0x100b_0d read only
    W2BYTEMSK(REG_001C_FRCPLL, FRCPLL_CONFIG_STEP_0_001C, REG_001C_FRCPLL_REG_FRCPLL_STEP_0_001C);      // 0x100b_0e = 0x1e, 0x100b_0f = 0x00
    W2BYTEMSK(REG_0020_FRCPLL, 0x00,   REG_0020_FRCPLL_REG_FRCPLL_STEP_1_0020);      // 0x100b_10 = 0x00, 0x100b_11(read only) = 0x00
    W2BYTEMSK(REG_0024_FRCPLL, FRCPLL_CONFIG_SPAN_0_0024, REG_0024_FRCPLL_REG_FRCPLL_SPAN_0_0024);      // 0x100b_12 = 0xa6, 0x100b_13 = 0x02
    W2BYTEMSK(REG_0028_FRCPLL, 0x00,   REG_0028_FRCPLL_REG_FRCPLL_SPAN_1_0028);      // 0x100b_14 = 0x00, 0x100b_15(read only) = 0x00
    W2BYTEMSK(REG_0034_FRCPLL, 0x01,   REG_0034_FRCPLL_REG_FRCPLL_SSC_SYNC_0034);    // 0x100b_1a[0] = b'1
    W2BYTEMSK(REG_0034_FRCPLL, 0x00,   REG_0034_FRCPLL_REG_FRCPLL_SSC_MODE_0034);    // 0x100b_1a[1] = b'0
    W2BYTEMSK(REG_0050_FRCPLL, 0x01,   REG_0050_FRCPLL_REG_FRCPLL_SLD_0050);         // bit[0] = b'1
    W2BYTEMSK(REG_0000_FRCPLL, FRCPLL_CONFIG_TEST_0000, REG_0000_FRCPLL_REG_FRCPLL_TEST_0000);        // 0x100b_00 = 0x12, 0x100b_01 = 0x00, 8 bit
    W2BYTEMSK(REG_0008_FRCPLL, 0x00,   REG_0008_FRCPLL_REG_FRCPLL_RST_0008);         // bit[0] = 0
    W2BYTEMSK(REG_0008_FRCPLL, 0x00,   REG_0008_FRCPLL_REG_FRCPLL_INPUT_DIV_FIRST_0008);// bit[5:4] = b'00
    W2BYTEMSK(REG_0008_FRCPLL, 0x01,  REG_0008_FRCPLL_REG_FRCPLL_LOOP_DIV_FIRST_0008); // bit[9:8] = b'01
    W2BYTEMSK(REG_000C_FRCPLL, FRCPLL_CONFIG_LOOP_DIV_SECOND_000C, REG_000C_FRCPLL_REG_FRCPLL_LOOP_DIV_SECOND_000C);// bit[7:0] = 0x03
    W2BYTEMSK(REG_000C_FRCPLL, FRCPLL_CONFIG_OUTPUT_DIV_000C, REG_000C_FRCPLL_REG_FRCPLL_OUTPUT_DIV_000C);  // bit[10:8] = b'100
    W2BYTEMSK(REG_000C_FRCPLL, 0x00,   REG_000C_FRCPLL_REG_FRCPLL_OUTPUT_DIV_FIRST_000C);// bit[13:12] = b'00
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_TEST_EN_0010);     // bit[0] = b'0
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_VCO_DIV3_EN_0010); // bit[1] = b'0
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_CP_SW_0010);       // bit[3:2] = b'00
    W2BYTEMSK(REG_0010_FRCPLL, FRCPLL_CONFIG_ICP_ICTRL_0010,   REG_0010_FRCPLL_REG_FRCPLL_ICP_ICTRL_0010);   // bit[6:4] = b'010
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_XTAL_0010);        // bit[10] = 0
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_OV_CP_SW_EN_0010); // bit[12] = 0
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_PRDT3_EN_0010);    // bit[13] = 0
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_PRDT2_EN_0010);    // bit[14] = 0
    W2BYTEMSK(REG_0010_FRCPLL, 0x00,   REG_0010_FRCPLL_REG_FRCPLL_PRDT_EN_0010);     // bit[15] = 0
    W2BYTEMSK(REG_0004_FRCPLL, 0x01, REG_0004_FRCPLL_REG_FRCPLL_PD_CLK_DIV1_0004); // bit[4] = 1
    W2BYTEMSK(REG_0004_FRCPLL, 0x01, REG_0004_FRCPLL_REG_FRCPLL_PD_CLK_DIV2_0004); // bit[8] = 1
    udelay(FRCPLL_CONFIG_UDELAY); // wait 500 us
    W2BYTEMSK(REG_0004_FRCPLL, 0x00,    REG_0004_FRCPLL_REG_FRCPLL_PD_CLK_DIV1_0004);// bit[4] = 0
    W2BYTEMSK(REG_0004_FRCPLL, 0x0000, REG_0004_FRCPLL_REG_FRCPLL_PD_CLK_DIV2_0004); // bit[8] = 0
    W2BYTEMSK(REG_0004_FRCPLL, 0x00,    REG_0004_FRCPLL_REG_FRCPLL_PD_0004);         // bit[0] = 0
}

void _PATCH_INIT_XC_CLK_v6(void)
{
    //ckgen 00

    //ckgen 01
	W2BYTEMSK(REG_0B18_CKGEN01_V006, 0x1, REG_0B18_CKGEN01_V006_REG_CKG_S_XC_DBG2MIU_SCIP_0B18); // hdmi
    W2BYTEMSK(REG_1578_CKGEN01_V006, 0x1, REG_1578_CKGEN01_V006_REG_SW_EN_FRC_FCLK_2X2FRCCORE1_1578); //h55e[0]
    W2BYTEMSK(REG_1578_CKGEN01_V006, 0x1, REG_1578_CKGEN01_V006_REG_SW_EN_FRC_FCLK2FRCCORE1_1578); //h55e[9]
    W2BYTEMSK(REG_157C_CKGEN01_V006, 0x1, REG_157C_CKGEN01_V006_REG_SW_EN_FRC_FCLK_2XPLUS2FRCCORE1_157C); //h55f[0]
    W2BYTEMSK(REG_15B4_CKGEN01_V006, 0x1, REG_15B4_CKGEN01_V006_REG_SW_EN_XTAL_12M2FRCMISC_15B4); //h56d[0]
    W2BYTEMSK(REG_15C0_CKGEN01_V006, 0x1, REG_15C0_CKGEN01_V006_REG_SW_EN_XTAL_24M2FRCCORE1_15C0); //h570[0]
    W2BYTEMSK(REG_1994_CKGEN01_V006, 0x1, REG_1994_CKGEN01_V006_REG_SW_EN_XC_FN2XC_DC0_CG_SCIP_1994); //h665[13]

    W2BYTEMSK(REG_01E8_CKGEN01_V006, 0x0, REG_01E8_CKGEN01_V006_REG_CKG_S_FRC_FCLK_01E8); //h7a[3:2], frc fclk select
    W2BYTEMSK(REG_01F0_CKGEN01_V006, 0x1, REG_01F0_CKGEN01_V006_REG_CKG_S_FRC_FCLK_2X_01F0); //h7c[3:2], frc fclk_2x select
    W2BYTEMSK(REG_01F8_CKGEN01_V006, 0x1, REG_01F8_CKGEN01_V006_REG_CKG_S_FRC_FCLK_2XPLUS_01F8); //h7e[3:2], frc fclk_2xplus select
    W2BYTEMSK(REG_0AD0_CKGEN01_V006, 0x1, REG_0AD0_CKGEN01_V006_REG_CKG_S_XC_FN_0AD0); //h2b4[3:2], fn clk select
    W2BYTEMSK(REG_0AF0_CKGEN01_V006, 0x1, REG_0AF0_CKGEN01_V006_REG_CKG_S_XC_SRS_0AF0); //h2bc[2], srs clk select
    W2BYTEMSK(REG_0E84_CKGEN01_V006, 0x0, REG_0E84_CKGEN01_V006_REG_GATE_XC_FN_0E84); //h3a1[0], fn clk gate

    //XCPLL Setting
    W2BYTEMSK(REG_0000_XCPLL_V006, 0x3, REG_0000_XCPLL_V006_REG_XCPLL_V006_TEST_0000); //BK100D_00[15:0] = 0x03
    W2BYTEMSK(REG_0004_XCPLL_V006, 0x0, REG_0004_XCPLL_V006_REG_XCPLL_V006_PD_0004); //BK100D_01[0] = b'0
    W2BYTEMSK(REG_0004_XCPLL_V006, 0x1, REG_0004_XCPLL_V006_REG_XCPLL_V006_PD_CLK_DIV1_0004); //BK100D_01[4] = b'1
    W2BYTEMSK(REG_0004_XCPLL_V006, 0x1, REG_0004_XCPLL_V006_REG_XCPLL_V006_PD_CLK_DIV2_0004); //BK100D_01[8] = b'1
    W2BYTEMSK(REG_0008_XCPLL_V006, 0x0, REG_0008_XCPLL_V006_REG_XCPLL_V006_RST_0008); //BK100D_02[0] = b'0
    W2BYTEMSK(REG_0008_XCPLL_V006, 0x0, REG_0008_XCPLL_V006_REG_XCPLL_V006_INPUT_DIV_FIRST_0008); //BK100D_02[5:4] = b'00
    W2BYTEMSK(REG_0008_XCPLL_V006, 0x1, REG_0008_XCPLL_V006_REG_XCPLL_V006_LOOP_DIV_FIRST_0008); //BK100D_02[9:8] = b'01
    W2BYTEMSK(REG_000C_XCPLL_V006, 0x4, REG_000C_XCPLL_V006_REG_XCPLL_V006_LOOP_DIV_SECOND_000C); //BK100D_03[7:0] = 0x04
    W2BYTEMSK(REG_000C_XCPLL_V006, 0x4, REG_000C_XCPLL_V006_REG_XCPLL_V006_OUTPUT_DIV_000C); //BK100D_03[10:8] = b'100
    W2BYTEMSK(REG_000C_XCPLL_V006, 0x0, REG_000C_XCPLL_V006_REG_XCPLL_V006_OUTPUT_DIV_FIRST_000C); //BK100D_03[13:12] = b'00
    W2BYTEMSK(REG_0014_XCPLL_V006, 0xF160, REG_0014_XCPLL_V006_REG_XCPLL_V006_SET_0_0014); //BK100D_05[15:0] = 0xF160
    W2BYTEMSK(REG_0018_XCPLL_V006, 0x15, REG_0018_XCPLL_V006_REG_XCPLL_V006_SET_1_0018); //BK100D_06[7:0] = 0x15
    W2BYTEMSK(REG_001C_XCPLL_V006, 0x000E, REG_001C_XCPLL_V006_REG_XCPLL_V006_STEP_0_001C); //BK100D_07[15:0] = 0x000E
    W2BYTEMSK(REG_0020_XCPLL_V006, 0x00, REG_0020_XCPLL_V006_REG_XCPLL_V006_STEP_1_0020); //BK100D_08[7:0] = 0x00
    W2BYTEMSK(REG_0024_XCPLL_V006, 0x03D9, REG_0024_XCPLL_V006_REG_XCPLL_V006_SPAN_0_0024); //BK100D_09[15:0] = 0x03D9
    W2BYTEMSK(REG_0028_XCPLL_V006, 0x00, REG_0028_XCPLL_V006_REG_XCPLL_V006_SPAN_1_0028); //BK100D_0A[7;0] = 0x00
    W2BYTEMSK(REG_0050_XCPLL_V006, 0x1, REG_0050_XCPLL_V006_REG_XCPLL_V006_SLD_0050); //BK100D_14[0] = b'1
    W2BYTEMSK(REG_0054_XCPLL_V006, 0x0, REG_0054_XCPLL_V006_REG_XCPLL_V006_PORST_0054); //BK100D_15[0] = b'0
    //Delay 500us
    udelay(500);
    W2BYTEMSK(REG_0004_XCPLL_V006, 0x0, REG_0004_XCPLL_V006_REG_XCPLL_V006_PD_0004); //BK100D_01[0] = b'0
    W2BYTEMSK(REG_0004_XCPLL_V006, 0x1, REG_0004_XCPLL_V006_REG_XCPLL_V006_PD_CLK_DIV1_0004); //BK100D_01[4] = b'1
    W2BYTEMSK(REG_0004_XCPLL_V006, 0x0, REG_0004_XCPLL_V006_REG_XCPLL_V006_PD_CLK_DIV2_0004); //BK100D_01[8] = b'0
}

void _PATCH_INIT_XC_CLK_v7(void)
{
	u16 u16PLL_CLK = 0;

	//ckgen 00 mux clk
	// H49A[3:2],mfdec
	W2BYTEMSK(REG_1268_CKGEN00_V007, 0x0, REG_1268_CKGEN00_V007_REG_CKG_S_DISP_MFDEC);
	// H2c[3:2],infra tc sc
	W2BYTEMSK(REG_00B0_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00B0_CKGEN00_V007_REG_CKG_S_INFRA_TX_SC_CK);
	// H2e[3:2],infra rx sc scmw
	W2BYTEMSK(REG_00B8_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00B8_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCMW_CK);
	// H2f[3:2],infra rx sc scip
	W2BYTEMSK(REG_00BC_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00BC_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCIP_CK);
	// H30[3:2],infra rx sc scnr
	W2BYTEMSK(REG_00C0_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00C0_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCNR_CK);
	// H31[3:2],infra rx sc scace
	W2BYTEMSK(REG_00C4_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00C4_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCACE_CK);
	// H34[3:2],infra rx sc sctcon
	W2BYTEMSK(REG_00D0_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00D0_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCTCON_CK);
	// H35[3:2],infra rx sc scsr
	W2BYTEMSK(REG_00D4_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00D4_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_SCSR_CK);
	// H36[3:2],infra rx sc frc
	W2BYTEMSK(REG_00D8_CKGEN00_V007, XC_CLK_007_INFRA_CK, REG_00D8_CKGEN00_V007_REG_CKG_S_INFRA_RX_SC_FRC_CK);

	//ckgen 01 mux clk
	// H3c0[2],vd
	W2BYTEMSK(REG_0F00_CKGEN01_V007, 0x0, REG_0F00_CKGEN01_V007_REG_CKG_S_VD);
	// H2b4[3:2],fn
	W2BYTEMSK(REG_0AD0_CKGEN01_V007, XC_CLK_007_XC_FN, REG_0AD0_CKGEN01_V007_REG_CKG_S_XC_FN);
	// H2ba[2],slow
	W2BYTEMSK(REG_0AE8_CKGEN01_V007, 0x1, REG_0AE8_CKGEN01_V007_REG_CKG_S_XC_SLOW);
	// H7A[3:2],frc fclk
	W2BYTEMSK(REG_01E8_CKGEN01_V007, 0x0, REG_01E8_CKGEN01_V007_REG_CKG_S_FRC_FCLK);
	// H7C[3:2],frc fclk 2x
	W2BYTEMSK(REG_01F0_CKGEN01_V007, 0x1, REG_01F0_CKGEN01_V007_REG_CKG_S_FRC_FCLK_2X);
	// H7E[3:2],frc fclk 2xplus
	W2BYTEMSK(REG_01F8_CKGEN01_V007, 0x1, REG_01F8_CKGEN01_V007_REG_CKG_S_FRC_FCLK_2XPLUS);

	// H3A1[0],fn clk gate
	W2BYTEMSK(REG_0E84_CKGEN01_V007, 0x0, REG_0E84_CKGEN01_V007_REG_GATE_XC_FN);

	//FRC00 mux clk
	// Hd[3:2],frc fclk 2x frccore1
	W2BYTEMSK(REG_0034_CLKGEN_FRC00, 0x0, REG_0034_CLKGEN_FRC00_REG_CKG_S_FRC_FCLK_2X_FRCCORE1);
	// Hd[11:10],frc fclk 2x frccore3
	W2BYTEMSK(REG_0034_CLKGEN_FRC00, 0x0, REG_0034_CLKGEN_FRC00_REG_CKG_S_FRC_FCLK_2X_FRCCORE3);

	//sc00 mux clk
	// H15[11:10],adc scip
	W2BYTEMSK(REG_0054_CLKGEN_SC00, 0x1, REG_0054_CLKGEN_SC00_REG_CKG_S_XC_ADC_SCIP);
	// H18[10],hdmi0 scip
	W2BYTEMSK(REG_0060_CLKGEN_SC00, 0x1, REG_0060_CLKGEN_SC00_REG_CKG_S_XC_HDMI0_SCIP);
	// H19[2],hdmi1 scip
	W2BYTEMSK(REG_0064_CLKGEN_SC00, 0x1, REG_0064_CLKGEN_SC00_REG_CKG_S_XC_HDMI1_SCIP);
	// H19[10],hdmi2 scip
	W2BYTEMSK(REG_0064_CLKGEN_SC00, 0x1, REG_0064_CLKGEN_SC00_REG_CKG_S_XC_HDMI2_SCIP);
	// H1a[2],hdmi3 scip
	W2BYTEMSK(REG_0068_CLKGEN_SC00, 0x1, REG_0068_CLKGEN_SC00_REG_CKG_S_XC_HDMI3_SCIP);
	// H23[2],dp0 scip
	W2BYTEMSK(REG_008C_CLKGEN_SC00, 0x1, REG_008C_CLKGEN_SC00_REG_CKG_S_XC_DP0_SCIP);
	// H23[10],dp1 scip
	W2BYTEMSK(REG_008C_CLKGEN_SC00, 0x1, REG_008C_CLKGEN_SC00_REG_CKG_S_XC_DP1_SCIP);
	// H24[2],dsc scip
	W2BYTEMSK(REG_0090_CLKGEN_SC00, 0x1, REG_0090_CLKGEN_SC00_REG_CKG_S_XC_DSC_SCIP);

	//sc02 mux clk
	// H66[2],ip aul clk merge
	W2BYTEMSK(REG_0198_CLKGEN_SC02, 0x0, REG_0198_CLKGEN_SC02_REG_CKG_S_XC_IP_AUL_CLK_MERGE_TMP);

	//sc02 odclk
	// H31[0],odclk
	W2BYTEMSK(REG_00C4_CLKGEN_SC02, 0x0, REG_00C4_CLKGEN_SC02_REG_V1_V2_O_ODCLK_FROM_MOD);
	// H31[1],odclk
	W2BYTEMSK(REG_00C4_CLKGEN_SC02, 0x0, REG_00C4_CLKGEN_SC02_REG_O_ODCLK_FROM_MOD);

	//FRC00 sw_en
	// H2c[0],frc fclk 2x2frccore1
	W2BYTEMSK(REG_00B0_CLKGEN_FRC00, 0x1, REG_00B0_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK_2X2FRCCORE1);
	// H2c[2],frc fclk 2x2frccore3
	W2BYTEMSK(REG_00B0_CLKGEN_FRC00, 0x1, REG_00B0_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK_2X2FRCCORE3);
	// H2d[0],frc fclk 2xplus2frccore1
	W2BYTEMSK(REG_00B4_CLKGEN_FRC00, 0x1, REG_00B4_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK_2XPLUS2FRCCORE1);
	// H2e[1],frc fclk 2x2frccore2
	W2BYTEMSK(REG_00B8_CLKGEN_FRC00, 0x1, REG_00B8_CLKGEN_FRC00_REG_SW_EN_FRC_FCLK2FRCCORE2);
	// H32[0],xtal 12m2frcmisc
	W2BYTEMSK(REG_00C8_CLKGEN_FRC00, 0x1, REG_00C8_CLKGEN_FRC00_REG_SW_EN_XTAL_12M2FRCMISC);
	// H33[0],xtal 24m2frccore1
	W2BYTEMSK(REG_00CC_CLKGEN_FRC00, 0x1, REG_00CC_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRCCORE1);
	// H33[2],xtal 24m2frccore2
	W2BYTEMSK(REG_00CC_CLKGEN_FRC00, 0x1, REG_00CC_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRCCORE2);
	// H33[4],xtal 24m2frccore3
	W2BYTEMSK(REG_00CC_CLKGEN_FRC00, 0x1, REG_00CC_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRCCORE3);
	// H3d[8],xtal 24m2frc mbist
	W2BYTEMSK(REG_00F4_CLKGEN_FRC00, 0x1, REG_00F4_CLKGEN_FRC00_REG_SW_EN_XTAL_24M2FRC_MBIST);

	//SC00 sw_en
	// H2[0],smi2scsr
	W2BYTEMSK(REG_0008_CLKGEN_SC00, 0x1, REG_0008_CLKGEN_SC00_REG_SW_EN_SMI2SCSR);
	// H6[0],smi2sctcon
	W2BYTEMSK(REG_0018_CLKGEN_SC00, 0x1, REG_0018_CLKGEN_SC00_REG_SW_EN_SMI2SCTCON);
	// H50[0],dbg2miu m2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DBG2MIU_M2SCIP);
	// H50[5],adc2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_ADC2SCIP);
	// H50[8],dbg2miu s2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_DBG2MIU_S2SCIP);
	// H50[9],gpu mfdec2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_GPU_MFDEC2SCIP);
	// H50[10],fn2scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_FN2SCIP);
	// H50[13],hdmi02scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI02SCIP);
	// H50[14],hdmi12scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI12SCIP);
	// H50[15],hdmi22scip
	W2BYTEMSK(REG_0140_CLKGEN_SC00, 0x1, REG_0140_CLKGEN_SC00_REG_SW_EN_XC_HDMI22SCIP);
	// H51[0],hdmi32scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_HDMI32SCIP);
	// H51[1],id02scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_ID02SCIP);
	// H51[2],id12scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_ID12SCIP);
	// H51[4],fn2xc_mfdec_cg_scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_MFDEC_CG_SCIP);
	// H51[6],sc2fpll2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_SC2FPLL2SCIP);
	// H51[7],slow2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_SLOW2SCIP);
	// H51[8],tgen win2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_TGEN_WIN2SCIP);
	// H51[9],vd2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XC_VD2SCIP);
	// H51[10],xtal 12m2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_12M2SCIP);
	// H51[11],xtal 24m2scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCIP);
	// H51[12],xtal ip12scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_XTAL_IP12SCIP);
	// H51[13],sidclk hd02scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD02SCIP);
	// H51[14],sidclk hd12scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD12SCIP);
	// H51[15],sidclk hd22scip
	W2BYTEMSK(REG_0144_CLKGEN_SC00, 0x1, REG_0144_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD22SCIP);
	// H52[0],sidclk hd32scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_HD32SCIP);
	// H52[4],xtal 24m2scip mbist
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCIP_MBIST);
	// H52[9],sidclk dp02scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DP02SCIP);
	// H52[10],sidclk dp12scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DP12SCIP);
	// H52[11],sidclk dsc2scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_SIDCLK_DSC2SCIP);
	// H52[12],xc dp02scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DP02SCIP);
	// H52[13],xc dp12scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DP12SCIP);
	// H52[14],xc dsc2scip
	W2BYTEMSK(REG_0148_CLKGEN_SC00, 0x1, REG_0148_CLKGEN_SC00_REG_SW_EN_XC_DSC2SCIP);
	// H53[0],fn2xc dc0 cg scip
	W2BYTEMSK(REG_014C_CLKGEN_SC00, 0x1, REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_DC0_CG_SCIP);
	// H53[1],fn2xc sub dc0 cg scip
	W2BYTEMSK(REG_014C_CLKGEN_SC00, 0x1, REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_SUB_DC0_CG_SCIP);
	// H53[2],fn2xc sub1 dc0 cg scip
	W2BYTEMSK(REG_014C_CLKGEN_SC00, 0x1, REG_014C_CLKGEN_SC00_REG_SW_EN_XC_FN2XC_SUB1_DC0_CG_SCIP);
	// H70[5], xtal 24m2scnr
	W2BYTEMSK(REG_01C0_CLKGEN_SC00, 0x1, REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCNR);
	// H70[7], xtal 24m2scnr
	W2BYTEMSK(REG_01C0_CLKGEN_SC00, 0x1, REG_01C0_CLKGEN_SC00_REG_SW_EN_XTAL_24M2SCNR_MBIST);
	// H70[8], xc fn2scnr
	W2BYTEMSK(REG_01C0_CLKGEN_SC00, 0x1, REG_01C0_CLKGEN_SC00_REG_SW_EN_XC_FN2SCNR);

	//SC01 sw_en
	// H38[0], xc gop2sctcon
	W2BYTEMSK(REG_00E0_CLKGEN_SC01, 0x1, REG_00E0_CLKGEN_SC01_REG_SW_EN_XC_GOP2SCTCON);
	// H39[0], xc od 1p2sctcon
	W2BYTEMSK(REG_00E4_CLKGEN_SC01, 0x1, REG_00E4_CLKGEN_SC01_REG_SW_EN_XC_OD_1P2SCTCON);
	// H3a[0], xc od b2p2sctcon
	W2BYTEMSK(REG_00E8_CLKGEN_SC01, 0x1, REG_00E8_CLKGEN_SC01_REG_SW_EN_XC_OD_B2P2SCTCON);
	// H43[0], xc od osd2sctcon
	W2BYTEMSK(REG_010C_CLKGEN_SC01, 0x1, REG_010C_CLKGEN_SC01_REG_SW_EN_XC_OD_OSD2SCTCON);
	// H74[9], xc fn2scsr
	W2BYTEMSK(REG_01D0_CLKGEN_SC01, 0x1, REG_01D0_CLKGEN_SC01_REG_SW_EN_XC_FN2SCSR);
	// H74[9], xc fn2sctcon
	W2BYTEMSK(REG_01D0_CLKGEN_SC01, 0x1, REG_01D0_CLKGEN_SC01_REG_SW_EN_XC_FN2SCTCON);

	//SC02 sw_en
	// H1[1], xc od2sctcon
	W2BYTEMSK(REG_0004_CLKGEN_SC02, 0x1, REG_0004_CLKGEN_SC02_REG_SW_EN_XC_OD2SCTCON);
	// Hb[7], xtal 24m2scsr
	W2BYTEMSK(REG_002C_CLKGEN_SC02, 0x1, REG_002C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCSR);
	// Hb[8], xtal 24m2sctcon
	W2BYTEMSK(REG_002C_CLKGEN_SC02, 0x1, REG_002C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCTCON);
	// H1a[0], xc od meta2sctcon
	W2BYTEMSK(REG_0068_CLKGEN_SC02, 0x1, REG_0068_CLKGEN_SC02_REG_SW_EN_XC_OD_META2SCTCON);
	// H1c[0], xc os osd meta2sctcon
	W2BYTEMSK(REG_0070_CLKGEN_SC02, 0x1, REG_0070_CLKGEN_SC02_REG_SW_EN_XC_OD_OSD_META2SCTCON);
	// H1f[3], mcu nonpm2scsr
	W2BYTEMSK(REG_007C_CLKGEN_SC02, 0x1, REG_007C_CLKGEN_SC02_REG_SW_EN_MCU_NONPM2SCSR);
	// H1f[4], mcu nonpm2sctcon
	W2BYTEMSK(REG_007C_CLKGEN_SC02, 0x1, REG_007C_CLKGEN_SC02_REG_SW_EN_MCU_NONPM2SCTCON);
	// H23[2], xtal 24m2scsr mbist
	W2BYTEMSK(REG_008C_CLKGEN_SC02, 0x1, REG_008C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCSR_MBIST);
	// H23[3], xtal 24m2sctcon mbist
	W2BYTEMSK(REG_008C_CLKGEN_SC02, 0x1, REG_008C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCTCON_MBIST);
	// H4a[0], xtal 24m2scace
	W2BYTEMSK(REG_0128_CLKGEN_SC02, 0x1, REG_0128_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCACE);
	// H4a[1], xtal 24m2scace mbist
	W2BYTEMSK(REG_0128_CLKGEN_SC02, 0x1, REG_0128_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCACE_MBIST);
	// H4d[0], smi2scace
	W2BYTEMSK(REG_0134_CLKGEN_SC02, 0x1, REG_0134_CLKGEN_SC02_REG_SW_EN_SMI2SCACE);
	// H4d[1], smi2scace gals
	W2BYTEMSK(REG_0134_CLKGEN_SC02, 0x1, REG_0134_CLKGEN_SC02_REG_SW_EN_SMI2SCACE_GALS);
	// H4f[0], xc fn2scace
	W2BYTEMSK(REG_013C_CLKGEN_SC02, 0x1, REG_013C_CLKGEN_SC02_REG_SW_EN_XC_FN2SCACE);
	// H50[0], frc fclk 2xplua2scace
	W2BYTEMSK(REG_0140_CLKGEN_SC02, 0x1, REG_0140_CLKGEN_SC02_REG_SW_EN_FRC_FCLK_2XPLUS2SCACE);
	// H52[0], xtal 24m2scmw
	W2BYTEMSK(REG_0148_CLKGEN_SC02, 0x1, REG_0148_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCMW);
	// H52[1], xtal 24m2scmw mbist
	W2BYTEMSK(REG_0148_CLKGEN_SC02, 0x1, REG_0148_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCMW_MBIST);
	// H55[0], smi2scmw
	W2BYTEMSK(REG_0154_CLKGEN_SC02, 0x1, REG_0154_CLKGEN_SC02_REG_SW_EN_SMI2SCMW);
	// H55[1], smi2scmw gals
	W2BYTEMSK(REG_0154_CLKGEN_SC02, 0x1, REG_0154_CLKGEN_SC02_REG_SW_EN_SMI2SCMW_GALS);
	// H57[0], xc fn2scmw
	W2BYTEMSK(REG_015C_CLKGEN_SC02, 0x1, REG_015C_CLKGEN_SC02_REG_SW_EN_XC_FN2SCMW);
	// H58[0], drc fclk 2xplua2scmw
	W2BYTEMSK(REG_0160_CLKGEN_SC02, 0x1, REG_0160_CLKGEN_SC02_REG_SW_EN_FRC_FCLK_2XPLUS2SCMW);
	// H5a[0], od b2p2scmw
	W2BYTEMSK(REG_0168_CLKGEN_SC02, 0x1, REG_0168_CLKGEN_SC02_REG_SW_EN_XC_OD_B2P2SCMW);
	// H5b[0], od 1p2scmw
	W2BYTEMSK(REG_016C_CLKGEN_SC02, 0x1, REG_016C_CLKGEN_SC02_REG_SW_EN_XC_OD_1P2SCMW);
	// H5c[0], dip02scmw
	W2BYTEMSK(REG_0170_CLKGEN_SC02, 0x1, REG_0170_CLKGEN_SC02_REG_SW_EN_XC_DIP02SCMW);
	// H5d[0], dip12scmw
	W2BYTEMSK(REG_0174_CLKGEN_SC02, 0x1, REG_0174_CLKGEN_SC02_REG_SW_EN_XC_DIP12SCMW);
	// H61[0], xtal 12m2scmw
	W2BYTEMSK(REG_0184_CLKGEN_SC02, 0x1, REG_0184_CLKGEN_SC02_REG_SW_EN_XTAL_12M2SCMW);
	// H64[0], dip22scmw
	W2BYTEMSK(REG_0190_CLKGEN_SC02, 0x1, REG_0190_CLKGEN_SC02_REG_SW_EN_XC_DIP22SCMW);
	// H67[0], ip aul clk merge2scace
	W2BYTEMSK(REG_019C_CLKGEN_SC02, 0x1, REG_019C_CLKGEN_SC02_REG_SW_EN_XC_IP_AUL_CLK_MERGE2SCACE_TMP);

	//XCPLL
	u16PLL_CLK = R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2_DIG)
			| (R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10_DIG) << XCPLL_4)
			| (R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12_DIG) << XCPLL_8)
			| (R2BYTEMSK(REG_0060_XCPLL_V007, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128_DIG) << XCPLL_12);

	if (u16PLL_CLK != XCPLL_REG_0007_SET) {
		//XCPLL Setting
		//BK100D_4a[7:0] = 0x00
		W2BYTEMSK(REG_0094_XCPLL_V007, 0x0, REG_0094_XCPLL_V007_REG_XCPLL_V007_SPAN_1);
		//BK100D_48[15:0] = 0x00
		W2BYTEMSK(REG_0090_XCPLL_V007, 0x0, REG_0090_XCPLL_V007_REG_XCPLL_V007_SPAN_0);
		//BK100D_46[7:0] = 0x00
		W2BYTEMSK(REG_008C_XCPLL_V007, 0x0, REG_008C_XCPLL_V007_REG_XCPLL_V007_STEP_1);
		//BK100D_44[15:0] = 0x0
		W2BYTEMSK(REG_0088_XCPLL_V007, 0x0, REG_0088_XCPLL_V007_REG_XCPLL_V007_STEP_0);
		//BK100D_42[7:0] = 0x70
		W2BYTEMSK(REG_0084_XCPLL_V007, XCPLL_REG_0007_SET_1, REG_0084_XCPLL_V007_REG_XCPLL_V007_SET_1);
		//BK100D_40[15:0] = 0xd957
		W2BYTEMSK(REG_0080_XCPLL_V007, XCPLL_REG_0007_SET_0, REG_0080_XCPLL_V007_REG_XCPLL_V007_SET_0);
		//BK100D_4e[0] = 1
		W2BYTEMSK(REG_009C_XCPLL_V007, 0x1, REG_009C_XCPLL_V007_REG_XCPLL_V007_SSC_SYNC);
		//BK100D_4e[4] = 0
		W2BYTEMSK(REG_009C_XCPLL_V007, 0x0, REG_009C_XCPLL_V007_REG_XCPLL_V007_SSC_MODE);
		//BK100D_5c[0] = 1
		W2BYTEMSK(REG_00B8_XCPLL_V007, 0x1, REG_00B8_XCPLL_V007_REG_XCPLL_V007_SLD);
		//BK100D_0e[2:0] = 0x3
		W2BYTEMSK(REG_001C_XCPLL_V007, XCPLL_REG_0007_ICTRL, REG_001C_XCPLL_V007_REG_XCPLL_V007_ICTRL);
		//BK100D_0e[8] = 0x0
		W2BYTEMSK(REG_001C_XCPLL_V007, 0x0, REG_001C_XCPLL_V007_REG_XCPLL_V007_ICTRL_SW);
		//BK100D_12[1:0] = 0x3
		W2BYTEMSK(REG_0024_XCPLL_V007,
				XCPLL_REG_0007_LOOP_DIV_FIRST,
				REG_0024_XCPLL_V007_REG_XCPLL_V007_LOOP_DIV_FIRST);
		//BK100D_14[7:0] = 0x6
		W2BYTEMSK(REG_0028_XCPLL_V007,
				XCPLL_REG_0007_LOOP_DIV_SECOND,
				REG_0028_XCPLL_V007_REG_XCPLL_V007_LOOP_DIV_SECOND);
		//BK100D_08[0] = 0x1
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x1, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2);
		//BK100D_08[4] = 0x0
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x0, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10);
		//BK100D_08[8] = 0x0
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x0, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12);
		//BK100D_08[12] = 0x0
		W2BYTEMSK(REG_0010_XCPLL_V007, 0x0, REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128);
		//BK100D_00[0] = 0x0
		W2BYTEMSK(REG_0000_XCPLL_V007, 0x0, REG_0000_XCPLL_V007_REG_XCPLL_V007_PD);
		//BK100D_00[4] = 0x1
		W2BYTEMSK(REG_0000_XCPLL_V007, 0x1, REG_0000_XCPLL_V007_REG_XCPLL_V007_PD_DROOP_BYPASS);
		//BK100D_00[8] = 0x0
		W2BYTEMSK(REG_0000_XCPLL_V007, 0x0, REG_0000_XCPLL_V007_REG_XCPLL_V007_PD_VRINGCMP);

		//Delay 500us
		udelay(XCPLL_DELAY_TIME);
		//BK100D_30[0] = 1
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x1, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2_DIG);
		//BK100D_30[4] = 0
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x0, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10_DIG);
		//BK100D_30[8] = 0
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x0, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12_DIG);
		//BK100D_30[12] = 0
		W2BYTEMSK(REG_0060_XCPLL_V007, 0x0, REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128_DIG);
	}

	//XCBPLL
	u16PLL_CLK =  (R2BYTEMSK(REG_0144_XCBPLL, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV1_DIG) << XCPLL_4)
			| (R2BYTEMSK(REG_0144_XCBPLL, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV2_DIG) << XCPLL_8)
			| (R2BYTEMSK(REG_0144_XCBPLL, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV3_DIG) << XCPLL_12);

	if (u16PLL_CLK != XCBPLL_REG_0007_SET) {
		//XCBPLL
		//BK100D_84[0] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_VCO_DIV3);
		//BK100D_84[4] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_OCC_DIV128);
		//BK100D_84[8] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_XTAL);
		//BK100D_84[12] = 0x0
		W2BYTEMSK(REG_0108_XCBPLL, 0x0, REG_0108_XCBPLL_REG_EN_XCBPLL_TEST);
		//BK100D_86[0] = 0x0
		W2BYTEMSK(REG_010C_XCBPLL, 0x0, REG_010C_XCBPLL_REG_EN_XCBPLL_PRDT);
		//BK100D_86[4] = 0x0
		W2BYTEMSK(REG_010C_XCBPLL, 0x0, REG_010C_XCBPLL_REG_EN_XCBPLL_RST);
		//BK100D_88[1:0] = 0x0
		W2BYTEMSK(REG_0110_XCBPLL, 0x0, REG_0110_XCBPLL_REG_GC_XCBPLL_INPUT_DIV);
		//BK100D_8a[1:0] = 0x0
		W2BYTEMSK(REG_0114_XCBPLL, 0x0, REG_0114_XCBPLL_REG_GC_XCBPLL_CP_SW);
		//BK100D_8a[10:8] = 0x2
		W2BYTEMSK(REG_0114_XCBPLL, XCBPLL_ICTRL, REG_0114_XCBPLL_REG_GC_XCBPLL_ICTRL);
		//BK100D_8c[1:0] = 0x0
		W2BYTEMSK(REG_0118_XCBPLL, 0x0, REG_0118_XCBPLL_REG_GC_XCBPLL_OUTPUT_DIV_FIRST);
		//BK100D_8c[10:8] = 0x0
		W2BYTEMSK(REG_0118_XCBPLL, 0x0, REG_0118_XCBPLL_REG_GC_XCBPLL_OUTPUT_DIV);
		//BK100D_8e[1:0] = 0x0
		W2BYTEMSK(REG_011C_XCBPLL, 0x0, REG_011C_XCBPLL_REG_GC_XCBPLL_LOOPDIV_FIRST);
		//BK100D_90[7:0] = 0x3c
		W2BYTEMSK(REG_0120_XCBPLL, XCBPLL_LOOPDIV_SECOND, REG_0120_XCBPLL_REG_GC_XCBPLL_LOOPDIV_SECOND);
		//BK100D_9d[15:0] = 0x10
		W2BYTEMSK(REG_0138_XCBPLL, TEST_XCBPLL, REG_0138_XCBPLL_REG_TEST_XCBPLL);
		//BK100D_82[0] = 0x1
		W2BYTEMSK(REG_0104_XCBPLL, 0x1, REG_0104_XCBPLL_REG_PD_XCBPLL_CLK_DIV5);
		//BK100D_82[4] = 0x0
		W2BYTEMSK(REG_0104_XCBPLL, 0x0, REG_0104_XCBPLL_REG_PD_XCBPLL_POSTDIV);
		//BK100D_80[0] = 0x0
		W2BYTEMSK(REG_0100_XCBPLL, 0x0, REG_0100_XCBPLL_REG_PD_XCBPLL);
		//BK100D_80[4] = 0x0
		W2BYTEMSK(REG_0100_XCBPLL, 0x0, REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV1);
		//BK100D_80[8] = 0x1
		W2BYTEMSK(REG_0100_XCBPLL, 0x1, REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV2);
		//BK100D_80[12] = 0x1
		W2BYTEMSK(REG_0100_XCBPLL, 0x1, REG_0100_XCBPLL_REG_PD_XCBPLL_CLK_DIV3);

		//Delay 500us
		udelay(XCPLL_DELAY_TIME);
		//BK100D_a2[4] = 0x0
		W2BYTEMSK(REG_0144_XCBPLL, 0x0, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV1_DIG);
		//BK100D_a2[8] = 0x1
		W2BYTEMSK(REG_0144_XCBPLL, 0x1, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV2_DIG);
		//BK100D_a2[12] = 0x1
		W2BYTEMSK(REG_0144_XCBPLL, 0x1, REG_0144_XCBPLL_REG_PD_XCBPLL_CLK_DIV3_DIG);
	}
}

static void _PATCH_XC_AID_RESET(void)
{
	//Enable SCAID binding
	W2BYTEMSK(REG_0004_SCAID_BIND_BKA3AE, 0x1, REG_0004_SCAID_BIND_BKA3AE_REG_SEC_EN_TEE_0004);

	//Set IP patgen
	W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA401, 0x780, REG_0170_PATGEN_SCALER_BKA401_REG_H_SIZE);
	W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA401, 0x438, REG_0174_PATGEN_SCALER_BKA401_REG_V_SIZE);
	W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA401, 0x1, REG_0104_PATGEN_SCALER_BKA401_REG_HSK_FORCE_SIGNAL);
	W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA401, 0x0, REG_0104_PATGEN_SCALER_BKA401_REG_BYPASS_PATGEN_SCALER);

	//SC trigger gen sel
	W2BYTEMSK(REG_0184_TRIGGER_GEN_BKA3A4, 0x4, REG_0184_TRIGGER_GEN_BKA3A4_REG_IP_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0004_TRIGGER_GEN_BKA3A5, 0x4, REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0084_TRIGGER_GEN_BKA3A5, 0x4, REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_INPUT_SRC_SEL);

	//SC clkgen
	W2BYTEMSK(REG_0AD0_CKGEN01, 0x4, REG_0AD0_CKGEN01_REG_CKG_XC_FN);
	W2BYTEMSK(REG_0AD8_CKGEN01, 0x4, REG_0AD8_CKGEN01_REG_CKG_XC_FS);
	W2BYTEMSK(REG_0AE8_CKGEN01, 0x4, REG_0AE8_CKGEN01_REG_CKG_XC_SLOW);
	W2BYTEMSK(REG_0AF0_CKGEN01, 0x4, REG_0AF0_CKGEN01_REG_CKG_XC_SRS);

	//GOP setting
	W2BYTEMSK(REG_0004_GOP0_BKA4DE, 0x1, REG_0004_GOP0_BKA4DE_REG_GOP_EN);
	W2BYTEMSK(REG_0004_GOP0_BKA4DE, 0x5, REG_0004_GOP0_BKA4DE_REG_DATA_FMT);
	W2BYTEMSK(REG_0010_GOP0_BKA4DE, 0x780, REG_0010_GOP0_BKA4DE_REG_PIC_HSIZE);
	W2BYTEMSK(REG_0014_GOP0_BKA4DE, 0x438, REG_0014_GOP0_BKA4DE_REG_PIC_VSIZE);
	W2BYTEMSK(REG_0018_GOP0_BKA4DE, 0x0, REG_0018_GOP0_BKA4DE_REG_PIC_X_POS);
	W2BYTEMSK(REG_001C_GOP0_BKA4DE, 0x0, REG_001C_GOP0_BKA4DE_REG_PIC_Y_POS);
	W2BYTEMSK(REG_0020_GOP0_BKA4DE, 0x780, REG_0020_GOP0_BKA4DE_REG_DISP_HSIZE);
	W2BYTEMSK(REG_0024_GOP0_BKA4DE, 0x438, REG_0024_GOP0_BKA4DE_REG_DISP_VSIZE);
	W2BYTEMSK(REG_0028_GOP0_BKA4DE, 0x0, REG_0028_GOP0_BKA4DE_REG_DISP_HSTR);
	W2BYTEMSK(REG_002C_GOP0_BKA4DE, 0x0, REG_002C_GOP0_BKA4DE_REG_DISP_VSTR);
	W2BYTEMSK(REG_0030_GOP0_BKA4DE, 0x0, REG_0030_GOP0_BKA4DE_REG_ALPHA_DEF0);
	W2BYTEMSK(REG_0004_GOPG_BKA4D9, 0x2, REG_0004_GOPG_BKA4D9_REG_GOP0_DEST_SEL);
	W2BYTEMSK(REG_0178_IP2_M_BKA330, 0x1, REG_0178_IP2_M_BKA330_REG_IP_OSDB_EN);

	W2BYTEMSK(REG_0E34_CKGEN01, 0x4, REG_0E34_CKGEN01_REG_CKG_XC_GOP0_DST_SCTCON);

	W2BYTEMSK(REG_0020_GOPG_BKA4D9, 0x1, REG_0020_GOPG_BKA4D9_REG_GOP0_CFG_TRIG);
	W2BYTEMSK(REG_0020_GOPG_BKA4D9, 0x1, REG_0020_GOPG_BKA4D9_REG_GOPG_CFG_TRIG);

	mdelay(10);//delay 10ms for gop aid reset

	//Restore GOP bank
	W2BYTEMSK(REG_0004_GOP0_BKA4DE, 0x0, REG_0004_GOP0_BKA4DE_REG_GOP_EN);
	W2BYTEMSK(REG_0004_GOP0_BKA4DE, 0x5, REG_0004_GOP0_BKA4DE_REG_DATA_FMT);
	W2BYTEMSK(REG_0010_GOP0_BKA4DE, 0x780, REG_0010_GOP0_BKA4DE_REG_PIC_HSIZE);
	W2BYTEMSK(REG_0014_GOP0_BKA4DE, 0x438, REG_0014_GOP0_BKA4DE_REG_PIC_VSIZE);
	W2BYTEMSK(REG_0018_GOP0_BKA4DE, 0x0, REG_0018_GOP0_BKA4DE_REG_PIC_X_POS);
	W2BYTEMSK(REG_001C_GOP0_BKA4DE, 0x0, REG_001C_GOP0_BKA4DE_REG_PIC_Y_POS);
	W2BYTEMSK(REG_0020_GOP0_BKA4DE, 0x0, REG_0020_GOP0_BKA4DE_REG_DISP_HSIZE);
	W2BYTEMSK(REG_0024_GOP0_BKA4DE, 0x0, REG_0024_GOP0_BKA4DE_REG_DISP_VSIZE);
	W2BYTEMSK(REG_0028_GOP0_BKA4DE, 0x0, REG_0028_GOP0_BKA4DE_REG_DISP_HSTR);
	W2BYTEMSK(REG_002C_GOP0_BKA4DE, 0x0, REG_002C_GOP0_BKA4DE_REG_DISP_VSTR);
	W2BYTEMSK(REG_0030_GOP0_BKA4DE, 0xff, REG_0030_GOP0_BKA4DE_REG_ALPHA_DEF0);
	W2BYTEMSK(REG_0004_GOPG_BKA4D9, 0x0, REG_0004_GOPG_BKA4D9_REG_GOP0_DEST_SEL);
	W2BYTEMSK(REG_0178_IP2_M_BKA330, 0x0, REG_0178_IP2_M_BKA330_REG_IP_OSDB_EN);

	W2BYTEMSK(REG_0E34_CKGEN01, 0x0, REG_0E34_CKGEN01_REG_CKG_XC_GOP0_DST_SCTCON);

	W2BYTEMSK(REG_0024_GOPG_BKA4D9, 0x1, REG_0024_GOPG_BKA4D9_REG_GOP0_FORCE_WR);
	W2BYTEMSK(REG_0024_GOPG_BKA4D9, 0x1, REG_0024_GOPG_BKA4D9_REG_GOPG_FORCE_WR);
	W2BYTEMSK(REG_0024_GOPG_BKA4D9, 0x0, REG_0024_GOPG_BKA4D9_REG_GOP0_FORCE_WR);
	W2BYTEMSK(REG_0024_GOPG_BKA4D9, 0x0, REG_0024_GOPG_BKA4D9_REG_GOPG_FORCE_WR);

	//Restore SC bank
	W2BYTEMSK(REG_0AD0_CKGEN01, 0x0, REG_0AD0_CKGEN01_REG_CKG_XC_FN);
	W2BYTEMSK(REG_0AD8_CKGEN01, 0x0, REG_0AD8_CKGEN01_REG_CKG_XC_FS);
	W2BYTEMSK(REG_0AE8_CKGEN01, 0x0, REG_0AE8_CKGEN01_REG_CKG_XC_SLOW);
	W2BYTEMSK(REG_0AF0_CKGEN01, 0x0, REG_0AF0_CKGEN01_REG_CKG_XC_SRS);

	W2BYTEMSK(REG_0184_TRIGGER_GEN_BKA3A4, 0x0, REG_0184_TRIGGER_GEN_BKA3A4_REG_IP_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0004_TRIGGER_GEN_BKA3A5, 0x0, REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0084_TRIGGER_GEN_BKA3A5, 0x0, REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_INPUT_SRC_SEL);

	W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA401, 0x0, REG_0170_PATGEN_SCALER_BKA401_REG_H_SIZE);
	W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA401, 0x0, REG_0174_PATGEN_SCALER_BKA401_REG_V_SIZE);
	W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA401, 0x0, REG_0104_PATGEN_SCALER_BKA401_REG_HSK_FORCE_SIGNAL);
	W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA401, 0x1, REG_0104_PATGEN_SCALER_BKA401_REG_BYPASS_PATGEN_SCALER);

	W2BYTEMSK(REG_0004_SCAID_BIND_BKA3AE, 0x0, REG_0004_SCAID_BIND_BKA3AE_REG_SEC_EN_TEE_0004);
}

static void _PATCH_TRIGGER_GEN(struct mtk_panel_priv *priv)
{
	#define TG_GEN_SW_HCOUNT (20)
	u32 u32VTT = 0;
	u32 u32HTT = 0;
	u16 u16VFreq = 0;
	u64 u64OneLineOutputUsx10000 = 0;
	u64 u64OneLineTrigUsx10000 = 0;
	u32 u32Value = 0;

	if (!priv)
		return;

	u32VTT = priv->typ_vtt;
	u32HTT = priv->typ_htt;

	if (u32HTT == 0)
		u32HTT = 1;
	if (u32VTT == 0)
		u32VTT = 1;

	u16VFreq = priv->typ_dclk / u32HTT / u32VTT;

	u64OneLineOutputUsx10000 = (u64)1000000 * 10000 / u16VFreq / u32VTT;
	u64OneLineTrigUsx10000 = 10000 * TG_GEN_SW_HCOUNT / 24;

	//patch for Trigger Gen
	W2BYTEMSK(REG_0018_TRIGGER_GEN_BKA3A4, 0x55, REG_0018_TRIGGER_GEN_BKA3A4_REG_SRC0_DMA_RD_TRIG_DLY_V);

	W2BYTEMSK((0x1474C00 + 0x0A8), 0x5, Fld(13,0,AC_MSKW10)); //reg_tgen_dummy0_trig_dly_v=5
	W2BYTEMSK((0x1474C00 + 0x0AC), 0x5, Fld(13,0,AC_MSKW10)); //reg_tgen_dummy1_trig_dly_v=5
	W2BYTEMSK(REG_0004_TRIGGER_GEN_BKA3A4, 0, REG_0004_TRIGGER_GEN_BKA3A4_REG_SRC0_INPUT_SRC_SEL);

	W2BYTEMSK(REG_0084_TRIGGER_GEN_BKA3A4, 0x1, REG_0084_TRIGGER_GEN_BKA3A4_REG_SRC1_INPUT_SRC_SEL);

	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A4, 0x0, REG_0104_TRIGGER_GEN_BKA3A4_REG_B2R_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0004_TRIGGER_GEN_BKA3A5, 0x4, REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0084_TRIGGER_GEN_BKA3A5, 0x4, REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A5, 0x4, REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL);
	W2BYTEMSK(REG_0184_TRIGGER_GEN_BKA3A5, 0x4, REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_INPUT_SRC_SEL);
	W2BYTEMSK((0x1474C00 + 0x04), 0x4, Fld(3, 0, AC_MSKB0)); //reg_frc2_input_src_sel=4
	W2BYTEMSK((0x1474C00 + 0x084), 0x2, Fld(3, 0, AC_MSKB0)); //reg_tgen_input_src_sel=0
	W2BYTEMSK((0x10A0800 + 0x004), 0x4, Fld(3,0,AC_MSKB0)); //reg_frc14=4
	W2BYTEMSK((0x10A0400 + 0x184), 0x4, Fld(3,0,AC_MSKB0)); //reg_frc15=4
	W2BYTEMSK((0x10A0600 + 0x084), 0x4, Fld(3,0,AC_MSKB0)); //frc_stage_src_sel=4

	W2BYTEMSK(REG_0018_TRIGGER_GEN_BKA3A4, 0x9, REG_0018_TRIGGER_GEN_BKA3A4_REG_SRC0_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0098_TRIGGER_GEN_BKA3A4, 0x9, REG_0098_TRIGGER_GEN_BKA3A4_REG_SRC1_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0118_TRIGGER_GEN_BKA3A4, 0x9, REG_0118_TRIGGER_GEN_BKA3A4_REG_B2R_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0198_TRIGGER_GEN_BKA3A4, 0x4, REG_0198_TRIGGER_GEN_BKA3A4_REG_IP_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0018_TRIGGER_GEN_BKA3A5, 0x9, REG_0018_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0098_TRIGGER_GEN_BKA3A5, 0x9, REG_0098_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0198_TRIGGER_GEN_BKA3A5, 0x9, REG_0198_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_DLY_V);
	// patch for gop trigger gen setting
	u32Value = 0;
	W2BYTEMSK(REG_0108_TRIGGER_GEN_BKA3A5, u32Value, REG_0108_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UP_TRIG_DLY_V);
	u32Value = (u32)(1 * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_010C_TRIGGER_GEN_BKA3A5, u32Value, REG_010C_TRIGGER_GEN_BKA3A5_REG_DISP_DS_TRIG_DLY_V);
	W2BYTEMSK(REG_0110_TRIGGER_GEN_BKA3A5, u32Value, REG_0110_TRIGGER_GEN_BKA3A5_REG_DISP_ML_TRIG_DLY_V);
	u32Value = (u32)(0x0D * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_0114_TRIGGER_GEN_BKA3A5, u32Value, REG_0114_TRIGGER_GEN_BKA3A5_REG_DISP_VS_TRIG_DLY_V);
	u32Value = (u32)(0x13 * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_0118_TRIGGER_GEN_BKA3A5, u32Value, REG_0118_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_DLY_V);
	W2BYTEMSK(REG_0170_TRIGGER_GEN_BKA3A5, (TG_GEN_SW_HCOUNT - 1), REG_0170_TRIGGER_GEN_BKA3A5_REG_DISP_SW_HTT_SIZE);
	W2BYTEMSK(REG_0174_TRIGGER_GEN_BKA3A5, 1, REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SW_H_USR_MD);
	W2BYTEMSK(REG_0174_TRIGGER_GEN_BKA3A5, 0, REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_VS_SW_TRIG);
	W2BYTEMSK(REG_0174_TRIGGER_GEN_BKA3A5, 0, REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SW_V_USR_MD);
	W2BYTEMSK(REG_0164_TRIGGER_GEN_BKA3A5, 1, REG_0164_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_OF_KEEP_EN);
	W2BYTEMSK(REG_0164_TRIGGER_GEN_BKA3A5, 8, REG_0164_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_UPD_MASK_RANGE);

	W2BYTEMSK((0x1474C00 + 0x018), 0x9, Fld(13,0,AC_MSKW10)); //reg_frc2_dma_rd_trig_dly_v=9
	W2BYTEMSK((0x1474C00 + 0x098), 0x9, Fld(13,0,AC_MSKW10)); //reg_tgen_dma_rd_trig_dly_v=9

	W2BYTEMSK(REG_0038_TRIGGER_GEN_BKA3A4, 0x1, REG_0038_TRIGGER_GEN_BKA3A4_REG_SRC0_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_00B8_TRIGGER_GEN_BKA3A4, 0x1, REG_00B8_TRIGGER_GEN_BKA3A4_REG_SRC1_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_0138_TRIGGER_GEN_BKA3A4, 0x1, REG_0138_TRIGGER_GEN_BKA3A4_REG_B2R_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_01B8_TRIGGER_GEN_BKA3A4, 2, REG_01B8_TRIGGER_GEN_BKA3A4_REG_IP_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_0038_TRIGGER_GEN_BKA3A5, 12, REG_0038_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_00B8_TRIGGER_GEN_BKA3A5, 19, REG_00B8_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_0138_TRIGGER_GEN_BKA3A5, 14, REG_0138_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UPD_TRIG_DLY_H);
	W2BYTEMSK(REG_01B8_TRIGGER_GEN_BKA3A5, 1, REG_01B8_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UPD_TRIG_DLY_H);

	W2BYTEMSK((0x1474C00 + 0x038), 0x1, Fld(3,0,AC_MSKB0)); //reg_frc2_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK((0x1474C00 + 0x0B8), 0x1, Fld(3,0,AC_MSKB0)); //reg_tgen_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK((0x1474C00 + 0x138), 0x1, Fld(3,0,AC_MSKB0)); //reg_b2r_lite0_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK((0x1474C00 + 0x1B8), 0x1, Fld(3,0,AC_MSKB0)); //reg_b2r_lite1_rw_bk_upd_trig_dly_h=1
	W2BYTEMSK(REG_0058_TRIGGER_GEN_BKA3A5, 1, REG_0058_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_REP_INTERVAL);
	// patch for ldm usage
	u32Value = (u32)(0x12 * u64OneLineOutputUsx10000 / u64OneLineTrigUsx10000);
	W2BYTEMSK(REG_0124_TRIGGER_GEN_BKA3A5, u32Value, REG_0124_TRIGGER_GEN_BKA3A5_REG_DISP_PQ_IRQ_TRIG_DLY_V);
}

static void _efuse_set_rcon(struct udevice *dev, u32 value)
{
	u16 rcon_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	bool rcon_en = 0;
	u32 rcon_max = 0;
	u32 rcon_min = 0;
	u32 rcon_default_value = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	rcon_en = priv->hw_info.rcon_enable;
	rcon_max = priv->hw_info.rcon_max;
	rcon_min = priv->hw_info.rcon_min;
	rcon_default_value = priv->hw_info.rcon_value;

	//check act bit is enabled
	if (value&_BIT(MOD_VOL_VX1_ACT_BIT)) {

		rcon_val = value & 0x3F; //bit[5:0]

		UBOOT_DEBUG("rcon value read from efuse is %d\n", rcon_val);

		//check if out of boundary
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
			if (rcon_en) {
				if (rcon_val > rcon_max || rcon_val < rcon_min)
					rcon_val = rcon_default_value;
			} else {
				rcon_val = rcon_default_value;
			}
		} else {
			if (rcon_val > RCON_MAX_VAL || rcon_val < RCON_MIN_VAL)
				rcon_val = RCON_DEF_VAL;
		}
	} else {
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0600)
			rcon_val = rcon_default_value;
		else
			rcon_val = RCON_DEF_VAL;
		UBOOT_DEBUG("RCON act value is set to default value [%d]\n", RCON_DEF_VAL);
	}

	W2BYTEMSK(REG_00E0_MODA1, rcon_val, REG_00E0_MODA1_REG_GCR_RCON_CH00);
	W2BYTEMSK(REG_00E0_MODA1, rcon_val, REG_00E0_MODA1_REG_GCR_RCON_CH01);
	W2BYTEMSK(REG_00E4_MODA1, rcon_val, REG_00E4_MODA1_REG_GCR_RCON_CH02);
	W2BYTEMSK(REG_00E4_MODA1, rcon_val, REG_00E4_MODA1_REG_GCR_RCON_CH03);
	W2BYTEMSK(REG_00E8_MODA1, rcon_val, REG_00E8_MODA1_REG_GCR_RCON_CH04);
	W2BYTEMSK(REG_00E8_MODA1, rcon_val, REG_00E8_MODA1_REG_GCR_RCON_CH05);
	W2BYTEMSK(REG_00EC_MODA1, rcon_val, REG_00EC_MODA1_REG_GCR_RCON_CH06);
	W2BYTEMSK(REG_00EC_MODA1, rcon_val, REG_00EC_MODA1_REG_GCR_RCON_CH07);
	W2BYTEMSK(REG_00F0_MODA1, rcon_val, REG_00F0_MODA1_REG_GCR_RCON_CH08);
	W2BYTEMSK(REG_00F0_MODA1, rcon_val, REG_00F0_MODA1_REG_GCR_RCON_CH09);
	W2BYTEMSK(REG_00F4_MODA1, rcon_val, REG_00F4_MODA1_REG_GCR_RCON_CH10);
	W2BYTEMSK(REG_00F4_MODA1, rcon_val, REG_00F4_MODA1_REG_GCR_RCON_CH11);
	W2BYTEMSK(REG_00F8_MODA1, rcon_val, REG_00F8_MODA1_REG_GCR_RCON_CH12);
	W2BYTEMSK(REG_00F8_MODA1, rcon_val, REG_00F8_MODA1_REG_GCR_RCON_CH13);
	W2BYTEMSK(REG_00FC_MODA1, rcon_val, REG_00FC_MODA1_REG_GCR_RCON_CH14);
	W2BYTEMSK(REG_00FC_MODA1, rcon_val, REG_00FC_MODA1_REG_GCR_RCON_CH15);
	W2BYTEMSK(REG_0100_MODA1, rcon_val, REG_0100_MODA1_REG_GCR_RCON_CH16);
	W2BYTEMSK(REG_0100_MODA1, rcon_val, REG_0100_MODA1_REG_GCR_RCON_CH17);
	W2BYTEMSK(REG_0104_MODA1, rcon_val, REG_0104_MODA1_REG_GCR_RCON_CH18);
	W2BYTEMSK(REG_0104_MODA1, rcon_val, REG_0104_MODA1_REG_GCR_RCON_CH19);
	W2BYTEMSK(REG_00E0_MODA2, rcon_val, REG_00E0_MODA2_REG_GCR_RCON_CH20);
	W2BYTEMSK(REG_00E0_MODA2, rcon_val, REG_00E0_MODA2_REG_GCR_RCON_CH21);
	W2BYTEMSK(REG_00E4_MODA2, rcon_val, REG_00E4_MODA2_REG_GCR_RCON_CH22);
	W2BYTEMSK(REG_00E4_MODA2, rcon_val, REG_00E4_MODA2_REG_GCR_RCON_CH23);
	W2BYTEMSK(REG_00E8_MODA2, rcon_val, REG_00E8_MODA2_REG_GCR_RCON_CH24);
	W2BYTEMSK(REG_00E8_MODA2, rcon_val, REG_00E8_MODA2_REG_GCR_RCON_CH25);
	W2BYTEMSK(REG_00EC_MODA2, rcon_val, REG_00EC_MODA2_REG_GCR_RCON_CH26);
	W2BYTEMSK(REG_00EC_MODA2, rcon_val, REG_00EC_MODA2_REG_GCR_RCON_CH27);
	W2BYTEMSK(REG_00F0_MODA2, rcon_val, REG_00F0_MODA2_REG_GCR_RCON_CH28);
	W2BYTEMSK(REG_00F0_MODA2, rcon_val, REG_00F0_MODA2_REG_GCR_RCON_CH29);
	W2BYTEMSK(REG_00F4_MODA2, rcon_val, REG_00F4_MODA2_REG_GCR_RCON_CH30);
	W2BYTEMSK(REG_00F4_MODA2, rcon_val, REG_00F4_MODA2_REG_GCR_RCON_CH31);
	W2BYTEMSK(REG_00F8_MODA2, rcon_val, REG_00F8_MODA2_REG_GCR_RCON_CH32);
	W2BYTEMSK(REG_00F8_MODA2, rcon_val, REG_00F8_MODA2_REG_GCR_RCON_CH33);
	W2BYTEMSK(REG_00FC_MODA2, rcon_val, REG_00FC_MODA2_REG_GCR_RCON_CH34);
	W2BYTEMSK(REG_00FC_MODA2, rcon_val, REG_00FC_MODA2_REG_GCR_RCON_CH35);
	W2BYTEMSK(REG_0100_MODA2, rcon_val, REG_0100_MODA2_REG_GCR_RCON_CH36);
	W2BYTEMSK(REG_0100_MODA2, rcon_val, REG_0100_MODA2_REG_GCR_RCON_CH37);
	W2BYTEMSK(REG_0104_MODA2, rcon_val, REG_0104_MODA2_REG_GCR_RCON_CH38);
	W2BYTEMSK(REG_0104_MODA2, rcon_val, REG_0104_MODA2_REG_GCR_RCON_CH39);
}

static bool _check_rint_frequency(void)
{
	//report single term or double term by check rint cnt and threshold
	//Return value=> true: SINGLE term, false: DOUBLE term


	if (R2BYTEMSK(REG_0160_MODA1, REG_0160_MODA1_REG_HW_RINT_EN)!= 0) {

		W2BYTEMSK(REG_0160_MODA1, RINT_THRESHOLD, REG_0160_MODA1_REG_HW_RINT_TH);

		u16 rint_cnt_val = 0;

		rint_cnt_val = R2BYTEMSK(REG_0164_MODA1, REG_0164_MODA1_REG_HW_RINT_CNT_VALUE);

		//mdelay(100);

		debug("[%s] rint cnt = %d, threshold = %d\n"
			, __func__, rint_cnt_val, RINT_THRESHOLD);

		if (rint_cnt_val > RINT_THRESHOLD)
			return false; //double term
		else
			return true; //single term

	} else {
		debug("[%s] RINT enable is FALSE\n", __func__);
		return false; // double term
	}

}


static void _efuse_set_biascon_offset(struct udevice *dev, u32 value, u32 value1, u32 value2)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	bool biascon_offset_en = false;
	u32 cal_value = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	// hw support or not
	if (priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
		if ( (value2 & _BIT(MOD_CUR_DOUBLE_ACT_BIT_VER5)) == _BIT(MOD_CUR_DOUBLE_ACT_BIT_VER5))
			biascon_offset_en = true;
		else
			biascon_offset_en = false;
	}else if (priv->pnl_lib_version == BOOT_PNL_VERSION0400) {
		biascon_offset_en = false;
	}else if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203) {
		if ( (value2 & _BIT(MOD_CUR_SINGLE_ACT_BIT_VER2)) == _BIT(MOD_CUR_SINGLE_ACT_BIT_VER2))
			biascon_offset_en = true;
		else
			biascon_offset_en = false;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
		//write reg
		if(biascon_offset_en){
			cal_value = (value >> 13) & 0xf;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH00_0168);
			cal_value = (value >> 17) & 0xf;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH01_0168);
			cal_value = (value >> 21) & 0xf;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH02_0168);
			cal_value = (value >> 25) & 0xf;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH03_0168);
			cal_value = (value1 >> 0) & 0xf;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH04_016C);
			cal_value = (value1 >> 4) & 0xf;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH05_016C);
			cal_value = (value1 >> 8) & 0xf;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH06_016C);
			cal_value = (value1 >>12) & 0xf;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH07_016C);
			cal_value = (value1 >>16) & 0xf;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH08_0170);
			cal_value = (value1 >>20) & 0xf;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH09_0170);
			cal_value = (value1 >>24) & 0xf;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH10_0170);
			cal_value = (value1 >>28) & 0xf;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH11_0170);
			cal_value = (value2 >> 0) & 0xf;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH12_0174);
			cal_value = (value2 >> 4) & 0xf;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH13_0174);
			cal_value = (value2 >> 8) & 0xf;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH14_0174);
			cal_value = (value2 >>12) & 0xf;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH15_0174);
			cal_value = 0;
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH16_0178);
			cal_value = 0;
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH17_0178);
			cal_value = 0;
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH18_0178);
			cal_value = 0;
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH19_0178);
		}else {
			cal_value = 0;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH00_0168);
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH01_0168);
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH02_0168);
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_V005_REG_BIAS_CON_OFFSET_CH03_0168);
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH04_016C);
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH05_016C);
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH06_016C);
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_V005_REG_BIAS_CON_OFFSET_CH07_016C);
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH08_0170);
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH09_0170);
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH10_0170);
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_V005_REG_BIAS_CON_OFFSET_CH11_0170);
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH12_0174);
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH13_0174);
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH14_0174);
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_V005_REG_BIAS_CON_OFFSET_CH15_0174);
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH16_0178);
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH17_0178);
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH18_0178);
			W2BYTEMSK(REG_0178_MODA1, cal_value, REG_0178_MODA1_V005_REG_BIAS_CON_OFFSET_CH19_0178);
		}
	}else {
		//write reg
		if(biascon_offset_en){
			cal_value = (value >> 14) & 0x7;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH00);
			cal_value = (value >> 17) & 0x7;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH01);
			cal_value = (value >> 20) & 0x7;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH02);
			cal_value = (value >> 23) & 0x7;
			W2BYTEMSK(REG_0168_MODA1, cal_value, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH03);
			cal_value = (value >> 26) & 0x7;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH04);
			cal_value = (value >> 29) & 0x7;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH05);
			cal_value = (value1 >> 0) & 0x7;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH06);
			cal_value = (value1 >> 3) & 0x7;
			W2BYTEMSK(REG_016C_MODA1, cal_value, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH07);
			cal_value = (value1 >> 6) & 0x7;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH08_V2);
			cal_value = (value1 >> 9) & 0x7;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH09_V2);
			cal_value = (value1 >> 12) & 0x7;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH10_V2);
			cal_value = (value1 >> 15) & 0x7;
			W2BYTEMSK(REG_0170_MODA1, cal_value, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH11_V2);
			cal_value = (value1 >> 18) & 0x7;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH12_V2);
			cal_value = (value1 >> 21) & 0x7;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH13_V2);
			cal_value = (value1 >> 24) & 0x7;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH14_V2);
			cal_value = (value1 >> 27) & 0x7;
			W2BYTEMSK(REG_0174_MODA1, cal_value, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH15_V2);
			cal_value = (value2 >> 0) & 0x7;
			W2BYTEMSK(REG_0174_MODA2, cal_value, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH32);
			cal_value = (value2 >> 3) & 0x7;
			W2BYTEMSK(REG_0174_MODA2, cal_value, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH33);
			cal_value = (value2 >> 6) & 0x7;
			W2BYTEMSK(REG_0174_MODA2, cal_value, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH34);
			cal_value = (value2 >> 9) & 0x7;
			W2BYTEMSK(REG_0174_MODA2, cal_value, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH35);
			cal_value = (value2 >> 12) & 0x7;
			W2BYTEMSK(REG_0178_MODA2, cal_value, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH36);
			cal_value = (value2 >> 15) & 0x7;
			W2BYTEMSK(REG_0178_MODA2, cal_value, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH37);
			cal_value = (value2 >> 18) & 0x7;
			W2BYTEMSK(REG_0178_MODA2, cal_value, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH38);
			cal_value = (value2 >> 21) & 0x7;
			W2BYTEMSK(REG_0178_MODA2, cal_value, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH39);
		}else {
			W2BYTEMSK(REG_0168_MODA1, 0, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH00);
			W2BYTEMSK(REG_0168_MODA1, 0, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH01);
			W2BYTEMSK(REG_0168_MODA1, 0, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH02);
			W2BYTEMSK(REG_0168_MODA1, 0, REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH03);
			W2BYTEMSK(REG_016C_MODA1, 0, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH04);
			W2BYTEMSK(REG_016C_MODA1, 0, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH05);
			W2BYTEMSK(REG_016C_MODA1, 0, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH06);
			W2BYTEMSK(REG_016C_MODA1, 0, REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH07);
			W2BYTEMSK(REG_0170_MODA1, 0, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH08_V2);
			W2BYTEMSK(REG_0170_MODA1, 0, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH09_V2);
			W2BYTEMSK(REG_0170_MODA1, 0, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH10_V2);
			W2BYTEMSK(REG_0170_MODA1, 0, REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH11_V2);
			W2BYTEMSK(REG_0174_MODA1, 0, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH12_V2);
			W2BYTEMSK(REG_0174_MODA1, 0, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH13_V2);
			W2BYTEMSK(REG_0174_MODA1, 0, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH14_V2);
			W2BYTEMSK(REG_0174_MODA1, 0, REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH15_V2);
			W2BYTEMSK(REG_0174_MODA2, 0, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH32);
			W2BYTEMSK(REG_0174_MODA2, 0, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH33);
			W2BYTEMSK(REG_0174_MODA2, 0, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH34);
			W2BYTEMSK(REG_0174_MODA2, 0, REG_0174_MODA2_REG_BIAS_CON_OFFSET_CH35);
			W2BYTEMSK(REG_0178_MODA2, 0, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH36);
			W2BYTEMSK(REG_0178_MODA2, 0, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH37);
			W2BYTEMSK(REG_0178_MODA2, 0, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH38);
			W2BYTEMSK(REG_0178_MODA2, 0, REG_0178_MODA2_REG_BIAS_CON_OFFSET_CH39);
		}
	}
}

static void _efuse_set_biascon(struct udevice *dev, u32 value, u32 value1, u32 value2)
{
	//for vby1 case, default read double term

	bool bSingleterm = false;
	u16 SingleActBitPosition = 0;
	u16 SingleBiasConMask = 0;
	u16 DoubleActBitPosition = 0;
	//u16 DoubleBiasConMask = 0;
	u16 cur_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u32 bias_single_max = 0;
	u32 bias_single_min = 0;
	u32 bias_single_default_val = 0;
	u32 bias_double_max = 0;
	u32 bias_double_min = 0;
	u32 bias_double_default_val = 0;
	bool efuseActive = false;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	bias_single_max = priv->hw_info.biascon_single_max;
	bias_single_min = priv->hw_info.biascon_single_min;
	bias_single_default_val = priv->hw_info.biascon_single_value;

	bias_double_max = priv->hw_info.biascon_double_max;
	bias_double_min = priv->hw_info.biascon_double_min;
	bias_double_default_val = priv->hw_info.biascon_double_value;

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203)
		bSingleterm = true; //just single term hw, no double term hw
	else if (priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			 priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
			 priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		bSingleterm = false;
	else
		bSingleterm = _check_rint_frequency();

	UBOOT_DEBUG("Current mode is %s\n", bSingleterm?"Single Term":"Double Term");

	if (bSingleterm==true) {
		if(priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		   priv->pnl_lib_version == BOOT_PNL_VERSION0203) {
			SingleActBitPosition = MOD_CUR_SINGLE_ACT_BIT_VER2;
			SingleBiasConMask = MOD_CUR_SINGLE_MASK;
		}else {
			SingleActBitPosition = MOD_CUR_SINGLE_ACT_BIT;
			SingleBiasConMask = MOD_CUR_SINGLE_MASK;
		}
	}else {
		if (priv->pnl_lib_version==BOOT_PNL_VERSION0500) {
			DoubleActBitPosition = MOD_CUR_DOUBLE_ACT_BIT_VER5;
			//DoubleBiasConMask = MOD_CUR_DOUBLE_MASK_VER5;
		}else {
			DoubleActBitPosition = MOD_CUR_DOUBLE_ACT_BIT;
			//DoubleBiasConMask = MOD_CUR_DOUBLE_MASK;
		}
	}

	if (bSingleterm) {
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
			if ( (value2 & _BIT(SingleActBitPosition)) == _BIT(SingleActBitPosition))
				efuseActive = true;
			else
				efuseActive = false;
		} else {
			if ( (value&_BIT(SingleActBitPosition)) == _BIT(SingleActBitPosition))
				efuseActive = true;
			else
				efuseActive = false;
		}

		if (efuseActive) {
			cur_val = (value>>MOD_CUR_SINGLE_LSB)&SingleBiasConMask; //bit[13:7]
			UBOOT_DEBUG("Dump single term biasCon = %d from efuse\n", cur_val);
			if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
 				if (cur_val > bias_single_max || cur_val < bias_single_min)
						cur_val = bias_single_default_val;
			} else {
				if (cur_val > BIASCON_SINGLE_MAX_VAL || cur_val < BIASCON_SINGLE_MIN_VAL)
					cur_val = BIASCON_DEF_VAL;
			}
		} else {
			if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0500)
				cur_val = bias_single_default_val;
			else
				cur_val = BIASCON_DEF_VAL;
			UBOOT_DEBUG("MOD CUR SINGLE ACT is 0, set default value\n");
		}
	} else {
		if (priv->pnl_lib_version==BOOT_PNL_VERSION0500) {
			if ( (value2 & _BIT(DoubleActBitPosition)) == _BIT(DoubleActBitPosition))
				efuseActive = true;
			else
				efuseActive = false;
		} else {
			if ( (value&_BIT(DoubleActBitPosition)) == _BIT(DoubleActBitPosition))
				efuseActive = true;
			else
				efuseActive = false;
		}

		UBOOT_DEBUG("Active=%d BitPosition=%d bias_max=%d bias_min=%d bias_default=%d\n",
			    efuseActive, DoubleActBitPosition, bias_double_max, bias_double_min,
			    bias_double_default_val);

		if (efuseActive) {
			if (priv->pnl_lib_version==BOOT_PNL_VERSION0500) {
				cur_val = (value>>MOD_CUR_DOUBLE_LSB_VER5)&MOD_CUR_DOUBLE_MASK_VER5; //bit[12:7]
			}else{
				cur_val = (value>>MOD_CUR_DOUBLE_LSB)&MOD_CUR_DOUBLE_MASK; //bit[21:15]
			}

			UBOOT_DEBUG("Dump double term biasCon = %d from efuse\n", cur_val);

			if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
				if (cur_val > bias_double_max || cur_val < bias_double_min)
						cur_val = bias_double_default_val;
			} else {
				if (cur_val > BIASCON_DOUBLE_MAX_VAL || cur_val < BIASCON_DOUBLE_MIN_VAL)
					cur_val = BIASCON_DEF_VAL;
			}
		} else {
			if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0300 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0500)
				cur_val = bias_double_default_val;
			else
				cur_val = BIASCON_DEF_VAL;
			UBOOT_DEBUG("MOD CUR DOUBLE ACT is 0, set default value\n");
		}
	}

	W2BYTEMSK(REG_0044_MODA1, cur_val, REG_0044_MODA1_REG_GCR_BIAS_CON);

	//set biascon offset
	_efuse_set_biascon_offset(dev, value, value1, value2);
}

static void _efuse_set_rint(struct udevice *dev, u32 value)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u16 rint_val = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	// no rint
	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		return;


	// if vby1 case, set rint to 0.
	// else if single set rint = 0, double read efuse.
	if (priv->linktype == E_LINK_VB1) {
		rint_val = 0;
		UBOOT_DEBUG("VB1 case, set rint to 0\n");
	} else {
		if (!_check_rint_frequency()) {
			UBOOT_DEBUG("Double term case, read rint from efuse\n");

			//check act bit is enabled
			if (value&_BIT(MOD_RINT_ACT_BIT)) {

				rint_val = (value>>MOD_RINT_OFFSET)&0xF; //bit[26:23]

				UBOOT_DEBUG("Dump RINT value from efuse\n");


			} else {
				rint_val = 0;
				UBOOT_DEBUG("RINT act value is 0\n");
			}
		} else {
			rint_val = 0;
		}

	}

	UBOOT_DEBUG("rint value is set to %d\n", rint_val);

	W2BYTEMSK(REG_0110_MODA1, rint_val, REG_0110_MODA1_REG_RINT_SEL_CH00);
	W2BYTEMSK(REG_0110_MODA1, rint_val, REG_0110_MODA1_REG_RINT_SEL_CH01);
	W2BYTEMSK(REG_0110_MODA1, rint_val, REG_0110_MODA1_REG_RINT_SEL_CH02);
	W2BYTEMSK(REG_0110_MODA1, rint_val, REG_0110_MODA1_REG_RINT_SEL_CH03);
	W2BYTEMSK(REG_0114_MODA1, rint_val, REG_0114_MODA1_REG_RINT_SEL_CH04);
	W2BYTEMSK(REG_0114_MODA1, rint_val, REG_0114_MODA1_REG_RINT_SEL_CH05);
	W2BYTEMSK(REG_0114_MODA1, rint_val, REG_0114_MODA1_REG_RINT_SEL_CH06);
	W2BYTEMSK(REG_0114_MODA1, rint_val, REG_0114_MODA1_REG_RINT_SEL_CH07);
	W2BYTEMSK(REG_0118_MODA1, rint_val, REG_0118_MODA1_REG_RINT_SEL_CH08);
	W2BYTEMSK(REG_0118_MODA1, rint_val, REG_0118_MODA1_REG_RINT_SEL_CH09);
	W2BYTEMSK(REG_0118_MODA1, rint_val, REG_0118_MODA1_REG_RINT_SEL_CH10);
	W2BYTEMSK(REG_0118_MODA1, rint_val, REG_0118_MODA1_REG_RINT_SEL_CH11);
	W2BYTEMSK(REG_011C_MODA1, rint_val, REG_011C_MODA1_REG_RINT_SEL_CH12);
	W2BYTEMSK(REG_011C_MODA1, rint_val, REG_011C_MODA1_REG_RINT_SEL_CH13);
	W2BYTEMSK(REG_011C_MODA1, rint_val, REG_011C_MODA1_REG_RINT_SEL_CH14);
	W2BYTEMSK(REG_011C_MODA1, rint_val, REG_011C_MODA1_REG_RINT_SEL_CH15);
	W2BYTEMSK(REG_0120_MODA1, rint_val, REG_0120_MODA1_REG_RINT_SEL_CH16);
	W2BYTEMSK(REG_0120_MODA1, rint_val, REG_0120_MODA1_REG_RINT_SEL_CH17);
	W2BYTEMSK(REG_0120_MODA1, rint_val, REG_0120_MODA1_REG_RINT_SEL_CH18);
	W2BYTEMSK(REG_0120_MODA1, rint_val, REG_0120_MODA1_REG_RINT_SEL_CH19);
	W2BYTEMSK(REG_0110_MODA2, rint_val, REG_0110_MODA2_REG_RINT_SEL_CH20);
	W2BYTEMSK(REG_0110_MODA2, rint_val, REG_0110_MODA2_REG_RINT_SEL_CH21);
	W2BYTEMSK(REG_0110_MODA2, rint_val, REG_0110_MODA2_REG_RINT_SEL_CH22);
	W2BYTEMSK(REG_0110_MODA2, rint_val, REG_0110_MODA2_REG_RINT_SEL_CH23);
	W2BYTEMSK(REG_0114_MODA2, rint_val, REG_0114_MODA2_REG_RINT_SEL_CH24);
	W2BYTEMSK(REG_0114_MODA2, rint_val, REG_0114_MODA2_REG_RINT_SEL_CH25);
	W2BYTEMSK(REG_0114_MODA2, rint_val, REG_0114_MODA2_REG_RINT_SEL_CH26);
	W2BYTEMSK(REG_0114_MODA2, rint_val, REG_0114_MODA2_REG_RINT_SEL_CH27);
	W2BYTEMSK(REG_0118_MODA2, rint_val, REG_0118_MODA2_REG_RINT_SEL_CH28);
	W2BYTEMSK(REG_0118_MODA2, rint_val, REG_0118_MODA2_REG_RINT_SEL_CH29);
	W2BYTEMSK(REG_0118_MODA2, rint_val, REG_0118_MODA2_REG_RINT_SEL_CH30);
	W2BYTEMSK(REG_0118_MODA2, rint_val, REG_0118_MODA2_REG_RINT_SEL_CH31);
	W2BYTEMSK(REG_011C_MODA2, rint_val, REG_011C_MODA2_REG_RINT_SEL_CH32);
	W2BYTEMSK(REG_011C_MODA2, rint_val, REG_011C_MODA2_REG_RINT_SEL_CH33);
	W2BYTEMSK(REG_011C_MODA2, rint_val, REG_011C_MODA2_REG_RINT_SEL_CH34);
	W2BYTEMSK(REG_011C_MODA2, rint_val, REG_011C_MODA2_REG_RINT_SEL_CH35);
	W2BYTEMSK(REG_0120_MODA2, rint_val, REG_0120_MODA2_REG_RINT_SEL_CH36);
	W2BYTEMSK(REG_0120_MODA2, rint_val, REG_0120_MODA2_REG_RINT_SEL_CH37);
	W2BYTEMSK(REG_0120_MODA2, rint_val, REG_0120_MODA2_REG_RINT_SEL_CH38);
	W2BYTEMSK(REG_0120_MODA2, rint_val, REG_0120_MODA2_REG_RINT_SEL_CH39);
}

static void _delta_path_hvsp_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	//delta path output setting
	W2BYTEMSK(REG_0E38_CKGEN01, 0x4, REG_0E38_CKGEN01_REG_CKG_XC_GOP_SCL_SCTCON);
	W2BYTEMSK(REG_0018_DELTA_PATH_BKA35B, priv->de_width, REG_0018_DELTA_PATH_BKA35B_REG_DISP_HSIZE);
	W2BYTEMSK(REG_001C_DELTA_PATH_BKA35B, priv->de_height, REG_001C_DELTA_PATH_BKA35B_REG_DISP_VSIZE);

	if(priv->out_format == E_OUTPUT_YUV444) {
		W2BYTEMSK(REG_0100_DELTA_PATH_BKA35B, 0, REG_0100_DELTA_PATH_BKA35B_REG_DELTA_CSC_OUT_BYPASS);
		W2BYTEMSK(REG_0104_DELTA_PATH_BKA35B, 1, REG_0104_DELTA_PATH_BKA35B_REG_DELTA_CSC_COL3X3_EN);
		W2BYTEMSK(REG_0104_DELTA_PATH_BKA35B, 1, REG_0104_DELTA_PATH_BKA35B_REG_DELTA_CSC_CR_ADD_128_POST_EN );
		W2BYTEMSK(REG_0104_DELTA_PATH_BKA35B, 1, REG_0104_DELTA_PATH_BKA35B_REG_DELTA_CSC_CB_ADD_128_POST_EN);
	} else {
		W2BYTEMSK(REG_0100_DELTA_PATH_BKA35B, 1, REG_0100_DELTA_PATH_BKA35B_REG_DELTA_CSC_OUT_BYPASS); //csc out bypass
	}


	W2BYTEMSK(REG_0100_DELTA_PATH_BKA35B, 1, REG_0100_DELTA_PATH_BKA35B_REG_DELTA_PATH_EN);
	W2BYTEMSK(REG_0100_DELTA_PATH_BKA35B, 1, REG_0100_DELTA_PATH_BKA35B_REG_DELTA_CSC_RANGE_BYPASS); //csc range bypass

	//hvsp setting
	//TODO: handel 1:1 and 1:2 case, need recognize resolution of main path
	W2BYTEMSK(REG_00A0_GOPG_HVSP4_BKA4DA, 0x1E00, REG_00A0_GOPG_HVSP4_BKA4DA_REG_H_SIZE);
	W2BYTEMSK(REG_00A4_GOPG_HVSP4_BKA4DA, 0x10E0, REG_00A4_GOPG_HVSP4_BKA4DA_REG_V_SIZE);
	W2BYTEMSK(REG_00A8_GOPG_HVSP4_BKA4DA, priv->de_width, REG_00A8_GOPG_HVSP4_BKA4DA_REG_SCL_H_SIZE);
	W2BYTEMSK(REG_00AC_GOPG_HVSP4_BKA4DA, priv->de_height, REG_00AC_GOPG_HVSP4_BKA4DA_REG_SCL_V_SIZE);

	//scaling ratio.
	//TODO: calcuation flow by src/dst size
	W2BYTEMSK(REG_0020_GOPG_HVSP4_BKA4DA, 0x20, REG_0020_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_HO_1);
	W2BYTEMSK(REG_0020_GOPG_HVSP4_BKA4DA, 1, REG_0020_GOPG_HVSP4_BKA4DA_REG_SCALE_HO_EN);

	W2BYTEMSK(REG_0028_GOPG_HVSP4_BKA4DA, 0x20, REG_0028_GOPG_HVSP4_BKA4DA_REG_SCALE_FACTOR_VE_1);
	W2BYTEMSK(REG_0028_GOPG_HVSP4_BKA4DA, 1, REG_0028_GOPG_HVSP4_BKA4DA_REG_SCALE_VE_EN);

	// HVSP bypass
	W2BYTEMSK(REG_0180_GOPG_HVSP4_BKA4DA, 0, REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_BYPASS);
	//H / V scaling order (H => V)
	W2BYTEMSK(REG_0180_GOPG_HVSP4_BKA4DA, 0, REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_ORDER_SEL);
	//USR MD enable
	W2BYTEMSK(REG_0180_GOPG_HVSP4_BKA4DA, 1, REG_0180_GOPG_HVSP4_BKA4DA_REG_HVSP_USR_MD);
}

u32 _align_floor(u32 input, u8 alignNum)
{
	if (alignNum > 0)
		input = (input/alignNum) * alignNum;
	return input;
}

u32 _tgen_target_vde(u32 u32DtsVde)
{
	u32 u32TargetVTT = TGEN_VDE_ST_2160;

	if (u32DtsVde == TGEN_VDE_4320)
		u32TargetVTT = TGEN_VDE_ST_4320;
	else if (u32DtsVde == TGEN_VDE_2160)
		u32TargetVTT = TGEN_VDE_ST_2160;
	else if (u32DtsVde <= TGEN_VDE_1080)
		u32TargetVTT = u32DtsVde*100*TGEN_VDE_ST_1080/1080/100;
	else
		u32TargetVTT = TGEN_VDE_ST_2160;

	return u32TargetVTT;
}

static u32 _tgen_target_VTTVBuf(u32 u32DtsVde)
{
	u32 u32TargetVTTBuf = TGEN_VDE_ST_2160;

	if (u32DtsVde == TGEN_VDE_4320)
		u32TargetVTTBuf = TGEN_VTTV_BUF_4320;
	else if (u32DtsVde == TGEN_VDE_2160)
		u32TargetVTTBuf = TGEN_VTTV_BUF_2160;
	else if (u32DtsVde <= TGEN_VDE_1080)
		u32TargetVTTBuf = TGEN_VTTV_BUF_1080;
	else
		u32TargetVTTBuf = TGEN_VTTV_BUF_2160;

	return u32TargetVTTBuf;
}

static void _PATCH_XCPLL_CLK_V5(en_output_timing timing)
{
#define XCPLL_SET0_620M                 (0x717F)
#define XCPLL_SET1_620M                 (0x21)
#define XCPLL_STEP0_620M                (0x21)
#define XCPLL_SPAN0_620M                (0x0286)
#define XCPLL_SET0_720M                 (0xCCCD)
#define XCPLL_SET1_720M                 (0x1C)
#define XCPLL_STEP0_720M                (0x19)
#define XCPLL_SPAN0_720M                (0x02EE)
	// When VRR144, XCPLL SLD need to toggle, to make sure PLL SET change
	// 4k2k144, XCPLL should be 720MHz
	// otherwise, should be 630MHz.
	if (timing == E_4K2K_144HZ) {
		W2BYTEMSK(REG_0014_XCPLL, XCPLL_SET0_720M, REG_0014_XCPLL_REG_XCPLL_SET_0_0014); //730M =0x67ce
		W2BYTEMSK(REG_0018_XCPLL, XCPLL_SET1_720M, REG_0018_XCPLL_REG_XCPLL_SET_1_0018); //730M =0x1c
		W2BYTEMSK(REG_001C_XCPLL, XCPLL_STEP0_720M, REG_001C_XCPLL_REG_XCPLL_STEP_0_001C); //730M 0x18 +- 1% ssc
		W2BYTEMSK(REG_0024_XCPLL, XCPLL_SPAN0_720M, REG_0024_XCPLL_REG_XCPLL_SPAN_0_0024); //730M 0x2f9
		W2BYTEMSK(REG_0050_XCPLL, 0x01, REG_0050_XCPLL_REG_XCPLL_SLD_0050); //SLD toggle
	} else {
		W2BYTEMSK(REG_0014_XCPLL, XCPLL_SET0_620M, REG_0014_XCPLL_REG_XCPLL_SET_0_0014);
		W2BYTEMSK(REG_0018_XCPLL, XCPLL_SET1_620M, REG_0018_XCPLL_REG_XCPLL_SET_1_0018);
		W2BYTEMSK(REG_001C_XCPLL, XCPLL_STEP0_620M, REG_001C_XCPLL_REG_XCPLL_STEP_0_001C);
		W2BYTEMSK(REG_0024_XCPLL, XCPLL_SPAN0_620M, REG_0024_XCPLL_REG_XCPLL_SPAN_0_0024);
		W2BYTEMSK(REG_0050_XCPLL, 0x01, REG_0050_XCPLL_REG_XCPLL_SLD_0050); //SLD toggle
	}
}

int mtk_tgen_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 alignNum = 0;
	u32 u32TargetVdeStart = 0;
	u32 u32TargetVTTVBuf = 0;
	u32 u32DtsVbp = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}

	//HAPS test, need to enable this bit first.
	//Let tool can switch ch5 to read scaler bank.
	W2BYTEMSK(0x60041C, 0x4,Fld(4,0,AC_MSKB0));

	// for video mute, enable render blending
	W2BYTEMSK(REG_0004_BLEND_TOP_BKA36B, 1, REG_0004_BLEND_TOP_BKA36B_REG_LAYER0_OFF);
	W2BYTEMSK(REG_000C_OSDB_COLOV_BKA3ED, 1, REG_000C_OSDB_COLOV_BKA3ED_REG_COLOV_SET_BLACK_DBF_EN);
	W2BYTEMSK(REG_0010_OSDB_COLOV_BKA3ED, 1, REG_0010_OSDB_COLOV_BKA3ED_REG_COLOV_SET_BLACK_MAIN_EN);

	//Patch for enable xc mcu clk.
	switch (priv->pnl_lib_version)  {
	case BOOT_PNL_VERSION0203:
	case BOOT_PNL_VERSION0200:
		_PATCH_INIT_XC_CLK();
		_PATCH_INIT_XC_CLK_v2();
		break;
	case BOOT_PNL_VERSION0300:
		_PATCH_INIT_XC_CLK();
		_PATCH_INIT_XC_CLK_v2();
		_PATCH_INIT_XC_CLK_v3();
		break;
	case BOOT_PNL_VERSION0400:
		_PATCH_INIT_XC_CLK_v4();
		break;
	case BOOT_PNL_VERSION0500:
		_PATCH_INIT_XC_CLK_v5();
		_PATCH_XCPLL_CLK_V5(priv->out_timing);
		break;
	case BOOT_PNL_VERSION0600:
		_PATCH_INIT_XC_CLK_v6();
	break;
	case BOOT_PNL_VERSION0700:
		_PATCH_INIT_XC_CLK_v7();
	break;
	default:
		_PATCH_INIT_XC_CLK();
		break;
	}

//#ifdef CONFIG_HAPS
#if 0
	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_TS_MD);
	W2BYTEMSK(REG_004C_TGEN_MAIN_BKA3A0, 0x112F, REG_004C_TGEN_MAIN_BKA3A0_REG_HTT);
	W2BYTEMSK(REG_008C_TGEN_MAIN_BKA3A0, 0x8C9, REG_008C_TGEN_MAIN_BKA3A0_REG_VTT);
	W2BYTEMSK(REG_0050_TGEN_MAIN_BKA3A0, 0, REG_0050_TGEN_MAIN_BKA3A0_REG_HSYNC_ST);
	W2BYTEMSK(REG_0054_TGEN_MAIN_BKA3A0, 0x3, REG_0054_TGEN_MAIN_BKA3A0_REG_HSYNC_END);
	W2BYTEMSK(REG_0058_TGEN_MAIN_BKA3A0, 0x30, REG_0058_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_ST);
	W2BYTEMSK(REG_005C_TGEN_MAIN_BKA3A0, 0xF2F, REG_005C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_END);
	W2BYTEMSK(REG_0060_TGEN_MAIN_BKA3A0, 0x30, REG_0060_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_ST);
	W2BYTEMSK(REG_0064_TGEN_MAIN_BKA3A0, 0xF2F, REG_0064_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_END);
	W2BYTEMSK(REG_0068_TGEN_MAIN_BKA3A0, 0x30, REG_0068_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_ST);
	W2BYTEMSK(REG_006C_TGEN_MAIN_BKA3A0, 0xF2f, REG_006C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_END);
	W2BYTEMSK(REG_0090_TGEN_MAIN_BKA3A0, 0, REG_0090_TGEN_MAIN_BKA3A0_REG_VSYNC_ST);
	W2BYTEMSK(REG_0094_TGEN_MAIN_BKA3A0, 0x0, REG_0094_TGEN_MAIN_BKA3A0_REG_VSYNC_END);
	W2BYTEMSK(REG_0098_TGEN_MAIN_BKA3A0, 0x1E, REG_0098_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_ST);
	W2BYTEMSK(REG_009C_TGEN_MAIN_BKA3A0, 0x88D, REG_009C_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_END);
	W2BYTEMSK(REG_00A0_TGEN_MAIN_BKA3A0, 0x1E, REG_00A0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_ST);
	W2BYTEMSK(REG_00A4_TGEN_MAIN_BKA3A0, 0x88D, REG_00A4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_END);
	W2BYTEMSK(REG_00A8_TGEN_MAIN_BKA3A0, 0x1E, REG_00A8_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_ST);
	W2BYTEMSK(REG_00AC_TGEN_MAIN_BKA3A0, 0x88D, REG_00AC_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_END);
	W2BYTEMSK(REG_01F4_TGEN_MAIN_BKA3A0, 0, REG_01F4_TGEN_MAIN_BKA3A0_REG_M_DELTA);
	W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, 0, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END);
	W2BYTEMSK(REG_01F8_TGEN_MAIN_BKA3A0, 0, REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND);
	W2BYTEMSK(REG_01FC_TGEN_MAIN_BKA3A0, 0xFFFF, REG_01FC_TGEN_MAIN_BKA3A0_REG_PANEL_UPPER_BOUND);
	W2BYTEMSK(REG_0084_TGEN_MAIN_BKA3A0, 1, REG_0084_TGEN_MAIN_BKA3A0_REG_EVEN_VTT_VCNT_EN);
	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_ODCLK);
	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_XTALI);
	W2BYTEMSK(REG_0008_TGEN_MAIN_BKA3A0, 1, REG_0008_TGEN_MAIN_BKA3A0_REG_TGEN_VIDEO_EN);
	W2BYTEMSK(REG_00C0_TGEN_MAIN_BKA3A0, 0x30, REG_00C0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_ST);
	W2BYTEMSK(REG_00C4_TGEN_MAIN_BKA3A0, 0xF2F, REG_00C4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_END);
	W2BYTEMSK(REG_0100_TGEN_MAIN_BKA3A0, 0x30, REG_0100_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_ST);
	W2BYTEMSK(REG_0104_TGEN_MAIN_BKA3A0, 0x88D, REG_0104_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_END);

	//set disp domain trigger gen setting, ref to tgen sync.
	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A5, 0x4, REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL);
#else
	if (!priv->cus_info.moni_p_en) {
	//Vde start protect
		u32TargetVdeStart = _tgen_target_vde(priv->de_height);
		u32TargetVTTVBuf = _tgen_target_VTTVBuf(priv->de_height);

		if ((priv->de_width == TIMING_4K_H_ACTIVE && priv->de_height == TIMING_4K_V_ACTIVE) &&
			(priv->pnl_lib_version == BOOT_PNL_VERSION0400 || priv->pnl_lib_version == BOOT_PNL_VERSION0500))
			u32TargetVdeStart = u32TargetVdeStart - TGEN_PIXELSHIFT_BUF;

		if (u32TargetVdeStart > priv->de_vstart) {
			u32DtsVbp = priv->de_vstart - (priv->vsync_st+priv->vsync_w);
			priv->de_vstart = u32TargetVdeStart;
			priv->vsync_st = u32TargetVdeStart - priv->vsync_w - u32DtsVbp;
		}

		if (priv->de_vstart > (priv->typ_vtt - priv->de_height - u32TargetVTTVBuf)) {
			u32DtsVbp = priv->de_vstart - (priv->vsync_st + priv->vsync_w);
			priv->de_vstart = priv->typ_vtt - priv->de_height - u32TargetVTTVBuf;
			if (priv->de_vstart > (priv->vsync_w + u32DtsVbp))
				priv->vsync_st = priv->de_vstart - priv->vsync_w - u32DtsVbp;
			else
				priv->vsync_st = 0;
		}
	}

	UBOOT_DEBUG("Vde start protect\n");
	UBOOT_DEBUG("u32TargetVdeStart %d\n", u32TargetVdeStart);
	UBOOT_DEBUG("u32DtsVbp %d\n", u32DtsVbp);
	UBOOT_DEBUG("priv->de_vstart %d\n", priv->de_vstart);
	UBOOT_DEBUG("priv->vsync_st %d\n", priv->vsync_st);

	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_TS_MD);	//legacy mode.

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0400
		|| priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
		// 1p aligned
	} else if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
		alignNum = (priv->lanes > TGEN_2P)?priv->lanes:TGEN_2P; // 2p
		priv->de_hstart = _align_floor(priv->de_hstart, alignNum);
		priv->de_width = _align_floor(priv->de_width, alignNum);
	} else {
		alignNum = (priv->lanes > TGEN_4P)?priv->lanes:TGEN_4P; // 4p
		priv->de_hstart = _align_floor(priv->de_hstart, alignNum);
		priv->de_width = _align_floor(priv->de_width, alignNum);
	}

	W2BYTEMSK(REG_004C_TGEN_MAIN_BKA3A0, priv->typ_htt -1, REG_004C_TGEN_MAIN_BKA3A0_REG_HTT);
	W2BYTEMSK(REG_008C_TGEN_MAIN_BKA3A0, priv->typ_vtt -1, REG_008C_TGEN_MAIN_BKA3A0_REG_VTT);

	W2BYTEMSK(REG_0050_TGEN_MAIN_BKA3A0, 0, REG_0050_TGEN_MAIN_BKA3A0_REG_HSYNC_ST);
	W2BYTEMSK(REG_0054_TGEN_MAIN_BKA3A0, priv->hsync_w - 1, REG_0054_TGEN_MAIN_BKA3A0_REG_HSYNC_END);

	W2BYTEMSK(REG_0058_TGEN_MAIN_BKA3A0, priv->de_hstart, REG_0058_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_ST);
	W2BYTEMSK(REG_005C_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1, REG_005C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_END);
	W2BYTEMSK(REG_0060_TGEN_MAIN_BKA3A0, priv->de_hstart, REG_0060_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_ST);
	W2BYTEMSK(REG_0064_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1, REG_0064_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_V_END);

	//set tcon de for sony justscan orbit case
	//the value is equal to panel DE
	W2BYTEMSK(REG_0070_TGEN_MAIN_BKA3A0, priv->de_hstart, REG_0070_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_TCON_ST);
	W2BYTEMSK(REG_0074_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1, REG_0074_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_TCON_END);

	//GFX?
	W2BYTEMSK(REG_0068_TGEN_MAIN_BKA3A0, priv->de_hstart, REG_0068_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_ST);
	W2BYTEMSK(REG_006C_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1, REG_006C_TGEN_MAIN_BKA3A0_REG_HDE_FRAME_G_END);

	//disp lb Hsize
	W2BYTEMSK(REG_0018_DISP_LB_BKA326, priv->de_width, REG_0018_DISP_LB_BKA326_REG_DISP_HSIZE);

	W2BYTEMSK(REG_0090_TGEN_MAIN_BKA3A0, priv->vsync_st, REG_0090_TGEN_MAIN_BKA3A0_REG_VSYNC_ST);
	W2BYTEMSK(REG_0014_TGEN_OUTPUT_BKA3A3, 0, REG_0014_TGEN_OUTPUT_BKA3A3_REG_TGEN_TO_TRIG_GEN_VSYNC_VCNT);  // to trigger gen vsync : same as vsync start

	W2BYTEMSK(REG_0094_TGEN_MAIN_BKA3A0, priv->vsync_st + priv->vsync_w - 1, REG_0094_TGEN_MAIN_BKA3A0_REG_VSYNC_END);
	W2BYTEMSK(REG_0098_TGEN_MAIN_BKA3A0, priv->de_vstart, REG_0098_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_ST);
	W2BYTEMSK(REG_009C_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1, REG_009C_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_END);
	W2BYTEMSK(REG_00A0_TGEN_MAIN_BKA3A0, priv->de_vstart, REG_00A0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_ST);
	W2BYTEMSK(REG_00A4_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1, REG_00A4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_V_END);

	//set tcon de for sony justscan orbit case
	//the value is equal to panel DE
	W2BYTEMSK(REG_00B0_TGEN_MAIN_BKA3A0, priv->de_vstart, REG_00B0_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_TCON_ST);
	W2BYTEMSK(REG_00B4_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1, REG_00B4_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_TCON_END);

	//GFX?
	W2BYTEMSK(REG_00A8_TGEN_MAIN_BKA3A0, priv->de_vstart, REG_00A8_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_ST);
	W2BYTEMSK(REG_00AC_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1, REG_00AC_TGEN_MAIN_BKA3A0_REG_VDE_FRAME_G_END);

	//disp lb Vsize
	W2BYTEMSK(REG_001C_DISP_LB_BKA326, priv->de_height, REG_001C_DISP_LB_BKA326_REG_DISP_VSIZE);

	W2BYTEMSK(REG_01F4_TGEN_MAIN_BKA3A0, 0xFFFF, REG_01F4_TGEN_MAIN_BKA3A0_REG_M_DELTA);  // m delta
	W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, priv->min_vtt_panelprotect, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END); // protect v endi

	if ((priv->de_vstart + priv->de_height) > priv->min_vtt_panelprotect) { //if Vde_end is after Vmin then use Vde_end as lower bound
		W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, priv->de_vstart + priv->de_height, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END); // protect v end
		W2BYTEMSK(REG_01F8_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height, REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND);
	} else {
		W2BYTEMSK(REG_0008_TGEN_FRAMELOCK_BKA3A2, priv->min_vtt_panelprotect, REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END); // protect v end
		W2BYTEMSK(REG_01F8_TGEN_MAIN_BKA3A0, priv->min_vtt_panelprotect, REG_01F8_TGEN_MAIN_BKA3A0_REG_PANEL_LOWER_BOUND);
	}
	W2BYTEMSK(REG_01FC_TGEN_MAIN_BKA3A0, priv->max_vtt_panelprotect, REG_01FC_TGEN_MAIN_BKA3A0_REG_PANEL_UPPER_BOUND);

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600)
		W2BYTEMSK(REG_0084_TGEN_MAIN_BKA3A0, 0, REG_0084_TGEN_MAIN_BKA3A0_REG_EVEN_VTT_VCNT_EN);
	else
		W2BYTEMSK(REG_0084_TGEN_MAIN_BKA3A0, 1, REG_0084_TGEN_MAIN_BKA3A0_REG_EVEN_VTT_VCNT_EN);

	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_XTALI);

	W2BYTEMSK(REG_0008_TGEN_MAIN_BKA3A0, 1, REG_0008_TGEN_MAIN_BKA3A0_REG_TGEN_VIDEO_EN); // only enable window 0

	W2BYTEMSK(REG_0004_TGEN_MAIN_BKA3A0, 0, REG_0004_TGEN_MAIN_BKA3A0_REG_TGEN_SW_RST_ODCLK);

	W2BYTEMSK(REG_00C0_TGEN_MAIN_BKA3A0, priv->de_hstart, REG_00C0_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_ST);
	W2BYTEMSK(REG_00C4_TGEN_MAIN_BKA3A0, priv->de_hstart + priv->de_width - 1, REG_00C4_TGEN_MAIN_BKA3A0_REG_HDE_VIDEO0_END);
	W2BYTEMSK(REG_0100_TGEN_MAIN_BKA3A0, priv->de_vstart, REG_0100_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_ST);
	W2BYTEMSK(REG_0104_TGEN_MAIN_BKA3A0, priv->de_vstart + priv->de_height - 1, REG_0104_TGEN_MAIN_BKA3A0_REG_VDE_VIDEO0_END);

	//set disp domain trigger gen setting, ref to tgen sync.
	W2BYTEMSK(REG_0104_TRIGGER_GEN_BKA3A5, 0x4, REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL);

	//For main video_out 120hz, GFX 60HZ output case,
	//need to reset gfx every 2 vsync
	if (priv->out_timing == E_4K2K_120HZ || priv->out_timing == E_4K2K_144HZ ||
	    priv->out_timing == E_4K1K_240HZ || priv->out_timing == E_5K2K_60HZ)
		W2BYTEMSK(REG_004C_TGEN_OUTPUT_BKA3A3, 0x1, REG_004C_TGEN_OUTPUT_BKA3A3_REG_TGEN_TO_GOP_REF_MASK_EN);

	//sw patch for reset gop-sc aid binding
	if (priv->pnl_lib_version == BOOT_PNL_VERSION0100)
		_PATCH_XC_AID_RESET();

	_PATCH_TRIGGER_GEN(priv);

#endif
	return 0;

}

int mtk_delta_tgen_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}

	W2BYTEMSK(REG_0004_TGEN_REGEN_BKA39C, 0, REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_NP_MD);

	W2BYTEMSK(REG_0044_TGEN_REGEN_BKA39C, 1, REG_0044_TGEN_REGEN_BKA39C_REG_HCNT_REGEN_CLR_EN);
	W2BYTEMSK(REG_0084_TGEN_REGEN_BKA39C, 1, REG_0084_TGEN_REGEN_BKA39C_REG_VCNT_REGEN_CLR_EN);

	W2BYTEMSK(REG_007C_TGEN_REGEN_BKA39C, 0, REG_007C_TGEN_REGEN_BKA39C_REG_REGEN_CNT_CLR_HCNT);
	W2BYTEMSK(REG_00BC_TGEN_REGEN_BKA39C, 0x2, REG_00BC_TGEN_REGEN_BKA39C_REG_REGEN_CNT_CLR_VCNT);

	//H timing
	W2BYTEMSK(REG_004C_TGEN_REGEN_BKA39C, priv->typ_htt - 1, REG_004C_TGEN_REGEN_BKA39C_REG_HTT);
	W2BYTEMSK(REG_0050_TGEN_REGEN_BKA39C, priv->hsync_st, REG_0050_TGEN_REGEN_BKA39C_REG_HSYNC_ST);
	W2BYTEMSK(REG_0054_TGEN_REGEN_BKA39C, priv->hsync_st + priv->hsync_w - 1, REG_0054_TGEN_REGEN_BKA39C_REG_HSYNC_END);
	W2BYTEMSK(REG_0058_TGEN_REGEN_BKA39C, priv->de_hstart, REG_0058_TGEN_REGEN_BKA39C_REG_HDE_FRAME_ST);
	W2BYTEMSK(REG_005C_TGEN_REGEN_BKA39C, priv->de_hstart + priv->de_width - 1, REG_005C_TGEN_REGEN_BKA39C_REG_HDE_FRAME_END);
	W2BYTEMSK(REG_0070_TGEN_REGEN_BKA39C, priv->de_hstart, REG_0070_TGEN_REGEN_BKA39C_REG_HDE_FRAME_TCON_ST_V3);
	W2BYTEMSK(REG_0074_TGEN_REGEN_BKA39C, priv->de_hstart + priv->de_width - 1, REG_0074_TGEN_REGEN_BKA39C_REG_HDE_FRAME_TCON_END_V3);

	//V timing
	W2BYTEMSK(REG_008C_TGEN_REGEN_BKA39C, priv->typ_vtt - 1, REG_008C_TGEN_REGEN_BKA39C_REG_VTT);
	W2BYTEMSK(REG_0090_TGEN_REGEN_BKA39C, priv->vsync_st, REG_0090_TGEN_REGEN_BKA39C_REG_VSYNC_ST);
	W2BYTEMSK(REG_0094_TGEN_REGEN_BKA39C, priv->vsync_st + priv->vsync_w - 1, REG_0094_TGEN_REGEN_BKA39C_REG_VSYNC_END);
	W2BYTEMSK(REG_0098_TGEN_REGEN_BKA39C, priv->de_vstart, REG_0098_TGEN_REGEN_BKA39C_REG_VDE_FRAME_ST);
	W2BYTEMSK(REG_009C_TGEN_REGEN_BKA39C, priv->de_vstart + priv->de_height - 1, REG_009C_TGEN_REGEN_BKA39C_REG_VDE_FRAME_END);
	W2BYTEMSK(REG_00B0_TGEN_REGEN_BKA39C, priv->de_vstart, REG_00B0_TGEN_REGEN_BKA39C_REG_VDE_FRAME_TCON_ST_V3);
	W2BYTEMSK(REG_00B4_TGEN_REGEN_BKA39C, priv->de_vstart + priv->de_height - 1, REG_00B4_TGEN_REGEN_BKA39C_REG_VDE_FRAME_TCON_END_V3);

	//sw rst
	W2BYTEMSK(REG_0004_TGEN_REGEN_BKA39C, 0, REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_SW_RST_XTALI);
	W2BYTEMSK(REG_0004_TGEN_REGEN_BKA39C, 0, REG_0004_TGEN_REGEN_BKA39C_REG_TGEN_SW_RST_ODCLK);


	_delta_path_hvsp_setting(dev);
	return 0;
}


int mtk_out_if_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}

	//clk setting

	if (priv->linktype == E_LINK_VB1) {
		switch (priv->out_timing) {

		case E_FHD_60HZ:
			_vby1_v_fhd_60HZ(dev);
		break;
		case E_FHD_120HZ:
			_vby1_v_fhd_120HZ(dev);
		break;
		case E_4K2K_60HZ:
		case E_4K1K_120HZ:
			_vby1_v_4k_60HZ(dev);
		break;
		case E_4K2K_120HZ:
		case E_4K2K_144HZ:
		case E_4K1K_240HZ:
		case E_5K2K_60HZ:
			_vby1_v_4k_120HZ(dev);
		break;
		case E_8K4K_60HZ:
		case E_5K2K_120HZ:
		if (priv->out_format == E_OUTPUT_YUV422)
			_vby1_v_8k422_60HZ(dev);
		else
			_vby1_v_8k_60HZ(dev);
		break;
		case E_8K4K_120HZ:
			_vby1_v_8k_120HZ();
		break;
		case E_8K4K_144HZ:
			_vby1_v_8k_144HZ();
		break;
		default:
			UBOOT_DEBUG("Video OUTPUT TIMING Not Support\n");
			return -EINVAL;
		break;
		}

		//ToDo:Add Fixed H-backporch code.

		//VBY1 byte-mode
		_vby1_set_byte_mode(dev);
	}

	if (priv->linktype == E_LINK_LVDS)
		_lvds_v_fhd_60HZ(dev);

	_vby1_set_mft(dev);
	_vby1_set_SCTCON_MISC(dev);

	//h/v sync polarity
	W2BYTEMSK(REG_0004_MODV12, priv->hsync_pol, REG_0004_MODV12_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV12, priv->vsync_pol, REG_0004_MODV12_REG_VBY1_VS_INV);

	_vby1_seri_data_sel(dev);

	//lane order setting
	_vby1_lane_order(dev);

	//fifo reset (video path)
	W2BYTEMSK(REG_0150_MODD1, 0x1, REG_0150_MODD1_REG_V1_SW_FORCE_FIX_TRIG);
	W2BYTEMSK(REG_0150_MODD1, 0x0, REG_0150_MODD1_REG_V1_SW_FORCE_FIX_TRIG);

#ifdef CONFIG_HAPS
	UBOOT_DEBUG("!!!! HAPS case !!!!!!\n");
	_hfrc_setting_for_HAPS();
#endif

	return 0;
}

int mtk_ext_video_out_if_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}

	if (IS_VB1_OUT(priv->linktype)) {
		if (priv->out_timing == E_4K2K_60HZ ||
		    priv->out_timing == E_4K1K_120HZ) {
			_vby1_extv_4k_60HZ();
		} else if (priv->out_timing == E_4K2K_120HZ ||
		priv->out_timing == E_4K1K_240HZ ||
		priv->out_timing == E_5K2K_60HZ) {
			_vby1_extv_4k_120HZ();
		} else {
			debug("[%s] Not supported timing\n", __func__);
			return -EINVAL;
		}
	}

	_vby1_extv_set_mft(dev); //mft setting

	//h/v sync polarity
	W2BYTEMSK(REG_0004_MODV22, priv->hsync_pol, REG_0004_MODV22_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODV22, priv->vsync_pol, REG_0004_MODV22_REG_VBY1_VS_INV);

	_vby1_extv_lane_order(dev);

	//fifo reset (delta video path)
	W2BYTEMSK(REG_0154_MODD1, 0x1, REG_0154_MODD1_REG_V2_SW_FORCE_FIX_TRIG);
	W2BYTEMSK(REG_0154_MODD1, 0x0, REG_0154_MODD1_REG_V2_SW_FORCE_FIX_TRIG);

	return 0;
}

int mtk_gfx_out_if_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 htt_slot = 0;

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return -ENXIO;
	}

	switch (priv->out_timing) {
	case E_4K2K_60HZ:
	case E_4K1K_120HZ:
		if (priv->vbo_byte == E_VBO_4BYTE_MODE) {
			_vby1_gfx_4kARGB8888_60HZ();
			if (priv->out_format == E_OUTPUT_ARGB8888_MODE0)
				W2BYTEMSK(REG_0008_MODOSD2, 0x2, REG_0008_MODOSD2_REG_FORMAT_MAP);
			if (priv->out_format == E_OUTPUT_ARGB8888_MODE1) {

				W2BYTEMSK(REG_0008_MODOSD2, 0x4, REG_0008_MODOSD2_REG_FORMAT_MAP);

				W2BYTEMSK(REG_0100_MODOSD2, 0x1C, REG_0100_MODOSD2_REG_SWAP_BIT_00);
				W2BYTEMSK(REG_0100_MODOSD2, 0x1D, REG_0100_MODOSD2_REG_SWAP_BIT_01);

				W2BYTEMSK(REG_0104_MODOSD2, 0x16, REG_0104_MODOSD2_REG_SWAP_BIT_02);
				W2BYTEMSK(REG_0104_MODOSD2, 0x17, REG_0104_MODOSD2_REG_SWAP_BIT_03);

				W2BYTEMSK(REG_0108_MODOSD2, 0x18, REG_0108_MODOSD2_REG_SWAP_BIT_04);
				W2BYTEMSK(REG_0108_MODOSD2, 0x19, REG_0108_MODOSD2_REG_SWAP_BIT_05);

				W2BYTEMSK(REG_010C_MODOSD2, 0x1A, REG_010C_MODOSD2_REG_SWAP_BIT_06);
				W2BYTEMSK(REG_010C_MODOSD2, 0x1B, REG_010C_MODOSD2_REG_SWAP_BIT_07);

				W2BYTEMSK(REG_0110_MODOSD2, 0x12, REG_0110_MODOSD2_REG_SWAP_BIT_08);
				W2BYTEMSK(REG_0110_MODOSD2, 0x13, REG_0110_MODOSD2_REG_SWAP_BIT_09);

				W2BYTEMSK(REG_0114_MODOSD2, 0x0C, REG_0114_MODOSD2_REG_SWAP_BIT_10);
				W2BYTEMSK(REG_0114_MODOSD2, 0x0D, REG_0114_MODOSD2_REG_SWAP_BIT_11);

				W2BYTEMSK(REG_0118_MODOSD2, 0x0E, REG_0118_MODOSD2_REG_SWAP_BIT_12);
				W2BYTEMSK(REG_0118_MODOSD2, 0x0F, REG_0118_MODOSD2_REG_SWAP_BIT_13);

				W2BYTEMSK(REG_011C_MODOSD2, 0x10, REG_011C_MODOSD2_REG_SWAP_BIT_14);
				W2BYTEMSK(REG_011C_MODOSD2, 0x11, REG_011C_MODOSD2_REG_SWAP_BIT_15);

				W2BYTEMSK(REG_0120_MODOSD2, 0x08, REG_0120_MODOSD2_REG_SWAP_BIT_16);
				W2BYTEMSK(REG_0120_MODOSD2, 0x09, REG_0120_MODOSD2_REG_SWAP_BIT_17);

				W2BYTEMSK(REG_0124_MODOSD2, 0x02, REG_0124_MODOSD2_REG_SWAP_BIT_18);
				W2BYTEMSK(REG_0124_MODOSD2, 0x03, REG_0124_MODOSD2_REG_SWAP_BIT_19);

				W2BYTEMSK(REG_0128_MODOSD2, 0x04, REG_0128_MODOSD2_REG_SWAP_BIT_20);
				W2BYTEMSK(REG_0128_MODOSD2, 0x05, REG_0128_MODOSD2_REG_SWAP_BIT_21);

				W2BYTEMSK(REG_012C_MODOSD2, 0x06, REG_012C_MODOSD2_REG_SWAP_BIT_22);
				W2BYTEMSK(REG_012C_MODOSD2, 0x07, REG_012C_MODOSD2_REG_SWAP_BIT_23);

				W2BYTEMSK(REG_0130_MODOSD2, 0x1F, REG_0130_MODOSD2_REG_SWAP_BIT_24);
				W2BYTEMSK(REG_0130_MODOSD2, 0x1E, REG_0130_MODOSD2_REG_SWAP_BIT_25);

				W2BYTEMSK(REG_0134_MODOSD2, 0x20, REG_0134_MODOSD2_REG_SWAP_BIT_26);
				W2BYTEMSK(REG_0134_MODOSD2, 0x21, REG_0134_MODOSD2_REG_SWAP_BIT_27);

				W2BYTEMSK(REG_0138_MODOSD2, 0x22, REG_0138_MODOSD2_REG_SWAP_BIT_28);
				W2BYTEMSK(REG_0138_MODOSD2, 0x23, REG_0138_MODOSD2_REG_SWAP_BIT_29);

				W2BYTEMSK(REG_013C_MODOSD2, 0x24, REG_013C_MODOSD2_REG_SWAP_BIT_30);
				W2BYTEMSK(REG_013C_MODOSD2, 0x25, REG_013C_MODOSD2_REG_SWAP_BIT_31);

			}
		} else if (priv->vbo_byte == E_VBO_5BYTE_MODE) {
			_vby1_gfx_4kARGB8101010_60HZ();
		} else {
			debug("[%s]4K60hz, Not supported format\n", __func__);
			return -EINVAL;
		}
	break;
	case E_4K2K_30HZ:
		_vby1_gfx_4k_30HZ();
		if (priv->out_format == E_OUTPUT_ARGB8888_MODE0)
			W2BYTEMSK(REG_0008_MODOSD2, 0x2, REG_0008_MODOSD2_REG_FORMAT_MAP);
		if (priv->out_format == E_OUTPUT_ARGB8888_MODE1) {

			W2BYTEMSK(REG_0008_MODOSD2, 0x4, REG_0008_MODOSD2_REG_FORMAT_MAP);

			W2BYTEMSK(REG_0100_MODOSD2, 0x1C, REG_0100_MODOSD2_REG_SWAP_BIT_00);
			W2BYTEMSK(REG_0100_MODOSD2, 0x1D, REG_0100_MODOSD2_REG_SWAP_BIT_01);

			W2BYTEMSK(REG_0104_MODOSD2, 0x16, REG_0104_MODOSD2_REG_SWAP_BIT_02);
			W2BYTEMSK(REG_0104_MODOSD2, 0x17, REG_0104_MODOSD2_REG_SWAP_BIT_03);

			W2BYTEMSK(REG_0108_MODOSD2, 0x18, REG_0108_MODOSD2_REG_SWAP_BIT_04);
			W2BYTEMSK(REG_0108_MODOSD2, 0x19, REG_0108_MODOSD2_REG_SWAP_BIT_05);

			W2BYTEMSK(REG_010C_MODOSD2, 0x1A, REG_010C_MODOSD2_REG_SWAP_BIT_06);
			W2BYTEMSK(REG_010C_MODOSD2, 0x1B, REG_010C_MODOSD2_REG_SWAP_BIT_07);

			W2BYTEMSK(REG_0110_MODOSD2, 0x12, REG_0110_MODOSD2_REG_SWAP_BIT_08);
			W2BYTEMSK(REG_0110_MODOSD2, 0x13, REG_0110_MODOSD2_REG_SWAP_BIT_09);

			W2BYTEMSK(REG_0114_MODOSD2, 0x0C, REG_0114_MODOSD2_REG_SWAP_BIT_10);
			W2BYTEMSK(REG_0114_MODOSD2, 0x0D, REG_0114_MODOSD2_REG_SWAP_BIT_11);

			W2BYTEMSK(REG_0118_MODOSD2, 0x0E, REG_0118_MODOSD2_REG_SWAP_BIT_12);
			W2BYTEMSK(REG_0118_MODOSD2, 0x0F, REG_0118_MODOSD2_REG_SWAP_BIT_13);

			W2BYTEMSK(REG_011C_MODOSD2, 0x10, REG_011C_MODOSD2_REG_SWAP_BIT_14);
			W2BYTEMSK(REG_011C_MODOSD2, 0x11, REG_011C_MODOSD2_REG_SWAP_BIT_15);

			W2BYTEMSK(REG_0120_MODOSD2, 0x08, REG_0120_MODOSD2_REG_SWAP_BIT_16);
			W2BYTEMSK(REG_0120_MODOSD2, 0x09, REG_0120_MODOSD2_REG_SWAP_BIT_17);

			W2BYTEMSK(REG_0124_MODOSD2, 0x02, REG_0124_MODOSD2_REG_SWAP_BIT_18);
			W2BYTEMSK(REG_0124_MODOSD2, 0x03, REG_0124_MODOSD2_REG_SWAP_BIT_19);

			W2BYTEMSK(REG_0128_MODOSD2, 0x04, REG_0128_MODOSD2_REG_SWAP_BIT_20);
			W2BYTEMSK(REG_0128_MODOSD2, 0x05, REG_0128_MODOSD2_REG_SWAP_BIT_21);

			W2BYTEMSK(REG_012C_MODOSD2, 0x06, REG_012C_MODOSD2_REG_SWAP_BIT_22);
			W2BYTEMSK(REG_012C_MODOSD2, 0x07, REG_012C_MODOSD2_REG_SWAP_BIT_23);

			W2BYTEMSK(REG_0130_MODOSD2, 0x1F, REG_0130_MODOSD2_REG_SWAP_BIT_24);
			W2BYTEMSK(REG_0130_MODOSD2, 0x1E, REG_0130_MODOSD2_REG_SWAP_BIT_25);

			W2BYTEMSK(REG_0134_MODOSD2, 0x20, REG_0134_MODOSD2_REG_SWAP_BIT_26);
			W2BYTEMSK(REG_0134_MODOSD2, 0x21, REG_0134_MODOSD2_REG_SWAP_BIT_27);

			W2BYTEMSK(REG_0138_MODOSD2, 0x22, REG_0138_MODOSD2_REG_SWAP_BIT_28);
			W2BYTEMSK(REG_0138_MODOSD2, 0x23, REG_0138_MODOSD2_REG_SWAP_BIT_29);

			W2BYTEMSK(REG_013C_MODOSD2, 0x24, REG_013C_MODOSD2_REG_SWAP_BIT_30);
			W2BYTEMSK(REG_013C_MODOSD2, 0x25, REG_013C_MODOSD2_REG_SWAP_BIT_31);

		}
	break;
	default:
		debug("[%s] Not supported timing\n", __func__);
		return -EINVAL;
	break;
	}

	if (priv->lanes/MFT_P > 0)
		htt_slot = priv->lanes/MFT_P -1;
	else
		htt_slot = 0;

	W2BYTEMSK(REG_000C_MODOSD1, htt_slot, REG_000C_MODOSD1_REG_MFT_VLD_WRAP_FIX_HTT);

	_vby1_gfx_set_mft(dev); //mft setting

	//h/v sync polarity
	W2BYTEMSK(REG_0004_MODOSD2, priv->hsync_pol, REG_0004_MODOSD2_REG_VBY1_HS_INV);
	W2BYTEMSK(REG_0004_MODOSD2, priv->vsync_pol, REG_0004_MODOSD2_REG_VBY1_VS_INV);

	//fifo reset (delta video path)
	W2BYTEMSK(REG_0158_MODD1, 0x1, REG_0158_MODD1_REG_OSD_SW_FORCE_FIX_TRIG);
	W2BYTEMSK(REG_0158_MODD1, 0x0, REG_0158_MODD1_REG_OSD_SW_FORCE_FIX_TRIG);


	return 0;
}

void mtk_out_if_hbkproch_protect_init(struct udevice *dev)
{
	//stHprotectInfo->lane_numbers;
	//stHprotectInfo->hsync_w;
	//stHprotectInfo->de_hstart;
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	u8 u8H_minus_line = 0;

	u8 u8Meta_data_mode_shift_line = 0;
	u16 u16Hstart_div_lane = 0;
	u16 u16Hread_de_st_set = 0;

	if (priv->lanes == VBO_USE_LANE_NUM_2 && priv->linktype == E_LINK_LVDS) {
		UBOOT_DEBUG("[%s][PNL_LIB %d] need to check more to DE\n",
			__func__, priv->pnl_lib_version);
		return;
	}

	W2BYTEMSK(REG_01E4_MODV11, 0x1, REG_01E4_MODV11_REG_HS_WID_ADJ_EN);

	if (priv->lanes >= 8)
		W2BYTEMSK(REG_000C_MODV11, (priv->lanes/8)-1, REG_000C_MODV11_REG_MFT_VLD_WRAP_FIX_HTT);

	if (priv->lanes == 8)
		u8H_minus_line = 4;
	else if (priv->lanes == 16)
		u8H_minus_line = 2;
	else
		u8H_minus_line = 0;

	if (R2BYTEMSK(REG_0020_MODV12,REG_0020_MODV12_REG_META_DATA_EN) == 0)
		u8Meta_data_mode_shift_line = 0;
	else
		u8Meta_data_mode_shift_line = 5;

	if ((priv->out_format == E_OUTPUT_YUV422) || (priv->out_format == E_OUTPUT_YUV420))
		u16Hstart_div_lane = ((priv->de_hstart/DIV_2)/priv->lanes);
	else
		u16Hstart_div_lane = (priv->de_hstart/priv->lanes);

	if ((u16Hstart_div_lane + u8Meta_data_mode_shift_line) >= (u8H_minus_line))
		u16Hread_de_st_set = u16Hstart_div_lane - u8H_minus_line + u8Meta_data_mode_shift_line;
	else
		u16Hread_de_st_set = 0;

	W2BYTEMSK(REG_003C_MODV11, u16Hread_de_st_set, REG_003C_MODV11_REG_MFT_READ_HDE_ST);


	if ((priv->hsync_w / priv->lanes) == 0)
		W2BYTEMSK(REG_0014_MODV11, 0, REG_0014_MODV11_REG_HS_FP_DELAY_VALUE);
	else
		W2BYTEMSK(REG_0014_MODV11, (priv->hsync_w/priv->lanes) - 1, REG_0014_MODV11_REG_HS_FP_DELAY_VALUE);

}

void mtk_ext_video_out_if_delta_hbkproch_protect_init(struct udevice *dev)
{
	//stHprotectInfo->lane_numbers;
	//stHprotectInfo->hsync_w;
	//stHprotectInfo->de_hstart;
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	u8 u8H_minus_line = 0;

	u8 u8Meta_data_mode_shift_line = 0;
	u16 u16Hstart_div_lane = 0;
	u16 u16Hread_de_st_set = 0;

	W2BYTEMSK(REG_01E4_MODV21, 0x1, REG_01E4_MODV21_REG_HS_WID_ADJ_EN);

	if (priv->lanes >= 8)
		W2BYTEMSK(REG_000C_MODV21, (priv->lanes/8)-1, REG_000C_MODV21_REG_MFT_VLD_WRAP_FIX_HTT);

	if (priv->lanes == 8)
		u8H_minus_line = 4;
	else if (priv->lanes == 16)
		u8H_minus_line = 2;
	else
		u8H_minus_line = 0;

	if (R2BYTEMSK(REG_0020_MODV22,REG_0020_MODV22_REG_META_DATA_EN) == 0)
		u8Meta_data_mode_shift_line = 0;
	else
		u8Meta_data_mode_shift_line = 5;

	if ((priv->out_format == E_OUTPUT_YUV422) || (priv->out_format == E_OUTPUT_YUV420))
		u16Hstart_div_lane = ((priv->de_hstart/DIV_2)/priv->lanes);
	else
		u16Hstart_div_lane = (priv->de_hstart/priv->lanes);

	if ((u16Hstart_div_lane + u8Meta_data_mode_shift_line) >= (u8H_minus_line))
		u16Hread_de_st_set = u16Hstart_div_lane - u8H_minus_line + u8Meta_data_mode_shift_line;
	else
		u16Hread_de_st_set = 0;

	W2BYTEMSK(REG_003C_MODV21, u16Hread_de_st_set, REG_003C_MODV21_REG_MFT_READ_HDE_ST);


	if ((priv->hsync_w / priv->lanes) == 0)
		W2BYTEMSK(REG_0014_MODV21, 0, REG_0014_MODV21_REG_HS_FP_DELAY_VALUE);
	else
		W2BYTEMSK(REG_0014_MODV21, (priv->hsync_w/priv->lanes) - 1, REG_0014_MODV21_REG_HS_FP_DELAY_VALUE);

}

void mtk_gfx_out_if_hbkproch_protect_init(struct udevice *dev)
{
	//stHprotectInfo->lane_numbers;
	//stHprotectInfo->hsync_w;
	//stHprotectInfo->de_hstart;
	//GFX part

	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 u8H_minus_line = 0;

	u8 u8Meta_data_mode_shift_line = 0;
	u16 u16Hstart_div_lane = 0;
	u16 u16Hread_de_st_set = 0;

	W2BYTEMSK(REG_01E4_MODOSD1, 0x1, REG_01E4_MODOSD1_REG_HS_WID_ADJ_EN);

	if (priv->lanes >= 8)
		W2BYTEMSK(REG_000C_MODOSD1, (priv->lanes/8)-1, REG_000C_MODOSD1_REG_MFT_VLD_WRAP_FIX_HTT);

	if (priv->lanes == 8)
		u8H_minus_line = 4;
	else if (priv->lanes == 16)
		u8H_minus_line = 2;
	else
		u8H_minus_line = 0;

	if (R2BYTEMSK(REG_0020_MODOSD2,REG_0020_MODOSD2_REG_META_DATA_EN) == 0)
		u8Meta_data_mode_shift_line = 0;
	else
		u8Meta_data_mode_shift_line = 5;

	if ((priv->out_format == E_OUTPUT_YUV422) || (priv->out_format == E_OUTPUT_YUV420))
		u16Hstart_div_lane = ((priv->de_hstart/DIV_2)/priv->lanes);
	else
		u16Hstart_div_lane = (priv->de_hstart/priv->lanes);

	if ((u16Hstart_div_lane + u8Meta_data_mode_shift_line) >= (u8H_minus_line))
		u16Hread_de_st_set = u16Hstart_div_lane - u8H_minus_line + u8Meta_data_mode_shift_line;
	else
		u16Hread_de_st_set = 0;

	W2BYTEMSK(REG_003C_MODOSD1, u16Hread_de_st_set, REG_003C_MODOSD1_REG_MFT_READ_HDE_ST);


	if ((priv->hsync_w / priv->lanes) == 0)
		W2BYTEMSK(REG_0014_MODOSD1, 0, REG_0014_MODOSD1_REG_HS_FP_DELAY_VALUE);
	else
		W2BYTEMSK(REG_0014_MODOSD1, (priv->hsync_w/priv->lanes) - 1, REG_0014_MODV21_REG_HS_FP_DELAY_VALUE);

}

void mtk_pnl_set_vby1_mft_hmirror(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv->cus_info.hmirror_en == true) {
		W2BYTEMSK(REG_0004_MODV11, 1, REG_0004_MODV11_REG_MFT_H_MIRROR);
		W2BYTEMSK(REG_0004_MODV21, 1, REG_0004_MODV21_REG_MFT_H_MIRROR);
		W2BYTEMSK(REG_0004_MODOSD1, 1, REG_0004_MODOSD1_REG_MFT_H_MIRROR);
	}
	else {
		W2BYTEMSK(REG_0004_MODV11, 0, REG_0004_MODV11_REG_MFT_H_MIRROR);
		W2BYTEMSK(REG_0004_MODV21, 0, REG_0004_MODV21_REG_MFT_H_MIRROR);
		W2BYTEMSK(REG_0004_MODOSD1, 0, REG_0004_MODOSD1_REG_MFT_H_MIRROR);
	}
}

void mtk_pnl_set_panel_SCDISP_Path_Sel(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	UBOOT_DEBUG("%s: priv->cus_info.scdisp_path_sel=%d\n", __func__, priv->cus_info.scdisp_path_sel);
	W2BYTEMSK(REG_0100_SCDISP_BKA4FA, priv->cus_info.scdisp_path_sel, REG_0100_SCDISP_BKA4FA_REG_SCDISP_PATH_SEL);

	if (((priv->cus_info.dmc_od_pga_path_sel == TCON_PATH_DEMURA_OD_PGA) ||
	(priv->cus_info.dmc_od_pga_path_sel == TCON_PATH_DEMURA_PGA_OD) ||
	(priv->cus_info.dmc_od_pga_path_sel == TCON_PATH_OD_DEMURA_PGA) ||
	(priv->cus_info.dmc_od_pga_path_sel == TCON_PATH_OD_PGA_DEMURA) ||
	(priv->cus_info.dmc_od_pga_path_sel == TCON_PATH_PGA_DEMURA_OD) ||
	(priv->cus_info.dmc_od_pga_path_sel == TCON_PATH_PGA_OD_DEMURA)) &&
	(!priv->tcon_info.bUsingTCON)) {
		UBOOT_DEBUG("%s: dmc_od_pga_path =%d\n", __func__, priv->cus_info.dmc_od_pga_path_sel);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004,
				  priv->cus_info.dmc_od_pga_path_sel,
				  REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
	}
}

bool _mtk_pnl_set_mod_block_pattern_enable(bool en)
{
	W2BYTEMSK(REG_0004_TCON_VCOM_PAT_V005, (en << 0), REG_0004_TCON_VCOM_PAT_V005_REG_BLOCK_TEST_EN_0004);
	return true;
}

bool _mtk_pnl_set_mod_block_pattern_table(u16 *pixel_tbl, u32 table_size, bool is_epi)
{
	u16 vcom_tbl[table_size];
	u32 table_addr_1 = 0;
	u32 table_addr_2 = 0;
	u32 table_addr = 0;
	u16 table_temp[table_size];

	memset(vcom_tbl, 0, sizeof(u16) * table_size);
	if (!pixel_tbl)
		return false;

	memcpy(vcom_tbl, pixel_tbl, sizeof(u16) * table_size);
	memset(table_temp, 0, sizeof(u16) * table_size);
	memcpy(table_temp, pixel_tbl, sizeof(u16) * table_size);
	if (is_epi) {
		for (table_addr_1 = 0; table_addr_1 < table_size; table_addr_1++) {
			table_addr_2 = table_addr_1 + MOD_BLOCKPATTERN_TBL_LINE_SIZE;
			while (table_addr_2 >= table_size)
				table_addr_2 = table_addr_2 - table_size;

			vcom_tbl[table_addr_2] = table_temp[table_addr_1];
		}
	}

	if (table_size == MOD_BLOCKPATTERN_TBL_MAX_SIZE) {
		for (table_addr = 0; table_addr < table_size; table_addr++) {
			// reg_detect_table, masks are same so keep
			W2BYTEMSK(REG_0020_TCON_VCOM_PAT_V005 + table_addr * MOD_BLOCKPATTERN_ADDR_STEP,
			vcom_tbl[table_addr],
			REG_0020_TCON_VCOM_PAT_V005_REG_LINE0_SUBP00_0020);
		}
		return true;
	} else {
		return false;
	}
}

void _mtk_pnl_vcom_pattern_en(bool en)
{
	u16 pixel_tbl[MOD_BLOCKPATTERN_TBL_MAX_SIZE];
	u8 idx_num = 0;

	// Vcom pattern
	for (idx_num = 0; idx_num < MOD_BLOCKPATTERN_TBL_MAX_SIZE; idx_num++) {
	     pixel_tbl[idx_num] = 0x00;
	     idx_num++;
	     pixel_tbl[idx_num] = 0x00;
	     idx_num++;
	     pixel_tbl[idx_num] = 0x00;
	}

	if (en)	{
		if (_mtk_pnl_set_mod_block_pattern_table(pixel_tbl, MOD_BLOCKPATTERN_TBL_MAX_SIZE, false)) {
			_mtk_pnl_set_mod_block_pattern_enable(true);
		} else {
			_mtk_pnl_set_mod_block_pattern_enable(false);
			UBOOT_DEBUG("set block pattern table fail!!\n");
		}
	} else {
		_mtk_pnl_set_mod_block_pattern_enable(false);
	}
}

void mtk_pnl_mute_en(struct udevice *dev, bool en)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		printf("%s: priv is NULL\n", __func__);
		return;
	}

	debug("%s(%s): panel version: %d\n",
		__func__, en ? "MUTE" : "UNMUTE",
		priv->pnl_lib_version);

	// TCON pattern
	switch (priv->pnl_lib_version) {
	case BOOT_PNL_VERSION0100:
		if (en) {
			W2BYTEMSK(REG_00B8_PATGEN_SCALER_BKA404, 0x0, REG_00B8_PATGEN_SCALER_BKA404_REG_G_END_MSB);
			W2BYTEMSK(REG_0084_PATGEN_SCALER_BKA404, 0x0, REG_0084_PATGEN_SCALER_BKA404_REG_BYPASS_PATGEN_SCALER);
			W2BYTEMSK(REG_0084_PATGEN_SCALER_BKA404, 0x1, REG_0084_PATGEN_SCALER_BKA404_REG_DB_EN);
		} else {
			W2BYTEMSK(REG_00B8_PATGEN_SCALER_BKA404, 0x0, REG_00B8_PATGEN_SCALER_BKA404_REG_G_END_MSB);
			W2BYTEMSK(REG_0084_PATGEN_SCALER_BKA404, 0x1, REG_0084_PATGEN_SCALER_BKA404_REG_BYPASS_PATGEN_SCALER);
		}
		break;
	case BOOT_PNL_VERSION0200:
	case BOOT_PNL_VERSION0203:
	case BOOT_PNL_VERSION0300:

		if (en) {
			// R
			W2BYTEMSK(REG_0194_PATGEN_SCALER_BKA407, 0x0, REG_0194_PATGEN_SCALER_BKA407_REG_R_ST_MSB);
			W2BYTEMSK(REG_0198_PATGEN_SCALER_BKA407, 0x0, REG_0198_PATGEN_SCALER_BKA407_REG_R_ST_LSB);
			W2BYTEMSK(REG_0198_PATGEN_SCALER_BKA407, 0x0, REG_0198_PATGEN_SCALER_BKA407_REG_R_END_MSB);
			W2BYTEMSK(REG_019C_PATGEN_SCALER_BKA407, 0x0, REG_019C_PATGEN_SCALER_BKA407_REG_R_END_LSB);
			// G
			W2BYTEMSK(REG_01B4_PATGEN_SCALER_BKA407, 0x0, REG_01B4_PATGEN_SCALER_BKA407_REG_G_ST_MSB);
			W2BYTEMSK(REG_01B8_PATGEN_SCALER_BKA407, 0x0, REG_01B8_PATGEN_SCALER_BKA407_REG_G_END_MSB);
			W2BYTEMSK(REG_01B8_PATGEN_SCALER_BKA407, 0x0, REG_01B8_PATGEN_SCALER_BKA407_REG_G_ST_LSB);
			W2BYTEMSK(REG_01BC_PATGEN_SCALER_BKA407, 0x0, REG_01BC_PATGEN_SCALER_BKA407_REG_G_END_LSB);
			// B
			W2BYTEMSK(REG_01D4_PATGEN_SCALER_BKA407, 0x0, REG_01D4_PATGEN_SCALER_BKA407_REG_B_ST_MSB);
			W2BYTEMSK(REG_01D8_PATGEN_SCALER_BKA407, 0x0, REG_01D8_PATGEN_SCALER_BKA407_REG_B_ST_LSB);
			W2BYTEMSK(REG_01D8_PATGEN_SCALER_BKA407, 0x0, REG_01D8_PATGEN_SCALER_BKA407_REG_B_END_MSB);
			W2BYTEMSK(REG_01DC_PATGEN_SCALER_BKA407, 0x0, REG_01DC_PATGEN_SCALER_BKA407_REG_B_END_LSB);

			W2BYTEMSK(REG_01F0_PATGEN_SCALER_BKA407, priv->de_width, REG_01F0_PATGEN_SCALER_BKA407_REG_H_SIZE);
			W2BYTEMSK(REG_01F4_PATGEN_SCALER_BKA407, priv->de_height, REG_01F4_PATGEN_SCALER_BKA407_REG_V_SIZE);

			W2BYTEMSK(REG_0184_PATGEN_SCALER_BKA407, 0x1, REG_0184_PATGEN_SCALER_BKA407_REG_DB_EN);
			W2BYTEMSK(REG_0184_PATGEN_SCALER_BKA407, 0x0, REG_0184_PATGEN_SCALER_BKA407_REG_BYPASS_PATGEN_SCALER);
		} else {
			W2BYTEMSK(REG_01B8_PATGEN_SCALER_BKA407, 0x0, REG_01B8_PATGEN_SCALER_BKA407_REG_G_END_MSB);
			W2BYTEMSK(REG_0184_PATGEN_SCALER_BKA407, 0x1, REG_0184_PATGEN_SCALER_BKA407_REG_BYPASS_PATGEN_SCALER);
		}
		break;
	case BOOT_PNL_VERSION0400:
	case BOOT_PNL_VERSION0500:
		_mtk_pnl_vcom_pattern_en(en);
		break;
	default: // The pattern gen is lighted for V4
		if (en) {
			W2BYTEMSK(REG_0198_MODV11, 0x0, REG_0198_MODV11_REG_TEST_COLOR_R);
			W2BYTEMSK(REG_019C_MODV11, 0x0, REG_019C_MODV11_REG_TEST_COLOR_G);
			W2BYTEMSK(REG_01A0_MODV11, 0x0, REG_01A0_MODV11_REG_TEST_COLOR_B);
			W2BYTEMSK(REG_0180_MODV11, 0x1, REG_0180_MODV11_REG_TEST_MODE);
			W2BYTEMSK(REG_0184_MODV11, 0, REG_0184_MODV11_REG_TEST_H_LINE_ST);
			W2BYTEMSK(REG_0188_MODV11, 0, REG_0188_MODV11_REG_TEST_H_LINE_END);
			W2BYTEMSK(REG_0180_MODV11, 0, REG_0180_MODV11_REG_TEST_H_LINE_MODE);
		} else {
			W2BYTEMSK(REG_0184_MODV11, REG_ALL, REG_0184_MODV11_REG_TEST_H_LINE_ST);
			W2BYTEMSK(REG_0188_MODV11, REG_ALL, REG_0188_MODV11_REG_TEST_H_LINE_END);
			W2BYTEMSK(REG_0180_MODV11, true, REG_0180_MODV11_REG_TEST_H_LINE_MODE);
			W2BYTEMSK(REG_0180_MODV11, 0x0, REG_0180_MODV11_REG_TEST_MODE);
			W2BYTEMSK(REG_0198_MODV11, 0, REG_0198_MODV11_REG_TEST_COLOR_R);
			W2BYTEMSK(REG_019C_MODV11, 0, REG_019C_MODV11_REG_TEST_COLOR_G);
			W2BYTEMSK(REG_01A0_MODV11, 0, REG_01A0_MODV11_REG_TEST_COLOR_B);
		}
		break;
	}
}

void mtk_extv_mute_en(struct udevice *dev, bool en)
{
	if(en) {
		W2BYTEMSK(REG_0198_MODV21, 0, REG_0198_MODV21_REG_TEST_COLOR_R);
		W2BYTEMSK(REG_019C_MODV21, 0, REG_019C_MODV21_REG_TEST_COLOR_G);
		W2BYTEMSK(REG_01A0_MODV21, 0, REG_01A0_MODV21_REG_TEST_COLOR_B);
		W2BYTEMSK(REG_0180_MODV21, 0x1, REG_0180_MODV21_REG_TEST_MODE);
		W2BYTEMSK(REG_0184_MODV21, 0, REG_0184_MODV21_REG_TEST_H_LINE_ST);
		W2BYTEMSK(REG_0188_MODV21, 0, REG_0188_MODV21_REG_TEST_H_LINE_END);
		W2BYTEMSK(REG_0180_MODV21, 0, REG_0180_MODV21_REG_TEST_H_LINE_MODE);
	} else {
		W2BYTEMSK(REG_0184_MODV21, REG_ALL, REG_0184_MODV21_REG_TEST_H_LINE_ST);
		W2BYTEMSK(REG_0188_MODV21, REG_ALL, REG_0188_MODV21_REG_TEST_H_LINE_END);
		W2BYTEMSK(REG_0180_MODV21, true, REG_0180_MODV21_REG_TEST_H_LINE_MODE);
		W2BYTEMSK(REG_0180_MODV21, 0x0, REG_0180_MODV21_REG_TEST_MODE);
		W2BYTEMSK(REG_0198_MODV21, 0, REG_0198_MODV21_REG_TEST_COLOR_R);
		W2BYTEMSK(REG_019C_MODV21, 0, REG_019C_MODV21_REG_TEST_COLOR_G);
		W2BYTEMSK(REG_01A0_MODV21, 0, REG_01A0_MODV21_REG_TEST_COLOR_B);
	}

}

void mtk_gfx_mute_en(struct udevice *dev, bool en)
{
	if(en) {
		W2BYTEMSK(REG_0198_MODOSD1, 0, REG_0198_MODOSD1_REG_TEST_COLOR_R);
		W2BYTEMSK(REG_019C_MODOSD1, 0, REG_019C_MODOSD1_REG_TEST_COLOR_G);
		W2BYTEMSK(REG_01A0_MODOSD1, 0, REG_01A0_MODOSD1_REG_TEST_COLOR_B);
		W2BYTEMSK(REG_0180_MODOSD1, 0x1, REG_0180_MODOSD1_REG_TEST_MODE);
		W2BYTEMSK(REG_0184_MODOSD1, 0, REG_0184_MODOSD1_REG_TEST_H_LINE_ST);
		W2BYTEMSK(REG_0188_MODOSD1, 0, REG_0188_MODOSD1_REG_TEST_H_LINE_END);
		W2BYTEMSK(REG_0180_MODOSD1, 0, REG_0180_MODOSD1_REG_TEST_H_LINE_MODE);
	} else {
		W2BYTEMSK(REG_0184_MODOSD1, REG_ALL, REG_0184_MODOSD1_REG_TEST_H_LINE_ST);
		W2BYTEMSK(REG_0188_MODOSD1, REG_ALL, REG_0188_MODOSD1_REG_TEST_H_LINE_END);
		W2BYTEMSK(REG_0180_MODOSD1, true, REG_0180_MODOSD1_REG_TEST_H_LINE_MODE);
		W2BYTEMSK(REG_0180_MODOSD1, 0x0, REG_0180_MODOSD1_REG_TEST_MODE);
		W2BYTEMSK(REG_0198_MODOSD1, 0, REG_0198_MODOSD1_REG_TEST_COLOR_R);
		W2BYTEMSK(REG_019C_MODOSD1, 0, REG_019C_MODOSD1_REG_TEST_COLOR_G);
		W2BYTEMSK(REG_01A0_MODOSD1, 0, REG_01A0_MODOSD1_REG_TEST_COLOR_B);
	}
}


#if (VBY1_LOCK_PROTECT_EN)
void _mtk_pnl_checkLockProtect(void)
{
#define COUNTMAX 50
#define TOGGLE_DELAY 50 //us
#define CHECK_DELAY 2 //ms
	bool bLocknEn = true;
	u8 u8uLockCount = 0;
	u8 u8ResetCount = 0;

	bLocknEn = R2BYTEMSK(REG_0184_MODV12, REG_0184_MODV12_REG_VBY1_LOCK_VIDEO);
	u8uLockCount = R2BYTEMSK(REG_01F8_MODV12, REG_01F8_MODV12_REG_UNLOCK_CNT);

	while ((bLocknEn == true) || (u8uLockCount != 0)) {
		if (bLocknEn) {
			if (u8uLockCount == 0) {
				// toggle vby1 test en
				W2BYTEMSK(REG_018C_MODV12, true, REG_018C_MODV12_REG_VBY1_TEST_EN);
				udelay(TOGGLE_DELAY);
				W2BYTEMSK(REG_018C_MODV12, false, REG_018C_MODV12_REG_VBY1_TEST_EN);
				// clear unlock cnt before training
				W2BYTEMSK(REG_01F8_MODV12, true, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
				udelay(TOGGLE_DELAY);
				W2BYTEMSK(REG_01F8_MODV12, false, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
				mdelay(CHECK_DELAY);
			} else {
				// clear unlock cnt before training
				W2BYTEMSK(REG_01F8_MODV12, true, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
				udelay(TOGGLE_DELAY);
				W2BYTEMSK(REG_01F8_MODV12, false, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
				mdelay(CHECK_DELAY);
			}
		} else {
			// clear unlock cnt before training
			W2BYTEMSK(REG_01F8_MODV12, true, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
			udelay(TOGGLE_DELAY);
			W2BYTEMSK(REG_01F8_MODV12, false, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
			mdelay(CHECK_DELAY);
		}

		bLocknEn = R2BYTEMSK(REG_0184_MODV12, REG_0184_MODV12_REG_VBY1_LOCK_VIDEO);
		u8uLockCount = R2BYTEMSK(REG_01F8_MODV12, REG_01F8_MODV12_REG_UNLOCK_CNT);

		if ((u8ResetCount > COUNTMAX) || ((bLocknEn == false) && (u8uLockCount == 0))) {
			if(u8ResetCount > COUNTMAX)
				debug("[%s] u8ResetCount=%d \n", __func__, u8ResetCount);
			break;
		}
		u8ResetCount++;
	}
}
#endif

void mtk_pnl_out_en(struct udevice *dev, bool en)
{
#define TOGGLE_DELAY 50 //us
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 u8laneCount;
	bool bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE_MAX] = {false};
	en_boot_pnl_output_lane_config eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}
	debug("[%s] enable panel output :%d\n",__func__,en);

	if (priv->tcon_info.bUsingTCON)
	{
		if (is_tcon_sti_flow())
		{
			//The order required by the general panel should be load pmic first
			//and then load tcon bin power on
			mtk_tcon_enable(dev, en);
			TCON_DEBUG("Tcon related output config settings are set in tcon bin.\n");
		}
		else
		{
			MHal_PNL_EnableTcon(dev);
		}
		return;
	}

	// clear unlock cnt before training
	W2BYTEMSK(REG_01F8_MODV12, true, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);
	udelay(TOGGLE_DELAY);
	W2BYTEMSK(REG_01F8_MODV12, false, REG_01F8_MODV12_REG_UNLOCK_CNT_CLR);

	debug("[%s] enable panel output :%d\n",__func__,en);

	if (en == true && priv->linktype == E_LINK_VB1) {
		W2BYTEMSK(REG_0184_MODV12, 0xF, REG_0184_MODV12_REG_VBY1_ALN_DE_CNT);
		W2BYTEMSK(REG_0184_MODV12, 0x3F, REG_0184_MODV12_REG_VBY1_ALN_PIX_CNT);
		//enable vby1 hw training.
		W2BYTEMSK(REG_0180_MODV12, 0xAAE, Fld(16,0,AC_FULLW10));
	}

	//video part. if use tcon bin, don't set outen here
	if (priv->linktype < E_LINK_MINILVDS_2BLK_6PAIR_8BIT) {

		switch (priv->out_timing) {
		case E_FHD_60HZ:
		{
			//temp test, use mask [15:0] instead of CODA defined mask.
			if (priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
				priv->pnl_lib_version == BOOT_PNL_VERSION0600)  {
				if(priv->linktype == E_LINK_LVDS) {
					// ch2 - ch13
					W2BYTEMSK(REG_0060_MODA1, en?0x5550:0x0, Fld(16,0,AC_FULLW10));
					W2BYTEMSK(REG_0064_MODA1, en?0x0555:0x0, Fld(16,0,AC_FULLW10));
				} else {
					W2BYTEMSK(REG_0060_MODA1, en?0x0440:0x0, Fld(16,0,AC_FULLW10));
					W2BYTEMSK(REG_0064_MODA1, 0x0, Fld(16,0,AC_FULLW10));
				}
			} else {
				for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE16; u8laneCount++) {
					if ((priv->lane_info.def_layout[u8laneCount]<E_BOOT_PNL_OUTPUT_LANE2) && (en==true))
						bOutputConfigEn[u8laneCount] = true;
					else
						bOutputConfigEn[u8laneCount] = false;
				}

				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);
			}
		}
		break;
		case E_FHD_120HZ:
		{
			for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE16; u8laneCount++) {
				if((priv->lane_info.def_layout[u8laneCount]<E_BOOT_PNL_OUTPUT_LANE4) && (en==true))
					bOutputConfigEn[u8laneCount] = true;
				else
					bOutputConfigEn[u8laneCount] = false;
			}

			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);
		}
		break;
		case E_4K2K_60HZ:
		case E_4K1K_120HZ:
		{
			if (priv->lane_duplicate_en)
				eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE16;
			else
				eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE8;

			for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE16; u8laneCount++) {
				if((priv->lane_info.def_layout[u8laneCount]<eOutputLaneEnNumber) && (en==true))
					bOutputConfigEn[u8laneCount] = true;
				else
					bOutputConfigEn[u8laneCount] = false;
			}

			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);
		}
		break;
		case E_4K1K_144HZ:
		{
			for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE16; u8laneCount++) {
				if((priv->lane_info.def_layout[u8laneCount]<E_BOOT_PNL_OUTPUT_LANE8) && (en==true))
					bOutputConfigEn[u8laneCount] = true;
				else
					bOutputConfigEn[u8laneCount] = false;
			}

			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);
		}
		break;
		case E_4K2K_120HZ:
		case E_4K2K_144HZ:
		case E_4K1K_240HZ:
		case E_5K2K_60HZ:
		{
			for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE16; u8laneCount++) {
				if((priv->lane_info.def_layout[u8laneCount]<E_BOOT_PNL_OUTPUT_LANE16) && (en==true))
					bOutputConfigEn[u8laneCount] = true;
				else
					bOutputConfigEn[u8laneCount] = false;
			}

			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);
		}
		break;
		case E_8K4K_60HZ:
		case E_5K2K_120HZ:
		{
			if (priv->out_format == E_OUTPUT_YUV422) {
				for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE16; u8laneCount++) {
					if((priv->lane_info.def_layout[u8laneCount]<E_BOOT_PNL_OUTPUT_LANE16) && (en==true))
						bOutputConfigEn[u8laneCount] = true;
					else
						bOutputConfigEn[u8laneCount] = false;
				}

				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);
			}

			if (priv->out_format == E_OUTPUT_YUV444 || priv->out_format == E_OUTPUT_RGB) {
				for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<E_BOOT_PNL_OUTPUT_LANE32; u8laneCount++) {
					if((priv->lane_info.def_layout[u8laneCount]<E_BOOT_PNL_OUTPUT_LANE32) && (en==true))
						bOutputConfigEn[u8laneCount] = true;
					else
						bOutputConfigEn[u8laneCount] = false;
				}

				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
				W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
				W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);

				W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE16], REG_0068_MODA1_REG_OUTPUT_CONF_CH16);
				W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE17], REG_0068_MODA1_REG_OUTPUT_CONF_CH17);
				W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE18], REG_0068_MODA1_REG_OUTPUT_CONF_CH18);
				W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE19], REG_0068_MODA1_REG_OUTPUT_CONF_CH19);

				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE20], REG_0060_MODA2_REG_OUTPUT_CONF_CH20);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE21], REG_0060_MODA2_REG_OUTPUT_CONF_CH21);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE22], REG_0060_MODA2_REG_OUTPUT_CONF_CH22);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE23], REG_0060_MODA2_REG_OUTPUT_CONF_CH23);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE24], REG_0060_MODA2_REG_OUTPUT_CONF_CH24);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE25], REG_0060_MODA2_REG_OUTPUT_CONF_CH25);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE26], REG_0060_MODA2_REG_OUTPUT_CONF_CH26);
				W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE27], REG_0060_MODA2_REG_OUTPUT_CONF_CH27);

				W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE28], REG_0064_MODA2_REG_OUTPUT_CONF_CH28);
				W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE29], REG_0064_MODA2_REG_OUTPUT_CONF_CH29);
				W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE30], REG_0064_MODA2_REG_OUTPUT_CONF_CH30);
				W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE31], REG_0064_MODA2_REG_OUTPUT_CONF_CH31);

			}
		}
		break;
		case E_8K4K_120HZ:
		case E_8K4K_144HZ:
		{
			for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE0; u8laneCount<=E_BOOT_PNL_OUTPUT_LANE63; u8laneCount++) {
				if((priv->lane_info.def_layout[u8laneCount]<=E_BOOT_PNL_OUTPUT_LANE63) && (en==true))
					bOutputConfigEn[u8laneCount] = true;
				else
					bOutputConfigEn[u8laneCount] = false;
			}

			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE0], REG_0060_MODA1_REG_OUTPUT_CONF_CH00);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE1], REG_0060_MODA1_REG_OUTPUT_CONF_CH01);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE2], REG_0060_MODA1_REG_OUTPUT_CONF_CH02);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE3], REG_0060_MODA1_REG_OUTPUT_CONF_CH03);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE4], REG_0060_MODA1_REG_OUTPUT_CONF_CH04);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE5], REG_0060_MODA1_REG_OUTPUT_CONF_CH05);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE6], REG_0060_MODA1_REG_OUTPUT_CONF_CH06);
			W2BYTEMSK(REG_0060_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE7], REG_0060_MODA1_REG_OUTPUT_CONF_CH07);

			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE8], REG_0064_MODA1_REG_OUTPUT_CONF_CH08);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE9], REG_0064_MODA1_REG_OUTPUT_CONF_CH09);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE10], REG_0064_MODA1_REG_OUTPUT_CONF_CH10);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE11], REG_0064_MODA1_REG_OUTPUT_CONF_CH11);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE12], REG_0064_MODA1_REG_OUTPUT_CONF_CH12);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE13], REG_0064_MODA1_REG_OUTPUT_CONF_CH13);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE14], REG_0064_MODA1_REG_OUTPUT_CONF_CH14);
			W2BYTEMSK(REG_0064_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE15], REG_0064_MODA1_REG_OUTPUT_CONF_CH15);

			W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE16], REG_0068_MODA1_REG_OUTPUT_CONF_CH16);
			W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE17], REG_0068_MODA1_REG_OUTPUT_CONF_CH17);
			W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE18], REG_0068_MODA1_REG_OUTPUT_CONF_CH18);
			W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE19], REG_0068_MODA1_REG_OUTPUT_CONF_CH19);

			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE20], REG_0060_MODA2_REG_OUTPUT_CONF_CH20);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE21], REG_0060_MODA2_REG_OUTPUT_CONF_CH21);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE22], REG_0060_MODA2_REG_OUTPUT_CONF_CH22);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE23], REG_0060_MODA2_REG_OUTPUT_CONF_CH23);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE24], REG_0060_MODA2_REG_OUTPUT_CONF_CH24);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE25], REG_0060_MODA2_REG_OUTPUT_CONF_CH25);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE26], REG_0060_MODA2_REG_OUTPUT_CONF_CH26);
			W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE27], REG_0060_MODA2_REG_OUTPUT_CONF_CH27);

			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE28], REG_0064_MODA2_REG_OUTPUT_CONF_CH28);
			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE29], REG_0064_MODA2_REG_OUTPUT_CONF_CH29);
			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE30], REG_0064_MODA2_REG_OUTPUT_CONF_CH30);
			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE31], REG_0064_MODA2_REG_OUTPUT_CONF_CH31);

			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE32], REG_0064_MODA2_REG_OUTPUT_CONF_CH32);
			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE33], REG_0064_MODA2_REG_OUTPUT_CONF_CH33);
			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE34], REG_0064_MODA2_REG_OUTPUT_CONF_CH34);
			W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE35], REG_0064_MODA2_REG_OUTPUT_CONF_CH35);

			W2BYTEMSK(REG_0068_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE36], REG_0068_MODA2_REG_OUTPUT_CONF_CH36);
			W2BYTEMSK(REG_0068_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE37], REG_0068_MODA2_REG_OUTPUT_CONF_CH37);
			W2BYTEMSK(REG_0068_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE38], REG_0068_MODA2_REG_OUTPUT_CONF_CH38);
			W2BYTEMSK(REG_0068_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE39], REG_0068_MODA2_REG_OUTPUT_CONF_CH39);

			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE40], REG_0060_MODA3_REG_OUTPUT_CONF_CH40);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE41], REG_0060_MODA3_REG_OUTPUT_CONF_CH41);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE42], REG_0060_MODA3_REG_OUTPUT_CONF_CH42);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE43], REG_0060_MODA3_REG_OUTPUT_CONF_CH43);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE44], REG_0060_MODA3_REG_OUTPUT_CONF_CH44);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE45], REG_0060_MODA3_REG_OUTPUT_CONF_CH45);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE46], REG_0060_MODA3_REG_OUTPUT_CONF_CH46);
			W2BYTEMSK(REG_0060_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE47], REG_0060_MODA3_REG_OUTPUT_CONF_CH47);

			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE48], REG_0064_MODA3_REG_OUTPUT_CONF_CH48);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE49], REG_0064_MODA3_REG_OUTPUT_CONF_CH49);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE50], REG_0064_MODA3_REG_OUTPUT_CONF_CH50);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE51], REG_0064_MODA3_REG_OUTPUT_CONF_CH51);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE52], REG_0064_MODA3_REG_OUTPUT_CONF_CH52);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE53], REG_0064_MODA3_REG_OUTPUT_CONF_CH53);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE54], REG_0064_MODA3_REG_OUTPUT_CONF_CH54);
			W2BYTEMSK(REG_0064_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE55], REG_0064_MODA3_REG_OUTPUT_CONF_CH55);

			W2BYTEMSK(REG_0068_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE56], REG_0068_MODA3_REG_OUTPUT_CONF_CH56);
			W2BYTEMSK(REG_0068_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE57], REG_0068_MODA3_REG_OUTPUT_CONF_CH57);
			W2BYTEMSK(REG_0068_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE58], REG_0068_MODA3_REG_OUTPUT_CONF_CH58);
			W2BYTEMSK(REG_0068_MODA3, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE59], REG_0068_MODA3_REG_OUTPUT_CONF_CH59);

			W2BYTEMSK(REG_0060_MODA4, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE60], REG_0060_MODA4_REG_OUTPUT_CONF_CH60);
			W2BYTEMSK(REG_0060_MODA4, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE61], REG_0060_MODA4_REG_OUTPUT_CONF_CH61);
			W2BYTEMSK(REG_0060_MODA4, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE62], REG_0060_MODA4_REG_OUTPUT_CONF_CH62);
			W2BYTEMSK(REG_0060_MODA4, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE63], REG_0060_MODA4_REG_OUTPUT_CONF_CH63);
		}
		break;
		default:
			debug("[%s][%d] OUTPUT TIMING Not Support\n", __func__, __LINE__);
		break;
		}

		#if (VBY1_LOCK_PROTECT_EN)
		if (en == true)
			_mtk_pnl_checkLockProtect();
		#endif
	}
}

void mtk_extv_out_en(struct udevice *dev, bool en)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u8 u8laneCount;
	bool bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE_MAX] = {false};
	en_boot_pnl_output_lane_config eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE0;

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (en == true && IS_VB1_OUT(priv->linktype)) {

		W2BYTEMSK(REG_0184_MODV22, 0xF, REG_0184_MODV22_REG_VBY1_ALN_DE_CNT);
		W2BYTEMSK(REG_0184_MODV22, 0x3F, REG_0184_MODV22_REG_VBY1_ALN_PIX_CNT);

		//enable vby1 hw training.
		W2BYTEMSK(REG_0180_MODV22, 0xAAE, Fld(16,0,AC_FULLW10));
	}

	switch (priv->out_timing) {

	case E_4K2K_60HZ:
	case E_4K1K_120HZ:
	{
		if (priv->lane_duplicate_en)
			eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE32;
		else
			eOutputLaneEnNumber = E_BOOT_PNL_OUTPUT_LANE24;
		for(u8laneCount=E_BOOT_PNL_OUTPUT_LANE16; u8laneCount<E_BOOT_PNL_OUTPUT_LANE32; u8laneCount++) {
			if((priv->lane_info.def_layout[u8laneCount]<eOutputLaneEnNumber) && (en==true))
				bOutputConfigEn[u8laneCount] = true;
			else
				bOutputConfigEn[u8laneCount] = false;
		}

		W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE16], REG_0068_MODA1_REG_OUTPUT_CONF_CH16);
		W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE17], REG_0068_MODA1_REG_OUTPUT_CONF_CH17);
		W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE18], REG_0068_MODA1_REG_OUTPUT_CONF_CH18);
		W2BYTEMSK(REG_0068_MODA1, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE19], REG_0068_MODA1_REG_OUTPUT_CONF_CH19);

		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE20], REG_0060_MODA2_REG_OUTPUT_CONF_CH20);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE21], REG_0060_MODA2_REG_OUTPUT_CONF_CH21);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE22], REG_0060_MODA2_REG_OUTPUT_CONF_CH22);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE23], REG_0060_MODA2_REG_OUTPUT_CONF_CH23);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE24], REG_0060_MODA2_REG_OUTPUT_CONF_CH24);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE25], REG_0060_MODA2_REG_OUTPUT_CONF_CH25);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE26], REG_0060_MODA2_REG_OUTPUT_CONF_CH26);
		W2BYTEMSK(REG_0060_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE27], REG_0060_MODA2_REG_OUTPUT_CONF_CH27);

		W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE28], REG_0064_MODA2_REG_OUTPUT_CONF_CH28);
		W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE29], REG_0064_MODA2_REG_OUTPUT_CONF_CH29);
		W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE30], REG_0064_MODA2_REG_OUTPUT_CONF_CH30);
		W2BYTEMSK(REG_0064_MODA2, bOutputConfigEn[E_BOOT_PNL_OUTPUT_LANE31], REG_0064_MODA2_REG_OUTPUT_CONF_CH31);
	}
	break;
	case E_4K2K_120HZ:
	case E_4K1K_240HZ:
	case E_5K2K_60HZ:
	{
		W2BYTEMSK(REG_0068_MODA1, en?0x0055:0x0, Fld(8,0,AC_FULLB0));
		W2BYTEMSK(REG_0060_MODA2, en?0x5555:0x0, Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0064_MODA2, en?0x0055:0x0, Fld(8,0,AC_FULLB0));
	}
	break;
	default:
		debug("[%s] Output timing NOT supported\n", __func__);
	break;

	}

}

void mtk_gfx_out_en(struct udevice *dev, bool en)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (en == true && IS_VB1_OUT(priv->linktype)) {

		W2BYTEMSK(REG_0184_MODOSD2, 0xF, REG_0184_MODOSD2_REG_VBY1_ALN_DE_CNT);
		W2BYTEMSK(REG_0184_MODOSD2, 0x3F, REG_0184_MODOSD2_REG_VBY1_ALN_PIX_CNT);

		//enable vby1 hw training.
		W2BYTEMSK(REG_0180_MODOSD2, 0xAAE, Fld(16,0,AC_FULLW10));
	}

	switch (priv->out_timing) {

	case E_4K2K_30HZ:
	{
		W2BYTEMSK(REG_0064_MODA2, en?0x55:0x0, Fld(8,8,AC_FULLB1));
		W2BYTEMSK(REG_0068_MODA2, en?0x55:0x0, Fld(8,0,AC_FULLB0));
	}
	break;
	case E_4K2K_60HZ:
	case E_4K1K_120HZ:
	{
		W2BYTEMSK(REG_0064_MODA2, en?0x55:0x0, Fld(8,8,AC_FULLB1));
		W2BYTEMSK(REG_0068_MODA2, en?0x55:0x0, Fld(8,0,AC_FULLB0));
	}
	break;
	default:
		debug("[%s] Output timing NOT supported\n", __func__);
	break;
	}

}

void mtk_pre_emphasis_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	enum drm_en_pnl_group epnl_group = E_PNL_GROUP_0;
	st_out_pe_level stpe_info = {0};
	__u32 i = 0;

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->epnl_group < E_PNL_GROUP_MAX)
		epnl_group = priv->epnl_group;

	memcpy(&stpe_info, &priv->pe_info[epnl_group], sizeof(st_out_pe_level));

	switch (priv->pnl_lib_version) {
	case BOOT_PNL_VERSION0400:
	case BOOT_PNL_VERSION0500:
	case BOOT_PNL_VERSION0600:
		if (stpe_info.pe_usr != 0) {
			if (stpe_info.ctrl_lanes <= DEC_16) {
				W2BYTEMSK(REG_0010_MODA1, HEX_FFFF >> (DEC_16 - stpe_info.ctrl_lanes),
					  REG_0010_MODA1_REG_GCR_PE_EN_CH_19_00_0);
			} else if (stpe_info.ctrl_lanes <= DEC_19) {
				W2BYTEMSK(REG_0010_MODA1, HEX_FFFF, REG_0010_MODA1_REG_GCR_PE_EN_CH_19_00_0);
				W2BYTEMSK(REG_0014_MODA1, HEX_F >> (DEC_19 - stpe_info.ctrl_lanes),
					  REG_0014_MODA1_REG_GCR_PE_EN_CH_19_00_1);
			} else {
				W2BYTEMSK(REG_0010_MODA1, HEX_FFFF, REG_0010_MODA1_REG_GCR_PE_EN_CH_19_00_0);
				W2BYTEMSK(REG_0014_MODA1, HEX_F, REG_0014_MODA1_REG_GCR_PE_EN_CH_19_00_1);
			}
		}
	break; //default disable
	default:
		//PE enable for all channels.
		W2BYTEMSK(REG_0010_MODA1, HEX_FFFF, REG_0010_MODA1_REG_GCR_PE_EN_CH_19_00_0);
		W2BYTEMSK(REG_0014_MODA1, HEX_F, REG_0014_MODA1_REG_GCR_PE_EN_CH_19_00_1);
		W2BYTEMSK(REG_0010_MODA2, HEX_FFFF, REG_0010_MODA2_REG_GCR_PE_EN_CH_39_20_0);
		W2BYTEMSK(REG_0014_MODA2, HEX_F, REG_0014_MODA2_REG_GCR_PE_EN_CH_39_20_1);
		W2BYTEMSK(REG_0010_MODA3, HEX_FFFF, REG_0010_MODA3_REG_GCR_PE_EN_CH_59_40_0);
		W2BYTEMSK(REG_0014_MODA3, HEX_F, REG_0014_MODA3_REG_GCR_PE_EN_CH_59_40_1);
		W2BYTEMSK(REG_000C_MODA4, HEX_F, REG_000C_MODA4_REG_GCR_PE_EN_CH_63_60);
	break;
	}

	if (stpe_info.pe_usr != 0) {
		if (stpe_info.common_pe != 0) {
			//pe_usr:True and common_pe: True , 0 is flase , >= 1 is True
			for (i = 1; i < stpe_info.ctrl_lanes; i++)
				stpe_info.pe_level[i] = stpe_info.pe_level[0];
		}
		switch (priv->pnl_lib_version) {
		case BOOT_PNL_VERSION0200: //0x2
		case BOOT_PNL_VERSION0203: //0x0203
			W2BYTEMSK(REG_0080_MODA1_V004, stpe_info.pe_level[0],
				  REG_0080_MODA1_V004_REG_GCR_PE_ADJ_CH00_0080);
			W2BYTEMSK(REG_0080_MODA1_V004, stpe_info.pe_level[1],
				  REG_0080_MODA1_V004_REG_GCR_PE_ADJ_CH01_0080);
			W2BYTEMSK(REG_0084_MODA1_V004, stpe_info.pe_level[2],
				  REG_0084_MODA1_V004_REG_GCR_PE_ADJ_CH02_0084);
			W2BYTEMSK(REG_0084_MODA1_V004, stpe_info.pe_level[3],
				  REG_0084_MODA1_V004_REG_GCR_PE_ADJ_CH03_0084);
			W2BYTEMSK(REG_0088_MODA1_V004, stpe_info.pe_level[4],
				  REG_0088_MODA1_V004_REG_GCR_PE_ADJ_CH04_0088);
			W2BYTEMSK(REG_0088_MODA1_V004, stpe_info.pe_level[5],
				  REG_0088_MODA1_V004_REG_GCR_PE_ADJ_CH05_0088);
			W2BYTEMSK(REG_008C_MODA1_V004, stpe_info.pe_level[6],
				  REG_008C_MODA1_V004_REG_GCR_PE_ADJ_CH06_008C);
			W2BYTEMSK(REG_008C_MODA1_V004, stpe_info.pe_level[7],
				  REG_008C_MODA1_V004_REG_GCR_PE_ADJ_CH07_008C);
			W2BYTEMSK(REG_0090_MODA1_V004, stpe_info.pe_level[8],
				  REG_0090_MODA1_V004_REG_GCR_PE_ADJ_CH08_0090);
			W2BYTEMSK(REG_0090_MODA1_V004, stpe_info.pe_level[9],
				  REG_0090_MODA1_V004_REG_GCR_PE_ADJ_CH09_0090);
			W2BYTEMSK(REG_0094_MODA1_V004, stpe_info.pe_level[10],
				  REG_0094_MODA1_V004_REG_GCR_PE_ADJ_CH10_0094);
			W2BYTEMSK(REG_0094_MODA1_V004, stpe_info.pe_level[11],
				  REG_0094_MODA1_V004_REG_GCR_PE_ADJ_CH11_0094);
			W2BYTEMSK(REG_0098_MODA1_V004, stpe_info.pe_level[12],
				  REG_0098_MODA1_V004_REG_GCR_PE_ADJ_CH12_0098);
			W2BYTEMSK(REG_0098_MODA1_V004, stpe_info.pe_level[13],
				  REG_0098_MODA1_V004_REG_GCR_PE_ADJ_CH13_0098);
			W2BYTEMSK(REG_009C_MODA1_V004, stpe_info.pe_level[14],
				  REG_009C_MODA1_V004_REG_GCR_PE_ADJ_CH14_009C);
			W2BYTEMSK(REG_009C_MODA1_V004, stpe_info.pe_level[15],
				  REG_009C_MODA1_V004_REG_GCR_PE_ADJ_CH15_009C);
			W2BYTEMSK(REG_0098_MODA2_V004, stpe_info.pe_level[16],
				  REG_0098_MODA2_V004_REG_GCR_PE_ADJ_CH32_0098);
			W2BYTEMSK(REG_0098_MODA2_V004, stpe_info.pe_level[17],
				  REG_0098_MODA2_V004_REG_GCR_PE_ADJ_CH33_0098);
			W2BYTEMSK(REG_009C_MODA2_V004, stpe_info.pe_level[18],
				  REG_009C_MODA2_V004_REG_GCR_PE_ADJ_CH34_009C);
			W2BYTEMSK(REG_009C_MODA2_V004, stpe_info.pe_level[19],
				  REG_009C_MODA2_V004_REG_GCR_PE_ADJ_CH35_009C);
			W2BYTEMSK(REG_00A0_MODA2_V004, stpe_info.pe_level[20],
				  REG_00A0_MODA2_V004_REG_GCR_PE_ADJ_CH36_00A0);
			W2BYTEMSK(REG_00A0_MODA2_V004, stpe_info.pe_level[21],
				  REG_00A0_MODA2_V004_REG_GCR_PE_ADJ_CH37_00A0);
			W2BYTEMSK(REG_00A4_MODA2_V004, stpe_info.pe_level[22],
				  REG_00A4_MODA2_V004_REG_GCR_PE_ADJ_CH38_00A4);
			W2BYTEMSK(REG_00A4_MODA2_V004, stpe_info.pe_level[23],
				  REG_00A4_MODA2_V004_REG_GCR_PE_ADJ_CH39_00A4);
		break;
		case BOOT_PNL_VERSION0400:
		case BOOT_PNL_VERSION0600:
			W2BYTEMSK(REG_0080_MODA1_V004, stpe_info.pe_level[0],
				  REG_0080_MODA1_V004_REG_GCR_PE_ADJ_CH00_0080);
			W2BYTEMSK(REG_0080_MODA1_V004, stpe_info.pe_level[1],
				  REG_0080_MODA1_V004_REG_GCR_PE_ADJ_CH01_0080);
			W2BYTEMSK(REG_0084_MODA1_V004, stpe_info.pe_level[2],
				  REG_0084_MODA1_V004_REG_GCR_PE_ADJ_CH02_0084);
			W2BYTEMSK(REG_0084_MODA1_V004, stpe_info.pe_level[3],
				  REG_0084_MODA1_V004_REG_GCR_PE_ADJ_CH03_0084);
			W2BYTEMSK(REG_0088_MODA1_V004, stpe_info.pe_level[4],
				  REG_0088_MODA1_V004_REG_GCR_PE_ADJ_CH04_0088);
			W2BYTEMSK(REG_0088_MODA1_V004, stpe_info.pe_level[5],
				  REG_0088_MODA1_V004_REG_GCR_PE_ADJ_CH05_0088);
			W2BYTEMSK(REG_008C_MODA1_V004, stpe_info.pe_level[6],
				  REG_008C_MODA1_V004_REG_GCR_PE_ADJ_CH06_008C);
			W2BYTEMSK(REG_008C_MODA1_V004, stpe_info.pe_level[7],
				  REG_008C_MODA1_V004_REG_GCR_PE_ADJ_CH07_008C);
			W2BYTEMSK(REG_0090_MODA1_V004, stpe_info.pe_level[8],
				  REG_0090_MODA1_V004_REG_GCR_PE_ADJ_CH08_0090);
			W2BYTEMSK(REG_0090_MODA1_V004, stpe_info.pe_level[9],
				  REG_0090_MODA1_V004_REG_GCR_PE_ADJ_CH09_0090);
			W2BYTEMSK(REG_0094_MODA1_V004, stpe_info.pe_level[10],
				  REG_0094_MODA1_V004_REG_GCR_PE_ADJ_CH10_0094);
			W2BYTEMSK(REG_0094_MODA1_V004, stpe_info.pe_level[11],
				  REG_0094_MODA1_V004_REG_GCR_PE_ADJ_CH11_0094);
			W2BYTEMSK(REG_0098_MODA1_V004, stpe_info.pe_level[12],
				  REG_0098_MODA1_V004_REG_GCR_PE_ADJ_CH12_0098);
			W2BYTEMSK(REG_0098_MODA1_V004, stpe_info.pe_level[13],
				  REG_0098_MODA1_V004_REG_GCR_PE_ADJ_CH13_0098);
			W2BYTEMSK(REG_009C_MODA1_V004, stpe_info.pe_level[14],
				  REG_009C_MODA1_V004_REG_GCR_PE_ADJ_CH14_009C);
			W2BYTEMSK(REG_009C_MODA1_V004, stpe_info.pe_level[15],
				  REG_009C_MODA1_V004_REG_GCR_PE_ADJ_CH15_009C);
			W2BYTEMSK(REG_00A0_MODA1_V004, stpe_info.pe_level[16],
				  REG_00A0_MODA1_V004_REG_GCR_PE_ADJ_CH16_00A0);
			W2BYTEMSK(REG_00A0_MODA1_V004, stpe_info.pe_level[17],
				  REG_00A0_MODA1_V004_REG_GCR_PE_ADJ_CH17_00A0);
			W2BYTEMSK(REG_00A4_MODA1_V004, stpe_info.pe_level[18],
				  REG_00A4_MODA1_V004_REG_GCR_PE_ADJ_CH18_00A4);
			W2BYTEMSK(REG_00A4_MODA1_V004, stpe_info.pe_level[19],
				  REG_00A4_MODA1_V004_REG_GCR_PE_ADJ_CH19_00A4);
			W2BYTEMSK(REG_0080_MODA2_V004, stpe_info.pe_level[20],
				  REG_0080_MODA2_V004_REG_GCR_PE_ADJ_CH20_0080);
			W2BYTEMSK(REG_0080_MODA2_V004, stpe_info.pe_level[21],
				  REG_0080_MODA2_V004_REG_GCR_PE_ADJ_CH21_0080);
			W2BYTEMSK(REG_0084_MODA2_V004, stpe_info.pe_level[22],
				  REG_0084_MODA2_V004_REG_GCR_PE_ADJ_CH22_0084);
			W2BYTEMSK(REG_0084_MODA2_V004, stpe_info.pe_level[23],
				  REG_0084_MODA2_V004_REG_GCR_PE_ADJ_CH23_0084);
			W2BYTEMSK(REG_0088_MODA2_V004, stpe_info.pe_level[24],
				  REG_0088_MODA2_V004_REG_GCR_PE_ADJ_CH24_0088);
			W2BYTEMSK(REG_0088_MODA2_V004, stpe_info.pe_level[25],
				  REG_0088_MODA2_V004_REG_GCR_PE_ADJ_CH25_0088);
			W2BYTEMSK(REG_008C_MODA2_V004, stpe_info.pe_level[26],
				  REG_008C_MODA2_V004_REG_GCR_PE_ADJ_CH26_008C);
			W2BYTEMSK(REG_008C_MODA2_V004, stpe_info.pe_level[27],
				  REG_008C_MODA2_V004_REG_GCR_PE_ADJ_CH27_008C);
			W2BYTEMSK(REG_0090_MODA2_V004, stpe_info.pe_level[28],
				  REG_0090_MODA2_V004_REG_GCR_PE_ADJ_CH28_0090);
			W2BYTEMSK(REG_0090_MODA2_V004, stpe_info.pe_level[29],
				  REG_0090_MODA2_V004_REG_GCR_PE_ADJ_CH29_0090);
			W2BYTEMSK(REG_0094_MODA2_V004, stpe_info.pe_level[30],
				  REG_0094_MODA2_V004_REG_GCR_PE_ADJ_CH30_0094);
			W2BYTEMSK(REG_0094_MODA2_V004, stpe_info.pe_level[31],
				  REG_0094_MODA2_V004_REG_GCR_PE_ADJ_CH31_0094);
			W2BYTEMSK(REG_0098_MODA2_V004, stpe_info.pe_level[32],
				  REG_0098_MODA2_V004_REG_GCR_PE_ADJ_CH32_0098);
			W2BYTEMSK(REG_0098_MODA2_V004, stpe_info.pe_level[33],
				  REG_0098_MODA2_V004_REG_GCR_PE_ADJ_CH33_0098);
			W2BYTEMSK(REG_009C_MODA2_V004, stpe_info.pe_level[34],
				  REG_009C_MODA2_V004_REG_GCR_PE_ADJ_CH34_009C);
			W2BYTEMSK(REG_009C_MODA2_V004, stpe_info.pe_level[35],
				  REG_009C_MODA2_V004_REG_GCR_PE_ADJ_CH35_009C);
			W2BYTEMSK(REG_00A0_MODA2_V004, stpe_info.pe_level[36],
				  REG_00A0_MODA2_V004_REG_GCR_PE_ADJ_CH36_00A0);
			W2BYTEMSK(REG_00A0_MODA2_V004, stpe_info.pe_level[37],
				  REG_00A0_MODA2_V004_REG_GCR_PE_ADJ_CH37_00A0);
			W2BYTEMSK(REG_00A4_MODA2_V004, stpe_info.pe_level[38],
				  REG_00A4_MODA2_V004_REG_GCR_PE_ADJ_CH38_00A4);
			W2BYTEMSK(REG_00A4_MODA2_V004, stpe_info.pe_level[39],
				  REG_00A4_MODA2_V004_REG_GCR_PE_ADJ_CH39_00A4);
		break;
		case BOOT_PNL_VERSION0500:
			W2BYTEMSK(REG_0080_MODA1_V005, stpe_info.pe_level[0],
				  REG_0080_MODA1_V005_REG_GCR_PE_ADJ_CH00_0080);
			W2BYTEMSK(REG_0080_MODA1_V005, stpe_info.pe_level[1],
				  REG_0080_MODA1_V005_REG_GCR_PE_ADJ_CH01_0080);
			W2BYTEMSK(REG_0084_MODA1_V005, stpe_info.pe_level[2],
				  REG_0084_MODA1_V005_REG_GCR_PE_ADJ_CH02_0084);
			W2BYTEMSK(REG_0084_MODA1_V005, stpe_info.pe_level[3],
				  REG_0084_MODA1_V005_REG_GCR_PE_ADJ_CH03_0084);
			W2BYTEMSK(REG_0088_MODA1_V005, stpe_info.pe_level[4],
				  REG_0088_MODA1_V005_REG_GCR_PE_ADJ_CH04_0088);
			W2BYTEMSK(REG_0088_MODA1_V005, stpe_info.pe_level[5],
				  REG_0088_MODA1_V005_REG_GCR_PE_ADJ_CH05_0088);
			W2BYTEMSK(REG_008C_MODA1_V005, stpe_info.pe_level[6],
				  REG_008C_MODA1_V005_REG_GCR_PE_ADJ_CH06_008C);
			W2BYTEMSK(REG_008C_MODA1_V005, stpe_info.pe_level[7],
				  REG_008C_MODA1_V005_REG_GCR_PE_ADJ_CH07_008C);
			W2BYTEMSK(REG_0090_MODA1_V005, stpe_info.pe_level[8],
				  REG_0090_MODA1_V005_REG_GCR_PE_ADJ_CH08_0090);
			W2BYTEMSK(REG_0090_MODA1_V005, stpe_info.pe_level[9],
				  REG_0090_MODA1_V005_REG_GCR_PE_ADJ_CH09_0090);
			W2BYTEMSK(REG_0094_MODA1_V005, stpe_info.pe_level[10],
				  REG_0094_MODA1_V005_REG_GCR_PE_ADJ_CH10_0094);
			W2BYTEMSK(REG_0094_MODA1_V005, stpe_info.pe_level[11],
				  REG_0094_MODA1_V005_REG_GCR_PE_ADJ_CH11_0094);
			W2BYTEMSK(REG_0098_MODA1_V005, stpe_info.pe_level[12],
				  REG_0098_MODA1_V005_REG_GCR_PE_ADJ_CH12_0098);
			W2BYTEMSK(REG_0098_MODA1_V005, stpe_info.pe_level[13],
				  REG_0098_MODA1_V005_REG_GCR_PE_ADJ_CH13_0098);
			W2BYTEMSK(REG_009C_MODA1_V005, stpe_info.pe_level[14],
				  REG_009C_MODA1_V005_REG_GCR_PE_ADJ_CH14_009C);
			W2BYTEMSK(REG_009C_MODA1_V005, stpe_info.pe_level[15],
				  REG_009C_MODA1_V005_REG_GCR_PE_ADJ_CH15_009C);
			W2BYTEMSK(REG_00A0_MODA1_V005, stpe_info.pe_level[16],
				  REG_00A0_MODA1_V005_REG_GCR_PE_ADJ_CH16_00A0);
			W2BYTEMSK(REG_00A0_MODA1_V005, stpe_info.pe_level[17],
				  REG_00A0_MODA1_V005_REG_GCR_PE_ADJ_CH17_00A0);
			W2BYTEMSK(REG_00A4_MODA1_V005, stpe_info.pe_level[18],
				  REG_00A4_MODA1_V005_REG_GCR_PE_ADJ_CH18_00A4);
			W2BYTEMSK(REG_00A4_MODA1_V005, stpe_info.pe_level[19],
				  REG_00A4_MODA1_V005_REG_GCR_PE_ADJ_CH19_00A4);
		break;
		default:
			W2BYTEMSK(REG_0080_MODA1, stpe_info.pe_level[0],
				  REG_0080_MODA1_REG_GCR_PE_ADJ_CH00);
			W2BYTEMSK(REG_0080_MODA1, stpe_info.pe_level[1],
				  REG_0080_MODA1_REG_GCR_PE_ADJ_CH01);
			W2BYTEMSK(REG_0084_MODA1, stpe_info.pe_level[2],
				  REG_0084_MODA1_REG_GCR_PE_ADJ_CH02);
			W2BYTEMSK(REG_0084_MODA1, stpe_info.pe_level[3],
				  REG_0084_MODA1_REG_GCR_PE_ADJ_CH03);
			W2BYTEMSK(REG_0088_MODA1, stpe_info.pe_level[4],
				  REG_0088_MODA1_REG_GCR_PE_ADJ_CH04);
			W2BYTEMSK(REG_0088_MODA1, stpe_info.pe_level[5],
				  REG_0088_MODA1_REG_GCR_PE_ADJ_CH05);
			W2BYTEMSK(REG_008C_MODA1, stpe_info.pe_level[6],
				  REG_008C_MODA1_REG_GCR_PE_ADJ_CH06);
			W2BYTEMSK(REG_008C_MODA1, stpe_info.pe_level[7],
				  REG_008C_MODA1_REG_GCR_PE_ADJ_CH07);
			W2BYTEMSK(REG_0090_MODA1, stpe_info.pe_level[8],
				  REG_0090_MODA1_REG_GCR_PE_ADJ_CH08);
			W2BYTEMSK(REG_0090_MODA1, stpe_info.pe_level[9],
				  REG_0090_MODA1_REG_GCR_PE_ADJ_CH09);
			W2BYTEMSK(REG_0094_MODA1, stpe_info.pe_level[10],
				  REG_0094_MODA1_REG_GCR_PE_ADJ_CH10);
			W2BYTEMSK(REG_0094_MODA1, stpe_info.pe_level[11],
				  REG_0094_MODA1_REG_GCR_PE_ADJ_CH11);
			W2BYTEMSK(REG_0098_MODA1, stpe_info.pe_level[12],
				  REG_0098_MODA1_REG_GCR_PE_ADJ_CH12);
			W2BYTEMSK(REG_0098_MODA1, stpe_info.pe_level[13],
				  REG_0098_MODA1_REG_GCR_PE_ADJ_CH13);
			W2BYTEMSK(REG_009C_MODA1, stpe_info.pe_level[14],
				  REG_009C_MODA1_REG_GCR_PE_ADJ_CH14);
			W2BYTEMSK(REG_009C_MODA1, stpe_info.pe_level[15],
				  REG_009C_MODA1_REG_GCR_PE_ADJ_CH15);
			W2BYTEMSK(REG_00A0_MODA1, stpe_info.pe_level[16],
				  REG_00A0_MODA1_REG_GCR_PE_ADJ_CH16);
			W2BYTEMSK(REG_00A0_MODA1, stpe_info.pe_level[17],
				  REG_00A0_MODA1_REG_GCR_PE_ADJ_CH17);
			W2BYTEMSK(REG_00A4_MODA1, stpe_info.pe_level[18],
				  REG_00A4_MODA1_REG_GCR_PE_ADJ_CH18);
			W2BYTEMSK(REG_00A4_MODA1, stpe_info.pe_level[19],
				  REG_00A4_MODA1_REG_GCR_PE_ADJ_CH19);
			W2BYTEMSK(REG_0080_MODA2, stpe_info.pe_level[20],
				  REG_0080_MODA2_REG_GCR_PE_ADJ_CH20);
			W2BYTEMSK(REG_0080_MODA2, stpe_info.pe_level[21],
				  REG_0080_MODA2_REG_GCR_PE_ADJ_CH21);
			W2BYTEMSK(REG_0084_MODA2, stpe_info.pe_level[22],
				  REG_0084_MODA2_REG_GCR_PE_ADJ_CH22);
			W2BYTEMSK(REG_0084_MODA2, stpe_info.pe_level[23],
				  REG_0084_MODA2_REG_GCR_PE_ADJ_CH23);
			W2BYTEMSK(REG_0088_MODA2, stpe_info.pe_level[24],
				  REG_0088_MODA2_REG_GCR_PE_ADJ_CH24);
			W2BYTEMSK(REG_0088_MODA2, stpe_info.pe_level[25],
				  REG_0088_MODA2_REG_GCR_PE_ADJ_CH25);
			W2BYTEMSK(REG_008C_MODA2, stpe_info.pe_level[26],
				  REG_008C_MODA2_REG_GCR_PE_ADJ_CH26);
			W2BYTEMSK(REG_008C_MODA2, stpe_info.pe_level[27],
				  REG_008C_MODA2_REG_GCR_PE_ADJ_CH27);
			W2BYTEMSK(REG_0090_MODA2, stpe_info.pe_level[28],
				  REG_0090_MODA2_REG_GCR_PE_ADJ_CH28);
			W2BYTEMSK(REG_0090_MODA2, stpe_info.pe_level[29],
				  REG_0090_MODA2_REG_GCR_PE_ADJ_CH29);
			W2BYTEMSK(REG_0094_MODA2, stpe_info.pe_level[30],
				  REG_0094_MODA2_REG_GCR_PE_ADJ_CH30);
			W2BYTEMSK(REG_0094_MODA2, stpe_info.pe_level[31],
				  REG_0094_MODA2_REG_GCR_PE_ADJ_CH31);
			W2BYTEMSK(REG_0098_MODA2, stpe_info.pe_level[32],
				  REG_0098_MODA2_REG_GCR_PE_ADJ_CH32);
			W2BYTEMSK(REG_0098_MODA2, stpe_info.pe_level[33],
				  REG_0098_MODA2_REG_GCR_PE_ADJ_CH33);
			W2BYTEMSK(REG_009C_MODA2, stpe_info.pe_level[34],
				  REG_009C_MODA2_REG_GCR_PE_ADJ_CH34);
			W2BYTEMSK(REG_009C_MODA2, stpe_info.pe_level[35],
				  REG_009C_MODA2_REG_GCR_PE_ADJ_CH35);
			W2BYTEMSK(REG_00A0_MODA2, stpe_info.pe_level[36],
				  REG_00A0_MODA2_REG_GCR_PE_ADJ_CH36);
			W2BYTEMSK(REG_00A0_MODA2, stpe_info.pe_level[37],
				  REG_00A0_MODA2_REG_GCR_PE_ADJ_CH37);
			W2BYTEMSK(REG_00A4_MODA2, stpe_info.pe_level[38],
				  REG_00A4_MODA2_REG_GCR_PE_ADJ_CH38);
			W2BYTEMSK(REG_00A4_MODA2, stpe_info.pe_level[39],
				  REG_00A4_MODA2_REG_GCR_PE_ADJ_CH39);
			W2BYTEMSK(REG_0080_MODA3, stpe_info.pe_level[40],
				  REG_0080_MODA3_REG_GCR_PE_ADJ_CH40);
			W2BYTEMSK(REG_0080_MODA3, stpe_info.pe_level[41],
				  REG_0080_MODA3_REG_GCR_PE_ADJ_CH41);
			W2BYTEMSK(REG_0084_MODA3, stpe_info.pe_level[42],
				  REG_0084_MODA3_REG_GCR_PE_ADJ_CH42);
			W2BYTEMSK(REG_0084_MODA3, stpe_info.pe_level[43],
				  REG_0084_MODA3_REG_GCR_PE_ADJ_CH43);
			W2BYTEMSK(REG_0088_MODA3, stpe_info.pe_level[44],
				  REG_0088_MODA3_REG_GCR_PE_ADJ_CH44);
			W2BYTEMSK(REG_0088_MODA3, stpe_info.pe_level[45],
				  REG_0088_MODA3_REG_GCR_PE_ADJ_CH45);
			W2BYTEMSK(REG_008C_MODA3, stpe_info.pe_level[46],
				  REG_008C_MODA3_REG_GCR_PE_ADJ_CH46);
			W2BYTEMSK(REG_008C_MODA3, stpe_info.pe_level[47],
				  REG_008C_MODA3_REG_GCR_PE_ADJ_CH47);
			W2BYTEMSK(REG_0090_MODA3, stpe_info.pe_level[48],
				  REG_0090_MODA3_REG_GCR_PE_ADJ_CH48);
			W2BYTEMSK(REG_0090_MODA3, stpe_info.pe_level[49],
				  REG_0090_MODA3_REG_GCR_PE_ADJ_CH49);
			W2BYTEMSK(REG_0094_MODA3, stpe_info.pe_level[50],
				  REG_0094_MODA3_REG_GCR_PE_ADJ_CH50);
			W2BYTEMSK(REG_0094_MODA3, stpe_info.pe_level[51],
				  REG_0094_MODA3_REG_GCR_PE_ADJ_CH51);
			W2BYTEMSK(REG_0098_MODA3, stpe_info.pe_level[52],
				  REG_0098_MODA3_REG_GCR_PE_ADJ_CH52);
			W2BYTEMSK(REG_0098_MODA3, stpe_info.pe_level[53],
				  REG_0098_MODA3_REG_GCR_PE_ADJ_CH53);
			W2BYTEMSK(REG_009C_MODA3, stpe_info.pe_level[54],
				  REG_009C_MODA3_REG_GCR_PE_ADJ_CH54);
			W2BYTEMSK(REG_009C_MODA3, stpe_info.pe_level[55],
				  REG_009C_MODA3_REG_GCR_PE_ADJ_CH55);
			W2BYTEMSK(REG_00A0_MODA3, stpe_info.pe_level[56],
				  REG_00A0_MODA3_REG_GCR_PE_ADJ_CH56);
			W2BYTEMSK(REG_00A0_MODA3, stpe_info.pe_level[57],
				  REG_00A0_MODA3_REG_GCR_PE_ADJ_CH57);
			W2BYTEMSK(REG_00A4_MODA3, stpe_info.pe_level[58],
				  REG_00A4_MODA3_REG_GCR_PE_ADJ_CH58);
			W2BYTEMSK(REG_00A4_MODA3, stpe_info.pe_level[59],
				  REG_00A4_MODA3_REG_GCR_PE_ADJ_CH59);
			W2BYTEMSK(REG_0080_MODA4, stpe_info.pe_level[60],
				  REG_0080_MODA4_REG_GCR_PE_ADJ_CH60);
			W2BYTEMSK(REG_0080_MODA4, stpe_info.pe_level[61],
				  REG_0080_MODA4_REG_GCR_PE_ADJ_CH61);
			W2BYTEMSK(REG_0084_MODA4, stpe_info.pe_level[62],
				  REG_0084_MODA4_REG_GCR_PE_ADJ_CH62);
			W2BYTEMSK(REG_0084_MODA4, stpe_info.pe_level[63],
				  REG_0084_MODA4_REG_GCR_PE_ADJ_CH63);
		break;
		}
	} else {
		switch (priv->pnl_lib_version) {
		case BOOT_PNL_VERSION0400:
		case BOOT_PNL_VERSION0500:
		case BOOT_PNL_VERSION0600:
			//_setAll_pe_value(0x0); //use hw default value
		break;
		default:
			_setAll_pe_value(HEX_1010);
		break;
		}
	}
}

void mtk_swing_level_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	enum drm_en_pnl_group epnl_group = E_PNL_GROUP_0;
	st_out_swing_level stswing_info = {0};
	__u16 swing_val = 0;
	__u32 i = 0;

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->epnl_group < E_PNL_GROUP_MAX)
		epnl_group = priv->epnl_group;

	memcpy(&stswing_info, &priv->swing_info[epnl_group], sizeof(st_out_swing_level));

	if ((priv->linktype == E_LINK_VB1) && (priv->pnl_lib_version == BOOT_PNL_VERSION0100))
		vby1_set_pn_swap(priv->pnl_lib_version); //PN swap setting

	if (stswing_info.usr_swing_level != 0 && priv->linktype == E_LINK_VB1) {
		//usr_swing_level : True , 0 is flase , >= 1 is True
		if (stswing_info.common_swing != 0) {
			//common_swing: True , 0 is flase , >= 1 is True
			UBOOT_DEBUG("[pnl]common swing value = %d, ctrl_lanes = %d\n",
				    stswing_info.swing_level[0],
				    stswing_info.ctrl_lanes);
			for (i = 1; i < stswing_info.ctrl_lanes; i++)
				stswing_info.swing_level[i] = stswing_info.swing_level[0];
		}

		swing_val = (stswing_info.swing_level[3] & 0xF) << 12 |
					(stswing_info.swing_level[2] & 0xF) << 8 |
					(stswing_info.swing_level[1] & 0xF) << 4 |
					(stswing_info.swing_level[0] & 0xF);
		UBOOT_DEBUG("[pnl]swing value ch3~0 = %d\n", swing_val);
		W2BYTEMSK(REG_0140_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch0-ch3

		swing_val = (stswing_info.swing_level[7] & 0xF) << 12 |
					(stswing_info.swing_level[6] & 0xF) << 8 |
					(stswing_info.swing_level[5] & 0xF) << 4 |
					(stswing_info.swing_level[4] & 0xF);
		UBOOT_DEBUG("[pnl]swing value ch7~4 = %d\n", swing_val);
		W2BYTEMSK(REG_0144_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch4-ch7

		swing_val = (stswing_info.swing_level[11] & 0xF) << 12 |
					(stswing_info.swing_level[10] & 0xF) << 8 |
					(stswing_info.swing_level[9] & 0xF) << 4 |
					(stswing_info.swing_level[8] & 0xF);
		UBOOT_DEBUG("[pnl]swing value ch11~8 = %d\n", swing_val);
		W2BYTEMSK(REG_0148_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch8-ch11

		swing_val = (stswing_info.swing_level[15] & 0xF) << 12 |
					(stswing_info.swing_level[14] & 0xF) << 8 |
					(stswing_info.swing_level[13] & 0xF) << 4 |
					(stswing_info.swing_level[12] & 0xF);
		UBOOT_DEBUG("[pnl]swing value ch15~12 = %d\n", swing_val);
		W2BYTEMSK(REG_014C_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch12-ch15

		swing_val = (stswing_info.swing_level[19] & 0xF) << 12 |
					(stswing_info.swing_level[18] & 0xF) << 8 |
					(stswing_info.swing_level[17] & 0xF) << 4 |
					(stswing_info.swing_level[16] & 0xF);
		UBOOT_DEBUG("[pnl]swing value ch19~16 = %d\n", swing_val);
		W2BYTEMSK(REG_0150_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch16-ch19

		swing_val = (stswing_info.swing_level[23] & 0xF) << 12 |
					(stswing_info.swing_level[22] & 0xF) << 8 |
					(stswing_info.swing_level[21] & 0xF) << 4 |
					(stswing_info.swing_level[20] & 0xF);
		UBOOT_DEBUG("[pnl]swing value ch23~20 = %d\n", swing_val);
		W2BYTEMSK(REG_0140_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch20-ch23

		if (priv->pnl_lib_version != BOOT_PNL_VERSION0203 &&
		    priv->pnl_lib_version != BOOT_PNL_VERSION0200) {
			swing_val = (stswing_info.swing_level[27] & 0xF) << 12 |
						(stswing_info.swing_level[26] & 0xF) << 8 |
						(stswing_info.swing_level[25] & 0xF) << 4 |
						(stswing_info.swing_level[24] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch27~24 = %d\n", swing_val);
			W2BYTEMSK(REG_0144_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch24-ch27

			swing_val = (stswing_info.swing_level[31] & 0xF) << 12 |
						(stswing_info.swing_level[30] & 0xF) << 8 |
						(stswing_info.swing_level[29] & 0xF) << 4 |
						(stswing_info.swing_level[28] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch31~28 = %d\n", swing_val);
			W2BYTEMSK(REG_0148_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch28-ch31

			swing_val = (stswing_info.swing_level[35] & 0xF) << 12 |
						(stswing_info.swing_level[34] & 0xF) << 8 |
						(stswing_info.swing_level[33] & 0xF) << 4 |
						(stswing_info.swing_level[32] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch35~32 = %d\n", swing_val);
			W2BYTEMSK(REG_014C_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch32-ch35

			swing_val = (stswing_info.swing_level[39] & 0xF) << 12 |
						(stswing_info.swing_level[38] & 0xF) << 8 |
						(stswing_info.swing_level[37] & 0xF) << 4 |
						(stswing_info.swing_level[36] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch39~36 = %d\n", swing_val);
			W2BYTEMSK(REG_0150_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch36-ch39
			swing_val = (stswing_info.swing_level[43] & 0xF) << 12 |
						(stswing_info.swing_level[42] & 0xF) << 8 |
						(stswing_info.swing_level[41] & 0xF) << 4 |
						(stswing_info.swing_level[40] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch43~40 = %d\n", swing_val);
			W2BYTEMSK(REG_0140_MODA3, swing_val, Fld(16, 0, AC_FULLW10));//ch40-ch43
			swing_val = (stswing_info.swing_level[47] & 0xF) << 12 |
						(stswing_info.swing_level[46] & 0xF) << 8 |
						(stswing_info.swing_level[45] & 0xF) << 4 |
						(stswing_info.swing_level[44] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch47~44 = %d\n", swing_val);
			W2BYTEMSK(REG_0144_MODA3, swing_val, Fld(16, 0, AC_FULLW10));//ch44-ch47
			swing_val = (stswing_info.swing_level[51] & 0xF) << 12 |
						(stswing_info.swing_level[50] & 0xF) << 8 |
						(stswing_info.swing_level[49] & 0xF) << 4 |
						(stswing_info.swing_level[48] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch51~48 = %d\n", swing_val);
			W2BYTEMSK(REG_0148_MODA3, swing_val, Fld(16, 0, AC_FULLW10));//ch48-ch51
			swing_val = (stswing_info.swing_level[55] & 0xF) << 12 |
						(stswing_info.swing_level[54] & 0xF) << 8 |
						(stswing_info.swing_level[53] & 0xF) << 4 |
						(stswing_info.swing_level[52] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch55~52 = %d\n", swing_val);
			W2BYTEMSK(REG_014C_MODA3, swing_val, Fld(16, 0, AC_FULLW10));//ch52-ch55
			swing_val = (stswing_info.swing_level[59] & 0xF) << 12 |
						(stswing_info.swing_level[58] & 0xF) << 8 |
						(stswing_info.swing_level[57] & 0xF) << 4 |
						(stswing_info.swing_level[56] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch59~56 = %d\n", swing_val);
			W2BYTEMSK(REG_0150_MODA3, swing_val, Fld(16, 0, AC_FULLW10));//ch56-ch59
			swing_val = (stswing_info.swing_level[63] & 0xF) << 12 |
						(stswing_info.swing_level[62] & 0xF) << 8 |
						(stswing_info.swing_level[61] & 0xF) << 4 |
						(stswing_info.swing_level[60] & 0xF);
			UBOOT_DEBUG("[pnl]swing value ch63~60 = %d\n", swing_val);
			W2BYTEMSK(REG_0140_MODA4, swing_val, Fld(16, 0, AC_FULLW10));//ch60-ch63
		}
	}

	if (stswing_info.usr_swing_level != 0 && priv->linktype == E_LINK_LVDS) {
		if (stswing_info.common_swing != 0) {
			//common_swing: True , 0 is flase , >= 1 is True
			UBOOT_DEBUG("[pnl]LVDS icon common swing value = %d, ctrl_lanes = %d\n",
			    stswing_info.swing_level[0],
			    stswing_info.ctrl_lanes);
			for (i = 1; i < stswing_info.ctrl_lanes; i++)
				stswing_info.swing_level[i] = stswing_info.swing_level[0];
		}

		swing_val = (stswing_info.swing_level[1] & 0xFF) << 8 |
					(stswing_info.swing_level[0] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch1~0 = %d\n", swing_val);
		W2BYTEMSK(REG_00B0_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch0-ch1

		swing_val = (stswing_info.swing_level[3] & 0xFF) << 8 |
					(stswing_info.swing_level[2] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch3~2 = %d\n", swing_val);
		W2BYTEMSK(REG_00B4_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch2-ch3

		swing_val = (stswing_info.swing_level[5] & 0xFF) << 8 |
					(stswing_info.swing_level[4] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch5~4 = %d\n", swing_val);
		W2BYTEMSK(REG_00B8_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch4-ch5

		swing_val = (stswing_info.swing_level[7] & 0xFF) << 8 |
					(stswing_info.swing_level[6] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch7~6 = %d\n", swing_val);
		W2BYTEMSK(REG_00BC_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch6-ch7

		swing_val = (stswing_info.swing_level[9] & 0xFF) << 8 |
					(stswing_info.swing_level[8] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch9~8 = %d\n", swing_val);
		W2BYTEMSK(REG_00C0_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch8-ch9

		swing_val = (stswing_info.swing_level[11] & 0xFF) << 8 |
					(stswing_info.swing_level[10] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch11~10 = %d\n", swing_val);
		W2BYTEMSK(REG_00C4_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch10-ch11

		swing_val = (stswing_info.swing_level[13] & 0xFF) << 8 |
					(stswing_info.swing_level[12] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch13~12 = %d\n", swing_val);
		W2BYTEMSK(REG_00C8_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch12-ch13

		swing_val = (stswing_info.swing_level[15] & 0xFF) << 8 |
					(stswing_info.swing_level[14] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch15~14 = %d\n", swing_val);
		W2BYTEMSK(REG_00CC_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch14-ch15

		swing_val = (stswing_info.swing_level[17] & 0xFF) << 8 |
					(stswing_info.swing_level[16] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch17~16 = %d\n", swing_val);
		W2BYTEMSK(REG_00D0_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch16-ch17

		swing_val = (stswing_info.swing_level[19] & 0xFF) << 8 |
					(stswing_info.swing_level[18] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch19~18 = %d\n", swing_val);
		W2BYTEMSK(REG_00D4_MODA1, swing_val, Fld(16, 0, AC_FULLW10));//ch18-ch19

		swing_val = (stswing_info.swing_level[21] & 0xFF) << 8 |
					(stswing_info.swing_level[20] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch21~20 = %d\n", swing_val);
		W2BYTEMSK(REG_00B0_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch20-ch21

		swing_val = (stswing_info.swing_level[23] & 0xFF) << 8 |
					(stswing_info.swing_level[22] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch23~22 = %d\n", swing_val);
		W2BYTEMSK(REG_00B4_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch22-ch23

		swing_val = (stswing_info.swing_level[25] & 0xFF) << 8 |
					(stswing_info.swing_level[24] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch25~24 = %d\n", swing_val);
		W2BYTEMSK(REG_00B8_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch24-ch25

		swing_val = (stswing_info.swing_level[27] & 0xFF) << 8 |
					(stswing_info.swing_level[26] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch27~26 = %d\n", swing_val);
		W2BYTEMSK(REG_00BC_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch26-ch27

		swing_val = (stswing_info.swing_level[29] & 0xFF) << 8 |
					(stswing_info.swing_level[28] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch29~28 = %d\n", swing_val);
		W2BYTEMSK(REG_00C0_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch28-ch29

		swing_val = (stswing_info.swing_level[31] & 0xFF) << 8 |
					(stswing_info.swing_level[30] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch31~30 = %d\n", swing_val);
		W2BYTEMSK(REG_00C4_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch30-ch31

		swing_val = (stswing_info.swing_level[33] & 0xFF) << 8 |
					(stswing_info.swing_level[32] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch33~32 = %d\n", swing_val);
		W2BYTEMSK(REG_00C8_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch32-ch33

		swing_val = (stswing_info.swing_level[35] & 0xFF) << 8 |
					(stswing_info.swing_level[34] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch35~34 = %d\n", swing_val);
		W2BYTEMSK(REG_00CC_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch34-ch35

		swing_val = (stswing_info.swing_level[37] & 0xFF) << 8 |
					(stswing_info.swing_level[36] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch37~36 = %d\n", swing_val);
		W2BYTEMSK(REG_00D0_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch36-ch37

		swing_val = (stswing_info.swing_level[39] & 0xFF) << 8 |
					(stswing_info.swing_level[38] & 0xFF);
		UBOOT_DEBUG("[pnl]swing value ch39~38 = %d\n", swing_val);
		W2BYTEMSK(REG_00D4_MODA2, swing_val, Fld(16, 0, AC_FULLW10));//ch38-ch39
	}
}

void mtk_skew_level_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_DEBUG("get device private fail\n");
		return;
	}

	UBOOT_DEBUG("Panel skew enable : %d\n", priv->skew_info.bPanelSkewCtrlEN);
	UBOOT_DEBUG("Panel skew ctrl lanes : %d\n", priv->skew_info.SkewCtrlLanes);

	for (int i = 0; i < priv->skew_info.SkewCtrlLanes; i++)
		UBOOT_DEBUG("Panel skew_level_lanes[%d] : %d\n", i, priv->skew_info.SkewLevel[i]);

	if (priv->skew_info.bPanelSkewCtrlEN && (priv->linktype == E_LINK_VB1 || priv->linktype == E_LINK_LVDS)) {
		if (priv->skew_info.SkewCtrlLanes <= DEC_16) {
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_0], REG_0070_MODA1_REG_FTUNE_SKEW_CH00);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_1], REG_0070_MODA1_REG_FTUNE_SKEW_CH01);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_2], REG_0070_MODA1_REG_FTUNE_SKEW_CH02);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_3], REG_0070_MODA1_REG_FTUNE_SKEW_CH03);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_4], REG_0070_MODA1_REG_FTUNE_SKEW_CH04);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_5], REG_0070_MODA1_REG_FTUNE_SKEW_CH05);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_6], REG_0070_MODA1_REG_FTUNE_SKEW_CH06);
			W2BYTEMSK(REG_0070_MODA1, priv->skew_info.SkewLevel[DEC_7], REG_0070_MODA1_REG_FTUNE_SKEW_CH07);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_8], REG_0074_MODA1_REG_FTUNE_SKEW_CH08);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_9], REG_0074_MODA1_REG_FTUNE_SKEW_CH09);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_10], REG_0074_MODA1_REG_FTUNE_SKEW_CH10);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_11], REG_0074_MODA1_REG_FTUNE_SKEW_CH11);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_12], REG_0074_MODA1_REG_FTUNE_SKEW_CH12);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_13], REG_0074_MODA1_REG_FTUNE_SKEW_CH13);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_14], REG_0074_MODA1_REG_FTUNE_SKEW_CH14);
			W2BYTEMSK(REG_0074_MODA1, priv->skew_info.SkewLevel[DEC_15], REG_0074_MODA1_REG_FTUNE_SKEW_CH15);
		}
	}
}

void mtk_SSC_control(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	u64 tmp = 0;
	u64 lpll_set = 0;
	u32 ssc_span = 0;
	u32 ssc_step = 0;
	const u32 Khz = 1000;
	const u32 Precision_unit = 10;
	u32 unit_align_vby1 = 1;
	st_out_ssc_ctrl stCtrl;
	enum drm_en_pnl_group epnl_group = E_PNL_GROUP_0;

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return;
	}

	if (priv->tcon_info.bUsingTCON && priv->tcon_info.stPanelInfo.u32SSC_TconBinCtrl == 0) {
		unit_align_vby1 = 10;
		stCtrl.ssc_en = priv->tcon_info.stPanelInfo.u32SSCEnable;
		stCtrl.ssc_modulation = priv->tcon_info.stPanelInfo.u32SSC_Fmodulation;
		stCtrl.ssc_deviation = priv->tcon_info.stPanelInfo.u32SSC_Percentage*unit_align_vby1;
		UBOOT_DEBUG("[%s,%5d] TCON control SSC value\n",__func__, __LINE__);
	} else {
		unit_align_vby1 = 1;
		if (priv->epnl_group < E_PNL_GROUP_MAX)
			epnl_group = priv->epnl_group;

		stCtrl.ssc_en = priv->ssc_info[epnl_group].ssc_en;
		stCtrl.ssc_modulation = priv->ssc_info[epnl_group].ssc_modulation;
		stCtrl.ssc_deviation = priv->ssc_info[epnl_group].ssc_deviation;
	}

	lpll_set = (u64)(((u64)(R2BYTEMSK(REG_0040_LPLL, REG_0040_LPLL_REG_PLL_SET_1)&0xFFFF))<<16);
	lpll_set = (u64)(((u64)(lpll_set)) | ((R2BYTEMSK(REG_003C_LPLL, REG_003C_LPLL_REG_PLL_SET_0)&0xFFFF)));
	UBOOT_DEBUG("\n  SSC LPLL set value : %x\n", (unsigned int)lpll_set);
	if (lpll_set == 0) {
		printf("[%s]LPLL_SET is 0. Check NG\n",__func__);
		return;
	}

	//Cal modulation (ssc span)
	if (stCtrl.ssc_modulation != 0) {
		if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
			priv->pnl_lib_version == BOOT_PNL_VERSION0600)
			tmp = (u64)((u64)MPLL_CLK_1296MHZ*LPLL_SPAN_FACTOR*LPLL_CAL_PARAM);
		else
			tmp = (u64)((u64)MPLL_CLK_864MHZ*LPLL_SPAN_FACTOR*LPLL_CAL_PARAM);
		UBOOT_DEBUG("\n  SSC tmp : %llx\n", tmp);
		tmp = (u64)((u64)(tmp)*Precision_unit); //for precision
		debug("\n  SSC tmp : %llx\n", tmp);
		tmp = (u64)((u64)(tmp)*Khz);
		debug("\n  SSC tmp : %llx\n", tmp);
		tmp = ((u64)(tmp*unit_align_vby1) / (stCtrl.ssc_modulation));
		UBOOT_DEBUG("\n  SSC tmp : %llx\n", tmp);
		UBOOT_DEBUG("\n  ssc_info.ssc_modulation : %x\n", stCtrl.ssc_modulation);
		tmp = (u64)((u64)(tmp)/lpll_set);
		debug("\n  SSC tmp : %llx\n", tmp);
		ssc_span = (u32)(tmp/Precision_unit);
		UBOOT_DEBUG("\n  SSC Span value : %x\n", ssc_span);

		W2BYTEMSK(REG_0060_LPLL, (ssc_span & 0x3FFF), REG_0060_LPLL_REG_LPLL_SPAN);
	}

	//ssc step (deviation)
	if (ssc_span != 0) {
		tmp = (u64)(lpll_set);
		debug("\n  SSC tmp : %llx\n", tmp);
		tmp = (u64)((u64)(tmp) * stCtrl.ssc_deviation);
		UBOOT_DEBUG("\n  SSC tmp : %llx\n", tmp);
		UBOOT_DEBUG("\n  ssc_info.ssc_deviation : %x\n", stCtrl.ssc_deviation);
		tmp = (u64)((u64)tmp / (Khz * Precision_unit * ssc_span));
		UBOOT_DEBUG("\n  SSC tmp : %llx, ssc_span :%x\n", tmp, ssc_span);
		ssc_step = (u32)tmp;
		UBOOT_DEBUG("\n  SSC Step value : %x\n", ssc_step);

		W2BYTEMSK(REG_005C_LPLL, (ssc_step&0xFFFF), REG_005C_LPLL_REG_LPLL_STEP);
	}

	//ssc enable
	W2BYTEMSK(REG_0034_LPLL, stCtrl.ssc_en, REG_0034_LPLL_REG_SSC_EN);
}

static u32 _mtk_get_efuse_val(u32 hwVersion, u16 subBank)
{
	u32 efuse_val = 0;
	u8 count = 0;

	W2BYTEMSK(EFUSE_BANK, (subBank<<2), Fld(16,0,AC_FULLW10));
	W2BYTEMSK(EFUSE_BANK, 1, Fld(1,13,AC_MSKB1));

	while (R2BYTEMSK(EFUSE_BANK,Fld(1,13,AC_MSKB1)) != 0) {
		mdelay(1);
		count++;
		if (count > TIME_OUT_CNT)
			break;
	}

	efuse_val = (R2BYTEMSK(EFUSE_VAL_MSB,Fld(16,0,AC_FULLW10))<<16) | R2BYTEMSK(EFUSE_VAL_LSB,Fld(16,0,AC_FULLW10));

	return efuse_val;
}

bool mtk_dump_tcon_efuse(u32 hwVersion)
{
	bool tcon_disable_bit = false;
	u32 efuse_val = 0;
	switch (hwVersion) {
	case BOOT_PNL_VERSION0400:
		efuse_val = _mtk_get_efuse_val(hwVersion, EFUSE_PPM_REG_TABLE_1);
		if ((efuse_val & EFUSE_PPM_REG_TABLE_1_TCON_DISABLE_BIT) == EFUSE_PPM_REG_TABLE_1_TCON_DISABLE_BIT)
			tcon_disable_bit = true;
		else
			tcon_disable_bit = false;
		break;
	default:
		break;
	}

	return tcon_disable_bit;
}

void efuse_set_lpllsetting(u32 hwVersion)
{
	u32 efuse_sub0D_val = 0;

	if (hwVersion == BOOT_PNL_VERSION0203) {
		//sub bank 0D
		efuse_sub0D_val = _mtk_get_efuse_val(hwVersion, MOD_ATOP_SUBBANK_0D);
		if ((efuse_sub0D_val & _BIT(LPLL_RETIME_CTRL)) == _BIT(LPLL_RETIME_CTRL)) {
			W2BYTEMSK(REG_00D8_LPLL, 1, Fld(1,0,AC_MSKB0));
			W2BYTEMSK(REG_0110_LPLL, 1, Fld(1,0,AC_MSKB0));
		} else {
			W2BYTEMSK(REG_00D8_LPLL, 0, Fld(1,0,AC_MSKB0));
			W2BYTEMSK(REG_0110_LPLL, 0, Fld(1,0,AC_MSKB0));
		}

		if ((efuse_sub0D_val & _BIT(LPLL_DELAY_TIME_CTRL)) == _BIT(LPLL_DELAY_TIME_CTRL)) {
			W2BYTEMSK(REG_00DC_LPLL, 1, Fld(1,3,AC_MSKB0));
			W2BYTEMSK(REG_0114_LPLL, 1, Fld(1,3,AC_MSKB0));
		} else {
			W2BYTEMSK(REG_00DC_LPLL, 0, Fld(1,3,AC_MSKB0));
			W2BYTEMSK(REG_0114_LPLL, 0, Fld(1,3,AC_MSKB0));
		}
	}
}


void mtk_dump_mod_efuse(struct udevice *dev)
{
	u32 efuse_val = 0;
	u32 efuse_sub0C_val = 0;
	u32 efuse_sub0D_val = 0;
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		printf("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0400)
		efuse_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK_VER004);
	else if (priv->pnl_lib_version == BOOT_PNL_VERSION0500)
		efuse_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK_VER005);
	else
		efuse_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK);

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0200 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0203 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
		//sub bank 0c
		efuse_sub0C_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK_0C);
		//sub bank 0D
		efuse_sub0D_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK_0D);
	} else if (priv->pnl_lib_version == BOOT_PNL_VERSION0500) {
		//sub bank 13
		efuse_sub0C_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK_13_VER005);
		//sub bank 14
		efuse_sub0D_val = _mtk_get_efuse_val(priv->pnl_lib_version, MOD_ATOP_SUBBANK_14_VER005);
	}

	UBOOT_DEBUG("Efuse value = 0x%x\n", efuse_val);

	//dump setting from efuse
	_efuse_set_rcon(dev, efuse_val);
	_efuse_set_biascon(dev, efuse_val, efuse_sub0C_val, efuse_sub0D_val);

	_efuse_set_rint(dev, efuse_val);
}

void mtk_pnl_controlbit_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	u16 metadata_low = 0,metadata_high = 0;

	//If CVRL_BIT_OFF OFF
	if (priv->cus_info.ctrl_bit_en != true) {
		UBOOT_DEBUG("ctrl_bit_en = 0x%x\n", priv->cus_info.ctrl_bit_en);
		return;
	}

	if (priv->pnl_lib_version == BOOT_PNL_VERSION0400 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0500 ||
		priv->pnl_lib_version == BOOT_PNL_VERSION0600) {
		metadata_low = metadata_low;
		metadata_high = metadata_high;
	} else {
		//Mdata V1
		W2BYTEMSK(REG_0020_MODV12,0x0201,Fld(16,0,AC_FULLW10));
		//[11:8]reg_meta_delay_num
		//[3]reg_meta_delay_auto
		//[2]reg_meta_mode
		//[1]reg_meta_test_en
		//[0]reg_meta_data_en
		W2BYTEMSK(REG_0024_MODV12,0x0010,Fld(16,0,AC_FULLW10));
		//[15:0]reg_meta_data_num
		W2BYTEMSK(REG_0028_MODV12,0x0000,Fld(16,0,AC_FULLW10));
		//[15:0]reg_meta_hs_sel

		metadata_low = 0x0100;//VG Stable Flag(VGSF)=TRUE at boot stage
		metadata_high = 0x0;

		//v1 data lane 1~16
		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));//v1_dat lsb[15:0]
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));//v1_dat msb[7:0]
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f40,Fld(16,0,AC_FULLW10));
		//[4:0]v1_address [6]db_enable[12:8]out numnber
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f60,Fld(16,0,AC_FULLW10));
		//[5]trig signal

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f41,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f61,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f42,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f62,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f43,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f63,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f44,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f64,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f45,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f65,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f46,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f66,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f47,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f67,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f48,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f60,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f49,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f69,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f4a,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f6a,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f4b,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f6b,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f4c,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f6c,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f4d,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f6d,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f4e,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f6e,Fld(16,0,AC_FULLW10));

		W2BYTEMSK(REG_0004_REG_META_DATA_TRANSFER_BKA35A,metadata_low,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_0008_REG_META_DATA_TRANSFER_BKA35A,metadata_high,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f4f,Fld(16,0,AC_FULLW10));
		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A,0x1f6f,Fld(16,0,AC_FULLW10));


		W2BYTEMSK(REG_000C_REG_META_DATA_TRANSFER_BKA35A, 0x1fc0,Fld(16,0,AC_FULLW10));//ouble buff trig
		W2BYTEMSK(REG_0028_REG_META_DATA_TRANSFER_BKA35A, 0x0040,Fld(16,0,AC_FULLW10));//sw trig out
	}


}

void mtk_extv_controlbit_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	//Mdata V2
	W2BYTEMSK(REG_0020_MODV22,0x0200,Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0024_MODV22,0x0010,Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0028_MODV22,0x0000,Fld(16,0,AC_FULLW10));

	//Lane 1 bit 0~bit 15 init value
	//bit[0:7]FNI=0, bit[8]VGSF=1,bit[12:14]FE SoC Type=001,bit[15]CBVF=0
	//24bit:0x001100
	W2BYTEMSK(REG_0040_MODV22,0x1100,Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0044_MODV22,0x0000,Fld(16,0,AC_FULLW10));

}

void mtk_gfx_controlbit_init(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	//lane1~lan4
	//lane1:bit[0:12]HTT,bit[14]GF=1,bit[15]VF=1
	//lane2:bit[0:11]VTT
	//lane3:bit[0:8]VTT
	u16 line1Ctr = 0x0, line2Ctr = 0x0, line3Ctr = 0x0, line4Ctr = 0x0;
	u16 valid_flag=0x1, gf_flag= 0x1;
	priv->typ_htt = priv->typ_htt & 0x1FFF;
	line1Ctr = priv->typ_htt | (valid_flag<<15) | (gf_flag<<14);
	line2Ctr = priv->typ_vtt & 0xFFF;
	line3Ctr = priv->de_hstart & 0x1FF;
	line4Ctr = priv->de_vstart & 0x7F;

	//Mdata OSD
	W2BYTEMSK(REG_0020_MODOSD2,0x0200,Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0024_MODOSD2,0x0010,Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0028_MODOSD2,0x0000,Fld(16,0,AC_FULLW10));

	//lane1~lan3
	W2BYTEMSK(REG_0040_MODOSD2,line1Ctr & 0xffff,Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0044_MODOSD2,(line2Ctr & 0xff),Fld(8,8,AC_MSKB1));
	W2BYTEMSK(REG_0048_MODOSD2,(line2Ctr>>8),Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_004C_MODOSD2,(line3Ctr & 0xffff),Fld(16,0,AC_FULLW10));
	W2BYTEMSK(REG_0050_MODOSD2,(line4Ctr & 0xff),Fld(8,8,AC_MSKB1));
	W2BYTEMSK(REG_0054_MODOSD2,(line4Ctr>>8),Fld(16,0,AC_FULLW10));

}

static void _mtk_dither_depth_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}
	if(priv->dither_info.dither_capability == 0)//input 10bit case
		switch(priv->dither_info.dither_depth) {
		case E_DITHER_DEPTH_6:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);//dither 4 bit (10to6 case)
			break;
		case E_DITHER_DEPTH_8:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);//dither 2 bit (10to8 case)
			break;
		case E_DITHER_DEPTH_10:
			//means by pass(10to10 case)
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			break;
		case E_DITHER_DEPTH_12:
		default:
			// To avoid dither pattern works in not support case, force bypass mode
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			debug("[%s] dither depth not support\n", __func__);
			break;
		}
	else if (priv->dither_info.dither_capability == 1) {//input 12bit case
		switch(priv->dither_info.dither_depth) {
		case E_DITHER_DEPTH_6:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);//dither 4 bit (12to6 case)
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		case E_DITHER_DEPTH_8:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);//dither 4 bit (12to8 case)
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		case E_DITHER_DEPTH_10:
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_DITH_BITS);//dither 2 bit (12to10 case)
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		case E_DITHER_DEPTH_12:
			//means by pass(12to12 case)
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			break;
		default:
			// To avoid dither pattern works in not support case, force bypass mode
			priv->dither_info.dither_pattern = E_DITHER_BYPASS;
			W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_12B);
			debug("[%s] dither depth not support\n", __func__);
			break;
		}

	}
	else
	{
		debug("[%s] dither capability not support\n", __func__);
	}

}

static void _mtk_dither_12bit_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_BOOST_EN);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_DITHER_BIT_1);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_LSB_ALIGNMENT_SEL);

	if((priv->dither_info.dither_depth == E_DITHER_DEPTH_12)||(priv->dither_info.dither_pattern ==E_DITHER_BYPASS))
	{
		W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_BYPASS_MODE);
	}
	else
	{
		W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_BYPASS_MODE);
	}

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_PAFRC_INPUT_IS_13B);

	W2BYTEMSK(REG_012C_PAFRC_BKA324, 0x0, REG_012C_PAFRC_BKA324_REG_13B_CLAMP_MODE);

}

static void _mtk_dither_common_setting(void)
{
	//setting here means different dither pattern use the same setting

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_POL_TYPE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_G_V_SWAP);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_G_H_SWAP);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_B_D_SWAP);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FR_SW);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX4X4_FR_SW);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX8X8_ROT_UNIT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_ROTATE_EN);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_TOP_BOX_UNIT_FLAG);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_SHRINK);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_FR_C2_BIT);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_C2X2_ROT_B_DIR_S);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_D2X2_ROT_B_DIR_S);

	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_A2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_B2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_R_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_R_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_R_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_A2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_B2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_G_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_G_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_G_DIR_S);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_A2X2_ROT_B_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x0, REG_0104_PAFRC_BKA324_REG_B2X2_ROT_B_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_C2X2_ROT_B_DIR);
	W2BYTEMSK(REG_0104_PAFRC_BKA324, 0x1, REG_0104_PAFRC_BKA324_REG_D2X2_ROT_B_DIR);

	W2BYTEMSK(REG_0108_PAFRC_BKA324, 0x9c, REG_0108_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ1);
	W2BYTEMSK(REG_0108_PAFRC_BKA324, 0xc9, REG_0108_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ2);

	W2BYTEMSK(REG_010C_PAFRC_BKA324, 0x9c, REG_010C_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ3);
	W2BYTEMSK(REG_010C_PAFRC_BKA324, 0xc9, REG_010C_PAFRC_BKA324_REG_TOP_BOX_FR_SEQ4);

	W2BYTEMSK(REG_0110_PAFRC_BKA324, 0xaa, REG_0110_PAFRC_BKA324_REG_TOP_BOX_FR_C2_SEQ12);
	W2BYTEMSK(REG_0110_PAFRC_BKA324, 0xaa, REG_0110_PAFRC_BKA324_REG_TOP_BOX_FR_C2_SEQ34);

	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_00);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x2, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_01);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_10);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x2, REG_0114_PAFRC_BKA324_REG_BOX8X8_ROT_11);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX_A_ROT_DIR);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x1, REG_0114_PAFRC_BKA324_REG_BOX_B_ROT_DIR);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x0, REG_0114_PAFRC_BKA324_REG_BOX_C_ROT_DIR);
	W2BYTEMSK(REG_0114_PAFRC_BKA324, 0x1, REG_0114_PAFRC_BKA324_REG_BOX_D_ROT_DIR);
}
static void _mtk_dither_entity_same_setting(void)
{
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_LD_10);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_LD_10);

	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_LD_10);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_LD_10);

	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_LD_10_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_LD_10_S);

	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_LD_10);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_LD_10);

	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_LD_10);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_LD_10);
}

static void _mtk_dither_bypass_setting(void)
{

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting();
	_mtk_dither_entity_same_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_FRC_ON);

}

static void _mtk_dither_truncate_setting(void)
{

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);//only diff with bypass

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting();
	_mtk_dither_entity_same_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_round_setting(void)
{

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting();
	_mtk_dither_entity_same_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);//only diff with truncate

}


static void _mtk_dither_entity_diff_setting(void)
{
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x3, REG_0118_PAFRC_BKA324_REG_A_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x1, REG_0118_PAFRC_BKA324_REG_A_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_A_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x0, REG_0118_PAFRC_BKA324_REG_A_LD_10);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x3, REG_0118_PAFRC_BKA324_REG_B_LU_00);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x1, REG_0118_PAFRC_BKA324_REG_B_RU_01);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x2, REG_0118_PAFRC_BKA324_REG_B_RD_11);
	W2BYTEMSK(REG_0118_PAFRC_BKA324, 0x0, REG_0118_PAFRC_BKA324_REG_B_LD_10);

	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x1, REG_011C_PAFRC_BKA324_REG_C_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x3, REG_011C_PAFRC_BKA324_REG_C_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x0, REG_011C_PAFRC_BKA324_REG_C_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_C_LD_10);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x1, REG_011C_PAFRC_BKA324_REG_D_LU_00);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x3, REG_011C_PAFRC_BKA324_REG_D_RU_01);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x0, REG_011C_PAFRC_BKA324_REG_D_RD_11);
	W2BYTEMSK(REG_011C_PAFRC_BKA324, 0x2, REG_011C_PAFRC_BKA324_REG_D_LD_10);

	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_C_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x0, REG_0120_PAFRC_BKA324_REG_C_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x3, REG_0120_PAFRC_BKA324_REG_C_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x1, REG_0120_PAFRC_BKA324_REG_C_LD_10_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x2, REG_0120_PAFRC_BKA324_REG_D_LU_00_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x0, REG_0120_PAFRC_BKA324_REG_D_RU_01_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x3, REG_0120_PAFRC_BKA324_REG_D_RD_11_S);
	W2BYTEMSK(REG_0120_PAFRC_BKA324, 0x1, REG_0120_PAFRC_BKA324_REG_D_LD_10_S);

	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x3, REG_0124_PAFRC_BKA324_REG_BOX_A_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x1, REG_0124_PAFRC_BKA324_REG_BOX_A_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_A_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x0, REG_0124_PAFRC_BKA324_REG_BOX_A_LD_10);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x0, REG_0124_PAFRC_BKA324_REG_BOX_B_LU_00);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x2, REG_0124_PAFRC_BKA324_REG_BOX_B_RU_01);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x1, REG_0124_PAFRC_BKA324_REG_BOX_B_RD_11);
	W2BYTEMSK(REG_0124_PAFRC_BKA324, 0x3, REG_0124_PAFRC_BKA324_REG_BOX_B_LD_10);

	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_C_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x0, REG_0128_PAFRC_BKA324_REG_BOX_C_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x3, REG_0128_PAFRC_BKA324_REG_BOX_C_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x1, REG_0128_PAFRC_BKA324_REG_BOX_C_LD_10);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x1, REG_0128_PAFRC_BKA324_REG_BOX_D_LU_00);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x3, REG_0128_PAFRC_BKA324_REG_BOX_D_RU_01);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x0, REG_0128_PAFRC_BKA324_REG_BOX_D_RD_11);
	W2BYTEMSK(REG_0128_PAFRC_BKA324, 0x2, REG_0128_PAFRC_BKA324_REG_BOX_D_LD_10);


}

static void _mtk_dither_random_static_setting(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting();
	_mtk_dither_entity_diff_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_random_dynamic_setting(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x0, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);//diff with random static

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);//diff with random static

	_mtk_dither_common_setting();

	_mtk_dither_entity_diff_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_pattern_table_static_setting(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);//diff with random
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x1, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);

	_mtk_dither_common_setting();
	_mtk_dither_entity_diff_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

static void _mtk_dither_pattern_table_dynamic_setting(void)
{
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_NOISE_DITH_DISABLE);//diff with random
	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_PAFRC_TAIL_CUT);

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_BOX_FREEZE);//diff with random static

	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_FREEZE);//diff with random static
	W2BYTEMSK(REG_0100_PAFRC_BKA324, 0x0, REG_0100_PAFRC_BKA324_REG_TOP_BOX_SHRINK);
	_mtk_dither_common_setting();
	_mtk_dither_entity_diff_setting();

	W2BYTEMSK(REG_00FC_PAFRC_BKA324, 0x1, REG_00FC_PAFRC_BKA324_REG_FRC_ON);


}

void mtk_dither_setting(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	_mtk_dither_depth_setting(dev);

	if(priv->dither_info.dither_capability == 1)
	{
		_mtk_dither_12bit_setting(dev);
	}

	switch (priv->dither_info.dither_pattern) {
		case E_DITHER_BYPASS:
    			_mtk_dither_bypass_setting();
    			break;
    		case E_DITHER_TRUNCATION:
    			_mtk_dither_truncate_setting();
    			break;
		case E_DITHER_ROUND:
    			_mtk_dither_round_setting();
    			break;
    		case E_DITHER_PATTERN_TABLE_DYNAMIC:
    			_mtk_dither_pattern_table_dynamic_setting();
			break;
    		case E_DITHER_PATTERN_TABLE_STATIC:
    			_mtk_dither_pattern_table_static_setting();
			break;
    		case E_DITHER_RANDOM_DYNAMIC:
    			_mtk_dither_random_dynamic_setting();
			break;
    		case E_DITHER_RANDOM_STATIC:
    			_mtk_dither_random_static_setting();
			break;
    		default:
			UBOOT_DEBUG("dither pattern fail\n");
			break;

    	}
}

/*----------------------------------MIXED MODE---------------------------------------*/

// Debug related
#define PNL_RGB_LUT_CHECK(R, G, B) ((R) == NULL || (G) == NULL || (B) == NULL)

#define BYTE_PER_WORD      (32)
#define OD_BYTE_PER_WORD   (32)

#define PCID_TABLE_SIZE_17X17           (289)
#define PCID_PIXEL_OD_POLARITY_LUT_SIZE (8)
#define PCID_SKIP_HEADER                (21)

#define PCID_RGB_CHANNEL                (3)
#define PCID_TABLE_COL_9                (9)
#define PCID_TABLE_COL_8                (8)
#define PCID_TABLE_ROW_9                (9)
#define PCID_TABLE_ROW_8                (8)

//PCID ADL
#define XC_AUTODOWNLOAD_PCID_19X19_OFFSET   (181) //10*10 + 9*9
#define XC_AUTODOWNLOAD_PCID_17X17_OFFSET   (145) //9*9 + 8*8

//LINE OD
#define LINE_OD_TABLE_SIZE_19X19        (361)
#define LINE_OD_TABLE_SIZE_17X17        (289)
#define LINE_OD_GAIN_TABLE_SIZE_4X4        (16)
#define LINE_OD_GAIN_TABLE_SIZE_13X9        (117)
#define LINE_OD_REG_NUM_1X1           (1)
#define LINE_OD_REG_NUM_4X4           (16)
#define LINE_OD_REG_NUM_2X8           (16)
#define LINE_OD_REG_NUM_10X1          (10)
#define LINE_OD_TABLE_COL_10            (10)
#define LINE_OD_TABLE_COL_9             (9)
#define LINE_OD_TABLE_ROW_10            (10)
#define LINE_OD_TABLE_ROW_9             (9)
#define LINE_OD_GAIN_TABLE_ROW_4           (4)
#define LINE_OD_GAIN_TABLE_COL_4           (4)
#define LINE_OD_GAIN_TABLE_COL_13           (13)
#define LINE_OD_GAIN_TABLE_ROW_9           (9)
#define LINE_OD_TABLE_UNIT_SIZE_8           (0)
#define LINE_OD_TABLE_UNIT_SIZE_12           (1)
#define LINE_OD_HW_GAIN_SIZE_13X9        (117)
#define LINE_OD_HW_GAIN_COL_13           (13)
#define LINE_OD_HW_GAIN_ROW_9           (9)

#define TRIG_WRITE_SRAM                 (0x2000)
#define SELECT_ALL_CHANNEL_RGB          (0x000C)
#define SELECT_SRAM1                    (0x0000)
#define SELECT_SRAM2                    (0x0100)
#define SELECT_SRAM3                    (0x0200)
#define SELECT_SRAM4                    (0x0300)
#define W_RGB_MASK                      (0x230C)
#define PNL_LINEOD_SHARE_SRAM        (TRUE)

//EVA Table
#define EVA_MAX_VALUE_OFFSET  (0x20+0x4)
#define EVA_MAX_VALUE_CNANNEL  (6)
#define EVA_MAINHEADER_OFFSET  (0x20+0x18)
#define EVA_DATA_START         (0x42)
#define EVA_TABLE_MATRIX_SIZE_17X2    (17)
#define EVA_TABLE_MATRIX_SIZE_257X2   (257)
#define EVA_LUT_SIZE_16    (16)
#define EVA_LUT_SIZE_256   (256)
#define EVA_TABLE_RGB_CNANNEL  (3)
#define EVA_TABLE_UNIT_SIZE_8  (0)
#define EVA_TABLE_UNIT_SIZE_12 (1)

//Polarity mode
//0: 1 pixel
//     reg_eva_polarity_lut0 = 0xE38
//     reg_eva_polarity_lut1 = 0x1C7
//     reg_eva_polarity_lut2 = 0xE38
//     reg_eva_polarity_lut3 = 0x1C7
//1: 1 subpixel
//     reg_eva_polarity_lut0 = 0xAAA
//     reg_eva_polarity_lut1 = 0x555
//     reg_eva_polarity_lut2 = 0xAAA
//     reg_eva_polarity_lut3 = 0x555
//2: 2 pixel (RBG)
//     reg_eva_polarity_lut0 = 0xCCC
//     reg_eva_polarity_lut1 = 0x333
//     reg_eva_polarity_lut2 = 0xCCC
//     reg_eva_polarity_lut3 = 0x333
//3: 2 subpixel (BGR) = 2 pixel (RBG) + RBswap enable
//     reg_eva_polarity_lut0 = 0x7A1
//     reg_eva_polarity_lut1 = 0x85E
//     reg_eva_polarity_lut2 = 0x7A1
//     reg_eva_polarity_lut3 = 0x85E
#define EVA_POLARITY_LUT0_MODE_0 (0xE38)
#define EVA_POLARITY_LUT0_MODE_1 (0xAAA)
#define EVA_POLARITY_LUT0_MODE_2 (0xCCC)
#define EVA_POLARITY_LUT0_MODE_3 (0x7A1)

//VAC ADL
#define XC_AUTODOWNLOAD_VAC_CHANNEL_OFFSET   (0x200) //16 entry * 32 byte
#define XC_AUTODOWNLOAD_VAC_MEM_SIZE         (0xC00) // (48+48)*32 bytes

#define TCON_REGISTERTYPE_1_BYTES   1
#define TCON_REGISTERTYPE_6_BYTES   6
#define TCON_REGISTERTYPE_4_BYTES   4
#define TCON_REGISTERTYPE_POWERSEQENCE_9_BYTES   9
#define TCON_REGISTERTYPE_POWERSEQENCE_7_BYTES   7
#define TCON_REGISTERTYPE_POWERSEQENCE_WITHSUB_15_BYTES   15
#define TCON_REGISTERTYPE_POWERSEQENCE_WITHSUB_11_BYTES   11
#define TCON_REGISTERTYPE_POWERSEQENCE_WITHSUB_14_BYTES   14

// OD
#define MAX_OVERDRIVER_TABLE 1089
#define OVERDRIVER_TABLE_SIZE_33X32    1056
#define OVERDRIVER_TABLE_SIZE_33X33    1089
//old od table
#define OVERDRIVER_TABLE_SIZE_33X32    1056
//new od table
#define OVERDRIVER_TABLE_SIZE_33X33    1089
#define MAX_OVERDRIVER_TABLE 1089
#define OVERDRIVER_SRAM1_SIZE (289)
#define OVERDRIVER_SRAM2_SIZE (272)
#define OVERDRIVER_SRAM3_SIZE (272)
#define OVERDRIVER_SRAM4_SIZE (256)
#define OD_DECRYPTION_IDX_1 (9)
#define OD_DECRYPTION_IDX_2 (10)
#define XC_AUTODOWNLOAD_OVERDRIVER_DEPTH  (289)

//Define OVERDRIVE
#define OVERDRIVE_WEIGHT                       (0x40)
#define OVERDRIVE_ACTIVE_THRESHOLD             (0x08)
#define OVERDRIVE_RGB_CHANNEL                  (3)
#define OVERDRIVE_RGBW_CHANNEL                 (4)
#define OVERDRIVE_MIU_BUS                      (256)
#define OVERDRIVE_PG_LENGTH                    (64)
#define OVERDRIVE_PG_ENTRY_PRE_REQ             (128)
#define OVERDRIVE_ENABLE_HSCALING              (TRUE)
#define OVERDRIVE_ENABLE_HSD_4X                (FALSE)
#define OVERDRIVE_ENABLE_VSCALING              (TRUE)
#define OVERDRIVE_ENABLE_VAC_HSCALING          (TRUE)
#define OVERDRIVE_ENABLE_RGBW                  (FALSE) //If HW supprt OD RGBW
#define OVERDRIVE_RGB_444_MODE                 (12) //pix-bit
#define OVERDRIVE_RGB_565_MODE                 (16) //pix-bit
#define OVERDRIVE_RGB_666_MODE                 (18) //pix-bit
#define OVERDRIVE_COMPRESS_MODE                (12) //pix-bit
#define OVERDRIVE_RGB_555_MODE                 (15) //pix-bit
#define OVERDRIVE_RGB_888_MODE                 (24) //pix-bit
#define OVERDRIVE_MODE                         (OVERDRIVE_COMPRESS_MODE)
#define OVERDRIVE_PIXEL                        (8)
#define OVERDRIVE_PANEL_EPI                    (5)
#define OVERDRIVE_PANEL_CEDS                   (8)
#define OVERDRIVE_EXTRA_MEM_SIZE_FACTOR                    (14)//extra DRAM size to prevent page table over run
#define OVERDRIVE_ODW_6_BITMODE              (6)
#define OVERDRIVE_ODW_8_BITMODE              (8)
#define OVERDRIVE_ODW_10_BITMODE             (10)
#define OVERDRIVE_ODW_BITMODE            (OVERDRIVE_ODW_6_BITMODE)
//Define OVERDRIVE CUSTOMIZED default value: it should reference register table
#define OVERDRIVE_WEIGHT_DEFAULT               (0x40)
#define OVERDRIVE_ACTIVE_THRESHOLD_DEFAULT     (0x04)
#define OVERDRIVE_STRENGTH_SLOP_DEFAULT        (0x2E)

//panel gamma
#define ST_PNL_PNLGAMMATBL_VERSION                       (1)

#define SUPPORT_PANEL_GAMMA_W_CHANNEL  (FALSE)
#if SUPPORT_PANEL_GAMMA_W_CHANNEL
#define PANEL_GAMMA_1LUT_MAX_CHANNEL           (3) //RGBW
#else
#define PANEL_GAMMA_1LUT_MAX_CHANNEL           (4) //RGBW
#endif
#define PANEL_GAMMA_2LUT_MAX_CHANNEL           (6) //RGBRGB

// Deafine Panel gamma ADL entry size
#define PNLGAMMA_ADL_CMD_LENGTH     (32) //byte
#define PNLGAMMA_ADL_CMD_ENTRY      (512)
#define PNLGAMMA_ADL_CMD_192_ENTRY  (192) //RGB
#define PNLGAMMA_ADL_CMD_256_ENTRY  (256) //RGBW
#define PNLGAMMA_ADL_CMD_384_ENTRY  (384) //RGBRGB

#define PANEL_GAMMA_MAINHEADER_LEN  (32)
#define PANEL_GAMMA_CHANNEL_OFFSET  (64*32)    //Each channel of R/G/B/W has 64 entry separately, each entry contains 32bytes command
#define PANEL_GAMMA_TBL_OFFSET      (0x2000)   //Each table contains R/G/B/W 4 channels, accouts for 64*32*4 = 0x2000 bytes
#define PANEL_GAMMA_ENTRY           (1024)     //Panel gamma curve has 1024 entries


typedef enum
{
    E_PNL_OVERDRIVER_SEPARATE_R_ENABLE = 0x08,
    E_PNL_OVERDRIVER_SEPARATE_G_ENABLE = 0x04,
    E_PNL_OVERDRIVER_SEPARATE_B_ENABLE = 0x02,
    E_PNL_OVERDRIVER_SEPARATE_W_ENABLE = 0x01,
} EN_PNL_OVERDRIVER_SEPARATE;

typedef enum
{
    E_HAL_PCID_LUT0 = 0,
    E_HAL_PCID_LUT1 = 1,
} PNL_HAL_PCID_LUT_TYPE;

typedef enum
{
    E_PNL_TCON_PANELINFO_PANELLINKTYPE = 0,
    E_PNL_TCON_PANELINFO_PANELLINKEXTTYPE,
    E_PNL_TCON_PANELINFO_FIXEDVABCKPORCH,
    E_PNL_TCON_PANELINFO_FIXEDHBACKPORCH,

    E_PNL_TCON_PANELINFO_VSYNC_START = 11,
    E_PNL_TCON_PANELINFO_VSYNC_END,
    E_PNL_TCON_PANELINFO_VDESTART,
    E_PNL_TCON_PANELINFO_VDEND,
    E_PNL_TCON_PANELINFO_PANELMAXVTOTAL,
    E_PNL_TCON_PANELINFO_PANELVTOTAL,
    E_PNL_TCON_PANELINFO_MINVTOTAL,
    E_PNL_TCON_PANELINFO_VDEHEADDUMMY,
    E_PNL_TCON_PANELINFO_VDETAILDUMMY,

    E_PNL_TCON_PANELINFO_HSYNC_START = 31,
    E_PNL_TCON_PANELINFO_HSYNC_END,
    E_PNL_TCON_PANELINFO_HDESTART,
    E_PNL_TCON_PANELINFO_HDEEND,
    E_PNL_TCON_PANELINFO_PANELMAXHTOTAL,
    E_PNL_TCON_PANELINFO_PANELHTOTAL,
    E_PNL_TCON_PANELINFO_PANELMINHTOTAL,
    E_PNL_TCON_PANELINFO_HDEHEADDUMMY,
    E_PNL_TCON_PANELINFO_HDETAILDUMMY,

    E_PNL_TCON_PANELINFO_PANELMAXDCLK = 51,
    E_PNL_TCON_PANELINFO_PANELDCLK,
    E_PNL_TCON_PANELINFO_PANELMINDCLK,
    E_PNL_TCON_PANELINFO_PANELMAXSET,
    E_PNL_TCON_PANELINFO_MINSET,
    E_PNL_TCON_PANELINFO_OUTTIMINGMODE,
    E_PNL_TCON_PANELINFO_TOTALPAIR,
    E_PNL_TCON_PANELINFO_PAIREVEN,
    E_PNL_TCON_PANELINFO_PAIRODD,
    E_PNL_TCON_PANELINFO_DUALPORT,

    E_PNL_TCON_PANELINFO_PANELHSYNCWIDTH = 71,
    E_PNL_TCON_PANELINFO_PANELHSYNCBACKPORCH,
    E_PNL_TCON_PANELINFO_PANELVSYNCWIDTH,
    E_PNL_TCON_PANELINFO_PANELVBACKPORCH,

    E_PNL_TCON_PANELINFO_SSC_ENABLE = 80,
    E_PNL_TCON_PANELINFO_SSC_FMODULATION,
    E_PNL_TCON_PANELINFO_SSC_PERCENTAGE,
    E_PNL_TCON_PANELINFO_SSC_BIN_CTRL,
    E_PNL_TCON_PANELINFO_DEMURA_SEL,
    E_PNL_TCON_PANELINFO_DATA_PATH_SEL,
    E_PNL_TCON_PANELINFO_VCOM_SEL,

    E_PNL_TCON_PANELINFO_DEMURA_ENABLE = 91,
} E_PNL_TCON_PANELINFO;

// TCon register type
typedef enum
{
    EN_TCON20_REGISTERTYPE_6_BYTES = 0,       // 32-bit address, 4+1+1, address+mask+value
    EN_TCON20_REGISTERTYPE_4_BYTES,       // 16-bit address, 2+1+1, address+mask+value
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_9_BYTES,      // 32-bit address, 4+1+1+1+1+1, address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_7_BYTES,      // 16-bit address, 2+1+1+1+1+1, address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_WITHSUB_15_BYTES, // 32-bit address, 4+1+1+4+1+1+1+1+1, subAddress+subMask+subValue+address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERSEQENCE_WITHSUB_11_BYTES, // 16-bit address, 2+1+1+2+1+1+1+1+1, subAddress+subMask+subValue+address+mask+value+delayReady+delayTime+signalType
    EN_TCON20_REGISTERTYPE_POWERGAMMA_4_BYTES, // Register type 6: P-Gamma (Power Gamma) 4-byte register format (16-bit address size and 16-bit value size)
    EN_TCON20_REGISTERTYPE_3_BYTES, // Register type 7: TCON 3-byte register format (12-bit address size)
    EN_TCON20_REGISTERTYPE_PANEL_1_BYTES, // Register type 8: 1-byte only data.
    EN_TCON20_REGISTERTYPE_PANEL_6_BYTES, //Register tyep 9: 2+4, panelinfo ID+value
    EN_TCON20_REGISTERTYPE_POWERSEQUENCE_14BYTES, // Register type A : 3+1+1+3+2+2+1+1 subbankaddress + mask+subbank+adress+mask+value+delaytime+prioriry
    EN_TCON20_REGISTERTYPE_PANEL_6_BYTES_NEWSSC, //Register tyep 9: 2+4, panelinfo ID+value, for new SSC calculation
    EN_TCON_REGISTERTYPE_END,
} E_PNL_TCON20_REGISTERTYPE;


/// Define the panel gamma precision type
typedef enum
{
    E_APIPNL_GAMMA_10BIT = 0,              ///< Gamma Type of 10bit
    E_APIPNL_GAMMA_12BIT,                  ///< Gamma Type of 12bit
    E_APIPNL_GAMMA_ALL                     ///< The library can support all mapping mode
} APIPNL_GAMMA_TYPE;

/// Define the panel gamma bin entry
typedef enum
{
    E_PNL_PNLGAMMA_256_ENTRIES = 0,              ///< Indicate PNL Gamma is 256 entrise
    E_PNL_PNLGAMMA_1024_ENTRIES,                 ///< Indicate PNL Gamma is 1024 entries
    E_PNL_PNLGAMMA_MAX_ENTRIES                   ///< Indicate PNL Gamma is MAX entries
} EN_PNL_PNLGAMMA_ENTRIES;

/// Define Gamma type
typedef enum
{
    E_APIPNL_GAMMA_8BIT_MAPPING = 0,      ///< mapping 1024 to 256 gamma entries
    E_APIPNL_GAMMA_10BIT_MAPPING,         ///< mapping 1024 to 1024 gamma entries
    E_APIPNL_GAMMA_ALL_MAPPING            ///< the library can map to any entries
} APIPNL_GAMMA_MAPPEING_MODE;             ///< samping mode for GAMMA correction

typedef struct __attribute__((packed))
{
    u32 u32SRAM_B1 : 8; //[7:0]
    u32 u32SRAM_B2 : 8; //[15:8]
    u32 u32SRAM_B3 : 8; //[23:16]
    u32 u32SRAM_B4 : 8; //[31:24]
    //u32 u32SRAM_B : 32;
    u32 u32SRAM_G1 : 8; //[7:0]
    u32 u32SRAM_G2 : 8; //[15:8]
    u32 u32SRAM_G3 : 8; //[23:16]
    u32 u32SRAM_G4 : 8; //[31:24]
    //u32 u32SRAM_G : 32;
    u32 u32SRAM_R1 : 8; //[7:0]
    u32 u32SRAM_R2 : 8; //[15:8]
    u32 u32SRAM_R3 : 8; //[23:16]
    u32 u32SRAM_R4 : 8; //[31:24]
    //u32 u32SRAM_R : 32;
    u32 u32OD_B_WriteEn : 1;
    u32 u32OD_G_WriteEn : 1;
    u32 u32OD_R_WriteEn : 1;
    u32 u32SecondOD_B_WriteEn : 1;
    u32 u32SecondOD_G_WriteEn : 1;
    u32 u32SecondOD_R_WriteEn : 1;
    u32 u32Dummy0 : 2;
    u32 u32Table_WriteAddr : 9;
    u32 u32Dummy1 : 15;
    u32 u32SRAM_W1 : 8; //[7:0]
    u32 u32SRAM_W2 : 8; //[15:8]
    u32 u32SRAM_W3 : 8; //[23:16]
    u32 u32SRAM_W4 : 8; //[31:24]
    //u32 u32SRAM_W : 32;
    u32 u32OD_W_WriteEn : 1;
    u32 u32SecondOD_W_WriteEn : 1;
    u32 u32Dummy2 : 30; //[191:162]
    u32 u32Dummy3 : 32; //[223:192]
    u32 u32Dummy4 : 32; //[255:224]
}ST_PNL_OD_NEW_MODE_DRAM_FORMAT;

typedef struct __attribute__((packed))
{
    u8 u8GammaType;
    u8 u8Table2DNumber;
    u8 u8Table3DNumber;
    u8 u8TableFormat;
    u16 u16PreTableOrignalSize;
    u16 u16PreTableAlignedSize;
    u32 u32Table2DStartAddress;
    u32 u32Table3DStartAddress;
    u8 u8BINVersion_Minor2;
    u8 u8BINVersion_Minor1;
    u8 u8BINVersion_Major;
    u8 u8PanelSize;
    u16 u16Minute : 11;
    u8 u8Day : 5;
    u8 u8Month : 4;
    u8 u8Year : 5;
    u8 u8Reserved0 : 7;
    bool bGamma2LutEnable : 1;
    u8 u8Gamma2LutMode : 2;
    u32 u32Reserved1 : 29;
    u32 u32Reserved2;
}MS_PNL_PNLGAMMA_Config;

typedef enum
{
    E_PNL_PNLGAMMA_TBL_FROM_BIN,
    E_PNL_PNLGAMMA_TBL_FROM_REG,
    E_PNL_PNLGAMMA_TBL_MAX,
}EN_PNL_PNLGAMMA_TBL;

typedef struct  __attribute__((packed))
{
	u32 u32Version;				   /// Struct version
	u32 u32Length;				   /// Sturct length
	EN_PNL_PNLGAMMA_TBL  enPnlGammaTbl; /// IN: select Get gamma value from
	u8*	pu8GammaTbl;				/// IN: Bin file address
#if !defined (__aarch64__)
	void *pDummy0;					   /// Dummy parameter
#endif
	u32	u32TblSize; 			   /// IN: PNL Gamma bin size
	u16* pu16RChannel0;			   /// IN/OUT: R channel 0 data
#if !defined (__aarch64__)
	void *pDummy1;					   /// Dummy parameter
#endif
	u16* pu16GChannel0;			   /// IN/OUT: G channel 0 data
#if !defined (__aarch64__)
	void *pDumm2;					  /// Dummy parameter
#endif
	u16* pu16BChannel0;			   /// IN/OUT: B channel 0 data
#if !defined (__aarch64__)
	void *pDummy3;					   /// Dummy parameter
#endif
	u16* pu16WChannel0;			   /// IN/OUT: W channel 0 data
#if !defined (__aarch64__)
	void *pDummy4;					   /// Dummy parameter
#endif
	u16* pu16RChannel1;			   /// IN/OUT: R channel 1 data
#if !defined (__aarch64__)
	void *pDummy5;					   /// Dummy parameter
#endif
	u16* pu16GChannel1;			   /// IN/OUT: G channel 1 data
#if !defined (__aarch64__)
	void *pDummy6;					   /// Dummy parameter
#endif
	u16* pu16BChannel1;			   /// IN/OUT: B channel 1 data
#if !defined (__aarch64__)
	void *pDummy7;					   /// Dummy parameter
#endif
	u16* pu16WChannel1;			   /// IN/OUT: W channel 1 data
#if !defined (__aarch64__)
	void *pDummy8;					   /// Dummy parameter
#endif
	u16 u16Index;				   /// IN: the index of the data want to get
	u16 u16Size; 				   /// IN: every channel data number
	bool bSupportChannel1;		   /// OUT: Support PNL gamma Channel 1
	EN_PNL_PNLGAMMA_ENTRIES enGammaEntries;// OUT: PNL gamma bin entries
	APIPNL_GAMMA_TYPE enGammaType;	   // OUT: PNL gamma bin type
	u16 u162DTableNum;			   // OUT: PNL gamma bin 2D table number
	u16 u163DTableNum;			   // OUT: PNL gamma bin 3D table number
}ST_PNL_PNLGAMMATBL;


typedef struct __attribute__((packed))
{
    u16 u16Version;               //[15:8]: major, [7:0]: minor version
    u8 u8LineOD_en;               //[0]: line od enable
    u8 u8SeparateFlag;            //[0]: channel separate flag [1]: table separate flag (unused)
    u32 u32YearMonthDayMinute;    //[31:25]: reserved, [24:20]: year, [19:16]: month, [15:11]: day, [10:0]: minute
    u8 u8TableMatrix;             //0: 19x19, 1: 17x17
    u8 u8RegionNumber;            //(Version>1 0: 1x1, 1: 2x8, 2:4X4) (Version<=1 16: 4x4 or 2x8, 1: 1x1)
    u8 u8GainMatrix;            //0: 4x4, 1: 13x9
    u8 u8GainRegion;            //0: 1x1
    u8 u8TableBit;                //(Version>2 0: 8bit 1:12bit) (Version<=2 no this member)
} ST_PNL_LINE_OD_SUB_HEADER, *pST_PNL_LINE_OD_SUB_HEADER;

typedef struct __attribute__((packed))
{
    //u16 u16Version;               //[15:8]: major, [7:0]: minor version
   // u8 u8Eva_en;                  //[0]: eva enable
    u8 u8SeparateFlag;            //[0]: channel separate flag [1]: table separate flag (unused)
    //u32 u32YearMonthDayMinute;    //[31:25]: reserved, [24:20]: year, [19:16]: month, [15:11]: day, [10:0]: minute
    u8 u8TableMatrix;             //0: 17x2, 1: 257x2
    u8 u8TableBit;                //0: 8bit 1:12bit
    //u8 u8Reserved1;
    //u8 u8Reserved2;
    //u8 u8Reserved3;
} ST_PNL_EVA_SUB_HEADER, *pST_PNL_EVA_SUB_HEADER;

typedef struct DLL_PACKED
{
    u16  u16TblSize;                /// IN: size
    u16* pu16RChannel0;               /// IN/OUT: R channel 0 data
#if !defined (__aarch64__)
    void *pDummy0;                     /// Dummy parameter
#endif
    u16* pu16GChannel0;               /// IN/OUT: G channel 0 data
#if !defined (__aarch64__)
    void *pDummy1;                     /// Dummy parameter
#endif
    u16* pu16BChannel0;               /// IN/OUT:: B channel 0 data
#if !defined (__aarch64__)
    void *pDummy2;                     /// Dummy parameter
#endif
    u16* pu16RChannel1;               /// IN/OUT:: R channel 1 data
#if !defined (__aarch64__)
    void *pDummy3;                     /// Dummy parameter
#endif
    u16* pu16GChannel1;               /// IN/OUT:: G channel 1 data
#if !defined (__aarch64__)
    void *pDummy4;                     /// Dummy parameter
#endif
    u16* pu16BChannel1;               /// IN/OUT:: B channel 1 data
#if !defined (__aarch64__)
    void *pDummy5;                     /// Dummy parameter
#endif
    u16* pu16RChannel0_17;             /// IN: R channel 0 data
#if !defined (__aarch64__)
    void *pDummy6;                     /// Dummy parameter
#endif
    u16* pu16GChannel0_17;             /// IN: G channel 0 data
#if !defined (__aarch64__)
    void *pDummy7;                     /// Dummy parameter
#endif
    u16* pu16BChannel0_17;             /// IN: B channel 0 data
#if !defined (__aarch64__)
    void *pDummy8;                     /// Dummy parameter
#endif
    u16* pu16RChannel1_17;             /// IN: R channel 1 data
#if !defined (__aarch64__)
    void *pDummy9;                     /// Dummy parameter
#endif
    u16* pu16GChannel1_17;             /// IN: G channel 1 data
#if !defined (__aarch64__)
    void *pDummy10;                     /// Dummy parameter
#endif
    u16* pu16BChannel1_17;             /// IN: B channel 1 data
#if !defined (__aarch64__)
    void *pDummy11;                     /// Dummy parameter
#endif
}ST_PNL_EVA_TBL;

typedef struct __attribute__((packed))
{
    u16 u16SRAM1_lut0 : 12; //[11:0]
    u16 u16SRAM1_lut1 : 12; //[23:12]
    u16 u16SRAM1_lut2 : 12; //[35:24]
    u16 u16SRAM1_lut3 : 12; //[47:36]
    u16 u16SRAM1_lut4 : 12; //[59:48]
    u16 u16SRAM1_lut5 : 12; //[71:60]
    u16 u16SRAM1_lut6 : 12; //[83:72]
    u16 u16SRAM1_lut7 : 12; //[95:84]
    u16 u16SRAM1_lut8 : 12; //[107:96]
    u16 u16SRAM1_lut9 : 12; //[119:108]
    u16 u16Dummy0 : 8;      //[127:120]
    u16 u16SRAM2_lut0 : 12; //[139:128]
    u16 u16SRAM2_lut1 : 12; //[151:140]
    u16 u16SRAM2_lut2 : 12; //[163:152]
    u16 u16SRAM2_lut3 : 12; //[175:164]
    u16 u16SRAM2_lut4 : 12; //[187:176]
    u16 u16SRAM2_lut5 : 12; //[199:88]
    u16 u16SRAM2_lut6 : 12; //[211:200]
    u16 u16SRAM2_lut7 : 12; //[223:212]
    u16 u16SRAM2_lut8 : 12; //[235:224]
    u16 u16SRAM2_lut9 : 12; //[247:236]
    u16 u16Dummy1 : 8;      //[255:248]
}ST_PNL_PCID_12BIT_DRAM_FORMAT;

#define CHECK_PTR_NULL(x) { if((x) == NULL){return FALSE;}}

ST_PNL_OD_NEW_MODE_DRAM_FORMAT* g_pstOD_ADL_CMD = NULL;
void (* set_adl_pcid_table[10])(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet);

#define TCON_PATH_REG_COUNT 13
#define TCON_CLK_BK1038_V004 0x207000 //bk1038
#define SCDISP_BKA4FA_V004 0x149F400

typedef enum
{
	E_PNL_TCON_PATH_MODE_0,//control by TCON bin
	E_PNL_TCON_PATH_MODE_1,//MTK Mode 4k2k@60
	E_PNL_TCON_PATH_MODE_2,//Game Mode for 4k1k@144
	E_PNL_TCON_PATH_MODE_3,
	E_PNL_TCON_PATH_MODE_4,
	E_PNL_TCON_PATH_MODE_5,
	E_PNL_TCON_PATH_MODE_6,
	E_PNL_TCON_PATH_MODE_7,//SiW Mode 4k2k@60
	E_PNL_TCON_PATH_MODE_8,//Specific OLED Mode 4k2k@60
	E_PNL_TCON_PATH_MODE_9,//Specific Mode 4k2k@120
	E_PNL_TCON_PATH_MODE_10,//Specific Mode 4k2k@120
	E_PNL_TCON_PATH_MODE_11,//SiW Mode 4k2k@120
	E_PNL_TCON_PATH_MODE_12,//Specific OLED Mode 4k2k@120
	E_PNL_TCON_PATH_MODE_MAX,
} E_PNL_TCON_PATH_MODE;

typedef enum {
    E_BOOT_TEST_PATTERN_NONE,
    E_BOOT_TEST_PATTERN_TCON,
    E_BOOT_TEST_PATTERN_PAFRC_POST,
    E_BOOT_TEST_PATTERN_MOD_H_HALF,
    E_BOOT_TEST_PATTERN_MOD_H_HALF_INV,
    E_BOOT_TEST_PATTERN_MOD_V_HALF,
    E_BOOT_TEST_PATTERN_MOD_V_HALF_INV,
    E_BOOT_TEST_PATTERN_MOD_FULL,
	E_BOOT_TEST_PATTERN_TOCN_GRAY,
	E_BOOT_TEST_PATTERN_TOCN_R,
	E_BOOT_TEST_PATTERN_TOCN_G,
	E_BOOT_TEST_PATTERN_TOCN_B,
	E_BOOT_TEST_PATTERN_MAX,
}en_boot_test_pattern_config;

u32 stTconPathReg[TCON_PATH_REG_COUNT]={
    SCDISP_BKA4FA_V004+0x0100,
    REG_0180_SCTCON_BKA4F7_V004,
    REG_0180_SCTCON_BKA4F7_V004,
    REG_0140_DEMURA_BKA377_V004,
    REG_012C_PAFRC_BKA324_V004,
    REG_003C_PAFRC_BKA324_V004,
    REG_003C_PAFRC_BKA324_V004,
    TCON_CLK_BK1038_V004+0x014c,
    TCON_CLK_BK1038_V004+0x0148,
    TCON_CLK_BK1038_V004+0x0144,
    TCON_CLK_BK1038_V004+0x0158,
    TCON_CLK_BK1038_V004+0x0154,
    TCON_CLK_BK1038_V004+0x0150,
};
u32 stTconPathMask[TCON_PATH_REG_COUNT]={
    Fld(3,0,AC_MSKB0),//bit[3:0]
    REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180,//bit[14:12]
    REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180,//bit[0]
    REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140,//bit[3]
    REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C,//bit[6]
    Fld(2,8,AC_MSKB1),//bit[9:8]
    REG_003C_PAFRC_BKA324_V004_REG_VAC_BF_PANEL_GAMMA_EN_003C,//bit[3]
    Fld(3,3,AC_MSKB0),//bit[5:3]
    Fld(3,3,AC_MSKB0),
    Fld(3,3,AC_MSKB0),
    Fld(3,3,AC_MSKB0),
    Fld(3,3,AC_MSKB0),
    Fld(3,3,AC_MSKB0)
};

u32 stTconPathVal[TCON_PATH_REG_COUNT][E_PNL_TCON_PATH_MODE_MAX-1]={
    //mode1 mode2   mode3   mode4   mode5   mode6
    {0x0,   0x0,   0x0,   0x3,   0x0,   0x0,},
    {0x0,   0x0,   0x0,   0x0,   0x1,   0x1,},
    {0x0,   0x0,   0x0,   0x0,   0x0,   0x0,},
    {0x1,   0x1,   0x0,   0x1,   0x1,   0x1,},
    {0x1,   0x1,   0x0,   0x1,   0x1,   0x1,},
    {0x0,   0x2,   0x0,   0x2,   0x1,   0x0,},
    {0x0,   0x0,   0x0,   0x0,   0x0,   0x1,},
    {0x0,   0x0,   0x0,   0x0,   0x0,   0x0,},
    {0x1,   0x0,   0x1,   0x1,   0x1,   0x1,},
    {0x1,   0x1,   0x1,   0x1,   0x1,   0x1,},
    {0x1,   0x0,   0x1,   0x1,   0x1,   0x1,},
    {0x1,   0x0,   0x1,   0x1,   0x1,   0x1,},
    {0x1,   0x0,   0x1,   0x1,   0x1,   0x1,},
};

static loff_t tcon_size;
static loff_t eva_size;
static u8 *file_buf;
static u8 *eva_buf;

static u8 *panel_gamma_buf;
static loff_t panel_gamma_size;

#define BIN_FILE_PATH_LENGTH              128

#define TCON_DEFAUL_PATH_MI               "tcon/TCON20.bin"
#define TCON_DEFAUL_PATH_LINUX            "config/tcon/TCON20.bin"
#define TCON_DEFAUL_PATH_AOSP             "bsp/common/TCON_BIN/TCON20.bin"

#define EVA_DEFAUL_PATH_MI                "tcon/EVA.bin"
#define EVA_DEFAUL_PATH_LINUX             "config/tcon/EVA.bin"
#define EVA_DEFAUL_PATH_AOSP              "bsp/common/TCON_BIN/EVA.bin"

#define PANELGAMMA_DEFAULT_PATH_MI        "gamma/panel_gamma.bin"
#define PANELGAMMA_DEFAULT_PATH_LINUX     "config/gamma/panel_gamma.bin"
#define PANELGAMMA_DEFAULT_PATH_AOSP      "bsp/common/GAMMA_BIN/panel_gamma.bin"
#define AUTO_PANEL_GAMMA_DATA_SIZE        (1024 * 2 * 3)  //1024 Entry, 2 Byte, RGB
#define PANEL_GAMMA_PRE_CHANNEL_LEN       (1024 * 2)
#define CSPI_GAMMA_SIZE_120HZ             (16)
#define USIT_GAMMA_SIZE_120HZ             (14)

static u16 _registerTypeToSize(u8 u8Registertype)
{
    E_PNL_TCON20_REGISTERTYPE en = (E_PNL_TCON20_REGISTERTYPE)u8Registertype;
    switch (en)
    {
        case EN_TCON20_REGISTERTYPE_6_BYTES:
            return TCON_REGISTERTYPE_6_BYTES;
        case EN_TCON20_REGISTERTYPE_4_BYTES:
            return TCON_REGISTERTYPE_4_BYTES;
        case EN_TCON20_REGISTERTYPE_POWERSEQENCE_9_BYTES:
            return TCON_REGISTERTYPE_POWERSEQENCE_9_BYTES;
        case EN_TCON20_REGISTERTYPE_POWERSEQENCE_7_BYTES:
            return TCON_REGISTERTYPE_POWERSEQENCE_7_BYTES;
        case EN_TCON20_REGISTERTYPE_POWERSEQENCE_WITHSUB_15_BYTES:
            return TCON_REGISTERTYPE_POWERSEQENCE_WITHSUB_15_BYTES;
        case EN_TCON20_REGISTERTYPE_POWERSEQENCE_WITHSUB_11_BYTES:
            return TCON_REGISTERTYPE_POWERSEQENCE_WITHSUB_11_BYTES;
        case EN_TCON20_REGISTERTYPE_PANEL_1_BYTES:
            return TCON_REGISTERTYPE_1_BYTES;
        case EN_TCON20_REGISTERTYPE_PANEL_6_BYTES:
        case EN_TCON20_REGISTERTYPE_PANEL_6_BYTES_NEWSSC:
            return TCON_REGISTERTYPE_6_BYTES;
        case EN_TCON20_REGISTERTYPE_POWERSEQUENCE_14BYTES:
            return TCON_REGISTERTYPE_POWERSEQENCE_WITHSUB_14_BYTES;
        default:
            debug("register type out of range: %d", en);
            return 0;
    }
}

//Panel Gamma
///halPNL.c
static void MHal_PNL_SetPanelGammaByPass(bool bEnable)
{
    W2BYTEMSK(REG_01B0_PAFRC_BKA324_V004,bEnable?0x1:0x0,REG_01B0_PAFRC_BKA324_V004_REG_GAMMA_BYPASS_01B0);
}
static bool MHal_PNL_GetPanelGammaByPass(void)
{
    return R2BYTEMSK(REG_01B0_PAFRC_BKA324_V004,REG_01B0_PAFRC_BKA324_V004_REG_GAMMA_BYPASS_01B0);
}

static void MHal_PNL_PanelGamma_Enable(bool bEnable)
{
    W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,bEnable?0x1:0x0,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_EN_01B4);
}
static bool MHal_PNL_GetPanelGamma_Enable(void)
{
    return R2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_EN_01B4);
}
static void MHal_PNL_PanelGamma_Set2LUTMode(struct udevice *dev,MS_PNL_PNLGAMMA_Config *pstPNLGammaConfig)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return;
    }
    if(priv->pnl_lib_version != VERSION4)
    {
        W2BYTEMSK(REG_01A8_PAFRC_BKA324,(pstPNLGammaConfig->u8Gamma2LutMode & 0x03),REG_01A8_PAFRC_BKA324_REG_GAMMA_2LUT_MODE_SEL);
        W2BYTEMSK(REG_01A4_PAFRC_BKA324,(pstPNLGammaConfig->bGamma2LutEnable? 0x1:0x0),REG_01A4_PAFRC_BKA324_REG_GAMMA_2LUT_EN);
    }
}
static bool MHal_PNL_PanelGamma_Get2LutEnable(struct udevice *dev)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return FALSE;
    }
    if(priv->pnl_lib_version != VERSION4)
    {
        return R2BYTEMSK(REG_01A4_PAFRC_BKA324,REG_01A4_PAFRC_BKA324_REG_GAMMA_2LUT_EN);
    }
    else
    {
        return FALSE;
    }
}

static bool MHal_PNL_Support_PanelGamma_W_Channel(void)
{
#ifdef SUPPORT_PANEL_GAMMA_W_CHANNEL
    return SUPPORT_PANEL_GAMMA_W_CHANNEL;
#endif
    return FALSE;
}

static bool MHal_PNL_GetPanelGammaTbl_From_Reg(struct udevice *dev, ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl)
{
    u16 u16NumOfLevel =1024;
    u16 u16Addr = 0;
    u8 u8Channel =0;
    bool bGammaByPass = MHal_PNL_GetPanelGammaByPass();
    bool bSupportWChannel = MHal_PNL_Support_PanelGamma_W_Channel();
    u16 u16Timeout = 0;
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return FALSE;
    }

    CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16RChannel0);
    CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16GChannel0);
    CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16BChannel0);
    if(bSupportWChannel == TRUE)
    {
        CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16WChannel0);
    }

    if (bGammaByPass == TRUE)
    {
        MHal_PNL_SetPanelGammaByPass(FALSE);
    }

    for(u8Channel = 0; u8Channel <4; u8Channel++)
    {
        //1. set Read channel
        W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,u8Channel,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_CH_SEL_01B4);

        for(u16Addr = 0; u16Addr < u16NumOfLevel; u16Addr++)
        {
            //2. set LUT_ADDR 0
            W2BYTEMSK(REG_01B0_PAFRC_BKA324_V004,u16Addr,REG_01B0_PAFRC_BKA324_V004_REG_GAMMA_ADR_01B0);
            //3. toggle LUT_R_FLAG
            W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,1,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_RD_EN_01B4);
            while(R2BYTEMSK(REG_01B4_PAFRC_BKA324_V004, REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_RD_EN_01B4) && (u16Timeout < MAX_DELAY_TIME))
            {
                udelay(10);
                u16Timeout++;
            }

            if(u8Channel == 0) //R channel
            {
                pstGetPNLGammaTbl->pu16RChannel0[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
            }
            if(u8Channel == 1) //G channel
            {
                pstGetPNLGammaTbl->pu16GChannel0[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
            }
            if(u8Channel == 2) //B channel
            {
                pstGetPNLGammaTbl->pu16BChannel0[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
            }
            if(u8Channel == 3) //W channel
            {
                if(bSupportWChannel == TRUE)
                {
                    pstGetPNLGammaTbl->pu16WChannel0[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
                }
            }
        }

    }

    if(priv->pnl_lib_version != VERSION4)
    {
        CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16RChannel1);
        CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16GChannel1);
        CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16BChannel1);
        if(bSupportWChannel == TRUE)
        {
            CHECK_PTR_NULL(pstGetPNLGammaTbl->pu16WChannel1);
        }
        // Set Channel1
        // Enable REG_GAMMA_2LUT_EN
        W2BYTEMSK(REG_01A4_PAFRC_BKA324,1,REG_01A4_PAFRC_BKA324_REG_GAMMA_2LUT_EN);
        // Set REG_GAMMA_LUT_SEL 1
        W2BYTEMSK(REG_01A4_PAFRC_BKA324,1,REG_01A4_PAFRC_BKA324_REG_GAMMA_LUT_SEL);
        for(u8Channel = 0; u8Channel <4; u8Channel++)
        {
            //1. set Read channel
            W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,u8Channel,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_CH_SEL_01B4);
            for(u16Addr = 0; u16Addr < u16NumOfLevel; u16Addr++)
            {
                //2. set LUT_ADDR 0
                W2BYTEMSK(REG_01B0_PAFRC_BKA324_V004,u16Addr,REG_01B0_PAFRC_BKA324_V004_REG_GAMMA_ADR_01B0);
                //3. toggle LUT_R_FLAG
                W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,1,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_RD_EN_01B4);
                while(R2BYTEMSK(REG_01B4_PAFRC_BKA324_V004, REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_RD_EN_01B4) && (u16Timeout < MAX_DELAY_TIME))
                {
                    udelay(10);
                    u16Timeout++;
                }

                if(u8Channel == 0) //R channel
                {
                    pstGetPNLGammaTbl->pu16RChannel1[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
                }
                if(u8Channel == 1) //G channel
                {
                    pstGetPNLGammaTbl->pu16GChannel1[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
                }
                if(u8Channel == 2) //B channel
                {
                    pstGetPNLGammaTbl->pu16BChannel1[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
                }
                if(u8Channel == 3) //W channel
                {
                    if(bSupportWChannel == TRUE)
                    {
                        pstGetPNLGammaTbl->pu16WChannel1[u16Addr] = R2BYTEMSK(REG_01C4_PAFRC_BKA324_V004,REG_01C4_PAFRC_BKA324_V004_REG_GAMMA_RD_DATA_01C4);
                    }
                }
            }

        }

        // Disable REG_GAMMA_2LUT_EN
        W2BYTEMSK(REG_01A4_PAFRC_BKA324,0,REG_01A4_PAFRC_BKA324_REG_GAMMA_2LUT_EN);
        // Set REG_GAMMA_LUT_SEL 0
        W2BYTEMSK(REG_01A4_PAFRC_BKA324,0,REG_01A4_PAFRC_BKA324_REG_GAMMA_LUT_SEL);
    }

    if (bGammaByPass == TRUE)
    {
        //restore setting
        MHal_PNL_SetPanelGammaByPass(bGammaByPass);
    }
    return TRUE;
}
static bool MHal_PNL_GetPanelGammaTbl_From_Bin(struct udevice *dev,ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl)
{
    u32 u32index = 0, u32StartAddress = 0;
    MS_PNL_PNLGAMMA_Config stPNLGammaConfig;
    u8 *u8ptr = NULL;
    bool bSupportWChannel = MHal_PNL_Support_PanelGamma_W_Channel();
    memset(&stPNLGammaConfig,0,sizeof(MS_PNL_PNLGAMMA_Config));
    memcpy(&stPNLGammaConfig,(pstGetPNLGammaTbl->pu8GammaTbl + PANEL_GAMMA_MAINHEADER_LEN),sizeof(MS_PNL_PNLGAMMA_Config));

    u32StartAddress = stPNLGammaConfig.u32Table2DStartAddress + stPNLGammaConfig.u16PreTableAlignedSize * pstGetPNLGammaTbl->u16Index;

    if (pstGetPNLGammaTbl->pu8GammaTbl == NULL)
    {
        return FALSE;
    }

    if (pstGetPNLGammaTbl->pu16RChannel0 == NULL || pstGetPNLGammaTbl->pu16GChannel0 == NULL || pstGetPNLGammaTbl->pu16BChannel0 == NULL)
    {
        return FALSE;
    }

    if(bSupportWChannel == TRUE)
    {
        if( pstGetPNLGammaTbl->pu16WChannel0 == NULL )
        {
            return FALSE;
        }
    }

    if (stPNLGammaConfig.bGamma2LutEnable == TRUE)
    {
        if (pstGetPNLGammaTbl->pu16RChannel1 == NULL || pstGetPNLGammaTbl->pu16GChannel1 == NULL || pstGetPNLGammaTbl->pu16BChannel1 == NULL)
        {
            return FALSE;
        }
        if(bSupportWChannel == TRUE)
        {
            if( pstGetPNLGammaTbl->pu16WChannel1 == NULL )
            {
                return FALSE;
            }
        }
    }

    u8ptr = u32StartAddress + pstGetPNLGammaTbl->pu8GammaTbl;

    if((stPNLGammaConfig.u8GammaType & _BIT(4)))
    {
        pstGetPNLGammaTbl->enGammaType = E_APIPNL_GAMMA_10BIT;
    }
    else if ((stPNLGammaConfig.u8GammaType & _BIT(5)))
    {
        pstGetPNLGammaTbl->enGammaType = E_APIPNL_GAMMA_12BIT;
    }

    if((stPNLGammaConfig.u8GammaType & _BIT(0)))
    {
        pstGetPNLGammaTbl->enGammaEntries = E_PNL_PNLGAMMA_256_ENTRIES;
    }
    else
    {
        pstGetPNLGammaTbl->enGammaEntries = E_PNL_PNLGAMMA_1024_ENTRIES;
    }
    /* data format
    //each cmd:
    //|  d_15  |   d_14  |   d_13  |  d_12   |   d_11  |   d_10  |   d_9   |   d_8   |   d_7   |   d_6  |  d_5  |  d_4  |  d_3  |  d_2  |  d_1  | d_0  |
    //|251:240 | 235:224 | 219:208 | 203:192 | 187:176 | 171:160 | 155:144 | 139:128 | 123:112 | 107:96 | 91:80 | 75:64 | 59:48 | 43:32 | 27:16 | 11:0 |
    //
    //R/G/B/W cmd order in DRAM
    //            |END | START |
    //  R_LUT0     63      0
    //  G_LUT0     127     64
    //  B_LUT0     191     128
    //  W_LUT0     255     192
    //  R_LUT1     319     256
    //  G_LUT1     383     320
    //  B_LUT1     447     384
    //  W_LUT1     511     448
    */

    u8* pu8ptr_R0 = u8ptr;
    u8* pu8ptr_G0 = pu8ptr_R0 + PANEL_GAMMA_CHANNEL_OFFSET;  // 64entry  * 32 byte =  2048
    u8* pu8ptr_B0 = pu8ptr_G0 + PANEL_GAMMA_CHANNEL_OFFSET;
    u8* pu8ptr_W0 = pu8ptr_B0 + PANEL_GAMMA_CHANNEL_OFFSET;

    u8* pu8ptr_R1 = pu8ptr_R0 + PANEL_GAMMA_TBL_OFFSET;
    u8* pu8ptr_G1 = pu8ptr_R1 + PANEL_GAMMA_CHANNEL_OFFSET;
    u8* pu8ptr_B1 = pu8ptr_G1 + PANEL_GAMMA_CHANNEL_OFFSET;
    u8* pu8ptr_W1 = pu8ptr_B1 + PANEL_GAMMA_CHANNEL_OFFSET;

    for(u32index=0 ; u32index<PANEL_GAMMA_ENTRY; u32index++)
    {
        //LUT 0
        pstGetPNLGammaTbl->pu16RChannel0[u32index] = ((u16)*((u16 *)pu8ptr_R0 + u32index));
        pstGetPNLGammaTbl->pu16GChannel0[u32index] = ((u16)*((u16 *)pu8ptr_G0 + u32index));
        pstGetPNLGammaTbl->pu16BChannel0[u32index] = ((u16)*((u16 *)pu8ptr_B0 + u32index));
        if(bSupportWChannel == TRUE)
        {
            pstGetPNLGammaTbl->pu16WChannel0[u32index] = ((u16)*((u16 *)pu8ptr_W0 + u32index));
        }
        if (stPNLGammaConfig.bGamma2LutEnable == TRUE)
        {
            //LUT 1
            pstGetPNLGammaTbl->pu16RChannel1[u32index] = ((u16)*((u16 *)pu8ptr_R1 + u32index));
            pstGetPNLGammaTbl->pu16GChannel1[u32index] = ((u16)*((u16 *)pu8ptr_G1 + u32index));
            pstGetPNLGammaTbl->pu16BChannel1[u32index] = ((u16)*((u16 *)pu8ptr_B1 + u32index));
            if(bSupportWChannel == TRUE)
            {
                pstGetPNLGammaTbl->pu16WChannel1[u32index] = ((u16)*((u16 *)pu8ptr_W1 + u32index));
            }
        }
    }
    return TRUE;
}
static bool _MHal_PNL_ADL_SetPanelGammaTbl(struct udevice *dev,ST_PNL_PNLGAMMATBL *pstSetPNLGammaTbl)
{
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_PNL_GAMMA_AUTODOWNLOAD == TRUE)
    u8 *pu8GammaTbl;
    bool bRet = TRUE;
    u32 u32index = 0, u32Size = 0;
    bool b2LutEn = MHal_PNL_PanelGamma_Get2LutEnable(dev);
    u32 u32PnlGammaADLCmdSize;
    u8 *pu8R0 = NULL, *pu8G0 = NULL, *pu8B0 = NULL, *pu8W0 = NULL, *pu8R1 = NULL, *pu8G1 = NULL, *pu8B1 = NULL;
    bool bGammaByPass = MHal_PNL_GetPanelGammaByPass();
    bool bSupportWChannel = MHal_PNL_Support_PanelGamma_W_Channel();

    if( b2LutEn == FALSE )
    {
        if(bSupportWChannel == TRUE)
        {
            u32PnlGammaADLCmdSize = PNLGAMMA_ADL_CMD_256_ENTRY;
        }
        else
        {
            u32PnlGammaADLCmdSize = PNLGAMMA_ADL_CMD_192_ENTRY;
        }
    }
    else
    {
        u32PnlGammaADLCmdSize = PNLGAMMA_ADL_CMD_384_ENTRY;
    }

    u32Size = PNLGAMMA_ADL_CMD_LENGTH*u32PnlGammaADLCmdSize;

    PNL_MALLOC_MEM(pu8GammaTbl, u32Size, bRet);

    if( bRet == TRUE )
    {
        pu8R0 = pu8GammaTbl;
        if( b2LutEn == FALSE )
        {
            pu8G0 = pu8R0 + PANEL_GAMMA_CHANNEL_OFFSET;  // 64entry  * 32 byte =  2048
            pu8B0 = pu8G0 + PANEL_GAMMA_CHANNEL_OFFSET;

            if(bSupportWChannel == TRUE)
            {
                pu8W0 = pu8B0 + PANEL_GAMMA_CHANNEL_OFFSET;
            }
        }
        else
        {
            pu8G0 = pu8R0 + PANEL_GAMMA_CHANNEL_OFFSET;  // 64entry  * 32 byte =  2048
            pu8B0 = pu8G0 + PANEL_GAMMA_CHANNEL_OFFSET;

            pu8R1 = pu8B0 + PANEL_GAMMA_CHANNEL_OFFSET;
            pu8G1 = pu8R1 + PANEL_GAMMA_CHANNEL_OFFSET;
            pu8B1 = pu8G1 + PANEL_GAMMA_CHANNEL_OFFSET;
        }

        for(u32index = 0 ; u32index < PANEL_GAMMA_ENTRY; u32index++)
        {
            if( b2LutEn == FALSE )
            {
                //LUT 0
                *((u16 *)pu8R0 + u32index) = pstSetPNLGammaTbl->pu16RChannel0[u32index];
                *((u16 *)pu8G0 + u32index) = pstSetPNLGammaTbl->pu16GChannel0[u32index];
                *((u16 *)pu8B0 + u32index) = pstSetPNLGammaTbl->pu16BChannel0[u32index];

                if(bSupportWChannel == TRUE)
                {
                    *((u16 *)pu8W0 + u32index) = pstSetPNLGammaTbl->pu16WChannel0[u32index];
                }
            }
            else
            {
                //LUT 0
                *((u16 *)pu8R0 + u32index) = pstSetPNLGammaTbl->pu16RChannel0[u32index];
                *((u16 *)pu8G0 + u32index) = pstSetPNLGammaTbl->pu16GChannel0[u32index];
                *((u16 *)pu8B0 + u32index) = pstSetPNLGammaTbl->pu16BChannel0[u32index];

                //LUT 1
                *((u16 *)pu8R1 + u32index) = pstSetPNLGammaTbl->pu16RChannel1[u32index];
                *((u16 *)pu8G1 + u32index) = pstSetPNLGammaTbl->pu16GChannel1[u32index];
                *((u16 *)pu8B1 + u32index) = pstSetPNLGammaTbl->pu16BChannel1[u32index];
            }
        }

        if (bGammaByPass == TRUE)
        {
            MHal_PNL_SetPanelGammaByPass(FALSE);
        }
        // Write ADL
        if(KHal_XC_WriteAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_PANEL_GAMMA,pu8GammaTbl,u32Size,NULL)!= TRUE)
        {
            UBOOT_ERROR(" Write ADL fail \n.");
            PNL_FREE_MEM(pu8GammaTbl);
            return FALSE;
        }

        //Fire ADL
        if(KHal_XC_FireAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_PANEL_GAMMA) != TRUE)
        {
            UBOOT_ERROR(" Fire ADL fail \n.");
            PNL_FREE_MEM(pu8GammaTbl);
            return FALSE;
        }
        PNL_FREE_MEM(pu8GammaTbl);
    }
    else
    {
        return FALSE;
    }
    return TRUE;
#else
    return FALSE;
#endif
}


static bool MHal_PNL_SetPanelGammaTbl(struct udevice *dev, ST_PNL_PNLGAMMATBL *pstSetPNLGammaTbl)
{
    u16 u16NumOfLevel =1024;
    u16 u16Addr = 0;
    u8 u8Channel =0;
    u16 u16Timeout = 0;
    bool bGammaEnable = 0;
    bool bSupportWChannel = MHal_PNL_Support_PanelGamma_W_Channel();
    bool b2LutEn = MHal_PNL_PanelGamma_Get2LutEnable(dev);
    u8 u8MaxChannel = b2LutEn?PANEL_GAMMA_2LUT_MAX_CHANNEL:PANEL_GAMMA_1LUT_MAX_CHANNEL; // 1: RGBRGB, 0: RGBW
    bool bGammaByPass = MHal_PNL_GetPanelGammaByPass();
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return FALSE;
    }

    if ((priv->pnl_lib_version == VERSION5) || (priv->pnl_lib_version == VERSION6))
    {
        //adl index user mode en have to be set 1 when boot time
        W2BYTEMSK(REG_0080_SCTCON_MISC_BKA3E0_V005, 0x1, REG_0080_SCTCON_MISC_BKA3E0_V005_REG_ADL_IDX_PGA_SEL_0080);
    }

    if( _MHal_PNL_ADL_SetPanelGammaTbl(dev,pstSetPNLGammaTbl) == TRUE )
    {
        //use ADL to set panel gamma table, use ML to set panel gamma enable
        //but ML trigger early ADL so that it shows garbage in AC on
        //so delay 1 vsync for ML
        mdelay(20);
        return TRUE;
    }

    if (bGammaByPass == TRUE)
    {
        MHal_PNL_SetPanelGammaByPass(FALSE);
    }

    // Store Panel Gamma enable flag
    bGammaEnable = MHal_PNL_GetPanelGamma_Enable();
    //Disbale Panel Gamma
    if(bGammaEnable)
    {
        MHal_PNL_PanelGamma_Enable(FALSE);
    }

    //Due to odclk and mcu clock not the same, the set value not stable.
    //Need add 4 NOP for burst wirte to guarantee that set value correct.
    //So use normal write to save time.

    for(u8Channel = 0; u8Channel < u8MaxChannel; u8Channel++)
    {
        W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,0x1,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_BW_EN_01B4); //BW enable
        if( b2LutEn == FALSE )
        {
            // set Write channel
            W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,u8Channel,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_CH_SEL_01B4);
            if(priv->pnl_lib_version != VERSION4)
            {
                //reg_gamma_lut_sel, select lut0 load table
                W2BYTEMSK(REG_01A4_PAFRC_BKA324, 0x0, REG_01A4_PAFRC_BKA324_REG_GAMMA_LUT_SEL);
            }
        }
        else
        {
            // set Write channel
            W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004, (u8Channel%3), REG_01B4_PAFRC_BKA324_REG_GAMMA_CH_SEL);
            if(priv->pnl_lib_version != VERSION4)
            {
                //reg_gamma_lut_sel, select lut0 or lut1 to load table
                W2BYTEMSK(REG_01A4_PAFRC_BKA324, (u8Channel >= 3)?0x1:0x0,REG_01A4_PAFRC_BKA324_REG_GAMMA_LUT_SEL);
            }
        }

        W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,0x1,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_BW_EN_01B4); //BW enable

        for(u16Addr = 0; u16Addr < u16NumOfLevel; u16Addr++)
        {
            //2. set LUT_ADDR
            W2BYTEMSK(REG_01B0_PAFRC_BKA324_V004,u16Addr,REG_01B0_PAFRC_BKA324_V004_REG_GAMMA_ADR_01B0);
            //3. set write data
            if( b2LutEn == FALSE )
            {
                if(u8Channel == 0) //R channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16RChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 1) //G channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16GChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 2) //B channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16BChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 3) //W channel
                {
                    if(bSupportWChannel == TRUE)
                    {
                        W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16WChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                    }
                }
            }
            else
            {
                //lut0
                if(u8Channel == 0) //R0 channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16RChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 1) //G0 channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16GChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 2) //B0 channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16BChannel0[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                //lut1
                if(u8Channel == 3) //R1 channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16RChannel1[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 4) //G1 channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16GChannel1[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
                if(u8Channel == 5) //B1 channel
                {
                    W2BYTEMSK(REG_01B8_PAFRC_BKA324_V004,pstSetPNLGammaTbl->pu16BChannel1[u16Addr],REG_01B8_PAFRC_BKA324_V004_REG_GAMMA_DATA_01B8);
                }
            }

            //4. toggle LUT_W_FLAG_R
            W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,0x1,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_WR_EN_01B4);
            // after setting toggle bit, we need to make sure the bit is already toggled.
            while(R2BYTEMSK(REG_01B4_PAFRC_BKA324_V004, REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_WR_EN_01B4) && (u16Timeout < MAX_DELAY_TIME))
            {
                udelay(10);
                u16Timeout++;
            }
            u16Timeout = 0;
        }

        W2BYTEMSK(REG_01B4_PAFRC_BKA324_V004,0x0,REG_01B4_PAFRC_BKA324_V004_REG_GAMMA_BW_EN_01B4); //Afetr writing one channel, disable BW.
    }

    // restore setting
    if(bGammaEnable)
    {
        MHal_PNL_PanelGamma_Enable(TRUE);
    }
    return TRUE;
}

///drvPNL.c
static bool _MDrv_PNLGammaTbl_MemAllocate(ST_PNL_PNLGAMMATBL *stPNLGammaTbl, bool bGamma2LutEnable)
{
    bool bRet = TRUE;
    bool bReturn = TRUE;
    bool bSupport_PanelGamma_W_Channel = MHal_PNL_Support_PanelGamma_W_Channel();

    if(bGamma2LutEnable == FALSE)
    {
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16RChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16GChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16BChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        if(bSupport_PanelGamma_W_Channel == TRUE)
        {
            PNL_MALLOC_MEM(stPNLGammaTbl->pu16WChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        }

        if(bRet != TRUE)
        {
            debug("[%s][%d] malloc fail\n", __func__,__LINE__);
            bReturn = FALSE;
        }

        if(bSupport_PanelGamma_W_Channel == TRUE)
        {
            if(stPNLGammaTbl->pu16WChannel0 == NULL)
            {
                debug("[%s][%d] malloc fail\n", __func__,__LINE__);
                bReturn = FALSE;
            }
        }
    }
    else
    {
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16RChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16GChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16BChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);

        if(bRet != TRUE)
        {
            debug("[%s][%d] malloc fail\n", __func__,__LINE__);
            bReturn = FALSE;
        }

        PNL_MALLOC_MEM(stPNLGammaTbl->pu16RChannel1, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16GChannel1, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16BChannel1, PANEL_GAMMA_CHANNEL_OFFSET, bRet);

        if(bRet != TRUE)
        {
            debug("[%s][%d] malloc fail\n", __func__,__LINE__);
            bReturn = FALSE;
        }

        PNL_MALLOC_MEM(stPNLGammaTbl->pu16WChannel0, PANEL_GAMMA_CHANNEL_OFFSET, bRet);
        PNL_MALLOC_MEM(stPNLGammaTbl->pu16WChannel1, PANEL_GAMMA_CHANNEL_OFFSET, bRet);

        if(bRet != TRUE)
        {
            debug("[%s][%d] malloc fail\n", __func__,__LINE__);
            bReturn = FALSE;
        }
    }

    if(bReturn == FALSE)
    {
        PNL_FREE_MEM(stPNLGammaTbl->pu16RChannel0);
        PNL_FREE_MEM(stPNLGammaTbl->pu16GChannel0);
        PNL_FREE_MEM(stPNLGammaTbl->pu16BChannel0);
        PNL_FREE_MEM(stPNLGammaTbl->pu16WChannel0);

        PNL_FREE_MEM(stPNLGammaTbl->pu16RChannel1);
        PNL_FREE_MEM(stPNLGammaTbl->pu16GChannel1);
        PNL_FREE_MEM(stPNLGammaTbl->pu16BChannel1);
        PNL_FREE_MEM(stPNLGammaTbl->pu16WChannel1);
        return bReturn;
    }

    return bReturn;
}

//--------------------------------------------------------------------------------------------------------------------
// Panel Gamma Auto Download Format
// Lut0                         2Lut case
// R/G/B/W cmd format in DRAM   R/G/B cmd format in DRAM
//            |END | START |              |END | START |
//  R_LUT0     63      0        R_LUT0     63      0
//  G_LUT0     127     64       G_LUT0     127     64
//  B_LUT0     191     128      B_LUT0     191     128
//  W_LUT0     255     192      R_LUT1     255     192
//                              G_LUT1     319     256
//                              B_LUT1     383     320
// Panel Gamma Bin File Format
// Lut0                         2Lut case
//  R_LUT0     63      0        R_LUT0     63      0
//  G_LUT0     127     64       G_LUT0     127     64
//  B_LUT0     191     128      B_LUT0     191     128
//  W_LUT0     255     192      W_LUT0     255     192
//                              R_LUT1     319     256
//                              G_LUT1     383     320
//                              B_LUT1     447     384
//                              W_LUT1     511     448
//--------------------------------------------------------------------------------------------------------------------
bool MDrv_PNL_SetPanelGammaBIN(struct udevice *dev,u8 * u8GammaTbl, u32 u32Size, u8 u8Index)
{
    ST_PNL_PNLGAMMATBL stPNLGammaTbl;
    MS_PNL_PNLGAMMA_Config stPNLGammaConfig;
    bool bRet = FALSE;

    if(u8GammaTbl == NULL)
    {
        debug("[%s] u8GammaTbl == NULL error\n.", __FUNCTION__);
        return FALSE;
    }

    //get panel gamma sub header
    memset(&stPNLGammaConfig, 0, sizeof(MS_PNL_PNLGAMMA_Config));
    memcpy(&stPNLGammaConfig, (u8GammaTbl + PANEL_GAMMA_MAINHEADER_LEN), sizeof(MS_PNL_PNLGAMMA_Config));

    //get panel gamma RGBW curve table from BIN
    memset(&stPNLGammaTbl, 0, sizeof(ST_PNL_PNLGAMMATBL));
    stPNLGammaTbl.pu8GammaTbl = u8GammaTbl;
    stPNLGammaTbl.enPnlGammaTbl = E_PNL_PNLGAMMA_TBL_FROM_BIN;
    stPNLGammaTbl.u16Index = u8Index;

    if(_MDrv_PNLGammaTbl_MemAllocate(&stPNLGammaTbl, stPNLGammaConfig.bGamma2LutEnable) == FALSE)
    {
        debug("\033[1;32m %s %d: _MDrv_PNLGammaTbl_MemAllocate E_PNL_FAIL\033[0m \n",__func__,__LINE__);
        return FALSE;
    }

    bRet = MHal_PNL_GetPanelGammaTbl_From_Bin(dev,&stPNLGammaTbl);
    if(bRet == TRUE)
    {
        //Set VAC 2Lut mode
        MHal_PNL_PanelGamma_Set2LUTMode(dev, &stPNLGammaConfig);
        MHal_PNL_SetPanelGammaTbl(dev,&stPNLGammaTbl);

        //Enable Panel gamma
        MHal_PNL_PanelGamma_Enable(TRUE);
    }
    else
    {
        debug("[%s] Failed!!!!\n",__FUNCTION__);
    }

    //free memory
    PNL_FREE_MEM(stPNLGammaTbl.pu16RChannel0);
    PNL_FREE_MEM(stPNLGammaTbl.pu16GChannel0);
    PNL_FREE_MEM(stPNLGammaTbl.pu16BChannel0);
    PNL_FREE_MEM(stPNLGammaTbl.pu16WChannel0);

    PNL_FREE_MEM(stPNLGammaTbl.pu16RChannel1);
    PNL_FREE_MEM(stPNLGammaTbl.pu16GChannel1);
    PNL_FREE_MEM(stPNLGammaTbl.pu16BChannel1);
    PNL_FREE_MEM(stPNLGammaTbl.pu16WChannel1);

    return bRet;
}

bool MDrv_PNL_GetPanelGammaTbl(struct udevice *dev,ST_PNL_PNLGAMMATBL *pstGetPNLGammaTbl)
{
    bool bResult = FALSE;
    switch(pstGetPNLGammaTbl->enPnlGammaTbl)
    {
        case E_PNL_PNLGAMMA_TBL_FROM_BIN:
        {
            bResult = MHal_PNL_GetPanelGammaTbl_From_Bin(dev, pstGetPNLGammaTbl);
            break;
        }
        case E_PNL_PNLGAMMA_TBL_FROM_REG:
        {
            bResult = MHal_PNL_GetPanelGammaTbl_From_Reg(dev, pstGetPNLGammaTbl);
            break;
        }
        default:
        {
            debug("ERROR!! SET WRONG type for read Panel gamma!!!!!\n");
            break;
        }

    }
    return bResult;
}

bool MApi_PNL_SetPanelGammaBIN(struct udevice *dev,u8* pu8GammaTab,u32 u32Size, u8 u8Index)
{
    bool bResult = FALSE;

    bResult = MDrv_PNL_SetPanelGammaBIN(dev, pu8GammaTab, u32Size, u8Index);

    return bResult;
}

void _MHal_PNL_TCON_Path_Sel_By_Ver(uint32_t u32DataPath_sel)
{
	if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_1) { //MTK Mode 4k2k@60
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x00, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x01, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x01, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, Fld(2, 8, AC_MSKB1));
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, REG_003C_PAFRC_BKA324_V004_REG_VAC_BF_PANEL_GAMMA_EN_003C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x03, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_9) { //MTK Mode 4k2k@120
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x00, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x01, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x01, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, Fld(2, 8, AC_MSKB1));
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, REG_003C_PAFRC_BKA324_V004_REG_VAC_BF_PANEL_GAMMA_EN_003C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x01, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_3) { //Specific Mode 4k2k@60
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x00, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x00, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x00, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, Fld(2, 8, AC_MSKB1));
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, REG_003C_PAFRC_BKA324_V004_REG_VAC_BF_PANEL_GAMMA_EN_003C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x03, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_10) { //Specific Mode 4k2k@120
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x00, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x00, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x00, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, Fld(2, 8, AC_MSKB1));
		W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, 0x00, REG_003C_PAFRC_BKA324_V004_REG_VAC_BF_PANEL_GAMMA_EN_003C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x01, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_7) { // SiW Mode 4k2k@60
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x03, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x01, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x00, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x00, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x03, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_11) { //SiW Mode 4k2k@120
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x03, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x01, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x00, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x00, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x01, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_8) {//Specific OLED Mode 4k2k@60
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x01, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x00, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x00, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x03, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	} else if (u32DataPath_sel == E_PNL_TCON_PATH_MODE_12) {//Specific OLED Mode 4k2k@120
		//W2BYTEMSK((SCDISP_BKA4FA_V004 + 0x0100), 0x01, Fld(3, 0, AC_MSKB0));
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
		W2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, 0x00, REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180);
		W2BYTEMSK(REG_0140_DEMURA_BKA377_V004, 0x00, REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_MOD_EN_0140);
		W2BYTEMSK(REG_012C_PAFRC_BKA324_V004, 0x00, REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);

		W2BYTEMSK(REG_1148_CKGEN01_V005, 0x01, REG_1148_CKGEN01_V005_REG_CKG_S_B2P_ODCLK_SCTC_TMP_1148);
	}
}

void MHal_PNL_TCON_Path_Patch(struct udevice *dev)
{
#ifndef HEX_01
#define HEX_01 0x01
#endif
    struct mtk_panel_priv *priv = dev_get_priv(dev);
	if (!priv) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

	if (priv->tcon_info.stPanelInfo.u32DataPath_sel >= E_PNL_TCON_PATH_MODE_MAX) {
		debug("[%s] Ivalid data path sel=%d\n", __func__, priv->tcon_info.stPanelInfo.u32DataPath_sel);
		return;
	}

	if (priv->pnl_lib_version == VERSION5) {
		_MHal_PNL_TCON_Path_Sel_By_Ver(priv->tcon_info.stPanelInfo.u32DataPath_sel);

		if (priv->tcon_info.stPanelInfo.u32DataPath_sel == E_PNL_TCON_PATH_MODE_2) {// if 144, divided by 1
			//W2BYTEMSK((0x206000+0x198), 0x0, Fld(1,8,AC_MSKB2));
			W2BYTEMSK(REG_0198_CKGEN01_V004, 0x1, REG_0198_CKGEN01_V004_REG_CKG_S_GPO_0198);
		} else if (priv->tcon_info.stPanelInfo.u32DataPath_sel == E_PNL_TCON_PATH_MODE_1) {
			//LPLL frequency divide by 2 for 4K2K60
			W2BYTEMSK(REG_0198_CKGEN01_V004, HEX_01, REG_0198_CKGEN01_V004_REG_CKG_S_GPO_0198);
		} else {
			//W2BYTEMSK((0x206000+0x198), 0x1, Fld(1,8,AC_MSKB2));
			W2BYTEMSK(REG_0198_CKGEN01_V004, 0x0, REG_0198_CKGEN01_V004_REG_CKG_S_GPO_0198);
		}
	} else {
		u8 u8ModeIdx = priv->tcon_info.stPanelInfo.u32DataPath_sel - 1;
		u8 u8RegCount = 0;
		u8 u8PAFRC_SWITCH_TO_MOD_EN = 0;

		for (u8RegCount = 0; u8RegCount < TCON_PATH_REG_COUNT; u8RegCount++)
		{
			W2BYTEMSK(stTconPathReg[u8RegCount],
				stTconPathVal[u8RegCount][u8ModeIdx],
				stTconPathMask[u8RegCount]);
		}

		if (priv->tcon_info.stPanelInfo.u32DataPath_sel == E_PNL_TCON_PATH_MODE_2) {// if 144, divided by 1
			//W2BYTEMSK((0x206000+0x198), 0x0, Fld(1,8,AC_MSKB2));
			W2BYTEMSK(REG_0198_CKGEN01_V004, 0x0, REG_0198_CKGEN01_V004_REG_CKG_S_GPO_0198);
		} else {
			//W2BYTEMSK((0x206000+0x198), 0x1, Fld(1,8,AC_MSKB2));
			W2BYTEMSK(REG_0198_CKGEN01_V004, 0x1, REG_0198_CKGEN01_V004_REG_CKG_S_GPO_0198);
		}

		u8PAFRC_SWITCH_TO_MOD_EN =
			R2BYTEMSK(REG_012C_PAFRC_BKA324_V004,
				  REG_012C_PAFRC_BKA324_V004_REG_PAFRC_SWITCH_TO_MOD_EN_012C);
		//When use PAFRC in MOD, need set OD mode to 1
		if (u8PAFRC_SWITCH_TO_MOD_EN)
			W2BYTEMSK(REG_01E0_TCON_4K, 0x1, REG_01E0_TCON_4K_REG_OD_MODE_01E0);
    }
}

// Dump TCON
void MDrv_PNL_TCON_DumpGENRegTab(struct udevice *dev,u8* pu8TconTab,u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32Addr;
    u8 u8Mask;
    u8 u8Value;
    //u16 u16TconSubBank;

    debug("MDrv_PNL_TCON_DumpGENRegTab\n");

    debug("tab: gen \n");

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return;
    }

    //u16TconSubBank = MHal_PNL_Read_TCON_SubBank(pInstance);
    //PNL_DBG("u16TconSubBank=%x\n", u16TconSubBank);

    while (u16RegisterCount--)
    {
        u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
        u8Mask  = pu8TconTab[(u32tabIdx +4)] & 0xFF;
        u8Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;

        debug("[addr=%04tx, msk=%02x, val=%02x] \n", (ptrdiff_t)u32Addr, u8Mask, u8Value);

        //Update to support ext register.
        TCON_W1BYTEMSK(u32Addr, u8Value, u8Mask);
        u32tabIdx = u32tabIdx + 6;
    }

    MHal_PNL_TCON_Path_Patch(dev);
    debug("MDrv_PNL_TCON_DumpGENRegTab end\n");
}

void MDrv_PNL_TCON_DumpGpioRegTab(u8* pu8TconTab,u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32Addr;
    u8 u8Mask;
    u8 u8Value;
    //u16 u16TconSubBank;

    debug("MDrv_PNL_TCON_DumpGpioRegTab\n");

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return;
    }

    //u16TconSubBank = MHal_PNL_Read_TCON_SubBank(pInstance);
    //PNL_DBG("u16TconSubBank=%x\n", u16TconSubBank);

    while (u16RegisterCount--)
    {
        u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
        u8Mask  = pu8TconTab[(u32tabIdx +4)] & 0xFF;
        u8Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;

        debug("[addr=%04tx, msk=%02x, val=%02x] \n", (ptrdiff_t)u32Addr, u8Mask, u8Value);

        //Update to support ext register.
        TCON_W1BYTEMSK(u32Addr, u8Value, u8Mask);
        u32tabIdx = u32tabIdx + 6;
    }

    TCON_W1BYTEMSK(0x2444A0, BIT(1), BIT(1));
    mdelay(30); //need to use mdelay , udelay didn't work
    TCON_W1BYTEMSK(0x2444A0, 0, BIT(1));

    debug("MDrv_PNL_TCON_DumpGpioRegTab end\n");
}

void MDrv_PNL_TCON_DumpSCRegTab(u8* pu8TconTab,u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32Addr;
    u16 u16Mask;
    u16 u16Value;

    debug("MDrv_PNL_TCON_DumpSCRegTab\n");
    debug("tab: sc \n");

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return;
    }

    while (u16RegisterCount--)
    {
        u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
        u16Mask  = pu8TconTab[(u32tabIdx +4)] & 0xFF;
        u16Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;

        debug("[addr=%04tx, msk=%02x, val=%02x] \n",(ptrdiff_t) u32Addr, u16Mask, u16Value);

        TCON_W1BYTEMSK(u32Addr, u16Value, u16Mask);
        u32tabIdx = u32tabIdx + 6;
    }

    //MHal_PNL_TCON_SCPatch(pInstance);
    debug("MDrv_PNL_TCON_DumpSCRegTab end\n");
}

void MDrv_PNL_TCON_DumpMODRegTab(u8* pu8TconTab,u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32Addr;
    u16 u16Mask;
    u16 u16Value;

    debug("MDrv_PNL_TCON_DumpMODRegTab\n");
    debug("tab: mod \n");

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return;
    }

    //pPNLResourcePrivate->stdrvPNL.g_bDrvPnl_UseTConTable_Mod = TRUE;

    while(u16RegisterCount--)
    {
        u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
        u16Mask  = pu8TconTab[(u32tabIdx +4)] & 0xFF;
        u16Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;

        debug("[addr=%04tx, msk=%02x, val=%02x] \n",(ptrdiff_t) u32Addr, u16Mask, u16Value);

        //Update to support ext register.
        TCON_W1BYTEMSK(u32Addr, u16Value, u16Mask);
        u32tabIdx = u32tabIdx + 6;
    }

    /// Add the TCON patch at here for different chip
    //MHal_PNL_TCON_Patch();
    //PNL_DBG("MDrv_PNL_TCON_DumpMODRegTab END: REG_MOD_BK00_6E_L=%X\n", MOD_R2BYTE(REG_MOD_BK00_6E_L));
    debug("MDrv_PNL_TCON_DumpMODRegTab end\n");
}

void MDrv_PNL_TCON_DumpPanelInfo(struct udevice *dev,u8* pu8TconTab,u32 u32RegisterlistSize)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);
    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return;
    }

    u16 u16PanelInfoID;
    u32 u32PanelInfoValue;
    u16 u16Count = 0;
    u16 u16MaxRegisterlistSize = u32RegisterlistSize/6;
    //ST_PNL_TCON_PANELINFO stPanelInfo;
    memset(&priv->tcon_info.stPanelInfo,0,sizeof(ST_PNL_TCON_PANELINFO));

    //demura enable default set to true
    priv->tcon_info.stPanelInfo.u32DemuraEnable = TRUE;

	debug("u16MaxRegisterlistSize=%d u32RegisterlistSize=%d\n",u16MaxRegisterlistSize,u32RegisterlistSize);
    for(u16Count=0;u16Count<u16MaxRegisterlistSize;u16Count++)
    {
        u16PanelInfoID = (pu8TconTab[1+6*u16Count]<<8) + (pu8TconTab[6*u16Count]);
        u32PanelInfoValue = (pu8TconTab[5+6*u16Count]<<24) + (pu8TconTab[4+6*u16Count]<<16) + (pu8TconTab[3+6*u16Count]<<8) + (pu8TconTab[2+6*u16Count]);
        debug("u16PanelInfoID=%d u32PanelInfoValue=%d\n",u16PanelInfoID,u32PanelInfoValue);

        switch(u16PanelInfoID)
        {
           case E_PNL_TCON_PANELINFO_PANELLINKTYPE:
               priv->tcon_info.stPanelInfo.u32PanelLinkType = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELLINKEXTTYPE:
               priv->tcon_info.stPanelInfo.u32PanelLinkExtType = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_FIXEDVABCKPORCH:
               priv->tcon_info.stPanelInfo.u32FixedVBackPorch = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_FIXEDHBACKPORCH:
               priv->tcon_info.stPanelInfo.u32FixedHBackPorch = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VSYNC_START:
               priv->tcon_info.stPanelInfo.u32VsyncStart = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VSYNC_END:
               priv->tcon_info.stPanelInfo.u32VsyncEnd = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VDESTART:
               priv->tcon_info.stPanelInfo.u32VDEStart = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VDEND:
               priv->tcon_info.stPanelInfo.u32VDEEnd = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELMAXVTOTAL:
               priv->tcon_info.stPanelInfo.u32PanelMaxVTotal = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELVTOTAL:
               priv->tcon_info.stPanelInfo.u32PanelVTotal = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_MINVTOTAL:
               priv->tcon_info.stPanelInfo.u32PanelMinVTotal = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VDEHEADDUMMY:
               priv->tcon_info.stPanelInfo.u32VDEHeadDummy = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VDETAILDUMMY:
               priv->tcon_info.stPanelInfo.u32VDETailDummy = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_HSYNC_START:
               priv->tcon_info.stPanelInfo.u32HsyncStart = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_HSYNC_END:
               priv->tcon_info.stPanelInfo.u32HsyncEnd = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_HDESTART:
               priv->tcon_info.stPanelInfo.u32HDEStart = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_HDEEND:
               priv->tcon_info.stPanelInfo.u32HDEEnd = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELMAXHTOTAL:
               priv->tcon_info.stPanelInfo.u32PanelMaxHTotal = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELHTOTAL:
               priv->tcon_info.stPanelInfo.u32PanelHTotal = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELMINHTOTAL:
               priv->tcon_info.stPanelInfo.u32PanelMinHTotal = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_HDEHEADDUMMY:
               priv->tcon_info.stPanelInfo.u32HDEHeadDummy = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_HDETAILDUMMY:
               priv->tcon_info.stPanelInfo.u32HDETailDummy = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELMAXDCLK:
               priv->tcon_info.stPanelInfo.u32PanelMaxDCLK = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELDCLK:
               priv->tcon_info.stPanelInfo.u32PanelDCLK = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELMINDCLK:
               priv->tcon_info.stPanelInfo.u32PanelMinDCLK = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELMAXSET:
               priv->tcon_info.stPanelInfo.u32PanelMaxSET = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_MINSET:
               priv->tcon_info.stPanelInfo.u32PanelMinSET = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_OUTTIMINGMODE:
               priv->tcon_info.stPanelInfo.u32OutTimingMode = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_TOTALPAIR:
               priv->tcon_info.stPanelInfo.u32HTotalPair = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PAIREVEN:
               priv->tcon_info.stPanelInfo.u32VTotalPair_Even = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PAIRODD:
               priv->tcon_info.stPanelInfo.u32VTotalPair_Odd = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_DUALPORT:
               priv->tcon_info.stPanelInfo.u32DaulPort = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELHSYNCWIDTH:
               priv->tcon_info.stPanelInfo.u32PanelHsyncWidth = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELHSYNCBACKPORCH:
               priv->tcon_info.stPanelInfo.u32PanelHsyncBackPorch = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELVSYNCWIDTH:
               priv->tcon_info.stPanelInfo.u32PanelVsyncWidth = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_PANELVBACKPORCH:
               priv->tcon_info.stPanelInfo.u32PanelVsyncBackPorch = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_SSC_ENABLE:
               priv->tcon_info.stPanelInfo.u32SSCEnable = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_SSC_FMODULATION:
               priv->tcon_info.stPanelInfo.u32SSC_Fmodulation = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_SSC_PERCENTAGE:
               priv->tcon_info.stPanelInfo.u32SSC_Percentage = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_SSC_BIN_CTRL:
               priv->tcon_info.stPanelInfo.u32SSC_TconBinCtrl = u32PanelInfoValue;
               break;
            case E_PNL_TCON_PANELINFO_DEMURA_SEL:
               priv->tcon_info.stPanelInfo.u32Demura_sel = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_DATA_PATH_SEL:
               priv->tcon_info.stPanelInfo.u32DataPath_sel = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_VCOM_SEL:
               priv->tcon_info.stPanelInfo.u32Vcom_sel = u32PanelInfoValue;
               break;
           case E_PNL_TCON_PANELINFO_DEMURA_ENABLE:
               priv->tcon_info.stPanelInfo.u32DemuraEnable = u32PanelInfoValue;
               break;
        }
    }
    priv->linktype = priv->tcon_info.stPanelInfo.u32PanelLinkType;

    priv->hsync_st = priv->tcon_info.stPanelInfo.u32HsyncStart;
    priv->hsync_w = priv->tcon_info.stPanelInfo.u32HsyncEnd - priv->tcon_info.stPanelInfo.u32HsyncStart + 1;
    priv->vsync_st = priv->tcon_info.stPanelInfo.u32VsyncStart;
    priv->vsync_w = priv->tcon_info.stPanelInfo.u32VsyncEnd - priv->tcon_info.stPanelInfo.u32VsyncStart + 1;

    priv->de_hstart = priv->tcon_info.stPanelInfo.u32HDEStart;
    priv->de_vstart = priv->tcon_info.stPanelInfo.u32VDEStart;
    priv->de_width = priv->tcon_info.stPanelInfo.u32HDEEnd - priv->tcon_info.stPanelInfo.u32HDEStart + 1;
    priv->de_height = priv->tcon_info.stPanelInfo.u32VDEEnd - priv->tcon_info.stPanelInfo.u32VDEStart + 1;

    //priv->max_htt = priv->tcon_info.stPanelInfo.u32PanelMaxHTotal;
    priv->typ_htt = priv->tcon_info.stPanelInfo.u32PanelHTotal;
    // priv->min_htt = priv->tcon_info.stPanelInfo.u32PanelMinHTotal;

    //priv->max_vtt = priv->tcon_info.stPanelInfo.u32PanelMaxVTotal;
    priv->typ_vtt = priv->tcon_info.stPanelInfo.u32PanelVTotal;
    //priv->min_vtt = priv->tcon_info.stPanelInfo.u32PanelMinVTotal;
    // max_htt / min_htt / max_vtt / min_vtt follow dtsi value.

    priv->max_dclk = priv->tcon_info.stPanelInfo.u32PanelMaxDCLK;
    priv->typ_dclk = priv->tcon_info.stPanelInfo.u32PanelDCLK;
    priv->min_dclk = priv->tcon_info.stPanelInfo.u32PanelMinDCLK;

	priv->ssc_info[priv->epnl_group].ssc_en = priv->tcon_info.stPanelInfo.u32SSCEnable;
	priv->ssc_info[priv->epnl_group].ssc_modulation = priv->tcon_info.stPanelInfo.u32SSC_Fmodulation;
	priv->ssc_info[priv->epnl_group].ssc_deviation = priv->tcon_info.stPanelInfo.u32SSC_Percentage;
}

void MDrv_PNL_TCON_DumpPowerSequenceRegTab(u8* pu8TconTab,u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32SubAddr = 0;
    u8 u8SubMask = 0;
    u8 u8SubNum = 0;
    u32 u32Addr = 0;
    u16 u16Mask = 0;
    u16 u16Value = 0;
    u16 u16Delay = 0;
    //u8 u8Reserved = 0;

    debug("tab: power sequence \n");
    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return;
    }
    while (u16RegisterCount--)
    {
        u32SubAddr = ((pu8TconTab[u32tabIdx+2]<<16) + (pu8TconTab[(u32tabIdx+1)]<<8) + pu8TconTab[(u32tabIdx)]);
        u8SubMask = pu8TconTab[(u32tabIdx + 3)];
        u8SubNum = pu8TconTab[(u32tabIdx + 4)];
        u32Addr = ((pu8TconTab[u32tabIdx+7]<<16) + (pu8TconTab[(u32tabIdx+6)]<<8) + pu8TconTab[(u32tabIdx+5)]);
        u16Mask = ((pu8TconTab[u32tabIdx+9]<<8) + pu8TconTab[(u32tabIdx+8)]);
        u16Value = ((pu8TconTab[u32tabIdx+11]<<8) + pu8TconTab[(u32tabIdx+10)]);
        u16Delay = ((pu8TconTab[u32tabIdx+13]<<8) + pu8TconTab[(u32tabIdx+12)]);
        //u8Reserved = pu8TconTab[(u32tabIdx+14)];

        debug("u32SubAddr %04tx\n",(ptrdiff_t)u32SubAddr);
        debug("u8SubMask %02x\n",u8SubMask);
        debug("u8SubNum %02x\n",u8SubNum);
        debug("u32Addr %04tx\n",(ptrdiff_t)u32Addr);
        debug("u16Mask %02x\n",u16Mask);
        debug("u16Value %02x\n",u16Value);
        debug("u8Delay %d\n",u16Delay);

        if(u32SubAddr!=0)//Change sub bank
        {
            TCON_W2BYTEMSK(u32SubAddr, u8SubNum, u8SubMask);
        }
        if(u32Addr!=0)
        {
            TCON_W2BYTEMSK(u32Addr,u16Value,u16Mask);
        }
        mdelay(u16Delay);

        u32tabIdx = u32tabIdx + 15;
    }
}

void MHal_PNL_OverDriver_VAC_HScaling_Setting(void)
{
#if OVERDRIVE_ENABLE_VAC_HSCALING
    u16 u16TconPath = 0;
    u16 u16VACPath = 0;
    bool bIsVacBeforeOD = FALSE;
    u16VACPath = R2BYTEMSK(REG_003C_PAFRC_BKA324_V004, Fld(2,8,AC_MSKB1));//bit[9:8]

    if (u16VACPath == 0x1) // VAC move to WM output
    {
        bIsVacBeforeOD = TRUE;
    }
    else if (u16VACPath == 0x2) //VAC mode to HSE output
    {
        bIsVacBeforeOD = FALSE;
    }
    else //VAC in the middle of TCON
    {
        u16TconPath = R2BYTEMSK(REG_0180_SCTCON_BKA4F7_V004, REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180);
        if ((u16TconPath == TCON_PATH_DEMURA_PGA_OD) ||
            (u16TconPath == TCON_PATH_PGA_DEMURA_OD) ||
            (u16TconPath == TCON_PATH_PGA_OD_DEMURA))
        {
            bIsVacBeforeOD = TRUE;
        }
        else
        {
            bIsVacBeforeOD = FALSE;
        }
    }

    if(bIsVacBeforeOD) // enable vac hscaling
    {
        u16 u16Case = 0;
        u16 u16VacPol = R2BYTEMSK(REG_0020_PAFRC_BKA324_V004, REG_0020_PAFRC_BKA324_V004_REG_VAC_POLARITY_LUT0_0020);
        bool bRBSwap = FALSE;
        // set mode
        W2BYTEMSK(REG_01B0_OD_3RD_BKA338_V004, 1, REG_01B0_OD_3RD_BKA338_V004_REG_VAC_SCALING_EN_01B0);
        if ((u16VacPol == EVA_POLARITY_LUT0_MODE_3) ||
            ((u16VacPol == EVA_POLARITY_LUT0_MODE_2) && (bRBSwap == TRUE)))
        {
            u16Case = 3;
        }
        else if(u16VacPol == EVA_POLARITY_LUT0_MODE_2 && (bRBSwap == FALSE))
        {
            u16Case = 2;
        }
        else if(u16VacPol == EVA_POLARITY_LUT0_MODE_1)
        {
            u16Case = 1;
        }
        else
        {
            u16Case = 0;
        }
        W2BYTEMSK(REG_01B0_OD_3RD_BKA338_V004, u16Case, REG_01B0_OD_3RD_BKA338_V004_REG_VAC_CASE_01B0);
    }
    else //disable vac hscaling
    {
        W2BYTEMSK(REG_01B0_OD_3RD_BKA338_V004, 0, REG_01B0_OD_3RD_BKA338_V004_REG_VAC_SCALING_EN_01B0);
    }
#endif
}

bool MHal_PNL_OverDriver_IsEnableRGBW(void)
{
#if SUPPORT_OVERDRIVE
    return (R2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004,REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC));
#else
    return FALSE;
#endif
}

void MHal_PNL_OverDriver_EnableWChannel(bool bEnWChannel)
{
#if SUPPORT_OVERDRIVE
    //use dummy register to store tcon w channel enable status
    W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004, bEnWChannel? 1: 0,REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);
#endif
}
////////////////////////////////////////////////////////////////////////
// Turn OD function
////////////////////////////////////////////////////////////////////////
void MHal_PNL_OverDriver_Init(struct udevice *dev, u64 u64OD_MSB_Addr, u64 u64OD_MSB_limit, u64 u64OD_LSB_Addr, u64 u64OD_LSB_limit, u8 u8MIUSel)
{
#if SUPPORT_OVERDRIVE
    u64 phypg_adde_base = 0;
    u64 phypg_addr_limit = 0;
    u64 phydram_addr_offset = 0;
    u32 u32panel_pixels = 0;
    u16 u16hsize = 0;
    u16 u16vsize = 0;
    //u32 u32ipm_offset = 0;
#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
    u16 u16Timeout = 0;
#endif

    struct mtk_panel_priv *priv = dev_get_priv(dev);
    if (priv == NULL) {
        debug("[%s] get device private fail\n", __func__);
        return;
    }
#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
    if(MHal_PNL_OverDriver_IsEnableRGBW())
    {
        //If LPLL is powerdown, Double buffer can't update register value.
        if(R2BYTEMSK(L_BK_LPLL(0x03),BIT(5))!= 0)
        {
            MHal_PNL_PowerDownLPLL(FALSE);
        }
        //Disable Overdriver RGBW to prevent miu hit.
        SC_W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004,0,REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);
        while(SC_R2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004, REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC)&&(u16Timeout < MAX_DELAY_TIME))
        {
            mdelay(10);
            u16Timeout++;
        }
    }
#endif
    u16hsize = ALIGN_8(priv->de_width);//panel H, need align 8
    u16vsize = priv->de_height;//panel V
#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
    if(MHal_PNL_OverDriver_IsEnableRGBW())
    {
        u16hsize = (u16hsize * OVERDRIVE_RGB_CHANNEL) / OVERDRIVE_RGBW_CHANNEL;// RGBW mode h*3/4
    }
#endif

    u32panel_pixels =u16hsize*u16vsize;

    //SC_W2BYTEMSK(REG_SC_BK16_61_L,u8MIUSel<<8,BIT(8)|BIT(9)); // OD MIU select
    W2BYTEMSK(REG_0054_OD_1ST_BKA336_V004, (u16)(u64OD_MSB_Addr & 0xFFFF), REG_0054_OD_1ST_BKA336_V004_REG_OD_BASE_ADR_0_0054); // OD MSB request base address
    W2BYTEMSK(REG_0058_OD_1ST_BKA336_V004, (u16)((u64OD_MSB_Addr >> 16) & 0xFFFF), REG_0058_OD_1ST_BKA336_V004_REG_OD_BASE_ADR_1_0058); // OD MSB request base address

    W2BYTEMSK(REG_00E4_OD_1ST_BKA336_V004, ((OVERDRIVE_MODE*u32panel_pixels+4096)/32)&0xFFFF, REG_00E4_OD_1ST_BKA336_V004_REG_OD_WADR_MAX_LIMIT_0_00E4); //low byte
    W2BYTEMSK(REG_00E8_OD_1ST_BKA336_V004, (((OVERDRIVE_MODE*u32panel_pixels+4096)/32)>>16), REG_00E8_OD_1ST_BKA336_V004_REG_OD_WADR_MAX_LIMIT_1_00E8); //hightbyte

    W2BYTEMSK(REG_00EC_OD_1ST_BKA336_V004, (u32panel_pixels)&0xFFFF, REG_00EC_OD_1ST_BKA336_V004_REG_OD_RADR_MAX_LIMIT_0_00EC); //low byte
    W2BYTEMSK(REG_00F0_OD_1ST_BKA336_V004, (u32panel_pixels)>>16, REG_00F0_OD_1ST_BKA336_V004_REG_OD_RADR_MAX_LIMIT_1_00F0); //high byte

    W2BYTEMSK(REG_00EC_OD_1ST_BKA336_V004, (u32panel_pixels)&0xFFFF, REG_00EC_OD_1ST_BKA336_V004_REG_OD_RADR_MAX_LIMIT_0_00EC); //low byte
    W2BYTEMSK(REG_00F0_OD_1ST_BKA336_V004, (u32panel_pixels)>>16, REG_00F0_OD_1ST_BKA336_V004_REG_OD_RADR_MAX_LIMIT_1_00F0); //high byte


    if(OVERDRIVE_ENABLE_HSCALING == TRUE)
    {
        if(OVERDRIVE_ENABLE_HSD_4X ==TRUE)
        {
            W2BYTEMSK(REG_01B0_OD_1ST_BKA336_V004,0x1,REG_01B0_OD_1ST_BKA336_V004_REG_HSD_2X4X_SEL_01B0); // HScaling_4X
            W2BYTEMSK(REG_01A0_OD_1ST_BKA336_V004,0xE60D, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_01A4_OD_1ST_BKA336_V004,0xD, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_00D0_OD_2ND_BKA337_V004,0x1804, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_00D4_OD_2ND_BKA337_V004,0x503C, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_00D8_OD_2ND_BKA337_V004,0x183C, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_00DC_OD_2ND_BKA337_V004,0x4, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_00E0_OD_2ND_BKA337_V004,0x8819, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_00E4_OD_2ND_BKA337_V004,0xFA65, Fld(16,0,AC_FULLW10));
            u16hsize=u16hsize/4;
        }
        else
        {
            W2BYTEMSK(REG_01B0_OD_1ST_BKA336_V004,0x0,REG_01B0_OD_1ST_BKA336_V004_REG_HSD_2X4X_SEL_01B0); // HScaling_2X
            W2BYTEMSK(REG_0198_OD_1ST_BKA336_V004,0x843E, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_019C_OD_1ST_BKA336_V004,0x3E, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_01A0_OD_1ST_BKA336_V004,0xE60D, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_01A4_OD_1ST_BKA336_V004,0xD, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_01A8_OD_1ST_BKA336_V004,0x95EB, Fld(16,0,AC_FULLW10));
            W2BYTEMSK(REG_01AC_OD_1ST_BKA336_V004,0xEB95, Fld(16,0,AC_FULLW10));
            u16hsize=u16hsize/2;
        }
    }

    if(OVERDRIVE_ENABLE_VSCALING == TRUE)
    {
        W2BYTEMSK(REG_003C_OD_2ND_BKA337_V004,u16vsize, Fld(16,0,AC_FULLW10));//V_size
        W2BYTEMSK(REG_0160_OD_1ST_BKA336_V004,u16vsize, Fld(16,0,AC_FULLW10));//vertical size of a frame
        //vertical scaling 2x
        W2BYTEMSK(REG_00E8_OD_2ND_BKA337_V004,0x8040, Fld(16,0,AC_FULLW10));
        W2BYTEMSK(REG_00EC_OD_2ND_BKA337_V004,0x40, Fld(16,0,AC_FULLW10));
        u16vsize=u16vsize/2;
    }

    if(R2BYTEMSK(REG_0044_OD_1ST_BKA336_V004,REG_0044_OD_1ST_BKA336_V004_REG_OD_USER_WEIGHT_0044) == OVERDRIVE_WEIGHT_DEFAULT)
    {
        // If equal to hardware default value, it means TCON bin do not write this value, software should write this value instead.
        W2BYTEMSK(REG_0044_OD_1ST_BKA336_V004,OVERDRIVE_WEIGHT,REG_0044_OD_1ST_BKA336_V004_REG_OD_USER_WEIGHT_0044); //OD Weight
    }
    if(R2BYTEMSK(REG_0048_OD_1ST_BKA336_V004,REG_0048_OD_1ST_BKA336_V004_REG_OD_ACT_THRD_0048) == OVERDRIVE_ACTIVE_THRESHOLD_DEFAULT)
    {
        // If equal to hardware default value, it means TCON bin do not write this value, software should write this value instead.
        W2BYTEMSK(REG_0048_OD_1ST_BKA336_V004,OVERDRIVE_ACTIVE_THRESHOLD,REG_0048_OD_1ST_BKA336_V004_REG_OD_ACT_THRD_0048); //OD Active threshold
    }


    W2BYTEMSK(REG_00BC_OD_1ST_BKA336_V004, u16hsize, REG_00BC_OD_1ST_BKA336_V004_REG_VDE_H_SIZE_00BC); // OD horizontal size of a frame
#if (OVERDRIVE_ENABLE_RGBW == TRUE)
    if(MHal_PNL_OverDriver_IsEnableRGBW())
    {
        W2BYTEMSK(REG_01BC_OD_1ST_BKA336_V004, ((u16hsize*OVERDRIVE_RGB_CHANNEL)/OVERDRIVE_RGBW_CHANNEL), REG_01BC_OD_1ST_BKA336_V004_REG_H_SIZE_01BC); //set reg_htotal*3/4
    }
    else
#endif
    {
        W2BYTEMSK(REG_01BC_OD_1ST_BKA336_V004, u16hsize, REG_01BC_OD_1ST_BKA336_V004_REG_H_SIZE_01BC); //set reg_htotal
    }

    phypg_addr_limit = ((u16hsize*u16vsize)*OVERDRIVE_MODE*OVERDRIVE_EXTRA_MEM_SIZE_FACTOR)/(10*OVERDRIVE_MIU_BUS*OVERDRIVE_PG_ENTRY_PRE_REQ*OVERDRIVE_PG_LENGTH);//254,128,64

    phydram_addr_offset = (phypg_addr_limit+1)*OVERDRIVE_PG_ENTRY_PRE_REQ*OVERDRIVE_PG_LENGTH;

    debug("[%s][%5d]pg_addr_limit=%td dram_addr_offset=%td \n", __FUNCTION__, __LINE__,(ptrdiff_t)phypg_addr_limit,(ptrdiff_t)phydram_addr_offset);

    u64OD_MSB_limit = u64OD_MSB_Addr + phydram_addr_offset + phypg_addr_limit;

    W2BYTEMSK(REG_005C_OD_1ST_BKA336_V004, (u16)(u64OD_MSB_limit & 0xFFFF), Fld(16,0,AC_FULLW10)); // OD MSB request address limit
    W2BYTEMSK(REG_0060_OD_1ST_BKA336_V004, (u16)((u64OD_MSB_limit >> 16) & 0xFFFF), REG_0060_OD_1ST_BKA336_V004_REG_OD_ADR_LIMIT_1_0060); // OD MSB request address limit

    phypg_adde_base = u64OD_MSB_Addr + phydram_addr_offset;


    W2BYTEMSK(REG_011C_OD_1ST_BKA336_V004, (u16)(phypg_adde_base & 0xFFFF), Fld(16,0,AC_FULLW10)); // OD PG Base request base address
    W2BYTEMSK(REG_0120_OD_1ST_BKA336_V004, (u16)((phypg_adde_base >> 16) & 0xFFFF), REG_0120_OD_1ST_BKA336_V004_REG_PG_BASE_ADR_1_0120); //OD PG Base request base address
    W2BYTEMSK(REG_009C_OD_1ST_BKA336_V004,phypg_addr_limit,REG_009C_OD_1ST_BKA336_V004_REG_PG_ADR_LIMIT_009C); //OD PG Address Limit
    W2BYTEMSK(REG_009C_OD_1ST_BKA336_V004,1,REG_009C_OD_1ST_BKA336_V004_REG_PG_LIMIT_EN_009C); //OD PG Address Limit Enable

    //SC_W2BYTE(REG_SC_BK16_6F_L,0x0F00);//for merlin definition different
    // Need Check
    //SC_W2BYTE(REG_SC_BK16_29_L,0x0F);
    //SC_W2BYTEMSK(REG_SC_BK16_29_L,BIT(8)|BIT(9)|BIT(10)|BIT(11),BIT(8)|BIT(9)|BIT(10)|BIT(11)); //OD one index containts

    W2BYTEMSK(REG_0064_OD_1ST_BKA336_V004,0x10, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0068_OD_1ST_BKA336_V004,0x3F, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0068_OD_1ST_BKA336_V004,0x00, Fld(8,8,AC_FULLB1));
    W2BYTEMSK(REG_006C_OD_1ST_BKA336_V004,0x0A, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0070_OD_1ST_BKA336_V004,0x3F, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0070_OD_1ST_BKA336_V004,0x00, Fld(8,8,AC_FULLB1));
    W2BYTEMSK(REG_00A0_OD_1ST_BKA336_V004,0x3F, REG_00A0_OD_1ST_BKA336_V004_REG_ARB_WACK_LENGTH_00A0);

    W2BYTEMSK(REG_0064_OD_1ST_BKA336_V004, 1,REG_0064_OD_1ST_BKA336_V004_REG_OD_RREQ_BREAK_MODE_0064);

#ifdef STELLAR
    if((SC_R2BYTEMSK(REG_SC_BKF2_73_L,0xF0) >> 4) == 5) //M+
    {
        W2BYTEMSK(REG_0154_OD_1ST_BKA336_V004,0x2,REG_0154_OD_1ST_BKA336_V004_REG_VFEND_DELAY_0154);
    }
    else if((SC_R2BYTEMSK(REG_SC_BKF2_73_L,0xF0) >> 4) == 8) //SiW RGBW
    {
        W2BYTEMSK(REG_0154_OD_1ST_BKA336_V004,0x1,REG_0154_OD_1ST_BKA336_V004_REG_VFEND_DELAY_0154);
    }
    else
#endif
    {
        W2BYTEMSK(REG_0154_OD_1ST_BKA336_V004,0,REG_0154_OD_1ST_BKA336_V004_REG_VFEND_DELAY_0154);
    }

    W2BYTEMSK(REG_00C8_OD_1ST_BKA336_V004,0,REG_00C8_OD_1ST_BKA336_V004_REG_LN_RATE_CTRL_EN_ODW_00C8);
    W2BYTEMSK(REG_00C8_OD_1ST_BKA336_V004,0,REG_00C8_OD_1ST_BKA336_V004_REG_LN_RATE_CTRL_EN_ODR_00C8);

    if((R2BYTEMSK(REG_00E8_OD_1ST_BKA336_V004,Fld(6,8,AC_MSKB1))) == OVERDRIVE_STRENGTH_SLOP_DEFAULT)
    {
        // If equal to hardware default value, it means TCON bin do not write this value, software should write this value instead.
        W2BYTEMSK(REG_00E8_OD_1ST_BKA336_V004,0x2EFF, Fld(16,0,AC_FULLW10));
    }
    W2BYTEMSK(REG_00D8_OD_1ST_BKA336_V004,0x0007, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_00E4_OD_1ST_BKA336_V004,0xFFFF, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_00F0_OD_1ST_BKA336_V004,0xFF,REG_00F0_OD_1ST_BKA336_V004_REG_OD_RADR_MAX_LIMIT_1_00F0);
    W2BYTEMSK(REG_00EC_OD_1ST_BKA336_V004,0xFFFF, Fld(16,0,AC_FULLW10));

    //OD setting
    W2BYTEMSK(REG_0080_OD_1ST_BKA336_V004,1,REG_0080_OD_1ST_BKA336_V004_REG_REQ_STATE_JUMP_SEL_0080);//od request vsync reset wait all request end enable,RD suggest for prevent miu lock problem

    //random_active_threshold
    W2BYTEMSK(REG_0020_OD_2ND_BKA337_V004,0x0302, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0024_OD_2ND_BKA337_V004,0x0905, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0028_OD_2ND_BKA337_V004,0x0302, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_002C_OD_2ND_BKA337_V004,0x0905, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0030_OD_2ND_BKA337_V004,0x0302, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0034_OD_2ND_BKA337_V004,0x0905, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0038_OD_2ND_BKA337_V004,1,REG_0038_OD_2ND_BKA337_V004_REG_RANDOM_ACT_THRD_EN_0038);

    //compression setting
    W2BYTEMSK(REG_0084_OD_1ST_BKA336_V004,0x1218, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0088_OD_1ST_BKA336_V004,0x060C, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_008C_OD_1ST_BKA336_V004,0x1417, Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0090_OD_1ST_BKA336_V004,0x8E11, Fld(16,0,AC_FULLW10));

    //compression decode round disable
W2BYTEMSK(REG_01B8_OD_1ST_BKA336_V004, 0, REG_01B8_OD_1ST_BKA336_V004_REG_DEC_ROUND_EN_01B8);

#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
    if(MHal_PNL_OverDriver_IsEnableRGBW())
    {
        W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004,0xE4,0x0FFF);//ch_loc_w,ch_loc_b,ch_loc_g,ch_loc_r
    }
#endif
#endif
}

void MHal_PNL_OverDriver_Enable(bool bEnable)
{
#if SUPPORT_OVERDRIVE
    u16 u16Taget_BR =0; //Target bit rate

    // OD mode
    // OD used user weight to output blending directly
    // OD Enable
    if (bEnable)
    {
         u16Taget_BR = (OVERDRIVE_MODE*64)+3;//Formula = 64*bits_per_pixel + 3
        //Target bit rate of compression engine output for 4 bit compression
        W2BYTEMSK( REG_00B4_OD_1ST_BKA336_V004, u16Taget_BR,REG_00B4_OD_1ST_BKA336_V004_REG_TARGET_BR_00B4);
        TCON_W2BYTEMSK( REG_0040_OD_1ST_BKA336_V004>>1, 0xB,0xF); //compression mode
#if (OVERDRIVE_ENABLE_RGBW == TRUE)
        if(MHal_PNL_OverDriver_IsEnableRGBW())//not support w channel
        {
            W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004,0x1,REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);//RGBW input Enable
        }
#endif
        if((OVERDRIVE_ENABLE_VSCALING == TRUE) || (OVERDRIVE_ENABLE_HSCALING == TRUE))
        {
            if((OVERDRIVE_ENABLE_VSCALING == TRUE) && (OVERDRIVE_ENABLE_HSCALING == TRUE)) //both need VScaling & HScaling
            {
                W2BYTEMSK(REG_01B0_OD_1ST_BKA336_V004,0x3,Fld(2,0,AC_MSKB0));//Enable VScaling HScaling together

            }
            else if(OVERDRIVE_ENABLE_VSCALING == TRUE) //only VScaling
            {
                W2BYTEMSK(REG_01B0_OD_1ST_BKA336_V004,1,REG_01B0_OD_1ST_BKA336_V004_REG_ENABLE_VSCALING_01B0);//Enable VScaling
            }
            else //only HScaling
            {
                W2BYTEMSK(REG_01B0_OD_1ST_BKA336_V004,1,REG_01B0_OD_1ST_BKA336_V004_REG_ENABLE_HSCALING_01B0);//Enable HScaling
            }
        }
#if OVERDRIVE_ENABLE_VAC_HSCALING
        MHal_PNL_OverDriver_VAC_HScaling_Setting();
#endif
    }
    else
    {
        W2BYTEMSK( REG_0040_OD_1ST_BKA336_V004, 0x0,  REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040);//RGB 444mode
    }

#endif
}

void MHal_PNL_OverDriver_TBL(u8 u8ODTbl[1056])
{
#if SUPPORT_OVERDRIVE
    u16 i;
    u8 u8target;
    bool bEnable;
    u16 u16Timeout = 0;

    bEnable = R2BYTEMSK( REG_0040_OD_1ST_BKA336_V004, REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040);
    W2BYTEMSK(REG_0040_OD_1ST_BKA336_V004, 0x00, REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040); //OD enable
    W2BYTEMSK(REG_0004_OD_1ST_BKA336_V004, 0x0E, Fld(3, 1, AC_MSKB0)); //OD table SRAM enable, RGB channel

    u8target= u8ODTbl[9];
    for (i=0; i<272; i++)
    {
        TCON_W2BYTEMSK( REG_000C_OD_1ST_BKA336_V004>>1, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
        TCON_W2BYTEMSK( REG_0008_OD_1ST_BKA336_V004>>1, (i|0x8000), 0x81FF);
        while(R2BYTEMSK( REG_0008_OD_1ST_BKA336_V004, REG_0008_OD_1ST_BKA336_V004_REG_OD_SRAM1_IOWE_READ_BACK_0008) && (u16Timeout < MAX_DELAY_TIME))
        {
            mdelay(1);
            u16Timeout++;
        }
        u16Timeout = 0;
    }

    u8target= u8ODTbl[(272+19)];
    for (i=0; i<272; i++)
    {
        TCON_W2BYTEMSK( REG_0018_OD_1ST_BKA336_V004>>1, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
        TCON_W2BYTEMSK( REG_0014_OD_1ST_BKA336_V004>>1, (i|0x8000), 0x81FF);
        while(R2BYTEMSK( REG_0014_OD_1ST_BKA336_V004, REG_0014_OD_1ST_BKA336_V004_REG_OD_SRAM2_IOWE_READ_BACK_0014) && (u16Timeout < MAX_DELAY_TIME))
        {
            mdelay(1);
            u16Timeout++;
        }
        u16Timeout = 0;
    }

    u8target= u8ODTbl[(272*2+29)];
    for (i=0; i<256; i++)
    {
        TCON_W2BYTEMSK( REG_0024_OD_1ST_BKA336_V004>>1, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
        TCON_W2BYTEMSK( REG_0020_OD_1ST_BKA336_V004>>1, (i|0x8000), 0x81FF);
        while(R2BYTEMSK( REG_0020_OD_1ST_BKA336_V004, REG_0020_OD_1ST_BKA336_V004_REG_OD_SRAM3_IOWE_READ_BACK_0020) && (u16Timeout < MAX_DELAY_TIME))
        {
            mdelay(1);
            u16Timeout++;
        }
        u16Timeout = 0;
    }

    u8target= u8ODTbl[(272*2+256+39)];
    for (i=0; i<256; i++)
    {
        TCON_W2BYTEMSK( REG_0030_OD_1ST_BKA336_V004>>1, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
        TCON_W2BYTEMSK( REG_002C_OD_1ST_BKA336_V004>>1, (i|0x8000), 0x81FF);
        while(R2BYTEMSK( REG_002C_OD_1ST_BKA336_V004, REG_002C_OD_1ST_BKA336_V004_REG_OD_SRAM4_IOWE_READ_BACK_002C) && (u16Timeout < MAX_DELAY_TIME))
        {
            mdelay(1);
            u16Timeout++;
        }
        u16Timeout = 0;
    }

    W2BYTEMSK(REG_0004_OD_1ST_BKA336_V004, 0x00, Fld(3, 1, AC_MSKB0)); //OD table SRAM enable, RGB channel
    W2BYTEMSK(REG_0040_OD_1ST_BKA336_V004, (bEnable?1:0), REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040); //OD enable
#endif
}

#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_OD_AUTODOWNLOAD == TRUE)
bool MHal_PNL_OverDriver_ADL_Init(struct udevice *dev, u32 u32ADLSize)
{
    bool bRet = TRUE;
    struct mtk_panel_priv *priv = dev_get_priv(dev);
    if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return FALSE;
	}
    if ((priv->pnl_lib_version == VERSION5) || (priv->pnl_lib_version == VERSION6)) {
		//adl index user mode en have to be set 1 when boot time
		W2BYTEMSK(REG_0084_SCTCON_MISC_BKA3E0_V005, 0x1, REG_0084_SCTCON_MISC_BKA3E0_V005_REG_ADL_IDX_OD_SEL_0084);
    }

    //Always use new mode, support write independent R/G/B/W tables
    W2BYTEMSK(REG_0004_OD_1ST_BKA336_V004, 1, REG_0004_OD_1ST_BKA336_V004_REG_AUTO_TABLE_LOAD_EN_0004);//[8]:reg_auto_table_load_en
    W2BYTEMSK(REG_0004_OD_1ST_BKA336_V004, 1, REG_0004_OD_1ST_BKA336_V004_REG_OD_AUTODL_TRIG_EN_0004);//[10]:reg_od_autodl_trig_en
    W2BYTEMSK(REG_01D4_OD_1ST_BKA336_V004, 0, REG_01D4_OD_1ST_BKA336_V004_REG_ADL_TRIG_SEL_01D4); //reg_adl_trig_sel
    W2BYTEMSK(REG_010C_OD_2ND_BKA337_V004, 1, REG_010C_OD_2ND_BKA337_V004_REG_AUTO_TABLE_MODE_010C);
    PNL_MALLOC_MEM(g_pstOD_ADL_CMD, u32ADLSize, bRet);
    if (bRet == FALSE) {
		debug("[%s][%d] OD Autodownload allocate mem fail\n", __FUNCTION__, __LINE__);
		PNL_FREE_MEM(g_pstOD_ADL_CMD);
		return FALSE;
    }

    memset(g_pstOD_ADL_CMD, 0, u32ADLSize);
    bRet = R2BYTEMSK(REG_0040_OD_1ST_BKA336_V004, REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040);
    W2BYTEMSK(REG_0040_OD_1ST_BKA336_V004, 0x00, REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040); //OD enable
    return bRet;
}

void _mdrv_pnl_over_driver_adl_decrypt_od_table(u16 *pu16ODTbl,
	u8 *pu8OD_SRAM1,
	u8 *pu8OD_SRAM2,
	u8 *pu8OD_SRAM3,
	u8 *pu8OD_SRAM4)
{
	u16 u16CodeTableIndex = 0;
	u16 u16CodeCurrentTableIndex = 0;
	u16 u16TargetIndex = 0;
	u16 u16Target = 0;

	//Decrypt OD table.
	u16TargetIndex = OD_DECRYPTION_IDX_1;
	u16Target = pu16ODTbl[u16TargetIndex];
	for (u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM1_SIZE; u16CodeTableIndex++) {
		if (u16CodeTableIndex == u16TargetIndex) {
			pu8OD_SRAM1[u16CodeTableIndex] = (u8)u16Target;
		} else {
			pu8OD_SRAM1[u16CodeTableIndex] = (u8)(pu16ODTbl[u16CodeTableIndex]^u16Target);
		}
	}

	u16CodeCurrentTableIndex += OVERDRIVER_SRAM1_SIZE;
	u16TargetIndex += OD_DECRYPTION_IDX_2;
	u16Target = pu16ODTbl[(u16CodeCurrentTableIndex+u16TargetIndex)];
	for (u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM2_SIZE; u16CodeTableIndex++) {
		if (u16CodeTableIndex == u16TargetIndex) {
			pu8OD_SRAM2[u16CodeTableIndex] = (u8)u16Target;
		} else {
			pu8OD_SRAM2[u16CodeTableIndex] = (u8)(pu16ODTbl[(u16CodeCurrentTableIndex+u16CodeTableIndex)]^u16Target);
		}
	}

	u16CodeCurrentTableIndex += OVERDRIVER_SRAM2_SIZE;
	u16TargetIndex += OD_DECRYPTION_IDX_2;
	u16Target = pu16ODTbl[(u16CodeCurrentTableIndex+u16TargetIndex)];
	for (u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM3_SIZE; u16CodeTableIndex++) {
		if (u16CodeTableIndex == u16TargetIndex) {
			pu8OD_SRAM3[u16CodeTableIndex] = (u8)u16Target;
		} else {
			pu8OD_SRAM3[u16CodeTableIndex] = (u8)(pu16ODTbl[(u16CodeCurrentTableIndex+u16CodeTableIndex)]^u16Target);
		}
	}

	u16CodeCurrentTableIndex += OVERDRIVER_SRAM3_SIZE;
	u16TargetIndex += OD_DECRYPTION_IDX_2;
	u16Target = pu16ODTbl[(u16CodeCurrentTableIndex+u16TargetIndex)];
	for (u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM4_SIZE; u16CodeTableIndex++) {
		if (u16CodeTableIndex == u16TargetIndex) {
			pu8OD_SRAM4[u16CodeTableIndex] = (u8)u16Target;
		} else {
			pu8OD_SRAM4[u16CodeTableIndex] = (u8)(pu16ODTbl[(u16CodeCurrentTableIndex+u16CodeTableIndex)]^u16Target);
		}
	}
}

void _mdrv_pnl_over_driver_adl_setting_sram1(u16 u16CodeTableIndex,
	u16 u16SepatateMode,
	u8 *pu8OD_SRAM)
{
	if (u16CodeTableIndex < OVERDRIVER_SRAM1_SIZE) {
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32Table_WriteAddr = u16CodeTableIndex;
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_B_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_B_WriteEn = (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_B_ENABLE)>>1;
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B1 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_G_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_G_WriteEn = (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_G_ENABLE)>>2;
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G1 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_R_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_R_WriteEn = (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_R_ENABLE)>>3;
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R1 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_W_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_W_WriteEn = u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_W_ENABLE;
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W1 = pu8OD_SRAM[u16CodeTableIndex];
		}
	} else {
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B1 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G1 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R1 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W1 = 0;
	}
}

void _mdrv_pnl_over_driver_adl_setting_sram2(u16 u16CodeTableIndex,
	u16 u16SepatateMode,
	u8 *pu8OD_SRAM)
{
	if (u16CodeTableIndex < OVERDRIVER_SRAM2_SIZE) {
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_B_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B2 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_G_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G2 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_R_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R2 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_W_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W2 = pu8OD_SRAM[u16CodeTableIndex];
		}
	} else {
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B2 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G2 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R2 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W2 = 0;
	}
}

void _mdrv_pnl_over_driver_adl_setting_sram3(u16 u16CodeTableIndex,
	u16 u16SepatateMode,
	u8 *pu8OD_SRAM)
{
	if (u16CodeTableIndex < OVERDRIVER_SRAM3_SIZE) {
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_B_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B3 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_G_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G3 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_R_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R3 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_W_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W3 = pu8OD_SRAM[u16CodeTableIndex];
		}
	} else {
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B3 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G3 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R3 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W3 = 0;
	}
}

void _mdrv_pnl_over_driver_adl_setting_sram4(u16 u16CodeTableIndex,
	u16 u16SepatateMode,
	u8 *pu8OD_SRAM)
{
	if (u16CodeTableIndex < OVERDRIVER_SRAM4_SIZE) {
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_B_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B4 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_G_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G4 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_R_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R4 = pu8OD_SRAM[u16CodeTableIndex];
		}
		if (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_W_ENABLE) {
			g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W4 = pu8OD_SRAM[u16CodeTableIndex];
		}
	} else {
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B4 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G4 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R4 = 0;
		g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W4 = 0;
	}
}

void MHal_PNL_OverDriver_ADL_Setting_TBL(u16 *pu16ODTbl, u16 u16SepatateMode)
{
    if (!pu16ODTbl || !g_pstOD_ADL_CMD) {
		return;
    }
    u16 u16CodeTableIndex = 0;
    u8 *pu8OD_SRAM1 = NULL;
    u8 *pu8OD_SRAM2 = NULL;
    u8 *pu8OD_SRAM3 = NULL;
    u8 *pu8OD_SRAM4 = NULL;
    bool bRet = TRUE;

    PNL_MALLOC_MEM(pu8OD_SRAM1, OVERDRIVER_SRAM1_SIZE, bRet);
    PNL_MALLOC_MEM(pu8OD_SRAM2, OVERDRIVER_SRAM2_SIZE, bRet);
    PNL_MALLOC_MEM(pu8OD_SRAM3, OVERDRIVER_SRAM3_SIZE, bRet);
    PNL_MALLOC_MEM(pu8OD_SRAM4, OVERDRIVER_SRAM4_SIZE, bRet);
    if (bRet != TRUE) {
		PNL_FREE_MEM(pu8OD_SRAM1);
		PNL_FREE_MEM(pu8OD_SRAM2);
		PNL_FREE_MEM(pu8OD_SRAM3);
		PNL_FREE_MEM(pu8OD_SRAM4);
		UBOOT_ERROR("Error: malloc od sram failed\n");
		return;
    }

    if (pu8OD_SRAM1 != NULL && pu8OD_SRAM2 != NULL && pu8OD_SRAM3 != NULL && pu8OD_SRAM4 != NULL) {
		_mdrv_pnl_over_driver_adl_decrypt_od_table(pu16ODTbl, pu8OD_SRAM1, pu8OD_SRAM2, pu8OD_SRAM3, pu8OD_SRAM4);

#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
		if (MHal_PNL_OverDriver_IsEnableRGBW()) {
			if (R2BYTEMSK(L_BK_LPLL(0x03), BIT(5)) != 0) {
				MHal_PNL_PowerDownLPLL(FALSE);
			}
			//Disable Overdriver RGBW to prevent write od table fail
			W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004, 0x00, REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);
		}
#endif
		for (u16CodeTableIndex = 0; u16CodeTableIndex < XC_AUTODOWNLOAD_OVERDRIVER_DEPTH; u16CodeTableIndex++) {
			_mdrv_pnl_over_driver_adl_setting_sram1(u16CodeTableIndex, u16SepatateMode, pu8OD_SRAM1);
			_mdrv_pnl_over_driver_adl_setting_sram2(u16CodeTableIndex, u16SepatateMode, pu8OD_SRAM2);
			_mdrv_pnl_over_driver_adl_setting_sram3(u16CodeTableIndex, u16SepatateMode, pu8OD_SRAM3);
			_mdrv_pnl_over_driver_adl_setting_sram4(u16CodeTableIndex, u16SepatateMode, pu8OD_SRAM4);
		}

#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
		if (MHal_PNL_OverDriver_IsEnableRGBW()) {
			if (R2BYTEMSK(L_BK_LPLL(0x03), BIT(5)) != 0) {
				MHal_PNL_PowerDownLPLL(FALSE);
			}
			W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004, bEnable, REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);
		}
#endif
	}

    PNL_FREE_MEM(pu8OD_SRAM1);
    PNL_FREE_MEM(pu8OD_SRAM2);
    PNL_FREE_MEM(pu8OD_SRAM3);
    PNL_FREE_MEM(pu8OD_SRAM4);
}

void MHal_PNL_OverDriver_ADL_Fire(u32 u32ADLSize, bool bEnableOD)
{
    if (!g_pstOD_ADL_CMD) {
		return;
    }

    if (KHal_XC_WriteAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_OD, (u8 *)g_pstOD_ADL_CMD, u32ADLSize, NULL) != TRUE) {
		UBOOT_ERROR("[%s]OD, Write ADL Fail!!! \n", __FUNCTION__);
    }

    if (KHal_XC_FireAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_OD) != TRUE) {
		UBOOT_ERROR("[%s]OD, FIRE ADL Fail!!! \n", __FUNCTION__);
    }

    PNL_FREE_MEM(g_pstOD_ADL_CMD);
    W2BYTEMSK(REG_0040_OD_1ST_BKA336_V004, (bEnableOD?1:0), REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040); //OD enable
}
#endif

void MHal_PNL_OverDriver_Setting_TBL(u16 *pu16ODTbl, u32 u32ODTabSize, u16 u16SepatateMode)
{
#if SUPPORT_OVERDRIVE
    if(!pu16ODTbl)
    {
        return;
    }
    u16 u16CodeTableIndex = 0;
    u16 u16CodeCurrentTableIndex = 0;
    u16 u16TargetIndex = 0;
    u16 u16Target = 0;
    bool bEnable = FALSE;
    u8* pu8OD_SRAM1 = NULL;
    u8* pu8OD_SRAM2 = NULL;
    u8* pu8OD_SRAM3 = NULL;
    u8* pu8OD_SRAM4 = NULL;
    bool bRet = TRUE;
    u32 u32Size = XC_AUTODOWNLOAD_OVERDRIVER_DEPTH*BYTE_PER_WORD;

    PNL_MALLOC_MEM(pu8OD_SRAM1, OVERDRIVER_SRAM1_SIZE, bRet);
    PNL_MALLOC_MEM(pu8OD_SRAM2, OVERDRIVER_SRAM2_SIZE, bRet);
    PNL_MALLOC_MEM(pu8OD_SRAM3, OVERDRIVER_SRAM3_SIZE, bRet);
    PNL_MALLOC_MEM(pu8OD_SRAM4, OVERDRIVER_SRAM4_SIZE, bRet);
    if(bRet != TRUE)
    {
        PNL_FREE_MEM(pu8OD_SRAM1);
        PNL_FREE_MEM(pu8OD_SRAM2);
        PNL_FREE_MEM(pu8OD_SRAM3);
        PNL_FREE_MEM(pu8OD_SRAM4);
        UBOOT_ERROR("Error: malloc od sram failed\n");
        return;
    }

    if(pu8OD_SRAM1 != NULL && pu8OD_SRAM2 != NULL && pu8OD_SRAM3 != NULL && pu8OD_SRAM4 != NULL)
    {
        //Decrypt OD table.
        u16TargetIndex = OD_DECRYPTION_IDX_1;
        u16Target = pu16ODTbl[u16TargetIndex];
        for(u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM1_SIZE; u16CodeTableIndex++)
        {
            if(u16CodeTableIndex == u16TargetIndex)
            {
                pu8OD_SRAM1[u16CodeTableIndex] = (u8)u16Target;
            }
            else
            {
                pu8OD_SRAM1[u16CodeTableIndex] = (u8)(pu16ODTbl[u16CodeTableIndex]^u16Target);
            }
        }

        u16CodeCurrentTableIndex += OVERDRIVER_SRAM1_SIZE;
        u16TargetIndex += OD_DECRYPTION_IDX_2;
        u16Target = pu16ODTbl[(u16CodeCurrentTableIndex+u16TargetIndex)];
        for(u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM2_SIZE; u16CodeTableIndex++)
        {
            if(u16CodeTableIndex == u16TargetIndex)
            {
                pu8OD_SRAM2[u16CodeTableIndex] = (u8)u16Target;
            }
            else
            {
                pu8OD_SRAM2[u16CodeTableIndex] = (u8)(pu16ODTbl[(u16CodeCurrentTableIndex+u16CodeTableIndex)]^u16Target);
            }
        }

        u16CodeCurrentTableIndex += OVERDRIVER_SRAM2_SIZE;
        u16TargetIndex += OD_DECRYPTION_IDX_2;
        u16Target = pu16ODTbl[(u16CodeCurrentTableIndex+u16TargetIndex)];
        for(u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM3_SIZE; u16CodeTableIndex++)
        {
            if(u16CodeTableIndex == u16TargetIndex)
            {
                pu8OD_SRAM3[u16CodeTableIndex] = (u8)u16Target;
            }
            else
            {
                pu8OD_SRAM3[u16CodeTableIndex] = (u8)(pu16ODTbl[(u16CodeCurrentTableIndex+u16CodeTableIndex)]^u16Target);
            }
        }

        u16CodeCurrentTableIndex += OVERDRIVER_SRAM3_SIZE;
        u16TargetIndex += OD_DECRYPTION_IDX_2;
        u16Target = pu16ODTbl[(u16CodeCurrentTableIndex+u16TargetIndex)];
        for(u16CodeTableIndex = 0; u16CodeTableIndex < OVERDRIVER_SRAM4_SIZE; u16CodeTableIndex++)
        {
            if(u16CodeTableIndex == u16TargetIndex)
            {
                pu8OD_SRAM4[u16CodeTableIndex] = (u8)u16Target;
            }
            else
            {
                pu8OD_SRAM4[u16CodeTableIndex] = (u8)(pu16ODTbl[(u16CodeCurrentTableIndex+u16CodeTableIndex)]^u16Target);
            }
        }

        bEnable = R2BYTEMSK( REG_0040_OD_1ST_BKA336_V004, REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040);
        W2BYTEMSK( REG_0040_OD_1ST_BKA336_V004, 0x00, REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040); // OD enable
#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
        if(MHal_PNL_OverDriver_IsEnableRGBW())
        {
            if(R2BYTEMSK(L_BK_LPLL(0x03),BIT(5))!= 0)
            {
                MHal_PNL_PowerDownLPLL(FALSE);
            }
            //Disable Overdriver RGBW to prevent write od table fail
            W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004,0x00,REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);
        }
#endif
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_OD_AUTODOWNLOAD == TRUE)
        //Always use new mode, support write independent R/G/B/W tables
        W2BYTEMSK(REG_0004_OD_1ST_BKA336_V004,1,REG_0004_OD_1ST_BKA336_V004_REG_AUTO_TABLE_LOAD_EN_0004);//[8]:reg_auto_table_load_en
        W2BYTEMSK(REG_0004_OD_1ST_BKA336_V004,1,REG_0004_OD_1ST_BKA336_V004_REG_OD_AUTODL_TRIG_EN_0004);//[10]:reg_od_autodl_trig_en
        W2BYTEMSK( REG_01D4_OD_1ST_BKA336_V004, 0, REG_01D4_OD_1ST_BKA336_V004_REG_ADL_TRIG_SEL_01D4); //reg_adl_trig_sel
        W2BYTEMSK( REG_010C_OD_2ND_BKA337_V004, 1, REG_010C_OD_2ND_BKA337_V004_REG_AUTO_TABLE_MODE_010C);
        PNL_MALLOC_MEM(g_pstOD_ADL_CMD,u32Size,bRet);
        if(bRet == FALSE)
        {
            debug("[%s][%d] OD Autodownload allocate mem fail\n",__FUNCTION__,__LINE__);
            PNL_FREE_MEM(g_pstOD_ADL_CMD);
            PNL_FREE_MEM(pu8OD_SRAM1);
            PNL_FREE_MEM(pu8OD_SRAM2);
            PNL_FREE_MEM(pu8OD_SRAM3);
            PNL_FREE_MEM(pu8OD_SRAM4);
            return;
        }

        memset(g_pstOD_ADL_CMD, 0, u32Size);

        for(u16CodeTableIndex = 0; u16CodeTableIndex < XC_AUTODOWNLOAD_OVERDRIVER_DEPTH; u16CodeTableIndex++)
        {
            if(u16CodeTableIndex < OVERDRIVER_SRAM1_SIZE)
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B1 = pu8OD_SRAM1[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G1 = pu8OD_SRAM1[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R1 = pu8OD_SRAM1[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W1 = pu8OD_SRAM1[u16CodeTableIndex];

                g_pstOD_ADL_CMD[u16CodeTableIndex].u32Table_WriteAddr = u16CodeTableIndex;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_B_WriteEn = (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_B_ENABLE)>>1;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_G_WriteEn = (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_G_ENABLE)>>2;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_R_WriteEn = (u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_R_ENABLE)>>3;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32OD_W_WriteEn = u16SepatateMode & E_PNL_OVERDRIVER_SEPARATE_W_ENABLE;
            }
            else
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B1 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G1 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R1 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W1 = 0;
            }

            if(u16CodeTableIndex < OVERDRIVER_SRAM2_SIZE)
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B2 =  pu8OD_SRAM2[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G2 =  pu8OD_SRAM2[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R2 =  pu8OD_SRAM2[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W2 =  pu8OD_SRAM2[u16CodeTableIndex];
            }
            else
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B2 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G2 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R2 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W2 = 0;
            }

            if(u16CodeTableIndex < OVERDRIVER_SRAM3_SIZE)
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B3 =  pu8OD_SRAM3[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G3 =  pu8OD_SRAM3[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R3 =  pu8OD_SRAM3[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W3 =  pu8OD_SRAM3[u16CodeTableIndex];
            }
            else
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B3 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G3 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R3 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W3 = 0;
            }

            if(u16CodeTableIndex < OVERDRIVER_SRAM4_SIZE)
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B4 =  pu8OD_SRAM4[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G4 =  pu8OD_SRAM4[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R4 =  pu8OD_SRAM4[u16CodeTableIndex];
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W4 =  pu8OD_SRAM4[u16CodeTableIndex];
            }
            else
            {
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_B4 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_G4 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_R4 = 0;
                g_pstOD_ADL_CMD[u16CodeTableIndex].u32SRAM_W4 = 0;
            }
        }

        if(KHal_XC_WriteAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_OD, (u8 *)read_storage_file_to_memory, u32Size, NULL) != TRUE)
        {
            UBOOT_ERROR("[%s]OD, Write ADL Fail!!! \n", __FUNCTION__);
        }

        if(KHal_XC_FireAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_OD)!= TRUE)
        {
            UBOOT_ERROR("[%s]OD, FIRE ADL Fail!!! \n", __FUNCTION__);
        }

        PNL_FREE_MEM(g_pstOD_ADL_CMD);

#else
        TCON_W2BYTEMSK( REG_0004_OD_1ST_BKA336_V004>>1, u16SepatateMode, 0x0F); // OD table SRAM enable, RGBW channel

        for(u16CodeTableIndex=0;u16CodeTableIndex<OVERDRIVER_SRAM1_SIZE;u16CodeTableIndex++)
        {
            TCON_W2BYTEMSK( REG_000C_OD_1ST_BKA336_V004>>1, pu8OD_SRAM1[u16CodeTableIndex], 0x00FF);
            TCON_W2BYTEMSK( REG_0008_OD_1ST_BKA336_V004>>1, (u16CodeTableIndex|0x8000), 0x81FF);
            while(R2BYTEMSK( REG_0008_OD_1ST_BKA336_V004, REG_0008_OD_1ST_BKA336_V004_REG_OD_SRAM1_IOWE_READ_BACK_0008));
        }

        for (u16CodeTableIndex=0; u16CodeTableIndex<OVERDRIVER_SRAM2_SIZE; u16CodeTableIndex++)
        {
            TCON_W2BYTEMSK( REG_0018_OD_1ST_BKA336_V004>>1, pu8OD_SRAM2[u16CodeTableIndex], 0x00FF);
            TCON_W2BYTEMSK( REG_0014_OD_1ST_BKA336_V004>>1, (u16CodeTableIndex|0x8000), 0x81FF);
            while(R2BYTEMSK( REG_0014_OD_1ST_BKA336_V004, REG_0014_OD_1ST_BKA336_V004_REG_OD_SRAM2_IOWE_READ_BACK_0014));
        }

        for (u16CodeTableIndex=0; u16CodeTableIndex<OVERDRIVER_SRAM3_SIZE; u16CodeTableIndex++)
        {
            TCON_W2BYTEMSK( REG_0024_OD_1ST_BKA336_V004>>1, pu8OD_SRAM3[u16CodeTableIndex], 0x00FF);
            TCON_W2BYTEMSK( REG_0020_OD_1ST_BKA336_V004>>1, (u16CodeTableIndex|0x8000), 0x81FF);
            while(R2BYTEMSK( REG_0020_OD_1ST_BKA336_V004, REG_0020_OD_1ST_BKA336_V004_REG_OD_SRAM3_IOWE_READ_BACK_0020));
        }

        for (u16CodeTableIndex=0; u16CodeTableIndex<OVERDRIVER_SRAM4_SIZE; u16CodeTableIndex++)
        {
            TCON_W2BYTEMSK( REG_0030_OD_1ST_BKA336_V004>>1, pu8OD_SRAM4[u16CodeTableIndex], 0x00FF);
            TCON_W2BYTEMSK( REG_002C_OD_1ST_BKA336_V004>>1, (u16CodeTableIndex|0x8000), 0x81FF);
            while(R2BYTEMSK( REG_002C_OD_1ST_BKA336_V004, REG_002C_OD_1ST_BKA336_V004_REG_OD_SRAM4_IOWE_READ_BACK_002C));
        }

        TCON_W2BYTEMSK( REG_0004_OD_1ST_BKA336_V004>>1, 0x00, 0x0F); // OD table SRAM enable, RGBW channel
#endif
#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
        if(MHal_PNL_OverDriver_IsEnableRGBW())
        {
            if(R2BYTEMSK(L_BK_LPLL(0x03),BIT(5))!= 0)
            {
                MHal_PNL_PowerDownLPLL(FALSE);
            }
            W2BYTEMSK(REG_01DC_OD_1ST_BKA336_V004,bEnable,REG_01DC_OD_1ST_BKA336_V004_REG_OD_RGBW_EN_01DC);
        }
#endif
        W2BYTEMSK( REG_0040_OD_1ST_BKA336_V004, (bEnable?1:0), REG_0040_OD_1ST_BKA336_V004_REG_OD_EN_0040); // OD enable
    }

    PNL_FREE_MEM(pu8OD_SRAM1);
    PNL_FREE_MEM(pu8OD_SRAM2);
    PNL_FREE_MEM(pu8OD_SRAM3);
    PNL_FREE_MEM(pu8OD_SRAM4);
#endif
}

void MDRv_PNL_OverDriver_Init(struct udevice *dev, u64 u64OD_MSB_Addr, u64 u64OD_LSB_Addr, u16 *pu16ODTbl, u32 u32ODTabSize)
{
    u64 u64OD_MSB_limit, u64OD_LSB_limit, u64Offset;
    u8 u8MIUSel = 0;
    u16 u16Width = 3840, u16Height = 2160;
    struct mtk_panel_priv *priv = dev_get_priv(dev);
    if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

    u16Width = priv->de_width;
    u16Height = priv->de_height;
	u32 pnl_version = priv->pnl_lib_version;

	KHal_XC_GetMiuOffset(pnl_version, u8MIUSel, &u64Offset);
    u64OD_MSB_Addr = u64OD_MSB_Addr - u64Offset;
    u64OD_LSB_Addr = u64OD_LSB_Addr - u64Offset;
    u64OD_MSB_Addr = (u64OD_MSB_Addr / BYTE_PER_WORD) & 0xFFFFFFFF;

#ifdef STELLAR
    u64 u64OD_PG_size = 0, u64OD_Buffer_size = 0;

#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
    if (MHal_PNL_OverDriver_IsEnableRGBW()) {
		u16Width = u16Width * OVERDRIVE_RGB_CHANNEL / OVERDRIVE_RGBW_CHANNEL;
    }
#endif
    u64OD_PG_size = (u16Width * u16Height * OVERDRIVE_MODE) / (OVERDRIVE_MIU_BUS * OVERDRIVE_PG_LENGTH * OVERDRIVE_PG_ENTRY_PRE_REQ)) + 2;
    u64OD_Buffer_size = (u64OD_PG_size * (OVERDRIVE_MIU_BUS * OVERDRIVE_PG_LENGTH * OVERDRIVE_PG_ENTRY_PRE_REQ) * 4) / 3;

    if (OVERDRIVE_ENABLE_HSCALING == TRUE) {
		u64OD_Buffer_size = u64OD_Buffer_size / 2;
    }

    u64OD_MSB_limit = u64OD_MSB_Addr + (u64OD_Buffer_size / (OVERDRIVE_PIXEL * BYTE_PER_WORD)) + ((u64OD_PG_size * OVERDRIVE_MIU_BUS) / (OVERDRIVE_PIXEL * BYTE_PER_WORD));
#else
    u64OD_MSB_limit = u64OD_MSB_Addr + (((u16Width *u16Height * 24)/(8 * BYTE_PER_WORD)) + (4096/BYTE_PER_WORD) + 16 * 40/BYTE_PER_WORD);
#endif

    u64OD_LSB_Addr = (u64OD_LSB_Addr / OD_BYTE_PER_WORD) & 0xFFFFFFFF;
    u64OD_LSB_limit = u64OD_LSB_Addr + (((u16Width *u16Height * 6)/(8 * BYTE_PER_WORD)) + 20 + 80);
    if (SUPPORT_OVERDRIVE) {
		MHal_PNL_OverDriver_Init(dev, u64OD_MSB_Addr, u64OD_MSB_limit, u64OD_LSB_Addr, u64OD_LSB_limit, u8MIUSel);
    }
}

void MDrv_PNL_OverDriver_Setting(struct udevice *dev,
	u64 u64OD_MSB_Addr, u64 u64OD_LSB_Addr, u16 *pu16ODTbl,
	u32 u32ODTabSize, u16 u16SepatateMode)
{
    u64 u64OD_MSB_limit, u64OD_LSB_limit, u64Offset;
    u8 u8MIUSel = 0;
    u16 u16Width = 3840, u16Height = 2160;
    struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (priv == NULL) {
		debug("[%s] get device private fail\n", __func__);
		return;
	}

    u16Width = priv->de_width;
    u16Height = priv->de_height;
	u32 pnl_version = priv->pnl_lib_version;

	KHal_XC_GetMiuOffset(pnl_version, u8MIUSel, &u64Offset);
    u64OD_MSB_Addr = u64OD_MSB_Addr - u64Offset;
    u64OD_LSB_Addr = u64OD_LSB_Addr - u64Offset;
    u64OD_MSB_Addr = (u64OD_MSB_Addr / BYTE_PER_WORD) & 0xFFFFFFFF;

#ifdef STELLAR
    u64 u64OD_PG_size = 0, u64OD_Buffer_size = 0;

#if (OVERDRIVE_ENABLE_RGBW == TRUE)//not support w channel
    if (MHal_PNL_OverDriver_IsEnableRGBW()) {
		u16Width = u16Width * OVERDRIVE_RGB_CHANNEL / OVERDRIVE_RGBW_CHANNEL;
    }
#endif
    u64OD_PG_size = (u16Width * u16Height * OVERDRIVE_MODE) / (OVERDRIVE_MIU_BUS * OVERDRIVE_PG_LENGTH * OVERDRIVE_PG_ENTRY_PRE_REQ)) + 2;
    u64OD_Buffer_size = (u64OD_PG_size * (OVERDRIVE_MIU_BUS * OVERDRIVE_PG_LENGTH * OVERDRIVE_PG_ENTRY_PRE_REQ) * 4) / 3;

    if (OVERDRIVE_ENABLE_HSCALING == TRUE) {
		u64OD_Buffer_size = u64OD_Buffer_size / 2;
    }

    u64OD_MSB_limit = u64OD_MSB_Addr+(u64OD_Buffer_size / (OVERDRIVE_PIXEL * BYTE_PER_WORD)) + ((u64OD_PG_size * OVERDRIVE_MIU_BUS) / (OVERDRIVE_PIXEL * BYTE_PER_WORD));
#else
    u64OD_MSB_limit = u64OD_MSB_Addr + (((u16Width *u16Height *24)/(8 * BYTE_PER_WORD)) + (4096/BYTE_PER_WORD) + 16 * 40/BYTE_PER_WORD);
#endif

    u64OD_LSB_Addr = (u64OD_LSB_Addr / OD_BYTE_PER_WORD) & 0xFFFFFFFF;
    u64OD_LSB_limit = u64OD_LSB_Addr + (((u16Width *u16Height *6)/(8 * BYTE_PER_WORD)) + 20 + 80);
    if (SUPPORT_OVERDRIVE) {
        MHal_PNL_OverDriver_Init(dev, u64OD_MSB_Addr, u64OD_MSB_limit, u64OD_LSB_Addr, u64OD_LSB_limit, u8MIUSel);
        MHal_PNL_OverDriver_Setting_TBL(pu16ODTbl,u32ODTabSize,u16SepatateMode);
    }
}

void MDrv_PNL_TCON_DumpOverDriveRegTab(struct udevice *dev, u8* pu8TconTab)
{
    debug("MDrv_PNL_TCON_DumpOverDriveRegTab\n");
    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return;
    }
    u16 u16Index = 0;

    u16* u16OverDriveTable = (u16*) malloc(sizeof(u16) * MAX_OVERDRIVER_TABLE);
    if (u16OverDriveTable==NULL)
    {
        debug("[%s] malloc error \n.", __FUNCTION__);
        return;
    }
    u64 _u32OD_MSB_Addr = 0;
    u64 _u32OD_LSB_Addr = 0;
    u32 _ODTbl_Size;
    struct dts_mmap mmap;
    int ret = 0;
    u16 u16TargetIndex = 0;
    u8 u8TConBinVersion = 0;
    bool bSupportWChannel = FALSE;
    u16 u16SepatateMode = 0;
    u8 u8RGBSeparateFlag        = (*((unsigned char*)(pu8TconTab + TCON_BIN_HEADER_BYTE_NUBMER(2)))) & BIT(0);
    u8 u8MaxODSizeFlag          = ((*((unsigned char*)(pu8TconTab + TCON_BIN_HEADER_BYTE_NUBMER(2)))) & BIT(2)) >> 2;
    u8TConBinVersion       = (*((unsigned char*)(pu8TconTab + TCON_BIN_HEADER_BYTE_NUBMER(3))));
    if(u8TConBinVersion >= TCON_BIN_VERSION_RGBW)
    {
        bSupportWChannel = ((*((unsigned char*)(pu8TconTab + TCON_BIN_HEADER_BYTE_NUBMER(2)))) & BIT(4)) >> 4;
        u16SepatateMode = E_PNL_OVERDRIVER_SEPARATE_R_ENABLE|E_PNL_OVERDRIVER_SEPARATE_G_ENABLE|E_PNL_OVERDRIVER_SEPARATE_B_ENABLE|E_PNL_OVERDRIVER_SEPARATE_W_ENABLE;
        u16TargetIndex = TCON_BIN_HEADER_BYTE_NUBMER(5);
    }
    else
    {
        u16SepatateMode = E_PNL_OVERDRIVER_SEPARATE_R_ENABLE|E_PNL_OVERDRIVER_SEPARATE_G_ENABLE|E_PNL_OVERDRIVER_SEPARATE_B_ENABLE;
        u16TargetIndex = TCON_BIN_HEADER_BYTE_NUBMER(4);
    }
    memset(&mmap, 0, sizeof(mmap));
    ret = parse_dt("/mmap_info/MI_DISP_OD_BUF",mmap_dt_parser,(void*)&mmap,"reg");
    if(ret < 0 || mmap.address == 0)
    {
        UBOOT_ERROR("Error: Get MI_DISP_OD_BUF buffer from DTS mmap failure\n");
        free(u16OverDriveTable);
        return;
    }
    else
    {
        _u32OD_MSB_Addr = mmap.address;//BA address
        _u32OD_LSB_Addr = mmap.address + mmap.size;
        debug("[%s][%d] od address = %llx, size = %llx \n", __FUNCTION__, __LINE__, mmap.address,mmap.size);
    }

    MHal_PNL_OverDriver_EnableWChannel(bSupportWChannel);

    debug("u8RGBSeparateFlag %d\n",u8RGBSeparateFlag);
    debug("u8MaxODSizeFlag %d\n",u8MaxODSizeFlag);
    debug("u8TConBinVersion %d\n",u8TConBinVersion);
    debug("bSupportWChannel %d\n",bSupportWChannel);

    if(!u8MaxODSizeFlag)
    {
        _ODTbl_Size = OVERDRIVER_TABLE_SIZE_33X32;
    }
    else
    {
        _ODTbl_Size = OVERDRIVER_TABLE_SIZE_33X33;
    }
    if(u8RGBSeparateFlag)//RGB sepatate
    {
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_OD_AUTODOWNLOAD == TRUE)
		u32 u32ADLSize = XC_AUTODOWNLOAD_OVERDRIVER_DEPTH*BYTE_PER_WORD;
		bool bEnableOD = FALSE;

		MDRv_PNL_OverDriver_Init(dev, _u32OD_MSB_Addr, _u32OD_LSB_Addr, u16OverDriveTable, _ODTbl_Size);
		bEnableOD = MHal_PNL_OverDriver_ADL_Init(dev, u32ADLSize);

		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index+u16TargetIndex];
		}
		MHal_PNL_OverDriver_ADL_Setting_TBL(u16OverDriveTable, E_PNL_OVERDRIVER_SEPARATE_R_ENABLE);

		u16TargetIndex = u16TargetIndex + u16Index;
		u16Index = 0;
		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
		}
		MHal_PNL_OverDriver_ADL_Setting_TBL(u16OverDriveTable, E_PNL_OVERDRIVER_SEPARATE_G_ENABLE);

		u16TargetIndex = u16Index + u16TargetIndex;
		u16Index = 0;
		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
		}
		MHal_PNL_OverDriver_ADL_Setting_TBL(u16OverDriveTable, E_PNL_OVERDRIVER_SEPARATE_B_ENABLE);

		if (bSupportWChannel) {
			u16TargetIndex = u16Index+u16TargetIndex;
			u16Index = 0;
			for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
				u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
			}

			MHal_PNL_OverDriver_ADL_Setting_TBL(u16OverDriveTable, E_PNL_OVERDRIVER_SEPARATE_W_ENABLE);
		}

		MHal_PNL_OverDriver_ADL_Fire(u32ADLSize, bEnableOD);
#else
		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
		}
        u16TargetIndex = u16TargetIndex + u16Index;

        MDrv_PNL_OverDriver_Setting(dev,
                                _u32OD_MSB_Addr,
                                _u32OD_LSB_Addr,
                                u16OverDriveTable,
                                _ODTbl_Size,
                                E_PNL_OVERDRIVER_SEPARATE_R_ENABLE);

        u16Index = 0;
		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
		}

        MDrv_PNL_OverDriver_Setting(dev,
                                _u32OD_MSB_Addr,
                                _u32OD_LSB_Addr,
                                u16OverDriveTable,
                                _ODTbl_Size,
                                E_PNL_OVERDRIVER_SEPARATE_G_ENABLE);

		u16TargetIndex = u16Index + u16TargetIndex;
		u16Index = 0;
		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
		}

        MDrv_PNL_OverDriver_Setting(dev,
                                _u32OD_MSB_Addr,
                                _u32OD_LSB_Addr,
                                u16OverDriveTable,
                                _ODTbl_Size,
                                E_PNL_OVERDRIVER_SEPARATE_B_ENABLE);

        if(bSupportWChannel)
        {
			u16TargetIndex = u16Index + u16TargetIndex;
			u16Index = 0;
			for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
				u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
			}

            MDrv_PNL_OverDriver_Setting(dev,
                                    _u32OD_MSB_Addr,
                                    _u32OD_LSB_Addr,
                                    u16OverDriveTable,
                                    _ODTbl_Size,
                                    E_PNL_OVERDRIVER_SEPARATE_W_ENABLE);

        }
#endif
    }
    else
    {
		for (u16Index = 0; u16Index < _ODTbl_Size; u16Index++) {
			u16OverDriveTable[u16Index] = pu8TconTab[u16Index + u16TargetIndex];
		}

        MDrv_PNL_OverDriver_Setting(dev,
                                _u32OD_MSB_Addr,
                                _u32OD_LSB_Addr,
                                u16OverDriveTable,
                                _ODTbl_Size,
                                u16SepatateMode);

    }
    free(u16OverDriveTable);
}

void MHal_PNL_PCID_Init(u8* pu8Tbl,bool bPixelOverdriveEn,bool bXTREn)
{
    W2BYTEMSK(REG_0140_DEMURA_BKA377_V004,(bPixelOverdriveEn?1:0), REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_EN_0140);
    W2BYTEMSK(REG_0140_DEMURA_BKA377_V004,(bXTREn?1:0), REG_0140_DEMURA_BKA377_V004_REG_PCID_PIXELOD_XTR_EN_0140);
    W2BYTEMSK(REG_0144_DEMURA_BKA377_V004,(pu8Tbl[0] | (pu8Tbl[1] << 8)), Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0148_DEMURA_BKA377_V004,(pu8Tbl[2] | (pu8Tbl[3] << 8)), Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_014C_DEMURA_BKA377_V004,(pu8Tbl[4] | (pu8Tbl[5] << 8)), Fld(16,0,AC_FULLW10));
    W2BYTEMSK(REG_0150_DEMURA_BKA377_V004,(pu8Tbl[6] | (pu8Tbl[7] << 8)), Fld(16,0,AC_FULLW10));
}

bool MHal_PNL_DumpPCID_TBL(u8* pu8RTbl,u8* pu8GTbl,u8* pu8BTbl,PNL_HAL_PCID_LUT_TYPE eLutType)
{
    bool bEnable = FALSE;
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16Timeout = 0;

    if(pu8RTbl == NULL || pu8GTbl == NULL || pu8BTbl == NULL)
    {
        debug("[%s] Table error \n.", __FUNCTION__);
        return FALSE;
    }

    bEnable = R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,0, REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C); // PCID Disable
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,eLutType, Fld(1,15,AC_MSKB1)); //sel lut bit[15]

    for(u16CodeTableY=0;u16CodeTableY<PCID_TABLE_ROW_9;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<PCID_TABLE_COL_9;u16CodeTableX++)
        {
           W2BYTEMSK(REG_0008_DEMURA_BKA377_V004,pu8RTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2], 0xFF); //R
           W2BYTEMSK(REG_000C_DEMURA_BKA377_V004,pu8GTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2], 0xFF); //G
           W2BYTEMSK(REG_0010_DEMURA_BKA377_V004,pu8BTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2], 0xFF); //B
           W2BYTEMSK(REG_0004_DEMURA_BKA377_V004,u16CodeTableX+(u16CodeTableY*PCID_TABLE_COL_9), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
           TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1,TRIG_WRITE_SRAM|SELECT_SRAM1|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
           while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
           {
               mdelay(1);
               u16Timeout++;
           }
           u16Timeout = 0;
        }
    }
    u16CodeTableX = 0;
    u16CodeTableY = 0;
    for(u16CodeTableY=0;u16CodeTableY<PCID_TABLE_ROW_9;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<PCID_TABLE_COL_8;u16CodeTableX++)
        {
           W2BYTEMSK(REG_0008_DEMURA_BKA377_V004,pu8RTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + 1], 0xFF); //R
           W2BYTEMSK(REG_000C_DEMURA_BKA377_V004,pu8GTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + 1], 0xFF); //G
           W2BYTEMSK(REG_0010_DEMURA_BKA377_V004,pu8BTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + 1], 0xFF); //B
           W2BYTEMSK(REG_0004_DEMURA_BKA377_V004,u16CodeTableX+(u16CodeTableY*PCID_TABLE_COL_8), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
           TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1,TRIG_WRITE_SRAM|SELECT_SRAM2|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
           while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
           {
               mdelay(1);
               u16Timeout++;
           }
           u16Timeout = 0;
        }
    }

    u16CodeTableX = 0;
    u16CodeTableY = 0;
    for(u16CodeTableY=0;u16CodeTableY<PCID_TABLE_ROW_8;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<PCID_TABLE_COL_9;u16CodeTableX++)
        {
           W2BYTEMSK(REG_0008_DEMURA_BKA377_V004,pu8RTbl[u16CodeTableX * 2 + (u16CodeTableY) * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + (PCID_TABLE_COL_9+PCID_TABLE_COL_8)], 0xFF); //R
           W2BYTEMSK(REG_000C_DEMURA_BKA377_V004,pu8GTbl[u16CodeTableX * 2 + (u16CodeTableY) * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + (PCID_TABLE_COL_9+PCID_TABLE_COL_8)], 0xFF); //G
           W2BYTEMSK(REG_0010_DEMURA_BKA377_V004,pu8BTbl[u16CodeTableX * 2 + (u16CodeTableY) * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + (PCID_TABLE_COL_9+PCID_TABLE_COL_8)], 0xFF); //B
           W2BYTEMSK(REG_0004_DEMURA_BKA377_V004,u16CodeTableX+(u16CodeTableY*PCID_TABLE_COL_9), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
           TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1,TRIG_WRITE_SRAM|SELECT_SRAM3|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
           while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
           {
               mdelay(1);
               u16Timeout++;
           }
           u16Timeout = 0;
        }
    }

    u16CodeTableX = 0;
    u16CodeTableY = 0;
    for(u16CodeTableY=0;u16CodeTableY<PCID_TABLE_ROW_8;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<PCID_TABLE_COL_8;u16CodeTableX++)
        {
           W2BYTEMSK(REG_0008_DEMURA_BKA377_V004,pu8RTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + (PCID_TABLE_COL_9+PCID_TABLE_COL_8) +1], 0xFF); //R
           W2BYTEMSK(REG_000C_DEMURA_BKA377_V004,pu8GTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + (PCID_TABLE_COL_9+PCID_TABLE_COL_8) +1], 0xFF); //G
           W2BYTEMSK(REG_0010_DEMURA_BKA377_V004,pu8BTbl[u16CodeTableX * 2 + u16CodeTableY * (PCID_TABLE_COL_9+PCID_TABLE_COL_8) * 2 + (PCID_TABLE_COL_9+PCID_TABLE_COL_8) +1], 0xFF); //B
           W2BYTEMSK(REG_0004_DEMURA_BKA377_V004,u16CodeTableX+(u16CodeTableY*PCID_TABLE_COL_8), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
           TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1,TRIG_WRITE_SRAM|SELECT_SRAM4|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
           while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
           {
               mdelay(1);
               u16Timeout++;
           }
           u16Timeout = 0;
        }
    }
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,0, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_CH_SEL_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,0, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEL_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,0, Fld(1,15,AC_MSKB1));
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,(bEnable?1:0), REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C); // PCID Enable
return TRUE;
}

void MHal_PNL_PCID_Enable(bool bEnable)
{
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, (bEnable? 1:0), REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C);
}


bool MDrv_PNL_TCON_DumpPCIDRegTab(u8* pu8TconTab)
{
    debug("MDrv_PNL_TCON_DumpPixelOverDriveRegTab\n");
    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return FALSE;
    }
    u8 *pu8PCIDTabA1 = NULL;
    u8 *pu8PCIDTabA2 = NULL;
    u8 *pu8PCIDTabA3 = NULL;
    u8 *pu8PCIDTabB1 = NULL;
    u8 *pu8PCIDTabB2 = NULL;
    u8 *pu8PCIDTabB3 = NULL;
    bool bRet = TRUE;

    PNL_MALLOC_MEM(pu8PCIDTabA1, PCID_TABLE_SIZE_17X17 * sizeof(u8), bRet);
    PNL_MALLOC_MEM(pu8PCIDTabA2, PCID_TABLE_SIZE_17X17 * sizeof(u8), bRet);
    PNL_MALLOC_MEM(pu8PCIDTabA3, PCID_TABLE_SIZE_17X17 * sizeof(u8), bRet);
    PNL_MALLOC_MEM(pu8PCIDTabB1, PCID_TABLE_SIZE_17X17 * sizeof(u8), bRet);
    PNL_MALLOC_MEM(pu8PCIDTabB2, PCID_TABLE_SIZE_17X17 * sizeof(u8), bRet);
    PNL_MALLOC_MEM(pu8PCIDTabB3, PCID_TABLE_SIZE_17X17 * sizeof(u8), bRet);

    if(pu8PCIDTabA1 != NULL && pu8PCIDTabA2 != NULL && pu8PCIDTabA3 != NULL && pu8PCIDTabB1 != NULL && pu8PCIDTabB2 != NULL && pu8PCIDTabB3 != NULL)
    {
        u8 u8PixelOverDriveLutTab[PCID_PIXEL_OD_POLARITY_LUT_SIZE];
        u16 u16TargetIndex = 0;
        u16 u16Verison                   = *((unsigned char*) (pu8TconTab));
        u8 u8PCID_En                     = *((unsigned char*) (pu8TconTab+2));
        u8 u8Pixel_OD_En                 = *((unsigned char*) (pu8TconTab+3));
        u8 u8PanelType                   = *((unsigned char*) (pu8TconTab+4));
        u8 u8Swap_En                     = *((unsigned char*) (pu8TconTab+5));
        u8 u8PCIDMode                    = *((unsigned char*) (pu8TconTab+6));
        u8 u8XTR_En                      = *((unsigned char*) (pu8TconTab+7));
        u16 u16XTR_threshold0_polarity   = *((unsigned char*) (pu8TconTab+8));
        u16 u16XTR_threshold1_polarity   = *((unsigned char*) (pu8TconTab+10));

        u16 u16XTR_thresholdW            = *((unsigned char*) (pu8TconTab+12));
        u16 u16XTR_thresholdB            = *((unsigned char*) (pu8TconTab+14));
        //u32 u32YearMonthDay              = *((unsigned char*) (pu8TconTab+16));
        u8 u8Reverse                     = *((unsigned char*) (pu8TconTab+20));
        bool bRetLut0 = FALSE;
        bool bRetLut1 = FALSE;

        debug("u16Verison %d\n",u16Verison);
        debug("u8PCID_En %d\n",u8PCID_En);
        debug("u8Pixel_OD_En %d\n",u8Pixel_OD_En);
        debug("u8PanelType %d\n",u8PanelType);
        debug("u8Swap_En %d\n",u8Swap_En);
        debug("u8PCIDMode %d\n",u8PCIDMode);
        debug("u8XTR_En %d\n",u8XTR_En);

        debug("u16XTR_threshold0_polarity %d\n",u16XTR_threshold0_polarity);
        debug("u16XTR_threshold1_polarity %d\n",u16XTR_threshold1_polarity);
        debug("u16XTR_thresholdW %d\n",u16XTR_thresholdW);
        debug("u16XTR_thresholdB %d\n",u16XTR_thresholdB);
        debug("u8Reverse %d\n",u8Reverse);

        u16TargetIndex = PCID_SKIP_HEADER;
        memcpy(pu8PCIDTabA1,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_TABLE_SIZE_17X17); //Load PCID R table for lut0
        u16TargetIndex += PCID_TABLE_SIZE_17X17;
        memcpy(pu8PCIDTabA2,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_TABLE_SIZE_17X17); //Load PCID G table for lut0
        u16TargetIndex += PCID_TABLE_SIZE_17X17;
        memcpy(pu8PCIDTabA3,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_TABLE_SIZE_17X17); //Load PCID B table for lut0
        u16TargetIndex += PCID_TABLE_SIZE_17X17;
        memcpy(pu8PCIDTabB1,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_TABLE_SIZE_17X17); //Load PCID R table for lut1
        u16TargetIndex += PCID_TABLE_SIZE_17X17;
        memcpy(pu8PCIDTabB2,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_TABLE_SIZE_17X17); //Load PCID G table for lut1
        u16TargetIndex += PCID_TABLE_SIZE_17X17;
        memcpy(pu8PCIDTabB3,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_TABLE_SIZE_17X17); //Load PCID B table for lut1
        u16TargetIndex += PCID_TABLE_SIZE_17X17;
        memcpy(&u8PixelOverDriveLutTab,(pu8TconTab+u16TargetIndex),sizeof(u8)*PCID_PIXEL_OD_POLARITY_LUT_SIZE);

        MHal_PNL_PCID_Init(u8PixelOverDriveLutTab,u8Pixel_OD_En,u8XTR_En);
        bRetLut0 = MHal_PNL_DumpPCID_TBL(pu8PCIDTabA1,pu8PCIDTabA2,pu8PCIDTabA3,E_HAL_PCID_LUT0);
        bRetLut1 = MHal_PNL_DumpPCID_TBL(pu8PCIDTabB1,pu8PCIDTabB2,pu8PCIDTabB3,E_HAL_PCID_LUT1);

        PNL_FREE_MEM(pu8PCIDTabA1);
        PNL_FREE_MEM(pu8PCIDTabA2);
        PNL_FREE_MEM(pu8PCIDTabA3);
        PNL_FREE_MEM(pu8PCIDTabB1);
        PNL_FREE_MEM(pu8PCIDTabB2);
        PNL_FREE_MEM(pu8PCIDTabB3);

        if(bRetLut0 && bRetLut1)
        {
            MHal_PNL_PCID_Enable(u8PCID_En);
			bRet = TRUE;
        }
    }
    else
    {
        PNL_FREE_MEM(pu8PCIDTabA1);
        PNL_FREE_MEM(pu8PCIDTabA2);
        PNL_FREE_MEM(pu8PCIDTabA3);
        PNL_FREE_MEM(pu8PCIDTabB1);
        PNL_FREE_MEM(pu8PCIDTabB2);
        PNL_FREE_MEM(pu8PCIDTabB3);
    }
    return bRet;
}

bool MDrv_PNL_TCON_DumpLineODRegTab(u8* pu8TconTab, u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32Addr;
    u8 u8Mask;
    u8 u8Value;

    debug("MDrv_PNL_TCON_DumpLineODRegTab\n");

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return FALSE;
    }

    while (u16RegisterCount--)
    {
        u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0x7FFFFFFF;
        u8Mask  = pu8TconTab[(u32tabIdx +4)] & 0xFF;
        u8Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;


        debug("[addr=%04tx, msk=%02x, val=%02x] \n", (ptrdiff_t)u32Addr, u8Mask, u8Value);
        TCON_W1BYTEMSK(u32Addr, u8Value, u8Mask);

        u32tabIdx = u32tabIdx + 6;
    }

    debug("MDrv_PNL_TCON_DumpLineODRegTab end\n");
    return TRUE;
}

bool MHal_PNL_DumpLineOD_TBL(u8* pu8EvenRTbl, u8* pu8EvenGTbl, u8* pu8EvenBTbl, u8* pu8OddRTbl, u8* pu8OddGTbl, u8* pu8OddBTbl, u8 u8LutSramSeg)
{
    bool bPcidEnable = FALSE, bLineODEnable = FALSE;
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16Timeout = 0, lutIndex = 0;

    if( PNL_RGB_LUT_CHECK(pu8EvenRTbl, pu8EvenGTbl, pu8EvenBTbl) || PNL_RGB_LUT_CHECK(pu8OddRTbl, pu8OddGTbl, pu8OddBTbl) )
    {
        debug("[%s] Table error \n.", __FUNCTION__);
        return FALSE;
    }

	W2BYTEMSK(REG_00A0_SCTCON_BKA4F7_V004, _BIT(2), REG_00A0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_0_00A0);
	W2BYTEMSK(REG_00C0_SCTCON_BKA4F7_V004, _BIT(2), REG_00C0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_0_00C0);
    bPcidEnable = R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,0x0, REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C); // PCID Disable
    bLineODEnable = R2BYTEMSK(REG_0180_PAT_DET_BKA37F_V004, REG_0180_PAT_DET_BKA37F_V004_REG_PCID_LINEOD_EN_0180);
    W2BYTEMSK(REG_0180_PAT_DET_BKA37F_V004, 0x0, REG_0180_PAT_DET_BKA37F_V004_REG_PCID_LINEOD_EN_0180); // LINE OD Disable
    W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u8LutSramSeg, REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEG_0004); //sel PCID lut sram segment

    //sram1
    for(u16CodeTableY=0;u16CodeTableY<LINE_OD_TABLE_ROW_10;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<LINE_OD_TABLE_COL_10;u16CodeTableX++)
        {
            lutIndex = u16CodeTableX * 2 + u16CodeTableY * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2;
            if( lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu8EvenRTbl[lutIndex] | pu8OddRTbl[lutIndex]<<8, REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu8EvenGTbl[lutIndex] | pu8OddGTbl[lutIndex]<<8, REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu8EvenBTbl[lutIndex] | pu8OddBTbl[lutIndex]<<8, REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_10), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM1|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    //sram2
    for(u16CodeTableY = 0; u16CodeTableY < LINE_OD_TABLE_ROW_10; u16CodeTableY++)
    {
        for(u16CodeTableX = 0; u16CodeTableX < LINE_OD_TABLE_COL_9; u16CodeTableX++)
        {
            lutIndex = u16CodeTableX * 2 + u16CodeTableY * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2 + 1;
            if( lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu8EvenRTbl[lutIndex] | pu8OddRTbl[lutIndex]<<8, REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu8EvenGTbl[lutIndex] | pu8OddGTbl[lutIndex]<<8, REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu8EvenBTbl[lutIndex] | pu8OddBTbl[lutIndex]<<8, REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_9), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM2|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    //sram3
    for(u16CodeTableY = 0; u16CodeTableY < LINE_OD_TABLE_ROW_9; u16CodeTableY++)
    {
        for(u16CodeTableX = 0; u16CodeTableX < LINE_OD_TABLE_COL_10; u16CodeTableX++)
        {
            lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2 + (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9);
            if( lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu8EvenRTbl[lutIndex] | pu8OddRTbl[lutIndex]<<8, REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu8EvenGTbl[lutIndex] | pu8OddGTbl[lutIndex]<<8, REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu8EvenBTbl[lutIndex] | pu8OddBTbl[lutIndex]<<8, REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_10), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM3|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    //sram4
    for(u16CodeTableY = 0; u16CodeTableY < LINE_OD_TABLE_ROW_9; u16CodeTableY++)
    {
        for(u16CodeTableX = 0; u16CodeTableX < LINE_OD_TABLE_COL_9; u16CodeTableX++)
        {
            lutIndex = u16CodeTableX * 2 + u16CodeTableY * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2 + (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) +1;
            if( lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu8EvenRTbl[lutIndex] | pu8OddRTbl[lutIndex]<<8, REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu8EvenGTbl[lutIndex] | pu8OddGTbl[lutIndex]<<8, REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu8EvenBTbl[lutIndex] | pu8OddBTbl[lutIndex]<<8, REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_9), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM4|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, 0, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_CH_SEL_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, 0, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEL_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, (bPcidEnable? 1:0), REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C); // PCID Enable
    W2BYTEMSK(REG_0180_PAT_DET_BKA37F_V004, (bLineODEnable? 1:0), REG_0180_PAT_DET_BKA37F_V004_REG_PCID_LINEOD_EN_0180); // LINE OD Enable
    return TRUE;
}

bool MHal_PNL_DumpLineOD_SingleTBL(u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u8 u8LutSramSeg)
{
    bool bPcidEnable = FALSE, bLineODEnable = FALSE;
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16Timeout = 0, u16lutIndex = 0;

    if(PNL_RGB_LUT_CHECK(pu16RTbl, pu16GTbl, pu16BTbl))
    {
        debug("[%s] Table error \n.", __FUNCTION__);
        return FALSE;
    }

    bPcidEnable = R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C);
    bLineODEnable = R2BYTEMSK(REG_0180_PAT_DET_BKA37F_V004, REG_0180_PAT_DET_BKA37F_V004_REG_PCID_LINEOD_EN_0180);

    if((bPcidEnable == FALSE)||(bLineODEnable == FALSE))
    {
        debug("[%s] Pcid enable: %d lineOD enable: %d\n", __FUNCTION__,bPcidEnable,bLineODEnable);
        return FALSE;
    }

	W2BYTEMSK(REG_00A0_SCTCON_BKA4F7_V004, _BIT(2), REG_00A0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_0_00A0);
	W2BYTEMSK(REG_00C0_SCTCON_BKA4F7_V004, _BIT(2), REG_00C0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_0_00C0);

    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004,0, REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C); // PCID Disable
    W2BYTEMSK(REG_0180_PAT_DET_BKA37F_V004, 0, REG_0180_PAT_DET_BKA37F_V004_REG_PCID_LINEOD_EN_0180); // LINE OD Disable

    if(PNL_LINEOD_SHARE_SRAM == TRUE)
    {
        TCON_W2BYTEMSK(0x1133A8, _BIT(2), _BIT(2));//bk1133_54 [2] set 1 for share SRAM with FCFC
        TCON_W2BYTEMSK(0x113308, _BIT(0), _BIT(0));//bk1133_04 [0] set 1 for share SRAM with LineOD
        TCON_W2BYTEMSK(0x1133AC, 0, _BIT(2));//bk1133_56 [2] set 0 for 1p path
    }

    W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u8LutSramSeg, REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEG_0004); //sel PCID lut sram segment

    //sram1
    for(u16CodeTableY=0;u16CodeTableY<LINE_OD_TABLE_ROW_10;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<LINE_OD_TABLE_COL_10;u16CodeTableX++)
        {
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, u16lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu16RTbl[u16lutIndex], REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu16GTbl[u16lutIndex], REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu16BTbl[u16lutIndex], REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_10), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM1|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    //sram2
    for(u16CodeTableY = 0; u16CodeTableY < LINE_OD_TABLE_ROW_10; u16CodeTableY++)
    {
        for(u16CodeTableX = 0; u16CodeTableX < LINE_OD_TABLE_COL_9; u16CodeTableX++)
        {
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2 + 1;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, u16lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu16RTbl[u16lutIndex], REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu16GTbl[u16lutIndex], REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu16BTbl[u16lutIndex], REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_9), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM2|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    //sram3
    for(u16CodeTableY = 0; u16CodeTableY < LINE_OD_TABLE_ROW_9; u16CodeTableY++)
    {
        for(u16CodeTableX = 0; u16CodeTableX < LINE_OD_TABLE_COL_10; u16CodeTableX++)
        {
            u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2 + (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9);
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, u16lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu16RTbl[u16lutIndex], REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu16GTbl[u16lutIndex], REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu16BTbl[u16lutIndex], REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_10), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM3|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }

    //sram4
    for(u16CodeTableY = 0; u16CodeTableY < LINE_OD_TABLE_ROW_9; u16CodeTableY++)
    {
        for(u16CodeTableX = 0; u16CodeTableX < LINE_OD_TABLE_COL_9; u16CodeTableX++)
        {
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) * 2 + (LINE_OD_TABLE_COL_10+LINE_OD_TABLE_COL_9) +1;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("[%s] lutIndex error: %d\n",__FUNCTION__, u16lutIndex);
                return FALSE;
            }
            W2BYTEMSK(REG_0008_DEMURA_BKA377_V004, pu16RTbl[u16lutIndex], REG_0008_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_R_DATA_0008); //R
            W2BYTEMSK(REG_000C_DEMURA_BKA377_V004, pu16GTbl[u16lutIndex], REG_000C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_G_DATA_000C); //G
            W2BYTEMSK(REG_0010_DEMURA_BKA377_V004, pu16BTbl[u16lutIndex], REG_0010_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_B_DATA_0010); //B

            W2BYTEMSK(REG_0004_DEMURA_BKA377_V004, u16CodeTableX+(u16CodeTableY*LINE_OD_TABLE_COL_9), REG_0004_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_ADDR_0004); //sram address
            TCON_W2BYTEMSK(REG_003C_DEMURA_BKA377_V004>>1, TRIG_WRITE_SRAM|SELECT_SRAM4|SELECT_ALL_CHANNEL_RGB, W_RGB_MASK); //sel RGB
            while(R2BYTEMSK(REG_003C_DEMURA_BKA377_V004, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_WR_003C) && (u16Timeout < MAX_DELAY_TIME))
            {
               mdelay(1);
               u16Timeout++;
            }
            u16Timeout = 0;
        }
    }
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, 0, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_CH_SEL_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, 0, REG_003C_DEMURA_BKA377_V004_REG_PCID_LUT_SRAM_SEL_003C);
    W2BYTEMSK(REG_003C_DEMURA_BKA377_V004, (bPcidEnable? 1:0), REG_003C_DEMURA_BKA377_V004_REG_PCID_EN_003C); // PCID Enable
    W2BYTEMSK(REG_0180_PAT_DET_BKA37F_V004, (bLineODEnable? 1:0), REG_0180_PAT_DET_BKA37F_V004_REG_PCID_LINEOD_EN_0180); // LINE OD Enable
    return TRUE;
}
bool MHal_PNL_DumpLineOD_Gain_TBL(u8* pu8ODGainTbl, u16 u16GainTableSize)
{
    bool bGainEnable = FALSE;
    u16 u16GainTableIndex = 0;
    //u16 u16HWGainSize = LINE_OD_HW_GAIN_SIZE_13X9;//hw size

    if( pu8ODGainTbl == NULL )
    {
        debug("[%s] GainTable error \n.", __FUNCTION__);
        return FALSE;
    }

    //Note:REG_SC_EXT_BK2D/332D/(Bank =104F Sub-Bank=2D)/0x302f00 0x2d --> Bank = A02F Sub-Bank=A8/0xA3A8

    bGainEnable = R2BYTEMSK(REG_0004_LINEOD_BKA3A8_V004, REG_0004_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_EN_0004);

    if(u16GainTableSize==LINE_OD_GAIN_TABLE_SIZE_13X9)
    {

        for(u16GainTableIndex =0; u16GainTableIndex <LINE_OD_GAIN_TABLE_SIZE_13X9; u16GainTableIndex++) //fill the 13x9 data on 13x9 hw address
        {
            W2BYTEMSK(REG_0004_LINEOD_BKA3A8_V004, 0, REG_0004_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_EN_0004);//gain disable
            W2BYTEMSK(REG_0008_LINEOD_BKA3A8_V004, u16GainTableIndex, REG_0008_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_ADR_0008);//[6:0]lineOD gain address
            W2BYTEMSK(REG_000C_LINEOD_BKA3A8_V004, pu8ODGainTbl[u16GainTableIndex],REG_000C_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_WR_DATA_000C);//[7:0]lineOD write data3.5
            W2BYTEMSK(REG_0004_LINEOD_BKA3A8_V004, 1, REG_0004_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_WR_EN_0004);//[3]wr enable
        }
    }
    else if(u16GainTableSize==LINE_OD_GAIN_TABLE_SIZE_4X4)
    {
        u16 u16HWGainIndex = 0;
        for(u16GainTableIndex =0; u16GainTableIndex <LINE_OD_GAIN_TABLE_SIZE_4X4; u16GainTableIndex++)// fill the 4x4 data on 13x9 hw address(other ignore)
        {
            u16HWGainIndex = ((u16GainTableIndex/LINE_OD_GAIN_TABLE_COL_4)*LINE_OD_GAIN_TABLE_COL_13)+(u16GainTableIndex%LINE_OD_GAIN_TABLE_COL_4);
            W2BYTEMSK( REG_0004_LINEOD_BKA3A8_V004, 0, REG_0004_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_EN_0004);//gain disable
            if(u16HWGainIndex<LINE_OD_HW_GAIN_SIZE_13X9)
            {
                W2BYTEMSK(REG_0008_LINEOD_BKA3A8_V004, u16HWGainIndex, REG_0008_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_ADR_0008);//[6:0]lineOD gain address
                W2BYTEMSK(REG_000C_LINEOD_BKA3A8_V004, pu8ODGainTbl[u16GainTableIndex],REG_000C_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_WR_DATA_000C);//[7:0]lineOD write data3.5
            }
            W2BYTEMSK(REG_0004_LINEOD_BKA3A8_V004, 1, REG_0004_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_WR_EN_0004);//[3]wr enable
        }
    }
    else
    {
        debug("[%s] Table size=%d not correct\n",__FUNCTION__,u16GainTableSize);
    }

    W2BYTEMSK(REG_0004_LINEOD_BKA3A8_V004, (bGainEnable?1:0), REG_0004_LINEOD_BKA3A8_V004_REG_PCID_LINEOD_GAIN_EN_0004);//gain enable status recovery
    return TRUE;
}

// PCID Auto Download Format
// 181 * 3 * 32 bytes = 0x43E0 (R/G/B channels)
//|<--------------32 bytes------------->|
//    SRAM1/SRAM4        SRAM2/SRAM3
//   lut0 .... lut9     lut0 .... lut9
//0   0   ....  0         1  ....  1
//.
//89  322 ....  322      359 .... 359
//                      ---------------
//90  358 ....  358       19 ....  19
//.
//99  360 ....  360       37 ....  37
//--------------------
//100 20  ....   20       57 ....  57
//.
//179 338 ....   338     341 ....  341
//                       ---------------
//180 340 ....   340       x ....  x
//--------------------------------------

static void _MHal_PNL_ADL_PCID_SetTBL0(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut0 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut0 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut0 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut0 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut0 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut0 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut0 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut0 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut0 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut0 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut0 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut0 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL1(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut1 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut1 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut1 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut1 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut1 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut1 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut1 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut1 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut1 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut1 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut1 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut1 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL2(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut2 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut2 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut2 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut2 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut2 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut2 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut2 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut2 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut2 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut2 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut2 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut2 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL3(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut3 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut3 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut3 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut3 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut3 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut3 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut3 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut3 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut3 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut3 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut3 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut3 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL4(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut4 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut4 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut4 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut4 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut4 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut4 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut4 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut4 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut4 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut4 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut4 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut4 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL5(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut5 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut5 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut5 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut5 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut5 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut5 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut5 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut5 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut5 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut5 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut5 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut5 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL6(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut6 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut6 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut6 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut6 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut6 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut6 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut6 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut6 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut6 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut6 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut6 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut6 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL7(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut7 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut7 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut7 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut7 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut7 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut7 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut7 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut7 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut7 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut7 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut7 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut7 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL8(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut8 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut8 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut8 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut8 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut8 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut8 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut8 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut8 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut8 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut8 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut8 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut8 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

static void _MHal_PNL_ADL_PCID_SetTBL9(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, bool* pbRet)
{
    u16 u16CodeTableX = 0;
    u16 u16CodeTableY = 0;
    u16 u16lutIndex  = 0;
    u16 u16Sram1Idx = 0,u16Sram2Idx =0, u16Sram3Idx =0,u16Sram4Idx=0;
    u16 u16ROW_MAX = 0,u16COL_MAX = 0;
    u16 u16SRAM3_Offset = 0, u16SRAM4_Offset =0, u16Channel_Offset = 0;

    u16ROW_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_ROW_10:LINE_OD_TABLE_ROW_9;
    u16COL_MAX = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? LINE_OD_TABLE_COL_10:LINE_OD_TABLE_COL_9;
    u16Channel_Offset = (u16TableSize == LINE_OD_TABLE_SIZE_19X19)? XC_AUTODOWNLOAD_PCID_19X19_OFFSET:XC_AUTODOWNLOAD_PCID_17X17_OFFSET;
    u16SRAM3_Offset = u16ROW_MAX*(u16COL_MAX-1);
    u16SRAM4_Offset = u16ROW_MAX*u16COL_MAX;

    for(u16CodeTableY=0;u16CodeTableY<u16ROW_MAX;u16CodeTableY++)
    {
        for(u16CodeTableX=0;u16CodeTableX<u16COL_MAX;u16CodeTableX++)
        {
            //sram1
            u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2;
            if( u16lutIndex >= LINE_OD_TABLE_SIZE_19X19 )
            {
                debug("%s %d: lutIndex error: %d\n",__func__,__LINE__, u16lutIndex);
                *pbRet = FALSE;
                return;
            }

            pstPCID_ADL_CMD[u16Sram1Idx].u16SRAM1_lut9 = pu16RTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset].u16SRAM1_lut9 = pu16GTbl[u16lutIndex];
            pstPCID_ADL_CMD[u16Sram1Idx + u16Channel_Offset*2].u16SRAM1_lut9 = pu16BTbl[u16lutIndex];
            u16Sram1Idx++;

            //sram2
            if (u16CodeTableX < u16COL_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + 1;
                pstPCID_ADL_CMD[u16Sram2Idx].u16SRAM2_lut9 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset].u16SRAM2_lut9 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram2Idx + u16Channel_Offset*2].u16SRAM2_lut9 = pu16BTbl[u16lutIndex];
                u16Sram2Idx++;
            }

            //sram3
            if (u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + (u16CodeTableY) * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1);
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset].u16SRAM2_lut9 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset].u16SRAM2_lut9 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram3Idx + u16SRAM3_Offset + u16Channel_Offset*2].u16SRAM2_lut9 = pu16BTbl[u16lutIndex];
                u16Sram3Idx++;
            }

            //sram4
            if (u16CodeTableX < u16COL_MAX-1 && u16CodeTableY < u16ROW_MAX-1)
            {
                u16lutIndex = u16CodeTableX * 2 + u16CodeTableY * (u16COL_MAX*2-1) * 2 + (u16COL_MAX*2-1) +1;
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset].u16SRAM1_lut9 = pu16RTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset].u16SRAM1_lut9 = pu16GTbl[u16lutIndex];
                pstPCID_ADL_CMD[u16Sram4Idx + u16SRAM4_Offset+ u16Channel_Offset*2].u16SRAM1_lut9 = pu16BTbl[u16lutIndex];
                u16Sram4Idx++;
            }

        }
    }
    *pbRet = TRUE;
}

bool MHal_PNL_ADL_PCID_AllocateDram(ST_PNL_PCID_12BIT_DRAM_FORMAT* pstPCID_ADL_CMD, u16* pu16RTbl, u16* pu16GTbl, u16* pu16BTbl, u16 u16TableSize, u8 u8TableNum)
{
    bool bRet = FALSE;

    set_adl_pcid_table[0]=_MHal_PNL_ADL_PCID_SetTBL0;
    set_adl_pcid_table[1]=_MHal_PNL_ADL_PCID_SetTBL1;
    set_adl_pcid_table[2]=_MHal_PNL_ADL_PCID_SetTBL2;
    set_adl_pcid_table[3]=_MHal_PNL_ADL_PCID_SetTBL3;
    set_adl_pcid_table[4]=_MHal_PNL_ADL_PCID_SetTBL4;
    set_adl_pcid_table[5]=_MHal_PNL_ADL_PCID_SetTBL5;
    set_adl_pcid_table[6]=_MHal_PNL_ADL_PCID_SetTBL6;
    set_adl_pcid_table[7]=_MHal_PNL_ADL_PCID_SetTBL7;
    set_adl_pcid_table[8]=_MHal_PNL_ADL_PCID_SetTBL8;
    set_adl_pcid_table[9]=_MHal_PNL_ADL_PCID_SetTBL9;

    if(pstPCID_ADL_CMD == NULL || pu16RTbl == NULL || pu16GTbl == NULL || pu16BTbl == NULL)
    {
        return bRet;
    }
    if(u8TableNum < 10)
    {
        set_adl_pcid_table[u8TableNum](pstPCID_ADL_CMD, pu16RTbl, pu16GTbl, pu16BTbl,u16TableSize,&bRet);
        return bRet;
    }
    else
    {
        return bRet;
    }
}
ST_PNL_PCID_12BIT_DRAM_FORMAT* g_pstPCID_ADL_CMD = NULL;

bool MDrv_PNL_TCON_DumpLineODLutTab(u8* pu8TconTab)
{
    debug("MDrv_PNL_TCON_DumpLineODLutTab\n");
    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return FALSE;
    }

    u8 u8LutSramSeg;
    u16 u16TargetIndex = 0;
    pST_PNL_LINE_OD_SUB_HEADER pstLineODSubHdr;
    bool bRetLut = FALSE, bChannelSeparate = FALSE, bTableSeparate = FALSE;
    u8 u8TabIndex, u8TableNum;
    u16 u16TableSize;
    u8 *pu8EvenRLut = NULL;
    u8 *pu8EvenGLut = NULL;
    u8 *pu8EvenBLut = NULL;
    u8 *pu8OddRLut = NULL;
    u8 *pu8OddGLut = NULL;
    u8 *pu8OddBLut = NULL;
    u16 *pu16RLut = NULL;
    u16 *pu16GLut = NULL;
    u16 *pu16BLut = NULL;
    u32 u32AdlSize = 0;
    bool bRet = TRUE;

    pstLineODSubHdr = (pST_PNL_LINE_OD_SUB_HEADER)pu8TconTab;
    bChannelSeparate = pstLineODSubHdr->u8SeparateFlag & BIT(0);
    bTableSeparate = (pstLineODSubHdr->u8SeparateFlag & BIT(1)) >> 1;

    debug("u16Version: %d\n", pstLineODSubHdr->u16Version);
    debug("u8LineOD_en: %d\n", pstLineODSubHdr->u8LineOD_en);
    debug("channel seperate: %d, table separate: %d\n", bChannelSeparate, bTableSeparate);
    debug("year: %u, month: %u, day: %u, minute: %u\n",
            (pstLineODSubHdr->u32YearMonthDayMinute & 0x1F00000)>>20, (pstLineODSubHdr->u32YearMonthDayMinute & 0xF0000)>>16,
            (pstLineODSubHdr->u32YearMonthDayMinute & 0xF800)>>11, (pstLineODSubHdr->u32YearMonthDayMinute & 0x7FF) );
    debug("table matrix: %d\n", pstLineODSubHdr->u8TableMatrix);
    debug("region number: %d\n", pstLineODSubHdr->u8RegionNumber);
    if(pstLineODSubHdr->u16Version > 2)//after verion 2 add new member table unit
    {
        debug("table bit: %d\n", pstLineODSubHdr->u8TableBit);
    }
    if(pstLineODSubHdr->u16Version > 1)
    {
        debug("gain matrix: %d\n", pstLineODSubHdr->u8GainMatrix);
        debug("gain region number: %d\n", pstLineODSubHdr->u8GainRegion);
    }
    u16TableSize = (pstLineODSubHdr->u8TableMatrix? LINE_OD_TABLE_SIZE_17X17: LINE_OD_TABLE_SIZE_19X19);

    if((pstLineODSubHdr->u16Version > 2) && (pstLineODSubHdr->u8TableBit == LINE_OD_TABLE_UNIT_SIZE_12))
    {
        PNL_MALLOC_MEM(pu16RLut, u16TableSize*sizeof(u16), bRet);
        PNL_MALLOC_MEM(pu16GLut, u16TableSize*sizeof(u16), bRet);
        PNL_MALLOC_MEM(pu16BLut, u16TableSize*sizeof(u16), bRet);

        if (PNL_RGB_LUT_CHECK(pu16RLut, pu16GLut, pu16BLut))
        {
            PNL_FREE_MEM(pu16RLut);
            PNL_FREE_MEM(pu16GLut);
            PNL_FREE_MEM(pu16BLut);

            return bRetLut;
        }

        u16TargetIndex = sizeof(ST_PNL_LINE_OD_SUB_HEADER);

        if(pstLineODSubHdr->u8RegionNumber == 0)
        {
            u8TableNum= LINE_OD_REG_NUM_1X1;
        }
        else if(pstLineODSubHdr->u8RegionNumber == 1)
        {
            u8TableNum= LINE_OD_REG_NUM_2X8;
        }
        else if(pstLineODSubHdr->u8RegionNumber == 2)
        {
            u8TableNum= LINE_OD_REG_NUM_4X4;
        }
        else if(pstLineODSubHdr->u8RegionNumber == 3)
        {
            u8TableNum= LINE_OD_REG_NUM_10X1;
        }
        else
        {
            u8TableNum= LINE_OD_REG_NUM_1X1;
        }
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_PCID_AUTODOWNLOAD == TRUE)
        if (u16TableSize == LINE_OD_TABLE_SIZE_17X17)
        {
            u32AdlSize = XC_AUTODOWNLOAD_PCID_17X17_OFFSET;// 32 bytes * 145 * 3
        }
        else
        {
            u32AdlSize = XC_AUTODOWNLOAD_PCID_19X19_OFFSET;// 32 bytes * 181 * 3
        }
        u32AdlSize = u32AdlSize * sizeof(ST_PNL_PCID_12BIT_DRAM_FORMAT) * PCID_RGB_CHANNEL;
        if(g_pstPCID_ADL_CMD == NULL)
        {
            PNL_MALLOC_MEM(g_pstPCID_ADL_CMD, u32AdlSize, bRet);
            if(g_pstPCID_ADL_CMD == NULL)
            {
                debug("[%s][%d] Autodownload allocate mem fail\n",__FUNCTION__,__LINE__);
                PNL_FREE_MEM(pu16RLut);
	            PNL_FREE_MEM(pu16GLut);
	            PNL_FREE_MEM(pu16BLut);
                return bRet;
            }
        }
        memset(g_pstPCID_ADL_CMD, 0, u32AdlSize);
#endif

        u8TabIndex = 0;
        while (u8TabIndex < u8TableNum)
        {
            if (bChannelSeparate)
            {
                memcpy(pu16RLut, (pu8TconTab+u16TargetIndex), sizeof(u16)*u16TableSize); //R
                u16TargetIndex += u16TableSize*2;
                memcpy(pu16GLut, (pu8TconTab+u16TargetIndex), sizeof(u16)*u16TableSize); //G
                u16TargetIndex += u16TableSize*2;
                memcpy(pu16BLut, (pu8TconTab+u16TargetIndex), sizeof(u16)*u16TableSize); //B
                u16TargetIndex += u16TableSize*2;
            }
            else
            {
                memcpy(pu16RLut, (pu8TconTab+u16TargetIndex), sizeof(u16)*u16TableSize); //R
                memcpy(pu16GLut, (pu8TconTab+u16TargetIndex), sizeof(u16)*u16TableSize); //G
                memcpy(pu16BLut, (pu8TconTab+u16TargetIndex), sizeof(u16)*u16TableSize); //B
                u16TargetIndex += u16TableSize*2;
            }

            u8LutSramSeg = u8TabIndex;
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_PCID_AUTODOWNLOAD == TRUE)
            bRetLut = MHal_PNL_ADL_PCID_AllocateDram(g_pstPCID_ADL_CMD,pu16RLut,pu16GLut,pu16BLut ,u16TableSize,u8TabIndex);
            if(bRetLut != TRUE)
            {
                debug("[%s] MHal_PNL_ADL_PCID_AllocateDram u8TabIndex=%d \n.", __FUNCTION__,u8TabIndex);
            }
#else

            bRetLut = MHal_PNL_DumpLineOD_SingleTBL(pu16RLut, pu16GLut, pu16BLut, u8LutSramSeg);
            if(bRetLut != TRUE)
            {
                debug("[%s] MHal_PNL_DumpLineOD_SingleTBL \n.", __FUNCTION__);
            }
#endif
            u8TabIndex+=1;
        }
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_PCID_AUTODOWNLOAD == TRUE)
        if (KHal_XC_WriteAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_PCID,(u8 *)g_pstPCID_ADL_CMD,u32AdlSize,NULL)!=TRUE)
        {
            UBOOT_ERROR("[%s]PCID, Write ADL Fail!!! \n", __FUNCTION__);
        }

        if(KHal_XC_FireAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_PCID)!=TRUE)
        {
            UBOOT_ERROR("[%s]PCID, FIRE ADL Fail!!! \n", __FUNCTION__);
        }
        PNL_FREE_MEM(g_pstPCID_ADL_CMD);
#endif

        PNL_FREE_MEM(pu16RLut);
        PNL_FREE_MEM(pu16GLut);
        PNL_FREE_MEM(pu16BLut);
    }
    else
    {
        PNL_MALLOC_MEM(pu8EvenRLut, u16TableSize*sizeof(u8), bRet);
        PNL_MALLOC_MEM(pu8EvenGLut, u16TableSize*sizeof(u8), bRet);
        PNL_MALLOC_MEM(pu8EvenBLut, u16TableSize*sizeof(u8), bRet);
        PNL_MALLOC_MEM(pu8OddRLut, u16TableSize*sizeof(u8), bRet);
        PNL_MALLOC_MEM(pu8OddGLut, u16TableSize*sizeof(u8), bRet);
        PNL_MALLOC_MEM(pu8OddBLut, u16TableSize*sizeof(u8), bRet);

        if (PNL_RGB_LUT_CHECK(pu8EvenRLut, pu8EvenGLut, pu8EvenBLut) || PNL_RGB_LUT_CHECK(pu8OddRLut, pu8OddGLut, pu8OddBLut))
        {
            PNL_FREE_MEM(pu8EvenRLut);
            PNL_FREE_MEM(pu8EvenGLut);
            PNL_FREE_MEM(pu8EvenBLut);
            PNL_FREE_MEM(pu8OddRLut);
            PNL_FREE_MEM(pu8OddGLut);
            PNL_FREE_MEM(pu8OddBLut);

            return bRetLut;
        }

        u16TargetIndex = sizeof(ST_PNL_LINE_OD_SUB_HEADER);

        if(pstLineODSubHdr->u16Version > 1)//after verion 1 region number define different
        {
             if(pstLineODSubHdr->u8RegionNumber == 0)
            {
                u8TableNum= LINE_OD_REG_NUM_1X1;
            }
            else if(pstLineODSubHdr->u8RegionNumber == 1)
            {
                u8TableNum= LINE_OD_REG_NUM_2X8;
            }
            else if(pstLineODSubHdr->u8RegionNumber == 2)
            {
                u8TableNum= LINE_OD_REG_NUM_4X4;
            }
            else
            {
                u8TableNum= LINE_OD_REG_NUM_1X1;
            }
        }
        else
        {
            u8TableNum = (bTableSeparate?pstLineODSubHdr->u8RegionNumber:1);
        }

        u8TabIndex = 0;
        while (u8TabIndex < u8TableNum)
        {
            if (bChannelSeparate)
            {
                //even lut
                memcpy(pu8EvenRLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //R
                u16TargetIndex += u16TableSize;
                memcpy(pu8EvenGLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //G
                u16TargetIndex += u16TableSize;
                memcpy(pu8EvenBLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //B
                u16TargetIndex += u16TableSize;

                if ((u8TabIndex + 1) != u8TableNum) //avoid to copy last odd lut table that doesn't exist
                {
                    //odd lut
                    memcpy(pu8OddRLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //R
                    u16TargetIndex += u16TableSize;
                    memcpy(pu8OddGLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //G
                    u16TargetIndex += u16TableSize;
                    memcpy(pu8OddBLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //B
                    u16TargetIndex += u16TableSize;
                }
            }
            else
            {
                //even lut
                memcpy(pu8EvenRLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //R
                memcpy(pu8EvenGLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //G
                memcpy(pu8EvenBLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //B
                u16TargetIndex += u16TableSize;

                if ((u8TabIndex + 1) != u8TableNum) //avoid to copy last odd lut table that doesn't exist
                {
                    //odd lut
                    memcpy(pu8OddRLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //R
                    memcpy(pu8OddGLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //G
                    memcpy(pu8OddBLut, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16TableSize); //B
                    u16TargetIndex += u16TableSize;
                }
            }

            u8LutSramSeg = u8TabIndex/2;
            bRetLut = MHal_PNL_DumpLineOD_TBL(pu8EvenRLut, pu8EvenGLut, pu8EvenBLut, pu8OddRLut, pu8OddGLut, pu8OddBLut, u8LutSramSeg);

            u8TabIndex+=2;
        }
        PNL_FREE_MEM(pu8EvenRLut);
        PNL_FREE_MEM(pu8EvenGLut);
        PNL_FREE_MEM(pu8EvenBLut);
        PNL_FREE_MEM(pu8OddRLut);
        PNL_FREE_MEM(pu8OddGLut);
        PNL_FREE_MEM(pu8OddBLut);
    }

    if(pstLineODSubHdr->u16Version > 1)
    {
        u8 *pu8Gain = NULL;
        u16 u16GainTableSize = 0;

        if(pstLineODSubHdr->u8GainMatrix == 0)
        {
            u16GainTableSize = LINE_OD_GAIN_TABLE_SIZE_4X4;
        }
        else if(pstLineODSubHdr->u8GainMatrix == 1)
        {
            u16GainTableSize = LINE_OD_GAIN_TABLE_SIZE_13X9;
        }
        else
        {
            u16GainTableSize = LINE_OD_GAIN_TABLE_SIZE_13X9;
        }

        PNL_MALLOC_MEM(pu8Gain, u16GainTableSize*sizeof(u8), bRet);
        if(pu8Gain != NULL)
        {
            memcpy(pu8Gain, (pu8TconTab+u16TargetIndex), sizeof(u8)*u16GainTableSize);
            bRetLut = MHal_PNL_DumpLineOD_Gain_TBL(pu8Gain, u16GainTableSize);
        }
        PNL_FREE_MEM(pu8Gain);
    }

    return bRetLut;
}

//Dump EVA Reg
bool MDrv_PNL_TCON_DumpRegTab(u8* pu8TconTab, u16 u16RegisterCount)
{
    u32 u32tabIdx = 0;
    u32 u32Addr = 0;
    u8 u8Mask = 0;
    u8 u8Value = 0;

    debug("MDrv_PNL_TCON_DumpRegTab\n");

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return FALSE;
    }

    while (u16RegisterCount--)
    {
        u32Addr = (((u32)pu8TconTab[u32tabIdx]<<24) + ((u32)pu8TconTab[(u32tabIdx +1)]<<16) + ((u32)pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0x7FFFFFFF;
        u8Mask  = pu8TconTab[(u32tabIdx +4)] & 0xFF;
        u8Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;


        debug("[addr=%04tx, msk=%02x, val=%02x] \n", (ptrdiff_t)u32Addr, u8Mask, u8Value);
        TCON_W1BYTEMSK(u32Addr, u8Value, u8Mask);

        u32tabIdx = u32tabIdx + 6;
    }

    debug("MDrv_PNL_TCON_DumpRegTab end\n");
    return TRUE;
}

//Dump EVA Table
void MHal_PNL_SetVACByPass(bool bEnable)
{
#if SUPPORT_VAC_256
    W2BYTEMSK(REG_001C_PAFRC_BKA324_V004, (bEnable? 1:0), REG_001C_PAFRC_BKA324_V004_REG_ADVAC_BYPASS_001C);
#endif
}

bool MHal_PNL_GetVACByPass(void)
{
#if SUPPORT_VAC_256
    if (R2BYTEMSK(REG_001C_PAFRC_BKA324_V004, REG_001C_PAFRC_BKA324_V004_REG_ADVAC_BYPASS_001C) >> 15)
    {
        return TRUE;
    }
    else
#endif
    {
        return FALSE;
    }
}

void MHal_PNL_SetVACEnable(bool bEnable)
{
    W2BYTEMSK(REG_003C_PAFRC_BKA324_V004, (bEnable? 1:0), REG_003C_PAFRC_BKA324_V004_REG_VAC_CURVE_FIT_EN_003C);//bit[0]:vac_en
}

bool MHal_PNL_GetVACEnable(void)
{
    return (R2BYTEMSK(REG_003C_PAFRC_BKA324_V004, REG_003C_PAFRC_BKA324_V004_REG_VAC_CURVE_FIT_EN_003C));
}

bool MHal_PNL_SetEva_TBL(ST_PNL_EVA_TBL *pstEvaTbl)
{
#if SUPPORT_VAC_256
    u8 u8Channel =0;
    u16 u16Index = 0;
    //bool bVACBypass = 0;
    bool bVACEnable = 0;
    u16 u16Timeout = 0;
    u16* p16TmpTbl0 = NULL;
    u16* p16TmpTbl1 = NULL;

    // Store VAC Bypass and enable flag
    //bVACBypass = MHal_PNL_GetVACByPass();
    bVACEnable = MHal_PNL_GetVACEnable();

    MHal_PNL_SetVACByPass(FALSE);
    MHal_PNL_SetVACEnable(FALSE);

    p16TmpTbl0 = pstEvaTbl->pu16RChannel0;
    p16TmpTbl1 = pstEvaTbl->pu16RChannel1;

    for (u8Channel = 0; u8Channel < EVA_TABLE_RGB_CNANNEL; u8Channel ++)
    {
        //1.  channel select
        W2BYTEMSK(REG_0140_PAFRC_BKA324_V004, u8Channel, REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_CH_SEL_0140);//bit[6:5]: 00=R, 01=B, 10=B
        if(u8Channel == 1)//G
        {
            p16TmpTbl0 = pstEvaTbl->pu16GChannel0;
            p16TmpTbl1 = pstEvaTbl->pu16GChannel1;
        }
        else if(u8Channel == 2)//B
        {
            p16TmpTbl0 = pstEvaTbl->pu16BChannel0;
            p16TmpTbl1 = pstEvaTbl->pu16BChannel1;
        }

        for (u16Index = 0; u16Index < EVA_LUT_SIZE_256; u16Index ++)//0~255 for lut0, 256~511 for lut1
        {
        //lut0
            //2. Addr
            W2BYTEMSK(REG_0144_PAFRC_BKA324_V004, u16Index, REG_0144_PAFRC_BKA324_V004_REG_VAC_GAMMA_ADR_0144);//bit[9:0]
            //3. Data
            W2BYTEMSK(REG_0148_PAFRC_BKA324_V004, p16TmpTbl0[u16Index], REG_0148_PAFRC_BKA324_V004_REG_VAC_GAMMA_DATA_0148);//bit[11:0]
            //4. toggle LUT_W_FLAG
            W2BYTEMSK(REG_0140_PAFRC_BKA324_V004,1,REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_WR_EN_0140);//bit[3]
            // after setting toggle bit, we need to make sure the bit is already toggled.
            while(R2BYTEMSK(REG_0140_PAFRC_BKA324_V004, REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_WR_EN_0140) && (u16Timeout < MAX_DELAY_TIME))
            {
                mdelay(1);
                u16Timeout++;
            }

        //lut1
            //2. Addr
            W2BYTEMSK(REG_0144_PAFRC_BKA324_V004, u16Index+EVA_LUT_SIZE_256, REG_0144_PAFRC_BKA324_V004_REG_VAC_GAMMA_ADR_0144);//bit[9:0]
            //3. Data
            W2BYTEMSK(REG_0148_PAFRC_BKA324_V004, p16TmpTbl1[u16Index], REG_0148_PAFRC_BKA324_V004_REG_VAC_GAMMA_DATA_0148);//bit[11:0]
            //4. toggle LUT_W_FLAG
            W2BYTEMSK(REG_0140_PAFRC_BKA324_V004,1,REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_WR_EN_0140);//bit[3]
            // after setting toggle bit, we need to make sure the bit is already toggled.
            while(R2BYTEMSK(REG_0140_PAFRC_BKA324_V004, REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_WR_EN_0140) && (u16Timeout < MAX_DELAY_TIME))
            {
                mdelay(1);
                u16Timeout++;
            }
        }
    }

    //Restore VAC status
    if(bVACEnable)
    {
        MHal_PNL_SetVACEnable(TRUE);
    }

#endif
    return TRUE;
}

bool MHal_PNL_GetEva_From_Reg(ST_PNL_EVA_TBL *pstEvaTbl)
{
#if SUPPORT_VAC_256
    u8 u8Channel =0;
    u16 u16Index = 0;
    //bool bVACBypass = 0;
    bool bVACEnable = 0;
    u16 u16Timeout = 0;
    u16* p16TmpTbl0 = NULL;
    u16* p16TmpTbl1 = NULL;

    if(PNL_RGB_LUT_CHECK(pstEvaTbl->pu16RChannel0, pstEvaTbl->pu16GChannel0, pstEvaTbl->pu16BChannel0) ||
       PNL_RGB_LUT_CHECK(pstEvaTbl->pu16RChannel1, pstEvaTbl->pu16GChannel1, pstEvaTbl->pu16BChannel1))
    {
        debug("[%s] Table error \n.", __FUNCTION__);
        return FALSE;
    }

    MHal_PNL_SetVACByPass(FALSE); // VSC is ON

    p16TmpTbl0 = pstEvaTbl->pu16RChannel0;
    p16TmpTbl1 = pstEvaTbl->pu16RChannel1;

    for (u8Channel = 0; u8Channel < EVA_TABLE_RGB_CNANNEL; u8Channel ++)
    {
        //1.  channel select
        W2BYTEMSK(REG_0140_PAFRC_BKA324_V004, u8Channel, REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_CH_SEL_0140);//bit[6:5]: 00=R, 01=B, 10=B
        if(u8Channel == 1)//G
        {
            p16TmpTbl0 = pstEvaTbl->pu16GChannel0;
            p16TmpTbl1 = pstEvaTbl->pu16GChannel1;
        }
        else if(u8Channel == 2)//B
        {
            p16TmpTbl0 = pstEvaTbl->pu16BChannel0;
            p16TmpTbl1 = pstEvaTbl->pu16BChannel1;
        }

        for (u16Index = 0; u16Index < EVA_LUT_SIZE_256; u16Index ++)//0~255 for lut0, 256~511 for lut1
        {
        //lut0
            //2. Addr
            W2BYTEMSK(REG_0144_PAFRC_BKA324_V004, u16Index, REG_0144_PAFRC_BKA324_V004_REG_VAC_GAMMA_ADR_0144);//bit[9:0]
            //3. toggle LUT_R_FLAG
            W2BYTEMSK(REG_0140_PAFRC_BKA324_V004,1,REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_RD_EN_0140);//bit[4]
            // after setting toggle bit, we need to make sure the bit is already toggled.
            while(R2BYTEMSK(REG_0140_PAFRC_BKA324_V004, REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_RD_EN_0140) && (u16Timeout < MAX_DELAY_TIME))
            {
                mdelay(1);
                u16Timeout++;
            }
            //4. Data
            p16TmpTbl0[u16Index] = R2BYTEMSK(REG_0150_PAFRC_BKA324_V004, REG_0150_PAFRC_BKA324_V004_REG_VAC_GAMMA_RD_DATA_0150);//bit[11:0]
         //lut1
            //2. Addr
            W2BYTEMSK(REG_0144_PAFRC_BKA324_V004, u16Index+EVA_LUT_SIZE_256, REG_0144_PAFRC_BKA324_V004_REG_VAC_GAMMA_ADR_0144);//bit[9:0]
            //3. toggle LUT_R_FLAG
            W2BYTEMSK(REG_0140_PAFRC_BKA324_V004,1,REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_RD_EN_0140);//bit[4]
            // after setting toggle bit, we need to make sure the bit is already toggled.
            while(R2BYTEMSK(REG_0140_PAFRC_BKA324_V004, REG_0140_PAFRC_BKA324_V004_REG_VAC_GAMMA_RD_EN_0140) && (u16Timeout < MAX_DELAY_TIME))
            {
                mdelay(1);
                u16Timeout++;
            }
            //4. Data
            p16TmpTbl1[u16Index] = R2BYTEMSK(REG_0150_PAFRC_BKA324_V004, REG_0150_PAFRC_BKA324_V004_REG_VAC_GAMMA_RD_DATA_0150);//bit[11:0]
        }
    }

    //Restore VAC status
    if(bVACEnable)
    {
        MHal_PNL_SetVACEnable(TRUE);
    }

#endif
    return TRUE;
}

bool MHal_PNL_ADL_SetEva_TBL(ST_PNL_EVA_TBL *pstEvaTbl)
{
#if (defined(UFO_XC_AUTO_DOWNLOAD) && ENABLE_VAC_AUTODOWNLOAD == TRUE)
    u32 u32index = 0;
    u8 *pu8EvaTbl;
    bool bRet = TRUE;
    u8 *pu8R0 = NULL, *pu8G0 = NULL, *pu8B0 = NULL, *pu8R1 = NULL, *pu8G1 = NULL, *pu8B1 = NULL;

    PNL_MALLOC_MEM(pu8EvaTbl, XC_AUTODOWNLOAD_VAC_MEM_SIZE, bRet);

    if (bRet == TRUE)
    {
       pu8R0 = pu8EvaTbl;
       pu8G0 = pu8R0 + XC_AUTODOWNLOAD_VAC_CHANNEL_OFFSET;  // 16entry  * 32 byte
       pu8B0 = pu8G0 + XC_AUTODOWNLOAD_VAC_CHANNEL_OFFSET;
       pu8R1 = pu8B0 + XC_AUTODOWNLOAD_VAC_CHANNEL_OFFSET;
       pu8G1 = pu8R1 + XC_AUTODOWNLOAD_VAC_CHANNEL_OFFSET;
       pu8B1 = pu8G1 + XC_AUTODOWNLOAD_VAC_CHANNEL_OFFSET;

       for(u32index = 0 ; u32index < EVA_LUT_SIZE_256; u32index++)
       {
           //LUT 0
           *((u16 *)pu8R0 + u32index) = pstEvaTbl->pu16RChannel0[u32index];
           *((u16 *)pu8G0 + u32index) = pstEvaTbl->pu16GChannel0[u32index];
           *((u16 *)pu8B0 + u32index) = pstEvaTbl->pu16BChannel0[u32index];
           //LUT 1
           *((u16 *)pu8R1 + u32index) = pstEvaTbl->pu16RChannel1[u32index];
           *((u16 *)pu8G1 + u32index) = pstEvaTbl->pu16GChannel1[u32index];
           *((u16 *)pu8B1 + u32index) = pstEvaTbl->pu16BChannel1[u32index];
       }

        // Write ADL
        if(KHal_XC_WriteAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_VAC, pu8EvaTbl, XC_AUTODOWNLOAD_VAC_MEM_SIZE, NULL)!= TRUE)
        {
            UBOOT_ERROR("VAC,Write ADL Fail!!!!!!!!!!\n");
            PNL_FREE_MEM(pu8EvaTbl);
            return FALSE;
        }

        //Fire ADL
        if(KHal_XC_FireAutoDownload(E_PNL_XC_AUTODOWNLOAD_CLIENT_VAC) != TRUE)
        {
            UBOOT_ERROR("VAC,Fire ADL Fail!!!!!!!!!!\n");
            PNL_FREE_MEM(pu8EvaTbl);
            return FALSE;
        }
        PNL_FREE_MEM(pu8EvaTbl);
    }
    else
    {
        return FALSE;
    }
    return TRUE;
#else
    return FALSE;
#endif
}

//EVA Table drvPNL.c
static bool _MDrv_EvaTbl_MemAllocate(ST_PNL_EVA_TBL *pstEvaTbl)
{
    bool bRet = TRUE;
    bool bMallocRet = TRUE;

    PNL_MALLOC_MEM(pstEvaTbl->pu16RChannel0, sizeof(u16)*EVA_TABLE_MATRIX_SIZE_257X2, bRet);
    PNL_MALLOC_MEM(pstEvaTbl->pu16GChannel0, sizeof(u16)*EVA_TABLE_MATRIX_SIZE_257X2, bRet);
    PNL_MALLOC_MEM(pstEvaTbl->pu16BChannel0, sizeof(u16)*EVA_TABLE_MATRIX_SIZE_257X2, bRet);
    if(bRet != TRUE)
    {
        UBOOT_ERROR("EVA_MALLOC_MEM Fail!!!!!!!!!!\n");
        bMallocRet = FALSE;
    }

    PNL_MALLOC_MEM(pstEvaTbl->pu16RChannel1, sizeof(u16)*EVA_TABLE_MATRIX_SIZE_257X2, bRet);
    PNL_MALLOC_MEM(pstEvaTbl->pu16GChannel1, sizeof(u16)*EVA_TABLE_MATRIX_SIZE_257X2, bRet);
    PNL_MALLOC_MEM(pstEvaTbl->pu16BChannel1, sizeof(u16)*EVA_TABLE_MATRIX_SIZE_257X2, bRet);

    if(bRet != TRUE)
    {
        UBOOT_ERROR("EVA_MALLOC_MEM Fail!!!!!!!!!!\n");
        bMallocRet = FALSE;
    }

    if(bMallocRet == FALSE)
    {
        PNL_FREE_MEM(pstEvaTbl->pu16RChannel0);
        PNL_FREE_MEM(pstEvaTbl->pu16GChannel0);
        PNL_FREE_MEM(pstEvaTbl->pu16BChannel0);

        PNL_FREE_MEM(pstEvaTbl->pu16RChannel1);
        PNL_FREE_MEM(pstEvaTbl->pu16GChannel1);
        PNL_FREE_MEM(pstEvaTbl->pu16BChannel1);
        return bMallocRet;
    }

    if(pstEvaTbl->u16TblSize == EVA_TABLE_MATRIX_SIZE_17X2)
    {
        PNL_MALLOC_MEM(pstEvaTbl->pu16RChannel0_17, sizeof(u16)*pstEvaTbl->u16TblSize, bRet);
        PNL_MALLOC_MEM(pstEvaTbl->pu16GChannel0_17, sizeof(u16)*pstEvaTbl->u16TblSize, bRet);
        PNL_MALLOC_MEM(pstEvaTbl->pu16BChannel0_17, sizeof(u16)*pstEvaTbl->u16TblSize, bRet);
        if(bRet != TRUE)
        {
            UBOOT_ERROR("EVA_MALLOC_MEM Fail!!!!!!!!!!\n");
            bMallocRet = FALSE;
        }
        PNL_MALLOC_MEM(pstEvaTbl->pu16RChannel1_17, sizeof(u16)*pstEvaTbl->u16TblSize, bRet);
        PNL_MALLOC_MEM(pstEvaTbl->pu16GChannel1_17, sizeof(u16)*pstEvaTbl->u16TblSize, bRet);
        PNL_MALLOC_MEM(pstEvaTbl->pu16BChannel1_17, sizeof(u16)*pstEvaTbl->u16TblSize, bRet);

        if(bRet != TRUE)
        {
            UBOOT_ERROR("EVA_MALLOC_MEM Fail!!!!!!!!!!\n");
            bMallocRet = FALSE;
        }

        if(bMallocRet == FALSE)
        {
            PNL_FREE_MEM(pstEvaTbl->pu16RChannel0_17);
            PNL_FREE_MEM(pstEvaTbl->pu16GChannel0_17);
            PNL_FREE_MEM(pstEvaTbl->pu16BChannel0_17);
            PNL_FREE_MEM(pstEvaTbl->pu16RChannel1_17);
            PNL_FREE_MEM(pstEvaTbl->pu16GChannel1_17);
            PNL_FREE_MEM(pstEvaTbl->pu16BChannel1_17);
            return bMallocRet;
        }
    }
    return bMallocRet;
}
static void _MDrv_PNL_ConvertEVA_17to257_TBL(ST_PNL_EVA_TBL *pstEvaTbl)
{
#define EVA_CONVERT_UNIT (16)
    u16 u16Index = 0;
    u16 i = 0;

    if( PNL_RGB_LUT_CHECK(pstEvaTbl->pu16RChannel0, pstEvaTbl->pu16GChannel0, pstEvaTbl->pu16BChannel0) ||
        PNL_RGB_LUT_CHECK(pstEvaTbl->pu16RChannel1, pstEvaTbl->pu16GChannel1, pstEvaTbl->pu16BChannel1) ||
        PNL_RGB_LUT_CHECK(pstEvaTbl->pu16RChannel0_17, pstEvaTbl->pu16GChannel0_17, pstEvaTbl->pu16BChannel0_17) ||
        PNL_RGB_LUT_CHECK(pstEvaTbl->pu16RChannel1_17, pstEvaTbl->pu16GChannel1_17, pstEvaTbl->pu16BChannel1_17))
    {
        debug("[%s] Table error \n.", __FUNCTION__);
        return;
    }

    if(pstEvaTbl->u16TblSize == EVA_TABLE_MATRIX_SIZE_257X2)
    {
        return;
    }

    for (u16Index = 0; u16Index < EVA_TABLE_MATRIX_SIZE_257X2; u16Index ++) //0~256
    {
        i = u16Index/EVA_CONVERT_UNIT;
        if(i+1 < pstEvaTbl->u16TblSize)
        {
            //llut0
            pstEvaTbl->pu16RChannel0[u16Index] = ((pstEvaTbl->pu16RChannel0_17[i+1]-pstEvaTbl->pu16RChannel0_17[i])*(u16Index%EVA_CONVERT_UNIT))+
                                                  ((pstEvaTbl->pu16RChannel0_17[i])*EVA_CONVERT_UNIT);
            pstEvaTbl->pu16GChannel0[u16Index] = ((pstEvaTbl->pu16GChannel0_17[i+1]-pstEvaTbl->pu16GChannel0_17[i])*(u16Index%EVA_CONVERT_UNIT))+
                                                  ((pstEvaTbl->pu16GChannel0_17[i])*EVA_CONVERT_UNIT);
            pstEvaTbl->pu16BChannel0[u16Index] = ((pstEvaTbl->pu16BChannel0_17[i+1]-pstEvaTbl->pu16BChannel0_17[i])*(u16Index%EVA_CONVERT_UNIT))+
                                                  ((pstEvaTbl->pu16BChannel0_17[i])*EVA_CONVERT_UNIT);

            //llut1
            pstEvaTbl->pu16RChannel1[u16Index] = ((pstEvaTbl->pu16RChannel1_17[i+1]-pstEvaTbl->pu16RChannel1_17[i])*(u16Index%EVA_CONVERT_UNIT))+
                                                  ((pstEvaTbl->pu16RChannel1_17[i])*EVA_CONVERT_UNIT);
            pstEvaTbl->pu16GChannel1[u16Index] = ((pstEvaTbl->pu16GChannel1_17[i+1]-pstEvaTbl->pu16GChannel1_17[i])*(u16Index%EVA_CONVERT_UNIT))+
                                                  ((pstEvaTbl->pu16GChannel1_17[i])*EVA_CONVERT_UNIT);
            pstEvaTbl->pu16BChannel1[u16Index] = ((pstEvaTbl->pu16BChannel1_17[i+1]-pstEvaTbl->pu16BChannel1_17[i])*(u16Index%EVA_CONVERT_UNIT))+
                                                  ((pstEvaTbl->pu16BChannel1_17[i])*EVA_CONVERT_UNIT);
        }
        else // i=16 max value
        {
            pstEvaTbl->pu16RChannel0[u16Index]= pstEvaTbl->pu16RChannel0_17[i]*EVA_CONVERT_UNIT;
            pstEvaTbl->pu16GChannel0[u16Index]= pstEvaTbl->pu16GChannel0_17[i]*EVA_CONVERT_UNIT;
            pstEvaTbl->pu16BChannel0[u16Index]= pstEvaTbl->pu16BChannel0_17[i]*EVA_CONVERT_UNIT;

            pstEvaTbl->pu16RChannel1[u16Index]= pstEvaTbl->pu16RChannel1_17[i]*EVA_CONVERT_UNIT;
            pstEvaTbl->pu16GChannel1[u16Index]= pstEvaTbl->pu16GChannel1_17[i]*EVA_CONVERT_UNIT;
            pstEvaTbl->pu16BChannel1[u16Index]= pstEvaTbl->pu16BChannel1_17[i]*EVA_CONVERT_UNIT;
        }
    }
}

bool MDrv_PNL_TCON_DumpEVALutTab(u8 * pu8TconTab)
{
#if SUPPORT_VAC_256
    u16 u16TargetIndex = 0;
    u16 pu16max_value[EVA_MAX_VALUE_CNANNEL];
    pST_PNL_EVA_SUB_HEADER pstEvaSubHdr;
    bool bRetLut = FALSE, bChannelSeparate = FALSE;
    ST_PNL_EVA_TBL stEvaTbl;
    //bool bRet = TRUE;
    u16 u16Index;

    if (pu8TconTab == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return FALSE;
    }

    memcpy(pu16max_value, (pu8TconTab + EVA_MAX_VALUE_OFFSET),sizeof(u16)*EVA_MAX_VALUE_CNANNEL);
    pstEvaSubHdr = (pST_PNL_EVA_SUB_HEADER)(pu8TconTab + EVA_MAINHEADER_OFFSET);
    bChannelSeparate = pstEvaSubHdr->u8SeparateFlag & _BIT(0);

    debug("%s: channel seperate: %d\n",__FUNCTION__, bChannelSeparate);
    debug("%s: table matrix: %d\n",__FUNCTION__, pstEvaSubHdr->u8TableMatrix);
    debug("%s: table bit: %d\n",__FUNCTION__, pstEvaSubHdr->u8TableBit);
    for(u16Index = 0; u16Index<EVA_MAX_VALUE_CNANNEL; u16Index++)
    {
        debug("%s: channel:%d: max value: %d\n",__FUNCTION__,u16Index, pu16max_value[u16Index]);
    }
    memset(&stEvaTbl,0,sizeof(ST_PNL_EVA_TBL));
    stEvaTbl.u16TblSize = (pstEvaSubHdr->u8TableMatrix? EVA_TABLE_MATRIX_SIZE_257X2: EVA_TABLE_MATRIX_SIZE_17X2);

    if (_MDrv_EvaTbl_MemAllocate(&stEvaTbl) == FALSE)
    {
        goto finally;
    }

    u16TargetIndex = EVA_DATA_START;

    if(stEvaTbl.u16TblSize == EVA_TABLE_MATRIX_SIZE_17X2)
    {
        // get table from bin
        if (bChannelSeparate)
        {
            memcpy(stEvaTbl.pu16RChannel0_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16RChannel1_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut1
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16GChannel0_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16GChannel1_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut1
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16BChannel0_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16BChannel1_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut1
        }
        else
        {
            memcpy(stEvaTbl.pu16RChannel0_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut0
            memcpy(stEvaTbl.pu16GChannel0_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut0
            memcpy(stEvaTbl.pu16BChannel0_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16RChannel1_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut1
            memcpy(stEvaTbl.pu16GChannel1_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut1
            memcpy(stEvaTbl.pu16BChannel1_17, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut1
        }
        // replace last with max
        stEvaTbl.pu16RChannel0_17[stEvaTbl.u16TblSize-1] = pu16max_value[0]/16;
        stEvaTbl.pu16GChannel0_17[stEvaTbl.u16TblSize-1] = pu16max_value[1]/16;
        stEvaTbl.pu16BChannel0_17[stEvaTbl.u16TblSize-1] = pu16max_value[2]/16;
        stEvaTbl.pu16RChannel1_17[stEvaTbl.u16TblSize-1] = pu16max_value[3]/16;
        stEvaTbl.pu16GChannel1_17[stEvaTbl.u16TblSize-1] = pu16max_value[4]/16;
        stEvaTbl.pu16BChannel1_17[stEvaTbl.u16TblSize-1] = pu16max_value[5]/16;
        //convert to 257
        _MDrv_PNL_ConvertEVA_17to257_TBL(&stEvaTbl);
    }
    else
    {
        // get table from bin
        if (bChannelSeparate)
        {
            memcpy(stEvaTbl.pu16RChannel0, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16RChannel1, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut1
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16GChannel0, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16GChannel1, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut1
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16BChannel0, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16BChannel1, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut1
        }
        else
        {
            memcpy(stEvaTbl.pu16RChannel0, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut0
            memcpy(stEvaTbl.pu16GChannel0, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut0
            memcpy(stEvaTbl.pu16BChannel0, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut0
            u16TargetIndex += stEvaTbl.u16TblSize*2;
            memcpy(stEvaTbl.pu16RChannel1, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //R lut1
            memcpy(stEvaTbl.pu16GChannel1, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //G lut1
            memcpy(stEvaTbl.pu16BChannel1, (pu8TconTab+u16TargetIndex), sizeof(u16)*stEvaTbl.u16TblSize); //B lut1
        }
    }

    bRetLut = MHal_PNL_ADL_SetEva_TBL(&stEvaTbl);
    if(MHal_PNL_ADL_SetEva_TBL(&stEvaTbl) != TRUE)
    {
        // riu
        bRetLut = MHal_PNL_SetEva_TBL(&stEvaTbl);
    }

    if(bRetLut != TRUE)
    {
        debug(" Eva table fail \n.");
    }

finally:
    PNL_FREE_MEM(stEvaTbl.pu16RChannel0);
    PNL_FREE_MEM(stEvaTbl.pu16GChannel0);
    PNL_FREE_MEM(stEvaTbl.pu16BChannel0);
    PNL_FREE_MEM(stEvaTbl.pu16RChannel1);
    PNL_FREE_MEM(stEvaTbl.pu16GChannel1);
    PNL_FREE_MEM(stEvaTbl.pu16BChannel1);

    if(stEvaTbl.u16TblSize == EVA_TABLE_MATRIX_SIZE_17X2)
    {
        PNL_FREE_MEM(stEvaTbl.pu16RChannel0_17);
        PNL_FREE_MEM(stEvaTbl.pu16GChannel0_17);
        PNL_FREE_MEM(stEvaTbl.pu16BChannel0_17);
        PNL_FREE_MEM(stEvaTbl.pu16RChannel1_17);
        PNL_FREE_MEM(stEvaTbl.pu16GChannel1_17);
        PNL_FREE_MEM(stEvaTbl.pu16BChannel1_17);
    }
    return bRetLut;
#else
    return FALSE;
#endif
}

bool _MHal_PNL_Free_resource(void)
{
	PNL_FREE_MEM(file_buf);
	PNL_FREE_MEM(eva_buf);
	PNL_FREE_MEM(panel_gamma_buf);

	return TRUE;
}

void MHal_PNL_EnableTcon(struct udevice *dev)
{
    if (dev == NULL) {
        UBOOT_ERROR("Input invalid!\n");
        return;
    }
    MApi_PNL_TCONMAP_DumpTable(dev, (uint8_t*)file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_POWER_SEQUENCE_ON);
	//free tcon bin resource
	_MHal_PNL_Free_resource();
    return;
}

bool MApi_PNL_TCONMAP_DumpTable(struct udevice *dev, uint8_t* pTCONTable, uint8_t* pEVATable, uint8_t u8Tcontype)
{
    uint8_t* g_pu8PNLTCONTable = NULL;
    uint8_t* g_pu8EVATable = NULL;
    uint8_t u8TableType=0;
    uint16_t u16RegisterCount=0;
    uint8_t  u8RegisterType=0;
    uint32_t u32RegisterlistOffset=0;
    uint32_t u32RegisterlistSize=0;
    uint8_t u8TCON_Version = 0;
    //uint8_t u8PanelInterface = 0;


    if(pTCONTable == NULL)
    {
        debug("[%s] TCONTable error \n.", __FUNCTION__);
        return FALSE;
    }

    if(u8Tcontype == E_APIPNL_TCON_TAB_TYPE_EVA_TABLE)
    {
        if(pEVATable ==NULL)
        {
            debug("[%s] TCONTable error \n.", __FUNCTION__);
            return FALSE;
        }
        g_pu8EVATable = pEVATable;
        MDrv_PNL_TCON_DumpEVALutTab(g_pu8EVATable);
    }
    else
    {
        g_pu8PNLTCONTable = pTCONTable;

        u8TCON_Version = *((uint8_t*)(g_pu8PNLTCONTable));
        debug("[%s][%d][%d]TCON VERSION %d \n", __FUNCTION__, __LINE__, u8Tcontype, u8TCON_Version);

        g_pu8PNLTCONTable+=SKIP_TCON_MAIMHEADER; // skip 32 bytes Main header
        g_pu8PNLTCONTable+=SKIP_TCON_SUBHEADER; // skip 8byte   subheader

        if(u8TCON_Version > TCON20_VERSION)
        {
            g_pu8PNLTCONTable+=SKIP_TCON20_SUBHEADER; // skip 8byte TCON2.0 subheader
            //u8PanelInterface = *((uint8_t*)(g_pu8PNLTCONTable+SKIP_TCON20_PANETYPE)); //get panel Interface
        }
        // sn MAY NEED version , so there needs a way to pass this info.
        u8TableType           = *((uint8_t*) (g_pu8PNLTCONTable + (u8Tcontype * 8) + 0));
        u16RegisterCount      = ((*((uint8_t*)(g_pu8PNLTCONTable + (u8Tcontype * 8) + 2)))<<8) | *((uint8_t*)(g_pu8PNLTCONTable + (u8Tcontype * 8) + 1));
        u8RegisterType        = *((uint8_t*) (g_pu8PNLTCONTable + (u8Tcontype * 8) + 3));
        u32RegisterlistOffset = ((*((uint8_t*)  (g_pu8PNLTCONTable + (u8Tcontype * 8) + 7)))<<24) | ((*((uint8_t*)  (g_pu8PNLTCONTable + (u8Tcontype * 8) + 6)))<<16) | ((*((uint8_t*)  (g_pu8PNLTCONTable + (u8Tcontype * 8) + 5)))<<8) | *((uint8_t*)  (g_pu8PNLTCONTable + (u8Tcontype * 8) + 4));
        u32RegisterlistSize   = u16RegisterCount * _registerTypeToSize(u8RegisterType);

        debug("[%s][%d] u8TableType=%d u16RegisterCount=%d u8RegisterType=%d u32RegisterlistOffset=%d u32RegisterlistSize=%d\n", __FUNCTION__, __LINE__, u8TableType, u16RegisterCount,u8RegisterType,u32RegisterlistOffset,u32RegisterlistSize);

        //error handling
        if((u8TableType != u8Tcontype)||(u16RegisterCount == 0))
        {
            g_pu8PNLTCONTable -= (SKIP_TCON_MAIMHEADER + SKIP_TCON_SUBHEADER);
            if(u8TCON_Version > TCON20_VERSION)
            {
                g_pu8PNLTCONTable -= SKIP_TCON20_SUBHEADER;
            }
            return TRUE;
        }

        if(u8TCON_Version > TCON20_VERSION)
        {
            g_pu8PNLTCONTable+=(u32RegisterlistOffset-(SKIP_TCON_MAIMHEADER+SKIP_TCON_SUBHEADER+SKIP_TCON20_SUBHEADER));
        }
        else
        {
            g_pu8PNLTCONTable+=(u32RegisterlistOffset-(SKIP_TCON_MAIMHEADER+SKIP_TCON_SUBHEADER));
        }
        switch(u8Tcontype)
        {
            case E_APIPNL_TCON_TAB_TYPE_GENERAL:
                MDrv_PNL_TCON_DumpGENRegTab(dev,g_pu8PNLTCONTable,u16RegisterCount);
                break;
            case E_APIPNL_TCON_TAB_TYPE_GPIO:
                MDrv_PNL_TCON_DumpGpioRegTab(g_pu8PNLTCONTable,u16RegisterCount);
                break;
            case E_APIPNL_TCON_TAB_TYPE_SCALER:
                MDrv_PNL_TCON_DumpSCRegTab(g_pu8PNLTCONTable,u16RegisterCount);
                break;
            case E_APIPNL_TCON_TAB_TYPE_MOD:
                MDrv_PNL_TCON_DumpMODRegTab(g_pu8PNLTCONTable,u16RegisterCount);
                break;

            case E_APIPNL_TCON_TAB_TYPE_POWER_SEQUENCE_ON:
            case E_APIPNL_TCON_TAB_TYPE_POWER_SEQUENCE_OFF:
                if(u8TCON_Version > TCON20_VERSION)
                {
                    MDrv_PNL_TCON_DumpPowerSequenceRegTab(g_pu8PNLTCONTable,u16RegisterCount);
                }
                break;
            case E_APIPNL_TCON_TAB_TYPE_GAMMA:
                break;
            case E_APIPNL_TCON_TAB_TYPE_PANEL_INFO:
                if(u8TCON_Version > TCON20_VERSION)
                {
                   if( (E_PNL_TCON20_REGISTERTYPE)u8RegisterType ==  EN_TCON20_REGISTERTYPE_PANEL_6_BYTES_NEWSSC)
                   {
                       //MDrv_PNL_Set_SSC_EnableHighAccurate(pInstance,1);
                   }
                   else
                   {
                       //MDrv_PNL_Set_SSC_EnableHighAccurate(pInstance,0);
                   }
                   MDrv_PNL_TCON_DumpPanelInfo(dev,g_pu8PNLTCONTable,u32RegisterlistSize);
                   //stTCONPanelConfig.enPanelInterface = u8PanelInterface;
                }
                break;
            case E_APIPNL_TCON_TAB_TYPE_OVERDRIVER:
                if(u8TCON_Version > TCON20_VERSION)
                {
                    MDrv_PNL_TCON_DumpOverDriveRegTab(dev,g_pu8PNLTCONTable);
                }
                break;
            case E_APIPNL_TCON_TAB_TYPE_PCID:
                if(u8TCON_Version > TCON20_VERSION)
                {
                    MDrv_PNL_TCON_DumpPCIDRegTab(g_pu8PNLTCONTable);
                }
                break;
            case E_APIPNL_TCON_TAB_TYPE_LINE_OD_TABLE:
                if(u8TCON_Version > TCON20_VERSION)
                {
                    MDrv_PNL_TCON_DumpLineODLutTab(g_pu8PNLTCONTable);
                }
                break;
            case E_APIPNL_TCON_TAB_TYPE_LINE_OD_REG:
                if(u8TCON_Version > TCON20_VERSION)
                {
                    MDrv_PNL_TCON_DumpLineODRegTab(g_pu8PNLTCONTable, u16RegisterCount);
                }
                break;
            case E_APIPNL_TCON_TAB_TYPE_EVA_REG:
                if(u8TCON_Version > TCON20_VERSION)
                {
                    MDrv_PNL_TCON_DumpRegTab(g_pu8PNLTCONTable, u16RegisterCount);
                }
                break;
            default:
                debug("GetTable: unknown tcon type=%u> \n", u8Tcontype);
                break;
        }
    }
    return TRUE;
}

void Init_TCON_Panel(struct udevice *dev)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);
    UBOOT_TRACE("IN\n");
    if (priv == NULL) {
        UBOOT_ERROR("Get device private fail\n");
        return;
    }

    if(file_buf == NULL)
    {
        UBOOT_ERROR("Error: Read raw data file failure\n");
        //return -1;
    }
    else
    {

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf,NULL,E_APIPNL_TCON_TAB_TYPE_GENERAL);

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf,NULL,E_APIPNL_TCON_TAB_TYPE_GPIO);

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf,NULL,E_APIPNL_TCON_TAB_TYPE_SCALER);

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf,NULL,E_APIPNL_TCON_TAB_TYPE_MOD);

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf,NULL,E_APIPNL_TCON_TAB_TYPE_PANEL_INFO); // verison 2 new panel table

        //MApi_PNL_TCONMAP_DumpTable(dev, file_buf,E_APIPNL_TCON_TAB_TYPE_PCID);
        //MApi_PNL_TCONMAP_DumpTable(dev, file_buf, E_APIPNL_TCON_TAB_TYPE_LINE_OD_REG);
        //MApi_PNL_TCONMAP_DumpTable(dev, file_buf, E_APIPNL_TCON_TAB_TYPE_LINE_OD_TABLE);
        //MApi_PNL_TCONMAP_DumpTable(dev, file_buf, E_APIPNL_TCON_TAB_TYPE_EVA_REG);

        if (mtk_pnl_autodownload_init(dev) == FALSE)
        {
            UBOOT_ERROR("Error: autodownload init failed\n");
        }

        if(eva_buf != NULL && eva_size > 0)
        {

            MApi_PNL_TCONMAP_DumpTable(dev, file_buf, eva_buf, E_APIPNL_TCON_TAB_TYPE_EVA_TABLE);
			MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_EVA_REG);
        }

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL,E_APIPNL_TCON_TAB_TYPE_LINE_OD_TABLE);

        MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL,E_APIPNL_TCON_TAB_TYPE_LINE_OD_REG);
    }
    UBOOT_TRACE("OUT\n");
}

void Init_TCON_Path(struct udevice *dev, bool dlg_mode)
{

    struct mtk_panel_priv *priv = dev_get_priv(dev);
	char chFilePath[BIN_FILE_PATH_LENGTH];
	bool is_dlg = dlg_mode;

    if (priv == NULL) {
        UBOOT_ERROR("Get device private fail\n");
        return;
    }
	memset(chFilePath, '\0', sizeof(chFilePath));

	//load tcon bin
	if (priv->tcon_info.tcon_bin_path || priv->tcon_info.tcon_dlg_bin_path)	{
		if (is_dlg) {
			if (priv->tcon_info.tcon_dlg_bin_path)
				strncpy(chFilePath, priv->tcon_info.tcon_dlg_bin_path, sizeof(chFilePath) - 1);
		} else {
			if (priv->tcon_info.tcon_bin_path)
				strncpy(chFilePath, priv->tcon_info.tcon_bin_path, sizeof(chFilePath) - 1);
		}
		UBOOT_TRACE("tcon: isDLG=%d, bin path %s\n", is_dlg, chFilePath);
		file_buf = (u8 *)read_storage_file_to_memory("tvconfig", chFilePath, &tcon_size);
	}

	//if not found, load tcon bin from default path
	if (!file_buf) {
		UBOOT_TRACE("read tcon bin file from /bsp/common/TCON_BIN/TCON20.bin\n");
		file_buf = (u8 *)read_storage_file_to_memory("tvconfig", TCON_DEFAUL_PATH_AOSP, &tcon_size);
	}
	if (!file_buf) {
		UBOOT_TRACE("read tcon bin file from tcon/TCON20.bin\n");
		file_buf = (u8 *)read_storage_file_to_memory("tvconfig", TCON_DEFAUL_PATH_MI, &tcon_size);
	}
	/*  The Linux Path is aligned with AOSP
	 *  if (file_buf == NULL) {
	 *	UBOOT_TRACE("read tcon bin file from config/tcon/TCON20.bin\n");
	 *	file_buf = (u8 *)read_storage_file_to_memory("tvconfig", TCON_DEFAUL_PATH_LINUX, &size);
	 *  }
	 */

	if (file_buf) {
	    eva_buf = (u8 *)read_storage_file_to_memory("tvconfig", EVA_DEFAUL_PATH_MI, &eva_size);
		if (!eva_buf)
			eva_buf = (u8 *)read_storage_file_to_memory("tvconfig", EVA_DEFAUL_PATH_AOSP, &eva_size);
		/*  The Linux Path is aligned with AOSP
		 *  if (eva_buf == NULL)
		 *	eva_buf = (u8 *)read_storage_file_to_memory("tvconfig", EVA_DEFAUL_PATH_LINUX, &eva_size);
		 */
	}

	UBOOT_DEBUG("tcon size=%lld\n", tcon_size);
    //debug("\033[0;32;31m [%s][%s][%d] 0x%X\n\033[m", __FILE__, __FUNCTION__, __LINE__, file_buf[0]);
    //debug("\033[0;32;31m [%s][%s][%d] 0x%X\n\033[m", __FILE__, __FUNCTION__, __LINE__, file_buf[1]);
	UBOOT_DEBUG("eva size=%lld\n", eva_size);
    //debug("\033[0;32;31m [%s][%s][%d] eva_buf[0] 0x%X\n\033[m", __FILE__, __FUNCTION__, __LINE__, eva_buf[0]);
    //debug("\033[0;32;31m [%s][%s][%d] eva_buf[1] 0x%X\n\033[m", __FILE__, __FUNCTION__, __LINE__, eva_buf[1]);

    if(file_buf == NULL)
    {
        priv->tcon_info.bUsingTCON = false;
        UBOOT_DEBUG("Error: Read tcon bin file failure\n");
        //return -1;
    }
    else
    {
		if (tcon_size > 0)
			MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_PANEL_INFO);
    }
}

void Init_TCON_Pq(struct udevice *dev)
{
	if (eva_buf && eva_size > 0) {
		MApi_PNL_TCONMAP_DumpTable(dev, file_buf, eva_buf, E_APIPNL_TCON_TAB_TYPE_EVA_TABLE);
		MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_EVA_REG);
	}
	if (file_buf && tcon_size > 0) {
		MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_EVA_REG);
		MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_LINE_OD_REG);
		MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_LINE_OD_TABLE);
	}

	_MHal_PNL_Free_resource();
}

void Init_TCON_Pq_Path(struct udevice *dev, struct st_tcon_pq_force_en force_en)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("Get device private fail\n");
		return;
	}
	if (!file_buf && force_en.force_enable && force_en.tcon_pq_bin_path)
		file_buf = (uint8_t *)read_storage_file_to_memory("tvconfig", force_en.tcon_pq_bin_path, &tcon_size);

	if (!eva_buf && force_en.force_enable && force_en.eva_bin_path)
		eva_buf = (uint8_t *)read_storage_file_to_memory("tvconfig", force_en.eva_bin_path, &eva_size);
	UBOOT_DEBUG("tcon pq size=%lld\n", tcon_size);
	UBOOT_DEBUG("eva size=%lld\n", eva_size);
}

#if (CONFIG_HAPS == 1)
static void _mtk_panelgamma_verify(struct udevice *dev)
{
    u32 u32I;
    //open pnl bin
    loff_t size;
    unsigned char* file_buf;
    bool bret = FALSE;

    UBOOT_DEBUG("read panel_gamma bin file from config/gamma/panel_gamma.bin\n");
    file_buf = read_storage_file_to_memory("tvconfig", "gamma/panel_gamma.bin", &size);
    if(file_buf == NULL)
    {
		UBOOT_ERROR("Error: Read raw data file failure\n");
        return;
    }

    // Read the panel gamma value from Bin
    ST_PNL_PNLGAMMATBL pstGetPNLGammaTbl;
    memset(&pstGetPNLGammaTbl,0,sizeof(ST_PNL_PNLGAMMATBL));
    pstGetPNLGammaTbl.enPnlGammaTbl = E_PNL_PNLGAMMA_TBL_FROM_BIN;
    pstGetPNLGammaTbl.pu8GammaTbl = (u8*)file_buf;
    pstGetPNLGammaTbl.u32TblSize = (u32) size;//64*32*8;
    pstGetPNLGammaTbl.u16Index = 0;
    pstGetPNLGammaTbl.u16Size = 16*64;
    pstGetPNLGammaTbl.pu16RChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16GChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16BChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16WChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16RChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16GChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16BChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.pu16WChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl.u32Version = ST_PNL_PNLGAMMATBL_VERSION;
    pstGetPNLGammaTbl.u32Length = sizeof(ST_PNL_PNLGAMMATBL);

    MDrv_PNL_GetPanelGammaTbl(dev, &pstGetPNLGammaTbl);

    // read the panel gamma value from reg.
    ST_PNL_PNLGAMMATBL pstGetPNLGammaTbl_reg;
    memset(&pstGetPNLGammaTbl_reg,0,sizeof(ST_PNL_PNLGAMMATBL));
    pstGetPNLGammaTbl_reg.enPnlGammaTbl = E_PNL_PNLGAMMA_TBL_FROM_REG;
    pstGetPNLGammaTbl_reg.pu8GammaTbl = (u8*)file_buf;
    pstGetPNLGammaTbl_reg.u32TblSize = (u32) size;//64*32*8;
    pstGetPNLGammaTbl_reg.u16Index = 0;
    pstGetPNLGammaTbl_reg.u16Size = 16*64;
    pstGetPNLGammaTbl_reg.pu16RChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16GChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16BChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16WChannel0 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16RChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16GChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16BChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.pu16WChannel1 = (u16*) malloc(sizeof(u16)*1024);
    pstGetPNLGammaTbl_reg.u32Version = ST_PNL_PNLGAMMATBL_VERSION;
    pstGetPNLGammaTbl_reg.u32Length = sizeof(ST_PNL_PNLGAMMATBL);
    MDrv_PNL_GetPanelGammaTbl(dev, &pstGetPNLGammaTbl_reg);

    // compare the data
    bret = TRUE;
    for (u32I = 0 ; u32I < 1024; u32I++)
    {
        if(*(pstGetPNLGammaTbl_reg.pu16RChannel0 + u32I) != *(pstGetPNLGammaTbl.pu16RChannel0 + u32I))
        {
			UBOOT_DEBUG("not same idx=%u, bin:%x, reg:%x\033[0m \n", u32I, *(pstGetPNLGammaTbl.pu16RChannel0 + u32I), *(pstGetPNLGammaTbl_reg.pu16RChannel0 + u32I));
            bret = FALSE;
            break;
        }
        if(*(pstGetPNLGammaTbl_reg.pu16GChannel0 + u32I) != *(pstGetPNLGammaTbl.pu16GChannel0 + u32I))
        {
			UBOOT_DEBUG(" not same idx=%u, bin:%x, reg:%x\033[0m \n", u32I, *(pstGetPNLGammaTbl.pu16GChannel0 + u32I), *(pstGetPNLGammaTbl_reg.pu16GChannel0 + u32I));
            bret = FALSE;
            break;
        }
        if(*(pstGetPNLGammaTbl_reg.pu16BChannel0 + u32I) != *(pstGetPNLGammaTbl.pu16BChannel0 + u32I))
        {
			UBOOT_DEBUG(" not same idx=%u, bin:%x, reg:%x\033[0m \n", u32I, *(pstGetPNLGammaTbl.pu16BChannel0 + u32I), *(pstGetPNLGammaTbl_reg.pu16BChannel0 + u32I));
            bret = FALSE;
            break;
        }

    }
    if(bret == TRUE)
    {
		UBOOT_DEBUG("panel gamma verify: OK!!!\033[0m \n");
    }
    else
    {
		UBOOT_DEBUG("panel gamma verify: NG!!!\033[0m \n");
    }
    return;
}
#endif

void mtk_panelgamma_setting(struct udevice *dev, bool dlg_mode)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        UBOOT_ERROR("Get device private fail\n");
        return;
    }

    if(priv->tcon_info.bPanelGammaEn)
    {
		bool is_dlg = dlg_mode;
		char chPanelGammaPath[BIN_FILE_PATH_LENGTH] = "\0";
		bool bret = FALSE;
		size_t pathLength = sizeof(chPanelGammaPath) - 1;

		if (priv->tcon_info.panelgamma_bin_path || priv->tcon_info.panelgamma_dlg_bin_path)	{
			if (is_dlg)	{
				if (priv->tcon_info.panelgamma_dlg_bin_path) {
					strncpy(chPanelGammaPath, priv->tcon_info.panelgamma_dlg_bin_path, pathLength);
					chPanelGammaPath[pathLength] = '\0'; // Ensure null termination
				}
			} else {
				if (priv->tcon_info.panelgamma_bin_path) {
					strncpy(chPanelGammaPath, priv->tcon_info.panelgamma_bin_path, pathLength);
					chPanelGammaPath[pathLength] = '\0'; // Ensure null termination
				}
			}
			debug("panel gamma is_dlg=%d, bin path %s\n", is_dlg, chPanelGammaPath);
			panel_gamma_buf = (u8 *)read_storage_file_to_memory("tvconfig", chPanelGammaPath, &panel_gamma_size);
		}

		//if not found, load tcon bin from default path
		if (!panel_gamma_buf) {
			debug("read panel_gamma bin file from gamma/panel_gamma.bin %s %d\n", __func__, __LINE__);
			panel_gamma_buf = (u8 *)read_storage_file_to_memory("tvconfig",
				PANELGAMMA_DEFAULT_PATH_MI, &panel_gamma_size);
		}
		if (!panel_gamma_buf) {
			debug("read tcon bin file from /bsp/common/GAMMA_BIN/panel_gamma.bin %s %d\n", __func__, __LINE__);
			panel_gamma_buf = (u8 *)read_storage_file_to_memory("tvconfig",
				PANELGAMMA_DEFAULT_PATH_AOSP, &panel_gamma_size);
		}
		/*	The Linux Path is aligned with AOSP
		 *	if(panel_gamma_buf == NULL) {
		 *	debug("read tcon bin file from config/gamma/panel_gamma.bin %s %d\n", __func__, __LINE__);
		 *	panel_gamma_buf = (u8 *)read_storage_file_to_memory("tvconfig",
		 *	PANELGAMMA_DEFAULT_PATH_LINUX, &panel_gamma_size);
		 *	}
		 */
		if (!panel_gamma_buf) {
			dev_err(dev, "Error: Read panel gamma bin failure\n");
			return;
		}
		debug("\033[0;32;31m [%s][%s][%d] size=%lld\n\033[m", __FILE__, __func__, __LINE__, panel_gamma_size);
		debug("\033[0;32;31m [%s][%s][%d] 0x%X\n\033[m", __FILE__, __func__, __LINE__, panel_gamma_buf[0]);
		debug("\033[0;32;31m [%s][%s][%d] 0x%X\n\033[m", __FILE__, __func__, __LINE__, panel_gamma_buf[1]);

		if (panel_gamma_size > 0)
        {
            mtk_pnl_autodownload_init(dev);
			bret = MApi_PNL_SetPanelGammaBIN(dev, panel_gamma_buf, (u32)panel_gamma_size, 0);
            if (bret != TRUE)
            {
                UBOOT_DEBUG("MApi_PNL_SetPanelGammaBIN fail\n");
            }
#if (CONFIG_HAPS == 1)
            _mtk_panelgamma_verify(dev);
#endif
        }
    }
}

void mtk_overdrive_setting(struct udevice *dev)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        UBOOT_ERROR("Get device private fail\n");
        return;
    }

    UBOOT_DEBUG("bOverDriveEn=%d\n", priv->tcon_info.bOverDriveEn);

#ifndef HEX_02
#define HEX_02 (0x02)
#endif
#ifndef HEX_03
#define HEX_03 (0x03)
#endif
	//patch for OD
		UBOOT_DEBUG("For OverDrive setting, Set HV scaling and H/V size first.\n");
		W2BYTEMSK(REG_01BC_OD_1ST_BKA336_V004, priv->de_width, REG_01BC_OD_1ST_BKA336_V004_REG_H_SIZE_01BC);
		W2BYTEMSK(REG_003C_OD_2ND_BKA337_V004, priv->de_height, REG_003C_OD_2ND_BKA337_V004_REG_V_SIZE_003C);
		W2BYTEMSK(REG_01B0_OD_1ST_BKA336_V004, HEX_03, Fld(HEX_02, 0, AC_MSKB0));//Enable VScaling HScaling together
/* //OverDrive Init at kernel
    if (priv->tcon_info.bOverDriveEn)
    {
        if(file_buf == NULL)
        {
            UBOOT_ERROR("Error: Read raw data file failure\n");
            return;
        }

        if (MApi_PNL_TCONMAP_DumpTable(dev, file_buf, NULL, E_APIPNL_TCON_TAB_TYPE_OVERDRIVER) == TRUE)
        {
            MHal_PNL_OverDriver_Enable(TRUE);
        }
        else
        {
            MHal_PNL_OverDriver_Enable(FALSE);
        }
    }
    else
    {
        MHal_PNL_OverDriver_Enable(FALSE);
    }
*/
	UBOOT_DEBUG("OverDrive Initialize at kernel, skip it.\n");
}

bool mtk_pnl_get_property(struct udevice *dev, int enType, int *pVal)
{
    bool nRet = TRUE;
    struct mtk_panel_priv *priv = dev_get_priv(dev);

    if (priv == NULL) {
        UBOOT_ERROR("get device private fail\n");
        return FALSE;
    }

    if (pVal == NULL) {
        UBOOT_ERROR("input parameter is null\n");
        return FALSE;
    }

    switch (enType) {
    case E_PNL_PROP_TCON_EN:
        *pVal = priv->tcon_info.bUsingTCON;
        UBOOT_TRACE("Tcon enable=%d\n", *pVal);
        break;
    case E_PNL_PROP_VGH_DELAY:
        *pVal = priv->tcon_info.vghDelay;
        UBOOT_TRACE("VGH delay=%d\n", *pVal);
        break;
    case E_PNL_PROP_DEMURA_SEL:
        *pVal = priv->tcon_info.stPanelInfo.u32Demura_sel;
        nRet = (priv->tcon_info.bUsingTCON) ? TRUE : FALSE;
        UBOOT_TRACE("Demura_sel=%d nRet=%d\n", *pVal, nRet);
        break;
    case E_PNL_PROP_VCOM_SEL:
        *pVal = priv->tcon_info.stPanelInfo.u32Vcom_sel;
        nRet = (priv->tcon_info.bUsingTCON) ? TRUE : FALSE;
        UBOOT_TRACE("Vcom_sel=%d nRet=%d\n", *pVal, nRet);
        break;
    case E_PNL_PROP_DEMURA_EN:
        *pVal = priv->tcon_info.stPanelInfo.u32DemuraEnable;
        nRet = (priv->tcon_info.bUsingTCON) ? TRUE : FALSE;
        UBOOT_TRACE("Demura_en=%d nRet=%d\n", *pVal, nRet);
        break;
	case E_PNL_PROP_AUTO_PGA_UPDATE:
		*pVal = priv->tcon_info.u32AutoPga;
		UBOOT_TRACE("Auto PGA sel=%d\n", *pVal);
		break;
	case E_PNL_PROP_AUTO_P2P_CMD_UPDATE:
		*pVal = priv->tcon_info.u32P2pCmdUpdate;
		UBOOT_TRACE("p2p cmd update=%d\n", *pVal);
		break;
	case E_PNL_PROP_STI_ARCH:
		*pVal = priv->tcon_info.dmc_bypass_wfs;
		UBOOT_TRACE("dmc_bypass_wfs=%d\n", *pVal);
		break;
	default:
		UBOOT_ERROR("Invalid type %u!\n", enType);
		nRet = FALSE;
		break;
	}
	return nRet;
}

int _mtk_panel_update_acc_gamma_mmap_addr(struct mtk_panel_priv *priv, u64 *u64Address)
{
	struct dts_mmap mmap;
	int ret = 0;

	if (priv->tcon_info.u32AutoPga == 0) {
		UBOOT_TRACE("Auto PGA is disable.\n");
		ret = -EINVAL;
		goto AUTOPANELGAMMAEXIT;
	}
	memset(&mmap, 0, sizeof(mmap));
	ret = parse_dt("/mmap_info/MI_DISP_ACC_GAMMA", mmap_dt_parser, (void *)&mmap, "reg");
	if (ret < 0 || mmap.address == 0) {
		UBOOT_ERROR("Error: Get MI_DISP_ACC_GAMMA_BUF buffer from DTS mmap failure\n");
		ret = -ENXIO;
		goto AUTOPANELGAMMAEXIT;
	} else {
		UBOOT_DEBUG("ACC BUS ADDRESS=%llx", mmap.address);
		*u64Address = mmap.address;//BA address
		UBOOT_DEBUG("acc gamma address = %llx, size = %llx\n",
			    mmap.address, mmap.size);
	}
AUTOPANELGAMMAEXIT:

	return ret;
}

bool mtk_pnl_set_property(struct udevice *dev, int enType, u8 *pVal)
{
	#define ACC_VERIFY_NUM (0x78)
	#define OFFSET8 (8)
	#define CHECKSUM_BYTE (2)
	bool nRet = TRUE;
	MS_PNL_PNLGAMMA_Config stPNLGammaConfig;
	int u32StartAddress = 0;
	int u32index = 0;
	bool bReturn;
	u8 u8Gamma[CSPI_GAMMA_SIZE_120HZ] = {0x00};
	u8 u8Index = 0;
	u8 *pnl_gamma_buf = NULL;
	loff_t pnl_gamma_len = 0;
	u64 u64acc_gamma_addr = 0;
	u8 *u8acc_gamma_buf = NULL;
	u16 u16checksum = 0;
	int ret_mmap = 0;

	if (is_tcon_sti_flow()) {
		is_pnlgamma_data_exist(&pnl_gamma_buf, &pnl_gamma_len);
	} else {
		pnl_gamma_buf = panel_gamma_buf;
		pnl_gamma_len = panel_gamma_size;
	}

	if (!dev || !pVal || !pnl_gamma_buf) {
		UBOOT_ERROR("Invalid input data!!!\n");
		return FALSE;
	}

	struct mtk_panel_priv *priv = dev_get_priv(dev);

	if (!priv) {
		UBOOT_ERROR("get device private fail\n");
		return FALSE;
	}

	switch (enType) {
	case E_SET_PNL_PROP_AUTO_PGA_120Hz:
		memset(&stPNLGammaConfig, 0, sizeof(MS_PNL_PNLGAMMA_Config));
		memcpy(&stPNLGammaConfig, (pnl_gamma_buf + PANEL_GAMMA_MAINHEADER_LEN), sizeof(MS_PNL_PNLGAMMA_Config));

		// get auto acc gamma MMAP BA address(need request MMAP to add this code)
		ret_mmap = _mtk_panel_update_acc_gamma_mmap_addr(priv, &u64acc_gamma_addr);

		// only 2d case
		u32StartAddress = stPNLGammaConfig.u32Table2DStartAddress;
		UBOOT_DEBUG("u32StartAddress = 0x%x\n", u32StartAddress);
		UBOOT_DEBUG("bGamma2LutEnable = 0x%x\n", stPNLGammaConfig.bGamma2LutEnable);
		if (u32StartAddress < (PANEL_GAMMA_MAINHEADER_LEN + PANEL_GAMMA_MAINHEADER_LEN)) {
			UBOOT_ERROR("Get panel gamma data start address error, pls check bin file!!!\n");
			return FALSE;
		}
		for (u32index = 0 ; u32index < AUTO_PANEL_GAMMA_DATA_SIZE; u32index++) {
		//LUT 0
			pnl_gamma_buf[u32StartAddress + u32index] = pVal[u32index];
			u16checksum += pnl_gamma_buf[u32StartAddress + u32index];
		}

		if (stPNLGammaConfig.bGamma2LutEnable) {
			//skip LUT0 RGBW channel
			u32StartAddress += (AUTO_PANEL_GAMMA_DATA_SIZE + PANEL_GAMMA_PRE_CHANNEL_LEN);
			for (u32index = 0 ; u32index < AUTO_PANEL_GAMMA_DATA_SIZE; u32index++) {
				//LUT 1
				pnl_gamma_buf[u32StartAddress] = pVal[u32index];
			}
		}

		if (ret_mmap == 0) {
			u8acc_gamma_buf = (u8 *)u64acc_gamma_addr;
			memcpy(u8acc_gamma_buf, pnl_gamma_buf,
				  u32StartAddress + AUTO_PANEL_GAMMA_DATA_SIZE);
			// Add checksum
			u8acc_gamma_buf[u32StartAddress + AUTO_PANEL_GAMMA_DATA_SIZE] =
			(u8)u16checksum;
			u8acc_gamma_buf[u32StartAddress + AUTO_PANEL_GAMMA_DATA_SIZE + 1] =
				(u8)(u16checksum >> OFFSET8);
			u8acc_gamma_buf[u32StartAddress + AUTO_PANEL_GAMMA_DATA_SIZE + CHECKSUM_BYTE] =
				(u8)ACC_VERIFY_NUM;
			UBOOT_DEBUG("AutoAccGamma u16checksum=%x\n", u16checksum);
			UBOOT_DEBUG("AutoAccGamma ACC_VERIFY_NUM=%x\n",
				    u8acc_gamma_buf[u32StartAddress + AUTO_PANEL_GAMMA_DATA_SIZE + CHECKSUM_BYTE]);
		} else {
			UBOOT_DEBUG("AutoAccGamma not support or MMAP not exist\n");
		}

		UBOOT_DUMP(pnl_gamma_buf, 0x200);
		UBOOT_DEBUG(" bPanelGammaEn = 0x%x\n", priv->tcon_info.bPanelGammaEn);
		if (priv->tcon_info.bPanelGammaEn) {
			mtk_pnl_autodownload_init(dev);
			bReturn = MApi_PNL_SetPanelGammaBIN(dev, pnl_gamma_buf, (u32)pnl_gamma_len, 0);
			if (!bReturn) {
				nRet = FALSE;
				UBOOT_DEBUG("Set Auto panel gamma fail!\n");
			}
		} else {
			nRet = FALSE;
			UBOOT_DEBUG("Panel gamma need to be initialized!\n");
		}

		nRet = TRUE;
		break;
	case E_SET_PNL_PROP_AUTO_PGA_60Hz:
		nRet = FALSE;
		break;
	case E_SET_PNL_PROP_CSPI_CMD_UPDATE:
		// TCBANK2 0x2442
		// CSOT 120Hz UHD, update SET14-SET20 AND SET23-SET29
		memcpy(u8Gamma, pVal, CSPI_GAMMA_SIZE_120HZ);
		W2BYTEMSK(REG_010C_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0110_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0110_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0114_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0114_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0118_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0118_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_011C_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_011C_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0120_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0120_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0124_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0124_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0128_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0128_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_012C_TCON_SET_V005, u8Gamma[u8Index], Fld(8, 0, AC_FULLB0)); //[7:0]
		nRet = TRUE;
		break;
	case E_SET_PNL_PROP_CEDS_CMD_UPDATE:
		nRet = FALSE;
		break;
	case E_SET_PNL_PROP_USIT_CMD_UPDATE:
		memcpy(u8Gamma, pVal, USIT_GAMMA_SIZE_120HZ);
		// TCBANK2 0x2442,reg 0x55~0x5B
		// CSOT USIT 120Hz UHD,Gamma 2~8/11~17
		W2BYTEMSK(REG_0154_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0154_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0158_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0158_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_015C_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_015C_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0160_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0160_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0164_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0164_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_0168_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_0168_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		++u8Index;
		W2BYTEMSK(REG_016C_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, DEC_8, AC_FULLB1)); //[15:8]
		++u8Index;
		W2BYTEMSK(REG_016C_TCON_SET_V005, u8Gamma[u8Index], Fld(DEC_8, 0, AC_FULLB0)); //[7:0]
		UBOOT_TRACE("Set USIT Gamma Done!\n");
		nRet = TRUE;
		break;
    default:
        UBOOT_ERROR("Invalid type %u!\n", enType);
        nRet = FALSE;
        break;
    }

	#undef CHECKSUM_BYTE
	#undef OFFSET8
	#undef ACC_VERIFY_NUM

    return nRet;
}

void mtk_testpattern_settings(struct udevice *dev)
{
    struct mtk_panel_priv *priv = dev_get_priv(dev);
    char *pattern_id = env_get("test_pattern");
    en_boot_test_pattern_config pat_id = E_BOOT_TEST_PATTERN_NONE;
    pat_id = mst_atoi(pattern_id);
    UBOOT_DEBUG("get pat_id=%d, de_height=0x%x, de_width=0x%x\n", pat_id, priv->de_height, priv->de_width);

    if ((priv == NULL) || (pat_id <= E_BOOT_TEST_PATTERN_NONE) || (pat_id >= E_BOOT_TEST_PATTERN_MAX)) {
        UBOOT_DEBUG("Invalid iniput parameters!\n");
        return;
    }

    // TCON pattern
    if(pat_id == E_BOOT_TEST_PATTERN_TCON) {
        W2BYTEMSK(REG_0120_PATGEN_SCALER_BKA409, 0x00, REG_0120_PATGEN_SCALER_BKA409_REG_DIFF_H_MSB_0120);
        W2BYTEMSK(REG_0124_PATGEN_SCALER_BKA409, 0x40, REG_0124_PATGEN_SCALER_BKA409_REG_DIFF_H_LSB_0124);
        W2BYTEMSK(REG_0140_PATGEN_SCALER_BKA409, 0x00, REG_0140_PATGEN_SCALER_BKA409_REG_DIFF_V_MSB_0140);
        W2BYTEMSK(REG_0144_PATGEN_SCALER_BKA409, 0x20, REG_0144_PATGEN_SCALER_BKA409_REG_DIFF_V_LSB_0144);

        W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA409, priv->de_width, REG_0170_PATGEN_SCALER_BKA409_REG_H_SIZE_0170);
        W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA409, priv->de_height, REG_0174_PATGEN_SCALER_BKA409_REG_V_SIZE_0174);

        W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, 0x1, REG_0104_PATGEN_SCALER_BKA409_REG_DB_EN_0104);
        W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, 0x0, REG_0104_PATGEN_SCALER_BKA409_REG_BYPASS_PATGEN_SCALER_0104);
    }
    // PAFRC_post pattern
    else if(pat_id == E_BOOT_TEST_PATTERN_PAFRC_POST) {
        W2BYTEMSK(REG_00A0_PATGEN_SCALER_BKA407, 0x00, REG_00A0_PATGEN_SCALER_BKA407_REG_DIFF_H_MSB);
        W2BYTEMSK(REG_00A4_PATGEN_SCALER_BKA407, 0x40, REG_00A4_PATGEN_SCALER_BKA407_REG_DIFF_H_LSB);
        W2BYTEMSK(REG_00C0_PATGEN_SCALER_BKA407, 0x00, REG_00C0_PATGEN_SCALER_BKA407_REG_DIFF_V_MSB);
        W2BYTEMSK(REG_00C4_PATGEN_SCALER_BKA407, 0x20, REG_00C4_PATGEN_SCALER_BKA407_REG_DIFF_V_LSB);

        W2BYTEMSK(REG_00F0_PATGEN_SCALER_BKA407, priv->de_width, REG_00F0_PATGEN_SCALER_BKA407_REG_H_SIZE);
        W2BYTEMSK(REG_00F4_PATGEN_SCALER_BKA407, priv->de_height, REG_00F4_PATGEN_SCALER_BKA407_REG_V_SIZE);

        W2BYTEMSK(REG_0084_PATGEN_SCALER_BKA407, 0x1, REG_0084_PATGEN_SCALER_BKA407_REG_DB_EN);
        W2BYTEMSK(REG_0084_PATGEN_SCALER_BKA407, 0x0, REG_0084_PATGEN_SCALER_BKA407_REG_BYPASS_PATGEN_SCALER);
    }
    // MOD pattern
    else if (pat_id == E_BOOT_TEST_PATTERN_MOD_H_HALF) {
        W2BYTEMSK(REG_0198_MODV11_V005, 0X03FF, REG_0198_MODV11_V005_REG_TEST_COLOR_R_0198);
        W2BYTEMSK(REG_019C_MODV11_V005, 0X03FF, REG_019C_MODV11_V005_REG_TEST_COLOR_G_019C);
        W2BYTEMSK(REG_01A0_MODV11_V005, 0X03FF, REG_01A0_MODV11_V005_REG_TEST_COLOR_B_01A0);
        W2BYTEMSK(REG_0184_MODV11_V005, 0x00, REG_0184_MODV11_V005_REG_TEST_H_LINE_ST_0184);
        W2BYTEMSK(REG_0188_MODV11_V005, priv->de_width / 2, REG_0188_MODV11_V005_REG_TEST_H_LINE_END_0188);

        W2BYTEMSK(REG_0180_MODV11_V005, 0x00, REG_0180_MODV11_V005_REG_TEST_MODE_0180);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_H_LINE_MODE_0180);
	W2BYTEMSK(REG_0180_MODV11_V005, REG_0001, REG_0180_MODV11_V005_REG_TEST_ENGINE_0180);
    }
    else if (pat_id == E_BOOT_TEST_PATTERN_MOD_H_HALF_INV) {
        W2BYTEMSK(REG_0198_MODV11_V005, 0X03FF, REG_0198_MODV11_V005_REG_TEST_COLOR_R_0198);
        W2BYTEMSK(REG_019C_MODV11_V005, 0X03FF, REG_019C_MODV11_V005_REG_TEST_COLOR_G_019C);
        W2BYTEMSK(REG_01A0_MODV11_V005, 0X03FF, REG_01A0_MODV11_V005_REG_TEST_COLOR_B_01A0);
        W2BYTEMSK(REG_0184_MODV11_V005, 0x0000, REG_0184_MODV11_V005_REG_TEST_H_LINE_ST_0184);
        W2BYTEMSK(REG_0188_MODV11_V005, priv->de_width / 2, REG_0188_MODV11_V005_REG_TEST_H_LINE_END_0188);

        W2BYTEMSK(REG_0180_MODV11_V005, 0x00, REG_0180_MODV11_V005_REG_TEST_MODE_0180);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_H_LINE_MODE_0180);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_H_INV_0180);
	W2BYTEMSK(REG_0180_MODV11_V005, REG_0001, REG_0180_MODV11_V005_REG_TEST_ENGINE_0180);
    }
    else if (pat_id == E_BOOT_TEST_PATTERN_MOD_V_HALF) {
        W2BYTEMSK(REG_0198_MODV11_V005, 0X03FF, REG_0198_MODV11_V005_REG_TEST_COLOR_R_0198);
        W2BYTEMSK(REG_019C_MODV11_V005, 0X03FF, REG_019C_MODV11_V005_REG_TEST_COLOR_G_019C);
        W2BYTEMSK(REG_01A0_MODV11_V005, 0X03FF, REG_01A0_MODV11_V005_REG_TEST_COLOR_B_01A0);
        W2BYTEMSK(REG_018C_MODV11_V005, 0x0000, REG_018C_MODV11_V005_REG_TEST_V_LINE_ST_018C);
        W2BYTEMSK(REG_0190_MODV11_V005, priv->de_height / 2, REG_0190_MODV11_V005_REG_TEST_V_LINE_END_0190);

        W2BYTEMSK(REG_0180_MODV11_V005, 0x00, REG_0180_MODV11_V005_REG_TEST_MODE_0180);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_V_LINE_MODE_0180);
    }
    else if (pat_id == E_BOOT_TEST_PATTERN_MOD_V_HALF_INV) {
        W2BYTEMSK(REG_0198_MODV11_V005, 0X03FF, REG_0198_MODV11_V005_REG_TEST_COLOR_R_0198);
        W2BYTEMSK(REG_019C_MODV11_V005, 0X03FF, REG_019C_MODV11_V005_REG_TEST_COLOR_G_019C);
        W2BYTEMSK(REG_01A0_MODV11_V005, 0X03FF, REG_01A0_MODV11_V005_REG_TEST_COLOR_B_01A0);
        W2BYTEMSK(REG_018C_MODV11_V005, 0x0000, REG_018C_MODV11_V005_REG_TEST_V_LINE_ST_018C);
        W2BYTEMSK(REG_0190_MODV11_V005, priv->de_height / 2, REG_0190_MODV11_V005_REG_TEST_V_LINE_END_0190);

        W2BYTEMSK(REG_0180_MODV11_V005, 0x00, REG_0180_MODV11_V005_REG_TEST_MODE_0180);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_V_LINE_MODE_0180);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_V_INV_0180);
    }
    else if (pat_id == E_BOOT_TEST_PATTERN_MOD_FULL) {
        W2BYTEMSK(REG_0198_MODV11_V005, 0X03FF, REG_0198_MODV11_V005_REG_TEST_COLOR_R_0198);
        W2BYTEMSK(REG_019C_MODV11_V005, 0X03FF, REG_019C_MODV11_V005_REG_TEST_COLOR_G_019C);
        W2BYTEMSK(REG_01A0_MODV11_V005, 0X03FF, REG_01A0_MODV11_V005_REG_TEST_COLOR_B_01A0);

        W2BYTEMSK(REG_0184_MODV11_V005, 0xFFFF, REG_0184_MODV11_V005_REG_TEST_H_LINE_ST_0184);
        W2BYTEMSK(REG_0188_MODV11_V005, 0xFFFF, REG_0188_MODV11_V005_REG_TEST_H_LINE_END_0188);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_H_LINE_MODE_0180);
        mdelay(10);
        W2BYTEMSK(REG_0180_MODV11_V005, 0x01, REG_0180_MODV11_V005_REG_TEST_MODE_0180);
	} else if ((pat_id == E_BOOT_TEST_PATTERN_TOCN_GRAY) && (priv->pnl_lib_version == BOOT_PNL_VERSION0600)) {
		W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA409, REG_0F00, REG_0170_PATGEN_SCALER_BKA409_REG_H_SIZE_0170);
		W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA409, REG_0870, REG_0174_PATGEN_SCALER_BKA409_REG_V_SIZE_0174);

		W2BYTEMSK(REG_0124_PATGEN_SCALER_BKA409, REG_01FF, REG_0124_PATGEN_SCALER_BKA409_REG_DIFF_H_LSB_0124);
		W2BYTEMSK(REG_0144_PATGEN_SCALER_BKA409, REG_01FF, REG_0144_PATGEN_SCALER_BKA409_REG_DIFF_V_LSB_0144);
		W2BYTEMSK(REG_0164_PATGEN_SCALER_BKA409, REG_01FF, REG_0164_PATGEN_SCALER_BKA409_REG_COLORBAR_SPEED_0164);
		mdelay(DELAY10);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000,
			REG_0104_PATGEN_SCALER_BKA409_REG_PATGEN_ULTRALITE_MODE_0104);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000, REG_0104_PATGEN_SCALER_BKA409_REG_BYPASS_PATGEN_SCALER_0104);
	} else if ((pat_id == E_BOOT_TEST_PATTERN_TOCN_R) && (priv->pnl_lib_version == BOOT_PNL_VERSION0600)) {
		W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA409, REG_0F00, REG_0170_PATGEN_SCALER_BKA409_REG_H_SIZE_0170);
		W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA409, REG_0870, REG_0174_PATGEN_SCALER_BKA409_REG_V_SIZE_0174);

		W2BYTEMSK(REG_0124_PATGEN_SCALER_BKA409, REG_03FF, REG_0124_PATGEN_SCALER_BKA409_REG_DIFF_H_LSB_0124);
		W2BYTEMSK(REG_0144_PATGEN_SCALER_BKA409, REG_0000, REG_0144_PATGEN_SCALER_BKA409_REG_DIFF_V_LSB_0144);
		W2BYTEMSK(REG_0164_PATGEN_SCALER_BKA409, REG_0000, REG_0164_PATGEN_SCALER_BKA409_REG_COLORBAR_SPEED_0164);
		mdelay(DELAY10);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000,
			REG_0104_PATGEN_SCALER_BKA409_REG_PATGEN_ULTRALITE_MODE_0104);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000, REG_0104_PATGEN_SCALER_BKA409_REG_BYPASS_PATGEN_SCALER_0104);
	} else if ((pat_id == E_BOOT_TEST_PATTERN_TOCN_G) && (priv->pnl_lib_version == BOOT_PNL_VERSION0600)) {
		W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA409, REG_0F00, REG_0170_PATGEN_SCALER_BKA409_REG_H_SIZE_0170);
		W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA409, REG_0870, REG_0174_PATGEN_SCALER_BKA409_REG_V_SIZE_0174);

		W2BYTEMSK(REG_0124_PATGEN_SCALER_BKA409, REG_0000, REG_0124_PATGEN_SCALER_BKA409_REG_DIFF_H_LSB_0124);
		W2BYTEMSK(REG_0144_PATGEN_SCALER_BKA409, REG_03FF, REG_0144_PATGEN_SCALER_BKA409_REG_DIFF_V_LSB_0144);
		W2BYTEMSK(REG_0164_PATGEN_SCALER_BKA409, REG_0000, REG_0164_PATGEN_SCALER_BKA409_REG_COLORBAR_SPEED_0164);
		mdelay(DELAY10);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000,
			REG_0104_PATGEN_SCALER_BKA409_REG_PATGEN_ULTRALITE_MODE_0104);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000, REG_0104_PATGEN_SCALER_BKA409_REG_BYPASS_PATGEN_SCALER_0104);
	} else if ((pat_id == E_BOOT_TEST_PATTERN_TOCN_B) && (priv->pnl_lib_version == BOOT_PNL_VERSION0600)) {
		W2BYTEMSK(REG_0170_PATGEN_SCALER_BKA409, REG_0F00, REG_0170_PATGEN_SCALER_BKA409_REG_H_SIZE_0170);
		W2BYTEMSK(REG_0174_PATGEN_SCALER_BKA409, REG_0870, REG_0174_PATGEN_SCALER_BKA409_REG_V_SIZE_0174);

		W2BYTEMSK(REG_0124_PATGEN_SCALER_BKA409, REG_0000, REG_0124_PATGEN_SCALER_BKA409_REG_DIFF_H_LSB_0124);
		W2BYTEMSK(REG_0144_PATGEN_SCALER_BKA409, REG_0000, REG_0144_PATGEN_SCALER_BKA409_REG_DIFF_V_LSB_0144);
		W2BYTEMSK(REG_0164_PATGEN_SCALER_BKA409, REG_03FF, REG_0164_PATGEN_SCALER_BKA409_REG_COLORBAR_SPEED_0164);
		mdelay(DELAY10);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000,
			REG_0104_PATGEN_SCALER_BKA409_REG_PATGEN_ULTRALITE_MODE_0104);
		W2BYTEMSK(REG_0104_PATGEN_SCALER_BKA409, REG_0000, REG_0104_PATGEN_SCALER_BKA409_REG_BYPASS_PATGEN_SCALER_0104);
	}
    else {
        UBOOT_DEBUG("Invalid iniput parameters! \n");
    }
    return;
}

void mtk_testmodtgen_settings(struct udevice *dev)
{
	struct mtk_panel_priv *priv = dev_get_priv(dev);
	char *enable_env = env_get("modtgen");
	bool en = false;

	en = mst_atoi(enable_env);

	if (!priv) {
		UBOOT_DEBUG("Invalid iniput parameters!\n");
		return;
	}

	UBOOT_DEBUG("get en=%d, de_height=%d, de_width=%d\n", en, priv->de_height, priv->de_width);

	if (en) {
		W2BYTEMSK(REG_01E0_MODV11, 0x00, REG_01E0_MODV11_REG_TGEN_SET_READY);

		W2BYTEMSK(REG_01C0_MODV11, priv->typ_htt, REG_01C0_MODV11_REG_TGEN_HTT);
		W2BYTEMSK(REG_01C4_MODV11, priv->hsync_w, REG_01C4_MODV11_REG_TGEN_HSYNC_WIDTH);
		W2BYTEMSK(REG_01C8_MODV11, priv->de_hstart, REG_01C8_MODV11_REG_TGEN_HDE_ST);
		W2BYTEMSK(REG_01CC_MODV11, priv->de_width, REG_01CC_MODV11_REG_TGEN_HDE_WIDTH);
		W2BYTEMSK(REG_01D0_MODV11, priv->typ_vtt, REG_01D0_MODV11_REG_TGEN_VTT);
		if (priv->tcon_info.bUsingTCON) {
			W2BYTEMSK(REG_01D4_MODV11, priv->vsync_w - 1, REG_01D4_MODV11_REG_TGEN_VSYNC_WIDTH);
			W2BYTEMSK(REG_01D8_MODV11, priv->vsync_w, REG_01D8_MODV11_REG_TGEN_VDE_ST);
		} else {
			W2BYTEMSK(REG_01D4_MODV11, priv->vsync_w, REG_01D4_MODV11_REG_TGEN_VSYNC_WIDTH);
			W2BYTEMSK(REG_01D8_MODV11, priv->de_vstart, REG_01D8_MODV11_REG_TGEN_VDE_ST);
		}
		W2BYTEMSK(REG_01DC_MODV11, priv->de_height, REG_01DC_MODV11_REG_TGEN_VDE_WIDTH);

		W2BYTEMSK(REG_01E0_MODV11, 0x01, REG_01E0_MODV11_REG_TGEN_ENGINE);
		// [4:0] = [LR, HDE, Hsync, VDE, Vsync]
		W2BYTEMSK(REG_01E0_MODV11, 0x0F, REG_01E0_MODV11_REG_TGEN_REPLACE_SEL);
		W2BYTEMSK(REG_01E0_MODV11, 0x01, REG_01E0_MODV11_REG_TGEN_DB_EN);
		//W2BYTEMSK(REG_01E0_MODV11, 0x01, REG_01E0_MODV11_REG_TGEN_VXDE_EN);
		W2BYTEMSK(REG_01E0_MODV11, 0x01, REG_01E0_MODV11_REG_TGEN_SET_READY);
		W2BYTEMSK(REG_01E0_MODV11, 0x01, REG_01E0_MODV11_REG_TGEN_EN);
	}
}
