/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define CLKGEN_SC02 0x1408400

//Page CLKGEN_SC02
#define REG_0004_CLKGEN_SC02 (CLKGEN_SC02 + 0x004)
	#define REG_0004_CLKGEN_SC02_REG_SW_EN_XC_OD2SCTCON Fld(1,  1,  AC_MSKB0)//[1:1]
#define REG_002C_CLKGEN_SC02 (CLKGEN_SC02 + 0x02C)
	#define REG_002C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCSR Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_002C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCTCON Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0068_CLKGEN_SC02 (CLKGEN_SC02 + 0x068)
	#define REG_0068_CLKGEN_SC02_REG_SW_EN_XC_OD_META2SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0070_CLKGEN_SC02 (CLKGEN_SC02 + 0x070)
	#define REG_0070_CLKGEN_SC02_REG_SW_EN_XC_OD_OSD_META2SCTCON Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_007C_CLKGEN_SC02 (CLKGEN_SC02 + 0x07C)
	#define REG_007C_CLKGEN_SC02_REG_SW_EN_MCU_NONPM2SCSR Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_007C_CLKGEN_SC02_REG_SW_EN_MCU_NONPM2SCTCON Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_0084_CLKGEN_SC02 (CLKGEN_SC02 + 0x084)
	#define REG_0084_CLKGEN_SC02_REG_SW_EN_MCU_XC2SCSR Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0084_CLKGEN_SC02_REG_SW_EN_MCU_XC2SCTCON Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_008C_CLKGEN_SC02 (CLKGEN_SC02 + 0x08C)
	#define REG_008C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCSR_MBIST Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_008C_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCTCON_MBIST Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_009C_CLKGEN_SC02 (CLKGEN_SC02 + 0x09C)
	#define REG_009C_CLKGEN_SC02_REG_SCACE_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_009C_CLKGEN_SC02_REG_SCACE_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_009C_CLKGEN_SC02_REG_SCACE_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A0_CLKGEN_SC02 (CLKGEN_SC02 + 0x0A0)
	#define REG_00A0_CLKGEN_SC02_REG_SCMW_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A0_CLKGEN_SC02_REG_SCMW_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00A0_CLKGEN_SC02_REG_SCMW_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A4_CLKGEN_SC02 (CLKGEN_SC02 + 0x0A4)
	#define REG_00A4_CLKGEN_SC02_REG_SCTCON_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A4_CLKGEN_SC02_REG_SCTCON_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00A4_CLKGEN_SC02_REG_SCTCON_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00A8_CLKGEN_SC02 (CLKGEN_SC02 + 0x0A8)
	#define REG_00A8_CLKGEN_SC02_REG_SCSR_TEST_ENABLE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00A8_CLKGEN_SC02_REG_SCSR_TEST_DIV_SEL Fld(3, 4, AC_MSKB0)//[6:4]
	#define REG_00A8_CLKGEN_SC02_REG_SCSR_TEST_SRC_SEL Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_00AC_CLKGEN_SC02 (CLKGEN_SC02 + 0x0AC)
	#define REG_00AC_CLKGEN_SC02_REG_SCACE_ALL_SW_EN_OVERWRITE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00AC_CLKGEN_SC02_REG_SCMW_ALL_SW_EN_OVERWRITE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_00AC_CLKGEN_SC02_REG_SCTCON_ALL_SW_EN_OVERWRITE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_00AC_CLKGEN_SC02_REG_SCSR_ALL_SW_EN_OVERWRITE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00B0_CLKGEN_SC02 (CLKGEN_SC02 + 0x0B0)
	#define REG_00B0_CLKGEN_SC02_REG_SCACE_ALL_SW_EN_VALUE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00B0_CLKGEN_SC02_REG_SCMW_ALL_SW_EN_VALUE Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_00B0_CLKGEN_SC02_REG_SCTCON_ALL_SW_EN_VALUE Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_00B0_CLKGEN_SC02_REG_SCSR_ALL_SW_EN_VALUE Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_00BC_CLKGEN_SC02 (CLKGEN_SC02 + 0x0BC)
	#define REG_00BC_CLKGEN_SC02_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSR Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00BC_CLKGEN_SC02_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCTCON Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_00C4_CLKGEN_SC02 (CLKGEN_SC02 + 0x0C4)
	#define REG_00C4_CLKGEN_SC02_REG_V1_V2_O_ODCLK_FROM_MOD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00C4_CLKGEN_SC02_REG_O_ODCLK_FROM_MOD Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00CC_CLKGEN_SC02 (CLKGEN_SC02 + 0x0CC)
	#define REG_00CC_CLKGEN_SC02_REG_CKG_G_V1_ODCLK_SCTCON_TMP Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00CC_CLKGEN_SC02_REG_CKG_I_V1_ODCLK_SCTCON_TMP Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00CC_CLKGEN_SC02_REG_CKG_S_V1_ODCLK_SCTCON_TMP Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_00D8_CLKGEN_SC02 (CLKGEN_SC02 + 0x0D8)
	#define REG_00D8_CLKGEN_SC02_REG_CKG_G_O_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00D8_CLKGEN_SC02_REG_CKG_I_O_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00D8_CLKGEN_SC02_REG_CKG_S_O_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_00DC_CLKGEN_SC02 (CLKGEN_SC02 + 0x0DC)
	#define REG_00DC_CLKGEN_SC02_REG_CKG_G_V1_ODCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00DC_CLKGEN_SC02_REG_CKG_I_V1_ODCLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00DC_CLKGEN_SC02_REG_CKG_S_V1_ODCLK Fld(4, 2, AC_MSKB0)//[5:2]
#define REG_00E4_CLKGEN_SC02 (CLKGEN_SC02 + 0x0E4)
	#define REG_00E4_CLKGEN_SC02_REG_CKG_G_XTAL_24M_SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00E4_CLKGEN_SC02_REG_CKG_I_XTAL_24M_SCACE Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00EC_CLKGEN_SC02 (CLKGEN_SC02 + 0x0EC)
	#define REG_00EC_CLKGEN_SC02_REG_CKG_G_SMI_SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00EC_CLKGEN_SC02_REG_CKG_I_SMI_SCACE Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00F0_CLKGEN_SC02 (CLKGEN_SC02 + 0x0F0)
	#define REG_00F0_CLKGEN_SC02_REG_CKG_G_XC_FN_SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00F0_CLKGEN_SC02_REG_CKG_I_XC_FN_SCACE Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00F4_CLKGEN_SC02 (CLKGEN_SC02 + 0x0F4)
	#define REG_00F4_CLKGEN_SC02_REG_CKG_G_FRC_FCLK_2XPLUS_SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00F4_CLKGEN_SC02_REG_CKG_I_FRC_FCLK_2XPLUS_SCACE Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_00F8_CLKGEN_SC02 (CLKGEN_SC02 + 0x0F8)
	#define REG_00F8_CLKGEN_SC02_REG_CKG_G_XTAL_24M_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00F8_CLKGEN_SC02_REG_CKG_I_XTAL_24M_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0104_CLKGEN_SC02 (CLKGEN_SC02 + 0x104)
	#define REG_0104_CLKGEN_SC02_REG_CKG_G_SMI_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0104_CLKGEN_SC02_REG_CKG_I_SMI_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0108_CLKGEN_SC02 (CLKGEN_SC02 + 0x108)
	#define REG_0108_CLKGEN_SC02_REG_CKG_G_XC_FN_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0108_CLKGEN_SC02_REG_CKG_I_XC_FN_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_010C_CLKGEN_SC02 (CLKGEN_SC02 + 0x10C)
	#define REG_010C_CLKGEN_SC02_REG_CKG_G_FRC_FCLK_2XPLUS_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_010C_CLKGEN_SC02_REG_CKG_I_FRC_FCLK_2XPLUS_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0110_CLKGEN_SC02 (CLKGEN_SC02 + 0x110)
	#define REG_0110_CLKGEN_SC02_REG_CKG_G_B2P_ODCLK_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0110_CLKGEN_SC02_REG_CKG_I_B2P_ODCLK_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0110_CLKGEN_SC02_REG_CKG_S_B2P_ODCLK_SCMW Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0110_CLKGEN_SC02_REG_CKG_S_B2P_ODCLK_MUX_SCMW Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_0114_CLKGEN_SC02 (CLKGEN_SC02 + 0x114)
	#define REG_0114_CLKGEN_SC02_REG_CKG_G_XC_OD_B2P_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0114_CLKGEN_SC02_REG_CKG_I_XC_OD_B2P_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0118_CLKGEN_SC02 (CLKGEN_SC02 + 0x118)
	#define REG_0118_CLKGEN_SC02_REG_CKG_G_1P_ODCLK_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0118_CLKGEN_SC02_REG_CKG_I_1P_ODCLK_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0118_CLKGEN_SC02_REG_CKG_S_1P_ODCLK_SCMW Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0118_CLKGEN_SC02_REG_CKG_S_1P_ODCLK_MUX_SCMW Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_011C_CLKGEN_SC02 (CLKGEN_SC02 + 0x11C)
	#define REG_011C_CLKGEN_SC02_REG_CKG_G_XC_OD_1P_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_011C_CLKGEN_SC02_REG_CKG_I_XC_OD_1P_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0120_CLKGEN_SC02 (CLKGEN_SC02 + 0x120)
	#define REG_0120_CLKGEN_SC02_REG_CKG_G_XC_DIP0_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0120_CLKGEN_SC02_REG_CKG_I_XC_DIP0_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0120_CLKGEN_SC02_REG_CKG_S_XC_DIP0_SCMW Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0124_CLKGEN_SC02 (CLKGEN_SC02 + 0x124)
	#define REG_0124_CLKGEN_SC02_REG_CKG_G_XC_DIP1_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0124_CLKGEN_SC02_REG_CKG_I_XC_DIP1_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0124_CLKGEN_SC02_REG_CKG_S_XC_DIP1_SCMW Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0128_CLKGEN_SC02 (CLKGEN_SC02 + 0x128)
	#define REG_0128_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0128_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCACE_MBIST Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0134_CLKGEN_SC02 (CLKGEN_SC02 + 0x134)
	#define REG_0134_CLKGEN_SC02_REG_SW_EN_SMI2SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0134_CLKGEN_SC02_REG_SW_EN_SMI2SCACE_GALS Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0138_CLKGEN_SC02 (CLKGEN_SC02 + 0x138)
	#define REG_0138_CLKGEN_SC02_REG_SW_EN_SCAN_MUX_SMI2SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0138_CLKGEN_SC02_REG_SW_EN_SCAN_MUX_SMI2SCACE_GALS Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_013C_CLKGEN_SC02 (CLKGEN_SC02 + 0x13C)
	#define REG_013C_CLKGEN_SC02_REG_SW_EN_XC_FN2SCACE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0140_CLKGEN_SC02 (CLKGEN_SC02 + 0x140)
	#define REG_0140_CLKGEN_SC02_REG_SW_EN_FRC_FCLK_2XPLUS2SCACE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0148_CLKGEN_SC02 (CLKGEN_SC02 + 0x148)
	#define REG_0148_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0148_CLKGEN_SC02_REG_SW_EN_XTAL_24M2SCMW_MBIST Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0154_CLKGEN_SC02 (CLKGEN_SC02 + 0x154)
	#define REG_0154_CLKGEN_SC02_REG_SW_EN_SMI2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0154_CLKGEN_SC02_REG_SW_EN_SMI2SCMW_GALS Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0158_CLKGEN_SC02 (CLKGEN_SC02 + 0x158)
	#define REG_0158_CLKGEN_SC02_REG_SW_EN_SCAN_MUX_SMI2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0158_CLKGEN_SC02_REG_SW_EN_SCAN_MUX_SMI2SCMW_GALS Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_015C_CLKGEN_SC02 (CLKGEN_SC02 + 0x15C)
	#define REG_015C_CLKGEN_SC02_REG_SW_EN_XC_FN2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0160_CLKGEN_SC02 (CLKGEN_SC02 + 0x160)
	#define REG_0160_CLKGEN_SC02_REG_SW_EN_FRC_FCLK_2XPLUS2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0168_CLKGEN_SC02 (CLKGEN_SC02 + 0x168)
	#define REG_0168_CLKGEN_SC02_REG_SW_EN_XC_OD_B2P2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_016C_CLKGEN_SC02 (CLKGEN_SC02 + 0x16C)
	#define REG_016C_CLKGEN_SC02_REG_SW_EN_XC_OD_1P2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0170_CLKGEN_SC02 (CLKGEN_SC02 + 0x170)
	#define REG_0170_CLKGEN_SC02_REG_SW_EN_XC_DIP02SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0174_CLKGEN_SC02 (CLKGEN_SC02 + 0x174)
	#define REG_0174_CLKGEN_SC02_REG_SW_EN_XC_DIP12SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_017C_CLKGEN_SC02 (CLKGEN_SC02 + 0x17C)
	#define REG_017C_CLKGEN_SC02_REG_CKG_G_XTAL_12M_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_017C_CLKGEN_SC02_REG_CKG_I_XTAL_12M_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0184_CLKGEN_SC02 (CLKGEN_SC02 + 0x184)
	#define REG_0184_CLKGEN_SC02_REG_SW_EN_XTAL_12M2SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_018C_CLKGEN_SC02 (CLKGEN_SC02 + 0x18C)
	#define REG_018C_CLKGEN_SC02_REG_CKG_G_XC_DIP2_SCMW Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_018C_CLKGEN_SC02_REG_CKG_I_XC_DIP2_SCMW Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_018C_CLKGEN_SC02_REG_CKG_S_XC_DIP2_SCMW Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0190_CLKGEN_SC02 (CLKGEN_SC02 + 0x190)
	#define REG_0190_CLKGEN_SC02_REG_SW_EN_XC_DIP22SCMW Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0194_CLKGEN_SC02 (CLKGEN_SC02 + 0x194)
	#define REG_0194_CLKGEN_SC02_REG_CKG_G_B2P_ODCLK_SCACE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0194_CLKGEN_SC02_REG_CKG_I_B2P_ODCLK_SCACE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0194_CLKGEN_SC02_REG_CKG_S_B2P_ODCLK_SCACE Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0194_CLKGEN_SC02_REG_CKG_S_B2P_ODCLK_MUX_SCACE Fld(3, 3, AC_MSKB0)//[5:3]
#define REG_0198_CLKGEN_SC02 (CLKGEN_SC02 + 0x198)
	#define REG_0198_CLKGEN_SC02_REG_CKG_G_XC_IP_AUL_CLK_MERGE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0198_CLKGEN_SC02_REG_CKG_I_XC_IP_AUL_CLK_MERGE Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0198_CLKGEN_SC02_REG_CKG_S_XC_IP_AUL_CLK_MERGE_TMP Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_019C_CLKGEN_SC02 (CLKGEN_SC02 + 0x19C)
	#define REG_019C_CLKGEN_SC02_REG_SW_EN_XC_IP_AUL_CLK_MERGE2SCACE_TMP Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_01F8_CLKGEN_SC02 (CLKGEN_SC02 + 0x1F8)
	#define REG_01F8_CLKGEN_SC02_REG_GATE_INV_WLOCK_PASSWD Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01FC_CLKGEN_SC02 (CLKGEN_SC02 + 0x1FC)
	#define REG_01FC_CLKGEN_SC02_REG_ALL_SW_EN_PASSWD Fld(16, 0, AC_FULLW10)//[15:0]
