/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define LPLLA 0x484000

//Page LPLLA
#define REG_0000_LPLLA (LPLLA + 0x000)
	#define REG_0000_LPLLA_REG_LPLL_MASTER_BC Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_BIAS_SEL Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_BP Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_CLKIN_SEL Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_CLKREF_FROM_OTHER_CHIP Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_CTRL_PAD Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_CTRL_REF Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0000_LPLLA_REG_LPLL_MASTER_EN_2CHIP_INTLOOP Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0004_LPLLA (LPLLA + 0x004)
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_BIT_CLKOUT Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_FIFO Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_MINI Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_REG Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_SCALAR Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_SYNTH_RESYNC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_EN_VBY1_HS Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0004_LPLLA_REG_LPLL_MASTER_LVROD_EN Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0008_LPLLA (LPLLA + 0x008)
	#define REG_0008_LPLLA_REG_LPLL_MASTER_EN_SKEWA_CLK Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0008_LPLLA_REG_LPLL_MASTER_EN_SKEWB_CLK Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0008_LPLLA_REG_LPLL_MASTER_EN_SKEWC_CLK Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0008_LPLLA_REG_LPLL_MASTER_EN_SKEWD_CLK Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_000C_LPLLA (LPLLA + 0x00C)
	#define REG_000C_LPLLA_REG_LPLL_MASTER_FIFO_DIV Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_000C_LPLLA_REG_LPLL_MASTER_FIFO_DIV5_EN Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_0010_LPLLA (LPLLA + 0x010)
	#define REG_0010_LPLLA_REG_LPLL_MASTER_IBAND Fld(10, 0, AC_MSKW10)//[9:0]
#define REG_0014_LPLLA (LPLLA + 0x014)
	#define REG_0014_LPLLA_REG_LPLL_MASTER_IC Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0014_LPLLA_REG_LPLL_MASTER_ICTRL_EXTRAZZ Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0014_LPLLA_REG_LPLL_MASTER_ICTRL Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_0018_LPLLA (LPLLA + 0x018)
	#define REG_0018_LPLLA_REG_LPLL_MASTER_INPUT_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0018_LPLLA_REG_LPLL_MASTER_IR Fld(5, 8, AC_MSKB1)//[12:8]
	#define REG_0018_LPLLA_REG_LPLL_MASTER_LDO_REF Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_001C_LPLLA (LPLLA + 0x01C)
	#define REG_001C_LPLLA_REG_LPLL_MASTER_LOOP_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0020_LPLLA (LPLLA + 0x020)
	#define REG_0020_LPLLA_REG_LPLL_MASTER_M2S_PREDIV Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0020_LPLLA_REG_LPLL_MASTER_MODE_SEL Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0020_LPLLA_REG_LPLL_MASTER_MONCK_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0020_LPLLA_REG_LPLL_MASTER_PD_FIFO Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0020_LPLLA_REG_LPLL_MASTER_REG_LEVEL Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0024_LPLLA (LPLLA + 0x024)
	#define REG_0024_LPLLA_REG_LPLL_MASTER_SCALAR_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0024_LPLLA_REG_LPLL_MASTER_SCALAR_DIV_SECOND Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_0028_LPLLA (LPLLA + 0x028)
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SCALAR2FIFO_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SDIV2P5_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SDIV3P5_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SEL_SCALAR Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SEL_SKEW1_DELAY1T Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SEL_SKEW2_DELAY1T Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SKEW_DIV Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_0028_LPLLA_REG_LPLL_MASTER_SKEW_EN_FIXCLK Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_002C_LPLLA (LPLLA + 0x02C)
	#define REG_002C_LPLLA_REG_LPLL_MASTER_SKEW1_COARSE Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_002C_LPLLA_REG_LPLL_MASTER_SKEW1_FINE Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_002C_LPLLA_REG_LPLL_MASTER_SKEW2_COARSE Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_002C_LPLLA_REG_LPLL_MASTER_SKEW2_FINE Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0030_LPLLA (LPLLA + 0x030)
	#define REG_0030_LPLLA_REG_LPLL_MASTER_SSC_DIR_DLY Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_SYN_SEL Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_SSC_MODE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_TEST_EN_SDIV Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_TEST_FIFO_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_TOSLAVE_DIV_FIRST Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_TOSLAVE_DIV5_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_VBY1_DIFF_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_VFB_SEL Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0030_LPLLA_REG_LPLL_MASTER_VREF_SEL Fld(2, 12, AC_MSKB1)//[13:12]
#define REG_0034_LPLLA (LPLLA + 0x034)
	#define REG_0034_LPLLA_REG_LPLL_MASTER_SPAN Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0038_LPLLA (LPLLA + 0x038)
	#define REG_0038_LPLLA_REG_LPLL_MASTER_TEST_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_003C_LPLLA (LPLLA + 0x03C)
	#define REG_003C_LPLLA_REG_LPLL_MASTER_TEST_1 Fld(15, 0, AC_MSKW10)//[14:0]
#define REG_0040_LPLLA (LPLLA + 0x040)
	#define REG_0040_LPLLA_REG_LPLL_MASTER_SDM_PCW_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0044_LPLLA (LPLLA + 0x044)
	#define REG_0044_LPLLA_REG_LPLL_MASTER_SDM_PCW_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0048_LPLLA (LPLLA + 0x048)
	#define REG_0048_LPLLA_REG_LPLL_MASTER_SDM_PCW_2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_004C_LPLLA (LPLLA + 0x04C)
	#define REG_004C_LPLLA_REG_LPLL_MASTER_SDM_SSC_DELTA Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_LPLLA (LPLLA + 0x050)
	#define REG_0050_LPLLA_REG_LPLL_MASTER_SDM_SSC_DELTA1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0054_LPLLA (LPLLA + 0x054)
	#define REG_0054_LPLLA_REG_LPLL_MASTER_SDM_HR_EN Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0054_LPLLA_REG_LPLL_MASTER_SDM_ORD Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0054_LPLLA_REG_LPLL_MASTER_SDM_FRA_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0054_LPLLA_REG_LPLL_MASTER_SDM_PCW_CHG_SW Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0054_LPLLA_REG_LPLL_MASTER_SDM_PCW_CHG_SW_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0054_LPLLA_REG_LPLL_MASTER_SDM_FPLL_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0058_LPLLA (LPLLA + 0x058)
	#define REG_0058_LPLLA_REG_LPLL_MASTER_VCOCAL_STATE Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0058_LPLLA_REG_LPLL_MASTER_VCOCAL_CPLT Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0058_LPLLA_REG_LPLL_MASTER_LOCK Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_005C_LPLLA (LPLLA + 0x05C)
	#define REG_005C_LPLLA_REG_LPLL_MASTER_PD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_005C_LPLLA_REG_LPLL_MASTER_ISO_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_005C_LPLLA_REG_LPLL_MASTER_PWR_ON Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0060_LPLLA (LPLLA + 0x060)
	#define REG_0060_LPLLA_REG_LPLL_SLAVE_CLKI_SYNTH_RESYNC_SEL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0060_LPLLA_REG_LPLL_SLAVE_DIV14_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0060_LPLLA_REG_LPLL_SLAVE_FROM_MASTER_EN Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0064_LPLLA (LPLLA + 0x064)
	#define REG_0064_LPLLA_REG_LPLL_SLAVE_INPUT_DIV Fld(5, 0, AC_MSKB0)//[4:0]
#define REG_0068_LPLLA (LPLLA + 0x068)
	#define REG_0068_LPLLA_REG_LPLL_SLAVE_PD_TEST_CLK Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0068_LPLLA_REG_LPLL_SLAVE_POST_DIV Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_006C_LPLLA (LPLLA + 0x06C)
	#define REG_006C_LPLLA_REG_LPLL_SLAVE_SPAN Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0070_LPLLA (LPLLA + 0x070)
	#define REG_0070_LPLLA_REG_LPLL_SLAVE_SSC_MODE Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0070_LPLLA_REG_LPLL_SLAVE_SYN_CLK_SEL Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0070_LPLLA_REG_LPLL_SLAVE_SYN_SEL Fld(2, 2, AC_MSKB0)//[3:2]
#define REG_0074_LPLLA (LPLLA + 0x074)
	#define REG_0074_LPLLA_REG_LPLL_SLAVE_TEST Fld(13, 0, AC_MSKW10)//[12:0]
#define REG_0080_LPLLA (LPLLA + 0x080)
	#define REG_0080_LPLLA_REG_LPLL_SLAVE_SDM_PCW_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0084_LPLLA (LPLLA + 0x084)
	#define REG_0084_LPLLA_REG_LPLL_SLAVE_SDM_PCW_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_008C_LPLLA (LPLLA + 0x08C)
	#define REG_008C_LPLLA_REG_LPLL_SLAVE_SDM_SSC_DELTA Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0090_LPLLA (LPLLA + 0x090)
	#define REG_0090_LPLLA_REG_LPLL_SLAVE_SDM_SSC_DELTA1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0094_LPLLA (LPLLA + 0x094)
	#define REG_0094_LPLLA_REG_LPLL_SLAVE_SDM_PCW_CHG_SW Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0094_LPLLA_REG_LPLL_SLAVE_SDM_PCW_CHG_SW_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0094_LPLLA_REG_LPLL_SLAVE_SDM_FPLL_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0098_LPLLA (LPLLA + 0x098)
	#define REG_0098_LPLLA_REG_LPLL_SLAVE_PD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0098_LPLLA_REG_LPLL_SLAVE_ISO_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0098_LPLLA_REG_LPLL_SLAVE_PWR_ON Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_00C0_LPLLA (LPLLA + 0x0C0)
	#define REG_00C0_LPLLA_REG_LPLL_OSD_BIAS_SEL Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00C0_LPLLA_REG_LPLL_OSD_BP Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_00C0_LPLLA_REG_LPLL_OSD_BP2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00C0_LPLLA_REG_LPLL_OSD_CTRL_PAD Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_00C0_LPLLA_REG_LPLL_OSD_CTRL_REF Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_00C0_LPLLA_REG_LPLL_OSD_EN_2CHIP_INTLOOP Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_00C4_LPLLA (LPLLA + 0x0C4)
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_BIT_CLKOUT Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_FIFO Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_MINI Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_REG Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_SCALAR Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_SYNTH_RESYNC Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00C4_LPLLA_REG_LPLL_OSD_EN_VBY1_HS Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_00C8_LPLLA (LPLLA + 0x0C8)
	#define REG_00C8_LPLLA_REG_LPLL_OSD_EN_SKEWA_CLK Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_00C8_LPLLA_REG_LPLL_OSD_EN_SKEWB_CLK Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_00C8_LPLLA_REG_LPLL_OSD_EN_SKEWC_CLK Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_00C8_LPLLA_REG_LPLL_OSD_EN_SKEWD_CLK Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00CC_LPLLA (LPLLA + 0x0CC)
	#define REG_00CC_LPLLA_REG_LPLL_OSD_FIFO_DIV Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_00CC_LPLLA_REG_LPLL_OSD_FIFO_DIV5_EN Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_00D0_LPLLA (LPLLA + 0x0D0)
	#define REG_00D0_LPLLA_REG_LPLL_OSD_IBAND Fld(10, 0, AC_MSKW10)//[9:0]
	#define REG_00D0_LPLLA_REG_LPLL_OSD_IBANDLDO_VOD_SEL12 Fld(2, 12, AC_MSKB1)//[13:12]
#define REG_00D4_LPLLA (LPLLA + 0x0D4)
	#define REG_00D4_LPLLA_REG_LPLL_OSD_IC Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_00D4_LPLLA_REG_LPLL_OSD_ICTRL_EXTRAZZ Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00D4_LPLLA_REG_LPLL_OSD_ICTRL Fld(3, 12, AC_MSKB1)//[14:12]
#define REG_00D8_LPLLA (LPLLA + 0x0D8)
	#define REG_00D8_LPLLA_REG_LPLL_OSD_INPUT_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00D8_LPLLA_REG_LPLL_OSD_IR Fld(5, 8, AC_MSKB1)//[12:8]
	#define REG_00D8_LPLLA_REG_LPLL_OSD_LDO_REF Fld(2, 14, AC_MSKB1)//[15:14]
#define REG_00DC_LPLLA (LPLLA + 0x0DC)
	#define REG_00DC_LPLLA_REG_LPLL_OSD_LOOP_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_00E0_LPLLA (LPLLA + 0x0E0)
	#define REG_00E0_LPLLA_REG_LPLL_OSD_LPLL_M2S_PREDIV Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00E0_LPLLA_REG_LPLL_OSD_MODE_SEL Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_00E0_LPLLA_REG_LPLL_OSD_MONCK_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00E0_LPLLA_REG_LPLL_OSD_PD_FIFO Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_00E0_LPLLA_REG_LPLL_OSD_REG_LEVEL Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00E4_LPLLA (LPLLA + 0x0E4)
	#define REG_00E4_LPLLA_REG_LPLL_OSD_SCALAR_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00E4_LPLLA_REG_LPLL_OSD_SCALAR_DIV_SECOND Fld(4, 8, AC_MSKB1)//[11:8]
#define REG_00E8_LPLLA (LPLLA + 0x0E8)
	#define REG_00E8_LPLLA_REG_LPLL_OSD_SCALAR2FIFO_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00E8_LPLLA_REG_LPLL_OSD_SEL_SCALAR Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00E8_LPLLA_REG_LPLL_OSD_SEL_SKEW1_DELAY1T Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_00E8_LPLLA_REG_LPLL_OSD_SEL_SKEW2_DELAY1T Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_00E8_LPLLA_REG_LPLL_OSD_SKEW_DIV Fld(3, 8, AC_MSKB1)//[10:8]
	#define REG_00E8_LPLLA_REG_LPLL_OSD_SKEW_EN_FIXCLK Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_00EC_LPLLA (LPLLA + 0x0EC)
	#define REG_00EC_LPLLA_REG_LPLL_OSD_SKEW1_COARSE Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_00EC_LPLLA_REG_LPLL_OSD_SKEW1_FINE Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_00EC_LPLLA_REG_LPLL_OSD_SKEW2_COARSE Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_00EC_LPLLA_REG_LPLL_OSD_SKEW2_FINE Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_00F0_LPLLA (LPLLA + 0x0F0)
	#define REG_00F0_LPLLA_REG_LPLL_OSD_SYN_SEL Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_SSC_MODE Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_TEST_EN_SDIV Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_TEST_FIFO_EN Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_TOSLAVE_DIV_FIRST Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_TOSLAVE_DIV5_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_VBY1_DIFF_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_VFB_SEL Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_00F0_LPLLA_REG_LPLL_OSD_VREF_SEL Fld(2, 12, AC_MSKB1)//[13:12]
#define REG_00F4_LPLLA (LPLLA + 0x0F4)
	#define REG_00F4_LPLLA_REG_LPLL_OSD_SPAN Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00F8_LPLLA (LPLLA + 0x0F8)
	#define REG_00F8_LPLLA_REG_LPLL_OSD_TEST_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00FC_LPLLA (LPLLA + 0x0FC)
	#define REG_00FC_LPLLA_REG_LPLL_OSD_TEST_1 Fld(15, 0, AC_MSKW10)//[14:0]
#define REG_0100_LPLLA (LPLLA + 0x100)
	#define REG_0100_LPLLA_REG_LPLL_OSD_SDM_PCW_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0104_LPLLA (LPLLA + 0x104)
	#define REG_0104_LPLLA_REG_LPLL_OSD_SDM_PCW_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0108_LPLLA (LPLLA + 0x108)
	#define REG_0108_LPLLA_REG_LPLL_OSD_SDM_PCW_2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_010C_LPLLA (LPLLA + 0x10C)
	#define REG_010C_LPLLA_REG_LPLL_OSD_SDM_SSC_DELTA Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0110_LPLLA (LPLLA + 0x110)
	#define REG_0110_LPLLA_REG_LPLL_OSD_SDM_SSC_DELTA1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0114_LPLLA (LPLLA + 0x114)
	#define REG_0114_LPLLA_REG_LPLL_OSD_SDM_HR_EN Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0114_LPLLA_REG_LPLL_OSD_SDM_ORD Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0114_LPLLA_REG_LPLL_OSD_SDM_FRA_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0114_LPLLA_REG_LPLL_OSD_SDM_PCW_CHG_SW Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0114_LPLLA_REG_LPLL_OSD_SDM_PCW_CHG_SW_EN Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0114_LPLLA_REG_LPLL_OSD_SDM_FPLL_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0118_LPLLA (LPLLA + 0x118)
	#define REG_0118_LPLLA_REG_LPLL_OSD_VCOCAL_STATE Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0118_LPLLA_REG_LPLL_OSD_VCOCAL_CPLT Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0118_LPLLA_REG_LPLL_OSD_LOCK Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_011C_LPLLA (LPLLA + 0x11C)
	#define REG_011C_LPLLA_REG_LPLL_OSD_PD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_011C_LPLLA_REG_LPLL_OSD_ISO_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_011C_LPLLA_REG_LPLL_OSD_PWR_ON Fld(1, 2, AC_MSKB0)//[2:2]
#define REG_0120_LPLLA (LPLLA + 0x120)
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_BR Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_BP Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_CKFIFO_DIV5_EN Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_CKFIFO_EN Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_DIV3P5_EN Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_EN_AMUX Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_EN_OCC Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_EN_PRDT Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0120_LPLLA_REG_LPLL_REFPLL_EN_SCALAR Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0124_LPLLA (LPLLA + 0x124)
	#define REG_0124_LPLLA_REG_LPLL_REFPLL_EN_TEST Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0124_LPLLA_REG_LPLL_REFPLL_FBKSEL Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0124_LPLLA_REG_LPLL_REFPLL_FIFO_DIV Fld(2, 6, AC_MSKB0)//[7:6]
	#define REG_0124_LPLLA_REG_LPLL_REFPLL_GCR_AMUX_SEL Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_0124_LPLLA_REG_LPLL_REFPLL_GCR_CP_HBW Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0128_LPLLA (LPLLA + 0x128)
	#define REG_0128_LPLLA_REG_LPLL_REFPLL_GCR_INPUT_DIV Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0128_LPLLA_REG_LPLL_REFPLL_GCR_OUTPUT_DIV_FIRST Fld(2, 8, AC_MSKB1)//[9:8]
#define REG_012C_LPLLA (LPLLA + 0x12C)
	#define REG_012C_LPLLA_REG_LPLL_REFPLL_GCR_OUTPUT_DIV Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0130_LPLLA (LPLLA + 0x130)
	#define REG_0130_LPLLA_REG_LPLL_REFPLL_IBAND Fld(10, 0, AC_MSKW10)//[9:0]
#define REG_0134_LPLLA (LPLLA + 0x134)
	#define REG_0134_LPLLA_REG_LPLL_REFPLL_IC Fld(5, 0, AC_MSKB0)//[4:0]
	#define REG_0134_LPLLA_REG_LPLL_REFPLL_IR Fld(5, 8, AC_MSKB1)//[12:8]
#define REG_0138_LPLLA (LPLLA + 0x138)
	#define REG_0138_LPLLA_REG_LPLL_REFPLL_KBAND_KFC Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0138_LPLLA_REG_LPLL_REFPLL_KBAND_PREDIV Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0138_LPLLA_REG_LPLL_REFPLL_LOAD_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0138_LPLLA_REG_LPLL_REFPLL_LVR_REFSEL Fld(2, 6, AC_MSKB0)//[7:6]
#define REG_013C_LPLLA (LPLLA + 0x13C)
	#define REG_013C_LPLLA_REG_LPLL_REFPLL_PD_CLK_ADC_VCO_DIV2_3 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_013C_LPLLA_REG_LPLL_REFPLL_PD_DIGCLK Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_013C_LPLLA_REG_LPLL_REFPLL_PD_TEST_CLKD Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_013C_LPLLA_REG_LPLL_REFPLL_SCALAR_DIV Fld(2, 8, AC_MSKB1)//[9:8]
	#define REG_013C_LPLLA_REG_LPLL_REFPLL_SSC_DIR_DLY Fld(2, 10, AC_MSKB1)//[11:10]
#define REG_0140_LPLLA (LPLLA + 0x140)
	#define REG_0140_LPLLA_REG_LPLL_REFPLL_TEST Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0144_LPLLA (LPLLA + 0x144)
	#define REG_0144_LPLLA_REG_LPLL_REFPLL_TEST19 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0160_LPLLA (LPLLA + 0x160)
	#define REG_0160_LPLLA_REG_LPLL_REFPLL_SDM_PCW_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0164_LPLLA (LPLLA + 0x164)
	#define REG_0164_LPLLA_REG_LPLL_REFPLL_SDM_PCW_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0168_LPLLA (LPLLA + 0x168)
	#define REG_0168_LPLLA_REG_LPLL_REFPLL_SDM_PCW_2 Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_016C_LPLLA (LPLLA + 0x16C)
	#define REG_016C_LPLLA_REG_LPLL_REFPLL_SDM_SSC_DELTA Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0170_LPLLA (LPLLA + 0x170)
	#define REG_0170_LPLLA_REG_LPLL_REFPLL_SDM_SSC_DELTA1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0174_LPLLA (LPLLA + 0x174)
	#define REG_0174_LPLLA_REG_LPLL_REFPLL_SDM_HR_EN Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0174_LPLLA_REG_LPLL_REFPLL_SDM_ORDER Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0174_LPLLA_REG_LPLL_REFPLL_SDM_FRA_EN Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0174_LPLLA_REG_LPLL_REFPLL_SDM_SSC_EN Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_0178_LPLLA (LPLLA + 0x178)
	#define REG_0178_LPLLA_REG_LPLL_REFPLL_SDM_SSC_PRD Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_017C_LPLLA (LPLLA + 0x17C)
	#define REG_017C_LPLLA_REG_LPLL_REFPLL_VCOCAL_STATE Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_017C_LPLLA_REG_LPLL_REFPLL_VCOCAL_CPLT Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_017C_LPLLA_REG_LPLL_REFPLL_RO_LOCK Fld(1, 9, AC_MSKB1)//[9:9]
#define REG_0180_LPLLA (LPLLA + 0x180)
	#define REG_0180_LPLLA_REG_LPLL_REFPLL_PD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0180_LPLLA_REG_LPLL_REFPLL_ISO_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0180_LPLLA_REG_LPLL_REFPLL_PWR_ON Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0180_LPLLA_REG_LPLL_REFPLL_SDM_PCW_CHG_SW Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0180_LPLLA_REG_LPLL_REFPLL_SDM_PCW_CHG_SW_EN Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0184_LPLLA (LPLLA + 0x184)
	#define REG_0184_LPLLA_REG_LPLL_2NDPLL_CLK_SEL Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0184_LPLLA_REG_LPLL_CKEN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0184_LPLLA_REG_LPLL_CKEN_PATH2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0184_LPLLA_REG_LPLL_CKGEN_EN_D Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_0184_LPLLA_REG_LPLL_CKGEN_EN_MINI_SKEW Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0184_LPLLA_REG_LPLL_CKGEN_EN_U Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0184_LPLLA_REG_LPLL_CKGEN_SEL_LP_D Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0184_LPLLA_REG_LPLL_CKGEN_SEL_LP_U Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0184_LPLLA_REG_LPLL_EN_SKEWCLK_PA Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0184_LPLLA_REG_LPLL_EN_SKEWCLK_PB Fld(1, 9, AC_MSKB1)//[9:9]
	#define REG_0184_LPLLA_REG_LPLL_FB_CLKIN_SYNCN_SEL Fld(1, 10, AC_MSKB1)//[10:10]
	#define REG_0184_LPLLA_REG_LPLL_RESET_IN Fld(1, 11, AC_MSKB1)//[11:11]
	#define REG_0184_LPLLA_REG_LPLL_PD_SCALAR Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0188_LPLLA (LPLLA + 0x188)
	#define REG_0188_LPLLA_REG_LPLL_CK1X_4DIG_PHSEL Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0188_LPLLA_REG_LPLL_CK1X_ANA_PHSEL_PATH2 Fld(2, 2, AC_MSKB0)//[3:2]
	#define REG_0188_LPLLA_REG_LPLL_CK1X_ANA_PHSEL Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_0188_LPLLA_REG_LPLL_CK1X_DIG_PHSEL_PATH2 Fld(2, 6, AC_MSKB0)//[7:6]
#define REG_018C_LPLLA (LPLLA + 0x18C)
	#define REG_018C_LPLLA_REG_LPLL_XTALRX_PD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_018C_LPLLA_REG_LPLL_XTALRX_TEST_REG Fld(2, 1, AC_MSKB0)//[2:1]
	#define REG_018C_LPLLA_REG_LPLL_XTALRX_TST_CLK Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_018C_LPLLA_REG_LPLL_XTALRX_TST_RSW Fld(2, 4, AC_MSKB0)//[5:4]
	#define REG_018C_LPLLA_REG_LPLL_XTALRX_CTRL_REF_HV_BAR Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_018C_LPLLA_REG_LPLL_XTALRX_CTRL_REF_PAD_BAR Fld(1, 7, AC_MSKB0)//[7:7]
#define REG_01F8_LPLLA (LPLLA + 0x1F8)
	#define REG_01F8_LPLLA_REG_LPLL2_DUMMY0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_01FC_LPLLA (LPLLA + 0x1FC)
	#define REG_01FC_LPLLA_REG_LPLL2_DUMMY1 Fld(16, 0, AC_FULLW10)//[15:0]
