/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */
#define EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 0x6F6200

//Page EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0
#define REG_0000_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x000)
	#define REG_0000_EDP_TX_PHY_P0_REG_VSEL_LDO Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0000_EDP_TX_PHY_P0_REG_GC_TXPLL_MODE_OV Fld(1, 14, AC_MSKB1)//[14:14]
#define REG_0004_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x004)
	#define REG_0004_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_MAIN_L0 Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0004_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_MAIN_L1 Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0008_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x008)
	#define REG_0008_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_MAIN_L2 Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0008_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_MAIN_L3 Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_000C_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x00C)
	#define REG_000C_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_PRE_L0 Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_000C_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_PRE_L1 Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0010_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x010)
	#define REG_0010_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_PRE_L2 Fld(6, 0, AC_MSKB0)//[5:0]
	#define REG_0010_EDP_TX_PHY_P0_REG_GC_ICTRL_DRV_PRE_L3 Fld(6, 8, AC_MSKB1)//[13:8]
#define REG_0014_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x014)
	#define REG_0014_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_MAIN_L0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0014_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_MAIN_L1 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0014_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_MAIN_L2 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0014_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_MAIN_L3 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_0018_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x018)
	#define REG_0018_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_PRE_L0 Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0018_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_PRE_L1 Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0018_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_PRE_L2 Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0018_EDP_TX_PHY_P0_REG_GC_ICTRL_PREDRV_PRE_L3 Fld(4, 12, AC_MSKB1)//[15:12]
#define REG_001C_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x01C)
	#define REG_001C_EDP_TX_PHY_P0_REG_GC_TXPLL_MODE Fld(2, 13, AC_MSKB1)//[14:13]
#define REG_002C_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x02C)
	#define REG_002C_EDP_TX_PHY_P0_REG_PD_BG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_002C_EDP_TX_PHY_P0_REG_PD_LDO Fld(1, 1, AC_MSKB0)//[1:1]
#define REG_0030_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x030)
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_DRV_L0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_DRV_L1 Fld(1, 5, AC_MSKB0)//[5:5]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_DRV_L2 Fld(1, 6, AC_MSKB0)//[6:6]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_DRV_L3 Fld(1, 7, AC_MSKB0)//[7:7]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_PREDRV_L0 Fld(1, 12, AC_MSKB1)//[12:12]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_PREDRV_L1 Fld(1, 13, AC_MSKB1)//[13:13]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_PREDRV_L2 Fld(1, 14, AC_MSKB1)//[14:14]
	#define REG_0030_EDP_TX_PHY_P0_REG_PD_PREDRV_L3 Fld(1, 15, AC_MSKB1)//[15:15]
#define REG_0034_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x034)
	#define REG_0034_EDP_TX_PHY_P0_REG_PD_PREEM_L0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0034_EDP_TX_PHY_P0_REG_PD_PREEM_L1 Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_0034_EDP_TX_PHY_P0_REG_PD_PREEM_L2 Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_0034_EDP_TX_PHY_P0_REG_PD_PREEM_L3 Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_003C_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x03C)
	#define REG_003C_EDP_TX_PHY_P0_REG_SEL_IB Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_003C_EDP_TX_PHY_P0_REG_DP1P3_EN Fld(1, 10, AC_MSKB1)//[10:10]
#define REG_0068_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x068)
	#define REG_0068_EDP_TX_PHY_P0_REG_DP_TX_PHY_DUMMY0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_006C_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x06C)
	#define REG_006C_EDP_TX_PHY_P0_REG_DP_TX_PHY_DUMMY1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0070_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x070)
	#define REG_0070_EDP_TX_PHY_P0_REG_DP_TX_PHY_DUMMY2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0080_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x080)
	#define REG_0080_EDP_TX_PHY_P0_REG_PHY_LANE_CLKGEN_EN Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0080_EDP_TX_PHY_P0_REG_PHY_LANE_2X_CLKGEN_EN Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0080_EDP_TX_PHY_P0_REG_PHY_XTAL_LANE_CLKGEN_EN Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0080_EDP_TX_PHY_P0_REG_PHY_XTAL_CLKGEN_EN Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_0084_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x084)
	#define REG_0084_EDP_TX_PHY_P0_REG_PHY_LANE_CLKGEN_INV Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_0084_EDP_TX_PHY_P0_REG_PHY_LANE_2X_CLKGEN_INV Fld(4, 4, AC_MSKB0)//[7:4]
	#define REG_0084_EDP_TX_PHY_P0_REG_PHY_XTAL_LANE_CLKGEN_INV Fld(4, 8, AC_MSKB1)//[11:8]
	#define REG_0084_EDP_TX_PHY_P0_REG_PHY_XTAL_CLKGEN_INV Fld(1, 13, AC_MSKB1)//[13:13]
#define REG_00AC_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0AC)
	#define REG_00AC_EDP_TX_PHY_P0_REG_SYNC_REPETITION_CTRL Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_00B4_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0B4)
	#define REG_00B4_EDP_TX_PHY_P0_REG_HBR2_ANA_EN Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00B4_EDP_TX_PHY_P0_REG_HBR_ANA_EN Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00B4_EDP_TX_PHY_P0_REG_RBR_ANA_EN Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00B4_EDP_TX_PHY_P0_REG_HBR2P5_ANA_EN Fld(1, 3, AC_MSKB0)//[3:3]
	#define REG_00B4_EDP_TX_PHY_P0_REG_HBR3_ANA_EN Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_00B8_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0B8)
	#define REG_00B8_EDP_TX_PHY_P0_REG_TESTBUS_DP_TX_PHY_40TO32_AFIFO_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00BC_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0BC)
	#define REG_00BC_EDP_TX_PHY_P0_REG_TESTBUS_DP_TX_PHY_40TO32_AFIFO_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00C0_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0C0)
	#define REG_00C0_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_GENSHOT_VALUE Fld(7, 0, AC_MSKB0)//[6:0]
#define REG_00C4_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0C4)
	#define REG_00C4_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_UP_BOUND_L0 Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_00C4_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_LOW_BOUND_L0 Fld(7, 8, AC_MSKB1)//[14:8]
#define REG_00C8_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0C8)
	#define REG_00C8_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_UP_BOUND_L1 Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_00C8_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_LOW_BOUND_L1 Fld(7, 8, AC_MSKB1)//[14:8]
#define REG_00CC_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0CC)
	#define REG_00CC_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_UP_BOUND_L2 Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_00CC_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_LOW_BOUND_L2 Fld(7, 8, AC_MSKB1)//[14:8]
#define REG_00D0_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0D0)
	#define REG_00D0_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_UP_BOUND_L3 Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_00D0_EDP_TX_PHY_P0_REG_OPENSHORT_DETECT_LOW_BOUND_L3 Fld(7, 8, AC_MSKB1)//[14:8]
#define REG_00D4_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0D4)
	#define REG_00D4_EDP_TX_PHY_P0_REG_OPENSHORT_OK_L0P Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_00D4_EDP_TX_PHY_P0_REG_OPENSHORT_OK_L1P Fld(1, 1, AC_MSKB0)//[1:1]
	#define REG_00D4_EDP_TX_PHY_P0_REG_OPENSHORT_OK_L2P Fld(1, 2, AC_MSKB0)//[2:2]
	#define REG_00D4_EDP_TX_PHY_P0_REG_OPENSHORT_OK_L3P Fld(1, 3, AC_MSKB0)//[3:3]
#define REG_00D8_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0D8)
	#define REG_00D8_EDP_TX_PHY_P0_REG_OPENSHORT_CNT_L0 Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_00D8_EDP_TX_PHY_P0_REG_OPENSHORT_CNT_L1 Fld(7, 8, AC_MSKB1)//[14:8]
#define REG_00DC_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0DC)
	#define REG_00DC_EDP_TX_PHY_P0_REG_OPENSHORT_CNT_L2 Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_00DC_EDP_TX_PHY_P0_REG_OPENSHORT_CNT_L3 Fld(7, 8, AC_MSKB1)//[14:8]
#define REG_00E0_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0E0)
	#define REG_00E0_EDP_TX_PHY_P0_REG_DP_TX_PHY_RESET_SW Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00E4_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x0E4)
	#define REG_00E4_EDP_TX_PHY_P0_REG_DATA_DEPACK_LANE_EN Fld(4, 0, AC_MSKB0)//[3:0]
	#define REG_00E4_EDP_TX_PHY_P0_REG_DATA_DEPACK_PACK_ORDER Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00E4_EDP_TX_PHY_P0_REG_DATA_DEPACK_EN_DEPACK Fld(1, 5, AC_MSKB0)//[5:5]
#define REG_0140_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x140)
	#define REG_0140_EDP_TX_PHY_P0_REG_PATTERN_GEN_DATA0_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0144_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x144)
	#define REG_0144_EDP_TX_PHY_P0_REG_PATTERN_GEN_DATA0_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0148_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x148)
	#define REG_0148_EDP_TX_PHY_P0_REG_PATTERN_GEN_DATA0_2 Fld(8, 0, AC_FULLB0)//[7:0]
	#define REG_0148_EDP_TX_PHY_P0_REG_PATTERN_GEN_DATA1_0 Fld(8, 8, AC_FULLB1)//[15:8]
#define REG_014C_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x14C)
	#define REG_014C_EDP_TX_PHY_P0_REG_PATTERN_GEN_DATA1_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0150_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x150)
	#define REG_0150_EDP_TX_PHY_P0_REG_PATTERN_GEN_DATA1_2 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0154_EDP_TX_PHY_P0 (EDP12_TV_TX_PAR_WRAP_EDP_TX_PHY_P0 + 0x154)
	#define REG_0154_EDP_TX_PHY_P0_REG_REPEAT_COUNT Fld(7, 0, AC_MSKB0)//[6:0]
	#define REG_0154_EDP_TX_PHY_P0_REG_PATTERN_GEN_ENABLE Fld(1, 7, AC_MSKB0)//[7:7]
