/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2024 MediaTek Inc.
 */

#define TOP_XCPLL_V007 0x00201a00

//Page TOP_XCPLL_V007
#define REG_0000_XCPLL_V007 (TOP_XCPLL_V007 + 0x000)
	#define REG_0000_XCPLL_V007_REG_XCPLL_V007_PD Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0000_XCPLL_V007_REG_XCPLL_V007_PD_DROOP_BYPASS Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0000_XCPLL_V007_REG_XCPLL_V007_PD_VRINGCMP Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0004_XCPLL_V007 (TOP_XCPLL_V007 + 0x004)
	#define REG_0004_XCPLL_V007_REG_XCPLL_V007_EN_CPUCLK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0004_XCPLL_V007_REG_XCPLL_V007_EN_CPU_TEST_CLK Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0004_XCPLL_V007_REG_XCPLL_V007_EN_DIV2P5 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0004_XCPLL_V007_REG_XCPLL_V007_EN_DIV3 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0008_XCPLL_V007 (TOP_XCPLL_V007 + 0x008)
	#define REG_0008_XCPLL_V007_REG_XCPLL_V007_EN_VCO_DIV5 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0008_XCPLL_V007_REG_XCPLL_V007_EN_DIV48 Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_000C_XCPLL_V007 (TOP_XCPLL_V007 + 0x00C)
	#define REG_000C_XCPLL_V007_REG_XCPLL_V007_EN_KF0 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_000C_XCPLL_V007_REG_XCPLL_V007_EN_KP0 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_000C_XCPLL_V007_REG_XCPLL_V007_EN_KP1 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_000C_XCPLL_V007_REG_XCPLL_V007_EN_KPDIV Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0010_XCPLL_V007 (TOP_XCPLL_V007 + 0x010)
	#define REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0010_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0014_XCPLL_V007 (TOP_XCPLL_V007 + 0x014)
	#define REG_0014_XCPLL_V007_REG_XCPLL_V007_EN_POST_DIV4 Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0014_XCPLL_V007_REG_XCPLL_V007_EN_PRDT1 Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0014_XCPLL_V007_REG_XCPLL_V007_EN_PRDT2 Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0014_XCPLL_V007_REG_XCPLL_V007_EN_PRDT3 Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0018_XCPLL_V007 (TOP_XCPLL_V007 + 0x018)
	#define REG_0018_XCPLL_V007_REG_XCPLL_V007_EN_TEST Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_001C_XCPLL_V007 (TOP_XCPLL_V007 + 0x01C)
	#define REG_001C_XCPLL_V007_REG_XCPLL_V007_ICTRL Fld(3, 0, AC_MSKB0)//[2:0]
	#define REG_001C_XCPLL_V007_REG_XCPLL_V007_ICTRL_SW Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0020_XCPLL_V007 (TOP_XCPLL_V007 + 0x020)
	#define REG_0020_XCPLL_V007_REG_XCPLL_V007_INPUT_DIV Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_0020_XCPLL_V007_REG_XCPLL_V007_INPUT_SEL Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0024_XCPLL_V007 (TOP_XCPLL_V007 + 0x024)
	#define REG_0024_XCPLL_V007_REG_XCPLL_V007_LOOP_DIV_FIRST Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0028_XCPLL_V007 (TOP_XCPLL_V007 + 0x028)
	#define REG_0028_XCPLL_V007_REG_XCPLL_V007_LOOP_DIV_SECOND Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_002C_XCPLL_V007 (TOP_XCPLL_V007 + 0x02C)
	#define REG_002C_XCPLL_V007_REG_XCPLL_V007_POST_DIV Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_0030_XCPLL_V007 (TOP_XCPLL_V007 + 0x030)
	#define REG_0030_XCPLL_V007_REG_XCPLL_V007_POST_DIV_CPU Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0034_XCPLL_V007 (TOP_XCPLL_V007 + 0x034)
	#define REG_0034_XCPLL_V007_REG_XCPLL_V007_POST_DIV_KP0 Fld(2, 0, AC_MSKB0)//[1:0]
#define REG_0038_XCPLL_V007 (TOP_XCPLL_V007 + 0x038)
	#define REG_0038_XCPLL_V007_REG_XCPLL_V007_POST_DIV_KP1 Fld(3, 0, AC_MSKB0)//[2:0]
#define REG_003C_XCPLL_V007 (TOP_XCPLL_V007 + 0x03C)
	#define REG_003C_XCPLL_V007_REG_XCPLL_V007_POST_DIV_KPDIV Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0040_XCPLL_V007 (TOP_XCPLL_V007 + 0x040)
	#define REG_0040_XCPLL_V007_REG_XCPLL_V007_SYNINPLL_MODE Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0044_XCPLL_V007 (TOP_XCPLL_V007 + 0x044)
	#define REG_0044_XCPLL_V007_REG_XCPLL_V007_LOCK Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0044_XCPLL_V007_REG_XCPLL_V007_HIGH_FLAG Fld(1, 8, AC_MSKB1)//[8:8]
#define REG_0048_XCPLL_V007 (TOP_XCPLL_V007 + 0x048)
	#define REG_0048_XCPLL_V007_REG_XCPLL_V007_TEST_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_004C_XCPLL_V007 (TOP_XCPLL_V007 + 0x04C)
	#define REG_004C_XCPLL_V007_REG_XCPLL_V007_TEST_1 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0050_XCPLL_V007 (TOP_XCPLL_V007 + 0x050)
	#define REG_0050_XCPLL_V007_REG_XCPLL_V007_TEST_LDO Fld(5, 0, AC_MSKB0)//[4:0]
#define REG_0054_XCPLL_V007 (TOP_XCPLL_V007 + 0x054)
	#define REG_0054_XCPLL_V007_REG_XCPLL_V007_EN_CPUCLK_DIG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0054_XCPLL_V007_REG_XCPLL_V007_EN_CPU_TEST_CLK_DIG Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0054_XCPLL_V007_REG_XCPLL_V007_EN_DIV2P5_DIG Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0054_XCPLL_V007_REG_XCPLL_V007_EN_DIV3_DIG Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0058_XCPLL_V007 (TOP_XCPLL_V007 + 0x058)
	#define REG_0058_XCPLL_V007_REG_XCPLL_V007_EN_VCO_DIV5_DIG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0058_XCPLL_V007_REG_XCPLL_V007_EN_DIV48_DIG Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_005C_XCPLL_V007 (TOP_XCPLL_V007 + 0x05C)
	#define REG_005C_XCPLL_V007_REG_XCPLL_V007_EN_KF0_DIG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_005C_XCPLL_V007_REG_XCPLL_V007_EN_KP0_DIG Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_005C_XCPLL_V007_REG_XCPLL_V007_EN_KP1_DIG Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_005C_XCPLL_V007_REG_XCPLL_V007_EN_KPDIV_DIG Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0060_XCPLL_V007 (TOP_XCPLL_V007 + 0x060)
	#define REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK2_DIG Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK10_DIG Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCCCLK12_DIG Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_0060_XCPLL_V007_REG_XCPLL_V007_EN_OCC_DIV128_DIG Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_0064_XCPLL_V007 (TOP_XCPLL_V007 + 0x064)
	#define REG_0064_XCPLL_V007_REG_XCPLL_V007_EN_POST_DIV4_DIG Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_0080_XCPLL_V007 (TOP_XCPLL_V007 + 0x080)
	#define REG_0080_XCPLL_V007_REG_XCPLL_V007_SET_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0084_XCPLL_V007 (TOP_XCPLL_V007 + 0x084)
	#define REG_0084_XCPLL_V007_REG_XCPLL_V007_SET_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0088_XCPLL_V007 (TOP_XCPLL_V007 + 0x088)
	#define REG_0088_XCPLL_V007_REG_XCPLL_V007_STEP_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_008C_XCPLL_V007 (TOP_XCPLL_V007 + 0x08C)
	#define REG_008C_XCPLL_V007_REG_XCPLL_V007_STEP_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0090_XCPLL_V007 (TOP_XCPLL_V007 + 0x090)
	#define REG_0090_XCPLL_V007_REG_XCPLL_V007_SPAN_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_0094_XCPLL_V007 (TOP_XCPLL_V007 + 0x094)
	#define REG_0094_XCPLL_V007_REG_XCPLL_V007_SPAN_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_0098_XCPLL_V007 (TOP_XCPLL_V007 + 0x098)
	#define REG_0098_XCPLL_V007_REG_XCPLL_V007_TESTD Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_009C_XCPLL_V007 (TOP_XCPLL_V007 + 0x09C)
	#define REG_009C_XCPLL_V007_REG_XCPLL_V007_SSC_SYNC Fld(1, 0, AC_MSKB0)//[0:0]
	#define REG_009C_XCPLL_V007_REG_XCPLL_V007_SSC_MODE Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_00A0_XCPLL_V007 (TOP_XCPLL_V007 + 0x0A0)
	#define REG_00A0_XCPLL_V007_REG_XCPLL_V007_SPAN_CNT_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00A4_XCPLL_V007 (TOP_XCPLL_V007 + 0x0A4)
	#define REG_00A4_XCPLL_V007_REG_XCPLL_V007_SPAN_CNT_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00A8_XCPLL_V007 (TOP_XCPLL_V007 + 0x0A8)
	#define REG_00A8_XCPLL_V007_REG_XCPLL_V007_SEGMENT Fld(2, 0, AC_MSKB0)//[1:0]
	#define REG_00A8_XCPLL_V007_REG_XCPLL_V007_STOP_FLAG Fld(1, 4, AC_MSKB0)//[4:4]
	#define REG_00A8_XCPLL_V007_REG_XCPLL_V007_REVERSE_FLAG Fld(1, 8, AC_MSKB1)//[8:8]
	#define REG_00A8_XCPLL_V007_REG_XCPLL_V007_SSC_OFF Fld(1, 12, AC_MSKB1)//[12:12]
#define REG_00AC_XCPLL_V007 (TOP_XCPLL_V007 + 0x0AC)
	#define REG_00AC_XCPLL_V007_REG_XCPLL_V007_SSC_OFFSET_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00B0_XCPLL_V007 (TOP_XCPLL_V007 + 0x0B0)
	#define REG_00B0_XCPLL_V007_REG_XCPLL_V007_SSC_OFFSET_1 Fld(8, 0, AC_FULLB0)//[7:0]
#define REG_00B4_XCPLL_V007 (TOP_XCPLL_V007 + 0x0B4)
	#define REG_00B4_XCPLL_V007_REG_XCPLL_V007_DIV Fld(5, 0, AC_MSKB0)//[4:0]
#define REG_00B8_XCPLL_V007 (TOP_XCPLL_V007 + 0x0B8)
	#define REG_00B8_XCPLL_V007_REG_XCPLL_V007_SLD Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_00BC_XCPLL_V007 (TOP_XCPLL_V007 + 0x0BC)
	#define REG_00BC_XCPLL_V007_REG_DA_XCPLL_V007_DIE_PWRGD_05 Fld(1, 4, AC_MSKB0)//[4:4]
#define REG_00C0_XCPLL_V007 (TOP_XCPLL_V007 + 0x0C0)
	#define REG_00C0_XCPLL_V007_REG_XCPLL_V007_LOCAL_RSTZ_EN Fld(1, 0, AC_MSKB0)//[0:0]
#define REG_00F8_XCPLL_V007 (TOP_XCPLL_V007 + 0x0F8)
	#define REG_00F8_XCPLL_V007_REG_XCPLL_V007_DUMMY_0 Fld(16, 0, AC_FULLW10)//[15:0]
#define REG_00FC_XCPLL_V007 (TOP_XCPLL_V007 + 0x0FC)
	#define REG_00FC_XCPLL_V007_REG_XCPLL_V007_DUMMY_1 Fld(16, 0, AC_FULLW10)//[15:0]
