//<MStar Software>
//******************************************************************************
// MStar Software
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//<MStar Software>
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
//==============================================================================
// [mhal_hdmi.h]
// Date: 20081203
// Descriptions: Add a new layer for HW setting
//==============================================================================
#ifndef MHAL_HDMI_H
#define MHAL_HDMI_H

#include "hwreg_ddc.h"
#include "hwreg_adc_atop.h"
#include "hwreg_adc_dtop.h"
#include "hwreg_hdcp.h"
#include "hwreg_hdmi.h"
#include "hwreg_sc.h"

#include "drvXC_HDMI_if.h"
#include "apiXC.h"

//==============================================================================
//==============================================================================
/* DDC SRAM SEL (After T3) */
#define DDC_RAM_SRAM_DVI                0U
#define DDC_RAM_SRAM_ADC                1U
#define DDC_RAM_SRAM_DVI0               0U
#define DDC_RAM_SRAM_DVI1               1U
#define DDC_RAM_SRAM_DVI2               2U
#define DDC_RAM_SRAM_DVI3               3U

#define DDC_OFFSET_SRAM_DVI0            0U
#define DDC_OFFSET_SRAM_DVI1            4U
#define DDC_OFFSET_SRAM_DVI2            8U
#define DDC_OFFSET_SRAM_DVI3            12U
#define DDC_OFFSET_SRAM_ADC             16U

#define INPUT_PORT_DVI_END              INPUT_PORT_DVI3

#define ABS_MINUS(a, b)                     ((a > b)? (a -b): (b -a))

#define HDMI_GET_PORT_SELECT(a)             ((MS_U8)(a - INPUT_PORT_DVI0))

//==============================================================================
//==============================================================================

#define IRQ_DVI_CK_CHG                      BIT(0)      //#[0]
#define IRQ_HDMI_MODE_CHG                   BIT(1)    //#[1]
#define IRQ_SCART_ID0_CHG                   BIT(2)     //#[2]
#define IRQ_SCART_ID1_CHG                   BIT(3)     //#[3]
#define IRQ_SAR_DET_UPD                     BIT(4)        //#[4]
#define IRQ_RESERVE                         (BIT(7)|BIT(6)|BIT(5))                 //#[5:7]
#define IRQ_ALL_BIT                         (BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))

#define TMDS_DIGITAL_LOCK_CNT_POWER         5U
#define TMDS_DIGITAL_LOSE_RANGE             3U

#define TMDS_POWER_SWITCH_IRQ_ENABLE        0U

#define TMDS_CLOCK_CMP_VALUE0               0x06U
#define TMDS_CLOCK_CMP_VALUE1               0x65U

#define TMDS_COARSE_TUNE_14_MIN             0x11U
#define TMDS_COARSE_TUNE_20_MIN             0x00U
#define TMDS_COARSE_TUNE_20_MAX             0x1FU
#define TMDS_COARSE_TUNE_20_START           0x12U
#define TMDS_COARSE_TUNE_14_DETECT_TIME     0xFFU
#define TMDS_COARSE_TUNE_20_DETECT_TIME     0x50U
#define TMDS_COARSE_TUNE_14_AABA_NUMBER     0x50U
#define TMDS_COARSE_TUNE_20_AABA_NUMBER     0x19U
#define TMDS_FINE_TUNE_AABA_14_NUMBER       0x3FFFU
#define TMDS_FINE_TUNE_AABA_20_NUMBER       0x1FFFU
#define TMDS_FINE_TUNE_UNDER_14_THRESHOLD   0x1U
#define TMDS_FINE_TUNE_UNDER_20_THRESHOLD   0x1FFU
#define TMDS_FINE_TUNE_UNDER_20_THRESHOLD1  0x9FFU
#define TMDS_CONTINUE_START                 0xFU
#define TMDS_CONTINUOUS_NUMBER              0x350U

#define HDMI_UNDER_150M_EQ_SETTING_VALUE    3U
#define HDMI_OVER_150M_EQ_SETTING_VALUE     7U
#define HDMI_EQ_14_SETTING_VALUE            20U
#define HDMI_EQ_14_LOW_SETTING_VALUE        10U
#define HDMI_EQ_20_SETTING_VALUE            0x19U

#define HDMI_MHL_EQ_SETTING_VALUE           4U

#define TMDS_SCDC_ACCESS_ADDERSS_A8         BIT(6)

#define HDMI_AUTO_EQ_CHECK_INTERVAL         30U

#define HDMI_EQ_CAL_TRIGGER_COUNT           1000U
#define HDMI_EQ_CAL_MEASURE_COUNT           250U

#define TMDS_5V_DETECT_GPIO_ENABLE          1
#define TMDS_POST_EQ_FUNCTION_ENABLE        0
#define TMDS_ACDR_AUTO_FUNCTION_ENABLE      0
#define TMDS_POWER_SAVING_ENABLE            0
#define TMDS_SW_DETECT_SCDC_SCRAMBLE        0
#define TMDS_HDMI21_LANE3_POWER_DOWN        0

#define TMDS_DE_FILTER_HDMI14_VALUE         0xCU
#define TMDS_DE_FILTER_HDMI20_VALUE         0x5U

#define TMDS_HDCP_WINDOW_END_VALUE          0x3U
#define TMDS_HDCP2_SOURCE_READ_OFFSET       130U

#define TMDS_14_CHECK_ERROR_INTERVAL        0x1U
#define TMDS_14_CHECK_ERROR_TIMES           0x80U
#define TMDS_14_RETRIG_UNDER_75M_TIMES      10
#define TMDS_20_CHECK_ERROR_INTERVAL        0x1U
#define TMDS_20_CHECK_ERROR_TIMES           0x80U
#define TMDS_20_ERROR_HAPPEN_COUNT          3U
#define TMDS_20_ERROR_HAPPEN_DCDR_COUNT     10U
#define TMDS_20_MODE_CHANGE_COUNT           8U
#define TMDS_20_RETRIGGER_TIMES             5U
#define TMDS_AUTO_EQ_PROCESS_INTERVAL       500U
#define TMDS_AUTO_EQ_BGPROCESS_INTERVAL     100U
#define TMDS_AUTO_EQ_VERIFY_COUNT           10U
#define TMDS_FORCE_ACDR_CHECK_INTERVAL      2U
#define HDMI_VDAC_DLEV_COUNT_H20            6U  //24mv
#define HDMI_VDAC_DLEV_COUNT_PORT20         0x20U
#define TMDS_CLEAR_ERROR_STATUS_COUNT       2U

#define HDMI_DECODE_ERROR_THRESHOLD14       0x8001U
#define HDMI_DECODE_ERROR_THRESHOLD20       0x8000U
#define HDMI_AUTO_EQ_ENABLE_THRESHOLD       140U
#define HDMI_AUTO_EQ_MEDIUM_THRESHOLD       (200U)
#define HDMI_AUTO_EQ_LOW_THRESHOLD          (150U)
#define HDMI_EQ_FIXED_LOW_THRESHOLD         75U
#define HDMI_CLOCK_UNSTABLE_OFFSET          4U
#define HDMI_SCAN_PHASE_THRESHOLD           (32U)
#define HDMI_SCAN_PHASE_THRESHOLD_14        37U
#define HDMI_SCAN_PHASE_THRESHOLD_20        30U

#define HDMI_CHECK_SCRAMBLE_INTERVAL        20U
#define HDMI_POWER_SAVING_CHECK_INTERVAL    500U
#define HDMI_POWER_SAVING_CHECK_COUNT       200U
#define HDMI_HDCP_AUTH_CHECK_INTERVAL       2000U
#define HDMI_LANE_LENGTH                    4U

#define HDMI_EDID_SUPPORT_128               128U
#define HDMI_EDID_SUPPORT_256               256U
#define HDMI_EDID_SUPPORT_384               384U
#define HDMI_EDID_SUPPORT_512               512U

#define HDMI_EDID_SUPPORT_SIZE              HDMI_EDID_SUPPORT_512

#define HDMI_EDID_0BLOCK                    (0)
#define HDMI_EDID_1BLOCK                    (1)
#define HDMI_EDID_2BLOCK                    (2)
#define HDMI_EDID_3BLOCK                    (3)
#define HDMI_EDID_4BLOCK                    (4)
#define HDMI_EDID_5BLOCK                    (5)

#define HDMI_EDID_EXTENSION_FLAG_ADDRESS    (0x7EU)

#define HDMI_VCO_DVI40_CLK_THR7_21          0x02FAU
#define HDMI_VCO_DVI40_CLK_THR6_21          0x02BDU
#define HDMI_VCO_DVI40_CLK_THR5_21          0x025DU
#define HDMI_VCO_DVI40_CLK_THR4_21          0x01FAU
#define HDMI_VCO_DVI40_CLK_THR3_21          0x01A0U
#define HDMI_VCO_DVI40_CLK_THR2_21          0x013AU
#define HDMI_VCO_DVI40_CLK_THR1_21          0x00E8U

#define HDMI_VCO_DVI40_CLK_THR7_20          0x05F5U
#define HDMI_VCO_DVI40_CLK_THR6_20          0x057AU
#define HDMI_VCO_DVI40_CLK_THR5_20          0x04BAU
#define HDMI_VCO_DVI40_CLK_THR4_20          0x03F5U
#define HDMI_VCO_DVI40_CLK_THR3_20          0x0340U
#define HDMI_VCO_DVI40_CLK_THR2_20          0x0275U
#define HDMI_VCO_DVI40_CLK_THR1_20          0x01D0U

#define HDMI_VCO_DVI40_CLK_THR7_14_HALF     0x1FFAU
#define HDMI_VCO_DVI40_CLK_THR6_14_HALF     0x1FFAU
#define HDMI_VCO_DVI40_CLK_THR5_14_HALF     0x1FFAU
#define HDMI_VCO_DVI40_CLK_THR4_14_HALF     0x0FD5U
#define HDMI_VCO_DVI40_CLK_THR3_14_HALF     0x0D00U
#define HDMI_VCO_DVI40_CLK_THR2_14_HALF     0x09D5U
#define HDMI_VCO_DVI40_CLK_THR1_14_HALF     0x0740U

#define HDMI_VCO_DVI40_CLK_THR7_14_FULL     0x0BEAU
#define HDMI_VCO_DVI40_CLK_THR6_14_FULL     0x0AF5U
#define HDMI_VCO_DVI40_CLK_THR5_14_FULL     0x0975U
#define HDMI_VCO_DVI40_CLK_THR4_14_FULL     0x07EAU
#define HDMI_VCO_DVI40_CLK_THR3_14_FULL     0x0680U
#define HDMI_VCO_DVI40_CLK_THR2_14_FULL     0x04EAU
#define HDMI_VCO_DVI40_CLK_THR1_14_FULL     0x03A0U

#define HDMI_VCO_DVI40_CLK_THR7_14_2X       0x05F5U
#define HDMI_VCO_DVI40_CLK_THR6_14_2X       0x057AU
#define HDMI_VCO_DVI40_CLK_THR5_14_2X       0x04BAU
#define HDMI_VCO_DVI40_CLK_THR4_14_2X       0x03F5U
#define HDMI_VCO_DVI40_CLK_THR3_14_2X       0x0340U
#define HDMI_VCO_DVI40_CLK_THR2_14_2X       0x0275U
#define HDMI_VCO_DVI40_CLK_THR1_14_2X       0x01D0U

#define HDMI_VCO_DVI40_CLK_THR7_14_4X       0x02FAU
#define HDMI_VCO_DVI40_CLK_THR6_14_4X       0x02BDU
#define HDMI_VCO_DVI40_CLK_THR5_14_4X       0x025DU
#define HDMI_VCO_DVI40_CLK_THR4_14_4X       0x01FAU
#define HDMI_VCO_DVI40_CLK_THR3_14_4X       0x01A0U
#define HDMI_VCO_DVI40_CLK_THR2_14_4X       0x013AU
#define HDMI_VCO_DVI40_CLK_THR1_14_4X       0x00E8U

#define HDMI_CLOCK_RATE_FRL_3G_MIDDLE       0x0C22U
#define HDMI_CLOCK_RATE_FRL_6G_MIDDLE       0x1844U
#define HDMI_CLOCK_RATE_FRL_8G_MIDDLE       0x0FB0U
#define HDMI_CLOCK_RATE_FRL_10G_MIDDLE      0x139CU
#define HDMI_CLOCK_RATE_FRL_12G_MIDDLE      0x1788U
#define HDMI_CLOCK_RATE_FRL_OFFSET          0x3U

#define HDMI_XTAL_CLOCK_MHZ                 12U
#define HDMI_XTAL_DIVIDER                   128U

typedef struct
{
    MS_BOOL bNoInputFlag;
    MS_BOOL bHDMI20Flag;
    MS_BOOL bYUV420Flag;
    MS_BOOL bHDMIModeFlag;
    MS_BOOL bAutoEQEnable;
    MS_BOOL bAutoEQRetrigger;
    MS_BOOL bTimingStableFlag;
    MS_BOOL bPowerOnLane;
    MS_BOOL bPowerControlOn;
    MS_BOOL bForcePowerDown;
    MS_BOOL bIsRepeater;
    MS_BOOL bPowerSavingFlag;
    MS_BOOL bDCDRDoneFlag;
    MS_BOOL bFRLTrainingFlag;
    MS_BOOL bDDCEnableFlag;
    MS_BOOL bDEChangeFlag;
    MS_BOOL bClockStableFlag;
    MS_BOOL bVersionChangeFlag;
    MS_BOOL bActiveCableFlag;
    MS_BOOL bEQError0[HDMI_LANE_LENGTH];
    MS_BOOL bEQError1[HDMI_LANE_LENGTH];
    MS_BOOL bEQError2[HDMI_LANE_LENGTH];
    MS_BOOL bResetDCFifoFlag;
    MS_U8 ucSourceVersion;
    MS_U8 ucHDCPState;
    MS_U8 ucHDCPInt;
    MS_U8 ucHDMIInfoSource;
    MS_U8 u8FRLRate;
    MS_U8 u8FastTrainingState;
    MS_U8 u8AutoEQState;
    MS_U8 u8AutoEQ14Mode;
    MS_U8 u8CheckErrorInterval;
    MS_U8 u8RatioDetect;
    MS_U8 u8ActiveCableState;
    MS_U8 u8TryNegativeC;
    MS_U8 u8ActiveCableClearErrorStatusCount;
    MS_U8 u8ChangePHYCase;
    MS_U8 u8ClearErrorStatusCount;
    MS_U8 u8EQValue0[HDMI_LANE_LENGTH];
    MS_U8 u8EQValue1[HDMI_LANE_LENGTH];
    MS_U8 u8EQValue2[HDMI_LANE_LENGTH];
    MS_U8 u8RetriggerCount20;
    MS_U8 u8RetriggerH14Under75M;
    MS_U16 usClockCount;
    MS_U16 u16CheckErrorCount;
    MS_U16 u16AutoEQProcCounter;
    MS_U16 u16ActiveCableCheckErrorCount;
    MS_U16 u16EMPacketInfo;
    MS_U8  u8Colordepth;
} stHDMI_POLLING_INFO;

typedef struct
{
    MS_U8 ucPowerSavingState;
    MS_U16 usCase1FailCount;
    MS_U16 usCase2FailCount;
    MS_U16 usCase3FailCount;
    MS_U16 usPowerSavingTime;
    MS_U16 usPowerSavingCount;
} stHDMI_POWER_SAVING_INFO;

typedef struct
{
    MS_BOOL bWordBoundaryErrorL0;
    MS_BOOL bWordBoundaryErrorL1;
    MS_BOOL bWordBoundaryErrorL2;
    MS_BOOL bWordBoundaryErrorL3;
    MS_U16 u16DecodeErrorL0;
    MS_U16 u16DecodeErrorL1;
    MS_U16 u16DecodeErrorL2;
    MS_U16 u16DecodeErrorL3;
}stHDMI_ERROR_STATUS;

typedef struct
{
    MS_U8 u8AudioMux;
    MS_U8 u8AudioStatusEnable;
    MS_U8 u8AudioMuteEnable;
    MS_U32 u32AudioInfo_CTS;
    MS_U32 u32AudioInfo_N;
    MS_U32 u32ClockRates;
    MS_U32 u32AudioInfo_FS;
} stHDMI_AUDIO_INFO;

typedef struct
{
    MS_U16 u16HDCP22HwControlStatus;
    MS_U16 u16HDCP14IrqStatus;
} stHDMI_HDCP_INFO;

enum HDMI_SIGNAL_DETECT_TYPE
{
    HDMI_SIGNAL_DETECT_NONE = 0,
    HDMI_SIGNAL_DETECT_SQUELCH,
    HDMI_SIGNAL_DETECT_CLOCK_STABLE,
    HDMI_SIGNAL_DETECT_DATA_ENABLE,
    HDMI_SIGNAL_DETECT_HDMI_MODE,
    HDMI_SIGNAL_DETECT_HDCP_STATUS,
    HDMI_SIGNAL_DETECT_AUDIO_MUTE_EVENT,
    HDMI_SIGNAL_DETECT_YUV420,
    HDMI_SIGNAL_DETECT_EMP,
};

enum HDMI_ACTIVE_CABLE_TYPE
{
    HDMI_ACTIVE_CABLE_NONE = 0,
    HDMI_ACTIVE_CABLE_START,
    HDMI_ACTIVE_CABLE_CHECK_DLEV,
    HDMI_ACTIVE_CABLE_CHECK_PHASE,
    HDMI_ACTIVE_CABLE_EQ_FLOW_H14,
    HDMI_ACTIVE_CABLE_WAIT_EQ_FLOW_DONE_H14,
    HDMI_ACTIVE_CABLE_CHECK_STABLE_H14,
    HDMI_ACTIVE_CABLE_EQ_FLOW_H20,
    HDMI_ACTIVE_CABLE_WAIT_EQ_FLOW_DONE_H20,
    HDMI_ACTIVE_CABLE_CHECK_STABLE_H20,
    HDMI_ACTIVE_CABLE_FINISH,
};

enum HDMI_CHANGE_PHY_TYPE
{
    HDMI_CHANGE_PHY_NONE = 0,
    HDMI_CHANGE_PHY_H14_CASE0,
    HDMI_CHANGE_PHY_H14_CASE1,
    HDMI_CHANGE_PHY_H14_CASE2,
    HDMI_CHANGE_PHY_H14_CASE3,
    HDMI_CHANGE_PHY_H14_CASE4,
    HDMI_CHANGE_PHY_H14_75M_TO_135M_CASE0,
    HDMI_CHANGE_PHY_H14_75M_TO_135M_CASE1,
    HDMI_CHANGE_PHY_H14_75M_TO_135M_CASE2,
    HDMI_CHANGE_PHY_H20_CASE0,
    HDMI_CHANGE_PHY_H20_CASE1,
    HDMI_CHANGE_PHY_H20_CASE2,
    HDMI_CHANGE_PHY_FINISH,
};

enum HDMI_FAST_TRAINING_TYPE
{
    HDMI_FAST_TRAINING_NONE = 0,
    HDMI_FAST_TRAINING_START,
    HDMI_FAST_TRAINING_SQUELCH,
    HDMI_FAST_TRAINING_CHECK_AUTO_EQ,
    HDMI_FAST_TRAINING_CHECK_ACTIVE_CABLE,
    HDMI_FAST_TRAINING_WAIT_EQ_FLOW_DONE_H14,
    HDMI_FAST_TRAINING_CLEAR_ERROR_H14,
    HDMI_FAST_TRAINING_CHECK_EQ0_H14,
    HDMI_FAST_TRAINING_CHECK_EQ1_H14,
    HDMI_FAST_TRAINING_CHECK_EQ2_H14,
    HDMI_FAST_TRAINING_CHECK_STABLE_H14,
    HDMI_FAST_TRAINING_TRY_NEGATIVE_C_H14,
    HDMI_FAST_TRAINING_CHANGE_PHY_H14,
    HDMI_FAST_TRAINING_CLEAR_ERROR_H14_75M_TO_135M,
    HDMI_FAST_TRAINING_CHECK_STABLE_H14_75M_TO_135M,
    HDMI_FAST_TRAINING_CHANGE_PHY_H14_75M_TO_135M,
    HDMI_FAST_TRAINING_CLEAR_ERROR_H14_UNDER_75M,
    HDMI_FAST_TRAINING_CHECK_STABLE_H14_UNDER_75M,
    HDMI_FAST_TRAINING_WAIT_EQ_FLOW_DONE_H20,
    HDMI_FAST_TRAINING_FORCE_PGA_PATCH_H20,
    HDMI_FAST_TRAINING_CLEAR_ERROR_H20,
    HDMI_FAST_TRAINING_CHECK_STABLE_H20,
    HDMI_FAST_TRAINING_CHANGE_PHY_H20,
    HDMI_FAST_TRAINING_WAIT_EQ_FLOW_DONE_H21,
    HDMI_FAST_TRAINING_CLEAR_DE_UNSTABLE_H21,
    HDMI_FAST_TRAINING_CHECK_DE_STABLE_H21,
    HDMI_FAST_TRAINING_CLEAR_ERROR_H21,
    HDMI_FAST_TRAINING_CHECK_STABLE_H21,
    HDMI_FAST_TRAINING_STOP,
    HDMI_FAST_TRAINING_FINISH,
};

typedef enum
{
    HDMI_14_TMDS_CLOCK_NONE = 0,
    HDMI_14_TMDS_CLOCK_UNDER_75M,
    HDMI_14_TMDS_CLOCK_75M_TO_135M,
    HDMI_14_TMDS_CLOCK_OVER_135M,
}EN_HDMI_14_TMDS_CLOCK_RANGE;

typedef enum
{
    HDMI_TMDS_CLOCK_H14_BAND0 = 0,
    HDMI_TMDS_CLOCK_H14_BAND1,
    HDMI_TMDS_CLOCK_H14_BAND2,
    HDMI_TMDS_CLOCK_H14_BAND3,
    HDMI_TMDS_CLOCK_H14_BAND4,
    HDMI_TMDS_CLOCK_H14_BAND5,
    HDMI_TMDS_CLOCK_H14_BAND6,
    HDMI_TMDS_CLOCK_H20_BAND0,
    HDMI_TMDS_CLOCK_H20_BAND1,
    HDMI_TMDS_CLOCK_H20_BAND2,
    HDMI_TMDS_CLOCK_H20_BAND3,
    HDMI_TMDS_CLOCK_NUMOF_BAND,
}EN_HDMI_TMDS_CLOCK_DETECT_BAND;

enum HDMI_FAST_TRAINING_RESULT_TYPE
{
    HDMI_FAST_TRAINING_RESULT_NONE = 0,
    HDMI_FAST_TRAINING_RESULT_MULTI_TRIGGER,
    HDMI_FAST_TRAINING_RESULT_IN_FRL,
    HDMI_FAST_TRAINING_RESULT_STABLE_READY,
    HDMI_FAST_TRAINING_RESULT_ALL_CASE_CHECK,
    HDMI_FAST_TRAINING_RESULT_PASS,
};

enum HDMI_FRL_TRAINING_STATE_TYPE
{
    HDMI_FRL_TRAINING_STATE_IDLE = 0,
    HDMI_FRL_TRAINING_STATE_CR_DONE,
    HDMI_FRL_TRAINING_STATE_EQ_DONE,
    HDMI_FRL_TRAINING_STATE_NORMAL_DONE,
    HDMI_FRL_TRAINING_STATE_NONE,
};

enum HDMI_FRL_MODE_TYPE
{
    HDMI_FRL_MODE_LEGACY = 0,
    HDMI_FRL_MODE_FRL_3G_3CH,
    HDMI_FRL_MODE_FRL_6G_3CH,
    HDMI_FRL_MODE_FRL_6G_4CH,
    HDMI_FRL_MODE_FRL_8G,
    HDMI_FRL_MODE_FRL_10G,
    HDMI_FRL_MODE_FRL_12G,
    HDMI_FRL_MODE_NONE,
    HDMI_FRL_MODE_LEGACY_14,
    HDMI_FRL_MODE_LEGACY_20,
};

enum HDMI_AUTO_EQ_STATE_TYPE
{
    HDMI_AUTO_EQ_START = 0,
    HDMI_AUTO_EQ_WAIT_DONE,
    HDMI_AUTO_EQ_FINISH_PROCESS,
    HDMI_AUTO_EQ_CHECK_STABLE,
    HDMI_AUTO_EQ_CHECK_DONE,
    HDMI_AUTO_EQ_14_CLEAR_STATUS,
    HDMI_AUTO_EQ_14_CHECK_STATUS,
    HDMI_AUTO_EQ_14_CHANGE_SETTING,
    HDMI_AUTO_EQ_20_CLEAR_STATUS,
    HDMI_AUTO_EQ_20_CHECK_STATUS,
    HDMI_AUTO_EQ_20_CHANGE_SETTING,
    HDMI_AUTO_EQ_DCDR_POLLING,
    HDMI_AUTO_EQ_STABLE_DONE,
    HDMI_AUTO_EQ_NONE,
    HDMI_AUTO_EQ_20_CHANGE_ACDR,
    HDMI_AUTO_EQ_FORCE_INTO_ACDR,
    HDMI_AUTO_EQ_20_ACDR_WAIT_DONE,
    HDMI_AUTO_EQ_20_DCDR_WAIT_DONE,
    HDMI_AUTO_EQ_20_DCDR_WAIT_STABLE,
};

enum HDMI_SOURCE_VERSION_TYPE
{
    HDMI_SOURCE_VERSION_NOT_SURE = 0,
    HDMI_SOURCE_VERSION_HDMI14,
    HDMI_SOURCE_VERSION_HDMI20,
    HDMI_SOURCE_VERSION_HDMI21,
};

enum HDMI_HDCP_STATE
{
    HDMI_HDCP_NO_ENCRYPTION = 0,
    HDMI_HDCP_1_4,
    HDMI_HDCP_2_2,
};

enum HDMI_HDCP_ENCRYPTION_STATE
{
    HDMI_HDCP_NOT_ENCRYPTION = 0,
    HDMI_HDCP_1_4_ENCRYPTION,
    HDMI_HDCP_2_2_ENCRYPTION,
};

enum HDMI_5V_DETECT_GPIO_TYPE
{
    HDMI_5V_DETECT_GPIO_NONE = 0,
    HDMI_5V_DETECT_GPIO_INDEX00,
    HDMI_5V_DETECT_GPIO_INDEX01,
    HDMI_5V_DETECT_GPIO_INDEX02,
    HDMI_5V_DETECT_GPIO_INDEX03,
    HDMI_5V_DETECT_GPIO_INDEX04,
    HDMI_5V_DETECT_GPIO_INDEX05,
    HDMI_5V_DETECT_GPIO_INDEX06,
    HDMI_5V_DETECT_GPIO_INDEX07,
    HDMI_5V_DETECT_GPIO_INDEX08,
    HDMI_5V_DETECT_GPIO_INDEX09,
    HDMI_5V_DETECT_GPIO_INDEX10,
    HDMI_5V_DETECT_GPIO_INDEX11,
    HDMI_5V_DETECT_GPIO_INDEX12,
    HDMI_5V_DETECT_GPIO_INDEX13,
    HDMI_5V_DETECT_GPIO_INDEX14,
    HDMI_5V_DETECT_GPIO_INDEX15,
    HDMI_5V_DETECT_GPIO_INDEX16,
    HDMI_5V_DETECT_GPIO_INDEX17,
    HDMI_5V_DETECT_GPIO_INDEX18,
    HDMI_5V_DETECT_GPIO_INDEX19,
    HDMI_5V_DETECT_GPIO_INDEX20,
    HDMI_5V_DETECT_GPIO_INDEX21,
    HDMI_5V_DETECT_GPIO_INDEX22,
    HDMI_5V_DETECT_GPIO_INDEX23,
    HDMI_5V_DETECT_GPIO_INDEX24,
    HDMI_5V_DETECT_GPIO_INDEX25,
};

enum HDMI_AUTO_EQ_14_MODE_TYPE
{
    HDMI_AUTO_EQ_14_MODE0 = 0,
    HDMI_AUTO_EQ_14_MODE1,
    HDMI_AUTO_EQ_14_MODE2,
    HDMI_AUTO_EQ_14_MODE3,
    HDMI_AUTO_EQ_14_MODE_MASK,
};

enum HDMI_AUTO_EQ_20_MODE_TYPE
{
    HDMI_AUTO_EQ_20_MODE0 = 0,
    HDMI_AUTO_EQ_20_MODE1,
    HDMI_AUTO_EQ_20_MODE2,
    HDMI_AUTO_EQ_20_MODE_MASK,
};

enum HDMI_STATUS_FLAG_TYPE
{
    HDMI_STATUS_MPEG_PACKET_RECEIVE_FLAG = BIT(0),
    HDMI_STATUS_AUDIO_PACKET_RECEIVE_FLAG = BIT(1),
    HDMI_STATUS_SPD_PACKET_RECEIVE_FLAG = BIT(2),
    HDMI_STATUS_AVI_PACKET_RECEIVE_FLAG = BIT(3),
    HDMI_STATUS_GCP_PACKET_RECEIVE_FLAG = BIT(4),
    HDMI_STATUS_AUDIO_SAMPLE_PACKET_RECEIVE_FLAG = BIT(5),
    HDMI_STATUS_ACR_PACKET_RECEIVE_FLAG = BIT(6),
    HDMI_STATUS_VS_PACKET_RECEIVE_FLAG = BIT(7),
    HDMI_STATUS_NULL_PACKET_RECEIVE_FLAG = BIT(8),
    HDMI_STATUS_ISRC2_PACKET_RECEIVE_FLAG = BIT(9),
    HDMI_STATUS_ISRC1_PACKET_RECEIVE_FLAG = BIT(10),
    HDMI_STATUS_ACP_PACKET_RECEIVE_FLAG = BIT(11),
    HDMI_STATUS_DSD_PACKET_RECEIVE_FLAG = BIT(12),
    HDMI_STATUS_GM_PACKET_RECEIVE_FLAG = BIT(13),
    HDMI_STATUS_HBR_PACKET_RECEIVE_FLAG = BIT(14),
    HDMI_STATUS_VBI_PACKET_RECEIVE_FLAG = BIT(15),
    HDMI_STATUS_HDR_PACKET_RECEIVE_FLAG = BIT(16),
    HDMI_STATUS_RESERVED_PACKET_RECEIVE_FLAG = BIT(17),
    HDMI_STATUS_EDR_VALID_FLAG = BIT(18),
    HDMI_STATUS_AUDIO_DST_RECEIVE_FLAG = BIT(19),
    HDMI_STATUS_AUDIO_3D_ASP_RECEIVE_FLAG = BIT(20),
    HDMI_STATUS_AUDIO_3D_DSD_RECEIVE_FLAG = BIT(21),
    HDMI_STATUS_AUDIO_METADATA_RECEIVE_FLAG = BIT(22),
    HDMI_STATUS_AUDIO_MULTI_ASP_RECEIVE_FLAG = BIT(23),
    HDMI_STATUS_AUDIO_MULTI_DSD_RECEIVE_FLAG = BIT(24),
    HDMI_STATUS_EM_PACKET_RECEIVE_FLAG = BIT(25),
};

enum HDMI_BCH_ERROR_TYPE
{
    HDMI_BCH_ERROR_CORRECTED = BIT(0),
    HDMI_BCH_ERROR = BIT(1),
    HDMI_CHECKSUM_ERROR = BIT(2),
};

enum HDMI_INFO_SOURCE_TYPE
{
    HDMI_INFO_SOURCE0 = 0,
    HDMI_INFO_SOURCE1,
    HDMI_INFO_SOURCE2,
    HDMI_INFO_SOURCE3,
    HDMI_INFO_SOURCE_MAX,
    HDMI_INFO_SOURCE_NONE,
};

enum HDMI_AUDIO_PATH_TYPE
{
    HDMI_AUDIO_PATH0 = 0,
    HDMI_AUDIO_PATH1,
    HDMI_AUDIO_PATH2,
    HDMI_AUDIO_PATH3,
    HDMI_AUDIO_PATH_MAX,
    HDMI_AUDIO_PATH_NONE,
};

enum HDMI_CHECK_PACKET_TYPE
{
    HDMI_CHECK_PACKET_CLEAR_RECEIVE_STATUS = 0,
    HDMI_CHECK_PACKET_WAIT_AVI_PACKET,
    HDMI_CHECK_PACKET_MEASURE_PACKET_INTERVAL,
    HDMI_CHECK_PACKET_UPDATE_RECEIVE_STATUS,
};

enum HDMI_POWER_SAVING_TEST_TYPE
{
    HDMI_POWER_SAVING_START = 0,
    HDMI_POWER_SAVING_ENABLE,
    HDMI_POWER_SAVING_WAIT_FAIL1,
    HDMI_POWER_SAVING_HPD_LOW,
    HDMI_POWER_SAVING_HPD_HIGH,
    HDMI_POWER_SAVING_WAIT_STATUS,
    HDMI_POWER_SAVING_WAIT_FAIL2,
    HDMI_POWER_SAVING_DISABLE,
    HDMI_POWER_SAVING_WAIT_FAIL3,
    HDMI_POWER_SAVING_FINISH,
};

enum HDMI_AUDIO_MUTE_EVENT
{
    HDMI_CTSN_OVERRANGE = BIT(0),
    HDMI_CLOCK_BIG_CHANGE = BIT(1),
    HDMI_AVMUTE = BIT(2),
    HDMI_NO_INPUT_CLOCK= BIT(3),
    HDMI_AUDIO_SAMPLE_FLAT_BIT = BIT(4),
    HDMI_AUDIO_PRESENT_BIT_ERROR = BIT(5),
    HDMI_AUDIO_FIFO_OVERFLOW_UNDERFLOW = BIT(6),
    HDMI_AUDIO_SAMPLE_PARITY_ERROR = BIT(7),
};

enum HDMI_ACDR_CHANNEL_TYPE
{
    HDMI_ACDR_CHANNEL_B = 0,
    HDMI_ACDR_CHANNEL_G,
    HDMI_ACDR_CHANNEL_R,
    HDMI_ACDR_CHANNEL_NONE,
};

enum HDMI_SW_RESET_TYPE
{
    HDMI_SW_RESET_DVI = BIT(4),
    HDMI_SW_RESET_HDCP = BIT(5),
    HDMI_SW_RESET_HDMI = BIT(6),
    HDMI_SW_RESET_DVI2MIU = BIT(10),
    HDMI_SW_RESET_AUDIO_FIFO = BIT(15),
};

enum HDMI_RESET_PHY_DTOP
{
    HDMI_RESET_PHY_DTOP_SYNTH = BIT(0),
    HDMI_RESET_PHY_DTOP_IRQ = BIT(1),
    HDMI_RESET_PHY_DTOP_1ST_FIFO = BIT(2),
    HDMI_RESET_PHY_DTOP_AFIFO = BIT(3),
    HDMI_RESET_PHY_DTOP_40to36_FIFO = BIT(4),
    HDMI_RESET_PHY_DTOP_SQH = BIT(5),
    HDMI_RESET_PHY_DTOP_LANE0 = BIT(6),
    HDMI_RESET_PHY_DTOP_LANE1 = BIT(7),
    HDMI_RESET_PHY_DTOP_LANE2 = BIT(8),
    HDMI_RESET_PHY_DTOP_LANE3 = BIT(9),
    HDMI_RESET_PHY_DTOP_FREQ_DET = BIT(10),
    HDMI_RESET_PHY_DTOP_MISC = BIT(11),
    HDMI_RESET_PHY_DTOP_CLOCK_DET = BIT(12),
    HDMI_RESET_PHY_DTOP_LONG_ZERO_ONE = BIT(13),
};

enum HDMI_FREE_SYNC_TYPE
{
    HDMI_FREE_SYNC_SUPPORTED = BIT(0),
    HDMI_FREE_SYNC_ENABLED = BIT(1),
    HDMI_FREE_SYNC_ACTIVE = BIT(2),
};

enum HDMI_EM_PACKET_STATUS_TYPE
{
    HDMI_EM_PACKET_DSC_ENABLE = BIT(0),
    HDMI_EM_PACKET_VRR_ENABLE = BIT(1),
    HDMI_EM_PACKET_VENDOR_ENABLE = BIT(2),
    HDMI_EM_PACKET_FVA_ENABLE = BIT(3),
    HDMI_EM_PACKET_HDR_ENABLE = BIT(4),
};

typedef enum
{
    HDMI_TIMING_DETECT_4_0 = 0, // (4) - 0, for legacy
    HDMI_TIMING_DETECT_4_1, // (4) - 1, for legacy
    HDMI_TIMING_DETECT_4_2, // (4) - 2, for FRL
    HDMI_TIMING_DETECT_4_3, // (4) - 3, for FRL
    HDMI_TIMING_DETECT_5_0, // (5) - 0
}EN_HDMI_TIMING_DETECT_PATH;

enum HDMI_COLORDEPTH_TYPE
{
    HDMI_COLOR_DEPTH_8BIT = 0,
    HDMI_COLOR_DEPTH_10BIT,
    HDMI_COLOR_DEPTH_12BIT,
    HDMI_COLOR_DEPTH_16BIT,
    HDMI_COLOR_DEPTH_NONE,
};

#define HDMI_PACKET_RECEIVE_INTERVAL_MIN    4
#define HDMI_PACKET_RECEIVE_INTERVAL_MAX    11

//==================================== EARC =====================================
#ifdef MSOS_TYPE_ECOS
#define HDMI_EARC_POLLING_STACK_SIZE             2048U
#else
#define HDMI_EARC_POLLING_STACK_SIZE             1U
#endif

#define HDMI_EARCTX_SELECT_ATOP_MODE             EARC_ATOP_MODE2

typedef struct
{
    MS_BOOL bCapChangeFlag;
    MS_BOOL bCapChangeTmpFlag;
    MS_BOOL bStatChangeFlag;
    MS_BOOL bStatChangeTmpFlag;
    MS_BOOL bSetLatencyFlag;
    MS_BOOL bCommonModeCapBusyFlag;
    MS_BOOL bCommonModeStatBusyFlag;
    MS_BOOL bCommonModeSetLatencyBusyFlag;
    MS_BOOL bCapChangeUpdateDoneFlag;
    MS_BOOL bStatChangeUpdateDoneFlag;
    MS_U16 u16OPCodeOffset;
    MS_U8 u8OPCodeDeviceID;
    MS_U8 u8TransactionState;
    MS_U8 u8TransactionResult;
    MS_U8 u8TransactioinRetryCnt;
    MS_U8 u8TransactionDataThreshold;
    MS_U8 u8CapabilityContent[256];
    MS_U8 u8LatencyContent;
    MS_U8 u8SetLatencyValue;
}stHDMI_EARCTX_COMMON_MODE_POLLING_INFO;

typedef struct _HDMI_EARCTX_RESOURCE_PRIVATE
{
    MS_BOOL bSelfCreateTaskFlag;
    MS_BOOL bEARCTaskProcFlag;
    MS_BOOL bEnable5VDetectInvert;
    MS_BOOL bEnableHPDInvert;
    MS_U8 u8EARCOutputPort;
    MS_U8 u8EARCTXConnectState;
    MS_U8 ucEARCPollingStack[HDMI_EARC_POLLING_STACK_SIZE];
    MS_S32 slEARCPollingTaskID;
    EN_POWER_MODE usPrePowerState;
    stHDMI_EARCTX_COMMON_MODE_POLLING_INFO stHDMIEARCTXCommonModePollinfInfo;
}HDMI_EARCTX_RESOURCE_PRIVATE;

enum EARC_ATOP_SELECT_MODE
{
    EARC_ATOP_MODE1 = 1,
    EARC_ATOP_MODE2,
};

enum HDMI_EARCTX_TRANSACTION_STATE
{
    HDMI_EARCTX_SET_OP_CODE_INFO,
    HDMI_EARCTX_WAIT_RX_HEARTBEAT_STATUS,
    HDMI_EARCTX_SET_DATA_CONTENT,
    HDMI_EARCTX_FIFO_WRITE_PULSE,
    HDMI_EARCTX_READ_TRIGGER,
    HDMI_EARCTX_WRITE_TRIGGER,
    HDMI_EARCTX_WAIT_READ_TRANSATION_DONE,
    HDMI_EARCTX_WAIT_WRITE_TRANSATION_DONE,
    HDMI_EARCTX_READ_DATA_CONTENT,
    HDMI_EARCTX_TRANSATION_FINISH,
    HDMI_EARCTX_TRANSATION_NONE,
};

enum HDMI_EARCTX_TRANSACTION_RESULT_TYPE
{
    HDMI_EARCTX_FREE,
    HDMI_EARCTX_FAIL,
    HDMI_EARCTX_ECC_ERROR,
    HDMI_EARCTX_RETRY_FORCE_STOP,
    HDMI_EARCTX_CONT_FORCE_STOP,
    HDMI_EARCTX_TRANSACTION_DONE,
};
//==================================== EARC =====================================

//==============================================================================
//==============================================================================
#ifdef MHAL_HDMI_C
#define INTERFACE
#else
#define INTERFACE extern
#endif

INTERFACE MS_BOOL Hal_HDCP_GetEncryptionFlag(E_MUX_INPUTPORT enInputPortType);
INTERFACE MS_U16 Hal_HDMI_Func_Caps(void);
////--------------> for HDCP
//INTERFACE void Hal_HDCP_clearflag( void );
INTERFACE void Hal_HDCP_ddc_en(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnable);
INTERFACE void Hal_HDCP_Vsync_end_en( MS_BOOL bEnalbe );

////--------------> for HDMI
INTERFACE void Hal_HDMI_pullhpd(MS_BOOL bHighLow, E_MUX_INPUTPORT enInputPortType, MS_BOOL bInverse, MS_U8 ucMHLSupportPath);
INTERFACE void Hal_HDMI_init(MS_BOOL bImmeswitchSupport, MS_U8 ucMHLSupportPath);
//INTERFACE void Hal_HDMI_init( void );
INTERFACE void Hal_HDMI_exit(E_MUX_INPUTPORT enInputPortType);

INTERFACE void Hal_HDMI_Set_EQ(E_MUX_INPUTPORT enInputPortType, MS_HDMI_EQ enEq, MS_U8 u8EQValue);
INTERFACE MS_U8 Hal_HDMI_GetGCPColorDepth(E_MUX_INPUTPORT enInputPortType, MS_U32 u32PacketStatus);
INTERFACE void Hal_HDMI_Audio_MUTE_Enable(MS_U16 u16MuteEvent, MS_U16 u16MuteMask);
INTERFACE void Hal_HDMI_Audio_Status_Clear(stHDMI_POLLING_INFO *stHDMIPollingInfo);

INTERFACE MS_U16 Hal_HDMI_gcontrol_info(HDMI_GControl_INFO_t gcontrol, MS_U8 ucHDMIInfoSource);
INTERFACE MS_U16 Hal_HDMI_pll_ctrl1(HDMI_PLL_CTRL_t pllctrl, MS_BOOL bread, MS_U16 u16value);
INTERFACE MS_U16 Hal_HDMI_pll_ctrl2(HDMI_PLL_CTRL2_t pllctrl, MS_BOOL bread, MS_U16 u16value);
INTERFACE MS_U16 Hal_HDMI_GetHDEInfo(MS_U8 ucHDMIInfoSource);
INTERFACE MS_U16 Hal_HDMI_GetDataInfo(E_HDMI_GET_DATA_INFO enInfo, MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_DVI_Accumulator_Monitor( void );

INTERFACE void Hal_DVI_HF_adjust( void );
INTERFACE void Hal_HDMI_ForcePowerDownPort(E_MUX_INPUTPORT enInputPortType, stHDMI_POLLING_INFO *pstHDMIPollingInfo, MS_BOOL bPowerDown);

////--------------> for HDMI Audio
INTERFACE void Hal_HDMI_audio_output(MS_BOOL bEnable);
INTERFACE MS_U8 Hal_HDMI_Get_Audio_Mux(void);

////--------------> for DVI
INTERFACE MS_BOOL Hal_DVI_clk_lessthan70mhz_usingportc( MS_BOOL bIsPortC);
INTERFACE MS_U16 Hal_DVI_ChannelPhaseStatus( MS_U8 u8Channel);
INTERFACE MS_BOOL Hal_DVI_clk_stable_usingportc(MS_BOOL bIsPortC);
INTERFACE MS_BOOL Hal_DVI_clklose_det(E_MUX_INPUTPORT enInputPortType);
INTERFACE void Hal_DVI_IMMESWITCH_PS_SW_Path(void);
INTERFACE void Hal_DVI_sw_reset(MS_U16 u16Reset);
INTERFACE MS_U16 Hal_DVI_irq_info(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit);
INTERFACE void Hal_DVI_irq_mask(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit);
INTERFACE void Hal_DVI_irq_forcemode(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit);
INTERFACE void Hal_DVI_irq_clear(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit);
INTERFACE void Hal_DVI_ClkPullLow(MS_BOOL bPullLow, E_MUX_INPUTPORT enInputPortType);
INTERFACE void Hal_DVI_SwitchSrc(E_MUX_INPUTPORT enInputPortType, MS_U8 ucHDMIInfoSource);

INTERFACE MS_U8 Hal_HDMI_err_status_update(MS_U8 ucHDMIInfoSource, MS_U8 u8value, MS_BOOL bread, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_pkt_reset(E_MUX_INPUTPORT enInputPortType, MS_U8 u8HDMIInfoSource, HDMI_REST_t enResetType, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_hpd_en(MS_BOOL benable);
INTERFACE void Hal_HDCP_initproductionkey( MS_U8 * pu8HdcpKeyData );
INTERFACE void Hal_HDCP_clearflag(E_MUX_INPUTPORT enInputPortType);
INTERFACE void Hal_HDMI_audio_output( MS_BOOL bEnable );
INTERFACE MS_U32 Hal_HDMI_packet_info(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_U8 Hal_HDMI_GetPacketReceiveCount(MS_U8 u8HDMIInfoSource, MS_U8 u8PrePacketReceiveCount, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_U8 Hal_HDMI_audio_content_protection_info(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE EN_AVI_INFOFRAME_VERSION Hal_HDMI_avi_infoframe_info_ver(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_U8 Hal_HDMI_avi_infoframe_info(MS_U8 ucHDMIInfoSource, MS_U8 u8byte, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_BOOL Hal_HDMI_get_packet_value(MS_U8 ucHDMIInfoSource, MS_HDMI_PACKET_STATE_t u8state, MS_U8 u8byte_idx, MS_U8 *pu8Value, stHDMI_POLLING_INFO *pstHDMIPollingInfo);

INTERFACE MS_U8 Hal_HDMI_audio_channel_status(MS_U8 ucHDMIInfoSource, MS_U8 u8byte, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_U16 Hal_HDCP_getstatus(E_MUX_INPUTPORT enInputPortType);
INTERFACE void Hal_DVI_adc_adjust( MS_BOOL bClockLessThan70MHz);

INTERFACE void Hal_HDMI_packet_ctrl(MS_U8 ucHDMIInfoSource, MS_U16 u16pkt, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_U8 Hal_HDMI_audio_payload_info(MS_U8 ucHDMIInfoSource, MS_U8 u8byte, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE E_HDMI_HDCP_STATE Hal_HDCP_GetAuthVersion(E_MUX_INPUTPORT enInputPortType, MS_BOOL bSetFlag);

// DDC
INTERFACE void HAL_HDMI_DDCRam_SelectPort(E_XC_DDCRAM_PROG_TYPE eDDCRamType);
INTERFACE void HAL_HDMI_DDCRAM_SetPhyAddr(XC_DDCRAM_PROG_INFO *pstDDCRam_Info);
INTERFACE void HAL_HDMI_LoadEDIDNewMode(E_XC_DDCRAM_PROG_TYPE eDDCRamType, MS_U16 u16EDIDSize, MS_U8 *pu8EDIDTable);
INTERFACE void HAL_HDMI_ReadEDIDNewMode(E_XC_DDCRAM_PROG_TYPE eDDCRamType, MS_U16 u16EDIDSize, MS_U8 *pu8EDIDTable);

// HDMI 1.4 new feature:
INTERFACE E_HDMI_ADDITIONAL_VIDEO_FORMAT Hal_HDMI_Check_Additional_Format(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE E_XC_3D_INPUT_MODE Hal_HDMI_Get_3D_Structure(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE E_HDMI_3D_EXT_DATA_T Hal_HDMI_Get_3D_Ext_Data(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_Get_3D_Meta_Field(MS_U8 ucHDMIInfoSource, sHDMI_3D_META_FIELD *pdata, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_U8 Hal_HDMI_Get_VIC_Code(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE E_HDMI_VIC_4Kx2K_CODE Hal_HDMI_Get_4Kx2K_VIC_Code(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_Set_YUV422to444_Bypass(MS_BOOL btrue);
INTERFACE MS_BOOL Hal_HDMI_Is_Input_Large_166MHz(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_AVG_ScaleringDown(MS_U8 ucHDMIInfoSource, MS_BOOL btrue);
INTERFACE void Hal_HDMI_ARC_PINControl(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnable, MS_BOOL bDrivingHigh);
INTERFACE void Hal_DVI_Software_Reset(E_MUX_INPUTPORT enInputPortType, MS_U16 u16Reset);

MS_BOOL Hal_DVI_GetPowerSavingStatus(E_MUX_INPUTPORT enInputPortType);
MS_BOOL Hal_DVI_GetDEStableStatus(E_MUX_INPUTPORT enInputPortType);
void Hal_DVI_EnhanceImmeswitch(E_MUX_INPUTPORT enInputPortType, MS_BOOL bflag);
void Hal_DVI_ForceAllPortsEnterPS(void);

//EX_ADD
INTERFACE MS_U16 Hal_HDMI_GetTMDSFreq(void);
INTERFACE MS_BOOL Hal_HDMI_CheckHDMI20_Setting(E_MUX_INPUTPORT enInputPortType);
INTERFACE void Hal_HDMI_StablePolling(MS_U8 ucMHLSupportPath, MS_U32 *ulPacketStatus, stHDMI_POLLING_INFO *stHDMIPollingInfo, HDCP14_AccessWriteProtectedReg_CBF fpHdcp14_AccessWriteProtectedReg);

INTERFACE void Hal_HDMI_Set5VDetectGPIOSelect(MS_U32 ul5VDetectGPIOIndex);

INTERFACE void Hal_HDMI_SwitchVSDBtoHDRPacket(MS_BOOL bEnableHDR);

INTERFACE MS_BOOL Hal_HDMI_Get_InfoFrame(MS_U8 ucHDMIInfoSource, MS_HDMI_PACKET_STATE_t u8state, void *pData, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_DataRtermControl(E_MUX_INPUTPORT enInputPortType, MS_BOOL bDataRtermEnable);
INTERFACE MS_U8 Hal_HDMI_GetSCDCValue(E_MUX_INPUTPORT enInputPortType, MS_U8 u8Offset);
INTERFACE MS_BOOL Hal_HDMI_GetSCDCCableDetectFlag(E_MUX_INPUTPORT enInputPortType);
INTERFACE MS_U8 Hal_HDMI_GetSourceSelect(E_MUX_INPUTPORT enInputPortType);
INTERFACE MS_U8 Hal_HDMI_GetPortToSourceMapping(E_MUX_INPUTPORT enInputPortType);
INTERFACE MS_BOOL Hal_HDMI_GetAverageModeFlag(E_MUX_INPUTPORT enInputPortType);
INTERFACE MS_U8 Hal_HDMI_GetISRC1HeaderInfo(MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE void Hal_HDMI_Get_AudioInfo(stHDMI_AUDIO_INFO *pstAudioInfo, MS_U8 ucHDMIInfoSource, stHDMI_POLLING_INFO *pstHDMIPollingInfo);

INTERFACE MS_BOOL Hal_HDCP14_PollingR0ReadDone(MS_U8 ucPortIdx);
//INTERFACE void Hal_HDCP22_InitCBFunc(HDCP22_Recv_CBF pCBFunc, void* pContext);
INTERFACE void Hal_HDCP22_SetReadyBit(MS_U8 ucPortIdx, MS_BOOL bIsReady);
INTERFACE void Hal_HDCP22_PortInit(MS_U8 ucPortIdx);
INTERFACE MS_BOOL Hal_HDCP22_PollingWriteDone(MS_U8 ucPortIdx);
INTERFACE MS_BOOL Hal_HDCP22_PollingReadDone(MS_U8 ucPortIdx);
INTERFACE void Hal_HDCP22_EnableCipher(MS_U8 ucPortType, MS_U8 ucPortIdx, MS_BOOL bIsEnable);
INTERFACE void Hal_HDCP22_FillCipherKey(MS_U8 ucPortIdx, MS_U8 *pucSessionKey, MS_U8 *pucRiv);
INTERFACE void Hal_HDCP22_FetchMsg(MS_U8 ucPortIdx, MS_U8* pucData, MS_U32 dwDataLen);
INTERFACE MS_BOOL Hal_HDCP22_RecvMsg(MS_U8 ucPortIdx, MS_U8 *ucMsgData);
INTERFACE void Hal_HDCP22_SendMsg(MS_U8 ucPortType, MS_U8 ucPortIdx, MS_U8* pucData, MS_U32 dwDataLen, void* pDummy, MS_U8* ubRecIDListSetDone);
/*************************** HDCP Repeater ***************************/
INTERFACE MS_BOOL Hal_HDCP_WriteX74(E_MUX_INPUTPORT enInputPortType, MS_U8 ubOffset, MS_U8 ubData);
INTERFACE MS_U8 Hal_HDCP_ReadX74(E_MUX_INPUTPORT enInputPortType, MS_U8 ubOffset);
INTERFACE void Hal_HDCP_SetReady(E_MUX_INPUTPORT enInputPortType, MS_BOOL bIsReady);
INTERFACE void Hal_HDCP_WriteKSVList(E_MUX_INPUTPORT enInputPortType, MS_U8* pucData, MS_U32 dwDataLen);
INTERFACE void Hal_HDCP_ClearStatus(E_MUX_INPUTPORT enInputPortType, MS_U16 usInt);
INTERFACE void Hal_HDCP_WriteDoneInterruptEnable(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnableIRQ);
INTERFACE E_HDMI_PIPELINE_MODE Hal_HDMI_GetPipeLineMode(void);
/*************************** HDCP 14 ***************************/
INTERFACE void Hal_HDCP_ReadR0InterruptEnable(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnableIRQ);
/******************************* EARC *******************************/
INTERFACE void Hal_EARC_TX_InitialSetting(void);
INTERFACE void Hal_EARC_TX_SetLatencyInfo(stHDMI_EARCTX_COMMON_MODE_POLLING_INFO *stCommonModePollingInfo, MS_U8 u8LatencyValue);
INTERFACE MS_BOOL Hal_EARC_TX_SetATOPSetting_AUPLL(MS_U8 u8AUPLLModeSelect, EN_EARC_AUDIO_FREQUENCY_TYPE enAudioFrequency, EN_EARC_AUDIO_CHANNEL_LAYOUT_TYPE enAudioChannelLayout);
INTERFACE void Hal_EARC_TX_SetAudioOutputStream(MS_BOOL bEnableFlag);
INTERFACE MS_BOOL Hal_EARC_TX_SetSupportMode(EN_EARC_SUPPORT_MODE enSupportMode);
INTERFACE MS_U8 Hal_EARC_TX_GetChipCapability(void);
INTERFACE void Hal_EARC_TX_OutputPortSelect(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnable5VDetectInvert, MS_BOOL bEnableHPDInvert);
INTERFACE void Hal_EARC_TX_PollingHandler(HDMI_EARCTX_RESOURCE_PRIVATE *pHDMIEARCTxResourcePrivate);
/******************************* EARC *******************************/
INTERFACE void Hal_HDMI_SCDCIsr(E_MUX_INPUTPORT enInputPortType, stHDMI_POLLING_INFO *pstHDMIPollingInfo);
INTERFACE MS_BOOL Hal_HDMI_GetCRCValue(E_MUX_INPUTPORT enInputPortType, MS_DVI_CHANNEL_TYPE u8Channel, MS_U16* pu16CRCVal, stHDMI_POLLING_INFO* pstHDMIPollingInfo);
MS_U16 Hal_HDCP_Read22HwControl(E_MUX_INPUTPORT enInputPortType);
MS_U32 Hal_HDMI_Get_HW_Ability(E_MUX_INPUTPORT enInputPortType, E_HDMI_GET_WHICH_HW_ABILITY enWhichAbility);
INTERFACE MS_BOOL Hal_HDMI_GetPHYDone(E_MUX_INPUTPORT enInputPortType, stHDMI_POLLING_INFO *pstHDMIPollingInfo);

#undef INTERFACE
#endif /* MHAL_HDMI_H */

