
#ifndef _MODA1_H
#define _MODA1_H

#include "hwreg_common.h"

#define moda1 0x00484600

//Page MODA1_1
#define REG_0000_MODA1 (moda1 + 0x000)
    #define REG_0000_MODA1_REG_EN_CLK_BANK Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0000_MODA1_REG_GCR_EN_SKEW Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0000_MODA1_REG_EN_MINI_SKEW Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0000_MODA1_REG_GCR_EN_CML Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0000_MODA1_REG_GCR_VCM_SEL Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0004_MODA1 (moda1 + 0x004)
    #define REG_0004_MODA1_REG_GCR_EN_REG Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_0004_MODA1_REG_PD_MOD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0008_MODA1 (moda1 + 0x008)
    #define REG_0008_MODA1_REG_GCR_DS_POL_CH_19_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_MODA1 (moda1 + 0x00C)
    #define REG_000C_MODA1_REG_GCR_DS_POL_CH_19_00_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0010_MODA1 (moda1 + 0x010)
    #define REG_0010_MODA1_REG_GCR_PE_EN_CH_19_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0014_MODA1 (moda1 + 0x014)
    #define REG_0014_MODA1_REG_GCR_PE_EN_CH_19_00_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0018_MODA1 (moda1 + 0x018)
    #define REG_0018_MODA1_REG_GCR_EN_RINT_CH_19_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_001C_MODA1 (moda1 + 0x01C)
    #define REG_001C_MODA1_REG_GCR_EN_RINT_CH_19_00_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0020_MODA1 (moda1 + 0x020)
    #define REG_0020_MODA1_REG_GCR_EN_VBY1_CH_19_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_MODA1 (moda1 + 0x024)
    #define REG_0024_MODA1_REG_GCR_EN_VBY1_CH_19_00_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0028_MODA1 (moda1 + 0x028)
    #define REG_0028_MODA1_REG_GCR_TTL_LPM_EN_CH_19_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_MODA1 (moda1 + 0x02C)
    #define REG_002C_MODA1_REG_GCR_TTL_LPM_EN_CH_19_00_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0030_MODA1 (moda1 + 0x030)
    #define REG_0030_MODA1_REG_GCR_EN_XSWING_CH_19_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_MODA1 (moda1 + 0x034)
    #define REG_0034_MODA1_REG_GCR_EN_XSWING_CH_19_00_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0038_MODA1 (moda1 + 0x038)
    #define REG_0038_MODA1_REG_GCR_BANK_CLK_SRC_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define REG_003C_MODA1 (moda1 + 0x03C)
    #define REG_003C_MODA1_REG_TEST_MOD Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_MODA1 (moda1 + 0x040)
    #define REG_0040_MODA1_REG_CK1X_ANA_PHSEL_PATH2 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0040_MODA1_REG_CK1X_DIG_PHSEL_PATH2 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0040_MODA1_REG_CK1X_ANA_PHSEL Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0040_MODA1_REG_CK1X_DIG_PHSEL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0044_MODA1 (moda1 + 0x044)
    #define REG_0044_MODA1_REG_GCR_SEL_REF18 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_0044_MODA1_REG_GCR_IMODE_SPEED_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0044_MODA1_REG_GCR_EN_VBY1_DIFF Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0044_MODA1_REG_GCR_EN_PULL_L Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0044_MODA1_REG_GCR_BIAS_CON Fld(7,0,AC_MSKB0)//[6:0]
#define REG_0048_MODA1 (moda1 + 0x048)
    #define REG_0048_MODA1_REG_GCR_CKEN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0048_MODA1_REG_GCR_CKEN_PATH2 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_004C_MODA1 (moda1 + 0x04C)
    #define REG_004C_MODA1_REG_GCR_REG_LEVEL_GP1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_004C_MODA1_REG_GCR_REG_LEVEL_GP2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_004C_MODA1_REG_GCR_REG_LEVEL_GP3 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_004C_MODA1_REG_GCR_REG_LEVEL_GP4 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0050_MODA1 (moda1 + 0x050)
    #define REG_0050_MODA1_REG_GCR_REG_LEVEL_GP5 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0050_MODA1_REG_GCR_REG_LEVEL_GP6 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0050_MODA1_REG_GCR_REG_LEVEL_GP7 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0050_MODA1_REG_GCR_REG_LEVEL_GP8 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0060_MODA1 (moda1 + 0x060)
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH00 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH01 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH02 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH03 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH04 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH05 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH06 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0060_MODA1_REG_OUTPUT_CONF_CH07 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0064_MODA1 (moda1 + 0x064)
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH08 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH09 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH10 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH11 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH12 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH13 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH14 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0064_MODA1_REG_OUTPUT_CONF_CH15 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0068_MODA1 (moda1 + 0x068)
    #define REG_0068_MODA1_REG_OUTPUT_CONF_CH16 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0068_MODA1_REG_OUTPUT_CONF_CH17 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0068_MODA1_REG_OUTPUT_CONF_CH18 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0068_MODA1_REG_OUTPUT_CONF_CH19 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0070_MODA1 (moda1 + 0x070)
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH00 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH01 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH02 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH03 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH04 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH05 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH06 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0070_MODA1_REG_FTUNE_SKEW_CH07 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0074_MODA1 (moda1 + 0x074)
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH08 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH09 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH10 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH11 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH12 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH13 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH14 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0074_MODA1_REG_FTUNE_SKEW_CH15 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0078_MODA1 (moda1 + 0x078)
    #define REG_0078_MODA1_REG_FTUNE_SKEW_CH16 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0078_MODA1_REG_FTUNE_SKEW_CH17 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0078_MODA1_REG_FTUNE_SKEW_CH18 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0078_MODA1_REG_FTUNE_SKEW_CH19 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0080_MODA1 (moda1 + 0x080)
    #define REG_0080_MODA1_REG_GCR_PE_ADJ_CH00 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0080_MODA1_REG_GCR_PE_ADJ_CH01 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0084_MODA1 (moda1 + 0x084)
    #define REG_0084_MODA1_REG_GCR_PE_ADJ_CH02 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0084_MODA1_REG_GCR_PE_ADJ_CH03 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0088_MODA1 (moda1 + 0x088)
    #define REG_0088_MODA1_REG_GCR_PE_ADJ_CH04 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0088_MODA1_REG_GCR_PE_ADJ_CH05 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_008C_MODA1 (moda1 + 0x08C)
    #define REG_008C_MODA1_REG_GCR_PE_ADJ_CH06 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_008C_MODA1_REG_GCR_PE_ADJ_CH07 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0090_MODA1 (moda1 + 0x090)
    #define REG_0090_MODA1_REG_GCR_PE_ADJ_CH08 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0090_MODA1_REG_GCR_PE_ADJ_CH09 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0094_MODA1 (moda1 + 0x094)
    #define REG_0094_MODA1_REG_GCR_PE_ADJ_CH10 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0094_MODA1_REG_GCR_PE_ADJ_CH11 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_0098_MODA1 (moda1 + 0x098)
    #define REG_0098_MODA1_REG_GCR_PE_ADJ_CH12 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0098_MODA1_REG_GCR_PE_ADJ_CH13 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_009C_MODA1 (moda1 + 0x09C)
    #define REG_009C_MODA1_REG_GCR_PE_ADJ_CH14 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_009C_MODA1_REG_GCR_PE_ADJ_CH15 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A0_MODA1 (moda1 + 0x0A0)
    #define REG_00A0_MODA1_REG_GCR_PE_ADJ_CH16 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00A0_MODA1_REG_GCR_PE_ADJ_CH17 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A4_MODA1 (moda1 + 0x0A4)
    #define REG_00A4_MODA1_REG_GCR_PE_ADJ_CH18 Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_00A4_MODA1_REG_GCR_PE_ADJ_CH19 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_00A8_MODA1 (moda1 + 0x0A8)
    #define REG_00A8_MODA1_REG_SKEW_CH_STATUS Fld(6,0,AC_MSKB0)//[5:0]
#define REG_00AC_MODA1 (moda1 + 0x0AC)
    #define REG_00AC_MODA1_REG_SKEW_WR_VALUE Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00AC_MODA1_REG_SKEW_CH_SEL Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_00AC_MODA1_REG_SKEW_WR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00AC_MODA1_REG_SKEW_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00B0_MODA1 (moda1 + 0x0B0)
    #define REG_00B0_MODA1_REG_GCR_ICON_CH00 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B0_MODA1_REG_GCR_ICON_CH01 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B4_MODA1 (moda1 + 0x0B4)
    #define REG_00B4_MODA1_REG_GCR_ICON_CH02 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B4_MODA1_REG_GCR_ICON_CH03 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00B8_MODA1 (moda1 + 0x0B8)
    #define REG_00B8_MODA1_REG_GCR_ICON_CH04 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00B8_MODA1_REG_GCR_ICON_CH05 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00BC_MODA1 (moda1 + 0x0BC)
    #define REG_00BC_MODA1_REG_GCR_ICON_CH06 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00BC_MODA1_REG_GCR_ICON_CH07 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C0_MODA1 (moda1 + 0x0C0)
    #define REG_00C0_MODA1_REG_GCR_ICON_CH08 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C0_MODA1_REG_GCR_ICON_CH09 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_MODA1 (moda1 + 0x0C4)
    #define REG_00C4_MODA1_REG_GCR_ICON_CH10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C4_MODA1_REG_GCR_ICON_CH11 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C8_MODA1 (moda1 + 0x0C8)
    #define REG_00C8_MODA1_REG_GCR_ICON_CH12 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C8_MODA1_REG_GCR_ICON_CH13 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_MODA1 (moda1 + 0x0CC)
    #define REG_00CC_MODA1_REG_GCR_ICON_CH14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00CC_MODA1_REG_GCR_ICON_CH15 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D0_MODA1 (moda1 + 0x0D0)
    #define REG_00D0_MODA1_REG_GCR_ICON_CH16 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D0_MODA1_REG_GCR_ICON_CH17 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D4_MODA1 (moda1 + 0x0D4)
    #define REG_00D4_MODA1_REG_GCR_ICON_CH18 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00D4_MODA1_REG_GCR_ICON_CH19 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00E0_MODA1 (moda1 + 0x0E0)
    #define REG_00E0_MODA1_REG_GCR_RCON_CH00 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E0_MODA1_REG_GCR_RCON_CH01 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00E4_MODA1 (moda1 + 0x0E4)
    #define REG_00E4_MODA1_REG_GCR_RCON_CH02 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E4_MODA1_REG_GCR_RCON_CH03 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00E8_MODA1 (moda1 + 0x0E8)
    #define REG_00E8_MODA1_REG_GCR_RCON_CH04 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00E8_MODA1_REG_GCR_RCON_CH05 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00EC_MODA1 (moda1 + 0x0EC)
    #define REG_00EC_MODA1_REG_GCR_RCON_CH06 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00EC_MODA1_REG_GCR_RCON_CH07 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F0_MODA1 (moda1 + 0x0F0)
    #define REG_00F0_MODA1_REG_GCR_RCON_CH08 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F0_MODA1_REG_GCR_RCON_CH09 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F4_MODA1 (moda1 + 0x0F4)
    #define REG_00F4_MODA1_REG_GCR_RCON_CH10 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F4_MODA1_REG_GCR_RCON_CH11 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00F8_MODA1 (moda1 + 0x0F8)
    #define REG_00F8_MODA1_REG_GCR_RCON_CH12 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00F8_MODA1_REG_GCR_RCON_CH13 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_00FC_MODA1 (moda1 + 0x0FC)
    #define REG_00FC_MODA1_REG_GCR_RCON_CH14 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_00FC_MODA1_REG_GCR_RCON_CH15 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0100_MODA1 (moda1 + 0x100)
    #define REG_0100_MODA1_REG_GCR_RCON_CH16 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0100_MODA1_REG_GCR_RCON_CH17 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0104_MODA1 (moda1 + 0x104)
    #define REG_0104_MODA1_REG_GCR_RCON_CH18 Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0104_MODA1_REG_GCR_RCON_CH19 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0110_MODA1 (moda1 + 0x110)
    #define REG_0110_MODA1_REG_RINT_SEL_CH00 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0110_MODA1_REG_RINT_SEL_CH01 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0110_MODA1_REG_RINT_SEL_CH02 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0110_MODA1_REG_RINT_SEL_CH03 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0114_MODA1 (moda1 + 0x114)
    #define REG_0114_MODA1_REG_RINT_SEL_CH04 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0114_MODA1_REG_RINT_SEL_CH05 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0114_MODA1_REG_RINT_SEL_CH06 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0114_MODA1_REG_RINT_SEL_CH07 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0118_MODA1 (moda1 + 0x118)
    #define REG_0118_MODA1_REG_RINT_SEL_CH08 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0118_MODA1_REG_RINT_SEL_CH09 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0118_MODA1_REG_RINT_SEL_CH10 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0118_MODA1_REG_RINT_SEL_CH11 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_011C_MODA1 (moda1 + 0x11C)
    #define REG_011C_MODA1_REG_RINT_SEL_CH12 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_011C_MODA1_REG_RINT_SEL_CH13 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_011C_MODA1_REG_RINT_SEL_CH14 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_011C_MODA1_REG_RINT_SEL_CH15 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0120_MODA1 (moda1 + 0x120)
    #define REG_0120_MODA1_REG_RINT_SEL_CH16 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0120_MODA1_REG_RINT_SEL_CH17 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0120_MODA1_REG_RINT_SEL_CH18 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0120_MODA1_REG_RINT_SEL_CH19 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0124_MODA1 (moda1 + 0x124)
    #define REG_0124_MODA1_REG_GCR_TEST_PRE_LDO_CH00 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0124_MODA1_REG_GCR_TEST_PRE_LDO_CH01 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0124_MODA1_REG_GCR_TEST_PRE_LDO_CH02 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0124_MODA1_REG_GCR_TEST_PRE_LDO_CH03 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0128_MODA1 (moda1 + 0x128)
    #define REG_0128_MODA1_REG_GCR_TEST_PRE_LDO_CH04 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0128_MODA1_REG_GCR_TEST_PRE_LDO_CH05 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0128_MODA1_REG_GCR_TEST_PRE_LDO_CH06 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0128_MODA1_REG_GCR_TEST_PRE_LDO_CH07 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_012C_MODA1 (moda1 + 0x12C)
    #define REG_012C_MODA1_REG_GCR_TEST_PRE_LDO_CH08 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_012C_MODA1_REG_GCR_TEST_PRE_LDO_CH09 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_012C_MODA1_REG_GCR_TEST_PRE_LDO_CH10 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_012C_MODA1_REG_GCR_TEST_PRE_LDO_CH11 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0130_MODA1 (moda1 + 0x130)
    #define REG_0130_MODA1_REG_GCR_TEST_PRE_LDO_CH12 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0130_MODA1_REG_GCR_TEST_PRE_LDO_CH13 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0130_MODA1_REG_GCR_TEST_PRE_LDO_CH14 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0130_MODA1_REG_GCR_TEST_PRE_LDO_CH15 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0134_MODA1 (moda1 + 0x134)
    #define REG_0134_MODA1_REG_GCR_TEST_PRE_LDO_CH16 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0134_MODA1_REG_GCR_TEST_PRE_LDO_CH17 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0134_MODA1_REG_GCR_TEST_PRE_LDO_CH18 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0134_MODA1_REG_GCR_TEST_PRE_LDO_CH19 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0138_MODA1 (moda1 + 0x138)
    #define REG_0138_MODA1_REG_MOD_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_013C_MODA1 (moda1 + 0x13C)
    #define REG_013C_MODA1_REG_MOD_DUMMY2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0140_MODA1 (moda1 + 0x140)
    #define REG_0140_MODA1_REG_GCR_VBY1_VREG_CH00 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0140_MODA1_REG_GCR_VBY1_VREG_CH01 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0140_MODA1_REG_GCR_VBY1_VREG_CH02 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0140_MODA1_REG_GCR_VBY1_VREG_CH03 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0144_MODA1 (moda1 + 0x144)
    #define REG_0144_MODA1_REG_GCR_VBY1_VREG_CH04 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0144_MODA1_REG_GCR_VBY1_VREG_CH05 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0144_MODA1_REG_GCR_VBY1_VREG_CH06 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0144_MODA1_REG_GCR_VBY1_VREG_CH07 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0148_MODA1 (moda1 + 0x148)
    #define REG_0148_MODA1_REG_GCR_VBY1_VREG_CH08 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0148_MODA1_REG_GCR_VBY1_VREG_CH09 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0148_MODA1_REG_GCR_VBY1_VREG_CH10 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0148_MODA1_REG_GCR_VBY1_VREG_CH11 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_014C_MODA1 (moda1 + 0x14C)
    #define REG_014C_MODA1_REG_GCR_VBY1_VREG_CH12 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_014C_MODA1_REG_GCR_VBY1_VREG_CH13 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_014C_MODA1_REG_GCR_VBY1_VREG_CH14 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_014C_MODA1_REG_GCR_VBY1_VREG_CH15 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0150_MODA1 (moda1 + 0x150)
    #define REG_0150_MODA1_REG_GCR_VBY1_VREG_CH16 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0150_MODA1_REG_GCR_VBY1_VREG_CH17 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0150_MODA1_REG_GCR_VBY1_VREG_CH18 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0150_MODA1_REG_GCR_VBY1_VREG_CH19 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0154_MODA1 (moda1 + 0x154)
    #define REG_0154_MODA1_REG_DRV_MODE_CH00 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0154_MODA1_REG_DRV_MODE_CH01 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0154_MODA1_REG_DRV_MODE_CH02 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0154_MODA1_REG_DRV_MODE_CH03 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0154_MODA1_REG_DRV_MODE_CH04 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0154_MODA1_REG_DRV_MODE_CH05 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0154_MODA1_REG_DRV_MODE_CH06 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0154_MODA1_REG_DRV_MODE_CH07 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0158_MODA1 (moda1 + 0x158)
    #define REG_0158_MODA1_REG_DRV_MODE_CH08 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0158_MODA1_REG_DRV_MODE_CH09 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_0158_MODA1_REG_DRV_MODE_CH10 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0158_MODA1_REG_DRV_MODE_CH11 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_0158_MODA1_REG_DRV_MODE_CH12 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0158_MODA1_REG_DRV_MODE_CH13 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0158_MODA1_REG_DRV_MODE_CH14 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_0158_MODA1_REG_DRV_MODE_CH15 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_015C_MODA1 (moda1 + 0x15C)
    #define REG_015C_MODA1_REG_DRV_MODE_CH16 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_015C_MODA1_REG_DRV_MODE_CH17 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_015C_MODA1_REG_DRV_MODE_CH18 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_015C_MODA1_REG_DRV_MODE_CH19 Fld(2,6,AC_MSKB0)//[7:6]
#define REG_0160_MODA1 (moda1 + 0x160)
    #define REG_0160_MODA1_REG_HW_RINT_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0160_MODA1_REG_HW_RINT_TH Fld(15,0,AC_MSKW10)//[14:0]
#define REG_0164_MODA1 (moda1 + 0x164)
    #define REG_0164_MODA1_REG_HW_RINT_CNT_VALUE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0168_MODA1 (moda1 + 0x168)
    #define REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH00 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH01 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH02 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0168_MODA1_REG_BIAS_CON_OFFSET_CH03 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_016C_MODA1 (moda1 + 0x16C)
    #define REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH04 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH05 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH06 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_016C_MODA1_REG_BIAS_CON_OFFSET_CH07 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0170_MODA1 (moda1 + 0x170)
    #define REG_0170_MODA1_REG_SKEW_CH_STATUS Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH08_V2 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH09_V2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH10_V2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0170_MODA1_REG_BIAS_CON_OFFSET_CH11_V2 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0174_MODA1 (moda1 + 0x174)
    #define REG_0174_MODA1_REG_SKEW_WR_VALUE Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0174_MODA1_REG_SKEW_CH_SEL Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_0174_MODA1_REG_SKEW_WR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0174_MODA1_REG_SKEW_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH12_V2 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH13_V2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH14_V2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0174_MODA1_REG_BIAS_CON_OFFSET_CH15_V2 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0178_MODA1 (moda1 + 0x178)
    #define REG_0178_MODA1_REG_MOD_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]
    #define REG_0178_MODA1_REG_BIAS_CON_OFFSET_CH16_V2 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0178_MODA1_REG_BIAS_CON_OFFSET_CH17_V2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0178_MODA1_REG_BIAS_CON_OFFSET_CH18_V2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_0178_MODA1_REG_BIAS_CON_OFFSET_CH19_V2 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_017C_MODA1 (moda1 + 0x17C)
    #define REG_017C_MODA1_REG_MOD_DUMMY2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0180_MODA1 (moda1 + 0x180)
    #define REG_0180_MODA1_REG_GPO_OEZ_39_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0184_MODA1 (moda1 + 0x184)
    #define REG_0184_MODA1_REG_GPO_OEZ_39_00_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_MODA1 (moda1 + 0x188)
    #define REG_0188_MODA1_REG_GPO_OEZ_39_00_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_018C_MODA1 (moda1 + 0x18C)
    #define REG_018C_MODA1_REG_GPO_DATA_39_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_MODA1 (moda1 + 0x190)
    #define REG_0190_MODA1_REG_GPO_DATA_39_00_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_MODA1 (moda1 + 0x194)
    #define REG_0194_MODA1_REG_GPO_DATA_39_00_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0198_MODA1 (moda1 + 0x198)
    #define REG_0198_MODA1_REG_GPI_DATA_39_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_019C_MODA1 (moda1 + 0x19C)
    #define REG_019C_MODA1_REG_GPI_DATA_39_00_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_MODA1 (moda1 + 0x1A0)
    #define REG_01A0_MODA1_REG_GPI_DATA_39_00_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01A4_MODA1 (moda1 + 0x1A4)
    #define REG_01A4_MODA1_REG_EXT_EN_39_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A8_MODA1 (moda1 + 0x1A8)
    #define REG_01A8_MODA1_REG_EXT_EN_39_00_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01AC_MODA1 (moda1 + 0x1AC)
    #define REG_01AC_MODA1_REG_EXT_EN_39_00_2 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01B0_MODA1 (moda1 + 0x1B0)
    #define REG_01B0_MODA1_REG_TTL_EN_39_00_0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B4_MODA1 (moda1 + 0x1B4)
    #define REG_01B4_MODA1_REG_TTL_EN_39_00_1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01B8_MODA1 (moda1 + 0x1B8)
    #define REG_01B8_MODA1_REG_TTL_EN_39_00_2 Fld(8,0,AC_FULLB0)//[7:0]

//Page MODA1_2
#define REG_01C0_MODA1 (moda1 + 0x1C0)
    #define REG_01C0_MODA1_REG_V1_PRBS_DET_CH_SEL Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01C0_MODA1_REG_V2_PRBS_DET_CH_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_01C0_MODA1_REG_OSD_PRBS_DET_CH_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01C0_MODA1_REG_V1_TEST_PRBS_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01C0_MODA1_REG_V2_TEST_PRBS_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01C0_MODA1_REG_OSD_TEST_PRBS_EN Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01C4_MODA1 (moda1 + 0x1C4)
    #define REG_01C4_MODA1_REG_V1_PRBS_BIT_ERROR_CNT Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01C4_MODA1_REG_V1_PRBS_BIT_ERROR_CNT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01C4_MODA1_REG_V1_PRBS_COMPARE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01C8_MODA1 (moda1 + 0x1C8)
    #define REG_01C8_MODA1_REG_V2_PRBS_BIT_ERROR_CNT Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01C8_MODA1_REG_V2_PRBS_BIT_ERROR_CNT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01C8_MODA1_REG_V2_PRBS_COMPARE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01CC_MODA1 (moda1 + 0x1CC)
    #define REG_01CC_MODA1_REG_OSD_PRBS_BIT_ERROR_CNT Fld(14,0,AC_MSKW10)//[13:0]
    #define REG_01CC_MODA1_REG_OSD_PRBS_BIT_ERROR_CNT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01CC_MODA1_REG_OSD_PRBS_COMPARE_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01D0_MODA1 (moda1 + 0x1D0)
    #define REG_01D0_MODA1_REG_CLKDLYSEL Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_01D0_MODA1_REG_ECLKDLYSEL Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01D0_MODA1_REG_TTL_CLK_INV Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_01D0_MODA1_REG_SKEW Fld(6,0,AC_MSKB0)//[5:0]
#define REG_01D4_MODA1 (moda1 + 0x1D4)
    #define REG_01D4_MODA1_REG_TCON_SWAP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01D4_MODA1_REG_GPO_EN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01D8_MODA1 (moda1 + 0x1D8)
    #define REG_01D8_MODA1_REG_CKG_MOD_SR_RCLK_OSD Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01D8_MODA1_REG_CKG_MOD_SR_RCLK_V2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_01D8_MODA1_REG_CKG_MOD_SR_RCLK_V1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_01DC_MODA1 (moda1 + 0x1DC)
    #define REG_01DC_MODA1_REG_VBY1_LOCKN_HTPDN_SEL_OSD Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_01DC_MODA1_REG_VBY1_LOCKN_HTPDN_SEL_V2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_01DC_MODA1_REG_VBY1_LOCKN_HTPDN_SEL_V1 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_01DC_MODA1_REG_VBY1_LOCKN_HPTDN_SWAP_OSD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01DC_MODA1_REG_VBY1_LOCKN_HPTDN_SWAP_V2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01DC_MODA1_REG_VBY1_LOCKN_HPTDN_SWAP_V1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01DC_MODA1_REG_SW_RSTZ Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01E0_MODA1 (moda1 + 0x1E0)
    #define REG_01E0_MODA1_REG_GCR_CAL_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01E0_MODA1_REG_C_CAL_OUT Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01E0_MODA1_REG_GCR_CAL_SRC Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_01E0_MODA1_REG_GCR_CAL_LEVEL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_01E4_MODA1 (moda1 + 0x1E4)
    #define REG_01E4_MODA1_REG_HW_CAL_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01E4_MODA1_REG_CAL_FINISH Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01E4_MODA1_REG_CAL_FAIL Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01E4_MODA1_REG_ICON_RESULT Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01E8_MODA1 (moda1 + 0x1E8)
    #define REG_01E8_MODA1_REG_KEEP_CAL_VALUE Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_01E8_MODA1_REG_5US_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_01E8_MODA1_REG_CAL_TOG_TIME Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01E8_MODA1_REG_NEW_HW_CAL_PATH Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01E8_MODA1_REG_HW_CAL_ON Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01E8_MODA1_REG_BIAS_CON_HW_CAL_ON Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01E8_MODA1_REG_KEEP_BIAS_CON_CAL_VALUE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01EC_MODA1 (moda1 + 0x1EC)
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_00 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_01 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_02 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_03 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_04 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_05 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_06 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01EC_MODA1_REG_TEST_DATA_SEL_07 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F0_MODA1 (moda1 + 0x1F0)
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_08 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_09 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_10 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_11 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_12 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_13 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_14 Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01F0_MODA1_REG_TEST_DATA_SEL_15 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F4_MODA1 (moda1 + 0x1F4)
    #define REG_01F4_MODA1_REG_TEST_DATA_SEL_16 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_01F4_MODA1_REG_TEST_DATA_SEL_17 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_01F4_MODA1_REG_TEST_DATA_SEL_18 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F4_MODA1_REG_TEST_DATA_SEL_19 Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_01F4_MODA1_REG_DATA_INV_BY_CLK Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01F4_MODA1_REG_TEST_PRBS_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01F4_MODA1_REG_TEST_PRBS_PAT_EN Fld(1,10,AC_MSKB1)//[10:10]
#define REG_01F8_MODA1 (moda1 + 0x1F8)
    #define REG_01F8_MODA1_REG_FORCE_DATA1_15_00 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_MODA1 (moda1 + 0x1FC)
    #define REG_01FC_MODA1_REG_FORCE_DATA2_15_00 Fld(16,0,AC_FULLW10)//[15:0]

#endif
