#ifndef _SCTCON_BKA4F7_V004_H
#define _SCTCON_BKA4F7_V004_H
#define SCTCON_BKA4F7_V004 0x149EE00

//Page SCTCON_BKA4F7_V004
#define REG_0008_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x008)
	#define REG_0008_SCTCON_BKA4F7_V004_REG_TEST_CTRL_0_0008 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_000C_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x00C)
	#define REG_000C_SCTCON_BKA4F7_V004_REG_TEST_CTRL_1_000C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0080_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x080)
	#define REG_0080_SCTCON_BKA4F7_V004_REG_SCTCON_ALL_AUTO_CLK_EN_0080 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_00A0_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0A0)
	#define REG_00A0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_0_00A0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0A4)
	#define REG_00A4_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_1_00A4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A8_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0A8)
	#define REG_00A8_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_2_00A8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00AC_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0AC)
	#define REG_00AC_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_3_00AC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B0_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0B0)
	#define REG_00B0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_4_00B0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B4_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0B4)
	#define REG_00B4_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_5_00B4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B8_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0B8)
	#define REG_00B8_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_6_00B8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0BC)
	#define REG_00BC_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_EN_7_00BC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C0_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0C0)
	#define REG_00C0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_0_00C0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0C4)
	#define REG_00C4_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_1_00C4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0C8)
	#define REG_00C8_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_2_00C8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0CC)
	#define REG_00CC_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_3_00CC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0D0)
	#define REG_00D0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_4_00D0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0D4)
	#define REG_00D4_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_5_00D4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0D8)
	#define REG_00D8_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_6_00D8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0DC)
	#define REG_00DC_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_SW_MD_EN_7_00DC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0E0)
	#define REG_00E0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_0_00E0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0E4)
	#define REG_00E4_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_1_00E4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0E8)
	#define REG_00E8_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_2_00E8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0EC)
	#define REG_00EC_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_3_00EC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0F0)
	#define REG_00F0_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_4_00F0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0F4)
	#define REG_00F4_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_5_00F4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0F8)
	#define REG_00F8_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_6_00F8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00FC_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x0FC)
	#define REG_00FC_SCTCON_BKA4F7_V004_REG_SCTCON_AUTO_CLK_DB_EN_7_00FC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x100)
	#define REG_0100_SCTCON_BKA4F7_V004_REG_SC2MOD_V1_VS_SEL_0100 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0100_SCTCON_BKA4F7_V004_REG_SC2MOD_V1_VFDE_SEL_0100 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0100_SCTCON_BKA4F7_V004_REG_SC2MOD_V1_HFDE_SEL_0100 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0100_SCTCON_BKA4F7_V004_REG_SC2MOD_V2_VS_SEL_0100 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0100_SCTCON_BKA4F7_V004_REG_SC2MOD_V2_VFDE_SEL_0100 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0100_SCTCON_BKA4F7_V004_REG_SC2MOD_V2_HFDE_SEL_0100 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_0180_SCTCON_BKA4F7_V004 (SCTCON_BKA4F7_V004 + 0x180)
	#define REG_0180_SCTCON_BKA4F7_V004_REG_LINEOD_PCLRC_PATH_SEL_0180 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0180_SCTCON_BKA4F7_V004_REG_DMC_OD_PGA_PATH_SEL_0180 Fld(3,12,AC_MSKB1)//[14:12]
#endif