/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * MediaTek Inc. (C) 2018. All rights reserved.
 *
 * Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein is
 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
 * the prior written permission of MediaTek inc. and/or its licensors, any
 * reproduction, modification, use or disclosure of MediaTek Software, and
 * information contained herein, in whole or in part, shall be strictly
 * prohibited.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 *
 * The following software/firmware and/or related documentation ("MediaTek
 * Software") have been modified by MediaTek Inc. All revisions are subject to
 * any receiver's applicable license agreements with MediaTek Inc.
 */

#ifndef _MTK_DTV_PWM_H_
#define _MTK_DTV_PWM_H_

////////////////////////////////////////////////////////////////////////////////
// Header Files
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// Define & and data type
////////////////////////////////////////////////////////////////////////////////

//############################
//
//IP bank address : for pad mux in chiptop
//
//############################
#define GPIO_FUNC_MUX_REG_BASE          (0x1F000000 + (0x322900 << 1))

//for pwm 0
#define CHIP_REG_PWM0                   (GPIO_FUNC_MUX_REG_BASE + 0x48 * 4)
#define CHIP_PWM0_PAD_0                 0
#define CHIP_PWM0_PAD_1                 BIT(0)	//PAD_PWM0
#define CHIP_PWM0_PAD_MSK               BIT(0)

//for pwm 1
#define CHIP_REG_PWM1                   (GPIO_FUNC_MUX_REG_BASE + 0x48 * 4)
#define CHIP_PWM1_PAD_0                 (0)
#define CHIP_PWM1_PAD_1                 BIT(4)	//PAD_PWM1
#define CHIP_PWM1_PAD_MSK               BIT(4)

//for pmw 2
#define CHIP_REG_PWM2                   (GPIO_FUNC_MUX_REG_BASE + 0x48 * 4 + 1)
#define CHIP_PWM2_PAD_0                 (0)
#define CHIP_PWM2_PAD_1                 BIT(0)	//PAD_PWM2
#define CHIP_PWM2_PAD_2                 BIT(1)	//PAD_TCON4
#define CHIP_PWM2_PAD_MSK               (BIT(0) | BIT(1))

//for pwm 3
#define CHIP_REG_PWM3                   (GPIO_FUNC_MUX_REG_BASE + 0x48 * 4 + 1)
#define CHIP_PWM3_PAD_0                 (0)
#define CHIP_PWM3_PAD_1                 BIT(4)	//PAD_PWM3
#define CHIP_PWM3_PAD_2                 BIT(5)	//PAD_GPIO0
#define CHIP_PWM3_PAD_MSK               (BIT(4) | BIT(5))

// for all pwms oen
#define CHIP_REG_PWM_OEN                (GPIO_FUNC_MUX_REG_BASE + 0x68 * 4)
#define CHIP_PWMS_OEN_MSK               (BIT(4) | BIT(5) | BIT(6) | BIT(7))

//############################
//
//PWM control registers
//
//############################
#define REG_PWM_CLKEN_BITMAP        (0x01)
#define PWM0_CLK_EN_MASK            BIT(0)
#define PWM1_CLK_EN_MASK            BIT(1)
#define PWM2_CLK_EN_MASK            BIT(2)
#define PWM3_CLK_EN_MASK            BIT(3)
#define PWM4_CLK_EN_MASK            BIT(4)
#define PWM5_CLK_EN_MASK            BIT(5)
#define PWMFULL_IP_ENGINE_EN_MASK   BIT(6)

#define REG_PWM0_PERIOD             (0x02)	//bit0~15
#define REG_PWM1_PERIOD             (0x05)	//bit0~15
#define REG_PWM2_PERIOD             (0x08)	//bit0~15
#define REG_PWM3_PERIOD             (0x0B)	//bit0~15
#define REG_PWM4_PERIOD             (0x0E)	//bit0~15
#define REG_PWM5_PERIOD             (0x11)	//bit0~15
//#define REG_PWM6_PERIOD             (0x40)  //bit0~15
//#define REG_PWM7_PERIOD             (0x43)  //bit0~15
//#define REG_PWM8_PERIOD             (0x46)  //bit0~15

#define REG_PWM0_DUTY               (0x03)	//bit0~15
#define REG_PWM1_DUTY               (0x06)	//bit0~15
#define REG_PWM2_DUTY               (0x09)	//bit0~15
#define REG_PWM3_DUTY               (0x0C)	//bit0~15
#define REG_PWM4_DUTY               (0x0F)	//bit0~15
#define REG_PWM5_DUTY               (0x12)	//bit0~15
//#define REG_PWM6_DUTY               (0x41)  //bit0~15
//#define REG_PWM7_DUTY               (0x44)  //bit0~15
//#define REG_PWM8_DUTY               (0x47)  //bit0~15

#define REG_PWM0_DIV                (0x04)	//bit0~7
#define REG_PWM1_DIV                (0x07)	//bit0~7
#define REG_PWM2_DIV                (0x0A)	//bit0~7
#define REG_PWM3_DIV                (0x0D)	//bit0~7
#define REG_PWM4_DIV                (0x10)	//bit0~7
#define REG_PWM5_DIV                (0x13)	//bit0~7
//#define REG_PWM6_DIV                (0x42)  //bit0~7
//#define REG_PWM7_DIV                (0x45)  //bit0~7
//#define REG_PWM8_DIV                (0x48)  //bit0~7
#define REG_PWM_DIV_MASK            (0xFF)

#define REG_PWM0_PORARITY           (0x04)	//bit8
#define REG_PWM1_PORARITY           (0x07)	//bit8
#define REG_PWM2_PORARITY           (0x0A)	//bit8
#define REG_PWM3_PORARITY           (0x0D)	//bit8
#define REG_PWM4_PORARITY           (0x10)	//bit8
#define REG_PWM5_PORARITY           (0x13)	//bit8
//#define REG_PWM6_PORARITY           (0x42)  //bit8
//#define REG_PWM7_PORARITY           (0x45)  //bit8
//#define REG_PWM8_PORARITY           (0x48)  //bit8
#define REG_PWM_POLARITY_MASK       BIT(8)

#define REG_PWM0_VDBEN              (0x04)	//bit9
#define REG_PWM1_VDBEN              (0x07)	//bit9
#define REG_PWM2_VDBEN              (0x0A)	//bit9
#define REG_PWM3_VDBEN              (0x0D)	//bit9
#define REG_PWM4_VDBEN              (0x10)	//bit9
#define REG_PWM5_VDBEN              (0x13)	//bit9
//#define REG_PWM6_VDBEN              (0x42)  //bit9
//#define REG_PWM7_VDBEN              (0x45)  //bit9
//#define REG_PWM8_VDBEN              (0x48)  //bit9
#define REG_PWM_VDBEN_MASK          BIT(9)

#define REG_PWM0_RESET_EN           (0x04)	//bit10
#define REG_PWM1_RESET_EN           (0x07)	//bit10
#define REG_PWM2_RESET_EN           (0x0A)	//bit10
#define REG_PWM3_RESET_EN           (0x0D)	//bit10
#define REG_PWM4_RESET_EN           (0x10)	//bit10
#define REG_PWM5_RESET_EN           (0x13)	//bit10
//#define REG_PWM6_RESET_EN           (0x42)  //bit10
//#define REG_PWM7_RESET_EN           (0x45)  //bit10
//#define REG_PWM8_RESET_EN           (0x48)  //bit10
#define REG_PWM_RESET_EN_MASK       BIT(10)

#define REG_PWM0_DBEN               (0x04)	//bit11
#define REG_PWM1_DBEN               (0x07)	//bit11
#define REG_PWM2_DBEN               (0x0A)	//bit11
#define REG_PWM3_DBEN               (0x0D)	//bit11
#define REG_PWM4_DBEN               (0x10)	//bit11
#define REG_PWM5_DBEN               (0x13)	//bit11
//#define REG_PWM6_DBEN               (0x42)  //bit11
//#define REG_PWM7_DBEN               (0x45)  //bit11
//#define REG_PWM8_DBEN               (0x48)  //bit11
#define REG_PWM_DBEN_MASK           BIT(11)

#define REG_PWM0_IMPULSE_EN         (0x04)	//bit12
#define REG_PWM1_IMPULSE_EN         (0x07)	//bit12
#define REG_PWM2_IMPULSE_EN         (0x0A)	//bit12
#define REG_PWM3_IMPULSE_EN         (0x0D)	//bit12
#define REG_PWM4_IMPULSE_EN         (0x10)	//bit12
#define REG_PWM5_IMPULSE_EN         (0x13)	//bit12
//#define REG_PWM6_IMPULSE_EN         (0x42)  //bit12
//#define REG_PWM7_IMPULSE_EN         (0x45)  //bit12
//#define REG_PWM8_IMPULSE_EN         (0x48)  //bit12
#define REG_PWM_IMPULSE_EN_MASK     BIT(12)

#define REG_PWM0_ODDEVEN_SYNC       (0x04)	//bit13
#define REG_PWM1_ODDEVEN_SYNC       (0x07)	//bit13
#define REG_PWM2_ODDEVEN_SYNC       (0x0A)	//bit13
#define REG_PWM3_ODDEVEN_SYNC       (0x0D)	//bit13
#define REG_PWM4_ODDEVEN_SYNC       (0x10)	//bit13
#define REG_PWM5_ODDEVEN_SYNC       (0x13)	//bit13
//#define REG_PWM6_ODDEVEN_SYNC       (0x42)  //bit13
//#define REG_PWM7_ODDEVEN_SYNC       (0x45)  //bit13
//#define REG_PWM8_ODDEVEN_SYNC       (0x48)  //bit13
#define REG_PWM_ODDVEN_SYNC_MASK    BIT(13)

// Add from T8
#define REG_PWM0_VDBEN_SW           (0x04)	//bit14
#define REG_PWM1_VDBEN_SW           (0x07)	//bit14
#define REG_PWM2_VDBEN_SW           (0x0A)	//bit14
#define REG_PWM3_VDBEN_SW           (0x0D)	//bit14
#define REG_PWM4_VDBEN_SW           (0x10)	//bit14
#define REG_PWM5_VDBEN_SW           (0x13)	//bit14
#define REG_PWM_VDBEN_SW_MASK       BIT(14)

/* If chiptop provides the related reg, please use them at chiptop reg. */
//#define REG_PWM0_OEN                (0x04)  //bit15
//#define REG_PWM1_OEN                (0x07)  //bit15
//#define REG_PWM2_OEN                (0x0a)  //bit15
//#define REG_PWM3_OEN                (0x0d)  //bit15
//#define REG_PWM4_OEN                (0x10)  //bit15
//#define REG_PWM5_OEN                (0x13)  //bit15
//#define REG_PWM6_OEN                (0x42)  //bit15
//#define REG_PWM7_OEN                (0x45)  //bit15
//#define REG_PWM8_OEN                (0x48)  //bit15
#define REG_PWM_SYNC_SEL_MASK       BIT(15)

#define REG_RST_MUX0                (0x14)	//bit15
#define REG_RST_MUX1                (0x14)	//bit7
#define REG_RST_MUX2                (0x15)	//bit15
#define REG_RST_MUX3                (0x15)	//bit7
#define REG_RST_MUX4                (0x16)	//bit15
#define REG_RST_MUX5                (0x16)	//bit7
//#define REG_RST_MUX6                (0x49)  //bit15
//#define REG_RST_MUX7                (0x49)  //bit7
//#define REG_RST_MUX8                (0x4A)  //bit15
#define REG_PWM_RST_MUX_EN_MASK_L   BIT(7)
#define REG_PWM_RST_MUX_EN_MASK_H   BIT(15)

#define REG_HS_RST_CNT0             (0x14)	//bit8~11
#define REG_HS_RST_CNT1             (0x14)	//bit0~3
#define REG_HS_RST_CNT2             (0x15)	//bit8~11
#define REG_HS_RST_CNT3             (0x15)	//bit0~3
#define REG_HS_RST_CNT4             (0x16)	//bit8~11
#define REG_HS_RST_CNT5             (0x16)	//bit0~3
//#define REG_HS_RST_CNT6             (0x49)  //bit8~11
//#define REG_HS_RST_CNT7             (0x49)  //bit0~3
//#define REG_HS_RST_CNT8             (0x4A)  //bit8~11
#define REG_PWM_RST_CNT_MASK_L      (BIT(3) | BIT(2) | BIT(1) | BIT(0))
#define REG_PWM_RST_CNT_MASK_H      (BIT(11) | BIT(10) | BIT(9) | BIT(8))

#define REG_PWM0_PERIOD_EXT         (0x20)	//bit0~1
#define REG_PWM1_PERIOD_EXT         (0x20)	//bit2~3
#define REG_PWM2_PERIOD_EXT         (0x20)	//bit4~5
#define REG_PWM3_PERIOD_EXT         (0x20)	//bit6~7
#define REG_PWM4_PERIOD_EXT         (0x20)	//bit8~9
#define REG_PWM5_PERIOD_EXT         (0x20)	//bit10~11
//#define REG_PWM6_PERIOD_EXT         (0x4B)  //bit0~1
//#define REG_PWM7_PERIOD_EXT         (0x4B)  //bit2~3
//#define REG_PWM8_PERIOD_EXT         (0x4B)  //bit4~5

#define REG_PWM0_DUTY_EXT           (0x21)	//bit0~1
#define REG_PWM1_DUTY_EXT           (0x21)	//bit2~3
#define REG_PWM2_DUTY_EXT           (0x21)	//bit4~5
#define REG_PWM3_DUTY_EXT           (0x21)	//bit6~7
#define REG_PWM4_DUTY_EXT           (0x21)	//bit8~9
#define REG_PWM5_DUTY_EXT           (0x21)	//bit10~11
//#define REG_PWM6_DUTY_EXT           (0x4B)  //bit8~9
//#define REG_PWM7_DUTY_EXT           (0x4B)  //bit10~11
//#define REG_PWM8_DUTY_EXT           (0x4B)  //bit12~13

#define REG_PWM0_DIV_EXT            (0x22)	//bit0~7
#define REG_PWM1_DIV_EXT            (0x22)	//bit8~15
#define REG_PWM2_DIV_EXT            (0x23)	//bit0~7
#define REG_PWM3_DIV_EXT            (0x23)	//bit8~15
#define REG_PWM4_DIV_EXT            (0x24)	//bit0~7
#define REG_PWM5_DIV_EXT            (0x24)	//bit8~15
//#define REG_PWM6_DIV_EXT            (0x4C)  //bit0~7
//#define REG_PWM7_DIV_EXT            (0x4C)  //bit8~15
//#define REG_PWM8_DIV_EXT            (0x4D)  //bit0~7

#define REG_PWM0_SHIFT_L            (0x28)	//bit0~15
#define REG_PWM0_SHIFT_H            (0x29)	//bit0~1
#define REG_PWM1_SHIFT_L            (0x2A)	//bit0~15
#define REG_PWM1_SHIFT_H            (0x2B)	//bit0~1
#define REG_PWM2_SHIFT_L            (0x2C)	//bit0~15
#define REG_PWM2_SHIFT_H            (0x2D)	//bit0~1
#define REG_PWM3_SHIFT_L            (0x2E)	//bit0~15
#define REG_PWM3_SHIFT_H            (0x2F)	//bit0~1
#define REG_PWM4_SHIFT_L            (0x30)	//bit0~15
#define REG_PWM4_SHIFT_H            (0x31)	//bit0~1
#define REG_PWM5_SHIFT_L            (0x32)	//bit0~15
#define REG_PWM5_SHIFT_H            (0x33)	//bit0~1
//#define REG_PWM6_SHIFT_L            (0x4E)  //bit0~15
//#define REG_PWM6_SHIFT_H            (0x4F)  //bit0~1
//#define REG_PWM7_SHIFT_L            (0x50)  //bit0~15
//#define REG_PWM7_SHIFT_H            (0x51)  //bit0~1
//#define REG_PWM8_SHIFT_L            (0x52)  //bit0~15
//#define REG_PWM8_SHIFT_H            (0x53)  //bit0~1

#define REG_PWM0_NVS                (0x34)	//bit0
#define REG_PWM1_NVS                (0x34)	//bit1
#define REG_PWM2_NVS                (0x34)	//bit2
#define REG_PWM3_NVS                (0x34)	//bit3
#define REG_PWM4_NVS                (0x34)	//bit4
#define REG_PWM5_NVS                (0x34)	//bit5

#define REG_PWM0_Align              (0x35)	//bit0
#define REG_PWM1_Align              (0x35)	//bit1
#define REG_PWM2_Align              (0x35)	//bit2
#define REG_PWM3_Align              (0x35)	//bit3
#define REG_PWM4_Align              (0x35)	//bit4
#define REG_PWM5_Align              (0x35)	//bit5

//#define reg_pwm_as_chip_config      (0x70)    //bit0
//#define REG_PM_PWM0_IS_GPIO         (0x1C)    //bit5
//#define REG_PM_PWM0_PERIOD          (0x6A)    //bit0~15
//#define REG_PM_PWM0_DUTY            (0x69)    //bit0~15
//#define REG_PM_PWM0_DIV             (0x68)    //bit0~7
//#define REG_PM_PWM0_PORARITY        (0x6B)    //bit0
//#define REG_PM_PWM0_DBEN            (0x6B)    //bit1
//
//#define REG_PM_PWM1_PERIOD          (0x7A)    //bit0~15
//#define REG_PM_PWM1_DUTY            (0x79)    //bit0~15
//#define REG_PM_PWM1_DIV             (0x78)    //bit0~7
//#define REG_PM_PWM1_PORARITY        (0x7B)    //bit0
//#define REG_PM_PWM1_DBEN            (0x7B)    //bit1

//For Debug Use
#define REG_PWM_DUMMY2              (0x36)	//bit0~15 Default:0x0000
#define REG_PWM_DUMMY3              (0x37)	//bit0~15 Default:0xFFFF

#endif // _MTK_DTV_PWM_H_
