#ifndef _TGEN_FRAMELOCK_BK_H
#define _TGEN_FRAMELOCK_BK_H

#define TGEN_FRAMELOCK_BKA3A2 0x01474400

//Page TGEN_FRAMELOCK_BKA3A2
#define REG_0004_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x004)
    #define REG_0004_TGEN_FRAMELOCK_BKA3A2_REG_INSERT_RECORD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_TGEN_FRAMELOCK_BKA3A2_REG_FORCE_INSERT_BYPASS Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0004_TGEN_FRAMELOCK_BKA3A2_REG_VRR_SW_RST_ODCLK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x008)
    #define REG_0008_TGEN_FRAMELOCK_BKA3A2_REG_PROTECT_V_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x020)
    #define REG_0020_TGEN_FRAMELOCK_BKA3A2_REG_INSERT_DISTANCE_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0024_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x024)
    #define REG_0024_TGEN_FRAMELOCK_BKA3A2_REG_LAST_TGEN_VTOTAL_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0040_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x040)
    #define REG_0040_TGEN_FRAMELOCK_BKA3A2_REG_STATE_READBACK Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0040_TGEN_FRAMELOCK_BKA3A2_REG_STATE_SW_MODE_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0040_TGEN_FRAMELOCK_BKA3A2_REG_STATE_SW_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0040_TGEN_FRAMELOCK_BKA3A2_REG_STATUS_RST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0044_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x044)
    #define REG_0044_TGEN_FRAMELOCK_BKA3A2_REG_FAKE_INSERT_P_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0044_TGEN_FRAMELOCK_BKA3A2_REG_FAKE_INSERT_P_SW_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0044_TGEN_FRAMELOCK_BKA3A2_REG_FAKE_INSERT_CNT_SW_MODE_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0048_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x048)
    #define REG_0048_TGEN_FRAMELOCK_BKA3A2_REG_FAKE_INSERT_CNT_SW_MODE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_004C_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x04C)
    #define REG_004C_TGEN_FRAMELOCK_BKA3A2_REG_TGEN_RESET_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x060)
    #define REG_0060_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_USR_MD Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x064)
    #define REG_0064_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_LOWER_BOUND_USR_MD Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x068)
    #define REG_0068_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_UPPER_BOUND_USR_MD Fld(16,0,AC_FULLW10)//[15:0]
#define REG_006C_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x06C)
    #define REG_006C_TGEN_FRAMELOCK_BKA3A2_REG_LOWER_BOUND_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x070)
    #define REG_0070_TGEN_FRAMELOCK_BKA3A2_REG_UPPER_BOUND_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x074)
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_LOWER_BOUND_TOLERANCE Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_LOWER_BOUND_TOLERANCE_V2 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_UPPER_BOUND_TOLERANCE Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_UPPER_BOUND_TOLERANCE_V2 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_VRR_SELF_PROT_FLAG_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_CLR_INSERT_FLAG Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_FLAG_DISTANCE_LOWER_BOUND Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0074_TGEN_FRAMELOCK_BKA3A2_REG_FLAG_DISTANCE_UPPER_BOUND Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0078_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x078)
    #define REG_0078_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_USR_MD_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0078_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_LOWER_BOUND_USR_MD_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0078_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_UPPER_BOUND_USR_MD_EN Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0080_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x080)
    #define REG_0080_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_TARGET_SW_MODE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0080_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_TARGET_SELECT Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0080_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_EQ_FRAME_NUM Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0080_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_DONE_READBACK Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0080_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_STATUS_READBACK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0084_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x084)
    #define REG_0084_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x088)
    #define REG_0088_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_DIFF_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_008C_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x08C)
    #define REG_008C_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_DIFF_RANGE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x090)
    #define REG_0090_TGEN_FRAMELOCK_BKA3A2_REG_ABS_IO_DIFF_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0094_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x094)
    #define REG_0094_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_TOTAL_RESULT_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0098_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x098)
    #define REG_0098_TGEN_FRAMELOCK_BKA3A2_REG_INSERT_LARGER_READBACK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0C0)
    #define REG_00C0_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_METHOD Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_00C0_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_EQ_FRAME_NUM Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_00C0_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_ALMOST_READBACK Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_00C0_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_DONE_READBACK Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00C0_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_STATUS_READBACK Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0C4)
    #define REG_00C4_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0C8)
    #define REG_00C8_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_ALMOST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0CC)
    #define REG_00CC_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_FIRST_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0D0)
    #define REG_00D0_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_FIRST_DIFF Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0D4)
    #define REG_00D4_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_SECOND_TARGET Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0D8)
    #define REG_00D8_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_SECOND_DIFF Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0E0)
    #define REG_00E0_TGEN_FRAMELOCK_BKA3A2_REG_PHASE_DISTANCE_CNT0_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0E4)
    #define REG_00E4_TGEN_FRAMELOCK_BKA3A2_REG_PHASE_DISTANCE_CNT1_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x0E8)
    #define REG_00E8_TGEN_FRAMELOCK_BKA3A2_REG_CHASE_PHASE_RESULT_READBACK Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01A0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1A0)
    #define REG_01A0_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_LOWER_BOUND_TOLERANCE_N_M Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01A0_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_UPPER_BOUND_TOLERANCE_N_M Fld(3,4,AC_MSKB0)//[6:4]
#define REG_01C0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1C0)
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_FREERUN_SWITCH_NUM Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_IP_LOCK_VSYNC_MASK_NUM Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_TGEN_FREE2LOCK_PRO_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_IP_LOCK_VSYNC_CNT_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_SYNC_PRO_Y_ST_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_SYNC_PRO_Y_ST_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_SYNC_PRO_Y_END_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01C0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_SYNC_PRO_Y_END_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01C4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1C4)
    #define REG_01C4_TGEN_FRAMELOCK_BKA3A2_REG_IP_LOCK_VSYNC_TRIG_DLY Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1C8)
    #define REG_01C8_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_SYNC_PRO_Y_ST Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1CC)
    #define REG_01CC_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_SYNC_PRO_Y_END Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1D0)
    #define REG_01D0_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_USR_MD_N_M Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1D4)
    #define REG_01D4_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_LOWER_BOUND_USR_MD_N_M Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D8_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1D8)
    #define REG_01D8_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_UPPER_BOUND_USR_MD_N_M Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01DC_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1DC)
    #define REG_01DC_TGEN_FRAMELOCK_BKA3A2_REG_M_DELTA_USR_MD_EN_N_M Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01DC_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_LOWER_BOUND_USR_MD_EN_N_M Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01DC_TGEN_FRAMELOCK_BKA3A2_REG_PANEL_UPPER_BOUND_USR_MD_EN_N_M Fld(1,2,AC_MSKB0)//[2:2]
#define REG_01E0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1E0)
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_FREE_RUN_FLAG Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_FREE2LOCK_FLAG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK2OF_FLAG Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK2OF_FLAG_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_VCNT_STOP_FLAG Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_IP_LOCK_IN_PRO_Y_REGION Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_01E0_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_DONE_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1E4)
    #define REG_01E4_TGEN_FRAMELOCK_BKA3A2_REG_IP_LOCK_SAMPLE_VCNT Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E8_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1E8)
    #define REG_01E8_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_DONE_TOLERANCE Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01EC_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1EC)
    #define REG_01EC_TGEN_FRAMELOCK_BKA3A2_REG_LOWER_BOUND_READBACK_N_M Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F0_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1F0)
    #define REG_01F0_TGEN_FRAMELOCK_BKA3A2_REG_UPPER_BOUND_READBACK_N_M Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_TGEN_FRAMELOCK_BKA3A2 (TGEN_FRAMELOCK_BKA3A2 + 0x1F4)
    #define REG_01F4_TGEN_FRAMELOCK_BKA3A2_REG_LOCK_STATE_READBACK Fld(8,0,AC_FULLB0)//[7:0]

#endif
