#define MODOSD1 0x485800

//Page MODOSD1
#define REG_0140_MODOSD1_V004 (MODOSD1_V004 + 0x140)
	#define REG_0140_MODOSD1_V004_REG_MOD_1PTO2P_EN_0140 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0140_MODOSD1_V004_REG_MOD_2PTO4P_EN_0140 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0140_MODOSD1_V004_REG_MOD_4PTO8P_EN_0140 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0140_MODOSD1_V004_REG_MLX_METHOD_0140 Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_0140_MODOSD1_V004_REG_ENDIAN_MLX_0140 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0140_MODOSD1_V004_REG_ARGB_MODE_0140 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0140_MODOSD1_V004_REG_YUV_422_MODE_0140 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0144_MODOSD1_V004 (MODOSD1_V004 + 0x144)
	#define REG_0144_MODOSD1_V004_REG_SEL_R_CH0_0144 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0144_MODOSD1_V004_REG_SEL_G_CH0_0144 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0144_MODOSD1_V004_REG_SEL_B_CH0_0144 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_0144_MODOSD1_V004_REG_SEL_R_CH1_0144 Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_0144_MODOSD1_V004_REG_SEL_G_CH1_0144 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_0144_MODOSD1_V004_REG_SEL_B_CH1_0144 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0148_MODOSD1_V004 (MODOSD1_V004 + 0x148)
	#define REG_0148_MODOSD1_V004_REG_SEL_R_CH2_0148 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0148_MODOSD1_V004_REG_SEL_G_CH2_0148 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0148_MODOSD1_V004_REG_SEL_B_CH2_0148 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_0148_MODOSD1_V004_REG_SEL_R_CH3_0148 Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_0148_MODOSD1_V004_REG_SEL_G_CH3_0148 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_0148_MODOSD1_V004_REG_SEL_B_CH3_0148 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_014C_MODOSD1_V004 (MODOSD1_V004 + 0x14C)
	#define REG_014C_MODOSD1_V004_REG_SEL_R_CH4_014C Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_014C_MODOSD1_V004_REG_SEL_G_CH4_014C Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_014C_MODOSD1_V004_REG_SEL_B_CH4_014C Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_014C_MODOSD1_V004_REG_SEL_R_CH5_014C Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_014C_MODOSD1_V004_REG_SEL_G_CH5_014C Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_014C_MODOSD1_V004_REG_SEL_B_CH5_014C Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0150_MODOSD1_V004 (MODOSD1_V004 + 0x150)
	#define REG_0150_MODOSD1_V004_REG_SEL_R_CH6_0150 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0150_MODOSD1_V004_REG_SEL_G_CH6_0150 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0150_MODOSD1_V004_REG_SEL_B_CH6_0150 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_0150_MODOSD1_V004_REG_SEL_R_CH7_0150 Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_0150_MODOSD1_V004_REG_SEL_G_CH7_0150 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_0150_MODOSD1_V004_REG_SEL_B_CH7_0150 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0154_MODOSD1_V004 (MODOSD1_V004 + 0x154)
	#define REG_0154_MODOSD1_V004_REG_IN_CH0_SWAP_0154 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0154_MODOSD1_V004_REG_IN_CH1_SWAP_0154 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0154_MODOSD1_V004_REG_IN_CH2_SWAP_0154 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0154_MODOSD1_V004_REG_IN_CH3_SWAP_0154 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0158_MODOSD1_V004 (MODOSD1_V004 + 0x158)
	#define REG_0158_MODOSD1_V004_REG_IN_CH4_SWAP_0158 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_0158_MODOSD1_V004_REG_IN_CH5_SWAP_0158 Fld(3,4,AC_MSKB0)//[6:4]
	#define REG_0158_MODOSD1_V004_REG_IN_CH6_SWAP_0158 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_0158_MODOSD1_V004_REG_IN_CH7_SWAP_0158 Fld(3,12,AC_MSKB1)//[14:12]
#define REG_0180_MODOSD1_V004 (MODOSD1_V004 + 0x180)
	#define REG_0180_MODOSD1_V004_REG_TEST_ENGINE_0180 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_0180_MODOSD1_V004_REG_TEST_V_LINE_MODE_0180 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0180_MODOSD1_V004_REG_TEST_V_INV_0180 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0180_MODOSD1_V004_REG_TEST_H_LINE_MODE_0180 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0180_MODOSD1_V004_REG_TEST_H_INV_0180 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_0180_MODOSD1_V004_REG_TEST_GRAY_B_EN_0180 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0180_MODOSD1_V004_REG_TEST_GRAY_G_EN_0180 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0180_MODOSD1_V004_REG_TEST_GRAY_R_EN_0180 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0180_MODOSD1_V004_REG_TEST_MODE_0180 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_MODOSD1_V004 (MODOSD1_V004 + 0x184)
	#define REG_0184_MODOSD1_V004_REG_TEST_H_LINE_ST_0184 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0188_MODOSD1_V004 (MODOSD1_V004 + 0x188)
	#define REG_0188_MODOSD1_V004_REG_TEST_H_LINE_END_0188 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_018C_MODOSD1_V004 (MODOSD1_V004 + 0x18C)
	#define REG_018C_MODOSD1_V004_REG_TEST_V_LINE_ST_018C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0190_MODOSD1_V004 (MODOSD1_V004 + 0x190)
	#define REG_0190_MODOSD1_V004_REG_TEST_V_LINE_END_0190 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0194_MODOSD1_V004 (MODOSD1_V004 + 0x194)
	#define REG_0194_MODOSD1_V004_REG_TEST_COLOR_A_0194 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0198_MODOSD1_V004 (MODOSD1_V004 + 0x198)
	#define REG_0198_MODOSD1_V004_REG_TEST_COLOR_R_0198 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_019C_MODOSD1_V004 (MODOSD1_V004 + 0x19C)
	#define REG_019C_MODOSD1_V004_REG_TEST_COLOR_G_019C Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01A0_MODOSD1_V004 (MODOSD1_V004 + 0x1A0)
	#define REG_01A0_MODOSD1_V004_REG_TEST_COLOR_B_01A0 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01A4_MODOSD1_V004 (MODOSD1_V004 + 0x1A4)
	#define REG_01A4_MODOSD1_V004_REG_TEST2_COLOR_A_01A4 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01A8_MODOSD1_V004 (MODOSD1_V004 + 0x1A8)
	#define REG_01A8_MODOSD1_V004_REG_TEST2_COLOR_R_01A8 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01AC_MODOSD1_V004 (MODOSD1_V004 + 0x1AC)
	#define REG_01AC_MODOSD1_V004_REG_TEST2_COLOR_G_01AC Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01B0_MODOSD1_V004 (MODOSD1_V004 + 0x1B0)
	#define REG_01B0_MODOSD1_V004_REG_TEST2_COLOR_B_01B0 Fld(12,0,AC_MSKW10)//[11:0]
#define REG_01B4_MODOSD1_V004 (MODOSD1_V004 + 0x1B4)
	#define REG_01B4_MODOSD1_V004_REG_TEST_COLOR_CHG_LEVEL_01B4 Fld(15,0,AC_MSKW10)//[14:0]
	#define REG_01B4_MODOSD1_V004_REG_TEST_COLOR_CHG_EN_01B4 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01C0_MODOSD1_V004 (MODOSD1_V004 + 0x1C0)
	#define REG_01C0_MODOSD1_V004_REG_TGEN_HTT_01C0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C4_MODOSD1_V004 (MODOSD1_V004 + 0x1C4)
	#define REG_01C4_MODOSD1_V004_REG_TGEN_HSYNC_WIDTH_01C4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01C8_MODOSD1_V004 (MODOSD1_V004 + 0x1C8)
	#define REG_01C8_MODOSD1_V004_REG_TGEN_HDE_ST_01C8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01CC_MODOSD1_V004 (MODOSD1_V004 + 0x1CC)
	#define REG_01CC_MODOSD1_V004_REG_TGEN_HDE_WIDTH_01CC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D0_MODOSD1_V004 (MODOSD1_V004 + 0x1D0)
	#define REG_01D0_MODOSD1_V004_REG_TGEN_VTT_01D0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D4_MODOSD1_V004 (MODOSD1_V004 + 0x1D4)
	#define REG_01D4_MODOSD1_V004_REG_TGEN_VSYNC_WIDTH_01D4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01D8_MODOSD1_V004 (MODOSD1_V004 + 0x1D8)
	#define REG_01D8_MODOSD1_V004_REG_TGEN_VDE_ST_01D8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01DC_MODOSD1_V004 (MODOSD1_V004 + 0x1DC)
	#define REG_01DC_MODOSD1_V004_REG_TGEN_VDE_WIDTH_01DC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E0_MODOSD1_V004 (MODOSD1_V004 + 0x1E0)
	#define REG_01E0_MODOSD1_V004_REG_TGEN_EN_01E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01E0_MODOSD1_V004_REG_TGEN_SET_READY_01E0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01E0_MODOSD1_V004_REG_TGEN_ENGINE_01E0 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01E0_MODOSD1_V004_REG_TGEN_REPLACE_SEL_01E0 Fld(5,4,AC_MSKW10)//[8:4]
	#define REG_01E0_MODOSD1_V004_REG_TGEN_DB_EN_01E0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01E0_MODOSD1_V004_REG_TGEN_VXDE_EN_01E0 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_01E0_MODOSD1_V004_REG_TGEN_NO_CONT_HDE_01E0 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01E4_MODOSD1_V004 (MODOSD1_V004 + 0x1E4)
	#define REG_01E4_MODOSD1_V004_REG_MFT_RSTZ_01E4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01E4_MODOSD1_V004_REG_HS_WID_ADJ_EN_01E4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_01E4_MODOSD1_V004_REG_SSAPYB_H_BOW_01E4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_01E4_MODOSD1_V004_REG_MEM_OFF_DLY_IN_01E4 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01E4_MODOSD1_V004_REG_MEM_OFF_DLY_ACK_01E4 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E8_MODOSD1_V004 (MODOSD1_V004 + 0x1E8)
	#define REG_01E8_MODOSD1_V004_REG_MFT_DUMMY0_01E8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01EC_MODOSD1_V004 (MODOSD1_V004 + 0x1EC)
	#define REG_01EC_MODOSD1_V004_REG_MFT_DUMMY1_01EC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F0_MODOSD1_V004 (MODOSD1_V004 + 0x1F0)
	#define REG_01F0_MODOSD1_V004_REG_MFT_DUMMY2_01F0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01F4_MODOSD1_V004 (MODOSD1_V004 + 0x1F4)
	#define REG_01F4_MODOSD1_V004_REG_MFT_DUMMY3_01F4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01FC_MODOSD1_V004 (MODOSD1_V004 + 0x1FC)
	#define REG_01FC_MODOSD1_V004_REG_DEBUG_OUT_SEL_01FC Fld(3,0,AC_MSKB0)//[2:0]
