#ifndef _BLEND_TOP_BKA36B_H_
#define _BLEND_TOP_BKA36B_H_

#define BLEND_TOP_BKA36B 0x0146D600

//Page BLEND_TOP_BKA36B
#define REG_0004_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x004)
    #define REG_0004_BLEND_TOP_BKA36B_REG_LAY0_CONST_ALPHA Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0004_BLEND_TOP_BKA36B_REG_LAY0_SRC_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0004_BLEND_TOP_BKA36B_REG_SRC0_ACK_SEL_0004 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0004_BLEND_TOP_BKA36B_REG_LAYER0_OFF Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0004_BLEND_TOP_BKA36B_REG_SRC0_OFF Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0004_BLEND_TOP_BKA36B_REG_LAY0_CONST_ALPHA_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x008)
    #define REG_0008_BLEND_TOP_BKA36B_REG_LAYER0_OFF_B Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0008_BLEND_TOP_BKA36B_REG_LAYER0_OFF_G Fld(8,8,AC_FULLB1)//[15:8]
#define REG_000C_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x00C)
    #define REG_000C_BLEND_TOP_BKA36B_REG_LAYER0_OFF_R Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_000C_BLEND_TOP_BKA36B_REG_OFF_LAY0_ALPHA Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0044_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x044)
    #define REG_0044_BLEND_TOP_BKA36B_REG_LAY1_CONST_ALPHA Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0044_BLEND_TOP_BKA36B_REG_LAY1_SRC_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0044_BLEND_TOP_BKA36B_REG_SRC1_ACK_SEL_0044 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0044_BLEND_TOP_BKA36B_REG_LAYER1_OFF Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0044_BLEND_TOP_BKA36B_REG_SRC1_OFF Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0044_BLEND_TOP_BKA36B_REG_LAY1_CONST_ALPHA_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0048_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x048)
    #define REG_0048_BLEND_TOP_BKA36B_REG_LAYER1_OFF_B Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0048_BLEND_TOP_BKA36B_REG_LAYER1_OFF_G Fld(8,8,AC_FULLB1)//[15:8]
#define REG_004C_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x04C)
    #define REG_004C_BLEND_TOP_BKA36B_REG_LAYER1_OFF_R Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_004C_BLEND_TOP_BKA36B_REG_OFF_LAY1_ALPHA Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0084_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x084)
    #define REG_0084_BLEND_TOP_BKA36B_REG_LAY2_CONST_ALPHA Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0084_BLEND_TOP_BKA36B_REG_LAY2_SRC_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0084_BLEND_TOP_BKA36B_REG_SRC2_ACK_SEL_0084 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_0084_BLEND_TOP_BKA36B_REG_LAYER2_OFF Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0084_BLEND_TOP_BKA36B_REG_SRC2_OFF Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0084_BLEND_TOP_BKA36B_REG_LAY2_CONST_ALPHA_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0088_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x088)
    #define REG_0088_BLEND_TOP_BKA36B_REG_LAYER2_OFF_B Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0088_BLEND_TOP_BKA36B_REG_LAYER2_OFF_G Fld(8,8,AC_FULLB1)//[15:8]
#define REG_008C_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x08C)
    #define REG_008C_BLEND_TOP_BKA36B_REG_LAYER2_OFF_R Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_008C_BLEND_TOP_BKA36B_REG_OFF_LAY2_ALPHA Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00C4_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x0C4)
    #define REG_00C4_BLEND_TOP_BKA36B_REG_LAY3_CONST_ALPHA Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C4_BLEND_TOP_BKA36B_REG_LAY3_SRC_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_00C4_BLEND_TOP_BKA36B_REG_SRC3_ACK_SEL_00C4 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_00C4_BLEND_TOP_BKA36B_REG_LAYER3_OFF Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_00C4_BLEND_TOP_BKA36B_REG_SRC3_OFF Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_00C4_BLEND_TOP_BKA36B_REG_LAY3_CONST_ALPHA_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00C8_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x0C8)
    #define REG_00C8_BLEND_TOP_BKA36B_REG_LAYER3_OFF_B Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00C8_BLEND_TOP_BKA36B_REG_LAYER3_OFF_G Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00CC_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x0CC)
    #define REG_00CC_BLEND_TOP_BKA36B_REG_LAYER3_OFF_R Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00CC_BLEND_TOP_BKA36B_REG_OFF_LAY3_ALPHA Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0100_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x100)
    #define REG_0100_BLEND_TOP_BKA36B_REG_H_SIZE Fld(13,0,AC_MSKW10)//[12:0]
    #define REG_0100_BLEND_TOP_BKA36B_REG_FORCE_DST_ACK_1 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0104_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x104)
    #define REG_0104_BLEND_TOP_BKA36B_REG_BK_B Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_0104_BLEND_TOP_BKA36B_REG_BK_G Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0108_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x108)
    #define REG_0108_BLEND_TOP_BKA36B_REG_BK_R Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01C4_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1C4)
    #define REG_01C4_BLEND_TOP_BKA36B_REG_SRC0_IN_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01C8_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1C8)
    #define REG_01C8_BLEND_TOP_BKA36B_REG_SRC1_IN_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01CC_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1CC)
    #define REG_01CC_BLEND_TOP_BKA36B_REG_SRC2_IN_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01D0_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1D0)
    #define REG_01D0_BLEND_TOP_BKA36B_REG_SRC3_IN_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01D4_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1D4)
    #define REG_01D4_BLEND_TOP_BKA36B_REG_OUT_BLACK_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01D4_BLEND_TOP_BKA36B_REG_OUT_NOISE_EN Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01D8_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1D8)
    #define REG_01D8_BLEND_TOP_BKA36B_REG_OUT_BLACK_R Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_01D8_BLEND_TOP_BKA36B_REG_OUT_BLACK_G Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01DC_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1DC)
    #define REG_01DC_BLEND_TOP_BKA36B_REG_OUT_BLACK_B Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01E0_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1E0)
    #define REG_01E0_BLEND_TOP_BKA36B_REG_VOP2MUX_OUT_SEL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01E0_BLEND_TOP_BKA36B_REG_MUX2VB_IN_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01E0_BLEND_TOP_BKA36B_REG_DBF_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_01E0_BLEND_TOP_BKA36B_REG_VB_BYPASS_01E0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01FC_BLEND_TOP_BKA36B (BLEND_TOP_BKA36B + 0x1FC)
    #define REG_01FC_BLEND_TOP_BKA36B_REG_BLEND_DUMMY Fld(16,0,AC_FULLW10)//[15:0]

#endif
