#ifndef _CKGEN01_H
#define _CKGEN01_H

#include "hwreg_common.h"

#define ckgen01 0x00206000

//Page CKGEN01_1
#define REG_0000_CKGEN01 (ckgen01 + 0x000)
    #define REG_0000_CKGEN01_REG_CKG_ADC2MIU Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0008_CKGEN01 (ckgen01 + 0x008)
    #define REG_0008_CKGEN01_REG_CKG_ADC2MIUSC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0010_CKGEN01 (ckgen01 + 0x010)
    #define REG_0010_CKGEN01_REG_CKG_ADC2SC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0018_CKGEN01 (ckgen01 + 0x018)
    #define REG_0018_CKGEN01_REG_CKG_ADC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0020_CKGEN01 (ckgen01 + 0x020)
    #define REG_0020_CKGEN01_REG_CKG_ADCPLL200 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0028_CKGEN01 (ckgen01 + 0x028)
    #define REG_0028_CKGEN01_REG_CKG_ADCPLL400 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0030_CKGEN01 (ckgen01 + 0x030)
    #define REG_0030_CKGEN01_REG_CKG_ADCPLLB_MPLL_216M Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0038_CKGEN01 (ckgen01 + 0x038)
    #define REG_0038_CKGEN01_REG_CKG_B_ADC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0040_CKGEN01 (ckgen01 + 0x040)
    #define REG_0040_CKGEN01_REG_CKG_B_INT Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0048_CKGEN01 (ckgen01 + 0x048)
    #define REG_0048_CKGEN01_REG_CKG_CLK_TSTBUS_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0058_CKGEN01 (ckgen01 + 0x058)
    #define REG_0058_CKGEN01_REG_CKG_CLKD_ADC_P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0060_CKGEN01 (ckgen01 + 0x060)
    #define REG_0060_CKGEN01_REG_CKG_CLKD_ATOP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0068_CKGEN01 (ckgen01 + 0x068)
    #define REG_0068_CKGEN01_REG_CKG_CLKD_ATOP_INTERNAL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0070_CKGEN01 (ckgen01 + 0x070)
    #define REG_0070_CKGEN01_REG_CKG_CLKPLL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0078_CKGEN01 (ckgen01 + 0x078)
    #define REG_0078_CKGEN01_REG_CKG_CVBS_DAC_A_DIGITAL0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0080_CKGEN01 (ckgen01 + 0x080)
    #define REG_0080_CKGEN01_REG_CKG_CVBS_DAC_A_DIGITAL0_MUX Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0088_CKGEN01 (ckgen01 + 0x088)
    #define REG_0088_CKGEN01_REG_CKG_CVBS_DAC_A_DIGITAL1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0090_CKGEN01 (ckgen01 + 0x090)
    #define REG_0090_CKGEN01_REG_CKG_DIG_108 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0098_CKGEN01 (ckgen01 + 0x098)
    #define REG_0098_CKGEN01_REG_CKG_DIG_216 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00A0_CKGEN01 (ckgen01 + 0x0A0)
    #define REG_00A0_CKGEN01_REG_CKG_FBLANK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00A8_CKGEN01 (ckgen01 + 0x0A8)
    #define REG_00A8_CKGEN01_REG_CKG_FSC_VD Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00B0_CKGEN01 (ckgen01 + 0x0B0)
    #define REG_00B0_CKGEN01_REG_CKG_FSCX2_FB2ATOP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_00B8_CKGEN01 (ckgen01 + 0x0B8)
    #define REG_00B8_CKGEN01_REG_CKG_G_ADC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_00C0_CKGEN01 (ckgen01 + 0x0C0)
    #define REG_00C0_CKGEN01_REG_CKG_G_INT Fld(4,0,AC_MSKB0)//[3:0]
#define REG_00C8_CKGEN01 (ckgen01 + 0x0C8)
    #define REG_00C8_CKGEN01_REG_CKG_ICLAMP_RGB Fld(4,0,AC_MSKB0)//[3:0]
#define REG_00D0_CKGEN01 (ckgen01 + 0x0D0)
    #define REG_00D0_CKGEN01_REG_CKG_ISOG Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00E0_CKGEN01 (ckgen01 + 0x0E0)
    #define REG_00E0_CKGEN01_REG_CKG_NCO_CLK Fld(2,0,AC_MSKB0)//[1:0]
#define REG_00F0_CKGEN01 (ckgen01 + 0x0F0)
    #define REG_00F0_CKGEN01_REG_CKG_R_ADC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_00F8_CKGEN01 (ckgen01 + 0x0F8)
    #define REG_00F8_CKGEN01_REG_CKG_R_INT Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0108_CKGEN01 (ckgen01 + 0x108)
    #define REG_0108_CKGEN01_REG_CKG_VD_ICLAMP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0110_CKGEN01 (ckgen01 + 0x110)
    #define REG_0110_CKGEN01_REG_CKG_VD_ADCPLL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0118_CKGEN01 (ckgen01 + 0x118)
    #define REG_0118_CKGEN01_REG_CKG_VD_NCO_CLK Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0120_CKGEN01 (ckgen01 + 0x120)
    #define REG_0120_CKGEN01_REG_CKG_VDPLL400 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0128_CKGEN01 (ckgen01 + 0x128)
    #define REG_0128_CKGEN01_REG_CKG_XTAL12_4INTERRUPT Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0130_CKGEN01 (ckgen01 + 0x130)
    #define REG_0130_CKGEN01_REG_CKG_XTAL12_4PLUGDET Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0138_CKGEN01 (ckgen01 + 0x138)
    #define REG_0138_CKGEN01_REG_CKG_XTAL12 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0140_CKGEN01 (ckgen01 + 0x140)
    #define REG_0140_CKGEN01_REG_CKG_XTAL24 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0148_CKGEN01 (ckgen01 + 0x148)
    #define REG_0148_CKGEN01_REG_CKG_Y_ADC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0150_CKGEN01 (ckgen01 + 0x150)
    #define REG_0150_CKGEN01_REG_CKG_Y_INT Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0158_CKGEN01 (ckgen01 + 0x158)
    #define REG_0158_CKGEN01_REG_CKG_YUV_ADC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0160_CKGEN01 (ckgen01 + 0x160)
    #define REG_0160_CKGEN01_REG_CKG_ADCPLB_MPLL_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_01E0_CKGEN01 (ckgen01 + 0x1E0)
    #define REG_01E0_CKGEN01_REG_CKG_RV55AUDIO_DAP_01E0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_01E8_CKGEN01 (ckgen01 + 0x1E8)
    #define REG_01E8_CKGEN01_REG_CKG_FRC_FCLK Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01E8_CKGEN01_REG_CKG_FRC_FCLK_FRCMI Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_01E8_CKGEN01_REG_CKG_FRC_FCLK_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_01E8_CKGEN01_REG_CKG_FRC_FCLK_FRCMEHALO Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01E8_CKGEN01_REG_CKG_FRC_FCLK_FRCMEMLB Fld(2,12,AC_MSKB1)//[13:12]
#define REG_01EC_CKGEN01 (ckgen01 + 0x1EC)
    #define REG_01EC_CKGEN01_REG_CKG_DAP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_01F0_CKGEN01 (ckgen01 + 0x1F0)
    #define REG_01F0_CKGEN01_REG_CKG_FRC_FCLK_2X Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01F0_CKGEN01_REG_CKG_FRC_FCLK_2X_FRCIOPMRV55 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_01F4_CKGEN01 (ckgen01 + 0x1F4)
    #define REG_01F4_CKGEN01_REG_CKG_FRC_FCLK_2X_FRCMEHALO Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_01F4_CKGEN01_REG_CKG_FRC_FCLK_2X_FRCCORE1_01F4 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01F4_CKGEN01_REG_CKG_FRC_FCLK_2X_FRCCORE2_01F4 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_01F4_CKGEN01_REG_CKG_FRC_FCLK_2X_FRCCORE3_01F4 Fld(4,8,AC_MSKB1)//[11:8]
#define REG_01F8_CKGEN01 (ckgen01 + 0x1F8)
    #define REG_01F8_CKGEN01_REG_CKG_FRC_FCLK_2XPLUS Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_01F8_CKGEN01_REG_CKG_FRC_FCLK_2XPLUS_SCNR_01F8 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_01F8_CKGEN01_REG_CKG_FRC_FCLK_2XPLUS_SCMW Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_01F8_CKGEN01_REG_CKG_FRC_FCLK_2XPLUS_SCIP Fld(2,14,AC_MSKB1)//[15:14]
#define REG_0200_CKGEN01 (ckgen01 + 0x200)
    #define REG_0200_CKGEN01_REG_CKG_RV55FRC_RV55FRC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0208_CKGEN01 (ckgen01 + 0x208)
    #define REG_0208_CKGEN01_REG_CKG_RV55FRC Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0208_CKGEN01_REG_CKG_RV55FRC_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0210_CKGEN01 (ckgen01 + 0x210)
    #define REG_0210_CKGEN01_REG_CKG_RV55FRC_JTAG_TCK_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0210_CKGEN01_REG_CKG_RV55FRC_JTAG_TCK_RV55FRC Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0218_CKGEN01 (ckgen01 + 0x218)
    #define REG_0218_CKGEN01_REG_CKG_RV55PQU_RV55PQU Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0220_CKGEN01 (ckgen01 + 0x220)
    #define REG_0220_CKGEN01_REG_CKG_RV55PQU Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0220_CKGEN01_REG_CKG_RV55PQU_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0228_CKGEN01 (ckgen01 + 0x228)
    #define REG_0228_CKGEN01_REG_CKG_RV55PQU_JTAG_TCK_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0228_CKGEN01_REG_CKG_RV55PQU_JTAG_TCK_RV55PQU Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0230_CKGEN01 (ckgen01 + 0x230)
    #define REG_0230_CKGEN01_REG_CKG_XCSRSPLL_SYN Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0238_CKGEN01 (ckgen01 + 0x238)
    #define REG_0238_CKGEN01_REG_CKG_DAP_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0238_CKGEN01_REG_CKG_DAP_RV55FRC Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0238_CKGEN01_REG_CKG_DAP_RV55PQU Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0240_CKGEN01 (ckgen01 + 0x240)
    #define REG_0240_CKGEN01_REG_CKG_RV55DAP_JTAG_TCK_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0248_CKGEN01 (ckgen01 + 0x248)
    #define REG_0248_CKGEN01_REG_CKG_XTAL_24M_FRCMEMLB Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0250_CKGEN01 (ckgen01 + 0x250)
    #define REG_0250_CKGEN01_REG_CKG_XTAL_24M_FRCMI Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0258_CKGEN01 (ckgen01 + 0x258)
    #define REG_0258_CKGEN01_REG_CKG_XTAL_12M_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0260_CKGEN01 (ckgen01 + 0x260)
    #define REG_0260_CKGEN01_REG_CKG_XTAL_24M_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0268_CKGEN01 (ckgen01 + 0x268)
    #define REG_0268_CKGEN01_REG_CKG_XTAL_24M_FRCMEHALO Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0270_CKGEN01 (ckgen01 + 0x270)
    #define REG_0270_CKGEN01_REG_CKG_XTAL_12M_RV55FRC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0278_CKGEN01 (ckgen01 + 0x278)
    #define REG_0278_CKGEN01_REG_CKG_XTAL_24M_RV55FRC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0280_CKGEN01 (ckgen01 + 0x280)
    #define REG_0280_CKGEN01_REG_CKG_XTAL_12M_RV55PQU Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0288_CKGEN01 (ckgen01 + 0x288)
    #define REG_0288_CKGEN01_REG_CKG_XTAL_24M_RV55PQU Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02A0_CKGEN01 (ckgen01 + 0x2A0)
    #define REG_02A0_CKGEN01_REG_CKG_GE Fld(5,0,AC_MSKB0)//[4:0]
#define REG_02B0_CKGEN01 (ckgen01 + 0x2B0)
    #define REG_02B0_CKGEN01_REG_CKG_HDMI_R2 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_02B8_CKGEN01 (ckgen01 + 0x2B8)
    #define REG_02B8_CKGEN01_REG_CKG_HDMIRX_TIMESTAMP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_02C0_CKGEN01 (ckgen01 + 0x2C0)
    #define REG_02C0_CKGEN01_REG_CKG_128FS_FB_S0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_02C8_CKGEN01 (ckgen01 + 0x2C8)
    #define REG_02C8_CKGEN01_REG_CKG_128FS_FB_S1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_02D0_CKGEN01 (ckgen01 + 0x2D0)
    #define REG_02D0_CKGEN01_REG_CKG_128FS_S0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_02D8_CKGEN01 (ckgen01 + 0x2D8)
    #define REG_02D8_CKGEN01_REG_CKG_128FS_S1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_02E0_CKGEN01 (ckgen01 + 0x2E0)
    #define REG_02E0_CKGEN01_REG_CKG_216 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_02E8_CKGEN01 (ckgen01 + 0x2E8)
    #define REG_02E8_CKGEN01_REG_CKG_256FS_S0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_02F0_CKGEN01 (ckgen01 + 0x2F0)
    #define REG_02F0_CKGEN01_REG_CKG_256FS_S1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_02F8_CKGEN01 (ckgen01 + 0x2F8)
    #define REG_02F8_CKGEN01_REG_CKG_432 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0300_CKGEN01 (ckgen01 + 0x300)
    #define REG_0300_CKGEN01_REG_CKG_864 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0308_CKGEN01 (ckgen01 + 0x308)
    #define REG_0308_CKGEN01_REG_CKG_CLK_DET_INNER_MISC_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0310_CKGEN01 (ckgen01 + 0x310)
    #define REG_0310_CKGEN01_REG_CKG_CLK_DET_INNER_MISC_0_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0318_CKGEN01 (ckgen01 + 0x318)
    #define REG_0318_CKGEN01_REG_CKG_CLK_DET_INNER_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0320_CKGEN01 (ckgen01 + 0x320)
    #define REG_0320_CKGEN01_REG_CKG_CLK_DET_INNER_MISC_1_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0328_CKGEN01 (ckgen01 + 0x328)
    #define REG_0328_CKGEN01_REG_CKG_CTS_SYNTH_S0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0330_CKGEN01 (ckgen01 + 0x330)
    #define REG_0330_CKGEN01_REG_CKG_CTS_SYNTH_S0_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0338_CKGEN01 (ckgen01 + 0x338)
    #define REG_0338_CKGEN01_REG_CKG_CTS_SYNTH_S1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0340_CKGEN01 (ckgen01 + 0x340)
    #define REG_0340_CKGEN01_REG_CKG_CTS_SYNTH_S1_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0348_CKGEN01 (ckgen01 + 0x348)
    #define REG_0348_CKGEN01_REG_CKG_DSC_ENGINE Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0350_CKGEN01 (ckgen01 + 0x350)
    #define REG_0350_CKGEN01_REG_CKG_DVI2MIU_RD_S0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0358_CKGEN01 (ckgen01 + 0x358)
    #define REG_0358_CKGEN01_REG_CKG_DVI2MIU_RD_S1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0360_CKGEN01 (ckgen01 + 0x360)
    #define REG_0360_CKGEN01_REG_CKG_DVI2MIU_WR_S0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0368_CKGEN01 (ckgen01 + 0x368)
    #define REG_0368_CKGEN01_REG_CKG_DVI2MIU_WR_S0_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0370_CKGEN01 (ckgen01 + 0x370)
    #define REG_0370_CKGEN01_REG_CKG_DVI2MIU_WR_S0_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0398_CKGEN01 (ckgen01 + 0x398)
    #define REG_0398_CKGEN01_REG_CKG_DVI2MIU_WR_S1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_03A0_CKGEN01 (ckgen01 + 0x3A0)
    #define REG_03A0_CKGEN01_REG_CKG_DVI2MIU_WR_S1_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_03A8_CKGEN01 (ckgen01 + 0x3A8)
    #define REG_03A8_CKGEN01_REG_CKG_DVI2MIU_WR_S1_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_03D0_CKGEN01 (ckgen01 + 0x3D0)
    #define REG_03D0_CKGEN01_REG_CKG_EARC_AUDIO Fld(3,0,AC_MSKB0)//[2:0]
#define REG_03D8_CKGEN01 (ckgen01 + 0x3D8)
    #define REG_03D8_CKGEN01_REG_CKG_EARC_CM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_03E0_CKGEN01 (ckgen01 + 0x3E0)
    #define REG_03E0_CKGEN01_REG_CKG_EARC_DEBOUNCE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_03E8_CKGEN01 (ckgen01 + 0x3E8)
    #define REG_03E8_CKGEN01_REG_CKG_EARC_DM_PRBS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_03F0_CKGEN01 (ckgen01 + 0x3F0)
    #define REG_03F0_CKGEN01_REG_CKG_LINK_DSCD Fld(5,0,AC_MSKB0)//[4:0]
#define REG_03F8_CKGEN01 (ckgen01 + 0x3F8)
    #define REG_03F8_CKGEN01_REG_CKG_P0_CLK_DET_DEC_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0400_CKGEN01 (ckgen01 + 0x400)
    #define REG_0400_CKGEN01_REG_CKG_P0_CLK_DET_DEC_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0408_CKGEN01 (ckgen01 + 0x408)
    #define REG_0408_CKGEN01_REG_CKG_P0_CLK_DET_DEC_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0410_CKGEN01 (ckgen01 + 0x410)
    #define REG_0410_CKGEN01_REG_CKG_P0_CLK_DET_DEC_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0418_CKGEN01 (ckgen01 + 0x418)
    #define REG_0418_CKGEN01_REG_CKG_P0_CLK_DET_DEP_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0420_CKGEN01 (ckgen01 + 0x420)
    #define REG_0420_CKGEN01_REG_CKG_P0_CLK_DET_DEP_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0428_CKGEN01 (ckgen01 + 0x428)
    #define REG_0428_CKGEN01_REG_CKG_P0_CLK_DET_DEP_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0430_CKGEN01 (ckgen01 + 0x430)
    #define REG_0430_CKGEN01_REG_CKG_P0_CLK_DET_DEP_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0438_CKGEN01 (ckgen01 + 0x438)
    #define REG_0438_CKGEN01_REG_CKG_P0_LINK Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0440_CKGEN01 (ckgen01 + 0x440)
    #define REG_0440_CKGEN01_REG_CKG_P0_PIX_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0448_CKGEN01 (ckgen01 + 0x448)
    #define REG_0448_CKGEN01_REG_CKG_P0_PIX_8P Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0450_CKGEN01 (ckgen01 + 0x450)
    #define REG_0450_CKGEN01_REG_CKG_P0_PIX_DC_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0458_CKGEN01 (ckgen01 + 0x458)
    #define REG_0458_CKGEN01_REG_CKG_P0_PIX_RCV_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0460_CKGEN01 (ckgen01 + 0x460)
    #define REG_0460_CKGEN01_REG_CKG_P0_PIX_REP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0468_CKGEN01 (ckgen01 + 0x468)
    #define REG_0468_CKGEN01_REG_CKG_P0_PIX_TMDSPLL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0478_CKGEN01 (ckgen01 + 0x478)
    #define REG_0478_CKGEN01_REG_CKG_P0_PIX_XC_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0480_CKGEN01 (ckgen01 + 0x480)
    #define REG_0480_CKGEN01_REG_CKG_P0_TIMING_DET_DEC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0488_CKGEN01 (ckgen01 + 0x488)
    #define REG_0488_CKGEN01_REG_CKG_P0_TIMING_DET_DEP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0490_CKGEN01 (ckgen01 + 0x490)
    #define REG_0490_CKGEN01_REG_CKG_P0_TIMING_DET_DTOP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0498_CKGEN01 (ckgen01 + 0x498)
    #define REG_0498_CKGEN01_REG_CKG_P0_TMDS_FRL_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04A0_CKGEN01 (ckgen01 + 0x4A0)
    #define REG_04A0_CKGEN01_REG_CKG_P0_TMDS_HDCP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04A8_CKGEN01 (ckgen01 + 0x4A8)
    #define REG_04A8_CKGEN01_REG_CKG_P0_TMDS_HDCP_4P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04B0_CKGEN01 (ckgen01 + 0x4B0)
    #define REG_04B0_CKGEN01_REG_CKG_P0_TMDS_HDCP_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04B8_CKGEN01 (ckgen01 + 0x4B8)
    #define REG_04B8_CKGEN01_REG_CKG_P0_TMDS_HDCP_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04C0_CKGEN01 (ckgen01 + 0x4C0)
    #define REG_04C0_CKGEN01_REG_CKG_P0_TMDS_HDMI_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04C8_CKGEN01 (ckgen01 + 0x4C8)
    #define REG_04C8_CKGEN01_REG_CKG_P0_TMDS_HDMI_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04D0_CKGEN01 (ckgen01 + 0x4D0)
    #define REG_04D0_CKGEN01_REG_CKG_P0_TMDS_HDMI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04D8_CKGEN01 (ckgen01 + 0x4D8)
    #define REG_04D8_CKGEN01_REG_CKG_P1_CLK_DET_DEC_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04E0_CKGEN01 (ckgen01 + 0x4E0)
    #define REG_04E0_CKGEN01_REG_CKG_P1_CLK_DET_DEC_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04E8_CKGEN01 (ckgen01 + 0x4E8)
    #define REG_04E8_CKGEN01_REG_CKG_P1_CLK_DET_DEC_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04F0_CKGEN01 (ckgen01 + 0x4F0)
    #define REG_04F0_CKGEN01_REG_CKG_P1_CLK_DET_DEC_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_04F8_CKGEN01 (ckgen01 + 0x4F8)
    #define REG_04F8_CKGEN01_REG_CKG_P1_CLK_DET_DEP_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0500_CKGEN01 (ckgen01 + 0x500)
    #define REG_0500_CKGEN01_REG_CKG_P1_CLK_DET_DEP_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0508_CKGEN01 (ckgen01 + 0x508)
    #define REG_0508_CKGEN01_REG_CKG_P1_CLK_DET_DEP_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0510_CKGEN01 (ckgen01 + 0x510)
    #define REG_0510_CKGEN01_REG_CKG_P1_CLK_DET_DEP_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0518_CKGEN01 (ckgen01 + 0x518)
    #define REG_0518_CKGEN01_REG_CKG_P1_LINK Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0520_CKGEN01 (ckgen01 + 0x520)
    #define REG_0520_CKGEN01_REG_CKG_P1_PIX_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0528_CKGEN01 (ckgen01 + 0x528)
    #define REG_0528_CKGEN01_REG_CKG_P1_PIX_8P Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0530_CKGEN01 (ckgen01 + 0x530)
    #define REG_0530_CKGEN01_REG_CKG_P1_PIX_DC_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0538_CKGEN01 (ckgen01 + 0x538)
    #define REG_0538_CKGEN01_REG_CKG_P1_PIX_RCV_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0540_CKGEN01 (ckgen01 + 0x540)
    #define REG_0540_CKGEN01_REG_CKG_P1_PIX_REP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0548_CKGEN01 (ckgen01 + 0x548)
    #define REG_0548_CKGEN01_REG_CKG_P1_PIX_TMDSPLL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0558_CKGEN01 (ckgen01 + 0x558)
    #define REG_0558_CKGEN01_REG_CKG_P1_PIX_XC_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0560_CKGEN01 (ckgen01 + 0x560)
    #define REG_0560_CKGEN01_REG_CKG_P1_TIMING_DET_DEC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0568_CKGEN01 (ckgen01 + 0x568)
    #define REG_0568_CKGEN01_REG_CKG_P1_TIMING_DET_DEP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0570_CKGEN01 (ckgen01 + 0x570)
    #define REG_0570_CKGEN01_REG_CKG_P1_TIMING_DET_DTOP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0578_CKGEN01 (ckgen01 + 0x578)
    #define REG_0578_CKGEN01_REG_CKG_P1_TMDS_FRL_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0580_CKGEN01 (ckgen01 + 0x580)
    #define REG_0580_CKGEN01_REG_CKG_P1_TMDS_HDCP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0588_CKGEN01 (ckgen01 + 0x588)
    #define REG_0588_CKGEN01_REG_CKG_P1_TMDS_HDCP_4P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0590_CKGEN01 (ckgen01 + 0x590)
    #define REG_0590_CKGEN01_REG_CKG_P1_TMDS_HDCP_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0598_CKGEN01 (ckgen01 + 0x598)
    #define REG_0598_CKGEN01_REG_CKG_P1_TMDS_HDCP_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05A0_CKGEN01 (ckgen01 + 0x5A0)
    #define REG_05A0_CKGEN01_REG_CKG_P1_TMDS_HDMI_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05A8_CKGEN01 (ckgen01 + 0x5A8)
    #define REG_05A8_CKGEN01_REG_CKG_P1_TMDS_HDMI_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05B0_CKGEN01 (ckgen01 + 0x5B0)
    #define REG_05B0_CKGEN01_REG_CKG_P1_TMDS_HDMI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05B8_CKGEN01 (ckgen01 + 0x5B8)
    #define REG_05B8_CKGEN01_REG_CKG_P2_CLK_DET_DEC_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05C0_CKGEN01 (ckgen01 + 0x5C0)
    #define REG_05C0_CKGEN01_REG_CKG_P2_CLK_DET_DEC_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05C8_CKGEN01 (ckgen01 + 0x5C8)
    #define REG_05C8_CKGEN01_REG_CKG_P2_CLK_DET_DEC_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05D0_CKGEN01 (ckgen01 + 0x5D0)
    #define REG_05D0_CKGEN01_REG_CKG_P2_CLK_DET_DEC_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05D8_CKGEN01 (ckgen01 + 0x5D8)
    #define REG_05D8_CKGEN01_REG_CKG_P2_CLK_DET_DEP_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]

//Page CKGEN01_2
#define REG_05E0_CKGEN01 (ckgen01 + 0x5E0)
    #define REG_05E0_CKGEN01_REG_CKG_P2_CLK_DET_DEP_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05E8_CKGEN01 (ckgen01 + 0x5E8)
    #define REG_05E8_CKGEN01_REG_CKG_P2_CLK_DET_DEP_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05F0_CKGEN01 (ckgen01 + 0x5F0)
    #define REG_05F0_CKGEN01_REG_CKG_P2_CLK_DET_DEP_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_05F8_CKGEN01 (ckgen01 + 0x5F8)
    #define REG_05F8_CKGEN01_REG_CKG_P2_LINK Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0600_CKGEN01 (ckgen01 + 0x600)
    #define REG_0600_CKGEN01_REG_CKG_P2_PIX_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0608_CKGEN01 (ckgen01 + 0x608)
    #define REG_0608_CKGEN01_REG_CKG_P2_PIX_8P Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0610_CKGEN01 (ckgen01 + 0x610)
    #define REG_0610_CKGEN01_REG_CKG_P2_PIX_DC_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0618_CKGEN01 (ckgen01 + 0x618)
    #define REG_0618_CKGEN01_REG_CKG_P2_PIX_RCV_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0620_CKGEN01 (ckgen01 + 0x620)
    #define REG_0620_CKGEN01_REG_CKG_P2_PIX_REP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0628_CKGEN01 (ckgen01 + 0x628)
    #define REG_0628_CKGEN01_REG_CKG_P2_PIX_TMDSPLL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0638_CKGEN01 (ckgen01 + 0x638)
    #define REG_0638_CKGEN01_REG_CKG_P2_PIX_XC_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0640_CKGEN01 (ckgen01 + 0x640)
    #define REG_0640_CKGEN01_REG_CKG_P2_TIMING_DET_DEC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0648_CKGEN01 (ckgen01 + 0x648)
    #define REG_0648_CKGEN01_REG_CKG_P2_TIMING_DET_DEP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0650_CKGEN01 (ckgen01 + 0x650)
    #define REG_0650_CKGEN01_REG_CKG_P2_TIMING_DET_DTOP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0658_CKGEN01 (ckgen01 + 0x658)
    #define REG_0658_CKGEN01_REG_CKG_P2_TMDS_FRL_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0660_CKGEN01 (ckgen01 + 0x660)
    #define REG_0660_CKGEN01_REG_CKG_P2_TMDS_HDCP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0668_CKGEN01 (ckgen01 + 0x668)
    #define REG_0668_CKGEN01_REG_CKG_P2_TMDS_HDCP_4P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0670_CKGEN01 (ckgen01 + 0x670)
    #define REG_0670_CKGEN01_REG_CKG_P2_TMDS_HDCP_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0678_CKGEN01 (ckgen01 + 0x678)
    #define REG_0678_CKGEN01_REG_CKG_P2_TMDS_HDCP_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0680_CKGEN01 (ckgen01 + 0x680)
    #define REG_0680_CKGEN01_REG_CKG_P2_TMDS_HDMI_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0688_CKGEN01 (ckgen01 + 0x688)
    #define REG_0688_CKGEN01_REG_CKG_P2_TMDS_HDMI_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0690_CKGEN01 (ckgen01 + 0x690)
    #define REG_0690_CKGEN01_REG_CKG_P2_TMDS_HDMI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0698_CKGEN01 (ckgen01 + 0x698)
    #define REG_0698_CKGEN01_REG_CKG_P3_CLK_DET_DEC_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06A0_CKGEN01 (ckgen01 + 0x6A0)
    #define REG_06A0_CKGEN01_REG_CKG_P3_CLK_DET_DEC_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06A8_CKGEN01 (ckgen01 + 0x6A8)
    #define REG_06A8_CKGEN01_REG_CKG_P3_CLK_DET_DEC_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06B0_CKGEN01 (ckgen01 + 0x6B0)
    #define REG_06B0_CKGEN01_REG_CKG_P3_CLK_DET_DEC_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06B8_CKGEN01 (ckgen01 + 0x6B8)
    #define REG_06B8_CKGEN01_REG_CKG_P3_CLK_DET_DEP_MISC_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06C0_CKGEN01 (ckgen01 + 0x6C0)
    #define REG_06C0_CKGEN01_REG_CKG_P3_CLK_DET_DEP_MISC_0_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06C8_CKGEN01 (ckgen01 + 0x6C8)
    #define REG_06C8_CKGEN01_REG_CKG_P3_CLK_DET_DEP_MISC_1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06D0_CKGEN01 (ckgen01 + 0x6D0)
    #define REG_06D0_CKGEN01_REG_CKG_P3_CLK_DET_DEP_MISC_1_0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06D8_CKGEN01 (ckgen01 + 0x6D8)
    #define REG_06D8_CKGEN01_REG_CKG_P3_LINK Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06E0_CKGEN01 (ckgen01 + 0x6E0)
    #define REG_06E0_CKGEN01_REG_CKG_P3_PIX_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_06E8_CKGEN01 (ckgen01 + 0x6E8)
    #define REG_06E8_CKGEN01_REG_CKG_P3_PIX_8P Fld(5,0,AC_MSKB0)//[4:0]
#define REG_06F0_CKGEN01 (ckgen01 + 0x6F0)
    #define REG_06F0_CKGEN01_REG_CKG_P3_PIX_DC_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_06F8_CKGEN01 (ckgen01 + 0x6F8)
    #define REG_06F8_CKGEN01_REG_CKG_P3_PIX_RCV_MUX Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0700_CKGEN01 (ckgen01 + 0x700)
    #define REG_0700_CKGEN01_REG_CKG_P3_PIX_REP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0708_CKGEN01 (ckgen01 + 0x708)
    #define REG_0708_CKGEN01_REG_CKG_P3_PIX_TMDSPLL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0718_CKGEN01 (ckgen01 + 0x718)
    #define REG_0718_CKGEN01_REG_CKG_P3_PIX_XC_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0720_CKGEN01 (ckgen01 + 0x720)
    #define REG_0720_CKGEN01_REG_CKG_P3_TIMING_DET_DEC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0728_CKGEN01 (ckgen01 + 0x728)
    #define REG_0728_CKGEN01_REG_CKG_P3_TIMING_DET_DEP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0730_CKGEN01 (ckgen01 + 0x730)
    #define REG_0730_CKGEN01_REG_CKG_P3_TIMING_DET_DTOP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0738_CKGEN01 (ckgen01 + 0x738)
    #define REG_0738_CKGEN01_REG_CKG_P3_TMDS_FRL_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0740_CKGEN01 (ckgen01 + 0x740)
    #define REG_0740_CKGEN01_REG_CKG_P3_TMDS_HDCP_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0748_CKGEN01 (ckgen01 + 0x748)
    #define REG_0748_CKGEN01_REG_CKG_P3_TMDS_HDCP_4P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0750_CKGEN01 (ckgen01 + 0x750)
    #define REG_0750_CKGEN01_REG_CKG_P3_TMDS_HDCP_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0758_CKGEN01 (ckgen01 + 0x758)
    #define REG_0758_CKGEN01_REG_CKG_P3_TMDS_HDCP_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0760_CKGEN01 (ckgen01 + 0x760)
    #define REG_0760_CKGEN01_REG_CKG_P3_TMDS_HDMI_1P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0768_CKGEN01 (ckgen01 + 0x768)
    #define REG_0768_CKGEN01_REG_CKG_P3_TMDS_HDMI_8P Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0770_CKGEN01 (ckgen01 + 0x770)
    #define REG_0770_CKGEN01_REG_CKG_P3_TMDS_HDMI_MUX Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0778_CKGEN01 (ckgen01 + 0x778)
    #define REG_0778_CKGEN01_REG_CKG_PIX_TMDSPLL_DSCD Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0780_CKGEN01 (ckgen01 + 0x780)
    #define REG_0780_CKGEN01_REG_CKG_PIX_XC_S0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0788_CKGEN01 (ckgen01 + 0x788)
    #define REG_0788_CKGEN01_REG_CKG_PIX_XC_S1 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0790_CKGEN01 (ckgen01 + 0x790)
    #define REG_0790_CKGEN01_REG_CKG_R2_HDMI Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0798_CKGEN01 (ckgen01 + 0x798)
    #define REG_0798_CKGEN01_REG_CKG_TIMING_DET_DTOP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_07A0_CKGEN01 (ckgen01 + 0x7A0)
    #define REG_07A0_CKGEN01_REG_CKG_TMDS_AUDIO_S0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_07A8_CKGEN01 (ckgen01 + 0x7A8)
    #define REG_07A8_CKGEN01_REG_CKG_TMDS_AUDIO_S0_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_07B0_CKGEN01 (ckgen01 + 0x7B0)
    #define REG_07B0_CKGEN01_REG_CKG_TMDS_AUDIO_S1 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_07B8_CKGEN01 (ckgen01 + 0x7B8)
    #define REG_07B8_CKGEN01_REG_CKG_TMDS_AUDIO_S1_0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_07C0_CKGEN01 (ckgen01 + 0x7C0)
    #define REG_07C0_CKGEN01_REG_CKG_TMDS_DSCD Fld(5,0,AC_MSKB0)//[4:0]
#define REG_07C8_CKGEN01 (ckgen01 + 0x7C8)
    #define REG_07C8_CKGEN01_REG_CKG_XTAL_24 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_07D0_CKGEN01 (ckgen01 + 0x7D0)
    #define REG_07D0_CKGEN01_REG_CKG_XTAL_HDMI_12 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_07D8_CKGEN01 (ckgen01 + 0x7D8)
    #define REG_07D8_CKGEN01_REG_CKG_P0_TMDSPLL_TEST_DIG Fld(4,0,AC_MSKB0)//[3:0]
#define REG_07E0_CKGEN01 (ckgen01 + 0x7E0)
    #define REG_07E0_CKGEN01_REG_CKG_P1_TMDSPLL_TEST_DIG Fld(4,0,AC_MSKB0)//[3:0]
#define REG_07E8_CKGEN01 (ckgen01 + 0x7E8)
    #define REG_07E8_CKGEN01_REG_CKG_P2_TMDSPLL_TEST_DIG Fld(4,0,AC_MSKB0)//[3:0]
#define REG_07F0_CKGEN01 (ckgen01 + 0x7F0)
    #define REG_07F0_CKGEN01_REG_CKG_P3_TMDSPLL_TEST_DIG Fld(4,0,AC_MSKB0)//[3:0]
#define REG_07F8_CKGEN01 (ckgen01 + 0x7F8)
    #define REG_07F8_CKGEN01_REG_CKG_128FS_FB_S0_FF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0800_CKGEN01 (ckgen01 + 0x800)
    #define REG_0800_CKGEN01_REG_CKG_128FS_FB_S1_FF Fld(4,0,AC_MSKB0)//[3:0]
#define REG_08E0_CKGEN01 (ckgen01 + 0x8E0)
    #define REG_08E0_CKGEN01_REG_CKG_DET_RCLK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_08E8_CKGEN01 (ckgen01 + 0x8E8)
    #define REG_08E8_CKGEN01_REG_CKG_DET_WCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_08F0_CKGEN01 (ckgen01 + 0x8F0)
    #define REG_08F0_CKGEN01_REG_CKG_LPLL_ODCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_08F8_CKGEN01 (ckgen01 + 0x8F8)
    #define REG_08F8_CKGEN01_REG_CKG_LPLL_ODCLK_NODIV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0900_CKGEN01 (ckgen01 + 0x900)
    #define REG_0900_CKGEN01_REG_CKG_LPLL_SYN_432 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0908_CKGEN01 (ckgen01 + 0x908)
    #define REG_0908_CKGEN01_REG_CKG_LPLL_SYN_864 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0910_CKGEN01 (ckgen01 + 0x910)
    #define REG_0910_CKGEN01_REG_CKG_MOD_A_ODCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0918_CKGEN01 (ckgen01 + 0x918)
    #define REG_0918_CKGEN01_REG_CKG_MOD_D_ODCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_091C_CKGEN01 (ckgen01 + 0x91C)
    #define REG_091C_CKGEN01_REG_CKG_MOD_O_SR_WCLK Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0920_CKGEN01 (ckgen01 + 0x920)
    #define REG_0920_CKGEN01_REG_CKG_MOD_V1_SR_WCLK Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0924_CKGEN01 (ckgen01 + 0x924)
    #define REG_0924_CKGEN01_REG_CKG_MOD_V2_SR_WCLK Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0928_CKGEN01 (ckgen01 + 0x928)
    #define REG_0928_CKGEN01_REG_CKG_O_MOD_SR_RCLK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0930_CKGEN01 (ckgen01 + 0x930)
    #define REG_0930_CKGEN01_REG_CKG_O_ODCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0938_CKGEN01 (ckgen01 + 0x938)
    #define REG_0938_CKGEN01_REG_CKG_O_ODCLK_STG1 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0940_CKGEN01 (ckgen01 + 0x940)
    #define REG_0940_CKGEN01_REG_CKG_O_ODCLK_STG2 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0948_CKGEN01 (ckgen01 + 0x948)
    #define REG_0948_CKGEN01_REG_CKG_O_ODCLK_STG3 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0950_CKGEN01 (ckgen01 + 0x950)
    #define REG_0950_CKGEN01_REG_CKG_O_ODCLK_STG4 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0958_CKGEN01 (ckgen01 + 0x958)
    #define REG_0958_CKGEN01_REG_CKG_O_ODCLK_STG5 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0960_CKGEN01 (ckgen01 + 0x960)
    #define REG_0960_CKGEN01_REG_CKG_O_ODCLK_STG6 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0968_CKGEN01 (ckgen01 + 0x968)
    #define REG_0968_CKGEN01_REG_CKG_PWM Fld(7,0,AC_MSKB0)//[6:0]
#define REG_0970_CKGEN01 (ckgen01 + 0x970)
    #define REG_0970_CKGEN01_REG_CKG_V1_MOD_SR_RCLK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0978_CKGEN01 (ckgen01 + 0x978)
    #define REG_0978_CKGEN01_REG_CKG_V1_ODCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0980_CKGEN01 (ckgen01 + 0x980)
    #define REG_0980_CKGEN01_REG_CKG_V1_ODCLK_STG1 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0988_CKGEN01 (ckgen01 + 0x988)
    #define REG_0988_CKGEN01_REG_CKG_V1_ODCLK_STG2 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0990_CKGEN01 (ckgen01 + 0x990)
    #define REG_0990_CKGEN01_REG_CKG_V1_ODCLK_STG3 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0998_CKGEN01 (ckgen01 + 0x998)
    #define REG_0998_CKGEN01_REG_CKG_V1_ODCLK_STG4 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09A0_CKGEN01 (ckgen01 + 0x9A0)
    #define REG_09A0_CKGEN01_REG_CKG_V1_ODCLK_STG5 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09A8_CKGEN01 (ckgen01 + 0x9A8)
    #define REG_09A8_CKGEN01_REG_CKG_V1_ODCLK_STG6 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09B0_CKGEN01 (ckgen01 + 0x9B0)
    #define REG_09B0_CKGEN01_REG_CKG_V1_ODCLK_STG7 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09B8_CKGEN01 (ckgen01 + 0x9B8)
    #define REG_09B8_CKGEN01_REG_CKG_V1_ODCLK_STG8 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09C0_CKGEN01 (ckgen01 + 0x9C0)
    #define REG_09C0_CKGEN01_REG_CKG_V2_MOD_SR_RCLK Fld(3,0,AC_MSKB0)//[2:0]
#define REG_09C8_CKGEN01 (ckgen01 + 0x9C8)
    #define REG_09C8_CKGEN01_REG_CKG_V2_ODCLK Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09D0_CKGEN01 (ckgen01 + 0x9D0)
    #define REG_09D0_CKGEN01_REG_CKG_V2_ODCLK_STG1 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09D8_CKGEN01 (ckgen01 + 0x9D8)
    #define REG_09D8_CKGEN01_REG_CKG_V2_ODCLK_STG2 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09E0_CKGEN01 (ckgen01 + 0x9E0)
    #define REG_09E0_CKGEN01_REG_CKG_V2_ODCLK_STG3 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09E8_CKGEN01 (ckgen01 + 0x9E8)
    #define REG_09E8_CKGEN01_REG_CKG_V2_ODCLK_STG4 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09F0_CKGEN01 (ckgen01 + 0x9F0)
    #define REG_09F0_CKGEN01_REG_CKG_V2_ODCLK_STG5 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_09F8_CKGEN01 (ckgen01 + 0x9F8)
    #define REG_09F8_CKGEN01_REG_CKG_V2_ODCLK_STG6 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0A00_CKGEN01 (ckgen01 + 0xA00)
    #define REG_0A00_CKGEN01_REG_CKG_V2_ODCLK_STG7 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0A08_CKGEN01 (ckgen01 + 0xA08)
    #define REG_0A08_CKGEN01_REG_CKG_O_MOD_SR_RCLK_FINIAL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A10_CKGEN01 (ckgen01 + 0xA10)
    #define REG_0A10_CKGEN01_REG_CKG_O_MOD_SR_RCLK_PRE0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A18_CKGEN01 (ckgen01 + 0xA18)
    #define REG_0A18_CKGEN01_REG_CKG_O_MOD_SR_RCLK_PRE1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A20_CKGEN01 (ckgen01 + 0xA20)
    #define REG_0A20_CKGEN01_REG_CKG_V1_MOD_SR_RCLK_FINIAL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A28_CKGEN01 (ckgen01 + 0xA28)
    #define REG_0A28_CKGEN01_REG_CKG_V1_MOD_SR_RCLK_PRE0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A30_CKGEN01 (ckgen01 + 0xA30)
    #define REG_0A30_CKGEN01_REG_CKG_V1_MOD_SR_RCLK_PRE1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A38_CKGEN01 (ckgen01 + 0xA38)
    #define REG_0A38_CKGEN01_REG_CKG_V2_MOD_SR_RCLK_FINIAL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A40_CKGEN01 (ckgen01 + 0xA40)
    #define REG_0A40_CKGEN01_REG_CKG_V2_MOD_SR_RCLK_PRE0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A48_CKGEN01 (ckgen01 + 0xA48)
    #define REG_0A48_CKGEN01_REG_CKG_V2_MOD_SR_RCLK_PRE1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A50_CKGEN01 (ckgen01 + 0x050)
    #define REG_0A50_CKGEN01_REG_CKG_IDCLK_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0A58_CKGEN01 (ckgen01 + 0xA58)
    #define REG_0A58_CKGEN01_REG_CKG_V1_ODCLK_STG9 Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0A60_CKGEN01 (ckgen01 + 0xA60)
    #define REG_0A60_CKGEN01_REG_CKG_XTAL_12M_MOD Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A68_CKGEN01 (ckgen01 + 0xA68)
    #define REG_0A68_CKGEN01_REG_CKG_XTAL_24M_MOD Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A7C_CKGEN01 (ckgen01 + 0xA7C)
    #define REG_0A7C_CKGEN01_REG_CKG_XC_OD_DELTA_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0A80_CKGEN01 (ckgen01 + 0xA80)
    #define REG_0A80_CKGEN01_REG_CKG_XC_OD_DELTA_SCSCL Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0A80_CKGEN01_REG_CKG_XC_OD_SCSCL Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0A84_CKGEN01 (ckgen01 + 0xA84)
    #define REG_0A84_CKGEN01_REG_CKG_V1_ODCLK_SCSCL Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0A84_CKGEN01_REG_CKG_V2_ODCLK_SCSCL Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0A88_CKGEN01 (ckgen01 + 0xA88)
    #define REG_0A88_CKGEN01_REG_V1_V2_O_ODCLK_FROM_MOD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0A8C_CKGEN01 (ckgen01 + 0xA8C)
    #define REG_0A8C_CKGEN01_REG_CKG_V1_ODCLK_SCIP Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0A8C_CKGEN01_REG_CKG_V2_ODCLK_SCIP Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0A90_CKGEN01 (ckgen01 + 0xA90)
    #define REG_0A90_CKGEN01_REG_CKG_V1_ODCLK_SCTCON Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0A90_CKGEN01_REG_CKG_V1_ODCLK_SCDISP_0A90 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0A94_CKGEN01 (ckgen01 + 0xA94)
    #define REG_0A94_CKGEN01_REG_CKG_V1_ODCLK_SCMW Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0A94_CKGEN01_REG_CKG_V1_ODCLK_SCPQ_0A94 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0A98_CKGEN01 (ckgen01 + 0xA98)
    #define REG_0A98_CKGEN01_REG_CKG_V2_ODCLK_SCTCON Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0A9C_CKGEN01 (ckgen01 + 0xA9C)
    #define REG_0A9C_CKGEN01_REG_CKG_O_ODCLK_SCTCON Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0AA0_CKGEN01 (ckgen01 + 0xAA0)
    #define REG_0AA0_CKGEN01_REG_CKG_XC_DC0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0AA4_CKGEN01 (ckgen01 + 0xAA4)
    #define REG_0AA4_CKGEN01_REG_CKG_XC_SUB1_DC0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0AA8_CKGEN01 (ckgen01 + 0xAA8)
    #define REG_0AA8_CKGEN01_REG_CKG_XC_SUB_DC0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0AAC_CKGEN01 (ckgen01 + 0xAAC)
    #define REG_0AAC_CKGEN01_REG_CKG_XC_VEIN_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0AB0_CKGEN01 (ckgen01 + 0xAB0)
    #define REG_0AB0_CKGEN01_REG_CKG_XC_B2R Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0AB4_CKGEN01 (ckgen01 + 0xAB4)
    #define REG_0AB4_CKGEN01_REG_CKG_XC_OD_META_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0AB8_CKGEN01 (ckgen01 + 0xAB8)
    #define REG_0AB8_CKGEN01_REG_CKG_XC_B2R_SUB Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0ABC_CKGEN01 (ckgen01 + 0xABC)
    #define REG_0ABC_CKGEN01_REG_CKG_XC_OD_DELTA_META_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0AC0_CKGEN01 (ckgen01 + 0xAC0)
    #define REG_0AC0_CKGEN01_REG_CKG_XC_ED Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0AC4_CKGEN01 (ckgen01 + 0xAC4)
    #define REG_0AC4_CKGEN01_REG_CKG_XC_OD_OSD_META_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0AC8_CKGEN01 (ckgen01 + 0xAC8)
    #define REG_0AC8_CKGEN01_REG_CKG_XC_FD Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0AC8_CKGEN01_REG_CKG_XC_FD_SCIP Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0AC8_CKGEN01_REG_CKG_XC_FD_SCSCL Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0ACC_CKGEN01 (ckgen01 + 0xACC)
    #define REG_0ACC_CKGEN01_REG_CKG_V1_META_ODCLK_SCTCON Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0AD0_CKGEN01 (ckgen01 + 0xAD0)
    #define REG_0AD0_CKGEN01_REG_CKG_XC_FN Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0AD4_CKGEN01 (ckgen01 + 0xAD4)
    #define REG_0AD4_CKGEN01_REG_CKG_V2_META_ODCLK_SCTCON Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0AD8_CKGEN01 (ckgen01 + 0xAD8)
    #define REG_0AD8_CKGEN01_REG_CKG_XC_FS Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0AD8_CKGEN01_REG_CKG_XC_FS_SCIP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0ADC_CKGEN01 (ckgen01 + 0xADC)
    #define REG_0ADC_CKGEN01_REG_CKG_O_META_ODCLK_SCTCON Fld(6,0,AC_MSKB0)//[5:0]
#define REG_0AE0_CKGEN01 (ckgen01 + 0xAE0)
    #define REG_0AE0_CKGEN01_REG_CKG_XC_OD Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0AE0_CKGEN01_REG_CKG_XC_OD_SCIP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0AE8_CKGEN01 (ckgen01 + 0xAE8)
    #define REG_0AE8_CKGEN01_REG_CKG_XC_SLOW Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0AF0_CKGEN01 (ckgen01 + 0xAF0)
    #define REG_0AF0_CKGEN01_REG_CKG_XC_SRS Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0AF8_CKGEN01 (ckgen01 + 0xAF8)
    #define REG_0AF8_CKGEN01_REG_CKG_XC_FS_SCACE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B00_CKGEN01 (ckgen01 + 0xB00)
    #define REG_0B00_CKGEN01_REG_CKG_XTAL_12M_SCACE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B08_CKGEN01 (ckgen01 + 0xB08)
    #define REG_0B08_CKGEN01_REG_CKG_XTAL_24M_SCACE Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B10_CKGEN01 (ckgen01 + 0xB10)
    #define REG_0B10_CKGEN01_REG_CKG_XC_DC0_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B18_CKGEN01 (ckgen01 + 0xB18)
    #define REG_0B18_CKGEN01_REG_CKG_XC_DBG2MIU_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0B20_CKGEN01 (ckgen01 + 0xB20)
    #define REG_0B20_CKGEN01_REG_CKG_XC_ED0_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B28_CKGEN01 (ckgen01 + 0xB28)
    #define REG_0B28_CKGEN01_REG_CKG_XC_ED1_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B30_CKGEN01 (ckgen01 + 0xB30)
    #define REG_0B30_CKGEN01_REG_CKG_XC_FN_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B38_CKGEN01 (ckgen01 + 0xB38)
    #define REG_0B38_CKGEN01_REG_CKG_XC_ID0_SCIP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B40_CKGEN01 (ckgen01 + 0xB40)
    #define REG_0B40_CKGEN01_REG_CKG_XC_ID1_SCIP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0B48_CKGEN01 (ckgen01 + 0xB48)
    #define REG_0B48_CKGEN01_REG_CKG_XTAL_24M_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B50_CKGEN01 (ckgen01 + 0xB50)
    #define REG_0B50_CKGEN01_REG_CKG_XTAL_12M_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B58_CKGEN01 (ckgen01 + 0xB58)
    #define REG_0B58_CKGEN01_REG_CKG_XTAL_IP1_SCIP Fld(4,0,AC_MSKB0)//[3:0]

//Page CKGEN01_3
#define REG_0B60_CKGEN01 (ckgen01 + 0xB60)
    #define REG_0B60_CKGEN01_REG_CKG_XC_FD_SCMW Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B68_CKGEN01 (ckgen01 + 0xB68)
    #define REG_0B68_CKGEN01_REG_CKG_XC_FN_SCMW Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B70_CKGEN01 (ckgen01 + 0xB70)
    #define REG_0B70_CKGEN01_REG_CKG_XC_FS_SCMW Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B78_CKGEN01 (ckgen01 + 0xB78)
    #define REG_0B78_CKGEN01_REG_CKG_XC_OD_SCMW Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B80_CKGEN01 (ckgen01 + 0xB80)
    #define REG_0B80_CKGEN01_REG_CKG_XTAL_24M_SCMW Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B84_CKGEN01 (ckgen01 + 0xB84)
    #define REG_0B84_CKGEN01_REG_CKG_XTAL_12M_SCMW_0B84 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B88_CKGEN01 (ckgen01 + 0xB88)
    #define REG_0B88_CKGEN01_REG_CKG_XC_FN_SCNR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0B98_CKGEN01 (ckgen01 + 0xB98)
    #define REG_0B98_CKGEN01_REG_CKG_XTAL_24M_SCNR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BA0_CKGEN01 (ckgen01 + 0xBA0)
    #define REG_0BA0_CKGEN01_REG_CKG_XC_FN_SCPQ Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0BA0_CKGEN01_REG_CKG_XC_OD_SCPQ_0BA0 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_0BA0_CKGEN01_REG_CKG_XC_FS_SCPQ_0BA0 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_0BA0_CKGEN01_REG_CKG_XC_FD_SCPQ_0BA0 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_0BA8_CKGEN01 (ckgen01 + 0xBA8)
    #define REG_0BA8_CKGEN01_REG_CKG_XTAL_24M_SCPQ Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BB0_CKGEN01 (ckgen01 + 0xBB0)
    #define REG_0BB0_CKGEN01_REG_CKG_XC_FN_SCSCL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BB8_CKGEN01 (ckgen01 + 0xBB8)
    #define REG_0BB8_CKGEN01_REG_CKG_XC_FS_SCSCL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BC0_CKGEN01 (ckgen01 + 0xBC0)
    #define REG_0BC0_CKGEN01_REG_CKG_XTAL_12M_SCSCL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BC8_CKGEN01 (ckgen01 + 0xBC8)
    #define REG_0BC8_CKGEN01_REG_CKG_XTAL_24M_SCSCL Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BD0_CKGEN01 (ckgen01 + 0xBD0)
    #define REG_0BD0_CKGEN01_REG_CKG_XC_FS_SCSR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BD8_CKGEN01 (ckgen01 + 0xBD8)
    #define REG_0BD8_CKGEN01_REG_CKG_XC_SR_ALAI_SCSR Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0BE0_CKGEN01 (ckgen01 + 0xBE0)
    #define REG_0BE0_CKGEN01_REG_CKG_XC_SR_SRAM_SHARE_SCSR Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0BE8_CKGEN01 (ckgen01 + 0xBE8)
    #define REG_0BE8_CKGEN01_REG_CKG_XC_SRS_SCSR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BF0_CKGEN01 (ckgen01 + 0xBF0)
    #define REG_0BF0_CKGEN01_REG_CKG_XTAL_12M_SCSR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0BF8_CKGEN01 (ckgen01 + 0xBF8)
    #define REG_0BF8_CKGEN01_REG_CKG_XTAL_24M_SCSR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0C00_CKGEN01 (ckgen01 + 0xC00)
    #define REG_0C00_CKGEN01_REG_CKG_XC_FD_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0C00_CKGEN01_REG_CKG_XC_FD_SCDISP_0C00 Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0C08_CKGEN01 (ckgen01 + 0xC08)
    #define REG_0C08_CKGEN01_REG_CKG_XC_FN_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C08_CKGEN01_REG_CKG_XC_FN_SCDISP_0C08 Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0C10_CKGEN01 (ckgen01 + 0xC10)
    #define REG_0C10_CKGEN01_REG_CKG_XC_OD_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0C18_CKGEN01 (ckgen01 + 0xC18)
    #define REG_0C18_CKGEN01_REG_CKG_XTAL_12M_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C18_CKGEN01_REG_CKG_XTAL_12M_SCDISP_0C18 Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0C20_CKGEN01 (ckgen01 + 0xC20)
    #define REG_0C20_CKGEN01_REG_CKG_XTAL_24M_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0C20_CKGEN01_REG_CKG_XTAL_24M_SCDISP_0C20 Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0C28_CKGEN01 (ckgen01 + 0xC28)
    #define REG_0C28_CKGEN01_REG_CKG_XC_FN_SCDV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0C30_CKGEN01 (ckgen01 + 0xC30)
    #define REG_0C30_CKGEN01_REG_CKG_XTAL_12M_SCDV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0C38_CKGEN01 (ckgen01 + 0xC38)
    #define REG_0C38_CKGEN01_REG_CKG_XTAL_24M_SCDV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0C40_CKGEN01 (ckgen01 + 0xC40)
    #define REG_0C40_CKGEN01_REG_CKG_XCPLL_SYN Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0C48_CKGEN01 (ckgen01 + 0xC48)
    #define REG_0C48_CKGEN01_REG_CKG_DELTA_B2P2_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C50_CKGEN01 (ckgen01 + 0xC50)
    #define REG_0C50_CKGEN01_REG_CKG_GUCD_18_LUT2_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C58_CKGEN01 (ckgen01 + 0xC58)
    #define REG_0C58_CKGEN01_REG_CKG_GUCD_256_LUT2_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C60_CKGEN01 (ckgen01 + 0xC60)
    #define REG_0C60_CKGEN01_REG_CKG_HSY_8P3_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C68_CKGEN01 (ckgen01 + 0xC68)
    #define REG_0C68_CKGEN01_REG_CKG_HSY_8P_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C6C_CKGEN01 (ckgen01 + 0xC6C)
    #define REG_0C6C_CKGEN01_REG_CKG_DIP1_HVSP_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C70_CKGEN01 (ckgen01 + 0xC70)
    #define REG_0C70_CKGEN01_REG_CKG_LCE_ACE_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C74_CKGEN01 (ckgen01 + 0xC74)
    #define REG_0C74_CKGEN01_REG_CKG_DIP1_XVYCC_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C78_CKGEN01 (ckgen01 + 0xC78)
    #define REG_0C78_CKGEN01_REG_CKG_PQ_GAMMA_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C80_CKGEN01 (ckgen01 + 0xC80)
    #define REG_0C80_CKGEN01_REG_CKG_RGB_3DLUT_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C88_CKGEN01 (ckgen01 + 0xC88)
    #define REG_0C88_CKGEN01_REG_CKG_VIP_ACE_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C90_CKGEN01 (ckgen01 + 0xC90)
    #define REG_0C90_CKGEN01_REG_CKG_XVYCC_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0C98_CKGEN01 (ckgen01 + 0xC98)
    #define REG_0C98_CKGEN01_REG_CKG_DV_HW5_SRAM Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0C98_CKGEN01_REG_CKG_DV_HW5_C2_SRAM_0C98 Fld(3,4,AC_MSKB0)//[6:4]
#define REG_0CA0_CKGEN01 (ckgen01 + 0xCA0)
    #define REG_0CA0_CKGEN01_REG_CKG_DC0_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CA8_CKGEN01 (ckgen01 + 0xCA8)
    #define REG_0CA8_CKGEN01_REG_CKG_UCD_ST_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CB0_CKGEN01 (ckgen01 + 0xCB0)
    #define REG_0CB0_CKGEN01_REG_CKG_XC_ADC_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CB8_CKGEN01 (ckgen01 + 0xCB8)
    #define REG_0CB8_CKGEN01_REG_CKG_XC_SUB_DC0_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0CBC_CKGEN01 (ckgen01 + 0xCBC)
    #define REG_0CBC_CKGEN01_REG_CKG_XC_SUB1_DC0_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0CC0_CKGEN01 (ckgen01 + 0xCC0)
    #define REG_0CC0_CKGEN01_REG_CKG_XC_DISP_MFDEC_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0CC8_CKGEN01 (ckgen01 + 0xCC8)
    #define REG_0CC8_CKGEN01_REG_CKG_XC_HD2MIU_M_SCIP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CD0_CKGEN01 (ckgen01 + 0xCD0)
    #define REG_0CD0_CKGEN01_REG_CKG_XC_HD2MIU_S_SCIP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CD8_CKGEN01 (ckgen01 + 0xCD8)
    #define REG_0CD8_CKGEN01_REG_CKG_XC_HDMI0_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CE0_CKGEN01 (ckgen01 + 0xCE0)
    #define REG_0CE0_CKGEN01_REG_CKG_XC_HDMI1_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CE8_CKGEN01 (ckgen01 + 0xCE8)
    #define REG_0CE8_CKGEN01_REG_CKG_XC_HDMI2_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CF0_CKGEN01 (ckgen01 + 0xCF0)
    #define REG_0CF0_CKGEN01_REG_CKG_XC_HDMI3_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0CF8_CKGEN01 (ckgen01 + 0xCF8)
    #define REG_0CF8_CKGEN01_REG_CKG_XC_IP2_SRC_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D00_CKGEN01 (ckgen01 + 0xD00)
    #define REG_0D00_CKGEN01_REG_CKG_XC_SLOW_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0D08_CKGEN01 (ckgen01 + 0xD08)
    #define REG_0D08_CKGEN01_REG_CKG_XC_TGEN_WIN_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D10_CKGEN01 (ckgen01 + 0xD10)
    #define REG_0D10_CKGEN01_REG_CKG_XC_UCD_STAT_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D18_CKGEN01 (ckgen01 + 0xD18)
    #define REG_0D18_CKGEN01_REG_CKG_XC_VD_SCIP Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0D18_CKGEN01_REG_CKG_XC_DV_SRC_SCIP_0D18 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_0D18_CKGEN01_REG_CKG_DV_HW5_C1_0D18 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_0D20_CKGEN01 (ckgen01 + 0xD20)
    #define REG_0D20_CKGEN01_REG_CKG_XC_VE_SCIP Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D28_CKGEN01 (ckgen01 + 0xD28)
    #define REG_0D28_CKGEN01_REG_CKG_XC_VEDAC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0D30_CKGEN01 (ckgen01 + 0xD30)
    #define REG_0D30_CKGEN01_REG_CKG_DBK_HW_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D38_CKGEN01 (ckgen01 + 0xD38)
    #define REG_0D38_CKGEN01_REG_CKG_SCNR_HDR_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D40_CKGEN01 (ckgen01 + 0xD40)
    #define REG_0D40_CKGEN01_REG_CKG_SPF_HDBK_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D48_CKGEN01 (ckgen01 + 0xD48)
    #define REG_0D48_CKGEN01_REG_CKG_VDBK_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D50_CKGEN01 (ckgen01 + 0xD50)
    #define REG_0D50_CKGEN01_REG_CKG_DELTA_B2P_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D58_CKGEN01 (ckgen01 + 0xD58)
    #define REG_0D58_CKGEN01_REG_CKG_GUCD_18_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D60_CKGEN01 (ckgen01 + 0xD60)
    #define REG_0D60_CKGEN01_REG_CKG_GUCD_256_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D68_CKGEN01 (ckgen01 + 0xD68)
    #define REG_0D68_CKGEN01_REG_CKG_HSY_SP3_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D70_CKGEN01 (ckgen01 + 0xD70)
    #define REG_0D70_CKGEN01_REG_CKG_HSY_SP_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D78_CKGEN01 (ckgen01 + 0xD78)
    #define REG_0D78_CKGEN01_REG_CKG_HVSP_STP1_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D80_CKGEN01 (ckgen01 + 0xD80)
    #define REG_0D80_CKGEN01_REG_CKG_HVSP_STP2_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D88_CKGEN01 (ckgen01 + 0xD88)
    #define REG_0D88_CKGEN01_REG_CKG_LCE_SCL_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D90_CKGEN01 (ckgen01 + 0xD90)
    #define REG_0D90_CKGEN01_REG_CKG_VIP_PQ_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D98_CKGEN01 (ckgen01 + 0xD98)
    #define REG_0D98_CKGEN01_REG_CKG_AISR_SRAM Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0D9C_CKGEN01 (ckgen01 + 0xD9C)
    #define REG_0D9C_CKGEN01_REG_CKG_AISR_HVSP_SRAM Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0DA0_CKGEN01 (ckgen01 + 0xDA0)
    #define REG_0DA0_CKGEN01_REG_CKG_XC_AISR_SCSR Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DA8_CKGEN01 (ckgen01 + 0xDA8)
    #define REG_0DA8_CKGEN01_REG_CKG_XC_FN_SCSR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0DB0_CKGEN01 (ckgen01 + 0xDB0)
    #define REG_0DB0_CKGEN01_REG_CKG_DEMURA_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DB8_CKGEN01 (ckgen01 + 0xDB8)
    #define REG_0DB8_CKGEN01_REG_CKG_GOP0_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DC0_CKGEN01 (ckgen01 + 0xDC0)
    #define REG_0DC0_CKGEN01_REG_CKG_GOP1_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DC8_CKGEN01 (ckgen01 + 0xDC8)
    #define REG_0DC8_CKGEN01_REG_CKG_GOP2_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DD0_CKGEN01 (ckgen01 + 0xDD0)
    #define REG_0DD0_CKGEN01_REG_CKG_GOP3_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DD8_CKGEN01 (ckgen01 + 0xDD8)
    #define REG_0DD8_CKGEN01_REG_CKG_LD_EDGE2D_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DE0_CKGEN01 (ckgen01 + 0xDE0)
    #define REG_0DE0_CKGEN01_REG_CKG_LDCOMP_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DE8_CKGEN01 (ckgen01 + 0xDE8)
    #define REG_0DE8_CKGEN01_REG_CKG_LDM_GA_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DEC_CKGEN01 (ckgen01 + 0xDEC)
    #define REG_0DEC_CKGEN01_REG_CKG_PQ_GA_SRAM_0DEC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DF0_CKGEN01 (ckgen01 + 0xDF0)
    #define REG_0DF0_CKGEN01_REG_CKG_LDMCG_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0DF8_CKGEN01 (ckgen01 + 0xDF8)
    #define REG_0DF8_CKGEN01_REG_CKG_LPQ_PA_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E00_CKGEN01 (ckgen01 + 0xE00)
    #define REG_0E00_CKGEN01_REG_CKG_OSD_DV_HW5_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E08_CKGEN01 (ckgen01 + 0xE08)
    #define REG_0E08_CKGEN01_REG_CKG_PADJ_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E10_CKGEN01 (ckgen01 + 0xE10)
    #define REG_0E10_CKGEN01_REG_CKG_PANEL_GA_SRAM Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E14_CKGEN01 (ckgen01 + 0xE14)
    #define REG_0E14_CKGEN01_REG_CKG_SIDCLK_HD0_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E18_CKGEN01 (ckgen01 + 0xE18)
    #define REG_0E18_CKGEN01_REG_CKG_SIDCLK_HD1_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E1C_CKGEN01 (ckgen01 + 0xE1C)
    #define REG_0E1C_CKGEN01_REG_CKG_SIDCLK_HD2_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E20_CKGEN01 (ckgen01 + 0xE20)
    #define REG_0E20_CKGEN01_REG_CKG_SIDCLK_HD3_SCIP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E24_CKGEN01 (ckgen01 + 0xE24)
    #define REG_0E24_CKGEN01_REG_CKG_XC_DIP0_SCIP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0E28_CKGEN01 (ckgen01 + 0xE28)
    #define REG_0E28_CKGEN01_REG_CKG_XC_DIP1_SCIP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0E2C_CKGEN01 (ckgen01 + 0xE2C)
    #define REG_0E2C_CKGEN01_REG_CKG_XC_DIP2_SCIP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0E30_CKGEN01 (ckgen01 + 0xE30)
    #define REG_0E30_CKGEN01_REG_CKG_XC_AFBC_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E34_CKGEN01 (ckgen01 + 0xE34)
    #define REG_0E34_CKGEN01_REG_CKG_XC_GOP0_DST_SCTCON Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E38_CKGEN01 (ckgen01 + 0xE38)
    #define REG_0E38_CKGEN01_REG_CKG_XC_GOP_SCL_SCTCON Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E3C_CKGEN01 (ckgen01 + 0xE3C)
    #define REG_0E3C_CKGEN01_REG_CKG_XC_GOP_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E40_CKGEN01 (ckgen01 + 0xE40)
    #define REG_0E40_CKGEN01_REG_CKG_XC_GOPC_DST_SCTCON Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E44_CKGEN01 (ckgen01 + 0xE44)
    #define REG_0E44_CKGEN01_REG_CKG_XC_GOPG_DST_SCTCON Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0E48_CKGEN01 (ckgen01 + 0xE48)
    #define REG_0E48_CKGEN01_REG_CKG_XC_OD_DELTA_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E4C_CKGEN01 (ckgen01 + 0xE4C)
    #define REG_0E4C_CKGEN01_REG_CKG_XC_OD_DIV2_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E50_CKGEN01 (ckgen01 + 0xE50)
    #define REG_0E50_CKGEN01_REG_CKG_XC_OD_DIV4_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E54_CKGEN01 (ckgen01 + 0xE54)
    #define REG_0E54_CKGEN01_REG_FLOW_CTRL_RATE_XC_ED Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0E54_CKGEN01_REG_FLOW_CTRL_RATE_XC_ED_SLD_0E54 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E58_CKGEN01 (ckgen01 + 0xE58)
    #define REG_0E58_CKGEN01_REG_FLOW_CTRL_RATE_XC_FN Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0E58_CKGEN01_REG_FLOW_CTRL_RATE_XC_FN_SLD_0E58 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E5C_CKGEN01 (ckgen01 + 0xE5C)
    #define REG_0E5C_CKGEN01_REG_FLOW_CTRL_RATE_XC_FS Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0E5C_CKGEN01_REG_FLOW_CTRL_RATE_XC_FS_SLD_0E5C Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E60_CKGEN01 (ckgen01 + 0xE60)
    #define REG_0E60_CKGEN01_REG_FLOW_CTRL_RATE_XC_FD Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_0E60_CKGEN01_REG_FLOW_CTRL_RATE_XC_FD_SLD_0E60 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0E68_CKGEN01 (ckgen01 + 0xE68)
    #define REG_0E68_CKGEN01_REG_CKG_XC_OD_OSD_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0E70_CKGEN01 (ckgen01 + 0xE70)
    #define REG_0E70_CKGEN01_REG_CKG_XC_FS_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_0E70_CKGEN01_REG_CKG_XC_FS_SCDISP_0E70 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E78_CKGEN01 (ckgen01 + 0xE78)
    #define REG_0E78_CKGEN01_REG_CKG_XC_SC2FPLL_SCIP Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0E80_CKGEN01 (ckgen01 + 0x0E80)
    #define REG_0E80_CKGEN01_REG_GATE_XC_ED_0E80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0E84_CKGEN01 (ckgen01 + 0x0E84)
    #define REG_0E84_CKGEN01_REG_GATE_XC_FN_0E84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0E88_CKGEN01 (ckgen01 + 0x0E88)
    #define REG_0E88_CKGEN01_REG_GATE_XC_FS_0E88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0E8C_CKGEN01 (ckgen01 + 0x0E8C)
    #define REG_0E8C_CKGEN01_REG_GATE_XC_FD_0E8C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0EE0_CKGEN01 (ckgen01 + 0xEE0)
    #define REG_0EE0_CKGEN01_REG_CKG_MCU_MAIL0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0EE8_CKGEN01 (ckgen01 + 0xEE8)
    #define REG_0EE8_CKGEN01_REG_CKG_MCU_MAIL1 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0EF0_CKGEN01 (ckgen01 + 0xEF0)
    #define REG_0EF0_CKGEN01_REG_CKG_VD2X Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0EF0_CKGEN01_REG_CKG_VD2X_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0EF8_CKGEN01 (ckgen01 + 0xEF8)
    #define REG_0EF8_CKGEN01_REG_CKG_VD_32FSC Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0EF8_CKGEN01_REG_CKG_VD_32FSC_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0F00_CKGEN01 (ckgen01 + 0xF00)
    #define REG_0F00_CKGEN01_REG_CKG_VD Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0F00_CKGEN01_REG_CKG_VD_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0F08_CKGEN01 (ckgen01 + 0xF08)
    #define REG_0F08_CKGEN01_REG_CKG_CMBAI Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F10_CKGEN01 (ckgen01 + 0xF10)
    #define REG_0F10_CKGEN01_REG_CKG_CMBAO Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F18_CKGEN01 (ckgen01 + 0xF18)
    #define REG_0F18_CKGEN01_REG_CKG_CMBBI Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F20_CKGEN01 (ckgen01 + 0xF20)
    #define REG_0F20_CKGEN01_REG_CKG_CMBBO Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F40_CKGEN01 (ckgen01 + 0xF40)
    #define REG_0F40_CKGEN01_REG_CKG_VE Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F48_CKGEN01 (ckgen01 + 0xF48)
    #define REG_0F48_CKGEN01_REG_CKG_VEDAC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_0F50_CKGEN01 (ckgen01 + 0xF50)
    #define REG_0F50_CKGEN01_REG_CKG_VENC Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0F50_CKGEN01_REG_CKG_VENC_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0F68_CKGEN01 (ckgen01 + 0xF68)
    #define REG_0F68_CKGEN01_REG_CKG_SMI_FCIE_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0F70_CKGEN01 (ckgen01 + 0xF70)
    #define REG_0F70_CKGEN01_REG_CKG_ECC Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0F70_CKGEN01_REG_CKG_ECC_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0F78_CKGEN01 (ckgen01 + 0xF78)
    #define REG_0F78_CKGEN01_REG_CKG_FCIE Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_0F78_CKGEN01_REG_CKG_FCIE_TSP Fld(4,8,AC_MSKB1)//[11:8]
#define REG_0F80_CKGEN01 (ckgen01 + 0xF80)
    #define REG_0F80_CKGEN01_REG_CKG_FCIE_SYN Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0F90_CKGEN01 (ckgen01 + 0xF90)
    #define REG_0F90_CKGEN01_REG_CKG_GMAC_AHB Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0F90_CKGEN01_REG_CKG_GMAC_AHB_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0F98_CKGEN01 (ckgen01 + 0xF98)
    #define REG_0F98_CKGEN01_REG_CKG_GMAC_RX_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0FA0_CKGEN01 (ckgen01 + 0xFA0)
    #define REG_0FA0_CKGEN01_REG_CKG_GMAC_TX_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0FB4_CKGEN01 (ckgen01 + 0xFB4)
    #define REG_0FB4_CKGEN01_REG_CKG_PEXTP_PL_PCLK_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FB8_CKGEN01 (ckgen01 + 0xFB8)
    #define REG_0FB8_CKGEN01_REG_CKG_XTAL_12M_PCIE_PHY Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0FC0_CKGEN01 (ckgen01 + 0xFC0)
    #define REG_0FC0_CKGEN01_REG_CKG_PEXTP_TL Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_0FC0_CKGEN01_REG_CKG_PEXTP_TL_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_0FC4_CKGEN01 (ckgen01 + 0xFC4)
    #define REG_0FC4_CKGEN01_REG_CKG_SSUSB_USB20_PHY_CLK_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FC8_CKGEN01 (ckgen01 + 0xFC8)
    #define REG_0FC8_CKGEN01_REG_CKG_SSUSB_USB20_PHY_CLK_1P_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FCC_CKGEN01 (ckgen01 + 0xFCC)
    #define REG_0FCC_CKGEN01_REG_CKG_SSUSB_USB20_PHY_CLK_2P_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FD0_CKGEN01 (ckgen01 + 0xFD0)
    #define REG_0FD0_CKGEN01_REG_CKG_SSUSB_FRMCNT_TSP Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0FD0_CKGEN01_REG_CKG_SSUSB_MISC_48M_TSP_0FD0 Fld(2,4,AC_MSKB0)//[5:4]
#define REG_0FD4_CKGEN01 (ckgen01 + 0xFD4)
    #define REG_0FD4_CKGEN01_REG_CKG_SSUSB_PCLK_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FD8_CKGEN01 (ckgen01 + 0xFD8)
    #define REG_0FD8_CKGEN01_REG_CKG_SSUSB_PCLK_1P_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FE0_CKGEN01 (ckgen01 + 0xFE0)
    #define REG_0FE0_CKGEN01_REG_CKG_XTAL_12M_USB_PHY Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0FE8_CKGEN01 (ckgen01 + 0xFE8)
    #define REG_0FE8_CKGEN01_REG_CKG_SSUSB_SYS_TSP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0FEC_CKGEN01 (ckgen01 + 0xFEC)
    #define REG_0FEC_CKGEN01_REG_CKG_SSUSB_XHCI_TSP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0FF0_CKGEN01 (ckgen01 + 0xFF0)
    #define REG_0FF0_CKGEN01_REG_CKG_USBPHY240_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FF4_CKGEN01 (ckgen01 + 0xFF4)
    #define REG_0FF4_CKGEN01_REG_CKG_USBPHY240_MUX_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FF8_CKGEN01 (ckgen01 + 0xFF8)
    #define REG_0FF8_CKGEN01_REG_CKG_USBPHY30_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FFC_CKGEN01 (ckgen01 + 0xFFC)
    #define REG_0FFC_CKGEN01_REG_CKG_SMI_UHC_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1000_CKGEN01 (ckgen01 + 0x1000)
    #define REG_1000_CKGEN01_REG_CKG_UFS Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1000_CKGEN01_REG_CKG_UFS_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1008_CKGEN01 (ckgen01 + 0x1008)
    #define REG_1008_CKGEN01_REG_CKG_UFS_AES Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1008_CKGEN01_REG_CKG_UFS_AES_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_100C_CKGEN01 (ckgen01 + 0x100C)
    #define REG_100C_CKGEN01_REG_CKG_UFS_MP_SAP_CFG_TSP Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1010_CKGEN01 (ckgen01 + 0x1010)
    #define REG_1010_CKGEN01_REG_CKG_UFS_RX_SYMBOL_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1014_CKGEN01 (ckgen01 + 0x1014)
    #define REG_1014_CKGEN01_REG_CKG_UFS_TX_SYMBOL_TSP Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1018_CKGEN01 (ckgen01 + 0x1018)
    #define REG_1018_CKGEN01_REG_CKG_UFS_UNIPRO_CG_SYN Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1018_CKGEN01_REG_CKG_UFS_UNIPRO_CG_SYN_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1020_CKGEN01 (ckgen01 + 0x1020)
    #define REG_1020_CKGEN01_REG_CKG_SMI_AESDMA_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1028_CKGEN01 (ckgen01 + 0x1028)
    #define REG_1028_CKGEN01_REG_CKG_SMI_TSP_SEL Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1028_CKGEN01_REG_CKG_SMI_SSUSB_SEL_1028 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1040_CKGEN01 (ckgen01 + 0x1040)
    #define REG_1040_CKGEN01_REG_CKG_MCU_NONPM Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1040_CKGEN01_REG_CKG_MCU_NONPM_DEMOD0 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1040_CKGEN01_REG_CKG_MCU_NONPM_FRCIOPMRV55 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1040_CKGEN01_REG_CKG_MCU_NONPM_FRCMEHALO Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_1040_CKGEN01_REG_CKG_MCU_NONPM_PCIE_PHY Fld(2,14,AC_MSKB1)//[15:14]

//Page CKGEN01_4
#define REG_1044_CKGEN01 (ckgen01 + 0x1044)
    #define REG_1044_CKGEN01_REG_CKG_MCU_NONPM_FRCCORE1_1044 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1044_CKGEN01_REG_CKG_MCU_NONPM_FRCCORE2_1044 Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_1044_CKGEN01_REG_CKG_MCU_NONPM_FRCCORE3_1044 Fld(2,4,AC_MSKB0)//[5:4]
#define REG_1048_CKGEN01 (ckgen01 + 0x1048)
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCACE Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCDV Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCIP Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCMW Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCNR Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCPQ Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCSCL Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_1048_CKGEN01_REG_CKG_MCU_NONPM_SCSR Fld(2,14,AC_MSKB1)//[15:14]
#define REG_104C_CKGEN01 (ckgen01 + 0x104C)
    #define REG_104C_CKGEN01_REG_CKG_MCU_NONPM_SCDISP_104C Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1050_CKGEN01 (ckgen01 + 0x1050)
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_SCTCON Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_UFS_PHY Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_USB_PHY Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_1050_CKGEN01_REG_CKG_XIU_VDEC_SOC Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_AIA Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_MHEG5 Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_GPU_DIE Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_1050_CKGEN01_REG_CKG_MCU_NONPM_GPU_NODIE Fld(2,14,AC_MSKB1)//[15:14]
#define REG_1054_CKGEN01 (ckgen01 + 0x1054)
    #define REG_1054_CKGEN01_REG_CKG_MCU_NONPM_RV55FRC_1054 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1054_CKGEN01_REG_CKG_MCU_NONPM_RV55PQU_1054 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1058_CKGEN01 (ckgen01 + 0x1058)
    #define REG_1058_CKGEN01_REG_CKG_MCU_NONPM_HDMIRX Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1058_CKGEN01_REG_CKG_MCU_NONPM_IP_WRAP Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_1058_CKGEN01_REG_CKG_MCU_NONPM_VIVA Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_1058_CKGEN01_REG_CKG_MCU_NONPM_TSP Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_1058_CKGEN01_REG_CKG_PEXTP_AHB_APB_TSP Fld(2,8,AC_MSKB1)//[9:8]
#define REG_10E0_CKGEN01 (ckgen01 + 0x10E0)
    #define REG_10E0_CKGEN01_REG_CKG_MCU_AU Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_10E0_CKGEN01_REG_CKG_MCU_AU_AUDIO_R2 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_10E0_CKGEN01_REG_CKG_VIVA_AU_MCU Fld(3,10,AC_MSKB1)//[12:10]
    #define REG_10E0_CKGEN01_REG_CKG_MCU_AU_RV55AUDIO Fld(2,14,AC_MSKB1)//[15:14]
#define REG_10F8_CKGEN01 (ckgen01 + 0x10F8)
    #define REG_10F8_CKGEN01_REG_CKG_MCU_CODEC Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1110_CKGEN01 (ckgen01 + 0x1110)
    #define REG_1110_CKGEN01_REG_CKG_MCU_DMD Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1110_CKGEN01_REG_CKG_MCU_DMD_DEMOD0 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1128_CKGEN01 (ckgen01 + 0x1128)
    #define REG_1128_CKGEN01_REG_CKG_MCU_FRC Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1128_CKGEN01_REG_CKG_MCU_FRC_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1128_CKGEN01_REG_CKG_MCU_FRC_RV55FRC Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1128_CKGEN01_REG_CKG_MCU_FRC_RV55PQU Fld(2,12,AC_MSKB1)//[13:12]
#define REG_1130_CKGEN01 (ckgen01 + 0x1130)
    #define REG_1130_CKGEN01_REG_CKG_MCU_FRC_FRCMISC_1130 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1140_CKGEN01 (ckgen01 + 0x1140)
    #define REG_1140_CKGEN01_REG_CKG_MCU_HDMI Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1140_CKGEN01_REG_CKG_MCU_HDMI_HDMIRX Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1170_CKGEN01 (ckgen01 + 0x1170)
    #define REG_1170_CKGEN01_REG_CKG_MCU_SC Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_1170_CKGEN01_REG_CKG_MCU_XC_SCACE Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1170_CKGEN01_REG_CKG_MCU_XC_SCDV Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_1170_CKGEN01_REG_CKG_MCU_XC_SCIP Fld(2,14,AC_MSKB1)//[15:14]
#define REG_1178_CKGEN01 (ckgen01 + 0x1178)
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCMW Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCNR Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCPQ Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCSCL Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCSR Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCTCON Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_1178_CKGEN01_REG_CKG_MCU_XC_SCDISP_1178 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_11A0_CKGEN01 (ckgen01 + 0x11A0)
    #define REG_11A0_CKGEN01_REG_CKG_MCU_VD Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_11A0_CKGEN01_REG_CKG_MCU_VD_MHEG5 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_11B8_CKGEN01 (ckgen01 + 0x11B8)
    #define REG_11B8_CKGEN01_REG_CKG_MCU_BUS Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_11B8_CKGEN01_REG_CKG_MCU_BUS_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_11B8_CKGEN01_REG_CKG_MCU_BUS_SCSCL Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_11B8_CKGEN01_REG_CKG_AU_MCU_BUS Fld(3,12,AC_MSKB1)//[14:12]
#define REG_11C0_CKGEN01 (ckgen01 + 0x11C0)
    #define REG_11C0_CKGEN01_REG_CKG_MCU_BUS_DEMOD0 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_11C0_CKGEN01_REG_CKG_MCU_BUS_HDMIRX Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_11C0_CKGEN01_REG_CKG_MCU_BUS_MHEG5 Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_11C0_CKGEN01_REG_CKG_MCU_BUS_RV55FRC Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_11C0_CKGEN01_REG_CKG_MCU_BUS_RV55PQU Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_11C0_CKGEN01_REG_CKG_MCU_BUS_FRCMISC_11C0 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_11C4_CKGEN01 (ckgen01 + 0x11C4)
    #define REG_11C4_CKGEN01_REG_CKG_MCU_BUS_SCMW_11C4 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_11F0_CKGEN01 (ckgen01 + 0x11F0)
    #define REG_11F0_CKGEN01_REG_CKG_MIIC0 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_11F0_CKGEN01_REG_CKG_MIIC0_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_11F8_CKGEN01 (ckgen01 + 0x11F8)
    #define REG_11F8_CKGEN01_REG_CKG_MIIC1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_11F8_CKGEN01_REG_CKG_MIIC1_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1200_CKGEN01 (ckgen01 + 0x1200)
    #define REG_1200_CKGEN01_REG_CKG_MIIC2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1200_CKGEN01_REG_CKG_MIIC2_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1208_CKGEN01 (ckgen01 + 0x1208)
    #define REG_1208_CKGEN01_REG_CKG_MIIC3 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1208_CKGEN01_REG_CKG_MIIC3_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1230_CKGEN01 (ckgen01 + 0x1230)
    #define REG_1230_CKGEN01_REG_CKG_MSPI_CILINK Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1230_CKGEN01_REG_CKG_MSPI_CILINK_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1238_CKGEN01 (ckgen01 + 0x1238)
    #define REG_1238_CKGEN01_REG_CKG_MSPI_CILINK_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1240_CKGEN01 (ckgen01 + 0x1240)
    #define REG_1240_CKGEN01_REG_CKG_MSPI0 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1240_CKGEN01_REG_CKG_MSPI0_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1248_CKGEN01 (ckgen01 + 0x1248)
    #define REG_1248_CKGEN01_REG_CKG_MSPI0_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1250_CKGEN01 (ckgen01 + 0x1250)
    #define REG_1250_CKGEN01_REG_CKG_MSPI1 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1250_CKGEN01_REG_CKG_MSPI1_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1258_CKGEN01 (ckgen01 + 0x1258)
    #define REG_1258_CKGEN01_REG_CKG_MSPI1_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1260_CKGEN01 (ckgen01 + 0x1260)
    #define REG_1260_CKGEN01_REG_CKG_MSPI2 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1260_CKGEN01_REG_CKG_MSPI2_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1268_CKGEN01 (ckgen01 + 0x1268)
    #define REG_1268_CKGEN01_REG_CKG_MSPI2_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1270_CKGEN01 (ckgen01 + 0x1270)
    #define REG_1270_CKGEN01_REG_CKG_MSPI3 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1270_CKGEN01_REG_CKG_MSPI3_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1278_CKGEN01 (ckgen01 + 0x1278)
    #define REG_1278_CKGEN01_REG_CKG_MSPI3_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1280_CKGEN01 (ckgen01 + 0x1280)
    #define REG_1280_CKGEN01_REG_CKG_MSPI4 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1280_CKGEN01_REG_CKG_MSPI4_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1288_CKGEN01 (ckgen01 + 0x1288)
    #define REG_1288_CKGEN01_REG_CKG_MSPI4_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1290_CKGEN01 (ckgen01 + 0x1290)
    #define REG_1290_CKGEN01_REG_CKG_MSPI5 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_1290_CKGEN01_REG_CKG_MSPI5_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1298_CKGEN01 (ckgen01 + 0x1298)
    #define REG_1298_CKGEN01_REG_CKG_MSPI5_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_12A0_CKGEN01 (ckgen01 + 0x12A0)
    #define REG_12A0_CKGEN01_REG_CKG_MSPI6 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_12A0_CKGEN01_REG_CKG_MSPI6_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_12A8_CKGEN01 (ckgen01 + 0x12A8)
    #define REG_12A8_CKGEN01_REG_CKG_MSPI6_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_12B0_CKGEN01 (ckgen01 + 0x12B0)
    #define REG_12B0_CKGEN01_REG_CKG_MSPI7 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_12B0_CKGEN01_REG_CKG_MSPI7_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_12B8_CKGEN01 (ckgen01 + 0x12B8)
    #define REG_12B8_CKGEN01_REG_CKG_MSPI7_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_12C0_CKGEN01 (ckgen01 + 0x12C0)
    #define REG_12C0_CKGEN01_REG_CKG_FRC_MSPI0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_12C8_CKGEN01 (ckgen01 + 0x12C8)
    #define REG_12C8_CKGEN01_REG_CKG_FRC_MSPI0_FRCIOPMRV55 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_12D0_CKGEN01 (ckgen01 + 0x12D0)
    #define REG_12D0_CKGEN01_REG_CKG_FRC_MSPI0_DIV Fld(5,0,AC_MSKB0)//[4:0]
#define REG_12E8_CKGEN01 (ckgen01 + 0x12E8)
    #define REG_12E8_CKGEN01_REG_CKG_SPI Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_12E8_CKGEN01_REG_CKG_SPI_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1368_CKGEN01 (ckgen01 + 0x1368)
    #define REG_1368_CKGEN01_REG_CKG_UART0 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1368_CKGEN01_REG_CKG_UART0_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1370_CKGEN01 (ckgen01 + 0x1370)
    #define REG_1370_CKGEN01_REG_CKG_UART0_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1378_CKGEN01 (ckgen01 + 0x1378)
    #define REG_1378_CKGEN01_REG_CKG_UART1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1378_CKGEN01_REG_CKG_UART1_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1380_CKGEN01 (ckgen01 + 0x1380)
    #define REG_1380_CKGEN01_REG_CKG_UART1_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1388_CKGEN01 (ckgen01 + 0x1388)
    #define REG_1388_CKGEN01_REG_CKG_UART2 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1388_CKGEN01_REG_CKG_UART2_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_1390_CKGEN01 (ckgen01 + 0x1390)
    #define REG_1390_CKGEN01_REG_CKG_UART2_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1398_CKGEN01 (ckgen01 + 0x1398)
    #define REG_1398_CKGEN01_REG_CKG_FRC_UART0 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_1398_CKGEN01_REG_CKG_FRC_UART0_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_13A0_CKGEN01 (ckgen01 + 0x13A0)
    #define REG_13A0_CKGEN01_REG_CKG_FRC_UART0_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_13A8_CKGEN01 (ckgen01 + 0x13A8)
    #define REG_13A8_CKGEN01_REG_CKG_FRC_UART1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_13A8_CKGEN01_REG_CKG_FRC_UART1_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_13B0_CKGEN01 (ckgen01 + 0x13B0)
    #define REG_13B0_CKGEN01_REG_CKG_FRC_UART1_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_13B8_CKGEN01 (ckgen01 + 0x13B8)
    #define REG_13B8_CKGEN01_REG_CKG_FUART0 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_13B8_CKGEN01_REG_CKG_FUART0_MHEG5 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_13C0_CKGEN01 (ckgen01 + 0x13C0)
    #define REG_13C0_CKGEN01_REG_CKG_FUART0_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_13C8_CKGEN01 (ckgen01 + 0x13C8)
    #define REG_13C8_CKGEN01_REG_CKG_AU_UART0 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_13C8_CKGEN01_REG_CKG_AU_UART0_VIVA Fld(2,8,AC_MSKB1)//[9:8]
#define REG_13D0_CKGEN01 (ckgen01 + 0x13D0)
    #define REG_13D0_CKGEN01_REG_CKG_AU_UART0_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_13D8_CKGEN01 (ckgen01 + 0x13D8)
    #define REG_13D8_CKGEN01_REG_CKG_FRC_FUART0 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_13D8_CKGEN01_REG_CKG_FRC_FUART0_FRCIOPMRV55 Fld(2,8,AC_MSKB1)//[9:8]
#define REG_13E0_CKGEN01 (ckgen01 + 0x13E0)
    #define REG_13E0_CKGEN01_REG_CKG_FRC_FUART0_SYNTH Fld(4,0,AC_MSKB0)//[3:0]
#define REG_14A8_CKGEN01 (ckgen01 + 0x14A8)
    #define REG_14A8_CKGEN01_REG_SW_EN_CLKD_ADC2ADC_TOP_DATA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14AC_CKGEN01 (ckgen01 + 0x14AC)
    #define REG_14AC_CKGEN01_REG_SW_EN_CLKD_ADC2GEMIU2ADC_TOP_DATA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B0_CKGEN01 (ckgen01 + 0x14B0)
    #define REG_14B0_CKGEN01_REG_SW_EN_CLKD_ADC2SC2ADC_TOP_DATA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B4_CKGEN01 (ckgen01 + 0x14B4)
    #define REG_14B4_CKGEN01_REG_SW_EN_CLKD_FBLANK2ADC_TOP_DATA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B8_CKGEN01 (ckgen01 + 0x14B8)
    #define REG_14B8_CKGEN01_REG_SW_EN_CLKD_VD2ADC_TOP_DATA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14BC_CKGEN01 (ckgen01 + 0x14BC)
    #define REG_14BC_CKGEN01_REG_SW_EN_CLKFSCX2_VD2ADC_TOP_DATA Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C0_CKGEN01 (ckgen01 + 0x14C0)
    #define REG_14C0_CKGEN01_REG_SW_EN_ADC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C4_CKGEN01 (ckgen01 + 0x14C4)
    #define REG_14C4_CKGEN01_REG_SW_EN_ADC2MIU2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C8_CKGEN01 (ckgen01 + 0x14C8)
    #define REG_14C8_CKGEN01_REG_SW_EN_ADC2MIUSC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14CC_CKGEN01 (ckgen01 + 0x14CC)
    #define REG_14CC_CKGEN01_REG_SW_EN_ADC2SC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D0_CKGEN01 (ckgen01 + 0x14D0)
    #define REG_14D0_CKGEN01_REG_SW_EN_ADCPLL2002ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D4_CKGEN01 (ckgen01 + 0x14D4)
    #define REG_14D4_CKGEN01_REG_SW_EN_ADCPLL4002ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D8_CKGEN01 (ckgen01 + 0x14D8)
    #define REG_14D8_CKGEN01_REG_SW_EN_B_ADC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14DC_CKGEN01 (ckgen01 + 0x14DC)
    #define REG_14DC_CKGEN01_REG_SW_EN_B_INT2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E0_CKGEN01 (ckgen01 + 0x14E0)
    #define REG_14E0_CKGEN01_REG_SW_EN_CLKPLL2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E4_CKGEN01 (ckgen01 + 0x14E4)
    #define REG_14E4_CKGEN01_REG_SW_EN_CVBS_DAC_A_DIGITAL0_MUX2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E8_CKGEN01 (ckgen01 + 0x14E8)
    #define REG_14E8_CKGEN01_REG_SW_EN_CVBS_DAC_A_DIGITAL02ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14EC_CKGEN01 (ckgen01 + 0x14EC)
    #define REG_14EC_CKGEN01_REG_SW_EN_CVBS_DAC_A_DIGITAL12ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14F0_CKGEN01 (ckgen01 + 0x14F0)
    #define REG_14F0_CKGEN01_REG_SW_EN_DIG_2162ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14F4_CKGEN01 (ckgen01 + 0x14F4)
    #define REG_14F4_CKGEN01_REG_SW_EN_FBLANK2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14F8_CKGEN01 (ckgen01 + 0x14F8)
    #define REG_14F8_CKGEN01_REG_SW_EN_FSC_VD2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1500_CKGEN01 (ckgen01 + 0x1500)
    #define REG_1500_CKGEN01_REG_SW_EN_G_ADC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1504_CKGEN01 (ckgen01 + 0x1504)
    #define REG_1504_CKGEN01_REG_SW_EN_G_INT2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1508_CKGEN01 (ckgen01 + 0x1508)
    #define REG_1508_CKGEN01_REG_SW_EN_ISOG2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1510_CKGEN01 (ckgen01 + 0x1510)
    #define REG_1510_CKGEN01_REG_SW_EN_NCO_CLK2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1518_CKGEN01 (ckgen01 + 0x1518)
    #define REG_1518_CKGEN01_REG_SW_EN_R_ADC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_151C_CKGEN01 (ckgen01 + 0x151C)
    #define REG_151C_CKGEN01_REG_SW_EN_R_INT2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1520_CKGEN01 (ckgen01 + 0x1520)
    #define REG_1520_CKGEN01_REG_SW_EN_VD_ICLAMP2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1524_CKGEN01 (ckgen01 + 0x1524)
    #define REG_1524_CKGEN01_REG_SW_EN_VD_ICLAMP2VIDEO_ATOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1528_CKGEN01 (ckgen01 + 0x1528)
    #define REG_1528_CKGEN01_REG_SW_EN_VD_NCO_CLK2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_152C_CKGEN01 (ckgen01 + 0x152C)
    #define REG_152C_CKGEN01_REG_SW_EN_VD2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1530_CKGEN01 (ckgen01 + 0x1530)
    #define REG_1530_CKGEN01_REG_SW_EN_VDPLL4002ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1534_CKGEN01 (ckgen01 + 0x1534)
    #define REG_1534_CKGEN01_REG_SW_EN_XTAL12_4INTERRUPT2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1538_CKGEN01 (ckgen01 + 0x1538)
    #define REG_1538_CKGEN01_REG_SW_EN_XTAL12_4PLUGDET2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_153C_CKGEN01 (ckgen01 + 0x153C)
    #define REG_153C_CKGEN01_REG_SW_EN_XTAL122ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1540_CKGEN01 (ckgen01 + 0x1540)
    #define REG_1540_CKGEN01_REG_SW_EN_XTAL242ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1544_CKGEN01 (ckgen01 + 0x1544)
    #define REG_1544_CKGEN01_REG_SW_EN_Y_ADC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1548_CKGEN01 (ckgen01 + 0x1548)
    #define REG_1548_CKGEN01_REG_SW_EN_Y_INT2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_154C_CKGEN01 (ckgen01 + 0x154C)
    #define REG_154C_CKGEN01_REG_SW_EN_YUV_ADC2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1550_CKGEN01 (ckgen01 + 0x1550)
    #define REG_1550_CKGEN01_REG_SW_EN_ADCPLB_MPLL2ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1564_CKGEN01 (ckgen01 + 0x1564)
    #define REG_1564_CKGEN01_REG_SW_EN_DISP_MFDEC2GPU_NODIE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1564_CKGEN01_REG_SW_EN_DISP_MFDEC2SCNR Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1570_CKGEN01 (ckgen01 + 0x1570)
    #define REG_1570_CKGEN01_REG_SW_EN_DAP2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1570_CKGEN01_REG_SW_EN_DAP2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1570_CKGEN01_REG_SW_EN_DAP2RV55AUDIO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1570_CKGEN01_REG_SW_EN_DAP2RV55FRC Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1570_CKGEN01_REG_SW_EN_DAP2RV55PQU Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1574_CKGEN01 (ckgen01 + 0x1574)
    #define REG_1574_CKGEN01_REG_SW_EN_DAP_TCK2RV55AUDIO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1578_CKGEN01 (ckgen01 + 0x1578)
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2DEFLICKER Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2FDCLK_2X Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2FRCIOPM Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2FRCIOPMRV55 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2MI_PH3 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2MI_PH4 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2OUT_STAGE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1578_CKGEN01_REG_SW_EN_FRC_FCLK_2X2SNR Fld(1,8,AC_MSKB1)//[8:8]
#define REG_157C_CKGEN01 (ckgen01 + 0x157C)
    #define REG_157C_CKGEN01_REG_SW_EN_FRC_FCLK_2XPLUS2FRCIOPMRV55 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_157C_CKGEN01_REG_SW_EN_FRC_FCLK_2XPLUS2SCIP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_157C_CKGEN01_REG_SW_EN_FRC_FCLK_2XPLUS2SCMW Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1580_CKGEN01 (ckgen01 + 0x1580)
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FDCLK Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCIOPM Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCIOPMRV55 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_ALL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_MLB_SRAM Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_1 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_2 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_3 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_4 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_5 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_6 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_7 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_GMV Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMI_CLK_ALL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1580_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_L Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1584_CKGEN01 (ckgen01 + 0x1584)
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_R Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_L Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMI_CLK_MLB_MI_SRAM_R Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2ME Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2ME_4X4 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2ME_PH1 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2ME_PH2 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1584_CKGEN01_REG_SW_EN_FRC_FCLK2FRCMEMLB_CLK_SAD_8 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_158C_CKGEN01 (ckgen01 + 0x158C)
    #define REG_158C_CKGEN01_REG_SW_EN_RV55FRC_JTAG_TCK2RV55FRC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1590_CKGEN01 (ckgen01 + 0x1590)
    #define REG_1590_CKGEN01_REG_SW_EN_RV55PQU_JTAG_TCK2RV55PQU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1594_CKGEN01 (ckgen01 + 0x1594)
    #define REG_1594_CKGEN01_REG_SW_EN_RV_TCK2RV55FRC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1594_CKGEN01_REG_SW_EN_RV_TCK2RV55PQU Fld(1,1,AC_MSKB0)//[1:1]
#define REG_159C_CKGEN01 (ckgen01 + 0x159C)
    #define REG_159C_CKGEN01_REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_159C_CKGEN01_REG_SW_EN_RV55DAP_JTAG_TCK2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_15A4_CKGEN01 (ckgen01 + 0x15A4)
    #define REG_15A4_CKGEN01_REG_SW_EN_RV55FRC2RV55FRC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A8_CKGEN01 (ckgen01 + 0x15A8)
    #define REG_15A8_CKGEN01_REG_SW_EN_RV55PQU2RV55PQU Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15AC_CKGEN01 (ckgen01 + 0x15AC)
    #define REG_15AC_CKGEN01_REG_SW_EN_XCSRSPLL_SYN2XCSRSPLL_DMACRO Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN01_5
#define REG_15B4_CKGEN01 (ckgen01 + 0x15B4)
    #define REG_15B4_CKGEN01_REG_SW_EN_XTAL_12M2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_15B4_CKGEN01_REG_SW_EN_XTAL_12M2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_15B4_CKGEN01_REG_SW_EN_XTAL_12M2RV55AUDIO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_15B4_CKGEN01_REG_SW_EN_XTAL_12M2RV55FRC Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_15B4_CKGEN01_REG_SW_EN_XTAL_12M2RV55PQU Fld(1,4,AC_MSKB0)//[4:4]
#define REG_15C0_CKGEN01 (ckgen01 + 0x15C0)
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCMEHALO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCMEMLB Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2FRCMI Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2RV55AUDIO Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2RV55FRC Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_15C0_CKGEN01_REG_SW_EN_XTAL_24M2RV55PQU Fld(1,7,AC_MSKB0)//[7:7]
#define REG_15CC_CKGEN01 (ckgen01 + 0x15CC)
    #define REG_15CC_CKGEN01_REG_SW_EN_GE_FIFO_R2GE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D0_CKGEN01 (ckgen01 + 0x15D0)
    #define REG_15D0_CKGEN01_REG_SW_EN_GE_FIFO_W2GE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D4_CKGEN01 (ckgen01 + 0x15D4)
    #define REG_15D4_CKGEN01_REG_SW_EN_GE_PSRAM2GE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D8_CKGEN01 (ckgen01 + 0x15D8)
    #define REG_15D8_CKGEN01_REG_SW_EN_GE2GE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15DC_CKGEN01 (ckgen01 + 0x15DC)
    #define REG_15DC_CKGEN01_REG_SW_EN_V1_ODCLK2SCDISP_15DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E4_CKGEN01 (ckgen01 + 0x15E4)
    #define REG_15E4_CKGEN01_REG_SW_EN_CLK_128FS_FB_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E8_CKGEN01 (ckgen01 + 0x15E8)
    #define REG_15E8_CKGEN01_REG_SW_EN_CLK_128FS_FB_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15EC_CKGEN01 (ckgen01 + 0x15EC)
    #define REG_15EC_CKGEN01_REG_SW_EN_CLK_128FS_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F0_CKGEN01 (ckgen01 + 0x15F0)
    #define REG_15F0_CKGEN01_REG_SW_EN_CLK_128FS_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F4_CKGEN01 (ckgen01 + 0x15F4)
    #define REG_15F4_CKGEN01_REG_SW_EN_CLK_2162MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F8_CKGEN01 (ckgen01 + 0x15F8)
    #define REG_15F8_CKGEN01_REG_SW_EN_CLK_CTS_SYNTH_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15FC_CKGEN01 (ckgen01 + 0x15FC)
    #define REG_15FC_CKGEN01_REG_SW_EN_CLK_CTS_SYNTH_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1600_CKGEN01 (ckgen01 + 0x1600)
    #define REG_1600_CKGEN01_REG_SW_EN_CLK_DET_INNER_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1604_CKGEN01 (ckgen01 + 0x1604)
    #define REG_1604_CKGEN01_REG_SW_EN_CLK_DET_INNER_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1608_CKGEN01 (ckgen01 + 0x1608)
    #define REG_1608_CKGEN01_REG_SW_EN_CLK_DSC_ENGINE2DSC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_160C_CKGEN01 (ckgen01 + 0x160C)
    #define REG_160C_CKGEN01_REG_SW_EN_CLK_DVI2MIU_RD_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1610_CKGEN01 (ckgen01 + 0x1610)
    #define REG_1610_CKGEN01_REG_SW_EN_CLK_DVI2MIU_RD_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1614_CKGEN01 (ckgen01 + 0x1614)
    #define REG_1614_CKGEN01_REG_SW_EN_CLK_DVI2MIU_WR_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1618_CKGEN01 (ckgen01 + 0x1618)
    #define REG_1618_CKGEN01_REG_SW_EN_CLK_DVI2MIU_WR_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_161C_CKGEN01 (ckgen01 + 0x161C)
    #define REG_161C_CKGEN01_REG_SW_EN_CLK_LINK_DSCD2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1620_CKGEN01 (ckgen01 + 0x1620)
    #define REG_1620_CKGEN01_REG_SW_EN_CLK_MPLL_4322MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1624_CKGEN01 (ckgen01 + 0x1624)
    #define REG_1624_CKGEN01_REG_SW_EN_CLK_MPLL_8642PHY Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1628_CKGEN01 (ckgen01 + 0x1628)
    #define REG_1628_CKGEN01_REG_SW_EN_CLK_PIX_TMDSPLL_DSCD2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_162C_CKGEN01 (ckgen01 + 0x162C)
    #define REG_162C_CKGEN01_REG_SW_EN_CLK_PIX_XC_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1630_CKGEN01 (ckgen01 + 0x1630)
    #define REG_1630_CKGEN01_REG_SW_EN_CLK_PIX_XC_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1634_CKGEN01 (ckgen01 + 0x1634)
    #define REG_1634_CKGEN01_REG_SW_EN_CLK_R2_HDMI2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1638_CKGEN01 (ckgen01 + 0x1638)
    #define REG_1638_CKGEN01_REG_SW_EN_CLK_TIMING_DET_DTOP2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_163C_CKGEN01 (ckgen01 + 0x163C)
    #define REG_163C_CKGEN01_REG_SW_EN_CLK_TMDS_AUDIO_S02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1640_CKGEN01 (ckgen01 + 0x1640)
    #define REG_1640_CKGEN01_REG_SW_EN_CLK_TMDS_AUDIO_S12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1644_CKGEN01 (ckgen01 + 0x1644)
    #define REG_1644_CKGEN01_REG_SW_EN_CLK_TMDS_DSCD2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1648_CKGEN01 (ckgen01 + 0x1648)
    #define REG_1648_CKGEN01_REG_SW_EN_CLK_XTAL_242MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_164C_CKGEN01 (ckgen01 + 0x164C)
    #define REG_164C_CKGEN01_REG_SW_EN_CLK_XTAL_HDMI_122MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1650_CKGEN01 (ckgen01 + 0x1650)
    #define REG_1650_CKGEN01_REG_SW_EN_EARC_AUDIO2EARC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1654_CKGEN01 (ckgen01 + 0x1654)
    #define REG_1654_CKGEN01_REG_SW_EN_EARC_CM2EARC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1658_CKGEN01 (ckgen01 + 0x1658)
    #define REG_1658_CKGEN01_REG_SW_EN_EARC_DEBOUNCE2EARC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_165C_CKGEN01 (ckgen01 + 0x165C)
    #define REG_165C_CKGEN01_REG_SW_EN_EARC_DM_PRBS2EARC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1664_CKGEN01 (ckgen01 + 0x1664)
    #define REG_1664_CKGEN01_REG_SW_EN_P0_CLK_DET_DEC_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1668_CKGEN01 (ckgen01 + 0x1668)
    #define REG_1668_CKGEN01_REG_SW_EN_P0_CLK_DET_DEC_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_166C_CKGEN01 (ckgen01 + 0x166C)
    #define REG_166C_CKGEN01_REG_SW_EN_P0_CLK_DET_DEP_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1670_CKGEN01 (ckgen01 + 0x1670)
    #define REG_1670_CKGEN01_REG_SW_EN_P0_CLK_DET_DEP_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1674_CKGEN01 (ckgen01 + 0x1674)
    #define REG_1674_CKGEN01_REG_SW_EN_P0_CLK_LINK2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1678_CKGEN01 (ckgen01 + 0x1678)
    #define REG_1678_CKGEN01_REG_SW_EN_P0_CLK_PIX_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_167C_CKGEN01 (ckgen01 + 0x167C)
    #define REG_167C_CKGEN01_REG_SW_EN_P0_CLK_PIX_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1680_CKGEN01 (ckgen01 + 0x1680)
    #define REG_1680_CKGEN01_REG_SW_EN_P0_CLK_PIX_DC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1684_CKGEN01 (ckgen01 + 0x1684)
    #define REG_1684_CKGEN01_REG_SW_EN_P0_CLK_PIX_RCV_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1688_CKGEN01 (ckgen01 + 0x1688)
    #define REG_1688_CKGEN01_REG_SW_EN_P0_CLK_PIX_REP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_168C_CKGEN01 (ckgen01 + 0x168C)
    #define REG_168C_CKGEN01_REG_SW_EN_P0_CLK_PIX_TMDSPLL2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1690_CKGEN01 (ckgen01 + 0x1690)
    #define REG_1690_CKGEN01_REG_SW_EN_P0_CLK_PIX_XC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1694_CKGEN01 (ckgen01 + 0x1694)
    #define REG_1694_CKGEN01_REG_SW_EN_P0_CLK_TIMING_DET_DEC2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1698_CKGEN01 (ckgen01 + 0x1698)
    #define REG_1698_CKGEN01_REG_SW_EN_P0_CLK_TIMING_DET_DEP2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_169C_CKGEN01 (ckgen01 + 0x169C)
    #define REG_169C_CKGEN01_REG_SW_EN_P0_CLK_TMDS_FRL_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A0_CKGEN01 (ckgen01 + 0x16A0)
    #define REG_16A0_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDCP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A4_CKGEN01 (ckgen01 + 0x16A4)
    #define REG_16A4_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDCP_4P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A8_CKGEN01 (ckgen01 + 0x16A8)
    #define REG_16A8_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDCP_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16AC_CKGEN01 (ckgen01 + 0x16AC)
    #define REG_16AC_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDCP_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B0_CKGEN01 (ckgen01 + 0x16B0)
    #define REG_16B0_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDMI_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B4_CKGEN01 (ckgen01 + 0x16B4)
    #define REG_16B4_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDMI_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B8_CKGEN01 (ckgen01 + 0x16B8)
    #define REG_16B8_CKGEN01_REG_SW_EN_P0_CLK_TMDS_HDMI_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16BC_CKGEN01 (ckgen01 + 0x16BC)
    #define REG_16BC_CKGEN01_REG_SW_EN_P1_CLK_DET_DEC_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C0_CKGEN01 (ckgen01 + 0x16C0)
    #define REG_16C0_CKGEN01_REG_SW_EN_P1_CLK_DET_DEC_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C4_CKGEN01 (ckgen01 + 0x16C4)
    #define REG_16C4_CKGEN01_REG_SW_EN_P1_CLK_DET_DEP_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C8_CKGEN01 (ckgen01 + 0x16C8)
    #define REG_16C8_CKGEN01_REG_SW_EN_P1_CLK_DET_DEP_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16CC_CKGEN01 (ckgen01 + 0x16CC)
    #define REG_16CC_CKGEN01_REG_SW_EN_P1_CLK_LINK2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D0_CKGEN01 (ckgen01 + 0x16D0)
    #define REG_16D0_CKGEN01_REG_SW_EN_P1_CLK_PIX_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D4_CKGEN01 (ckgen01 + 0x16D4)
    #define REG_16D4_CKGEN01_REG_SW_EN_P1_CLK_PIX_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D8_CKGEN01 (ckgen01 + 0x16D8)
    #define REG_16D8_CKGEN01_REG_SW_EN_P1_CLK_PIX_DC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16DC_CKGEN01 (ckgen01 + 0x16DC)
    #define REG_16DC_CKGEN01_REG_SW_EN_P1_CLK_PIX_RCV_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E0_CKGEN01 (ckgen01 + 0x16E0)
    #define REG_16E0_CKGEN01_REG_SW_EN_P1_CLK_PIX_REP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E4_CKGEN01 (ckgen01 + 0x16E4)
    #define REG_16E4_CKGEN01_REG_SW_EN_P1_CLK_PIX_TMDSPLL2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E8_CKGEN01 (ckgen01 + 0x16E8)
    #define REG_16E8_CKGEN01_REG_SW_EN_P1_CLK_PIX_XC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16EC_CKGEN01 (ckgen01 + 0x16EC)
    #define REG_16EC_CKGEN01_REG_SW_EN_P1_CLK_TIMING_DET_DEC2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F0_CKGEN01 (ckgen01 + 0x16F0)
    #define REG_16F0_CKGEN01_REG_SW_EN_P1_CLK_TIMING_DET_DEP2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F4_CKGEN01 (ckgen01 + 0x16F4)
    #define REG_16F4_CKGEN01_REG_SW_EN_P1_CLK_TMDS_FRL_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F8_CKGEN01 (ckgen01 + 0x16F8)
    #define REG_16F8_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDCP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16FC_CKGEN01 (ckgen01 + 0x16FC)
    #define REG_16FC_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDCP_4P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1700_CKGEN01 (ckgen01 + 0x1700)
    #define REG_1700_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDCP_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1704_CKGEN01 (ckgen01 + 0x1704)
    #define REG_1704_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDCP_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1708_CKGEN01 (ckgen01 + 0x1708)
    #define REG_1708_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDMI_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_170C_CKGEN01 (ckgen01 + 0x170C)
    #define REG_170C_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDMI_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1710_CKGEN01 (ckgen01 + 0x1710)
    #define REG_1710_CKGEN01_REG_SW_EN_P1_CLK_TMDS_HDMI_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1714_CKGEN01 (ckgen01 + 0x1714)
    #define REG_1714_CKGEN01_REG_SW_EN_P2_CLK_DET_DEC_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1718_CKGEN01 (ckgen01 + 0x1718)
    #define REG_1718_CKGEN01_REG_SW_EN_P2_CLK_DET_DEC_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_171C_CKGEN01 (ckgen01 + 0x171C)
    #define REG_171C_CKGEN01_REG_SW_EN_P2_CLK_DET_DEP_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1720_CKGEN01 (ckgen01 + 0x1720)
    #define REG_1720_CKGEN01_REG_SW_EN_P2_CLK_DET_DEP_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1724_CKGEN01 (ckgen01 + 0x1724)
    #define REG_1724_CKGEN01_REG_SW_EN_P2_CLK_LINK2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1728_CKGEN01 (ckgen01 + 0x1728)
    #define REG_1728_CKGEN01_REG_SW_EN_P2_CLK_PIX_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_172C_CKGEN01 (ckgen01 + 0x172C)
    #define REG_172C_CKGEN01_REG_SW_EN_P2_CLK_PIX_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1730_CKGEN01 (ckgen01 + 0x1730)
    #define REG_1730_CKGEN01_REG_SW_EN_P2_CLK_PIX_DC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1734_CKGEN01 (ckgen01 + 0x1734)
    #define REG_1734_CKGEN01_REG_SW_EN_P2_CLK_PIX_RCV_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1738_CKGEN01 (ckgen01 + 0x1738)
    #define REG_1738_CKGEN01_REG_SW_EN_P2_CLK_PIX_REP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_173C_CKGEN01 (ckgen01 + 0x173C)
    #define REG_173C_CKGEN01_REG_SW_EN_P2_CLK_PIX_TMDSPLL2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1740_CKGEN01 (ckgen01 + 0x1740)
    #define REG_1740_CKGEN01_REG_SW_EN_P2_CLK_PIX_XC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1744_CKGEN01 (ckgen01 + 0x1744)
    #define REG_1744_CKGEN01_REG_SW_EN_P2_CLK_TIMING_DET_DEC2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1748_CKGEN01 (ckgen01 + 0x1748)
    #define REG_1748_CKGEN01_REG_SW_EN_P2_CLK_TIMING_DET_DEP2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_174C_CKGEN01 (ckgen01 + 0x174C)
    #define REG_174C_CKGEN01_REG_SW_EN_P2_CLK_TMDS_FRL_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1750_CKGEN01 (ckgen01 + 0x1750)
    #define REG_1750_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDCP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1754_CKGEN01 (ckgen01 + 0x1754)
    #define REG_1754_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDCP_4P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1758_CKGEN01 (ckgen01 + 0x1758)
    #define REG_1758_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDCP_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_175C_CKGEN01 (ckgen01 + 0x175C)
    #define REG_175C_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDCP_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1760_CKGEN01 (ckgen01 + 0x1760)
    #define REG_1760_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDMI_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1764_CKGEN01 (ckgen01 + 0x1764)
    #define REG_1764_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDMI_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1768_CKGEN01 (ckgen01 + 0x1768)
    #define REG_1768_CKGEN01_REG_SW_EN_P2_CLK_TMDS_HDMI_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_176C_CKGEN01 (ckgen01 + 0x176C)
    #define REG_176C_CKGEN01_REG_SW_EN_P3_CLK_DET_DEC_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1770_CKGEN01 (ckgen01 + 0x1770)
    #define REG_1770_CKGEN01_REG_SW_EN_P3_CLK_DET_DEC_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1774_CKGEN01 (ckgen01 + 0x1774)
    #define REG_1774_CKGEN01_REG_SW_EN_P3_CLK_DET_DEP_MISC_02MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1778_CKGEN01 (ckgen01 + 0x1778)
    #define REG_1778_CKGEN01_REG_SW_EN_P3_CLK_DET_DEP_MISC_12MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_177C_CKGEN01 (ckgen01 + 0x177C)
    #define REG_177C_CKGEN01_REG_SW_EN_P3_CLK_LINK2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1780_CKGEN01 (ckgen01 + 0x1780)
    #define REG_1780_CKGEN01_REG_SW_EN_P3_CLK_PIX_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1784_CKGEN01 (ckgen01 + 0x1784)
    #define REG_1784_CKGEN01_REG_SW_EN_P3_CLK_PIX_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1788_CKGEN01 (ckgen01 + 0x1788)
    #define REG_1788_CKGEN01_REG_SW_EN_P3_CLK_PIX_DC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_178C_CKGEN01 (ckgen01 + 0x178C)
    #define REG_178C_CKGEN01_REG_SW_EN_P3_CLK_PIX_RCV_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1790_CKGEN01 (ckgen01 + 0x1790)
    #define REG_1790_CKGEN01_REG_SW_EN_P3_CLK_PIX_REP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1794_CKGEN01 (ckgen01 + 0x1794)
    #define REG_1794_CKGEN01_REG_SW_EN_P3_CLK_PIX_TMDSPLL2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1798_CKGEN01 (ckgen01 + 0x1798)
    #define REG_1798_CKGEN01_REG_SW_EN_P3_CLK_PIX_XC_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_179C_CKGEN01 (ckgen01 + 0x179C)
    #define REG_179C_CKGEN01_REG_SW_EN_P3_CLK_TIMING_DET_DEC2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A0_CKGEN01 (ckgen01 + 0x17A0)
    #define REG_17A0_CKGEN01_REG_SW_EN_P3_CLK_TIMING_DET_DEP2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A4_CKGEN01 (ckgen01 + 0x17A4)
    #define REG_17A4_CKGEN01_REG_SW_EN_P3_CLK_TMDS_FRL_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A8_CKGEN01 (ckgen01 + 0x17A8)
    #define REG_17A8_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDCP_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17AC_CKGEN01 (ckgen01 + 0x17AC)
    #define REG_17AC_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDCP_4P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B0_CKGEN01 (ckgen01 + 0x17B0)
    #define REG_17B0_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDCP_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B4_CKGEN01 (ckgen01 + 0x17B4)
    #define REG_17B4_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDCP_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B8_CKGEN01 (ckgen01 + 0x17B8)
    #define REG_17B8_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDMI_1P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17BC_CKGEN01 (ckgen01 + 0x17BC)
    #define REG_17BC_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDMI_8P2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C0_CKGEN01 (ckgen01 + 0x17C0)
    #define REG_17C0_CKGEN01_REG_SW_EN_P3_CLK_TMDS_HDMI_MUX2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C8_CKGEN01 (ckgen01 + 0x17C8)
    #define REG_17C8_CKGEN01_REG_SW_EN_XC_AFBC2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17CC_CKGEN01 (ckgen01 + 0x17CC)
    #define REG_17CC_CKGEN01_REG_SW_EN_XC_GOP0_DST2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17D0_CKGEN01 (ckgen01 + 0x17D0)
    #define REG_17D0_CKGEN01_REG_SW_EN_XC_GOP_SCL2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17D4_CKGEN01 (ckgen01 + 0x17D4)
    #define REG_17D4_CKGEN01_REG_SW_EN_XC_GOP2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17D8_CKGEN01 (ckgen01 + 0x17D8)
    #define REG_17D8_CKGEN01_REG_SW_EN_XC_GOPC_DST2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17DC_CKGEN01 (ckgen01 + 0x17DC)
    #define REG_17DC_CKGEN01_REG_SW_EN_XC_GOPG_DST2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E0_CKGEN01 (ckgen01 + 0x17E0)
    #define REG_17E0_CKGEN01_REG_SW_EN_XC_OD_DELTA2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_17E0_CKGEN01_REG_SW_EN_XC_OD_DELTA2SCIP Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_17E0_CKGEN01_REG_SW_EN_XC_OD_DELTA2SCSCL Fld(1,1,AC_MSKB0)//[1:1]
#define REG_17E4_CKGEN01 (ckgen01 + 0x17E4)
    #define REG_17E4_CKGEN01_REG_SW_EN_XC_OD_DIV22SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E8_CKGEN01 (ckgen01 + 0x17E8)
    #define REG_17E8_CKGEN01_REG_SW_EN_XC_OD_DIV42SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F0_CKGEN01 (ckgen01 + 0x17F0)
    #define REG_17F0_CKGEN01_REG_SW_EN_LPLL_SYN_864_PIPE2FPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F4_CKGEN01 (ckgen01 + 0x17F4)
    #define REG_17F4_CKGEN01_REG_SW_EN_DET_RCLK2DET Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F8_CKGEN01 (ckgen01 + 0x17F8)
    #define REG_17F8_CKGEN01_REG_SW_EN_DET_WCLK2DET Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17FC_CKGEN01 (ckgen01 + 0x17FC)
    #define REG_17FC_CKGEN01_REG_SW_EN_IDCLK2FPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1800_CKGEN01 (ckgen01 + 0x1800)
    #define REG_1800_CKGEN01_REG_SW_EN_LPLL_ODCLK_NODIV2FPLL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1800_CKGEN01_REG_SW_EN_LPLL_ODCLK_NODIV2TTL Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1804_CKGEN01 (ckgen01 + 0x1804)
    #define REG_1804_CKGEN01_REG_SW_EN_LPLL_ODCLK2FPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1808_CKGEN01 (ckgen01 + 0x1808)
    #define REG_1808_CKGEN01_REG_SW_EN_LPLL_SYN_4322FPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_180C_CKGEN01 (ckgen01 + 0x180C)
    #define REG_180C_CKGEN01_REG_SW_EN_LPLL_SYN_8642FPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1810_CKGEN01 (ckgen01 + 0x1810)
    #define REG_1810_CKGEN01_REG_SW_EN_MOD_A_ODCLK2MOD_A Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1814_CKGEN01 (ckgen01 + 0x1814)
    #define REG_1814_CKGEN01_REG_SW_EN_MOD_D_ODCLK2MOD_D Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1814_CKGEN01_REG_SW_EN_MOD_D_ODCLK2LVDS Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1814_CKGEN01_REG_SW_EN_MOD_D_ODCLK2TTL Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1818_CKGEN01 (ckgen01 + 0x1818)
    #define REG_1818_CKGEN01_REG_SW_EN_MOD_O_SR_WCLK2O Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1818_CKGEN01_REG_SW_EN_MOD_O_SR_WCLK2VBY1_O Fld(1,1,AC_MSKB0)//[1:1]
#define REG_181C_CKGEN01 (ckgen01 + 0x181C)
    #define REG_181C_CKGEN01_REG_SW_EN_MOD_V1_SR_WCLK2V1 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_181C_CKGEN01_REG_SW_EN_MOD_V1_SR_WCLK2VBY1_V1 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1820_CKGEN01 (ckgen01 + 0x1820)
    #define REG_1820_CKGEN01_REG_SW_EN_MOD_V2_SR_WCLK2V2 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1820_CKGEN01_REG_SW_EN_MOD_V2_SR_WCLK2VBY1_V2 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1824_CKGEN01 (ckgen01 + 0x1824)
    #define REG_1824_CKGEN01_REG_SW_EN_O_MOD_SR_RCLK2O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1828_CKGEN01 (ckgen01 + 0x1828)
    #define REG_1828_CKGEN01_REG_SW_EN_O_ODCLK_STG12O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_182C_CKGEN01 (ckgen01 + 0x182C)
    #define REG_182C_CKGEN01_REG_SW_EN_O_ODCLK_STG22O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1830_CKGEN01 (ckgen01 + 0x1830)
    #define REG_1830_CKGEN01_REG_SW_EN_O_ODCLK_STG32O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1834_CKGEN01 (ckgen01 + 0x1834)
    #define REG_1834_CKGEN01_REG_SW_EN_O_ODCLK_STG42O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1838_CKGEN01 (ckgen01 + 0x1838)
    #define REG_1838_CKGEN01_REG_SW_EN_O_ODCLK_STG52O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_183C_CKGEN01 (ckgen01 + 0x183C)
    #define REG_183C_CKGEN01_REG_SW_EN_O_ODCLK_STG62O Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN01_6
#define REG_1840_CKGEN01 (ckgen01 + 0x1840)
    #define REG_1840_CKGEN01_REG_SW_EN_O_ODCLK2O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1844_CKGEN01 (ckgen01 + 0x1844)
    #define REG_1844_CKGEN01_REG_SW_EN_PWM2PWM Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1848_CKGEN01 (ckgen01 + 0x1848)
    #define REG_1848_CKGEN01_REG_SW_EN_V1_MOD_SR_RCLK2V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_184C_CKGEN01 (ckgen01 + 0x184C)
    #define REG_184C_CKGEN01_REG_SW_EN_V1_ODCLK_STG12V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1850_CKGEN01 (ckgen01 + 0x1850)
    #define REG_1850_CKGEN01_REG_SW_EN_V1_ODCLK_STG22V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1854_CKGEN01 (ckgen01 + 0x1854)
    #define REG_1854_CKGEN01_REG_SW_EN_V1_ODCLK_STG32V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1858_CKGEN01 (ckgen01 + 0x1858)
    #define REG_1858_CKGEN01_REG_SW_EN_V1_ODCLK_STG42V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_185C_CKGEN01 (ckgen01 + 0x185C)
    #define REG_185C_CKGEN01_REG_SW_EN_V1_ODCLK_STG52V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1860_CKGEN01 (ckgen01 + 0x1860)
    #define REG_1860_CKGEN01_REG_SW_EN_V1_ODCLK_STG62V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1864_CKGEN01 (ckgen01 + 0x1864)
    #define REG_1864_CKGEN01_REG_SW_EN_V1_ODCLK_STG72V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1868_CKGEN01 (ckgen01 + 0x1868)
    #define REG_1868_CKGEN01_REG_SW_EN_V1_ODCLK_STG82V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_186C_CKGEN01 (ckgen01 + 0x186C)
    #define REG_186C_CKGEN01_REG_SW_EN_V1_ODCLK2V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1870_CKGEN01 (ckgen01 + 0x1870)
    #define REG_1870_CKGEN01_REG_SW_EN_V2_MOD_SR_RCLK2V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1874_CKGEN01 (ckgen01 + 0x1874)
    #define REG_1874_CKGEN01_REG_SW_EN_V2_ODCLK_STG12V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1878_CKGEN01 (ckgen01 + 0x1878)
    #define REG_1878_CKGEN01_REG_SW_EN_V2_ODCLK_STG22V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_187C_CKGEN01 (ckgen01 + 0x187C)
    #define REG_187C_CKGEN01_REG_SW_EN_V2_ODCLK_STG32V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1880_CKGEN01 (ckgen01 + 0x1880)
    #define REG_1880_CKGEN01_REG_SW_EN_V2_ODCLK_STG42V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1884_CKGEN01 (ckgen01 + 0x1884)
    #define REG_1884_CKGEN01_REG_SW_EN_V2_ODCLK_STG52V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1888_CKGEN01 (ckgen01 + 0x1888)
    #define REG_1888_CKGEN01_REG_SW_EN_V2_ODCLK_STG62V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_188C_CKGEN01 (ckgen01 + 0x188C)
    #define REG_188C_CKGEN01_REG_SW_EN_V2_ODCLK_STG72V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1890_CKGEN01 (ckgen01 + 0x1890)
    #define REG_1890_CKGEN01_REG_SW_EN_V2_ODCLK2V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1894_CKGEN01 (ckgen01 + 0x1894)
    #define REG_1894_CKGEN01_REG_SW_EN_XTAL_12M2MOD_A Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1894_CKGEN01_REG_SW_EN_XTAL_12M2PWM Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1898_CKGEN01 (ckgen01 + 0x1898)
    #define REG_1898_CKGEN01_REG_SW_EN_XTAL_24M2FPLL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_189C_CKGEN01 (ckgen01 + 0x189C)
    #define REG_189C_CKGEN01_REG_SW_EN_O_MOD_SR_RCLK_FINIAL2O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A0_CKGEN01 (ckgen01 + 0x18A0)
    #define REG_18A0_CKGEN01_REG_SW_EN_O_MOD_SR_RCLK_PRE02O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A4_CKGEN01 (ckgen01 + 0x18A4)
    #define REG_18A4_CKGEN01_REG_SW_EN_O_MOD_SR_RCLK_PRE12O Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A8_CKGEN01 (ckgen01 + 0x18A8)
    #define REG_18A8_CKGEN01_REG_SW_EN_V1_MOD_SR_RCLK_FINIAL2V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18AC_CKGEN01 (ckgen01 + 0x18AC)
    #define REG_18AC_CKGEN01_REG_SW_EN_V1_MOD_SR_RCLK_PRE02V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B0_CKGEN01 (ckgen01 + 0x18B0)
    #define REG_18B0_CKGEN01_REG_SW_EN_V1_MOD_SR_RCLK_PRE12V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B4_CKGEN01 (ckgen01 + 0x18B4)
    #define REG_18B4_CKGEN01_REG_SW_EN_V2_MOD_SR_RCLK_FINIAL2V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B8_CKGEN01 (ckgen01 + 0x18B8)
    #define REG_18B8_CKGEN01_REG_SW_EN_V2_MOD_SR_RCLK_PRE02V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18BC_CKGEN01 (ckgen01 + 0x18BC)
    #define REG_18BC_CKGEN01_REG_SW_EN_V2_MOD_SR_RCLK_PRE12V2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C0_CKGEN01 (ckgen01 + 0x18C0)
    #define REG_18C0_CKGEN01_REG_SW_EN_V1_ODCLK_STG92V1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C8_CKGEN01 (ckgen01 + 0x18C8)
    #define REG_18C8_CKGEN01_REG_SW_EN_AISR_HVSP_SRAM2SCSR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18CC_CKGEN01 (ckgen01 + 0x18CC)
    #define REG_18CC_CKGEN01_REG_SW_EN_XC_FS2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D0_CKGEN01 (ckgen01 + 0x18D0)
    #define REG_18D0_CKGEN01_REG_SW_EN_XC_OD_OSD2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D4_CKGEN01 (ckgen01 + 0x18D4)
    #define REG_18D4_CKGEN01_REG_SW_EN_AISR_SRAM2SCSR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_18D4_CKGEN01_REG_SW_EN_AISR_SRAM_PH_12SCSR Fld(1,1,AC_MSKB0)//[1:1]
#define REG_18D8_CKGEN01 (ckgen01 + 0x18D8)
    #define REG_18D8_CKGEN01_REG_SW_EN_DC0_SRAM2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18DC_CKGEN01 (ckgen01 + 0x18DC)
    #define REG_18DC_CKGEN01_REG_SW_EN_DBK_HW_SRAM2SCPQ Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E0_CKGEN01 (ckgen01 + 0x18E0)
    #define REG_18E0_CKGEN01_REG_SW_EN_DELTA_B2P_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E4_CKGEN01 (ckgen01 + 0x18E4)
    #define REG_18E4_CKGEN01_REG_SW_EN_DELTA_B2P2_SRAM2SCACE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E8_CKGEN01 (ckgen01 + 0x18E8)
    #define REG_18E8_CKGEN01_REG_SW_EN_DEMURA_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18EC_CKGEN01 (ckgen01 + 0x18EC)
    #define REG_18EC_CKGEN01_REG_SW_EN_DV_HW5_SRAM2SCDV Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F0_CKGEN01 (ckgen01 + 0x18F0)
    #define REG_18F0_CKGEN01_REG_SW_EN_GOP0_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F4_CKGEN01 (ckgen01 + 0x18F4)
    #define REG_18F4_CKGEN01_REG_SW_EN_GOP1_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F8_CKGEN01 (ckgen01 + 0x18F8)
    #define REG_18F8_CKGEN01_REG_SW_EN_GOP2_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18FC_CKGEN01 (ckgen01 + 0x18FC)
    #define REG_18FC_CKGEN01_REG_SW_EN_GOP3_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1900_CKGEN01 (ckgen01 + 0x1900)
    #define REG_1900_CKGEN01_REG_SW_EN_GUCD_18_LUT2_SRAM2SCACE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1904_CKGEN01 (ckgen01 + 0x1904)
    #define REG_1904_CKGEN01_REG_SW_EN_GUCD_18_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1908_CKGEN01 (ckgen01 + 0x1908)
    #define REG_1908_CKGEN01_REG_SW_EN_GUCD_256_LUT2_SRAM2SCACE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_190C_CKGEN01 (ckgen01 + 0x190C)
    #define REG_190C_CKGEN01_REG_SW_EN_GUCD_256_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1910_CKGEN01 (ckgen01 + 0x1910)
    #define REG_1910_CKGEN01_REG_SW_EN_HSY_8P_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1910_CKGEN01_REG_SW_EN_HSY_8P_SRAM2SCACE Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1914_CKGEN01 (ckgen01 + 0x1914)
    #define REG_1914_CKGEN01_REG_SW_EN_HSY_8P3_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1914_CKGEN01_REG_SW_EN_HSY_8P3_SRAM2SCACE Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1918_CKGEN01 (ckgen01 + 0x1918)
    #define REG_1918_CKGEN01_REG_SW_EN_HSY_SP_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_191C_CKGEN01 (ckgen01 + 0x191C)
    #define REG_191C_CKGEN01_REG_SW_EN_HSY_SP3_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1920_CKGEN01 (ckgen01 + 0x1920)
    #define REG_1920_CKGEN01_REG_SW_EN_HVSP_STP1_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1924_CKGEN01 (ckgen01 + 0x1924)
    #define REG_1924_CKGEN01_REG_SW_EN_HVSP_STP2_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1928_CKGEN01 (ckgen01 + 0x1928)
    #define REG_1928_CKGEN01_REG_SW_EN_LCE_ACE_SRAM2SCACE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_192C_CKGEN01 (ckgen01 + 0x192C)
    #define REG_192C_CKGEN01_REG_SW_EN_LCE_SCL_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1930_CKGEN01 (ckgen01 + 0x1930)
    #define REG_1930_CKGEN01_REG_SW_EN_LD_EDGE2D_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1934_CKGEN01 (ckgen01 + 0x1934)
    #define REG_1934_CKGEN01_REG_SW_EN_LDCOMP_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1938_CKGEN01 (ckgen01 + 0x1938)
    #define REG_1938_CKGEN01_REG_SW_EN_LDM_GA_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_193C_CKGEN01 (ckgen01 + 0x193C)
    #define REG_193C_CKGEN01_REG_SW_EN_LDMCG_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1940_CKGEN01 (ckgen01 + 0x1940)
    #define REG_1940_CKGEN01_REG_SW_EN_LPQ_PA_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1944_CKGEN01 (ckgen01 + 0x1944)
    #define REG_1944_CKGEN01_REG_SW_EN_OSD_DV_HW5_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1948_CKGEN01 (ckgen01 + 0x1948)
    #define REG_1948_CKGEN01_REG_SW_EN_PADJ_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_194C_CKGEN01 (ckgen01 + 0x194C)
    #define REG_194C_CKGEN01_REG_SW_EN_PANEL_GA_SRAM2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1950_CKGEN01 (ckgen01 + 0x1950)
    #define REG_1950_CKGEN01_REG_SW_EN_PQ_GAMMA_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1954_CKGEN01 (ckgen01 + 0x1954)
    #define REG_1954_CKGEN01_REG_SW_EN_RGB_3DLUT_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1958_CKGEN01 (ckgen01 + 0x1958)
    #define REG_1958_CKGEN01_REG_SW_EN_SCNR_HDR_SRAM2SCPQ Fld(1,0,AC_MSKB0)//[0:0]
#define REG_195C_CKGEN01 (ckgen01 + 0x195C)
    #define REG_195C_CKGEN01_REG_SW_EN_SPF_HDBK_SRAM2SCPQ Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1960_CKGEN01 (ckgen01 + 0x1960)
    #define REG_1960_CKGEN01_REG_SW_EN_UCD_ST_SRAM2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1964_CKGEN01 (ckgen01 + 0x1964)
    #define REG_1964_CKGEN01_REG_SW_EN_VDBK_SRAM2SCPQ Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1968_CKGEN01 (ckgen01 + 0x1968)
    #define REG_1968_CKGEN01_REG_SW_EN_VIP_ACE_SRAM2SCACE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_196C_CKGEN01 (ckgen01 + 0x196C)
    #define REG_196C_CKGEN01_REG_SW_EN_VIP_PQ_SRAM2SCSCL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1970_CKGEN01 (ckgen01 + 0x1970)
    #define REG_1970_CKGEN01_REG_SW_EN_XC_ADC2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1974_CKGEN01 (ckgen01 + 0x1974)
    #define REG_1974_CKGEN01_REG_SW_EN_XC_AISR2SCSR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1978_CKGEN01 (ckgen01 + 0x1978)
    #define REG_1978_CKGEN01_REG_SW_EN_XC_SUB_DC02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_197C_CKGEN01 (ckgen01 + 0x197C)
    #define REG_197C_CKGEN01_REG_SW_EN_XC_DC02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1980_CKGEN01 (ckgen01 + 0x1980)
    #define REG_1980_CKGEN01_REG_SW_EN_XC_DBG2MIU2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1984_CKGEN01 (ckgen01 + 0x1984)
    #define REG_1984_CKGEN01_REG_SW_EN_XC_DISP_MFDEC2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1988_CKGEN01 (ckgen01 + 0x1988)
    #define REG_1988_CKGEN01_REG_SW_EN_XC_ED02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_198C_CKGEN01 (ckgen01 + 0x198C)
    #define REG_198C_CKGEN01_REG_SW_EN_XC_ED12SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1990_CKGEN01 (ckgen01 + 0x1990)
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCMW Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCTCON Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCIP Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD2SCSCL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD_ABF2SCTCON Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD_GOP02SCTCON Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1990_CKGEN01_REG_SW_EN_XC_FD_DV2SCTCON Fld(1,6,AC_MSKB0)//[6:6]
#define REG_1994_CKGEN01 (ckgen01 + 0x1994)
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCDV Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCIP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCM Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCMO Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCMW Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCNR Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCPQ_DOLBY Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCPQ_SPF Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCSCL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCSR Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN2SCTCON Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1994_CKGEN01_REG_SW_EN_XC_FN_22SCDV Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1998_CKGEN01 (ckgen01 + 0x1998)
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCACE_HSY Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCACE_VIP Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCACE_VOP2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCMW Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCSCL Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCSR Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1998_CKGEN01_REG_SW_EN_XC_FS2SCIP Fld(1,6,AC_MSKB0)//[6:6]
#define REG_199C_CKGEN01 (ckgen01 + 0x199C)
    #define REG_199C_CKGEN01_REG_SW_EN_XC_HD2MIU_M2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A0_CKGEN01 (ckgen01 + 0x19A0)
    #define REG_19A0_CKGEN01_REG_SW_EN_XC_HD2MIU_S2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A4_CKGEN01 (ckgen01 + 0x19A4)
    #define REG_19A4_CKGEN01_REG_SW_EN_XC_HDMI02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A8_CKGEN01 (ckgen01 + 0x19A8)
    #define REG_19A8_CKGEN01_REG_SW_EN_XC_HDMI12SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19AC_CKGEN01 (ckgen01 + 0x19AC)
    #define REG_19AC_CKGEN01_REG_SW_EN_XC_HDMI22SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B0_CKGEN01 (ckgen01 + 0x19B0)
    #define REG_19B0_CKGEN01_REG_SW_EN_XC_HDMI32SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B4_CKGEN01 (ckgen01 + 0x19B4)
    #define REG_19B4_CKGEN01_REG_SW_EN_XC_ID02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B8_CKGEN01 (ckgen01 + 0x19B8)
    #define REG_19B8_CKGEN01_REG_SW_EN_XC_ID12SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19BC_CKGEN01 (ckgen01 + 0x19BC)
    #define REG_19BC_CKGEN01_REG_SW_EN_XC_IP2_SRC2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C0_CKGEN01 (ckgen01 + 0x19C0)
    #define REG_19C0_CKGEN01_REG_SW_EN_XC_MFDEC2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C4_CKGEN01 (ckgen01 + 0x19C4)
    #define REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCMW Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCTCON Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCIP Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_19C4_CKGEN01_REG_SW_EN_XC_OD2SCSCL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_19C4_CKGEN01_REG_SW_EN_XC_OD_EDGE2SCTCON Fld(1,4,AC_MSKB0)//[4:4]
#define REG_19C8_CKGEN01 (ckgen01 + 0x19C8)
    #define REG_19C8_CKGEN01_REG_SW_EN_XC_SLOW2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19CC_CKGEN01 (ckgen01 + 0x19CC)
    #define REG_19CC_CKGEN01_REG_SW_EN_XC_SR_ALAI2SCSR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D0_CKGEN01 (ckgen01 + 0x19D0)
    #define REG_19D0_CKGEN01_REG_SW_EN_XC_SR_SRAM_SHARE2SCSR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D4_CKGEN01 (ckgen01 + 0x19D4)
    #define REG_19D4_CKGEN01_REG_SW_EN_XC_SRS2SCSR Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D8_CKGEN01 (ckgen01 + 0x19D8)
    #define REG_19D8_CKGEN01_REG_SW_EN_XC_TGEN_WIN2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19DC_CKGEN01 (ckgen01 + 0x19DC)
    #define REG_19DC_CKGEN01_REG_SW_EN_XC_UCD_STAT2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19E0_CKGEN01 (ckgen01 + 0x19E0)
    #define REG_19E0_CKGEN01_REG_SW_EN_XC_VD2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19E4_CKGEN01 (ckgen01 + 0x19E4)
    #define REG_19E4_CKGEN01_REG_SW_EN_XC_VE2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19E8_CKGEN01 (ckgen01 + 0x19E8)
    #define REG_19E8_CKGEN01_REG_SW_EN_XCPLL_SYN2XCPLL_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19EC_CKGEN01 (ckgen01 + 0x19EC)
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCACE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCDV Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCNR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCSCL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCSR Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCTCON Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_19EC_CKGEN01_REG_SW_EN_XTAL_12M2SCIP Fld(1,6,AC_MSKB0)//[6:6]
#define REG_19F0_CKGEN01 (ckgen01 + 0x19F0)
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCACE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCDV Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCIP Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCMW Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCNR Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCPQ Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCSCL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCSR Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_19F0_CKGEN01_REG_SW_EN_XTAL_24M2SCTCON Fld(1,8,AC_MSKB1)//[8:8]
#define REG_19F4_CKGEN01 (ckgen01 + 0x19F4)
    #define REG_19F4_CKGEN01_REG_SW_EN_XTAL_IP12SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19F8_CKGEN01 (ckgen01 + 0x1F8)
    #define REG_19F8_CKGEN01_REG_SW_EN_XC_SUB1_DC02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19FC_CKGEN01 (ckgen01 + 0x1FC)
    #define REG_19FC_CKGEN01_REG_SW_EN_XVYCC_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A00_CKGEN01 (ckgen01 + 0x1A00)
    #define REG_1A00_CKGEN01_REG_SW_EN_SIDCLK_HD02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A04_CKGEN01 (ckgen01 + 0x1A04)
    #define REG_1A04_CKGEN01_REG_SW_EN_SIDCLK_HD12SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A08_CKGEN01 (ckgen01 + 0x1A08)
    #define REG_1A08_CKGEN01_REG_SW_EN_SIDCLK_HD22SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A0C_CKGEN01 (ckgen01 + 0x1A0C)
    #define REG_1A0C_CKGEN01_REG_SW_EN_SIDCLK_HD32SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A10_CKGEN01 (ckgen01 + 0x1A10)
    #define REG_1A10_CKGEN01_REG_SW_EN_XC_DIP02SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A14_CKGEN01 (ckgen01 + 0x1A14)
    #define REG_1A14_CKGEN01_REG_SW_EN_XC_DIP12SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A18_CKGEN01 (ckgen01 + 0x1A18)
    #define REG_1A18_CKGEN01_REG_SW_EN_XC_DIP22SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A1C_CKGEN01 (ckgen01 + 0x1A1C)
    #define REG_1A1C_CKGEN01_REG_SW_EN_XC_VEDAC2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A20_CKGEN01 (ckgen01 + 0x1A20)
    #define REG_1A20_CKGEN01_REG_SW_EN_XC_VEIN2SCIP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A24_CKGEN01 (ckgen01 + 0x1A24)
    #define REG_1A24_CKGEN01_REG_SW_EN_DIP1_HVSP_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A28_CKGEN01 (ckgen01 + 0x1A28)
    #define REG_1A28_CKGEN01_REG_SW_EN_DIP1_XVYCC_SRAM2SCMW Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A2C_CKGEN01 (ckgen01 + 0x1A2C)
    #define REG_1A2C_CKGEN01_REG_SW_EN_CMBAI2VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A30_CKGEN01 (ckgen01 + 0x1A30)
    #define REG_1A30_CKGEN01_REG_SW_EN_CMBAO2VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A34_CKGEN01 (ckgen01 + 0x1A34)
    #define REG_1A34_CKGEN01_REG_SW_EN_CMBBI2VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A38_CKGEN01 (ckgen01 + 0x1A38)
    #define REG_1A38_CKGEN01_REG_SW_EN_CMBBO2VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A3C_CKGEN01 (ckgen01 + 0x1A3C)
    #define REG_1A3C_CKGEN01_REG_SW_EN_MCU_MAIL02VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A40_CKGEN01 (ckgen01 + 0x1A40)
    #define REG_1A40_CKGEN01_REG_SW_EN_MCU_MAIL12VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A44_CKGEN01 (ckgen01 + 0x1A44)
    #define REG_1A44_CKGEN01_REG_SW_EN_VD_32FSC2VD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A48_CKGEN01 (ckgen01 + 0x1A48)
    #define REG_1A48_CKGEN01_REG_SW_EN_VD2MHEG5_ADC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A48_CKGEN01_REG_SW_EN_VD2VD Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A4C_CKGEN01 (ckgen01 + 0x1A4C)
    #define REG_1A4C_CKGEN01_REG_SW_EN_VD2X2MHEG5_ADC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A4C_CKGEN01_REG_SW_EN_VD2X2VD Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A50_CKGEN01 (ckgen01 + 0x1A50)
    #define REG_1A50_CKGEN01_REG_SW_EN_XC_OD_META2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A54_CKGEN01 (ckgen01 + 0x1A54)
    #define REG_1A54_CKGEN01_REG_SW_EN_XC_OD_DELTA_META2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A58_CKGEN01 (ckgen01 + 0x1A58)
    #define REG_1A58_CKGEN01_REG_SW_EN_VENC2VENC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A58_CKGEN01_REG_SW_EN_VENC2VENC_IP_1A58 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A5C_CKGEN01 (ckgen01 + 0x1A5C)
    #define REG_1A5C_CKGEN01_REG_SW_EN_XC_OD_OSD_META2SCTCON Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A60_CKGEN01 (ckgen01 + 0x1A60)
    #define REG_1A60_CKGEN01_REG_SW_EN_CLK_IP_1X_N2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A64_CKGEN01 (ckgen01 + 0x1A64)
    #define REG_1A64_CKGEN01_REG_SW_EN_CLK_IP_1X2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A68_CKGEN01 (ckgen01 + 0x1A68)
    #define REG_1A68_CKGEN01_REG_SW_EN_CLK_M_2X_N2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A6C_CKGEN01 (ckgen01 + 0x1A6C)
    #define REG_1A6C_CKGEN01_REG_SW_EN_CLK_M_2X2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]

//Page CKGEN01_7
#define REG_1A70_CKGEN01 (ckgen01 + 0x1A70)
    #define REG_1A70_CKGEN01_REG_SW_EN_CLK_M_4X_MID2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A74_CKGEN01 (ckgen01 + 0x1A74)
    #define REG_1A74_CKGEN01_REG_SW_EN_CLK_M_4X2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A78_CKGEN01 (ckgen01 + 0x1A78)
    #define REG_1A78_CKGEN01_REG_SW_EN_FB_MCLK2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A7C_CKGEN01 (ckgen01 + 0x1A7C)
    #define REG_1A7C_CKGEN01_REG_SW_EN_MPLL2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A80_CKGEN01 (ckgen01 + 0x1A80)
    #define REG_1A80_CKGEN01_REG_SW_EN_OSP2FLASH_DMACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A84_CKGEN01 (ckgen01 + 0x1A84)
    #define REG_1A84_CKGEN01_REG_SW_EN_ECC2FCIE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A88_CKGEN01 (ckgen01 + 0x1A88)
    #define REG_1A88_CKGEN01_REG_SW_EN_FCIE_N2FCIE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A8C_CKGEN01 (ckgen01 + 0x1A8C)
    #define REG_1A8C_CKGEN01_REG_SW_EN_FCIE2FCIE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A8C_CKGEN01_REG_SW_EN_FCIE2SD_SDR_MACRO Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A90_CKGEN01 (ckgen01 + 0x1A90)
    #define REG_1A90_CKGEN01_REG_SW_EN_PAD_SD2SD_SDR_MACRO Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A94_CKGEN01 (ckgen01 + 0x1A94)
    #define REG_1A94_CKGEN01_REG_SW_EN_EMMC_DQS_SKEW2EMMC_DQS_SKEW Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A94_CKGEN01_REG_SW_EN_EMMC_DQS_SKEW2SD_DQS_SKEW Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A98_CKGEN01 (ckgen01 + 0x1A98)
    #define REG_1A98_CKGEN01_REG_SW_EN_EMMC_DQS_DLY_N2SKEW_LATCH Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1A98_CKGEN01_REG_SW_EN_EMMC_DQS_DLY_N2DQS Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1A9C_CKGEN01 (ckgen01 + 0x1A9C)
    #define REG_1A9C_CKGEN01_REG_SW_EN_EMMC_DQS_DLY_2ND_N2SKEW_LATCH_CMD Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AAC_CKGEN01 (ckgen01 + 0x1AAC)
    #define REG_1AAC_CKGEN01_REG_SW_EN_GMAC_AHB2GMAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB0_CKGEN01 (ckgen01 + 0x1AB0)
    #define REG_1AB0_CKGEN01_REG_SW_EN_GMAC_REF2GMAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB4_CKGEN01 (ckgen01 + 0x1AB4)
    #define REG_1AB4_CKGEN01_REG_SW_EN_GMAC_RX2GMAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB8_CKGEN01 (ckgen01 + 0x1AB8)
    #define REG_1AB8_CKGEN01_REG_SW_EN_GMAC_TX2GMAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ACC_CKGEN01 (ckgen01 + 0x1ACC)
    #define REG_1ACC_CKGEN01_REG_SW_EN_AU_UART0_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD0_CKGEN01 (ckgen01 + 0x1AD0)
    #define REG_1AD0_CKGEN01_REG_SW_EN_AU_UART02AU_UART0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD4_CKGEN01 (ckgen01 + 0x1AD4)
    #define REG_1AD4_CKGEN01_REG_SW_EN_FRC_FUART0_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD8_CKGEN01 (ckgen01 + 0x1AD8)
    #define REG_1AD8_CKGEN01_REG_SW_EN_FRC_FUART02FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1AD8_CKGEN01_REG_SW_EN_FRC_FUART02FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1ADC_CKGEN01 (ckgen01 + 0x1ADC)
    #define REG_1ADC_CKGEN01_REG_SW_EN_FRC_MSPI0_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE0_CKGEN01 (ckgen01 + 0x1AE0)
    #define REG_1AE0_CKGEN01_REG_SW_EN_FRC_MSPI02FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1AE0_CKGEN01_REG_SW_EN_FRC_MSPI02FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1AE4_CKGEN01 (ckgen01 + 0x1AE4)
    #define REG_1AE4_CKGEN01_REG_SW_EN_FRC_UART0_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE8_CKGEN01 (ckgen01 + 0x1AE8)
    #define REG_1AE8_CKGEN01_REG_SW_EN_FRC_UART02FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1AE8_CKGEN01_REG_SW_EN_FRC_UART02FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1AEC_CKGEN01 (ckgen01 + 0x1AEC)
    #define REG_1AEC_CKGEN01_REG_SW_EN_FRC_UART1_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF0_CKGEN01 (ckgen01 + 0x1AF0)
    #define REG_1AF0_CKGEN01_REG_SW_EN_FRC_UART12FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1AF0_CKGEN01_REG_SW_EN_FRC_UART12FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1AF4_CKGEN01 (ckgen01 + 0x1AF4)
    #define REG_1AF4_CKGEN01_REG_SW_EN_FUART0_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF8_CKGEN01 (ckgen01 + 0x1AF8)
    #define REG_1AF8_CKGEN01_REG_SW_EN_FUART02MCU_FUART0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AFC_CKGEN01 (ckgen01 + 0x1AFC)
    #define REG_1AFC_CKGEN01_REG_SW_EN_UART0_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B00_CKGEN01 (ckgen01 + 0x1B00)
    #define REG_1B00_CKGEN01_REG_SW_EN_UART02MCU_UART0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B04_CKGEN01 (ckgen01 + 0x1B04)
    #define REG_1B04_CKGEN01_REG_SW_EN_UART1_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B08_CKGEN01 (ckgen01 + 0x1B08)
    #define REG_1B08_CKGEN01_REG_SW_EN_UART12MCU_UART1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B0C_CKGEN01 (ckgen01 + 0x1B0C)
    #define REG_1B0C_CKGEN01_REG_SW_EN_UART2_SYNTH2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B10_CKGEN01 (ckgen01 + 0x1B10)
    #define REG_1B10_CKGEN01_REG_SW_EN_UART22MCU_UART2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B44_CKGEN01 (ckgen01 + 0x1B44)
    #define REG_1B44_CKGEN01_REG_SW_EN_MCU_AU2AUDIO_R2 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B44_CKGEN01_REG_SW_EN_MCU_AU2RV55AUDIO Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1B4C_CKGEN01 (ckgen01 + 0x1B4C)
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2MAC Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2SCSCL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1B4C_CKGEN01_REG_SW_EN_AU_MCU_BUS2AU_MCU Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2DEMOD0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2MCU_M2MCU Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2RV55FRC Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2RV55PQU Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2MCU_NONPM_RIU_BRIDGE Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2MCU_CODEC_RIU_BRIDGE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1B4C_CKGEN01_REG_SW_EN_MCU_BUS2MCUSYS_XIU_BRIDGE Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1B54_CKGEN01 (ckgen01 + 0x1B54)
    #define REG_1B54_CKGEN01_REG_SW_EN_MCU_CODEC2MCU_CODEC_RIU_BRIDGE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B54_CKGEN01_REG_SW_EN_MCU_CODEC2SECURE_TOP_CODEC Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1B5C_CKGEN01 (ckgen01 + 0x1B5C)
    #define REG_1B5C_CKGEN01_REG_SW_EN_MCU_DMD2DEMOD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B64_CKGEN01 (ckgen01 + 0x1B64)
    #define REG_1B64_CKGEN01_REG_SW_EN_MCU_FRC2FRCIOPM Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B64_CKGEN01_REG_SW_EN_MCU_FRC2FRCIOPMRV55 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B64_CKGEN01_REG_SW_EN_MCU_FRC2RV55FRC Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B64_CKGEN01_REG_SW_EN_MCU_FRC2RV55PQU Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1B6C_CKGEN01 (ckgen01 + 0x1B6C)
    #define REG_1B6C_CKGEN01_REG_SW_EN_MCU_HDMI2MAC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1B74_CKGEN01 (ckgen01 + 0x1B74)
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2CHIP_REG Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2CMDQ Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2DEMOD0 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2DSCRMB Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2FCIE Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2PAD_TOP Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2FRCIOPMRV55 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2FRCMEHALO Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2GE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2GMAC Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2GPD Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2GPU_DIE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2GPU_NODIE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2INTR_CTRL_TOP_WP Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2MAC Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1B74_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_BDMA Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B78_CKGEN01 (ckgen01 + 0x1B78)
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_DEMURA Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_FUART Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MAILBOX0 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MAILBOX1 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MAILBOX2 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MAILBOX3 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MAILBOX4 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MAILBOX5 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MCUIF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MIIC0 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MIIC1 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MIIC2 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MIIC3 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_MSPI_ALL Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_FMLY_ROM Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1B78_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_NONPM_RIU_BRIDGE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B7C_CKGEN01 (ckgen01 + 0x1B7C)
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_UART0 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_UART1 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_UART2 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2MCU_XD2MIU Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2MCUSYS_XIU_BRIDGE Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2MHEG5_SMI Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2PEXTP Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2PEXTP_PHY_TOP Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2PREARB2PM_RIU_TOP Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2RV55FRC Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2RV55PQU Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2SCACE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2SCDV Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2SCIP Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1B7C_CKGEN01_REG_SW_EN_MCU_NONPM2SCMW Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B80_CKGEN01 (ckgen01 + 0x1B80)
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SCNR Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SCPQ Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SCSCL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SCSR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SCTCON Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SMART0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SMART1 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SSUSB Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_P1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2TSP Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2TSP_SMI Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2UFS Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2UFS_PHY Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1B80_CKGEN01_REG_SW_EN_MCU_NONPM2USB20 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1B84_CKGEN01 (ckgen01 + 0x1B84)
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2VD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2VENC Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1B84_CKGEN01_REG_SW_EN_XIU2GCE_BIU Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2XIU2APB Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2IP_WRAP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2VIVA_SMI Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2VIVA_VBDMA Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2FRCCORE1_1B84 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2FRCCORE2_1B84 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2FRCCORE3_1B84 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2FRCMISC_1B84 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1B84_CKGEN01_REG_SW_EN_MCU_NONPM2SCDISP_1B84 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1BAC_CKGEN01 (ckgen01 + 0x1BAC)
    #define REG_1BAC_CKGEN01_REG_SW_EN_MCU_VD2MCU_M2MCU Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1BAC_CKGEN01_REG_SW_EN_MCU_VD2MCU_MCUIF Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1BAC_CKGEN01_REG_SW_EN_MCU_VD2VD Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1BB4_CKGEN01 (ckgen01 + 0x1BB4)
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_SC2RV55FRC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_SC2RV55PQU Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCACE Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCDV Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCIP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCMW Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCNR Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCPQ Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCSCL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCSR Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCTCON Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1BB4_CKGEN01_REG_SW_EN_MCU_XC2SCDISP_1BB4 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1BC4_CKGEN01 (ckgen01 + 0x1BC4)
    #define REG_1BC4_CKGEN01_REG_SW_EN_MIIC02MCU_MIIC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC8_CKGEN01 (ckgen01 + 0x1BC8)
    #define REG_1BC8_CKGEN01_REG_SW_EN_MIIC12MCU_MIIC1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BCC_CKGEN01 (ckgen01 + 0x1BCC)
    #define REG_1BCC_CKGEN01_REG_SW_EN_MIIC22MCU_MIIC2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD0_CKGEN01 (ckgen01 + 0x1BD0)
    #define REG_1BD0_CKGEN01_REG_SW_EN_MIIC32MCU_MIIC3 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE4_CKGEN01 (ckgen01 + 0x1BE4)
    #define REG_1BE4_CKGEN01_REG_SW_EN_MSPI12MCU_MSPI1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE8_CKGEN01 (ckgen01 + 0x1BE8)
    #define REG_1BE8_CKGEN01_REG_SW_EN_MSPI22MCU_MSPI2 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BEC_CKGEN01 (ckgen01 + 0x1BEC)
    #define REG_1BEC_CKGEN01_REG_SW_EN_MSPI32MCU_MSPI3 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF0_CKGEN01 (ckgen01 + 0x1BF0)
    #define REG_1BF0_CKGEN01_REG_SW_EN_MSPI42MCU_MSPI4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF4_CKGEN01 (ckgen01 + 0x1BF4)
    #define REG_1BF4_CKGEN01_REG_SW_EN_MSPI52MCU_MSPI5 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF8_CKGEN01 (ckgen01 + 0x1BF8)
    #define REG_1BF8_CKGEN01_REG_SW_EN_MSPI62MCU_MSPI6 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BFC_CKGEN01 (ckgen01 + 0x1BFC)
    #define REG_1BFC_CKGEN01_REG_SW_EN_MSPI72MCU_MSPI7 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C00_CKGEN01 (ckgen01 + 0x1C00)
    #define REG_1C00_CKGEN01_REG_SW_EN_MSPI_CILINK_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C04_CKGEN01 (ckgen01 + 0x1C04)
    #define REG_1C04_CKGEN01_REG_SW_EN_MSPI_CILINK2MCU_MSPI_CILINK Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C08_CKGEN01 (ckgen01 + 0x1C08)
    #define REG_1C08_CKGEN01_REG_SW_EN_MSPI0_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C0C_CKGEN01 (ckgen01 + 0x1C0C)
    #define REG_1C0C_CKGEN01_REG_SW_EN_MSPI1_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C10_CKGEN01 (ckgen01 + 0x1C10)
    #define REG_1C10_CKGEN01_REG_SW_EN_MSPI2_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C14_CKGEN01 (ckgen01 + 0x1C14)
    #define REG_1C14_CKGEN01_REG_SW_EN_MSPI02MCU_MSPI0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C18_CKGEN01 (ckgen01 + 0x1C18)
    #define REG_1C18_CKGEN01_REG_SW_EN_MSPI3_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C1C_CKGEN01 (ckgen01 + 0x1C1C)
    #define REG_1C1C_CKGEN01_REG_SW_EN_MSPI4_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C20_CKGEN01 (ckgen01 + 0x1C20)
    #define REG_1C20_CKGEN01_REG_SW_EN_MSPI5_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C24_CKGEN01 (ckgen01 + 0x1C24)
    #define REG_1C24_CKGEN01_REG_SW_EN_MSPI6_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C28_CKGEN01 (ckgen01 + 0x1C28)
    #define REG_1C28_CKGEN01_REG_SW_EN_MSPI7_DIV2MCU_CKCTRL_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C34_CKGEN01 (ckgen01 + 0x1C34)
    #define REG_1C34_CKGEN01_REG_SW_EN_SPI2MCU_SPI Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1C34_CKGEN01_REG_SW_EN_SPI2MCUSYS_XIU_BRIDGE Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1C54_CKGEN01 (ckgen01 + 0x1C54)
    #define REG_1C54_CKGEN01_REG_SW_EN_XTAL_12M2PEXTP_PHY_TOP Fld(1,0,AC _MSKB0)//[0:0]
#define REG_1C58_CKGEN01 (ckgen01 + 0x1C58)
    #define REG_1C58_CKGEN01_REG_SW_EN_PEXTP_AHB_APB2PEXTP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C60_CKGEN01 (ckgen01 + 0x1C60)
    #define REG_1C60_CKGEN01_REG_SW_EN_PEXTP_PL_PCLK2PEXTP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C64_CKGEN01 (ckgen01 + 0x1C64)
    #define REG_1C64_CKGEN01_REG_SW_EN_PEXTP_TL2PEXTP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C78_CKGEN01 (ckgen01 + 0x1C78)
    #define REG_1C78_CKGEN01_REG_SW_EN_UFS_AES2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C7C_CKGEN01 (ckgen01 + 0x1C7C)
    #define REG_1C7C_CKGEN01_REG_SW_EN_UFS_AHB2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C84_CKGEN01 (ckgen01 + 0x1C84)
    #define REG_1C84_CKGEN01_REG_SW_EN_UFS_MP_SAP_CFG2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C88_CKGEN01 (ckgen01 + 0x1C88)
    #define REG_1C88_CKGEN01_REG_SW_EN_UFS_RX_SYMBOL2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C8C_CKGEN01 (ckgen01 + 0x1C8C)
    #define REG_1C8C_CKGEN01_REG_SW_EN_UFS_TX_SYMBOL2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C90_CKGEN01 (ckgen01 + 0x1C90)
    #define REG_1C90_CKGEN01_REG_SW_EN_UFS_UNIPRO_CG_SYN2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C94_CKGEN01 (ckgen01 + 0x1C94)
    #define REG_1C94_CKGEN01_REG_SW_EN_UFS2UFS Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C98_CKGEN01 (ckgen01 + 0x1C98)
    #define REG_1C98_CKGEN01_REG_SW_EN_UFS_PHY_SCAN_150M2UFS_PHY Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C9C_CKGEN01 (ckgen01 + 0x1C9C)
    #define REG_1C9C_CKGEN01_REG_SW_EN_UFS_PHY_SCAN_300M2UFS_PHY Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA0_CKGEN01 (ckgen01 + 0x1CA0)
    #define REG_1CA0_CKGEN01_REG_SW_EN_UFS_PHY_SCAN_600M2UFS_PHY Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA4_CKGEN01 (ckgen01 + 0x1CA4)
    #define REG_1CA4_CKGEN01_REG_SW_EN_UFS_PHY_SCAN_26M2UFS_PHY Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB4_CKGEN01 (ckgen01 + 0x1CB4)
    #define REG_1CB4_CKGEN01_REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB8_CKGEN01 (ckgen01 + 0x1CB8)
    #define REG_1CB8_CKGEN01_REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_P1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CBC_CKGEN01 (ckgen01 + 0x1CBC)
    #define REG_1CBC_CKGEN01_REG_SW_EN_XTAL_12M2SSUSB_U2_PHY_TOP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC0_CKGEN01 (ckgen01 + 0x1CC0)
    #define REG_1CC0_CKGEN01_REG_SW_EN_SSUSB_FRMCNT2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC4_CKGEN01 (ckgen01 + 0x1CC4)
    #define REG_1CC4_CKGEN01_REG_SW_EN_SSUSB_PCLK_1P2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC8_CKGEN01 (ckgen01 + 0x1CC8)
    #define REG_1CC8_CKGEN01_REG_SW_EN_SSUSB_PCLK2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CCC_CKGEN01 (ckgen01 + 0x1CCC)
    #define REG_1CCC_CKGEN01_REG_SW_EN_SSUSB_SCL2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD0_CKGEN01 (ckgen01 + 0x1CD0)
    #define REG_1CD0_CKGEN01_REG_SW_EN_SSUSB_SDIN2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD4_CKGEN01 (ckgen01 + 0x1CD4)
    #define REG_1CD4_CKGEN01_REG_SW_EN_SSUSB_SYS2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD8_CKGEN01 (ckgen01 + 0x1CD8)
    #define REG_1CD8_CKGEN01_REG_SW_EN_SSUSB_USB20_PHY_CLK_1P2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CDC_CKGEN01 (ckgen01 + 0x1CDC)
    #define REG_1CDC_CKGEN01_REG_SW_EN_SSUSB_USB20_PHY_CLK_2P2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE0_CKGEN01 (ckgen01 + 0x1CE0)
    #define REG_1CE0_CKGEN01_REG_SW_EN_SSUSB_USB20_PHY_CLK2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE4_CKGEN01 (ckgen01 + 0x1CE4)
    #define REG_1CE4_CKGEN01_REG_SW_EN_SSUSB_XHCI2SSUSB Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE8_CKGEN01 (ckgen01 + 0x1CE8)
    #define REG_1CE8_CKGEN01_REG_SW_EN_USBPHY240_MUX2USB20_SHBG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CEC_CKGEN01 (ckgen01 + 0x1CEC)
    #define REG_1CEC_CKGEN01_REG_SW_EN_USBPHY2402USB20_SHBG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF0_CKGEN01 (ckgen01 + 0x1CF0)
    #define REG_1CF0_CKGEN01_REG_SW_EN_USBPHY302USB20_SHBG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF4_CKGEN01 (ckgen01 + 0x1CF4)
    #define REG_1CF4_CKGEN01_REG_SW_EN_SSUSB_MISC_48M2SSUSB_1CF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D14_CKGEN01 (ckgen01 + 0x1D14)
    #define REG_1D14_CKGEN01_REG_SW_EN_P0_CLK_TMDSPLL_TEST_DIG2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D18_CKGEN01 (ckgen01 + 0x1D18)
    #define REG_1D18_CKGEN01_REG_SW_EN_P1_CLK_TMDSPLL_TEST_DIG2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D1C_CKGEN01 (ckgen01 + 0x1D1C)
    #define REG_1D1C_CKGEN01_REG_SW_EN_P2_CLK_TMDSPLL_TEST_DIG2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D20_CKGEN01 (ckgen01 + 0x1D20)
    #define REG_1D20_CKGEN01_REG_SW_EN_P3_CLK_TMDSPLL_TEST_DIG2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D24_CKGEN01 (ckgen01 + 0x1D24)
    #define REG_1D24_CKGEN01_REG_SW_EN_CLK_128FS_FB_S0_FF2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D28_CKGEN01 (ckgen01 + 0x1D28)
    #define REG_1D28_CKGEN01_REG_SW_EN_CLK_128FS_FB_S1_FF2MAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D80_CKGEN01 (ckgen01 + 0x1D80)
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2MHEG5_MBIST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2TSP_MBIST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2DEMOD0_MBIST Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2DEMOD1_MBIST Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1D80_CKGEN01_REG_SW_EN_GCE_F26M2VDEC_SOC_MBIST Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2VDEC_CORE0_MBIST Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2VDEC_CORE1_MBIST Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2VDEC_CORE2_MBIST Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2AIA_MBIST Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2DRAMC0_MBIST Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2DRAMC1_MBIST Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2DRAMC2_MBIST Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2GPU_DIE_MBIST Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2GPU_NODIE_MBIST Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1D80_CKGEN01_REG_SW_EN_CLK_XTAL_242HDMIRX_MBIST Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1D80_CKGEN01_REG_SW_EN_XTAL_24M2IP_WRAP_MBIST Fld(1,15,AC_MSKB1)//[15:15]

//Page CKGEN01_8
#define REG_1D84_CKGEN01 (ckgen01 + 0x1D84)
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2MCUSYS_MBIST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2MOD_MBIST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1D84_CKGEN01_REG_SW_EN_VIVA_XTAL_24M2VIVALDI9_MBIST Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2AUDIO_R2_MBIST Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2RV55AUDIO_MBIST Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2FRCIOPMRV55_MBIST Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2RV55FRC_MBIST Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2RV55PQU_MBIST Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2FRCMEHALO_MBIST Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2FRCMEMLB_MBIST Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2FRCMI_MBIST Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2SCACE_MBIST Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2SCDV_MBIST Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2SCIP_MBIST Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2SCMW_MBIST Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1D84_CKGEN01_REG_SW_EN_XTAL_24M2SCNR_MBIST Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1D88_CKGEN01 (ckgen01 + 0x1D88)
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2SCPQ_MBIST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2SCSCL_MBIST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2SCSR_MBIST Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2SCTCON_MBIST Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2SCDISP_MBIST_1D88 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2VDEC_CORE0_MERGE_MBIST_1D88 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1D88_CKGEN01_REG_SW_EN_XTAL_24M2FRC_MBIST_1D88 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1DBC_CKGEN01 (ckgen01 + 0x1DBC)
    #define REG_1DBC_CKGEN01_REG_VDEC_CORE0_MERGE_TEST_ENABLE_1DBC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DBC_CKGEN01_REG_VDEC_CORE0_MERGE_TEST_DIV_SEL_1DBC Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DBC_CKGEN01_REG_VDEC_CORE0_MERGE_TEST_SRC_SEL_1DBC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DC0_CKGEN01 (ckgen01 + 0x1DC0)
    #define REG_1DC0_CKGEN01_REG_ADCPLL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DC0_CKGEN01_REG_ADCPLL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DC0_CKGEN01_REG_ADCPLL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DC4_CKGEN01 (ckgen01 + 0x1DC4)
    #define REG_1DC4_CKGEN01_REG_AIA_TOP_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DC4_CKGEN01_REG_AIA_TOP_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DC4_CKGEN01_REG_AIA_TOP_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DC8_CKGEN01 (ckgen01 + 0x1DC8)
    #define REG_1DC8_CKGEN01_REG_DEMOD0_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DC8_CKGEN01_REG_DEMOD0_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DC8_CKGEN01_REG_DEMOD0_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DCC_CKGEN01 (ckgen01 + 0x1DCC)
    #define REG_1DCC_CKGEN01_REG_DEMOD1_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DCC_CKGEN01_REG_DEMOD1_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DCC_CKGEN01_REG_DEMOD1_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DD0_CKGEN01 (ckgen01 + 0x1DD0)
    #define REG_1DD0_CKGEN01_REG_VDEC_SOC_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DD0_CKGEN01_REG_VDEC_SOC_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DD0_CKGEN01_REG_VDEC_SOC_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DD4_CKGEN01 (ckgen01 + 0x1DD4)
    #define REG_1DD4_CKGEN01_REG_VDEC_CORE0_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DD4_CKGEN01_REG_VDEC_CORE0_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DD4_CKGEN01_REG_VDEC_CORE0_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DD8_CKGEN01 (ckgen01 + 0x1DD8)
    #define REG_1DD8_CKGEN01_REG_VDEC_CORE1_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DD8_CKGEN01_REG_VDEC_CORE1_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DD8_CKGEN01_REG_VDEC_CORE1_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DDC_CKGEN01 (ckgen01 + 0x1DDC)
    #define REG_1DDC_CKGEN01_REG_VDEC_CORE2_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DDC_CKGEN01_REG_VDEC_CORE2_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DDC_CKGEN01_REG_VDEC_CORE2_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DE0_CKGEN01 (ckgen01 + 0x1DE0)
    #define REG_1DE0_CKGEN01_REG_DRAMC0_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DE0_CKGEN01_REG_DRAMC0_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DE0_CKGEN01_REG_DRAMC0_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DE4_CKGEN01 (ckgen01 + 0x1DE4)
    #define REG_1DE4_CKGEN01_REG_DRAMC1_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DE4_CKGEN01_REG_DRAMC1_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DE4_CKGEN01_REG_DRAMC1_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DE8_CKGEN01 (ckgen01 + 0x1DE8)
    #define REG_1DE8_CKGEN01_REG_DRAMC2_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DE8_CKGEN01_REG_DRAMC2_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DE8_CKGEN01_REG_DRAMC2_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DEC_CKGEN01 (ckgen01 + 0x1DEC)
    #define REG_1DEC_CKGEN01_REG_TOP_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DEC_CKGEN01_REG_TOP_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DEC_CKGEN01_REG_TOP_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DF0_CKGEN01 (ckgen01 + 0x1DF0)
    #define REG_1DF0_CKGEN01_REG_MHEG5_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DF0_CKGEN01_REG_MHEG5_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DF0_CKGEN01_REG_MHEG5_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DF4_CKGEN01 (ckgen01 + 0x1DF4)
    #define REG_1DF4_CKGEN01_REG_GPU_DIE_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DF4_CKGEN01_REG_GPU_DIE_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DF4_CKGEN01_REG_GPU_DIE_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DF8_CKGEN01 (ckgen01 + 0x1DF8)
    #define REG_1DF8_CKGEN01_REG_GPU_NODIE_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DF8_CKGEN01_REG_GPU_NODIE_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DF8_CKGEN01_REG_GPU_NODIE_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1DFC_CKGEN01 (ckgen01 + 0x1DFC)
    #define REG_1DFC_CKGEN01_REG_GPU_SHADER_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1DFC_CKGEN01_REG_GPU_SHADER_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1DFC_CKGEN01_REG_GPU_SHADER_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E00_CKGEN01 (ckgen01 + 0x1E00)
    #define REG_1E00_CKGEN01_REG_HDMIRX_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E00_CKGEN01_REG_HDMIRX_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E00_CKGEN01_REG_HDMIRX_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E04_CKGEN01 (ckgen01 + 0x1E04)
    #define REG_1E04_CKGEN01_REG_IP_WRAP_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E04_CKGEN01_REG_IP_WRAP_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E04_CKGEN01_REG_IP_WRAP_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E08_CKGEN01 (ckgen01 + 0x1E08)
    #define REG_1E08_CKGEN01_REG_MCUSYS_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E08_CKGEN01_REG_MCUSYS_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E08_CKGEN01_REG_MCUSYS_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E0C_CKGEN01 (ckgen01 + 0x1E0C)
    #define REG_1E0C_CKGEN01_REG_MOD_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E0C_CKGEN01_REG_MOD_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E0C_CKGEN01_REG_MOD_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E10_CKGEN01 (ckgen01 + 0x1E10)
    #define REG_1E10_CKGEN01_REG_MOD_DOT_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E10_CKGEN01_REG_MOD_DOT_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E10_CKGEN01_REG_MOD_DOT_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E14_CKGEN01 (ckgen01 + 0x1E14)
    #define REG_1E14_CKGEN01_REG_LPLL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E14_CKGEN01_REG_LPLL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E14_CKGEN01_REG_LPLL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E18_CKGEN01 (ckgen01 + 0x1E18)
    #define REG_1E18_CKGEN01_REG_VIVALDI9_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E18_CKGEN01_REG_VIVALDI9_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E18_CKGEN01_REG_VIVALDI9_TEST_SRC_SEL Fld(9,7,AC_MSKW10)//[15:7]
#define REG_1E1C_CKGEN01 (ckgen01 + 0x1E1C)
    #define REG_1E1C_CKGEN01_REG_AUDIO_R2_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E1C_CKGEN01_REG_AUDIO_R2_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E1C_CKGEN01_REG_AUDIO_R2_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E20_CKGEN01 (ckgen01 + 0x1E20)
    #define REG_1E20_CKGEN01_REG_RV55AUDIO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E20_CKGEN01_REG_RV55AUDIO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E20_CKGEN01_REG_RV55AUDIO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E24_CKGEN01 (ckgen01 + 0x1E24)
    #define REG_1E24_CKGEN01_REG_TSP_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E24_CKGEN01_REG_TSP_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E24_CKGEN01_REG_TSP_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E28_CKGEN01 (ckgen01 + 0x1E28)
    #define REG_1E28_CKGEN01_REG_FRCIOPMRV55_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E28_CKGEN01_REG_FRCIOPMRV55_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E28_CKGEN01_REG_FRCIOPMRV55_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E2C_CKGEN01 (ckgen01 + 0x1E2C)
    #define REG_1E2C_CKGEN01_REG_RV55FRC_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E2C_CKGEN01_REG_RV55FRC_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E2C_CKGEN01_REG_RV55FRC_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E30_CKGEN01 (ckgen01 + 0x1E30)
    #define REG_1E30_CKGEN01_REG_RV55PQU_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E30_CKGEN01_REG_RV55PQU_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E30_CKGEN01_REG_RV55PQU_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E34_CKGEN01 (ckgen01 + 0x1E34)
    #define REG_1E34_CKGEN01_REG_FRCMEHALO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E34_CKGEN01_REG_FRCMEHALO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E34_CKGEN01_REG_FRCMEHALO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E38_CKGEN01 (ckgen01 + 0x1E38)
    #define REG_1E38_CKGEN01_REG_FRCMEMLB_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E38_CKGEN01_REG_FRCMEMLB_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E38_CKGEN01_REG_FRCMEMLB_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E3C_CKGEN01 (ckgen01 + 0x1E3C)
    #define REG_1E3C_CKGEN01_REG_FRCMI_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E3C_CKGEN01_REG_FRCMI_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E3C_CKGEN01_REG_FRCMI_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E40_CKGEN01 (ckgen01 + 0x1E40)
    #define REG_1E40_CKGEN01_REG_SCACE_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E40_CKGEN01_REG_SCACE_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E40_CKGEN01_REG_SCACE_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E44_CKGEN01 (ckgen01 + 0x1E44)
    #define REG_1E44_CKGEN01_REG_SCDV_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E44_CKGEN01_REG_SCDV_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E44_CKGEN01_REG_SCDV_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E48_CKGEN01 (ckgen01 + 0x1E48)
    #define REG_1E48_CKGEN01_REG_SCIP_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E48_CKGEN01_REG_SCIP_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E48_CKGEN01_REG_SCIP_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E4C_CKGEN01 (ckgen01 + 0x1E4C)
    #define REG_1E4C_CKGEN01_REG_SCMW_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E4C_CKGEN01_REG_SCMW_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E4C_CKGEN01_REG_SCMW_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E50_CKGEN01 (ckgen01 + 0x1E50)
    #define REG_1E50_CKGEN01_REG_SCNR_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E50_CKGEN01_REG_SCNR_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E50_CKGEN01_REG_SCNR_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E54_CKGEN01 (ckgen01 + 0x1E54)
    #define REG_1E54_CKGEN01_REG_SCPQ_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E54_CKGEN01_REG_SCPQ_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E54_CKGEN01_REG_SCPQ_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E58_CKGEN01 (ckgen01 + 0x1E58)
    #define REG_1E58_CKGEN01_REG_SCSCL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E58_CKGEN01_REG_SCSCL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E58_CKGEN01_REG_SCSCL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E5C_CKGEN01 (ckgen01 + 0x1E5C)
    #define REG_1E5C_CKGEN01_REG_SCSR_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E5C_CKGEN01_REG_SCSR_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E5C_CKGEN01_REG_SCSR_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E60_CKGEN01 (ckgen01 + 0x1E60)
    #define REG_1E60_CKGEN01_REG_SCTCON_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E60_CKGEN01_REG_SCTCON_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E60_CKGEN01_REG_SCTCON_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E64_CKGEN01 (ckgen01 + 0x1E64)
    #define REG_1E64_CKGEN01_REG_HDMIRX_DPHY_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E64_CKGEN01_REG_HDMIRX_DPHY_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E64_CKGEN01_REG_HDMIRX_DPHY_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E68_CKGEN01 (ckgen01 + 0x1E68)
    #define REG_1E68_CKGEN01_REG_HDMIRX_APHY_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E68_CKGEN01_REG_HDMIRX_APHY_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E68_CKGEN01_REG_HDMIRX_APHY_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E6C_CKGEN01 (ckgen01 + 0x1E6C)
    #define REG_1E6C_CKGEN01_REG_AUSDM_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E6C_CKGEN01_REG_AUSDM_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E6C_CKGEN01_REG_AUSDM_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E70_CKGEN01 (ckgen01 + 0x1E70)
    #define REG_1E70_CKGEN01_REG_AUR2PLL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E70_CKGEN01_REG_AUR2PLL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E70_CKGEN01_REG_AUR2PLL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E74_CKGEN01 (ckgen01 + 0x1E74)
    #define REG_1E74_CKGEN01_REG_AUPLL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E74_CKGEN01_REG_AUPLL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E74_CKGEN01_REG_AUPLL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E78_CKGEN01 (ckgen01 + 0x1E78)
    #define REG_1E78_CKGEN01_REG_MCUSYS_DIE_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E78_CKGEN01_REG_MCUSYS_DIE_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E78_CKGEN01_REG_MCUSYS_DIE_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E7C_CKGEN01 (ckgen01 + 0x1E7C)
    #define REG_1E7C_CKGEN01_REG_DMD_ANA_MISC_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E7C_CKGEN01_REG_DMD_ANA_MISC_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E7C_CKGEN01_REG_DMD_ANA_MISC_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E80_CKGEN01 (ckgen01 + 0x1E80)
    #define REG_1E80_CKGEN01_REG_ARMPLL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E80_CKGEN01_REG_ARMPLL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E80_CKGEN01_REG_ARMPLL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E84_CKGEN01 (ckgen01 + 0x1E84)
    #define REG_1E84_CKGEN01_REG_ARM2PLL_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E84_CKGEN01_REG_ARM2PLL_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E84_CKGEN01_REG_ARM2PLL_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E88_CKGEN01 (ckgen01 + 0x1E88)
    #define REG_1E88_CKGEN01_REG_ARMPLL_GPU_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E88_CKGEN01_REG_ARMPLL_GPU_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E88_CKGEN01_REG_ARMPLL_GPU_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E8C_CKGEN01 (ckgen01 + 0x1E8C)
    #define REG_1E8C_CKGEN01_REG_ARMPLL_APU_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E8C_CKGEN01_REG_ARMPLL_APU_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E8C_CKGEN01_REG_ARMPLL_APU_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E90_CKGEN01 (ckgen01 + 0x1E90)
    #define REG_1E90_CKGEN01_REG_EARC_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E90_CKGEN01_REG_EARC_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E90_CKGEN01_REG_EARC_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E94_CKGEN01 (ckgen01 + 0x1E94)
    #define REG_1E94_CKGEN01_REG_USB_PHY_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E94_CKGEN01_REG_USB_PHY_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E94_CKGEN01_REG_USB_PHY_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E98_CKGEN01 (ckgen01 + 0x1E98)
    #define REG_1E98_CKGEN01_REG_PCIE_PHY_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E98_CKGEN01_REG_PCIE_PHY_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E98_CKGEN01_REG_PCIE_PHY_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1E9C_CKGEN01 (ckgen01 + 0x1E9C)
    #define REG_1E9C_CKGEN01_REG_UFS_PHY_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1E9C_CKGEN01_REG_UFS_PHY_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1E9C_CKGEN01_REG_UFS_PHY_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EA0_CKGEN01 (ckgen01 + 0x1EA0)
    #define REG_1EA0_CKGEN01_REG_FLASH_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EA0_CKGEN01_REG_FLASH_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EA0_CKGEN01_REG_FLASH_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EA4_CKGEN01 (ckgen01 + 0x1EA4)
    #define REG_1EA4_CKGEN01_REG_FLASH_32BIF_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EA4_CKGEN01_REG_FLASH_32BIF_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EA4_CKGEN01_REG_FLASH_32BIF_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EA8_CKGEN01 (ckgen01 + 0x1EA8)
    #define REG_1EA8_CKGEN01_REG_FLASH_8BIT_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EA8_CKGEN01_REG_FLASH_8BIT_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EA8_CKGEN01_REG_FLASH_8BIT_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EAC_CKGEN01 (ckgen01 + 0x1EAC)
    #define REG_1EAC_CKGEN01_REG_SD_SDR_MACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EAC_CKGEN01_REG_SD_SDR_MACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EAC_CKGEN01_REG_SD_SDR_MACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EB0_CKGEN01 (ckgen01 + 0x1EB0)
    #define REG_1EB0_CKGEN01_REG_VDECPLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EB0_CKGEN01_REG_VDECPLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EB0_CKGEN01_REG_VDECPLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EB4_CKGEN01 (ckgen01 + 0x1EB4)
    #define REG_1EB4_CKGEN01_REG_SYS0PLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EB4_CKGEN01_REG_SYS0PLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EB4_CKGEN01_REG_SYS0PLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EB8_CKGEN01 (ckgen01 + 0x1EB8)
    #define REG_1EB8_CKGEN01_REG_SYS1PLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EB8_CKGEN01_REG_SYS1PLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EB8_CKGEN01_REG_SYS1PLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EBC_CKGEN01 (ckgen01 + 0x1EBC)
    #define REG_1EBC_CKGEN01_REG_SYS2PLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EBC_CKGEN01_REG_SYS2PLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EBC_CKGEN01_REG_SYS2PLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EC0_CKGEN01 (ckgen01 + 0x1EC0)
    #define REG_1EC0_CKGEN01_REG_RV55FRCPLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EC0_CKGEN01_REG_RV55FRCPLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EC0_CKGEN01_REG_RV55FRCPLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EC4_CKGEN01 (ckgen01 + 0x1EC4)
    #define REG_1EC4_CKGEN01_REG_XCPLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EC4_CKGEN01_REG_XCPLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EC4_CKGEN01_REG_XCPLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EC8_CKGEN01 (ckgen01 + 0x1EC8)
    #define REG_1EC8_CKGEN01_REG_XCSRSPLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EC8_CKGEN01_REG_XCSRSPLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EC8_CKGEN01_REG_XCSRSPLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1ECC_CKGEN01 (ckgen01 + 0x1ECC)
    #define REG_1ECC_CKGEN01_REG_SYS3PLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1ECC_CKGEN01_REG_SYS3PLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1ECC_CKGEN01_REG_SYS3PLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1ED0_CKGEN01 (ckgen01 + 0x1ED0)
    #define REG_1ED0_CKGEN01_REG_GPUBRDGPLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1ED0_CKGEN01_REG_GPUBRDGPLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1ED0_CKGEN01_REG_GPUBRDGPLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1ED4_CKGEN01 (ckgen01 + 0x1ED4)
    #define REG_1ED4_CKGEN01_REG_APUBUSPLL_DMACRO_TEST_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1ED4_CKGEN01_REG_APUBUSPLL_DMACRO_TEST_DIV_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1ED4_CKGEN01_REG_APUBUSPLL_DMACRO_TEST_SRC_SEL Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EE8_CKGEN01 (ckgen01 + 0x0E8)
    #define REG_1EE8_CKGEN01_REG_SCDISP_TEST_ENABLE_1EE8 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EE8_CKGEN01_REG_SCDISP_TEST_DIV_SEL_1EE8 Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EE8_CKGEN01_REG_SCDISP_TEST_SRC_SEL_1EE8 Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1EEC_CKGEN01 (ckgen01 + 0x0EC)
    #define REG_1EEC_CKGEN01_REG_DISP_MFDEC_BRG_TEST_ENABLE_1EEC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1EEC_CKGEN01_REG_DISP_MFDEC_BRG_TEST_DIV_SEL_1EEC Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_1EEC_CKGEN01_REG_DISP_MFDEC_BRG_TEST_SRC_SEL_1EEC Fld(8,8,AC_FULLB1)//[15:8]
#define REG_1F38_CKGEN01 (ckgen01 + 0x138)
    #define REG_1F38_CKGEN01_REG_GATE_INV_WLOCK_PASSWD_1F38 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F3C_CKGEN01 (ckgen01 + 0x13C)
    #define REG_1F3C_CKGEN01_REG_ALL_SW_EN_PASSWD_1F3C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F40_CKGEN01 (ckgen01 + 0x140)
    #define REG_1F40_CKGEN01_REG_XCPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F40_CKGEN01_REG_XCSRSPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F40_CKGEN01_REG_VDECPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F40_CKGEN01_REG_SYS0PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F40_CKGEN01_REG_SYS1PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F40_CKGEN01_REG_SYS2PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F40_CKGEN01_REG_SYS3PLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F40_CKGEN01_REG_ARMPLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F40_CKGEN01_REG_ARM2PLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F40_CKGEN01_REG_ARMPLL_APU_ALL_SW_EN_OVERWRITE_1F40 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F40_CKGEN01_REG_APUBUSPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F40_CKGEN01_REG_AUPLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F40_CKGEN01_REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F40_CKGEN01_REG_RV55FRCPLL_DMACRO_ALL_SW_EN_OVERWRITE_1F40 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F40_CKGEN01_REG_DMD_ANA_MISC_ALL_SW_EN_OVERWRITE_1F40 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F40_CKGEN01_REG_ADCPLL_ALL_SW_EN_OVERWRITE_1F40 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F44_CKGEN01 (ckgen01 + 0x144)
    #define REG_1F44_CKGEN01_REG_AUSDM_ALL_SW_EN_OVERWRITE_1F44 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F44_CKGEN01_REG_EARC_DMACRO_ALL_SW_EN_OVERWRITE_1F44 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F44_CKGEN01_REG_DEMOD1_ALL_SW_EN_OVERWRITE_1F44 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F44_CKGEN01_REG_FLASH_8BIT_ALL_SW_EN_OVERWRITE_1F44 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F44_CKGEN01_REG_FLASH_32BIF_ALL_SW_EN_OVERWRITE_1F44 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F44_CKGEN01_REG_FLASH_DMACRO_ALL_SW_EN_OVERWRITE_1F44 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F44_CKGEN01_REG_GPU_SHADER_ALL_SW_EN_OVERWRITE_1F44 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F44_CKGEN01_REG_HDMIRX_APHY_ALL_SW_EN_OVERWRITE_1F44 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F44_CKGEN01_REG_HDMIRX_DPHY_ALL_SW_EN_OVERWRITE_1F44 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F44_CKGEN01_REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_OVERWRITE_1F44 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F44_CKGEN01_REG_IP_WRAP_ALL_SW_EN_OVERWRITE_1F44 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F44_CKGEN01_REG_MHEG5_ALL_SW_EN_OVERWRITE_1F44 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F44_CKGEN01_REG_SD_SDR_MACRO_ALL_SW_EN_OVERWRITE_1F44 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F44_CKGEN01_REG_USB_PHY_ALL_SW_EN_OVERWRITE_1F44 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F44_CKGEN01_REG_MOD_DOT_ALL_SW_EN_OVERWRITE_1F44 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F48_CKGEN01 (ckgen01 + 0x148)
    #define REG_1F48_CKGEN01_REG_VDEC_CORE0_ALL_SW_EN_OVERWRITE_1F48 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F48_CKGEN01_REG_SCSR_ALL_SW_EN_OVERWRITE_1F48 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F48_CKGEN01_REG_DEMOD0_ALL_SW_EN_OVERWRITE_1F48 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F48_CKGEN01_REG_HDMIRX_ALL_SW_EN_OVERWRITE_1F48 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F48_CKGEN01_REG_TOP_ALL_SW_EN_OVERWRITE_1F48 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F48_CKGEN01_REG_AIA_TOP_ALL_SW_EN_OVERWRITE_1F48 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F48_CKGEN01_REG_VDEC_CORE0_MERGE_ALL_SW_EN_OVERWRITE_1F48 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F48_CKGEN01_REG_MCUSYS_ALL_SW_EN_OVERWRITE_1F48 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F48_CKGEN01_REG_MCUSYS_DIE_ALL_SW_EN_OVERWRITE_1F48 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F48_CKGEN01_REG_RV55FRC_ALL_SW_EN_OVERWRITE_1F48 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F48_CKGEN01_REG_RV55PQU_ALL_SW_EN_OVERWRITE_1F48 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F48_CKGEN01_REG_SCACE_ALL_SW_EN_OVERWRITE_1F48 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F48_CKGEN01_REG_SCDV_ALL_SW_EN_OVERWRITE_1F48 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F48_CKGEN01_REG_SCNR_ALL_SW_EN_OVERWRITE_1F48 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F48_CKGEN01_REG_DISP_MFDEC_BRG_ALL_SW_EN_OVERWRITE_1F48 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F48_CKGEN01_REG_MOD_ALL_SW_EN_OVERWRITE_1F48 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F4C_CKGEN01 (ckgen01 + 0x14C)
    #define REG_1F4C_CKGEN01_REG_FRC_MISC_ALL_SW_EN_OVERWRITE_1F4C Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F4C_CKGEN01_REG_FRC_CORE1_ALL_SW_EN_OVERWRITE_1F4C Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F4C_CKGEN01_REG_FRC_CORE2_ALL_SW_EN_OVERWRITE_1F4C Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F4C_CKGEN01_REG_FRC_CORE3_ALL_SW_EN_OVERWRITE_1F4C Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F4C_CKGEN01_REG_DRAMC0_ALL_SW_EN_OVERWRITE_1F4C Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F4C_CKGEN01_REG_DRAMC1_ALL_SW_EN_OVERWRITE_1F4C Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F4C_CKGEN01_REG_VDEC_SOC_ALL_SW_EN_OVERWRITE_1F4C Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F4C_CKGEN01_REG_SCDISP_ALL_SW_EN_OVERWRITE_1F4C Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F4C_CKGEN01_REG_SCSCL_ALL_SW_EN_OVERWRITE_1F4C Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F4C_CKGEN01_REG_TSP_ALL_SW_EN_OVERWRITE_1F4C Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F4C_CKGEN01_REG_GPU_PAR_GP_ALL_SW_EN_OVERWRITE_1F4C Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F4C_CKGEN01_REG_SCIP_ALL_SW_EN_OVERWRITE_1F4C Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F4C_CKGEN01_REG_SCMW_ALL_SW_EN_OVERWRITE_1F4C Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F4C_CKGEN01_REG_SCPQ_ALL_SW_EN_OVERWRITE_1F4C Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F4C_CKGEN01_REG_SCTCON_ALL_SW_EN_OVERWRITE_1F4C Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F4C_CKGEN01_REG_VIVALDI9_ALL_SW_EN_OVERWRITE_1F4C Fld(1,15,AC_MSKB1)//[15:15]
//Page CKGEN01_9
#define REG_1F60_CKGEN01 (ckgen01 + 0x160)
    #define REG_1F60_CKGEN01_REG_XCPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F60_CKGEN01_REG_XCSRSPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F60_CKGEN01_REG_VDECPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F60_CKGEN01_REG_SYS0PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F60_CKGEN01_REG_SYS1PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F60_CKGEN01_REG_SYS2PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F60_CKGEN01_REG_SYS3PLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F60_CKGEN01_REG_ARMPLL_ALL_SW_EN_VALUE_1F60 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F60_CKGEN01_REG_ARM2PLL_ALL_SW_EN_VALUE_1F60 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F60_CKGEN01_REG_ARMPLL_APU_ALL_SW_EN_VALUE_1F60 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F60_CKGEN01_REG_APUBUSPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F60_CKGEN01_REG_AUPLL_ALL_SW_EN_VALUE_1F60 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F60_CKGEN01_REG_GPUBRDGPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F60_CKGEN01_REG_RV55FRCPLL_DMACRO_ALL_SW_EN_VALUE_1F60 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F60_CKGEN01_REG_DMD_ANA_MISC_ALL_SW_EN_VALUE_1F60 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F60_CKGEN01_REG_ADCPLL_ALL_SW_EN_VALUE_1F60 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F64_CKGEN01 (ckgen01 + 0x164)
    #define REG_1F64_CKGEN01_REG_AUSDM_ALL_SW_EN_VALUE_1F64 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F64_CKGEN01_REG_EARC_DMACRO_ALL_SW_EN_VALUE_1F64 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F64_CKGEN01_REG_DEMOD1_ALL_SW_EN_VALUE_1F64 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F64_CKGEN01_REG_FLASH_8BIT_ALL_SW_EN_VALUE_1F64 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F64_CKGEN01_REG_FLASH_32BIF_ALL_SW_EN_VALUE_1F64 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F64_CKGEN01_REG_FLASH_DMACRO_ALL_SW_EN_VALUE_1F64 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F64_CKGEN01_REG_GPU_SHADER_ALL_SW_EN_VALUE_1F64 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F64_CKGEN01_REG_HDMIRX_APHY_ALL_SW_EN_VALUE_1F64 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F64_CKGEN01_REG_HDMIRX_DPHY_ALL_SW_EN_VALUE_1F64 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F64_CKGEN01_REG_HDMIRX_DPHY_NOP0_ALL_SW_EN_VALUE_1F64 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F64_CKGEN01_REG_IP_WRAP_ALL_SW_EN_VALUE_1F64 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F64_CKGEN01_REG_MHEG5_ALL_SW_EN_VALUE_1F64 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F64_CKGEN01_REG_SD_SDR_MACRO_ALL_SW_EN_VALUE_1F64 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F64_CKGEN01_REG_USB_PHY_ALL_SW_EN_VALUE_1F64 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F64_CKGEN01_REG_MOD_DOT_ALL_SW_EN_VALUE_1F64 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F68_CKGEN01 (ckgen01 + 0x168)
    #define REG_1F68_CKGEN01_REG_VDEC_CORE0_ALL_SW_EN_VALUE_1F68 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F68_CKGEN01_REG_SCSR_ALL_SW_EN_VALUE_1F68 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F68_CKGEN01_REG_DEMOD0_ALL_SW_EN_VALUE_1F68 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F68_CKGEN01_REG_HDMIRX_ALL_SW_EN_VALUE_1F68 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F68_CKGEN01_REG_TOP_ALL_SW_EN_VALUE_1F68 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F68_CKGEN01_REG_AIA_TOP_ALL_SW_EN_VALUE_1F68 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F68_CKGEN01_REG_VDEC_CORE0_MERGE_ALL_SW_EN_VALUE_1F68 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F68_CKGEN01_REG_MCUSYS_ALL_SW_EN_VALUE_1F68 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F68_CKGEN01_REG_MCUSYS_DIE_ALL_SW_EN_VALUE_1F68 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F68_CKGEN01_REG_RV55FRC_ALL_SW_EN_VALUE_1F68 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F68_CKGEN01_REG_RV55PQU_ALL_SW_EN_VALUE_1F68 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F68_CKGEN01_REG_SCACE_ALL_SW_EN_VALUE_1F68 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F68_CKGEN01_REG_SCDV_ALL_SW_EN_VALUE_1F68 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F68_CKGEN01_REG_SCNR_ALL_SW_EN_VALUE_1F68 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F68_CKGEN01_REG_DISP_MFDEC_BRG_ALL_SW_EN_VALUE_1F68 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F68_CKGEN01_REG_MOD_ALL_SW_EN_VALUE_1F68 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F6C_CKGEN01 (ckgen01 + 0x16C)
    #define REG_1F6C_CKGEN01_REG_FRC_MISC_ALL_SW_EN_VALUE_1F6C Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F6C_CKGEN01_REG_FRC_CORE1_ALL_SW_EN_VALUE_1F6C Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1F6C_CKGEN01_REG_FRC_CORE2_ALL_SW_EN_VALUE_1F6C Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1F6C_CKGEN01_REG_FRC_CORE3_ALL_SW_EN_VALUE_1F6C Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1F6C_CKGEN01_REG_DRAMC0_ALL_SW_EN_VALUE_1F6C Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1F6C_CKGEN01_REG_DRAMC1_ALL_SW_EN_VALUE_1F6C Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1F6C_CKGEN01_REG_VDEC_SOC_ALL_SW_EN_VALUE_1F6C Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1F6C_CKGEN01_REG_SCDISP_ALL_SW_EN_VALUE_1F6C Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1F6C_CKGEN01_REG_SCSCL_ALL_SW_EN_VALUE_1F6C Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1F6C_CKGEN01_REG_TSP_ALL_SW_EN_VALUE_1F6C Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1F6C_CKGEN01_REG_GPU_PAR_GP_ALL_SW_EN_VALUE_1F6C Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1F6C_CKGEN01_REG_SCIP_ALL_SW_EN_VALUE_1F6C Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1F6C_CKGEN01_REG_SCMW_ALL_SW_EN_VALUE_1F6C Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1F6C_CKGEN01_REG_SCPQ_ALL_SW_EN_VALUE_1F6C Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1F6C_CKGEN01_REG_SCTCON_ALL_SW_EN_VALUE_1F6C Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1F6C_CKGEN01_REG_VIVALDI9_ALL_SW_EN_VALUE_1F6C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1F88_CKGEN01 (ckgen01 + 0x1F88)
    #define REG_1F88_CKGEN01_REG_SW_EN_CALC2TEST_CLK_CALCULATE Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F90_CKGEN01 (ckgen01 + 0x1F90)
    #define REG_1F90_CKGEN01_REG_SW_EN_RIU_DMD2RIU_DFT_DEMOD1 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F94_CKGEN01 (ckgen01 + 0x1F94)
    #define REG_1F94_CKGEN01_REG_SW_EN_RIU_AU2RIU_DFT_AU_AUDIO_R2 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F94_CKGEN01_REG_SW_EN_RIU_AU2RIU_DFT_AU_RV55AUDIO Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1F98_CKGEN01 (ckgen01 + 0x1F98)
    #define REG_1F98_CKGEN01_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_DPHY Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1F98_CKGEN01_REG_SW_EN_RIU_HDMI2RIU_DFT_HDMI_HDMIRX_APHY Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1FA8_CKGEN01 (ckgen01 + 0x1FA8)
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCACE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDV Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCIP Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCMW Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCNR Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCPQ Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCSR Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCTCON Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1FA8_CKGEN01_REG_SW_EN_RIU_XC2RIU_DFT_XC_SCDISP_1FA8 Fld(1,8,AC_MSKB1)//[8:8]
//Page CKGEN01_9
#define REG_1FB4_CKGEN01 (ckgen01 + 0x1FB4)
    #define REG_1FB4_CKGEN01_REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55FRC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1FB4_CKGEN01_REG_SW_EN_RIU_FRC2RIU_DFT_FRC_RV55PQU Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1FB4_CKGEN01_REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMEHALO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1FB4_CKGEN01_REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMEMLB Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1FB4_CKGEN01_REG_SW_EN_RIU_FRC2RIU_DFT_FRC_FRCMI Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1FC0_CKGEN01 (ckgen01 + 0x1FC0)
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_ADC Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_AIA Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD0 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_DEMOD1 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_SOC Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE0 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE1 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_VDEC_CORE2 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_DRAMC2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_MHEG5 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_GPU_NODIE Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_HDMIRX Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_IP_WRAP Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1FC0_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_MCUSYS Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1FC4_CKGEN01 (ckgen01 + 0x1FC4)
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_MOD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1FC4_CKGEN01_REG_SW_EN_VIVA_RIU2RIU_DFT_VIVALDI9 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_AUDIO_R2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55AUDIO Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_TSP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_FRCIOPMRV55 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55FRC Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_RV55PQU Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMEHALO Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMEMLB Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_FRCMI Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCACE Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDV Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCIP Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCMW Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1FC4_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCNR Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1FC8_CKGEN01 (ckgen01 + 0x1FC8)
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCPQ Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSCL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCSR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCTCON Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_DPHY Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_HDMIRX_APHY Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_1FC8_CKGEN01_REG_SW_EN_RIU_NONPM2RIU_DFT_NONPM_SCDISP_1FC8 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1FE8_CKGEN01 (ckgen01 + 0x1FE8)
    #define REG_1FE8_CKGEN01_REG_CKG_OCC_SRC_FOR_TEST_DIV Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1FEC_CKGEN01 (ckgen01 + 0x1FEC)
    #define REG_1FEC_CKGEN01_REG_SW_EN_OCC_SRC_FOR_TEST_DIV2TEST_CTRL_WP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1FF0_CKGEN01 (ckgen01 + 0x1FF0)
    #define REG_1FF0_CKGEN01_REG_CKGEN01_DUMMY0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF4_CKGEN01 (ckgen01 + 0x1FF4)
    #define REG_1FF4_CKGEN01_REG_CKGEN01_DUMMY1 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF8_CKGEN01 (ckgen01 + 0x1FF8)
    #define REG_1FF8_CKGEN01_REG_CKGEN01_DUMMY2 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FFC_CKGEN01 (ckgen01 + 0x1FFC)
    #define REG_1FFC_CKGEN01_REG_CKGEN01_DUMMY3 Fld(16,0,AC_FULLW10)//[15:0]

#endif
