////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (; MStar; Confidential; Information; ) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
//****************************************************
//   Quality Map CodeGen Version 4.0
// 1920
// M7332
// 2020/1/30 10:46
// 17607
//****************************************************
// DDR: 4K2K_1p5G_48bitMIU

#define Version_17607

#ifndef _M7332_MAIN_EX_H_
#define _M7332_MAIN_EX_H_

#define PQ_XRULE_MM_DS_RULE_Main_Ex_ENABLE 1
#define PQ_XRULE_DISABLEUC_RULE_Main_Ex_ENABLE 1
#define PQ_XRULE_MM_DS_RULE_FBL_Main_Ex_ENABLE 1

typedef enum
{
#if PQ_XRULE_MM_DS_RULE_Main_Ex_ENABLE
    PQ_XRule_MM_DS_rule_Main_Ex,
#endif

#if PQ_XRULE_DISABLEUC_RULE_Main_Ex_ENABLE
    PQ_XRule_DisableUC_rule_Main_Ex,
#endif

#if PQ_XRULE_MM_DS_RULE_FBL_Main_Ex_ENABLE
    PQ_XRule_MM_DS_rule_FBL_Main_Ex,
#endif

}
MST_XRule_Index_Main_Ex;

#define PQ_IP_NUM_Main_Ex 104
#define PQ_Source_RF_NTSC_44
#define PQ_Source_RF_NTSC_M
#define PQ_Source_RF_PAL_BGHI
#define PQ_Source_RF_PAL_60
#define PQ_Source_RF_PAL_M
#define PQ_Source_RF_PAL_N
#define PQ_Source_RF_SECAM
#define PQ_Source_VIF_NTSC_44
#define PQ_Source_VIF_NTSC_M
#define PQ_Source_VIF_PAL_BGHI
#define PQ_Source_VIF_PAL_60
#define PQ_Source_VIF_PAL_M
#define PQ_Source_VIF_PAL_N
#define PQ_Source_VIF_SECAM
#define PQ_Source_SV_NTSC_44
#define PQ_Source_SV_NTSC_M
#define PQ_Source_SV_PAL_BGHI
#define PQ_Source_SV_PAL_60
#define PQ_Source_SV_PAL_M
#define PQ_Source_SV_PAL_N
#define PQ_Source_SV_SECAM
#define PQ_Source_AV_NTSC_44
#define PQ_Source_AV_NTSC_M
#define PQ_Source_AV_PAL_BGHI
#define PQ_Source_AV_PAL_60
#define PQ_Source_AV_PAL_M
#define PQ_Source_AV_PAL_N
#define PQ_Source_AV_SECAM
#define PQ_Source_SCART_AV_NTSC_44
#define PQ_Source_SCART_AV_NTSC_M
#define PQ_Source_SCART_AV_PAL_BGHI
#define PQ_Source_SCART_AV_PAL_60
#define PQ_Source_SCART_AV_PAL_M
#define PQ_Source_SCART_AV_PAL_N
#define PQ_Source_SCART_AV_SECAM
#define PQ_Source_SCART_SV_NTSC_44
#define PQ_Source_SCART_SV_NTSC_M
#define PQ_Source_SCART_SV_PAL_BGHI
#define PQ_Source_SCART_SV_PAL_60
#define PQ_Source_SCART_SV_PAL_M
#define PQ_Source_SCART_SV_PAL_N
#define PQ_Source_SCART_SV_SECAM
#define PQ_Source_SCART_RGB_NTSC
#define PQ_Source_SCART_RGB_PAL
#define PQ_Source_YPbPr_480i
#define PQ_Source_YPbPr_576i
#define PQ_Source_YPbPr_480p
#define PQ_Source_YPbPr_576p
#define PQ_Source_YPbPr_720p_24hz
#define PQ_Source_YPbPr_720p_50hz
#define PQ_Source_YPbPr_720p_60hz
#define PQ_Source_YPbPr_1080i_50hz
#define PQ_Source_YPbPr_1080i_60hz
#define PQ_Source_YPbPr_1080p_24hz
#define PQ_Source_YPbPr_1080p_50hz
#define PQ_Source_YPbPr_1080p_60hz
#define PQ_Source_HDMI_480i
#define PQ_Source_HDMI_576i
#define PQ_Source_HDMI_480p
#define PQ_Source_HDMI_576p
#define PQ_Source_HDMI_720p_24hz
#define PQ_Source_HDMI_720p_50hz
#define PQ_Source_HDMI_720p_60hz
#define PQ_Source_HDMI_FP_720p
#define PQ_Source_HDMI_1080i_50hz
#define PQ_Source_HDMI_1080i_60hz
#define PQ_Source_HDMI_1080p_24hz
#define PQ_Source_HDMI_1080p_60hz
#define PQ_Source_HDMI_1080p_50hz
#define PQ_Source_HDMI_FP_1080i
#define PQ_Source_HDMI_FP_1080p
#define PQ_Source_4K2K_24Hz
#define PQ_Source_4K2K_30Hz
#define PQ_Source_4K2K_60Hz
#define PQ_Source_HDMI_444_PC_Hup_Vup
#define PQ_Source_HDMI_444_PC_Hup_Vdown
#define PQ_Source_HDMI_444_PC_Hup_Vno
#define PQ_Source_HDMI_444_PC_Hdown_Vup
#define PQ_Source_HDMI_444_PC_Hdown_Vdown
#define PQ_Source_HDMI_444_PC_Hdown_Vno
#define PQ_Source_HDMI_444_PC_Hno_Vup
#define PQ_Source_HDMI_444_PC_Hno_Vdown
#define PQ_Source_HDMI_444_PC_Hno_Vno
#define PQ_Source_HDMI_444_PC_Hno_Vno_4K
#define PQ_Source_HDMI_422_PC_Hup_Vup
#define PQ_Source_HDMI_422_PC_Hup_Vdown
#define PQ_Source_HDMI_422_PC_Hup_Vno
#define PQ_Source_HDMI_422_PC_Hdown_Vup
#define PQ_Source_HDMI_422_PC_Hdown_Vdown
#define PQ_Source_HDMI_422_PC_Hdown_Vno
#define PQ_Source_HDMI_422_PC_Hno_Vup
#define PQ_Source_HDMI_422_PC_Hno_Vdown
#define PQ_Source_HDMI_422_PC_Hno_Vno
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hup_Vup
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hup_Vdown
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hup_Vno
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hdown_Vup
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hdown_Vdown
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hdown_Vno
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hno_Vup
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hno_Vdown
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hno_Vno
#define PQ_Source_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_4K
#define PQ_Source_DTV_480i_352x480_MPEG2
#define PQ_Source_DTV_480i_MPEG2
#define PQ_Source_DTV_576i_MPEG2
#define PQ_Source_DTV_480p_MPEG2
#define PQ_Source_DTV_576p_MPEG2
#define PQ_Source_DTV_720p_24hz_MPEG2
#define PQ_Source_DTV_720p_50hz_MPEG2
#define PQ_Source_DTV_720p_60hz_MPEG2
#define PQ_Source_DTV_1080i_50hz_MPEG2
#define PQ_Source_DTV_1080i_60hz_MPEG2
#define PQ_Source_DTV_1080p_24hz_MPEG2
#define PQ_Source_DTV_1080p_50hz_MPEG2
#define PQ_Source_DTV_1080p_60hz_MPEG2
#define PQ_Source_DTV_4K2K_MPEG2
#define PQ_Source_DTV_4K2K_60Hz_MPEG2
#define PQ_Source_DTV_480i_352x480_H264
#define PQ_Source_DTV_480i_H264
#define PQ_Source_DTV_576i_H264
#define PQ_Source_DTV_480p_H264
#define PQ_Source_DTV_576p_H264
#define PQ_Source_DTV_720p_24hz_H264
#define PQ_Source_DTV_720p_50hz_H264
#define PQ_Source_DTV_720p_60hz_H264
#define PQ_Source_DTV_1080i_50hz_H264
#define PQ_Source_DTV_1080i_60hz_H264
#define PQ_Source_DTV_1080p_24hz_H264
#define PQ_Source_DTV_1080p_50hz_H264
#define PQ_Source_DTV_1080p_60hz_H264
#define PQ_Source_DTV_4K2K_H264
#define PQ_Source_DTV_4K2K_60Hz_H264
#define PQ_Source_Multimedia_video_SD_interlace
#define PQ_Source_Multimedia_video_SD_progressive
#define PQ_Source_Multimedia_video_SD_progressive_24hz
#define PQ_Source_Multimedia_video_HD_interlace
#define PQ_Source_Multimedia_video_HD_progressive
#define PQ_Source_Multimedia_video_HD_progressive_24hz
#define PQ_Source_Multimedia_photo_SD_progressive
#define PQ_Source_Multimedia_photo_HD_progressive
#define PQ_Source_Multimedia_video_online_SD_interlace
#define PQ_Source_Multimedia_video_online_SD_progressive
#define PQ_Source_Multimedia_video_online_SD_progressive_24hz
#define PQ_Source_Multimedia_video_online_HD_interlace
#define PQ_Source_Multimedia_video_online_HD_progressive
#define PQ_Source_Multimedia_video_online_HD_progressive_24hz
#define PQ_Source_MM_FHD_I_DS
#define PQ_Source_MM_FHD_P_DS
#define PQ_Source_MM_4K2K_DS
#define PQ_Source_MM_4K2K
#define PQ_Source_MM_4K2K_Photo
#define PQ_Source_MM_4K2K_60Hz
#define PQ_Source_MM_non_4K2K
#define PQ_Source_DTV_iFrame_SD_interlace
#define PQ_Source_DTV_iFrame_SD_progressive
#define PQ_Source_DTV_iFrame_HD_interlace
#define PQ_Source_DTV_iFrame_HD_progressive
#define PQ_Source_Multimedia_video_4K2K_FS_progressive
#define PQ_Source_NetWork_4K2K_DS
#define PQ_Source_I_Mode_Unlock
#define PQ_Source_P_Mode_Unlock
#define PQ_Source_DVI_480i
#define PQ_Source_DVI_576i
#define PQ_Source_DVI_1080i_50hz
#define PQ_Source_DVI_1080i_60hz
#define PQ_Source_DTV_4K2K_DS
#define PQ_Source_MM_4K2K_Photo_444
#define PQ_Source_DTV_FHD_I_DS
#define PQ_Source_Multimedia_video_Preview_interlace
#define PQ_Source_Multimedia_video_Preview_progressive
#define PQ_Source_DTV_Preview_interlace
#define PQ_Source_DTV_Preview_progressive
#define PQ_Source_NetWork_FHD_I_DS
#define PQ_Source_NetWork_FHD_P_DS

typedef enum
{
    #if PQ_QM_CVBS
    QM_RF_NTSC_44_Main_Ex, //0
    #endif
    #if PQ_QM_CVBS
    QM_RF_NTSC_M_Main_Ex, //1
    #endif
    #if PQ_QM_CVBS
    QM_RF_PAL_BGHI_Main_Ex, //2
    #endif
    #if PQ_QM_CVBS
    QM_RF_PAL_60_Main_Ex, //3
    #endif
    #if PQ_QM_CVBS
    QM_RF_PAL_M_Main_Ex, //4
    #endif
    #if PQ_QM_CVBS
    QM_RF_PAL_N_Main_Ex, //5
    #endif
    #if PQ_QM_CVBS
    QM_RF_SECAM_Main_Ex, //6
    #endif
    #if PQ_QM_CVBS
    QM_VIF_NTSC_44_Main_Ex, //7
    #endif
    #if PQ_QM_CVBS
    QM_VIF_NTSC_M_Main_Ex, //8
    #endif
    #if PQ_QM_CVBS
    QM_VIF_PAL_BGHI_Main_Ex, //9
    #endif
    #if PQ_QM_CVBS
    QM_VIF_PAL_60_Main_Ex, //10
    #endif
    #if PQ_QM_CVBS
    QM_VIF_PAL_M_Main_Ex, //11
    #endif
    #if PQ_QM_CVBS
    QM_VIF_PAL_N_Main_Ex, //12
    #endif
    #if PQ_QM_CVBS
    QM_VIF_SECAM_Main_Ex, //13
    #endif
    #if PQ_QM_CVBS
    QM_SV_NTSC_44_Main_Ex, //14
    #endif
    #if PQ_QM_CVBS
    QM_SV_NTSC_M_Main_Ex, //15
    #endif
    #if PQ_QM_CVBS
    QM_SV_PAL_BGHI_Main_Ex, //16
    #endif
    #if PQ_QM_CVBS
    QM_SV_PAL_60_Main_Ex, //17
    #endif
    #if PQ_QM_CVBS
    QM_SV_PAL_M_Main_Ex, //18
    #endif
    #if PQ_QM_CVBS
    QM_SV_PAL_N_Main_Ex, //19
    #endif
    #if PQ_QM_CVBS
    QM_SV_SECAM_Main_Ex, //20
    #endif
    #if PQ_QM_CVBS
    QM_AV_NTSC_44_Main_Ex, //21
    #endif
    #if PQ_QM_CVBS
    QM_AV_NTSC_M_Main_Ex, //22
    #endif
    #if PQ_QM_CVBS
    QM_AV_PAL_BGHI_Main_Ex, //23
    #endif
    #if PQ_QM_CVBS
    QM_AV_PAL_60_Main_Ex, //24
    #endif
    #if PQ_QM_CVBS
    QM_AV_PAL_M_Main_Ex, //25
    #endif
    #if PQ_QM_CVBS
    QM_AV_PAL_N_Main_Ex, //26
    #endif
    #if PQ_QM_CVBS
    QM_AV_SECAM_Main_Ex, //27
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_NTSC_44_Main_Ex, //28
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_NTSC_M_Main_Ex, //29
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_PAL_BGHI_Main_Ex, //30
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_PAL_60_Main_Ex, //31
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_PAL_M_Main_Ex, //32
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_PAL_N_Main_Ex, //33
    #endif
    #if PQ_QM_CVBS
    QM_SCART_AV_SECAM_Main_Ex, //34
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_NTSC_44_Main_Ex, //35
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_NTSC_M_Main_Ex, //36
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_PAL_BGHI_Main_Ex, //37
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_PAL_60_Main_Ex, //38
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_PAL_M_Main_Ex, //39
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_PAL_N_Main_Ex, //40
    #endif
    #if PQ_QM_CVBS
    QM_SCART_SV_SECAM_Main_Ex, //41
    #endif
    #if PQ_QM_CVBS
    QM_SCART_RGB_NTSC_Main_Ex, //42
    #endif
    #if PQ_QM_CVBS
    QM_SCART_RGB_PAL_Main_Ex, //43
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_480i_Main_Ex, //44
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_576i_Main_Ex, //45
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_480p_Main_Ex, //46
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_576p_Main_Ex, //47
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_720p_24hz_Main_Ex, //48
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_720p_50hz_Main_Ex, //49
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_720p_60hz_Main_Ex, //50
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_1080i_50hz_Main_Ex, //51
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_1080i_60hz_Main_Ex, //52
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_1080p_24hz_Main_Ex, //53
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_1080p_50hz_Main_Ex, //54
    #endif
    #if PQ_QM_YPBPR
    QM_YPbPr_1080p_60hz_Main_Ex, //55
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_480i_Main_Ex, //56
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_576i_Main_Ex, //57
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_480p_Main_Ex, //58
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_576p_Main_Ex, //59
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_720p_24hz_Main_Ex, //60
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_720p_50hz_Main_Ex, //61
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_720p_60hz_Main_Ex, //62
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_FP_720p_Main_Ex, //63
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_1080i_50hz_Main_Ex, //64
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_1080i_60hz_Main_Ex, //65
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_1080p_24hz_Main_Ex, //66
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_1080p_60hz_Main_Ex, //67
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_1080p_50hz_Main_Ex, //68
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_FP_1080i_Main_Ex, //69
    #endif
    #if PQ_QM_HMDI
    QM_HDMI_FP_1080p_Main_Ex, //70
    #endif
    #if PQ_QM_HMDI
    QM_4K2K_24Hz_Main_Ex, //71
    #endif
    #if PQ_QM_HMDI
    QM_4K2K_30Hz_Main_Ex, //72
    #endif
    #if PQ_QM_HMDI
    QM_4K2K_60Hz_Main_Ex, //73
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hup_Vup_Main_Ex, //74
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hup_Vdown_Main_Ex, //75
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hup_Vno_Main_Ex, //76
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hdown_Vup_Main_Ex, //77
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hdown_Vdown_Main_Ex, //78
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hdown_Vno_Main_Ex, //79
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hno_Vup_Main_Ex, //80
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hno_Vdown_Main_Ex, //81
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hno_Vno_Main_Ex, //82
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_444_PC_Hno_Vno_4K_Main_Ex, //83
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hup_Vup_Main_Ex, //84
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hup_Vdown_Main_Ex, //85
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hup_Vno_Main_Ex, //86
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hdown_Vup_Main_Ex, //87
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hdown_Vdown_Main_Ex, //88
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hdown_Vno_Main_Ex, //89
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hno_Vup_Main_Ex, //90
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hno_Vdown_Main_Ex, //91
    #endif
    #if PQ_QM_HDMI_PC
    QM_HDMI_422_PC_Hno_Vno_Main_Ex, //92
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vup_Main_Ex, //93
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vdown_Main_Ex, //94
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vno_Main_Ex, //95
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vup_Main_Ex, //96
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vdown_Main_Ex, //97
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vno_Main_Ex, //98
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vup_Main_Ex, //99
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vdown_Main_Ex, //100
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_Main_Ex, //101
    #endif
    #if PQ_QM_PC
    QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_4K_Main_Ex, //102
    #endif
    #if PQ_QM_DTV
    QM_DTV_480i_352x480_MPEG2_Main_Ex, //103
    #endif
    #if PQ_QM_DTV
    QM_DTV_480i_MPEG2_Main_Ex, //104
    #endif
    #if PQ_QM_DTV
    QM_DTV_576i_MPEG2_Main_Ex, //105
    #endif
    #if PQ_QM_DTV
    QM_DTV_480p_MPEG2_Main_Ex, //106
    #endif
    #if PQ_QM_DTV
    QM_DTV_576p_MPEG2_Main_Ex, //107
    #endif
    #if PQ_QM_DTV
    QM_DTV_720p_24hz_MPEG2_Main_Ex, //108
    #endif
    #if PQ_QM_DTV
    QM_DTV_720p_50hz_MPEG2_Main_Ex, //109
    #endif
    #if PQ_QM_DTV
    QM_DTV_720p_60hz_MPEG2_Main_Ex, //110
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080i_50hz_MPEG2_Main_Ex, //111
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080i_60hz_MPEG2_Main_Ex, //112
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080p_24hz_MPEG2_Main_Ex, //113
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080p_50hz_MPEG2_Main_Ex, //114
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080p_60hz_MPEG2_Main_Ex, //115
    #endif
    #if PQ_QM_DTV
    QM_DTV_4K2K_MPEG2_Main_Ex, //116
    #endif
    #if PQ_QM_DTV
    QM_DTV_4K2K_60Hz_MPEG2_Main_Ex, //117
    #endif
    #if PQ_QM_DTV
    QM_DTV_480i_352x480_H264_Main_Ex, //118
    #endif
    #if PQ_QM_DTV
    QM_DTV_480i_H264_Main_Ex, //119
    #endif
    #if PQ_QM_DTV
    QM_DTV_576i_H264_Main_Ex, //120
    #endif
    #if PQ_QM_DTV
    QM_DTV_480p_H264_Main_Ex, //121
    #endif
    #if PQ_QM_DTV
    QM_DTV_576p_H264_Main_Ex, //122
    #endif
    #if PQ_QM_DTV
    QM_DTV_720p_24hz_H264_Main_Ex, //123
    #endif
    #if PQ_QM_DTV
    QM_DTV_720p_50hz_H264_Main_Ex, //124
    #endif
    #if PQ_QM_DTV
    QM_DTV_720p_60hz_H264_Main_Ex, //125
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080i_50hz_H264_Main_Ex, //126
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080i_60hz_H264_Main_Ex, //127
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080p_24hz_H264_Main_Ex, //128
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080p_50hz_H264_Main_Ex, //129
    #endif
    #if PQ_QM_DTV
    QM_DTV_1080p_60hz_H264_Main_Ex, //130
    #endif
    #if PQ_QM_DTV
    QM_DTV_4K2K_H264_Main_Ex, //131
    #endif
    #if PQ_QM_DTV
    QM_DTV_4K2K_60Hz_H264_Main_Ex, //132
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_SD_interlace_Main_Ex, //133
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_SD_progressive_Main_Ex, //134
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_SD_progressive_24hz_Main_Ex, //135
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_HD_interlace_Main_Ex, //136
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_HD_progressive_Main_Ex, //137
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_HD_progressive_24hz_Main_Ex, //138
    #endif
    #if PQ_QM_MM_PHOTO
    QM_Multimedia_photo_SD_progressive_Main_Ex, //139
    #endif
    #if PQ_QM_MM_PHOTO
    QM_Multimedia_photo_HD_progressive_Main_Ex, //140
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_online_SD_interlace_Main_Ex, //141
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_online_SD_progressive_Main_Ex, //142
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_online_SD_progressive_24hz_Main_Ex, //143
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_online_HD_interlace_Main_Ex, //144
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_online_HD_progressive_Main_Ex, //145
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_online_HD_progressive_24hz_Main_Ex, //146
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_FHD_I_DS_Main_Ex, //147
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_FHD_P_DS_Main_Ex, //148
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_4K2K_DS_Main_Ex, //149
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_4K2K_Main_Ex, //150
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_4K2K_Photo_Main_Ex, //151
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_4K2K_60Hz_Main_Ex, //152
    #endif
    #if PQ_QM_MM_VIDEO
    QM_MM_non_4K2K_Main_Ex, //153
    #endif
    #if PQ_QM_DTV
    QM_DTV_iFrame_SD_interlace_Main_Ex, //154
    #endif
    #if PQ_QM_DTV
    QM_DTV_iFrame_SD_progressive_Main_Ex, //155
    #endif
    #if PQ_QM_DTV
    QM_DTV_iFrame_HD_interlace_Main_Ex, //156
    #endif
    #if PQ_QM_DTV
    QM_DTV_iFrame_HD_progressive_Main_Ex, //157
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_4K2K_FS_progressive_Main_Ex, //158
    #endif
    #if PQ_QM_MM_VIDEO
    QM_NetWork_4K2K_DS_Main_Ex, //159
    #endif
    #if PQ_QM_HMDI
    QM_I_Mode_Unlock_Main_Ex, //160
    #endif
    #if PQ_QM_HMDI
    QM_P_Mode_Unlock_Main_Ex, //161
    #endif
    #if PQ_QM_HMDI
    QM_DVI_480i_Main_Ex, //162
    #endif
    #if PQ_QM_HMDI
    QM_DVI_576i_Main_Ex, //163
    #endif
    #if PQ_QM_HMDI
    QM_DVI_1080i_50hz_Main_Ex, //164
    #endif
    #if PQ_QM_HMDI
    QM_DVI_1080i_60hz_Main_Ex, //165
    #endif
    #if PQ_QM_DTV
    QM_DTV_4K2K_DS_Main_Ex, //166
    #endif
    #if PQ_QM_PC
    QM_MM_4K2K_Photo_444_Main_Ex, //167
    #endif
    #if PQ_QM_DTV
    QM_DTV_FHD_I_DS_Main_Ex, //168
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_Preview_interlace_Main_Ex, //169
    #endif
    #if PQ_QM_MM_VIDEO
    QM_Multimedia_video_Preview_progressive_Main_Ex, //170
    #endif
    #if PQ_QM_DTV
    QM_DTV_Preview_interlace_Main_Ex, //171
    #endif
    #if PQ_QM_DTV
    QM_DTV_Preview_progressive_Main_Ex, //172
    #endif
    #if PQ_QM_MM_VIDEO
    QM_NetWork_FHD_I_DS_Main_Ex, //173
    #endif
    #if PQ_QM_MM_VIDEO
    QM_NetWork_FHD_P_DS_Main_Ex, //174
    #endif
    QM_INPUTTYPE_NUM_Main_Ex, // 175
} SC_QUALITY_MAP_INDEX_e_Main_Ex;

#define PQ_IP_YHSL_Main_Ex_ENABLE 1
#define PQ_IP_YHSL_ext_Main_Ex_ENABLE 1
#define PQ_IP_AFEC_no_comm_Main_Ex_ENABLE 1
#define PQ_IP_VOF_Main_Ex_ENABLE 1
#define PQ_IP_FOD_Main_Ex_ENABLE 1
#define PQ_IP_MLP_EN_Main_Ex_ENABLE 1
#define PQ_IP_SPF_Mot_Itlv_Main_Ex_ENABLE 1
#define PQ_IP_DiPF2_Main_Ex_ENABLE 1
#define PQ_IP_DiPF2_Motion_Main_Ex_ENABLE 1
#define PQ_IP_Spike_NR_Main_Ex_ENABLE 1
#define PQ_IP_SPF_DBK_Main_Ex_ENABLE 1
#define PQ_IP_SPF_DBK_BKN_Main_Ex_ENABLE 1
#define PQ_IP_SPF_DBK_HDE_Main_Ex_ENABLE 1
#define PQ_IP_SPF_VDBK_Main_Ex_ENABLE 1
#define PQ_IP_SPF_WIDTH_DET_Main_Ex_ENABLE 1
#define PQ_IP_SPF_SNR_Main_Ex_ENABLE 1
#define PQ_IP_SPF_SNR_Std_Adj_Main_Ex_ENABLE 1
#define PQ_IP_SPF_SNR_Std_Stat_Main_Ex_ENABLE 1
#define PQ_IP_DMS_Main_Ex_ENABLE 1
#define PQ_IP_DMS_H_Main_Ex_ENABLE 1
#define PQ_IP_DMS_V_Main_Ex_ENABLE 1
#define PQ_IP_DMS_NMR_Main_Ex_ENABLE 1
#define PQ_IP_PreCTI_V_Main_Ex_ENABLE 1
#define PQ_IP_PreCTI_V_VR_Main_Ex_ENABLE 1
#define PQ_IP_VIP_pseudo_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Post_YC_delay_Main_Ex_ENABLE 1
#define PQ_IP_VIP_YC_gain_offset_Main_Ex_ENABLE 1
#define PQ_IP_VIP_LDE_setting_Main_Ex_ENABLE 1
#define PQ_IP_VIP_LDE_C_win1_Main_Ex_ENABLE 1
#define PQ_IP_VIP_LDE_C_win2_Main_Ex_ENABLE 1
#define PQ_IP_VIP_LDE_C_win3_Main_Ex_ENABLE 1
#define PQ_IP_VIP_LDE_C_win4_Main_Ex_ENABLE 1
#define PQ_IP_VIP_LDE_suppress_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_alpha_MIN_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_gain_by_Cedge_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_Cplx_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band2_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band1_adaptive_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band2_adaptive_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band3_adaptive_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band4_adaptive_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band5_adaptive_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_band6_adaptive_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_shoot_ad_Y_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_sum_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_sum_adaptive2_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_Mbt_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_H_dering2_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_V_dering1_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_V_dering2_Main_Ex_ENABLE 1
#define PQ_IP_VIP_postpk_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Peaking_Drv_VR_Main_Ex_ENABLE 1
#define PQ_IP_VIP_UVC_Main_Ex_ENABLE 1
#define PQ_IP_VIP_cplxLPF_Main_Ex_ENABLE 1
#define PQ_IP_VIP_ACback_Mode_Main_Ex_ENABLE 1
#define PQ_IP_VIP_ACback_Gain_Main_Ex_ENABLE 1
#define PQ_IP_VIP_UVC_Mux_Main_Ex_ENABLE 1
#define PQ_IP_VIP_UVC_dark_Main_Ex_ENABLE 1
#define PQ_IP_VIP_Post_SNR_Main_Ex_ENABLE 1
#define PQ_IP_VIP_ICC_Target_Main_Ex_ENABLE 1
#define PQ_IP_VIP_IBC_weight_Main_Ex_ENABLE 1
#define PQ_IP_VIP_ACK_Main_Ex_ENABLE 1
#define PQ_IP_VOP2_out_dither_Main_Ex_ENABLE 1
#define PQ_IP_OP1_LBOX_Main_Ex_ENABLE 1
#define PQ_IP_HSL_Enable_Main_Ex_ENABLE 1
#define PQ_IP_HSL_Setting_Main_Ex_ENABLE 1
#define PQ_IP_HSL_Global_Settings_Main_Ex_ENABLE 1
#define PQ_IP_HSL_VR_Main_Ex_ENABLE 1
#define PQ_IP_DMSNR_Main_Ex_ENABLE 1
#define PQ_IP_SwDriver_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_0_IP_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_1_IP_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_5_IP_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_9_IP_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_Dummy_IP_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_0_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_1_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_5_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_9_Main_Ex_ENABLE 1
#define PQ_IP_MM_DS_frame_delay_Dummy_Main_Ex_ENABLE 1
#define PQ_IP_BWR_Main_Ex_ENABLE 1
#define PQ_IP_BWS_Main_Ex_ENABLE 1
#define PQ_IP_BWS_UI_VR_Main_Ex_ENABLE 1
#define PQ_IP_BWD_Main_Ex_ENABLE 1
#define PQ_IP_MADi_Main_Ex_ENABLE 1
#define PQ_IP_MADi_VR_Main_Ex_ENABLE 1
#define PQ_IP_MADi_Motion_Main_Ex_ENABLE 1
#define PQ_IP_MADi_DFK_Main_Ex_ENABLE 1
#define PQ_IP_MADi_SST_Main_Ex_ENABLE 1
#define PQ_IP_MADi_SST_EN_VR_Main_Ex_ENABLE 1
#define PQ_IP_MADi_EODiW_Main_Ex_ENABLE 1
#define PQ_IP_DS_Main_Ex_ENABLE 1
#define PQ_IP_DS_Settings_Main_Ex_ENABLE 1
#define PQ_IP_DS_Drv_VR_Main_Ex_ENABLE 1
#define PQ_IP_UCDi_Main_Ex_ENABLE 1
#define PQ_IP_UCDi_UI_VR_Main_Ex_ENABLE 1
#define PQ_IP_UC_CTL_Main_Ex_ENABLE 1
#define PQ_IP_UC_CTL_UI_VR_Main_Ex_ENABLE 1
#define PQ_IP_UCD_VR_Main_Ex_ENABLE 1
#define PQ_IP_UCD_PR_Main_Ex_ENABLE 1
#define PQ_IP_TMO_VR_Main_Ex_ENABLE 1
#define PQ_IP_Game_Mode_Type_Main_Ex_ENABLE 1
#define PQ_IP_HVSP_Force_Main_Ex_ENABLE 1

typedef enum
{
#if PQ_IP_YHSL_Main_Ex_ENABLE
    PQ_IP_YHSL_Main_Ex,  //0
#endif

#if PQ_IP_YHSL_ext_Main_Ex_ENABLE
    PQ_IP_YHSL_ext_Main_Ex,  //1
#endif

#if PQ_IP_AFEC_no_comm_Main_Ex_ENABLE
    PQ_IP_AFEC_no_comm_Main_Ex,  //2
#endif

#if PQ_IP_VOF_Main_Ex_ENABLE
    PQ_IP_VOF_Main_Ex,  //3
#endif

#if PQ_IP_FOD_Main_Ex_ENABLE
    PQ_IP_FOD_Main_Ex,  //4
#endif

#if PQ_IP_MLP_EN_Main_Ex_ENABLE
    PQ_IP_MLP_EN_Main_Ex,  //5
#endif

#if PQ_IP_SPF_Mot_Itlv_Main_Ex_ENABLE
    PQ_IP_SPF_Mot_Itlv_Main_Ex,  //6
#endif

#if PQ_IP_DiPF2_Main_Ex_ENABLE
    PQ_IP_DiPF2_Main_Ex,  //7
#endif

#if PQ_IP_DiPF2_Motion_Main_Ex_ENABLE
    PQ_IP_DiPF2_Motion_Main_Ex,  //8
#endif

#if PQ_IP_Spike_NR_Main_Ex_ENABLE
    PQ_IP_Spike_NR_Main_Ex,  //9
#endif

#if PQ_IP_SPF_DBK_Main_Ex_ENABLE
    PQ_IP_SPF_DBK_Main_Ex,  //10
#endif

#if PQ_IP_SPF_DBK_BKN_Main_Ex_ENABLE
    PQ_IP_SPF_DBK_BKN_Main_Ex,  //11
#endif

#if PQ_IP_SPF_DBK_HDE_Main_Ex_ENABLE
    PQ_IP_SPF_DBK_HDE_Main_Ex,  //12
#endif

#if PQ_IP_SPF_VDBK_Main_Ex_ENABLE
    PQ_IP_SPF_VDBK_Main_Ex,  //13
#endif

#if PQ_IP_SPF_WIDTH_DET_Main_Ex_ENABLE
    PQ_IP_SPF_WIDTH_DET_Main_Ex,  //14
#endif

#if PQ_IP_SPF_SNR_Main_Ex_ENABLE
    PQ_IP_SPF_SNR_Main_Ex,  //15
#endif

#if PQ_IP_SPF_SNR_Std_Adj_Main_Ex_ENABLE
    PQ_IP_SPF_SNR_Std_Adj_Main_Ex,  //16
#endif

#if PQ_IP_SPF_SNR_Std_Stat_Main_Ex_ENABLE
    PQ_IP_SPF_SNR_Std_Stat_Main_Ex,  //17
#endif

#if PQ_IP_DMS_Main_Ex_ENABLE
    PQ_IP_DMS_Main_Ex,  //18
#endif

#if PQ_IP_DMS_H_Main_Ex_ENABLE
    PQ_IP_DMS_H_Main_Ex,  //19
#endif

#if PQ_IP_DMS_V_Main_Ex_ENABLE
    PQ_IP_DMS_V_Main_Ex,  //20
#endif

#if PQ_IP_DMS_NMR_Main_Ex_ENABLE
    PQ_IP_DMS_NMR_Main_Ex,  //21
#endif

#if PQ_IP_PreCTI_V_Main_Ex_ENABLE
    PQ_IP_PreCTI_V_Main_Ex,  //22
#endif

#if PQ_IP_PreCTI_V_VR_Main_Ex_ENABLE
    PQ_IP_PreCTI_V_VR_Main_Ex,  //23
#endif

#if PQ_IP_VIP_pseudo_Main_Ex_ENABLE
    PQ_IP_VIP_pseudo_Main_Ex,  //24
#endif

#if PQ_IP_VIP_Post_YC_delay_Main_Ex_ENABLE
    PQ_IP_VIP_Post_YC_delay_Main_Ex,  //25
#endif

#if PQ_IP_VIP_YC_gain_offset_Main_Ex_ENABLE
    PQ_IP_VIP_YC_gain_offset_Main_Ex,  //26
#endif

#if PQ_IP_VIP_LDE_setting_Main_Ex_ENABLE
    PQ_IP_VIP_LDE_setting_Main_Ex,  //27
#endif

#if PQ_IP_VIP_LDE_C_win1_Main_Ex_ENABLE
    PQ_IP_VIP_LDE_C_win1_Main_Ex,  //28
#endif

#if PQ_IP_VIP_LDE_C_win2_Main_Ex_ENABLE
    PQ_IP_VIP_LDE_C_win2_Main_Ex,  //29
#endif

#if PQ_IP_VIP_LDE_C_win3_Main_Ex_ENABLE
    PQ_IP_VIP_LDE_C_win3_Main_Ex,  //30
#endif

#if PQ_IP_VIP_LDE_C_win4_Main_Ex_ENABLE
    PQ_IP_VIP_LDE_C_win4_Main_Ex,  //31
#endif

#if PQ_IP_VIP_LDE_suppress_Main_Ex_ENABLE
    PQ_IP_VIP_LDE_suppress_Main_Ex,  //32
#endif

#if PQ_IP_VIP_Peaking_alpha_MIN_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_alpha_MIN_Main_Ex,  //33
#endif

#if PQ_IP_VIP_Peaking_gain_by_Cedge_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_gain_by_Cedge_Main_Ex,  //34
#endif

#if PQ_IP_VIP_Peaking_Cplx_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_Cplx_Main_Ex,  //35
#endif

#if PQ_IP_VIP_Peaking_band_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band_Main_Ex,  //36
#endif

#if PQ_IP_VIP_Peaking_band2_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band2_Main_Ex,  //37
#endif

#if PQ_IP_VIP_Peaking_band1_adaptive_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band1_adaptive_Main_Ex,  //38
#endif

#if PQ_IP_VIP_Peaking_band2_adaptive_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band2_adaptive_Main_Ex,  //39
#endif

#if PQ_IP_VIP_Peaking_band3_adaptive_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band3_adaptive_Main_Ex,  //40
#endif

#if PQ_IP_VIP_Peaking_band4_adaptive_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band4_adaptive_Main_Ex,  //41
#endif

#if PQ_IP_VIP_Peaking_band5_adaptive_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band5_adaptive_Main_Ex,  //42
#endif

#if PQ_IP_VIP_Peaking_band6_adaptive_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_band6_adaptive_Main_Ex,  //43
#endif

#if PQ_IP_VIP_Peaking_shoot_ad_Y_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_shoot_ad_Y_Main_Ex,  //44
#endif

#if PQ_IP_VIP_Peaking_sum_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_sum_Main_Ex,  //45
#endif

#if PQ_IP_VIP_Peaking_sum_adaptive2_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_sum_adaptive2_Main_Ex,  //46
#endif

#if PQ_IP_VIP_Peaking_Mbt_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_Mbt_Main_Ex,  //47
#endif

#if PQ_IP_VIP_Peaking_H_dering2_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_H_dering2_Main_Ex,  //48
#endif

#if PQ_IP_VIP_Peaking_V_dering1_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_V_dering1_Main_Ex,  //49
#endif

#if PQ_IP_VIP_Peaking_V_dering2_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_V_dering2_Main_Ex,  //50
#endif

#if PQ_IP_VIP_postpk_Main_Ex_ENABLE
    PQ_IP_VIP_postpk_Main_Ex,  //51
#endif

#if PQ_IP_VIP_Peaking_Drv_VR_Main_Ex_ENABLE
    PQ_IP_VIP_Peaking_Drv_VR_Main_Ex,  //52
#endif

#if PQ_IP_VIP_UVC_Main_Ex_ENABLE
    PQ_IP_VIP_UVC_Main_Ex,  //53
#endif

#if PQ_IP_VIP_cplxLPF_Main_Ex_ENABLE
    PQ_IP_VIP_cplxLPF_Main_Ex,  //54
#endif

#if PQ_IP_VIP_ACback_Mode_Main_Ex_ENABLE
    PQ_IP_VIP_ACback_Mode_Main_Ex,  //55
#endif

#if PQ_IP_VIP_ACback_Gain_Main_Ex_ENABLE
    PQ_IP_VIP_ACback_Gain_Main_Ex,  //56
#endif

#if PQ_IP_VIP_UVC_Mux_Main_Ex_ENABLE
    PQ_IP_VIP_UVC_Mux_Main_Ex,  //57
#endif

#if PQ_IP_VIP_UVC_dark_Main_Ex_ENABLE
    PQ_IP_VIP_UVC_dark_Main_Ex,  //58
#endif

#if PQ_IP_VIP_Post_SNR_Main_Ex_ENABLE
    PQ_IP_VIP_Post_SNR_Main_Ex,  //59
#endif

#if PQ_IP_VIP_ICC_Target_Main_Ex_ENABLE
    PQ_IP_VIP_ICC_Target_Main_Ex,  //60
#endif

#if PQ_IP_VIP_IBC_weight_Main_Ex_ENABLE
    PQ_IP_VIP_IBC_weight_Main_Ex,  //61
#endif

#if PQ_IP_VIP_ACK_Main_Ex_ENABLE
    PQ_IP_VIP_ACK_Main_Ex,  //62
#endif

#if PQ_IP_VOP2_out_dither_Main_Ex_ENABLE
    PQ_IP_VOP2_out_dither_Main_Ex,  //63
#endif

#if PQ_IP_OP1_LBOX_Main_Ex_ENABLE
    PQ_IP_OP1_LBOX_Main_Ex,  //64
#endif

#if PQ_IP_HSL_Enable_Main_Ex_ENABLE
    PQ_IP_HSL_Enable_Main_Ex,  //65
#endif

#if PQ_IP_HSL_Setting_Main_Ex_ENABLE
    PQ_IP_HSL_Setting_Main_Ex,  //66
#endif

#if PQ_IP_HSL_Global_Settings_Main_Ex_ENABLE
    PQ_IP_HSL_Global_Settings_Main_Ex,  //67
#endif

#if PQ_IP_HSL_VR_Main_Ex_ENABLE
    PQ_IP_HSL_VR_Main_Ex,  //68
#endif

#if PQ_IP_DMSNR_Main_Ex_ENABLE
    PQ_IP_DMSNR_Main_Ex,  //69
#endif

#if PQ_IP_SwDriver_Main_Ex_ENABLE
    PQ_IP_SwDriver_Main_Ex,  //70
#endif

#if PQ_IP_MM_DS_frame_delay_0_IP_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_0_IP_Main_Ex,  //71
#endif

#if PQ_IP_MM_DS_frame_delay_1_IP_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_1_IP_Main_Ex,  //72
#endif

#if PQ_IP_MM_DS_frame_delay_5_IP_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_5_IP_Main_Ex,  //73
#endif

#if PQ_IP_MM_DS_frame_delay_9_IP_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_9_IP_Main_Ex,  //74
#endif

#if PQ_IP_MM_DS_frame_delay_Dummy_IP_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_Dummy_IP_Main_Ex,  //75
#endif

#if PQ_IP_MM_DS_frame_delay_0_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_0_Main_Ex,  //76
#endif

#if PQ_IP_MM_DS_frame_delay_1_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_1_Main_Ex,  //77
#endif

#if PQ_IP_MM_DS_frame_delay_5_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_5_Main_Ex,  //78
#endif

#if PQ_IP_MM_DS_frame_delay_9_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_9_Main_Ex,  //79
#endif

#if PQ_IP_MM_DS_frame_delay_Dummy_Main_Ex_ENABLE
    PQ_IP_MM_DS_frame_delay_Dummy_Main_Ex,  //80
#endif

#if PQ_IP_BWR_Main_Ex_ENABLE
    PQ_IP_BWR_Main_Ex,  //81
#endif

#if PQ_IP_BWS_Main_Ex_ENABLE
    PQ_IP_BWS_Main_Ex,  //82
#endif

#if PQ_IP_BWS_UI_VR_Main_Ex_ENABLE
    PQ_IP_BWS_UI_VR_Main_Ex,  //83
#endif

#if PQ_IP_BWD_Main_Ex_ENABLE
    PQ_IP_BWD_Main_Ex,  //84
#endif

#if PQ_IP_MADi_Main_Ex_ENABLE
    PQ_IP_MADi_Main_Ex,  //85
#endif

#if PQ_IP_MADi_VR_Main_Ex_ENABLE
    PQ_IP_MADi_VR_Main_Ex,  //86
#endif

#if PQ_IP_MADi_Motion_Main_Ex_ENABLE
    PQ_IP_MADi_Motion_Main_Ex,  //87
#endif

#if PQ_IP_MADi_DFK_Main_Ex_ENABLE
    PQ_IP_MADi_DFK_Main_Ex,  //88
#endif

#if PQ_IP_MADi_SST_Main_Ex_ENABLE
    PQ_IP_MADi_SST_Main_Ex,  //89
#endif

#if PQ_IP_MADi_SST_EN_VR_Main_Ex_ENABLE
    PQ_IP_MADi_SST_EN_VR_Main_Ex,  //90
#endif

#if PQ_IP_MADi_EODiW_Main_Ex_ENABLE
    PQ_IP_MADi_EODiW_Main_Ex,  //91
#endif

#if PQ_IP_DS_Main_Ex_ENABLE
    PQ_IP_DS_Main_Ex,  //92
#endif

#if PQ_IP_DS_Settings_Main_Ex_ENABLE
    PQ_IP_DS_Settings_Main_Ex,  //93
#endif

#if PQ_IP_DS_Drv_VR_Main_Ex_ENABLE
    PQ_IP_DS_Drv_VR_Main_Ex,  //94
#endif

#if PQ_IP_UCDi_Main_Ex_ENABLE
    PQ_IP_UCDi_Main_Ex,  //95
#endif

#if PQ_IP_UCDi_UI_VR_Main_Ex_ENABLE
    PQ_IP_UCDi_UI_VR_Main_Ex,  //96
#endif

#if PQ_IP_UC_CTL_Main_Ex_ENABLE
    PQ_IP_UC_CTL_Main_Ex,  //97
#endif

#if PQ_IP_UC_CTL_UI_VR_Main_Ex_ENABLE
    PQ_IP_UC_CTL_UI_VR_Main_Ex,  //98
#endif

#if PQ_IP_UCD_VR_Main_Ex_ENABLE
    PQ_IP_UCD_VR_Main_Ex,  //99
#endif

#if PQ_IP_UCD_PR_Main_Ex_ENABLE
    PQ_IP_UCD_PR_Main_Ex,  //100
#endif

#if PQ_IP_TMO_VR_Main_Ex_ENABLE
    PQ_IP_TMO_VR_Main_Ex,  //101
#endif

#if PQ_IP_Game_Mode_Type_Main_Ex_ENABLE
    PQ_IP_Game_Mode_Type_Main_Ex,  //102
#endif

#if PQ_IP_HVSP_Force_Main_Ex_ENABLE
    PQ_IP_HVSP_Force_Main_Ex,  //103
#endif

 }   PQ_IPTYPE_Main_Ex;

typedef enum
{
PQ_IP_YHSL_COM_Main_Ex,  //0
PQ_IP_YHSL_ext_COM_Main_Ex,  //1
PQ_IP_AFEC_no_comm_COM_Main_Ex,  //2
PQ_IP_VOF_COM_Main_Ex,  //3
PQ_IP_FOD_COM_Main_Ex,  //4
PQ_IP_MLP_EN_COM_Main_Ex,  //5
PQ_IP_SPF_Mot_Itlv_COM_Main_Ex,  //6
PQ_IP_DiPF2_COM_Main_Ex,  //7
PQ_IP_DiPF2_Motion_COM_Main_Ex,  //8
PQ_IP_Spike_NR_COM_Main_Ex,  //9
PQ_IP_SPF_DBK_COM_Main_Ex,  //10
PQ_IP_SPF_DBK_BKN_COM_Main_Ex,  //11
PQ_IP_SPF_DBK_HDE_COM_Main_Ex,  //12
PQ_IP_SPF_VDBK_COM_Main_Ex,  //13
PQ_IP_SPF_WIDTH_DET_COM_Main_Ex,  //14
PQ_IP_SPF_SNR_COM_Main_Ex,  //15
PQ_IP_SPF_SNR_Std_Adj_COM_Main_Ex,  //16
PQ_IP_SPF_SNR_Std_Stat_COM_Main_Ex,  //17
PQ_IP_DMS_COM_Main_Ex,  //18
PQ_IP_DMS_H_COM_Main_Ex,  //19
PQ_IP_DMS_V_COM_Main_Ex,  //20
PQ_IP_DMS_NMR_COM_Main_Ex,  //21
PQ_IP_PreCTI_V_COM_Main_Ex,  //22
PQ_IP_PreCTI_V_VR_COM_Main_Ex,  //23
PQ_IP_VIP_pseudo_COM_Main_Ex,  //24
PQ_IP_VIP_Post_YC_delay_COM_Main_Ex,  //25
PQ_IP_VIP_YC_gain_offset_COM_Main_Ex,  //26
PQ_IP_VIP_LDE_setting_COM_Main_Ex,  //27
PQ_IP_VIP_LDE_C_win1_COM_Main_Ex,  //28
PQ_IP_VIP_LDE_C_win2_COM_Main_Ex,  //29
PQ_IP_VIP_LDE_C_win3_COM_Main_Ex,  //30
PQ_IP_VIP_LDE_C_win4_COM_Main_Ex,  //31
PQ_IP_VIP_LDE_suppress_COM_Main_Ex,  //32
PQ_IP_VIP_Peaking_alpha_MIN_COM_Main_Ex,  //33
PQ_IP_VIP_Peaking_gain_by_Cedge_COM_Main_Ex,  //34
PQ_IP_VIP_Peaking_Cplx_COM_Main_Ex,  //35
PQ_IP_VIP_Peaking_band_COM_Main_Ex,  //36
PQ_IP_VIP_Peaking_band2_COM_Main_Ex,  //37
PQ_IP_VIP_Peaking_band1_adaptive_COM_Main_Ex,  //38
PQ_IP_VIP_Peaking_band2_adaptive_COM_Main_Ex,  //39
PQ_IP_VIP_Peaking_band3_adaptive_COM_Main_Ex,  //40
PQ_IP_VIP_Peaking_band4_adaptive_COM_Main_Ex,  //41
PQ_IP_VIP_Peaking_band5_adaptive_COM_Main_Ex,  //42
PQ_IP_VIP_Peaking_band6_adaptive_COM_Main_Ex,  //43
PQ_IP_VIP_Peaking_shoot_ad_Y_COM_Main_Ex,  //44
PQ_IP_VIP_Peaking_sum_COM_Main_Ex,  //45
PQ_IP_VIP_Peaking_sum_adaptive2_COM_Main_Ex,  //46
PQ_IP_VIP_Peaking_Mbt_COM_Main_Ex,  //47
PQ_IP_VIP_Peaking_H_dering2_COM_Main_Ex,  //48
PQ_IP_VIP_Peaking_V_dering1_COM_Main_Ex,  //49
PQ_IP_VIP_Peaking_V_dering2_COM_Main_Ex,  //50
PQ_IP_VIP_postpk_COM_Main_Ex,  //51
PQ_IP_VIP_Peaking_Drv_VR_COM_Main_Ex,  //52
PQ_IP_VIP_UVC_COM_Main_Ex,  //53
PQ_IP_VIP_cplxLPF_COM_Main_Ex,  //54
PQ_IP_VIP_ACback_Mode_COM_Main_Ex,  //55
PQ_IP_VIP_ACback_Gain_COM_Main_Ex,  //56
PQ_IP_VIP_UVC_Mux_COM_Main_Ex,  //57
PQ_IP_VIP_UVC_dark_COM_Main_Ex,  //58
PQ_IP_VIP_Post_SNR_COM_Main_Ex,  //59
PQ_IP_VIP_ICC_Target_COM_Main_Ex,  //60
PQ_IP_VIP_IBC_weight_COM_Main_Ex,  //61
PQ_IP_VIP_ACK_COM_Main_Ex,  //62
PQ_IP_VOP2_out_dither_COM_Main_Ex,  //63
PQ_IP_OP1_LBOX_COM_Main_Ex,  //64
PQ_IP_HSL_Enable_COM_Main_Ex,  //65
PQ_IP_HSL_Setting_COM_Main_Ex,  //66
PQ_IP_HSL_Global_Settings_COM_Main_Ex,  //67
PQ_IP_HSL_VR_COM_Main_Ex,  //68
PQ_IP_DMSNR_COM_Main_Ex,  //69
PQ_IP_SwDriver_COM_Main_Ex,  //70
PQ_IP_MM_DS_frame_delay_0_IP_COM_Main_Ex,  //71
PQ_IP_MM_DS_frame_delay_1_IP_COM_Main_Ex,  //72
PQ_IP_MM_DS_frame_delay_5_IP_COM_Main_Ex,  //73
PQ_IP_MM_DS_frame_delay_9_IP_COM_Main_Ex,  //74
PQ_IP_MM_DS_frame_delay_Dummy_IP_COM_Main_Ex,  //75
PQ_IP_MM_DS_frame_delay_0_COM_Main_Ex,  //76
PQ_IP_MM_DS_frame_delay_1_COM_Main_Ex,  //77
PQ_IP_MM_DS_frame_delay_5_COM_Main_Ex,  //78
PQ_IP_MM_DS_frame_delay_9_COM_Main_Ex,  //79
PQ_IP_MM_DS_frame_delay_Dummy_COM_Main_Ex,  //80
PQ_IP_BWR_COM_Main_Ex,  //81
PQ_IP_BWS_COM_Main_Ex,  //82
PQ_IP_BWS_UI_VR_COM_Main_Ex,  //83
PQ_IP_BWD_COM_Main_Ex,  //84
PQ_IP_MADi_COM_Main_Ex,  //85
PQ_IP_MADi_VR_COM_Main_Ex,  //86
PQ_IP_MADi_Motion_COM_Main_Ex,  //87
PQ_IP_MADi_DFK_COM_Main_Ex,  //88
PQ_IP_MADi_SST_COM_Main_Ex,  //89
PQ_IP_MADi_SST_EN_VR_COM_Main_Ex,  //90
PQ_IP_MADi_EODiW_COM_Main_Ex,  //91
PQ_IP_DS_COM_Main_Ex,  //92
PQ_IP_DS_Settings_COM_Main_Ex,  //93
PQ_IP_DS_Drv_VR_COM_Main_Ex,  //94
PQ_IP_UCDi_COM_Main_Ex,  //95
PQ_IP_UCDi_UI_VR_COM_Main_Ex,  //96
PQ_IP_UC_CTL_COM_Main_Ex,  //97
PQ_IP_UC_CTL_UI_VR_COM_Main_Ex,  //98
PQ_IP_UCD_VR_COM_Main_Ex,  //99
PQ_IP_UCD_PR_COM_Main_Ex,  //100
PQ_IP_TMO_VR_COM_Main_Ex,  //101
PQ_IP_Game_Mode_Type_COM_Main_Ex,  //102
PQ_IP_HVSP_Force_COM_Main_Ex,  //103
PQ_IP_COM_NUMS_Main_Ex
} PQ_IP_COM_Group_Main_Ex;

typedef enum
{
PQ_IP_YHSL_OFF_Main_Ex,
PQ_IP_YHSL_ON_Main_Ex,
PQ_IP_YHSL_bypass_Main_Ex,
PQ_IP_YHSL_NUMS_Main_Ex
} PQ_IP_YHSL_Group_Main_Ex;

typedef enum
{
PQ_IP_YHSL_ext_OFF_Main_Ex,
PQ_IP_YHSL_ext_ON_Main_Ex,
PQ_IP_YHSL_ext_bypass_Main_Ex,
PQ_IP_YHSL_ext_NUMS_Main_Ex
} PQ_IP_YHSL_ext_Group_Main_Ex;

typedef enum
{
PQ_IP_AFEC_no_comm_ON_Main_Ex,
PQ_IP_AFEC_no_comm_NUMS_Main_Ex
} PQ_IP_AFEC_no_comm_Group_Main_Ex;

typedef enum
{
PQ_IP_VOF_OFF_Main_Ex,
PQ_IP_VOF_SD_Main_Ex,
PQ_IP_VOF_HD_Main_Ex,
PQ_IP_VOF_NUMS_Main_Ex
} PQ_IP_VOF_Group_Main_Ex;

typedef enum
{
PQ_IP_FOD_OFF_Main_Ex,
PQ_IP_FOD_ON_Main_Ex,
PQ_IP_FOD_NUMS_Main_Ex
} PQ_IP_FOD_Group_Main_Ex;

typedef enum
{
PQ_IP_MLP_EN_OFF_Main_Ex,
PQ_IP_MLP_EN_ON_Main_Ex,
PQ_IP_MLP_EN_ON_SD_Main_Ex,
PQ_IP_MLP_EN_ON_FHD_Main_Ex,
PQ_IP_MLP_EN_ON_4K_Main_Ex,
PQ_IP_MLP_EN_NUMS_Main_Ex
} PQ_IP_MLP_EN_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_Mot_Itlv_OFF_Main_Ex,
PQ_IP_SPF_Mot_Itlv_ON_Main_Ex,
PQ_IP_SPF_Mot_Itlv_NUMS_Main_Ex
} PQ_IP_SPF_Mot_Itlv_Group_Main_Ex;

typedef enum
{
PQ_IP_DiPF2_OFF_Main_Ex,
PQ_IP_DiPF2_ON_Main_Ex,
PQ_IP_DiPF2_SD_Main_Ex,
PQ_IP_DiPF2_ON_SDHDD_Main_Ex,
PQ_IP_DiPF2_NUMS_Main_Ex
} PQ_IP_DiPF2_Group_Main_Ex;

typedef enum
{
PQ_IP_DiPF2_Motion_DIPF1_4k_Main_Ex,
PQ_IP_DiPF2_Motion_DIPF1_Main_Ex,
PQ_IP_DiPF2_Motion_NUMS_Main_Ex
} PQ_IP_DiPF2_Motion_Group_Main_Ex;

typedef enum
{
PQ_IP_Spike_NR_OFF_Main_Ex,
PQ_IP_Spike_NR_S1_Main_Ex,
PQ_IP_Spike_NR_S1_1_Main_Ex,
PQ_IP_Spike_NR_S2_Main_Ex,
PQ_IP_Spike_NR_S3_Main_Ex,
PQ_IP_Spike_NR_4K_Main_Ex,
PQ_IP_Spike_NR_NUMS_Main_Ex
} PQ_IP_Spike_NR_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_DBK_OFF_Main_Ex,
PQ_IP_SPF_DBK_E2S2_Main_Ex,
PQ_IP_SPF_DBK_Low_Main_Ex,
PQ_IP_SPF_DBK_Mid_Main_Ex,
PQ_IP_SPF_DBK_High_Main_Ex,
PQ_IP_SPF_DBK_NUMS_Main_Ex
} PQ_IP_SPF_DBK_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_DBK_BKN_OFF_Main_Ex,
PQ_IP_SPF_DBK_BKN_T0_Main_Ex,
PQ_IP_SPF_DBK_BKN_T1_Main_Ex,
PQ_IP_SPF_DBK_BKN_T2_Main_Ex,
PQ_IP_SPF_DBK_BKN_T0_Jay_Main_Ex,
PQ_IP_SPF_DBK_BKN_T1_Jay_Main_Ex,
PQ_IP_SPF_DBK_BKN_T2_Jay_Main_Ex,
PQ_IP_SPF_DBK_BKN_AVN1_Main_Ex,
PQ_IP_SPF_DBK_BKN_AVN2_Main_Ex,
PQ_IP_SPF_DBK_BKN_AVP1_Main_Ex,
PQ_IP_SPF_DBK_BKN_AVP2_Main_Ex,
PQ_IP_SPF_DBK_BKN_2xsampling_Main_Ex,
PQ_IP_SPF_DBK_BKN_AVN0_Main_Ex,
PQ_IP_SPF_DBK_BKN_AVP0_Main_Ex,
PQ_IP_SPF_DBK_BKN_D1_Main_Ex,
PQ_IP_SPF_DBK_BKN_A1_Main_Ex,
PQ_IP_SPF_DBK_BKN_C2N_Main_Ex,
PQ_IP_SPF_DBK_BKN_SDtoHD_Main_Ex,
PQ_IP_SPF_DBK_BKN_HD1_Main_Ex,
PQ_IP_SPF_DBK_BKN_HD2_Main_Ex,
PQ_IP_SPF_DBK_BKN_HD3_Main_Ex,
PQ_IP_SPF_DBK_BKN_C1_Main_Ex,
PQ_IP_SPF_DBK_BKN_C2_Main_Ex,
PQ_IP_SPF_DBK_BKN_C3_Main_Ex,
PQ_IP_SPF_DBK_BKN_HDMI1_Main_Ex,
PQ_IP_SPF_DBK_BKN_HDMI2_Main_Ex,
PQ_IP_SPF_DBK_BKN_HDMI3_Main_Ex,
PQ_IP_SPF_DBK_BKN_UHD_Main_Ex,
PQ_IP_SPF_DBK_BKN_SEC_C1_Main_Ex,
PQ_IP_SPF_DBK_BKN_SEC_C3_Main_Ex,
PQ_IP_SPF_DBK_BKN_SEC_HDMI1_Main_Ex,
PQ_IP_SPF_DBK_BKN_SEC_HDMI2_Main_Ex,
PQ_IP_SPF_DBK_BKN_SEC_HDMI3_Main_Ex,
PQ_IP_SPF_DBK_BKN_SEC_HDMI1_LM18A_Main_Ex,
PQ_IP_SPF_DBK_BKN_NUMS_Main_Ex
} PQ_IP_SPF_DBK_BKN_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_DBK_HDE_OFF_Main_Ex,
PQ_IP_SPF_DBK_HDE_HD_Main_Ex,
PQ_IP_SPF_DBK_HDE_NUMS_Main_Ex
} PQ_IP_SPF_DBK_HDE_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_VDBK_OFF_Main_Ex,
PQ_IP_SPF_VDBK_HD_Main_Ex,
PQ_IP_SPF_VDBK_UHD_Main_Ex,
PQ_IP_SPF_VDBK_NUMS_Main_Ex
} PQ_IP_SPF_VDBK_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_WIDTH_DET_OFF_Main_Ex,
PQ_IP_SPF_WIDTH_DET_SD_Main_Ex,
PQ_IP_SPF_WIDTH_DET_HD_Main_Ex,
PQ_IP_SPF_WIDTH_DET_UHD_Main_Ex,
PQ_IP_SPF_WIDTH_DET_NUMS_Main_Ex
} PQ_IP_SPF_WIDTH_DET_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_SNR_OFF_Main_Ex,
PQ_IP_SPF_SNR_D1_Main_Ex,
PQ_IP_SPF_SNR_D2_Main_Ex,
PQ_IP_SPF_SNR_4K_Main_Ex,
PQ_IP_SPF_SNR_NUMS_Main_Ex
} PQ_IP_SPF_SNR_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_SNR_Std_Adj_OFF_Main_Ex,
PQ_IP_SPF_SNR_Std_Adj_D1_Main_Ex,
PQ_IP_SPF_SNR_Std_Adj_D1_SD_Main_Ex,
PQ_IP_SPF_SNR_Std_Adj_NUMS_Main_Ex
} PQ_IP_SPF_SNR_Std_Adj_Group_Main_Ex;

typedef enum
{
PQ_IP_SPF_SNR_Std_Stat_OFF_Main_Ex,
PQ_IP_SPF_SNR_Std_Stat_SD_Main_Ex,
PQ_IP_SPF_SNR_Std_Stat_HD_Main_Ex,
PQ_IP_SPF_SNR_Std_Stat_4K_Main_Ex,
PQ_IP_SPF_SNR_Std_Stat_NUMS_Main_Ex
} PQ_IP_SPF_SNR_Std_Stat_Group_Main_Ex;

typedef enum
{
PQ_IP_DMS_OFF_Main_Ex,
PQ_IP_DMS_ON_Main_Ex,
PQ_IP_DMS_NUMS_Main_Ex
} PQ_IP_DMS_Group_Main_Ex;

typedef enum
{
PQ_IP_DMS_H_OFF_Main_Ex,
PQ_IP_DMS_H_S0_Main_Ex,
PQ_IP_DMS_H_S1_Main_Ex,
PQ_IP_DMS_H_S2_Main_Ex,
PQ_IP_DMS_H_S3_Main_Ex,
PQ_IP_DMS_H_DTV_S1_Main_Ex,
PQ_IP_DMS_H_DTV_S2_Main_Ex,
PQ_IP_DMS_H_DTV_S3_Main_Ex,
PQ_IP_DMS_H_DTV_S4_Main_Ex,
PQ_IP_DMS_H_DTV_S5_Main_Ex,
PQ_IP_DMS_H_S1_HD_Main_Ex,
PQ_IP_DMS_H_S2_HD_Main_Ex,
PQ_IP_DMS_H_S3_HD_Main_Ex,
PQ_IP_DMS_H_SEC_S1_Main_Ex,
PQ_IP_DMS_H_S4_N_Main_Ex,
PQ_IP_DMS_H_S5_P_Main_Ex,
PQ_IP_DMS_H_S_TCL_Main_Ex,
PQ_IP_DMS_H_S_TCL_low_Main_Ex,
PQ_IP_DMS_H_S_TCL_mid_Main_Ex,
PQ_IP_DMS_H_S_TCL_high_Main_Ex,
PQ_IP_DMS_H_LM18A_S1_Main_Ex,
PQ_IP_DMS_H_S_LGE_mid_Main_Ex,
PQ_IP_DMS_H_LM18A_S2_Main_Ex,
PQ_IP_DMS_H_D1_Main_Ex,
PQ_IP_DMS_H_D2_Main_Ex,
PQ_IP_DMS_H_D3_Main_Ex,
PQ_IP_DMS_H_4K_Main_Ex,
PQ_IP_DMS_H_NUMS_Main_Ex
} PQ_IP_DMS_H_Group_Main_Ex;

typedef enum
{
PQ_IP_DMS_V_OFF_Main_Ex,
PQ_IP_DMS_V_S1_Main_Ex,
PQ_IP_DMS_V_S2_Main_Ex,
PQ_IP_DMS_V_S3_Main_Ex,
PQ_IP_DMS_V_HD_Main_Ex,
PQ_IP_DMS_V_DTV_S1_Main_Ex,
PQ_IP_DMS_V_DTV_S2_Main_Ex,
PQ_IP_DMS_V_DTV_S3_Main_Ex,
PQ_IP_DMS_V_S1_HD_Main_Ex,
PQ_IP_DMS_V_S2_HD_Main_Ex,
PQ_IP_DMS_V_S3_HD_Main_Ex,
PQ_IP_DMS_V_S4_N_Main_Ex,
PQ_IP_DMS_V_S5_P_Main_Ex,
PQ_IP_DMS_V_S_TCL_Main_Ex,
PQ_IP_DMS_V_S_LGE_Main_Ex,
PQ_IP_DMS_V_D1_Main_Ex,
PQ_IP_DMS_V_D2_Main_Ex,
PQ_IP_DMS_V_D3_Main_Ex,
PQ_IP_DMS_V_4K_Main_Ex,
PQ_IP_DMS_V_NUMS_Main_Ex
} PQ_IP_DMS_V_Group_Main_Ex;

typedef enum
{
PQ_IP_DMS_NMR_OFF_Main_Ex,
PQ_IP_DMS_NMR_ON_Main_Ex,
PQ_IP_DMS_NMR_ON_SD_Main_Ex,
PQ_IP_DMS_NMR_ON_SD_1_Main_Ex,
PQ_IP_DMS_NMR_NUMS_Main_Ex
} PQ_IP_DMS_NMR_Group_Main_Ex;

typedef enum
{
PQ_IP_PreCTI_V_OFF_Main_Ex,
PQ_IP_PreCTI_V_SD_CTI_MS5_low_Main_Ex,
PQ_IP_PreCTI_V_SD_CTI_MS3_mid_Main_Ex,
PQ_IP_PreCTI_V_SD_CTI_MS3_high_Main_Ex,
PQ_IP_PreCTI_V_HD_CTI_MS3_low_Main_Ex,
PQ_IP_PreCTI_V_HD_CTI_MS3_high_Main_Ex,
PQ_IP_PreCTI_V_NUMS_Main_Ex
} PQ_IP_PreCTI_V_Group_Main_Ex;

typedef enum
{
PQ_IP_PreCTI_V_VR_OFF_Main_Ex,
PQ_IP_PreCTI_V_VR_ON_Main_Ex,
PQ_IP_PreCTI_V_VR_SD_CTI_MS5_low_Main_Ex,
PQ_IP_PreCTI_V_VR_SD_CTI_MS3_mid_Main_Ex,
PQ_IP_PreCTI_V_VR_SD_CTI_MS3_high_Main_Ex,
PQ_IP_PreCTI_V_VR_HD_CTI_MS3_low_Main_Ex,
PQ_IP_PreCTI_V_VR_HD_CTI_MS3_high_Main_Ex,
PQ_IP_PreCTI_V_VR_NUMS_Main_Ex
} PQ_IP_PreCTI_V_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_pseudo_OFF_Main_Ex,
PQ_IP_VIP_pseudo_ON_Main_Ex,
PQ_IP_VIP_pseudo_NUMS_Main_Ex
} PQ_IP_VIP_pseudo_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Post_YC_delay_OFF_Main_Ex,
PQ_IP_VIP_Post_YC_delay_Y0Cb0Cr0_Main_Ex,
PQ_IP_VIP_Post_YC_delay_Y0Cb1Cr0_Main_Ex,
PQ_IP_VIP_Post_YC_delay_Y0Cb2Cr0_Main_Ex,
PQ_IP_VIP_Post_YC_delay_Y0Cb3Cr0_Main_Ex,
PQ_IP_VIP_Post_YC_delay_Y1Cb0Cr0_Main_Ex,
PQ_IP_VIP_Post_YC_delay_NUMS_Main_Ex
} PQ_IP_VIP_Post_YC_delay_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_YC_gain_offset_OFF_Main_Ex,
PQ_IP_VIP_YC_gain_offset_compress_1023_to_940_Main_Ex,
PQ_IP_VIP_YC_gain_offset_extend_940_to_1023_limitout_Main_Ex,
PQ_IP_VIP_YC_gain_offset_extend_940_to_1023_fullout_Main_Ex,
PQ_IP_VIP_YC_gain_offset_NUMS_Main_Ex
} PQ_IP_VIP_YC_gain_offset_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_LDE_setting_S1_Main_Ex,
PQ_IP_VIP_LDE_setting_NUMS_Main_Ex
} PQ_IP_VIP_LDE_setting_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_LDE_C_win1_S1_Main_Ex,
PQ_IP_VIP_LDE_C_win1_NUMS_Main_Ex
} PQ_IP_VIP_LDE_C_win1_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_LDE_C_win2_S1_Main_Ex,
PQ_IP_VIP_LDE_C_win2_NUMS_Main_Ex
} PQ_IP_VIP_LDE_C_win2_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_LDE_C_win3_S1_Main_Ex,
PQ_IP_VIP_LDE_C_win3_NUMS_Main_Ex
} PQ_IP_VIP_LDE_C_win3_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_LDE_C_win4_S1_Main_Ex,
PQ_IP_VIP_LDE_C_win4_NUMS_Main_Ex
} PQ_IP_VIP_LDE_C_win4_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_LDE_suppress_S1_Main_Ex,
PQ_IP_VIP_LDE_suppress_NUMS_Main_Ex
} PQ_IP_VIP_LDE_suppress_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_alpha_MIN_OFF_Main_Ex,
PQ_IP_VIP_Peaking_alpha_MIN_m1_Main_Ex,
PQ_IP_VIP_Peaking_alpha_MIN_m2_Main_Ex,
PQ_IP_VIP_Peaking_alpha_MIN_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_alpha_MIN_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_gain_by_Cedge_OFF_Main_Ex,
PQ_IP_VIP_Peaking_gain_by_Cedge_T2_Main_Ex,
PQ_IP_VIP_Peaking_gain_by_Cedge_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_gain_by_Cedge_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_Cplx_OFF_Main_Ex,
PQ_IP_VIP_Peaking_Cplx_SD_Main_Ex,
PQ_IP_VIP_Peaking_Cplx_HD_Main_Ex,
PQ_IP_VIP_Peaking_Cplx_4K_Main_Ex,
PQ_IP_VIP_Peaking_Cplx_SD_2K_Main_Ex,
PQ_IP_VIP_Peaking_Cplx_HD_2K_Main_Ex,
PQ_IP_VIP_Peaking_Cplx_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_Cplx_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band_SD_Main_Ex,
PQ_IP_VIP_Peaking_band_HD_Main_Ex,
PQ_IP_VIP_Peaking_band_4K_Main_Ex,
PQ_IP_VIP_Peaking_band_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band2_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band2_SD_Main_Ex,
PQ_IP_VIP_Peaking_band2_HD_Main_Ex,
PQ_IP_VIP_Peaking_band2_4K_Main_Ex,
PQ_IP_VIP_Peaking_band2_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band2_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band1_adaptive_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band1_adaptive_SD_Main_Ex,
PQ_IP_VIP_Peaking_band1_adaptive_HD_Main_Ex,
PQ_IP_VIP_Peaking_band1_adaptive_4K_Main_Ex,
PQ_IP_VIP_Peaking_band1_adaptive_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band1_adaptive_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band2_adaptive_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band2_adaptive_SD_Main_Ex,
PQ_IP_VIP_Peaking_band2_adaptive_HD_Main_Ex,
PQ_IP_VIP_Peaking_band2_adaptive_4K_Main_Ex,
PQ_IP_VIP_Peaking_band2_adaptive_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band2_adaptive_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band3_adaptive_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band3_adaptive_SD_Main_Ex,
PQ_IP_VIP_Peaking_band3_adaptive_HD_Main_Ex,
PQ_IP_VIP_Peaking_band3_adaptive_4K_Main_Ex,
PQ_IP_VIP_Peaking_band3_adaptive_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band3_adaptive_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band4_adaptive_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band4_adaptive_SD_Main_Ex,
PQ_IP_VIP_Peaking_band4_adaptive_HD_Main_Ex,
PQ_IP_VIP_Peaking_band4_adaptive_4K_Main_Ex,
PQ_IP_VIP_Peaking_band4_adaptive_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band4_adaptive_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band5_adaptive_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band5_adaptive_SD_Main_Ex,
PQ_IP_VIP_Peaking_band5_adaptive_HD_Main_Ex,
PQ_IP_VIP_Peaking_band5_adaptive_4K_Main_Ex,
PQ_IP_VIP_Peaking_band5_adaptive_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band5_adaptive_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_band6_adaptive_OFF_Main_Ex,
PQ_IP_VIP_Peaking_band6_adaptive_SD_Main_Ex,
PQ_IP_VIP_Peaking_band6_adaptive_HD_Main_Ex,
PQ_IP_VIP_Peaking_band6_adaptive_4K_Main_Ex,
PQ_IP_VIP_Peaking_band6_adaptive_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_band6_adaptive_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_shoot_ad_Y_OFF_Main_Ex,
PQ_IP_VIP_Peaking_shoot_ad_Y_ON_Main_Ex,
PQ_IP_VIP_Peaking_shoot_ad_Y_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_shoot_ad_Y_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_sum_OFF_Main_Ex,
PQ_IP_VIP_Peaking_sum_4K_LM19ADemo_Main_Ex,
PQ_IP_VIP_Peaking_sum_FHD_LM19ADemo_Main_Ex,
PQ_IP_VIP_Peaking_sum_FHD_LM19ADemo_future_Main_Ex,
PQ_IP_VIP_Peaking_sum_FHD_LM19ADemo_future_strong_Main_Ex,
PQ_IP_VIP_Peaking_sum_SD_Main_Ex,
PQ_IP_VIP_Peaking_sum_HD_Main_Ex,
PQ_IP_VIP_Peaking_sum_4K_Main_Ex,
PQ_IP_VIP_Peaking_sum_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_sum_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_sum_adaptive2_OFF_Main_Ex,
PQ_IP_VIP_Peaking_sum_adaptive2_SD_Main_Ex,
PQ_IP_VIP_Peaking_sum_adaptive2_HD_Main_Ex,
PQ_IP_VIP_Peaking_sum_adaptive2_4K_Main_Ex,
PQ_IP_VIP_Peaking_sum_adaptive2_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_sum_adaptive2_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_Mbt_OFF_Main_Ex,
PQ_IP_VIP_Peaking_Mbt_SD_Main_Ex,
PQ_IP_VIP_Peaking_Mbt_HD_Main_Ex,
PQ_IP_VIP_Peaking_Mbt_4K_Main_Ex,
PQ_IP_VIP_Peaking_Mbt_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_Mbt_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_H_dering2_OFF_Main_Ex,
PQ_IP_VIP_Peaking_H_dering2_SD_Main_Ex,
PQ_IP_VIP_Peaking_H_dering2_HD_Main_Ex,
PQ_IP_VIP_Peaking_H_dering2_4K_Main_Ex,
PQ_IP_VIP_Peaking_H_dering2_SD_2K_Main_Ex,
PQ_IP_VIP_Peaking_H_dering2_HD_2K_Main_Ex,
PQ_IP_VIP_Peaking_H_dering2_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_H_dering2_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_V_dering1_OFF_Main_Ex,
PQ_IP_VIP_Peaking_V_dering1_SD_Main_Ex,
PQ_IP_VIP_Peaking_V_dering1_HD_Main_Ex,
PQ_IP_VIP_Peaking_V_dering1_4K_Main_Ex,
PQ_IP_VIP_Peaking_V_dering1_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_V_dering1_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_V_dering2_OFF_Main_Ex,
PQ_IP_VIP_Peaking_V_dering2_SD_Main_Ex,
PQ_IP_VIP_Peaking_V_dering2_HD_Main_Ex,
PQ_IP_VIP_Peaking_V_dering2_4K_Main_Ex,
PQ_IP_VIP_Peaking_V_dering2_SD_2K_Main_Ex,
PQ_IP_VIP_Peaking_V_dering2_HD_2K_Main_Ex,
PQ_IP_VIP_Peaking_V_dering2_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_V_dering2_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_postpk_OFF_Main_Ex,
PQ_IP_VIP_postpk_SD_Main_Ex,
PQ_IP_VIP_postpk_HD_Main_Ex,
PQ_IP_VIP_postpk_4K_Main_Ex,
PQ_IP_VIP_postpk_SD_2K_Main_Ex,
PQ_IP_VIP_postpk_HD_2K_Main_Ex,
PQ_IP_VIP_postpk_NUMS_Main_Ex
} PQ_IP_VIP_postpk_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Peaking_Drv_VR_OFF_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_SD_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_HD_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_4K_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_HD_SDin_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_SD_2K_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_HD_2K_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_HD_SDin_2K_Main_Ex,
PQ_IP_VIP_Peaking_Drv_VR_NUMS_Main_Ex
} PQ_IP_VIP_Peaking_Drv_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_UVC_OFF_Main_Ex,
PQ_IP_VIP_UVC_ON_Main_Ex,
PQ_IP_VIP_UVC_ON_6CC_Main_Ex,
PQ_IP_VIP_UVC_ON_RGB_Main_Ex,
PQ_IP_VIP_UVC_ON_HDR_Main_Ex,
PQ_IP_VIP_UVC_ON_noAC_Main_Ex,
PQ_IP_VIP_UVC_NUMS_Main_Ex
} PQ_IP_VIP_UVC_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_cplxLPF_OFF_Main_Ex,
PQ_IP_VIP_cplxLPF_ON_Main_Ex,
PQ_IP_VIP_cplxLPF_NUMS_Main_Ex
} PQ_IP_VIP_cplxLPF_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_ACback_Mode_Mode0_Main_Ex,
PQ_IP_VIP_ACback_Mode_Mode1_Main_Ex,
PQ_IP_VIP_ACback_Mode_NUMS_Main_Ex
} PQ_IP_VIP_ACback_Mode_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_ACback_Gain_Gain1_Main_Ex,
PQ_IP_VIP_ACback_Gain_NUMS_Main_Ex
} PQ_IP_VIP_ACback_Gain_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_UVC_Mux_Mode0_Main_Ex,
PQ_IP_VIP_UVC_Mux_Mode1_Main_Ex,
PQ_IP_VIP_UVC_Mux_NUMS_Main_Ex
} PQ_IP_VIP_UVC_Mux_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_UVC_dark_OFF_Main_Ex,
PQ_IP_VIP_UVC_dark_ON_Main_Ex,
PQ_IP_VIP_UVC_dark_NUMS_Main_Ex
} PQ_IP_VIP_UVC_dark_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_Post_SNR_OFF_Main_Ex,
PQ_IP_VIP_Post_SNR_ON_Main_Ex,
PQ_IP_VIP_Post_SNR_NUMS_Main_Ex
} PQ_IP_VIP_Post_SNR_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_ICC_Target_OFF_Main_Ex,
PQ_IP_VIP_ICC_Target_ON_Main_Ex,
PQ_IP_VIP_ICC_Target_NUMS_Main_Ex
} PQ_IP_VIP_ICC_Target_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_IBC_weight_W6_Main_Ex,
PQ_IP_VIP_IBC_weight_W8_Main_Ex,
PQ_IP_VIP_IBC_weight_NUMS_Main_Ex
} PQ_IP_VIP_IBC_weight_Group_Main_Ex;

typedef enum
{
PQ_IP_VIP_ACK_OFF_Main_Ex,
PQ_IP_VIP_ACK_NUMS_Main_Ex
} PQ_IP_VIP_ACK_Group_Main_Ex;

typedef enum
{
PQ_IP_VOP2_out_dither_OFF_Main_Ex,
PQ_IP_VOP2_out_dither_ON_Main_Ex,
PQ_IP_VOP2_out_dither_NUMS_Main_Ex
} PQ_IP_VOP2_out_dither_Group_Main_Ex;

typedef enum
{
PQ_IP_OP1_LBOX_SD_Main_Ex,
PQ_IP_OP1_LBOX_FHD_Main_Ex,
PQ_IP_OP1_LBOX_UHD_Main_Ex,
PQ_IP_OP1_LBOX_HD_Main_Ex,
PQ_IP_OP1_LBOX_QHD_Main_Ex,
PQ_IP_OP1_LBOX_NUMS_Main_Ex
} PQ_IP_OP1_LBOX_Group_Main_Ex;

typedef enum
{
PQ_IP_HSL_Enable_OFF_Main_Ex,
PQ_IP_HSL_Enable_ON_Main_Ex,
PQ_IP_HSL_Enable_NUMS_Main_Ex
} PQ_IP_HSL_Enable_Group_Main_Ex;

typedef enum
{
PQ_IP_HSL_Setting_H_NS_Y_M_Main_Ex,
PQ_IP_HSL_Setting_H_NS_Y_Main_Ex,
PQ_IP_HSL_Setting_H_UVN_Y_M_Main_Ex,
PQ_IP_HSL_Setting_H_NS_L_Main_Ex,
PQ_IP_HSL_Setting_H_NS_V_Main_Ex,
PQ_IP_HSL_Setting_NUMS_Main_Ex
} PQ_IP_HSL_Setting_Group_Main_Ex;

typedef enum
{
PQ_IP_HSL_Global_Settings_ON_Main_Ex,
PQ_IP_HSL_Global_Settings_NUMS_Main_Ex
} PQ_IP_HSL_Global_Settings_Group_Main_Ex;

typedef enum
{
PQ_IP_HSL_VR_ON_Main_Ex,
PQ_IP_HSL_VR_OFF_Main_Ex,
PQ_IP_HSL_VR_NUMS_Main_Ex
} PQ_IP_HSL_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_DMSNR_OFF_Main_Ex,
PQ_IP_DMSNR_ON_Main_Ex,
PQ_IP_DMSNR_4K_Main_Ex,
PQ_IP_DMSNR_4K_current_Main_Ex,
PQ_IP_DMSNR_NUMS_Main_Ex
} PQ_IP_DMSNR_Group_Main_Ex;

typedef enum
{
PQ_IP_SwDriver_OFF_Main_Ex,
PQ_IP_SwDriver_ALL_Main_Ex,
PQ_IP_SwDriver_SD_Main_Ex,
PQ_IP_SwDriver_SD_new_Main_Ex,
PQ_IP_SwDriver_SD_DFET_off_Main_Ex,
PQ_IP_SwDriver_DynamicDNR_ON_Main_Ex,
PQ_IP_SwDriver_HD_Main_Ex,
PQ_IP_SwDriver_HD_DFET_off_Main_Ex,
PQ_IP_SwDriver_LM18A_Demo_Main_Ex,
PQ_IP_SwDriver_LM18A_DemoSD_Main_Ex,
PQ_IP_SwDriver_NUMS_Main_Ex
} PQ_IP_SwDriver_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_0_IP_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_IP_OFF_4K_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_IP_frame_0_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_IP_frame_0_p_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_IP_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_IP_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_0_IP_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_1_IP_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_IP_frame_0_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_IP_frame_0_p_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_IP_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_IP_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_1_IP_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_5_IP_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_IP_frame_0_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_IP_frame_0_p_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_IP_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_IP_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_5_IP_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_9_IP_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_i_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_p_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_i_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_p_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_i_4K_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_p_4K_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_frame_9_UC_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_IP_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_9_IP_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_Dummy_IP_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_IP_frame_0_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_IP_frame_0_p_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_IP_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_IP_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_Dummy_IP_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_0_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_OFF_4K_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_OFF_4K_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_frame_0_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_frame_0_p_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_OFF_UC_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_frame_0_p_4k_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_0_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_0_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_1_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_frame_1_i_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_frame_1_p_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_1_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_1_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_5_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_frame_5_i_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_frame_5_i_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_frame_5_p_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_frame_5_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_frame_5_UC_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_5_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_5_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_9_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_i_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_p_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_i_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_p_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_i_4K_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_p_4K_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_frame_9_UC_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_9_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_9_Group_Main_Ex;

typedef enum
{
PQ_IP_MM_DS_frame_delay_Dummy_OFF_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_frame_9_i_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_frame_9_p_NTSC_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_frame_9_i_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_frame_9_p_PAL_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_dummy_Main_Ex,
PQ_IP_MM_DS_frame_delay_Dummy_NUMS_Main_Ex
} PQ_IP_MM_DS_frame_delay_Dummy_Group_Main_Ex;

typedef enum
{
PQ_IP_BWR_OFF_Main_Ex,
PQ_IP_BWR_BWR_422_Main_Ex,
PQ_IP_BWR_BWR_444_Main_Ex,
PQ_IP_BWR_BWR_RGB_Main_Ex,
PQ_IP_BWR_NUMS_Main_Ex
} PQ_IP_BWR_Group_Main_Ex;

typedef enum
{
PQ_IP_BWS_OFF_Main_Ex,
PQ_IP_BWS_BWS1_Main_Ex,
PQ_IP_BWS_BWS2_Main_Ex,
PQ_IP_BWS_NUMS_Main_Ex
} PQ_IP_BWS_Group_Main_Ex;

typedef enum
{
PQ_IP_BWS_UI_VR_OFF_Main_Ex,
PQ_IP_BWS_UI_VR_De_Comm_Main_Ex,
PQ_IP_BWS_UI_VR_BWS1_Main_Ex,
PQ_IP_BWS_UI_VR_BWS2_Main_Ex,
PQ_IP_BWS_UI_VR_NUMS_Main_Ex
} PQ_IP_BWS_UI_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_BWD_OFF_Main_Ex,
PQ_IP_BWD_ON_Main_Ex,
PQ_IP_BWD_LOW_Main_Ex,
PQ_IP_BWD_MID_Main_Ex,
PQ_IP_BWD_HIGH_Main_Ex,
PQ_IP_BWD_NUMS_Main_Ex
} PQ_IP_BWD_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_24_4R_Main_Ex,
PQ_IP_MADi_24_2R_Main_Ex,
PQ_IP_MADi_25_4R_Main_Ex,
PQ_IP_MADi_25_2R_Main_Ex,
PQ_IP_MADi_26_4R_Main_Ex,
PQ_IP_MADi_26_2R_Main_Ex,
PQ_IP_MADi_27_4R_Main_Ex,
PQ_IP_MADi_27_2R_Main_Ex,
PQ_IP_MADi_P_MODE8_Main_Ex,
PQ_IP_MADi_P_MODE10_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_8Frame_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_Main_Ex,
PQ_IP_MADi_P_MODE_MOT8_Main_Ex,
PQ_IP_MADi_24_4R_880_Main_Ex,
PQ_IP_MADi_24_2R_880_Main_Ex,
PQ_IP_MADi_25_4R_880_Main_Ex,
PQ_IP_MADi_25_4R_884_Main_Ex,
PQ_IP_MADi_25_2R_884_Main_Ex,
PQ_IP_MADi_25_2R_880_Main_Ex,
PQ_IP_MADi_25_4R_MC_Main_Ex,
PQ_IP_MADi_25_4R_MC_NW_Main_Ex,
PQ_IP_MADi_25_6R_MC_NW_Main_Ex,
PQ_IP_MADi_25_6R_MC_Main_Ex,
PQ_IP_MADi_25_12F_8R_MC_Main_Ex,
PQ_IP_MADi_25_14F_8R_MC_Main_Ex,
PQ_IP_MADi_25_16F_8R_MC_Main_Ex,
PQ_IP_MADi_P_MODE8_444_Main_Ex,
PQ_IP_MADi_P_MODE8_2BYTE_3D_Main_Ex,
PQ_IP_MADi_P_MODE10_444_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_4Frame_Main_Ex,
PQ_IP_MADi_P_MODE_MOT8_4Frame_Main_Ex,
PQ_IP_MADi_RFBL_2D_Main_Ex,
PQ_IP_MADi_RFBL_25D_Main_Ex,
PQ_IP_MADi_RFBL_3D_Main_Ex,
PQ_IP_MADi_RFBL_P_MODE10_MOT_Main_Ex,
PQ_IP_MADi_RFBL_P_MODE10_MOT_Y8_Main_Ex,
PQ_IP_MADi_RFBL_P_MODE8_MOT_Main_Ex,
PQ_IP_MADi_25_14F_6R_MC_Main_Ex,
PQ_IP_MADi_P_MODE_MC_3Frame_Main_Ex,
PQ_IP_MADi_P_MODE_MC_4Frame_Main_Ex,
PQ_IP_MADi_P_MODE_MC_6Frame_6R_Main_Ex,
PQ_IP_MADi_P_MODE_MC_12Frame_8R_Main_Ex,
PQ_IP_MADi_25_8F_4R_MC_Main_Ex,
PQ_IP_MADi_25_6F_4R_MC_I_Main_Ex,
PQ_IP_MADi_25_6F_4R_MC_P_Main_Ex,
PQ_IP_MADi_P_MODE_MC_6Frame_Main_Ex,
PQ_IP_MADi_FBL_Mode_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_noNR_Main_Ex,
PQ_IP_MADi_FBL_P_MODE10_MOT_Y8_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NR_YOnly_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NR_YMOnly_Main_Ex,
PQ_IP_MADi_P_MODE10_NR_YOnly_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NR_Yonly_4Frame_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NR_YMOnly_4Frame_Main_Ex,
PQ_IP_MADi_P_MODE10_NR_Yonly_4Frame_Main_Ex,
PQ_IP_MADi_P_MODE_N_MC_12Frame_8R_Main_Ex,
PQ_IP_MADi_P_MODE_P_MC_12Frame_8R_Main_Ex,
PQ_IP_MADi_25_16F_6R_MC_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NR_Yonly_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NR_YConly_Main_Ex,
PQ_IP_MADi_P_MODE_MOT10_NO_DNR_Main_Ex,
PQ_IP_MADi_P_MODE_Y8C8M4_RWDIFF2_Main_Ex,
PQ_IP_MADi_P_MODE_MC_YC8_4Frame_Main_Ex,
PQ_IP_MADi_25_8F_4R_MC_Y8C8M4_Main_Ex,
PQ_IP_MADi_I_Mode_Unlock_Main_Ex,
PQ_IP_MADi_25_4R_Y8C8M4_Main_Ex,
PQ_IP_MADi_P_MODE_MOT8_Y8C8M4_Main_Ex,
PQ_IP_MADi_25_2R_Y8C8M4_Main_Ex,
PQ_IP_MADi_P_MODE_Y8C4_COMPACT_Main_Ex,
PQ_IP_MADi_NUMS_Main_Ex
} PQ_IP_MADi_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_VR_24_4R_Main_Ex,
PQ_IP_MADi_VR_24_2R_Main_Ex,
PQ_IP_MADi_VR_25_4R_Main_Ex,
PQ_IP_MADi_VR_25_2R_Main_Ex,
PQ_IP_MADi_VR_26_4R_Main_Ex,
PQ_IP_MADi_VR_26_2R_Main_Ex,
PQ_IP_MADi_VR_27_4R_Main_Ex,
PQ_IP_MADi_VR_27_2R_Main_Ex,
PQ_IP_MADi_VR_P_MODE8_Main_Ex,
PQ_IP_MADi_VR_P_MODE10_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_8Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT8_Main_Ex,
PQ_IP_MADi_VR_24_4R_880_Main_Ex,
PQ_IP_MADi_VR_24_2R_880_Main_Ex,
PQ_IP_MADi_VR_25_4R_880_Main_Ex,
PQ_IP_MADi_VR_25_4R_884_Main_Ex,
PQ_IP_MADi_VR_25_2R_884_Main_Ex,
PQ_IP_MADi_VR_25_2R_880_Main_Ex,
PQ_IP_MADi_VR_25_4R_MC_Main_Ex,
PQ_IP_MADi_VR_25_4R_MC_NW_Main_Ex,
PQ_IP_MADi_VR_25_6R_MC_NW_Main_Ex,
PQ_IP_MADi_VR_25_6R_MC_Main_Ex,
PQ_IP_MADi_VR_25_12F_8R_MC_Main_Ex,
PQ_IP_MADi_VR_25_14F_8R_MC_Main_Ex,
PQ_IP_MADi_VR_25_16F_8R_MC_Main_Ex,
PQ_IP_MADi_VR_P_MODE8_444_Main_Ex,
PQ_IP_MADi_VR_P_MODE8_2BYTE_3D_Main_Ex,
PQ_IP_MADi_VR_P_MODE10_444_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_4Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT8_4Frame_Main_Ex,
PQ_IP_MADi_VR_RFBL_2D_Main_Ex,
PQ_IP_MADi_VR_RFBL_25D_Main_Ex,
PQ_IP_MADi_VR_RFBL_3D_Main_Ex,
PQ_IP_MADi_VR_RFBL_P_MODE10_MOT_Main_Ex,
PQ_IP_MADi_VR_RFBL_P_MODE10_MOT_Y8_Main_Ex,
PQ_IP_MADi_VR_RFBL_P_MODE8_MOT_Main_Ex,
PQ_IP_MADi_VR_25_16F_6R_MC_Main_Ex,
PQ_IP_MADi_VR_25_14F_6R_MC_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MC_3Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MC_4Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MC_6Frame_6R_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MC_12Frame_8R_Main_Ex,
PQ_IP_MADi_VR_25_8F_4R_MC_Main_Ex,
PQ_IP_MADi_VR_25_6F_4R_MC_I_Main_Ex,
PQ_IP_MADi_VR_25_6F_4R_MC_P_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MC_6Frame_Main_Ex,
PQ_IP_MADi_VR_FBL_Mode_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_noNR_Main_Ex,
PQ_IP_MADi_VR_FBL_P_MODE10_MOT_Y8_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_NR_Yonly_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_NO_DNR_Main_Ex,
PQ_IP_MADi_VR_P_MODE_NO_DNR_NO_MOT_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_NR_YMOnly_Main_Ex,
PQ_IP_MADi_VR_P_MODE10_NR_YOnly_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_NR_YConly_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_NR_Yonly_4Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT10_NR_YMOnly_4Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE10_NR_Yonly_4Frame_Main_Ex,
PQ_IP_MADi_VR_P_MODE_N_MC_12Frame_8R_Main_Ex,
PQ_IP_MADi_VR_P_MODE_P_MC_12Frame_8R_Main_Ex,
PQ_IP_MADi_VR_P_MODE_Y8C4_DNRY_Main_Ex,
PQ_IP_MADi_VR_P_MODE_Y8C8M4_RWDIFF2_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MC_YC8_4Frame_Main_Ex,
PQ_IP_MADi_VR_25_8F_4R_MC_Y8C8M4_Main_Ex,
PQ_IP_MADi_VR_I_Mode_Unlock_Main_Ex,
PQ_IP_MADi_VR_25_4R_Y8C8M4_Main_Ex,
PQ_IP_MADi_VR_P_MODE_MOT8_Y8C8M4_Main_Ex,
PQ_IP_MADi_VR_25_2R_Y8C8M4_Main_Ex,
PQ_IP_MADi_VR_P_MODE_Y8C4_COMPACT_Main_Ex,
PQ_IP_MADi_VR_P_MODE_Y8C8M4_RWDIFF2_PHOTO422_Main_Ex,
PQ_IP_MADi_VR_P_MODE8_444_PHOTO444_Main_Ex,
PQ_IP_MADi_VR_NUMS_Main_Ex
} PQ_IP_MADi_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_Motion_MOT_4R_5_Main_Ex,
PQ_IP_MADi_Motion_MOT_4R_6_Main_Ex,
PQ_IP_MADi_Motion_MOT_4R_7_Main_Ex,
PQ_IP_MADi_Motion_MOT_2R_Main_Ex,
PQ_IP_MADi_Motion_MOT_4R_5_MC_Main_Ex,
PQ_IP_MADi_Motion_MOT_PMODE_Main_Ex,
PQ_IP_MADi_Motion_MOT_4R_5_MC_SDD_Main_Ex,
PQ_IP_MADi_Motion_NUMS_Main_Ex
} PQ_IP_MADi_Motion_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_DFK_OFF_Main_Ex,
PQ_IP_MADi_DFK_DFK1_Main_Ex,
PQ_IP_MADi_DFK_DFK2_Main_Ex,
PQ_IP_MADi_DFK_DFK3_Main_Ex,
PQ_IP_MADi_DFK_DFK4_Main_Ex,
PQ_IP_MADi_DFK_DFK5_Main_Ex,
PQ_IP_MADi_DFK_DFK6_Main_Ex,
PQ_IP_MADi_DFK_NUMS_Main_Ex
} PQ_IP_MADi_DFK_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_SST_OFF_Main_Ex,
PQ_IP_MADi_SST_SST1_Main_Ex,
PQ_IP_MADi_SST_SST2_Main_Ex,
PQ_IP_MADi_SST_SST3_Main_Ex,
PQ_IP_MADi_SST_SST4_Main_Ex,
PQ_IP_MADi_SST_SST5_Main_Ex,
PQ_IP_MADi_SST_SST6_Main_Ex,
PQ_IP_MADi_SST_SST_Rec1_Main_Ex,
PQ_IP_MADi_SST_SST3_adp_Main_Ex,
PQ_IP_MADi_SST_NUMS_Main_Ex
} PQ_IP_MADi_SST_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_SST_EN_VR_OFF_Main_Ex,
PQ_IP_MADi_SST_EN_VR_ON_Main_Ex,
PQ_IP_MADi_SST_EN_VR_NUMS_Main_Ex
} PQ_IP_MADi_SST_EN_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_MADi_EODiW_OFF_Main_Ex,
PQ_IP_MADi_EODiW_W1_Main_Ex,
PQ_IP_MADi_EODiW_W2_Main_Ex,
PQ_IP_MADi_EODiW_W3_Main_Ex,
PQ_IP_MADi_EODiW_NUMS_Main_Ex
} PQ_IP_MADi_EODiW_Group_Main_Ex;

typedef enum
{
PQ_IP_DS_OFF_Main_Ex,
PQ_IP_DS_ON_Main_Ex,
PQ_IP_DS_NUMS_Main_Ex
} PQ_IP_DS_Group_Main_Ex;

typedef enum
{
PQ_IP_DS_Settings_OFF_Main_Ex,
PQ_IP_DS_Settings_W0_Main_Ex,
PQ_IP_DS_Settings_W1_Main_Ex,
PQ_IP_DS_Settings_W2_Main_Ex,
PQ_IP_DS_Settings_SD_Main_Ex,
PQ_IP_DS_Settings_NUMS_Main_Ex
} PQ_IP_DS_Settings_Group_Main_Ex;

typedef enum
{
PQ_IP_DS_Drv_VR_OFF_Main_Ex,
PQ_IP_DS_Drv_VR_SD_Main_Ex,
PQ_IP_DS_Drv_VR_HD_Main_Ex,
PQ_IP_DS_Drv_VR_4K_Main_Ex,
PQ_IP_DS_Drv_VR_NUMS_Main_Ex
} PQ_IP_DS_Drv_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_UCDi_OFF_Main_Ex,
PQ_IP_UCDi_SD_1_Main_Ex,
PQ_IP_UCDi_SD_2_Main_Ex,
PQ_IP_UCDi_SD_3_Main_Ex,
PQ_IP_UCDi_RF_1_Main_Ex,
PQ_IP_UCDi_RF_2_Main_Ex,
PQ_IP_UCDi_RF_3_Main_Ex,
PQ_IP_UCDi_T12_Main_Ex,
PQ_IP_UCDi_NUMS_Main_Ex
} PQ_IP_UCDi_Group_Main_Ex;

typedef enum
{
PQ_IP_UCDi_UI_VR_OFF_Main_Ex,
PQ_IP_UCDi_UI_VR_De_Comm_Main_Ex,
PQ_IP_UCDi_UI_VR_SD_1_Main_Ex,
PQ_IP_UCDi_UI_VR_SD_2_Main_Ex,
PQ_IP_UCDi_UI_VR_SD_3_Main_Ex,
PQ_IP_UCDi_UI_VR_RF_1_Main_Ex,
PQ_IP_UCDi_UI_VR_RF_2_Main_Ex,
PQ_IP_UCDi_UI_VR_RF_3_Main_Ex,
PQ_IP_UCDi_UI_VR_T12_Main_Ex,
PQ_IP_UCDi_UI_VR_NUMS_Main_Ex
} PQ_IP_UCDi_UI_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_UC_CTL_OFF_Main_Ex,
PQ_IP_UC_CTL_ON_Main_Ex,
PQ_IP_UC_CTL_ON_DHD_Main_Ex,
PQ_IP_UC_CTL_ON_UCNR_Main_Ex,
PQ_IP_UC_CTL_ON_TV_Main_Ex,
PQ_IP_UC_CTL_NUMS_Main_Ex
} PQ_IP_UC_CTL_Group_Main_Ex;

typedef enum
{
PQ_IP_UC_CTL_UI_VR_OFF_Main_Ex,
PQ_IP_UC_CTL_UI_VR_De_Comm_Main_Ex,
PQ_IP_UC_CTL_UI_VR_ON_Main_Ex,
PQ_IP_UC_CTL_UI_VR_ON_DHD_Main_Ex,
PQ_IP_UC_CTL_UI_VR_ON_UCNR_Main_Ex,
PQ_IP_UC_CTL_UI_VR_ON_TV_Main_Ex,
PQ_IP_UC_CTL_UI_VR_NUMS_Main_Ex
} PQ_IP_UC_CTL_UI_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_UCD_VR_Default_Main_Ex,
PQ_IP_UCD_VR_NUMS_Main_Ex
} PQ_IP_UCD_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_UCD_PR_Default_Main_Ex,
PQ_IP_UCD_PR_NUMS_Main_Ex
} PQ_IP_UCD_PR_Group_Main_Ex;

typedef enum
{
PQ_IP_TMO_VR_Default_Main_Ex,
PQ_IP_TMO_VR_Off_Main_Ex,
PQ_IP_TMO_VR_NUMS_Main_Ex
} PQ_IP_TMO_VR_Group_Main_Ex;

typedef enum
{
PQ_IP_Game_Mode_Type_Type0_Main_Ex,
PQ_IP_Game_Mode_Type_Type1_Main_Ex,
PQ_IP_Game_Mode_Type_NUMS_Main_Ex
} PQ_IP_Game_Mode_Type_Group_Main_Ex;

typedef enum
{
PQ_IP_HVSP_Force_Default_Main_Ex,
PQ_IP_HVSP_Force_NUMS_Main_Ex
} PQ_IP_HVSP_Force_Group_Main_Ex;

extern U8 MST_SkipRule_IP_Main_Ex[PQ_IP_NUM_Main_Ex];
extern EN_IPTAB_INFO PQ_IPTAB_INFO_Main_Ex[];
extern U8 QMAP_1920_Main_Ex[QM_INPUTTYPE_NUM_Main_Ex][PQ_IP_NUM_Main_Ex];
extern U8 QMAP_1366_Main_Ex[QM_INPUTTYPE_NUM_Main_Ex][PQ_IP_NUM_Main_Ex];
extern U8 QMAP_4K2K_Main_Ex[QM_INPUTTYPE_NUM_Main_Ex][PQ_IP_NUM_Main_Ex];

#endif
