//<MStar Software>
//******************************************************************************
// MStar Software
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//<MStar Software>
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////

#ifndef MHAL_FRC_H
#define MHAL_FRC_H

#include "hwreg_frc_map.h"
#include "hwreg_frc.h"
#include "hwreg_sc.h"
#include "mhal_xc_chip_config.h"

#ifdef MHAL_FRC_C
#define INTERFACE
#else
#define INTERFACE extern
#endif

//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
#define CRYSTAL_CLOCK    12000000ul//24000000ul
#define MST_CLOCK_HZ    CRYSTAL_CLOCK
#define MST_CLOCK_KHZ    (MST_CLOCK_HZ / 1000)
#define MST_CLOCK_MHZ    (MST_CLOCK_KHZ / 1000)
#define FRC_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF)
#define FRC_IP_ALL 0xff
#define FRC_IP_NULL 0xff
#define REG_ADDR_SIZE 2
#define REG_MASK_SIZE 1
//#define REG_TABLE_END          0xFFFF
#define _END_OF_TBL_        0xFFFF
#define  MS_ALG_CMD_LEN         16
#define FRC_BK_SWITCH(_x_)\
        MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
#define FRC_BK_CURRENT   \
        MDrv_ReadByte(REG_FRC_BANK_BASE)

#define VSTART_OFFSET 2
#ifdef STELLAR
#define VSTART_OFFSET_FHD 1
#endif
#define VSYNCSTART_OFFSET 14
#ifdef STELLAR
#define VSYNC_FRONT_PORCH 5
#else
#define VSYNC_FRONT_PORCH 11
#endif
#define VSYNC_OFFSET 2
#define VSYNC_FRONT_PORCH_EPI 7

#define FRC_Y_TRIGGER_DE_START 8

#ifdef PATCH_TCON_BRING_UP
#define VSYNC_OFFSET_FOR_UD_VB1_8LANE_DRDEPI 65
#define FRC_Y_TRIGGER_START_OFFSET_YUV_FOR_UD_VB1_8LANE_DRDEPI 69
#define FRC_Y_TRIGGER_START_OFFSET_RGB_FOR_UD_VB1_8LANE_DRDEPI 10
#define FRC_TGEN_VSYNC_START_FOR_UD_VB1_8LANE_DRDEPI 1
#define FRC_TGEN_VSYNC_END_FOR_UD_VB1_8LANE_DRDEPI 3
#endif

#define FRC_YTRIG_OFFSET (2)

#define FRC_COMPOSER_SOURCE_MODE_VIP    (0x01)

#define FRC_COMPOSER_SOURCE_MODE_MASK   (0x83)

typedef struct
{
    MS_U8 *pIPTable;
    MS_U8 u8TabNums;
    MS_U8 u8TabIdx;
} EN_FRC_IP_Info;

typedef struct
{
    MS_U8 *pIPTable;
    MS_U8 u8TabNums;
} EN_FRC_IPTAB_INFO;

typedef struct  __attribute__((packed))
{
    MS_U8 u8FRC_InputType_Num;
    MS_U8 u8FRC_IP_Num;
}FRCTABLE_INFO;


typedef enum
{
    E_FRC_op2_gamma_table = 1,  // gamma table
    E_FRC_od_table                = 2, // OD table
    E_FRC_ld_table                 = 3, // Local diming table
} FRC_CLIENT_TABLE;

//-------------------------------------------------------------------------------------------------
//  Structure enum
//-------------------------------------------------------------------------------------------------

typedef enum
{
    FRC_IP_MEM_IP_YC_8              = 0x00,
    FRC_IP_MEM_IP_YC_10             = 0x01,
    FRC_IP_MEM_IP_RGB_8             = 0x02,
    FRC_IP_MEM_IP_RGB_10            = 0x03,
    FRC_IP_MEM_IP_YC_10_SPECIAL     = 0x04,
    FRC_IP_MEM_IP_YUV_8             = 0x05,
    FRC_IP_MEM_IP_RGB_10_SPECIAL    = 0x06,
    FRC_IP_MEM_IP_YUV_10_SPECIAL    = 0x07

} FRC_IP_MEM_MODE_e;

typedef enum
{
    FRC_MIRROR_OFF,
    FRC_MIRROR_H_MODE,
    FRC_MIRROR_V_MODE,
    FRC_MIRROR_HV_MODE
} FRC_MirrorModeType_e;

typedef struct MST_PANEL_INFO_s
{
    // Basic
    MS_U16 u16HStart; //ursa scaler
    MS_U16 u16VStart; //ursa scaler
    MS_U16 u16Width; //ursa scaler
    MS_U16 u16Height; //ursa scaler
    MS_U16 u16HTotal; //ursa scaler
    MS_U16 u16VTotal; //ursa scaler

    MS_U16 u16DE_VStart;

    MS_U16 u16DefaultVFreq;

    // LPLL
    MS_U16 u16LPLL_InputDiv;
    MS_U16 u16LPLL_LoopDiv;
    MS_U16 u16LPLL_OutputDiv;

    MS_U8  u8LPLL_Type;
    MS_U8  u8LPLL_Mode;

    // sync
    MS_U8  u8HSyncWidth;
    MS_BOOL bPnlDblVSync;

    // output control
    MS_U16 u16OCTRL;
    MS_U16 u16OSTRL;
    MS_U16 u16ODRV;
    MS_U16 u16DITHCTRL;

    // MOD
    MS_U16 u16MOD_CTRL0;  // BIT2: tiMode, BIT5: lvdsSwapPol, BIT6: lvdsSwapCh
    MS_U8  u8MOD_CTRL2;
    MS_U16 u16MOD_CTRL9;
    MS_U16 u16MOD_CTRLA;  // BIT2: invertDE, BIT3: invertVS, BIT12: invertHS
    MS_U8  u8MOD_CTRLB;   // BIT0~1: panelBitNums

    MS_U8  u8MOD_CTRL77;    //pre-emphasis level
    MS_U8  u8MOD_CTRL78;
    //LGE [vivakjh] 2008/11/12     Add for DVB PDP Panel
    //Additional Info.(V Total)
    MS_U16 u16VTotal60Hz; //ursa scaler
    MS_U16 u16VTotal50Hz; //ursa scaler
    MS_U16 u16VTotal48Hz; //ursa scaler
    //[vivakjh] 2008/12/23    Add for adjusting the MRE in PDP S6
    MS_U16 u16VStart60Hz;
    MS_U16 u16VStart50Hz;
    MS_U16 u16VStart48Hz;
    MS_U16 u16VBackPorch60Hz;
    MS_U16 u16VBackPorch50Hz;
    MS_U16 u16VBackPorch48Hz;

    /*Panel Option
    0: LCD
    1: PDP
    2: LCD_NO_FRC
    3: LCD_TCON
    */
    MS_U8    u8LCDorPDP;

    MS_U32 u32LimitD5d6d7; //thchen 20081216
    MS_U16 u16LimitOffset; //thchen 20081216
    MS_U8  u8LvdsSwingUp;
    MS_BOOL bTTL_10BIT;
    MS_BOOL bOD_DataPath;

//-------------------------------------------------------------------------------------------------
// FRC Control
//-------------------------------------------------------------------------------------------------
    MS_BOOL bFRC;
    MS_U16 u16MOD_SwingLevel;
    MS_U16 u16MOD_SwingCLK;
    MS_U16 u16output_cfg_10;
    MS_U16 u16output_cfg_11;
    MS_U16 u16output_cfg_12;
    MS_U8 u8output_cfg_13;
    MS_U8 u8PanelNoiseDith;
    MS_U8 u8lvdsSwapCh;
    MS_U8 u8FRC3DPanelType;

    MS_BOOL bdither6Bits;
    MS_BOOL blvdsShiftPair;
    MS_BOOL blvdsSwapPair;

// TGEN
    MS_U16  u16HSyncStart;
    MS_U16  u16HSyncEnd;
    MS_U16  u16VSyncStart;
    MS_U16  u16VSyncEnd;
    MS_U16 u16VTrigX;
    MS_U16 u16VTrigY;

// EPI
    MS_BOOL bepiLRSwap;
    MS_BOOL bepiLMirror;
    MS_BOOL bepiRMirror;

} MST_PANEL_INFO_t, *PMST_PANEL_INFO_t;

// for composer setting
typedef enum
{
    E_FRC_COMPOSER_SOURCE_MODE_VIP     = 0,  // m7332 always set VIP.
    E_FRC_COMPOSER_SOURCE_MODE_FSC     = 1,
    E_FRC_COMPOSER_SOURCE_MODE_FRC     = 2,
    E_FRC_COMPOSER_SOURCE_MODE_VIP_FB  = 3,
} E_FRC_COMPOSER_SOURCE_MODE;

typedef enum
{
    E_FRC_PIPE_DELAY_MODE_FIXED     = 0,
    E_FRC_PIPE_DELAY_MODE_USER      = 1,
    E_FRC_PIPE_DELAY_MODE_AUTO      = 2,
} E_FRC_PIPE_DELAY_MODE;

typedef enum
{
    E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_IP     = 0,  // with FRC case
    E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN   = 1,  // no FRC case
} E_FRC_TGEN_LOCK_SOURCE_MODE;

typedef enum
{
    E_FRC_STGEN_ODCLK_1      = 0,  // ODLCK
    E_FRC_STGEN_ODCLK_N      = 1,  // ODLCK div N
    E_FRC_STGEN_ODCLK_2      = 2,  // ODLCK/2
    E_FRC_STGEN_ODCLK_4      = 3,  // ODCLK/4
} E_FRC_STGEN_ODCLK;

typedef enum
{
    E_FSC_IDCLK_1      = 0,  // ODLCK
    E_FSC_IDCLK_2      = 1,  // ODLCK/2
    E_FSC_IDCLK_4      = 2,  // ODCLK/4
} E_FSC_IDCLK;

typedef enum
{
    E_FRC_FSC_SOURCE_MODE_MDE     = 0,
    E_FRC_FSC_SOURCE_MODE_FDE     = 1, //it actually means to "MDE", vip to fsc's de selection use MDE
} E_FRC_FSC_SOURCE_MODE;

typedef enum
{
    E_FRC_MLOAD_TRIG_MODE_FROM_OP1     = 0,  // no FRC case, menuload trig form stgen(FSC is enabled)
    E_FRC_MLOAD_TRIG_MODE_FROM_OP2     = 1,  // 1. with FRC case 2. no FRC and no FSC case, menuload trig form tgen
} E_FRC_MLOAD_TRIG_MODE;

typedef enum
{
    ///  MEMC level off
    MEMC_LEVEL_OFF,
    ///  MEMC level low
    MEMC_LEVEL_LOW,
    ///  MEMC level middle
    MEMC_LEVEL_MID,
    ///  MEMC level high
    MEMC_LEVEL_HIGH,
    ///  MEMC level bypass, its same as bypass 64 mode
    MEMC_LEVEL_BYPASS,
    ///  MEMC level bypass 64, one kind framerate converter of bypass.
    MEMC_LEVEL_BYPASS_64 = MEMC_LEVEL_BYPASS,
    ///  MEMC level bypass 55, one kind framerate convertr of bypass.
    MEMC_LEVEL_BYPASS_55,
    MEMC_LEVEL_USER = 0x0A,
}E_MEMC_LEVEL;

//if SUPPORT_HFR_PATH start
typedef enum
{
    E_FRC_COMPOSER_BEFORE_MEMC,
    E_FRC_COMPOSER_AFTER_MEMC,
    E_FRC_COMPOSER_MAX,
}EN_FRC_HFR_COMPOSER_TYPE;

typedef struct DLL_PACKED
{
    MS_U16 u16Hstart;
    MS_U16 u16Hend;
    MS_U16 u16Vstart;
    MS_U16 u16Vend;
}ST_FRC_WINDOW_INFO;

typedef struct DLL_PACKED
{
    EN_FRC_HFR_COMPOSER_TYPE eType;
    MS_BOOL bMainOnlyBypass;
}ST_FRC_HFR_COMPOSER_MAIN_ONLY_BYPASS;

typedef struct DLL_PACKED
{
    EN_FRC_HFR_COMPOSER_TYPE eType;
    MS_BOOL bMainSubSwap;
}ST_FRC_HFR_COMPOSER_MAIN_SUB_SWAP;

typedef struct DLL_PACKED
{
    EN_FRC_HFR_COMPOSER_TYPE eType;
    MS_BOOL bEnable;
    MS_BOOL bMenuload;
}ST_FRC_HFR_COMPOSER_PATH_ENABLE;

typedef struct DLL_PACKED
{
    EN_FRC_HFR_COMPOSER_TYPE eType;
    MS_BOOL bEnable;
}ST_FRC_HFR_COMPOSER_INSERT_MODE;

typedef struct DLL_PACKED
{
    EN_FRC_HFR_COMPOSER_TYPE eType;
    MS_BOOL bEnable;
}ST_FRC_HFR_COMPOSER_INSERT_USER_MODE;

typedef struct DLL_PACKED
{
    EN_FRC_HFR_COMPOSER_TYPE eType;
    ST_FRC_WINDOW_INFO stWinInfo;
}ST_FRC_HFR_COMPOSER_INSERT_WINDOW_DE;
//if SUPPORT_HFR_PATH end

typedef enum
{
    E_FRC_BW_CTRL_SOURCE_FRC = 0,
    E_FRC_BW_CTRL_SOURCE_HSE = 1,
}EN_FRC_BW_CTRL_SOURCE_TYPE;

#define PIP_DELAY_COUNTER_RESET    (BIT(3)) // BK68_50_L [3]
//-------------------------------------------------------------------------------------------------
//  Function and Variable
//-------------------------------------------------------------------------------------------------
#define MHal_FRC_IsRGB(args...) 0

#define MHal_FRC_TGEN_SWReset(args...)
#define MHal_FRC_TGEN_DoubleBuf(args...)
INTERFACE void MHal_FRC_TGEN_SetVTotal(void *pInstance, MS_U16 u16VTotal);
INTERFACE void MHal_FRC_TGEN_SetHTotal(void *pInstance, MS_U16 u16HTotal);

// TGEN VTT FRAME LOCK MODE
#if (TGEN_VTT_LOCK_MODE_VER > 0)
INTERFACE void MHal_FRC_TGEN_VTT_StoreCentralVTT(void *pInstance, MS_U16 u16CentralVTT);
INTERFACE void MHal_FRC_TGEN_VTT_LOCK_VTT_DIFF_LIMIT(void *pInstance, MS_BOOL bEn, MS_U16 u16DiffLimit);
INTERFACE void MHal_FRC_TGEN_VTT_CENTAL_VTT_CHANGE(void *pInstance, MS_BOOL bEn, MS_U8 u8FrameCount, MS_U8 u8threshold);
INTERFACE void MHal_FRC_TGEN_VTT_VAR_MODE_DATA_PATH(void *pInstance, MS_BOOL bEn);
INTERFACE void MHal_FRC_TGEN_VttLockModeEnable(void *pInstance, MS_BOOL bEn);
INTERFACE void MHal_FRC_TGEN_VTT_LOCK_PROTECT_ENABLE(void *pInstance, MS_BOOL bEn);
INTERFACE void MHal_FRC_TGEN_SetLockCentralVTotal(void* pInstance, MS_BOOL bEn, MS_U8 u8VframeCnt, MS_U8 u8threshold);
INTERFACE void MHal_FRC_TGEN_ClearState(void *pInstance);
INTERFACE void MHal_FRC_TGEN_SetVTotalRange(void* pInstance, MS_U16 u16VFreq);
INTERFACE void MHal_FRC_TGEN_SetIvsOvs(void* pInstance, MS_U16 u16FrcIn, MS_U16 u16FrcOut);
INTERFACE void MHal_FRC_TGEN_VTT_UD_SW_ENABLE(void *pInstance, MS_BOOL bEn);
INTERFACE void MHal_FRC_TGEN_CalculateVtt(void* pInstance);
INTERFACE MS_BOOL MHal_FRC_TGEN_GetFPLLDoneStatus(void* pInstance);
INTERFACE void MHal_FRC_TGEN_IVSShiftModeEnable(void *pInstance, MS_BOOL bEn);
#else
#define MHal_FRC_TGEN_VTT_StoreCentralVTT(args...)
#define MHal_FRC_TGEN_VTT_VAR_MODE_DATA_PATH(args...)
#define MHal_FRC_TGEN_VttLockModeEnable(args...)
#define MHal_FRC_TGEN_SetLockCentralVTotal(args...)
#define MHal_FRC_TGEN_ClearState(args...)
#define MHal_FRC_TGEN_SetVTotalRange(args...)
#define MHal_FRC_TGEN_SetIvsOvs(args...)
#define MHal_FRC_TGEN_VTT_UD_SW_ENABLE(args...)
#define MHal_FRC_TGEN_CalculateVtt(args...)
#define MHal_FRC_TGEN_GetFPLLDoneStatus(args...) FALSE
#define MHal_FRC_TGEN_VTT_LOCK_VTT_DIFF_LIMIT(args...)
#define MHal_FRC_TGEN_VTT_CENTAL_VTT_CHANGE(args...)
#define MHal_FRC_TGEN_VTT_LOCK_PROTECT_ENABLE(args...)
#define MHal_FRC_TGEN_IVSShiftModeEnable(args...)
#endif

#define MHal_FRC_TGEN_SetVTrigY(args...)
#define MHal_FRC_TGEN_SetVTrigX(args...)
INTERFACE void MHal_FRC_TGEN_SetVSyncStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End, MS_U16 u16VTT);
INTERFACE void MHal_FRC_TGEN_SetHSyncStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End);
INTERFACE void MHal_FRC_TGEN_SetFdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End);
INTERFACE void MHal_FRC_TGEN_SetFdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End);
INTERFACE void MHal_FRC_TGEN_SetMdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End);
INTERFACE void MHal_FRC_TGEN_SetMdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End);
INTERFACE void MHal_FRC_TGEN_SetSubMdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End);
INTERFACE void MHal_FRC_TGEN_SetSubMdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End);

#define MHal_FRC_TGEN_FpllRefPointY(args...)
#define MHal_FRC_TGEN_1Clk2PixOut(args...)
#define MHal_FRC_TGEN_SetSyncHcnt(args...)
#define MHal_FRC_TGEN_SetClrSyncAhead(args...)

INTERFACE void MHal_FRC_TGEN_Init(void *pInstance);
INTERFACE void MHal_FRC_TGEN_Enable_LockMode(void *pInstance, MS_BOOL bEn);
INTERFACE void MHal_FRC_TGEN_Enable_Source_Select_Mode(void *pInstance, MS_BOOL bEn);
//INTERFACE void MHal_FRC_TGEN_Set_Lock_Source(void *pInstance, E_FRC_TGEN_LOCK_SOURCE_MODE eMode);
INTERFACE void MHal_FRC_TGEN_Enable_Lock_Source(void *pInstance, MS_BOOL bEn, E_FRC_TGEN_LOCK_SOURCE_MODE eMode, MS_BOOL bMenuload);

INTERFACE void MHal_FRC_SetYTrig(void *pInstance, MS_U16 u16Trig1, MS_U16 u16Trig2);

#define MHal_FRC_Enable_MiuMask(args...)
#define MHal_FRC_Disable_MiuMask(args...)
#define MHal_FRC_set_miusel(args...)

#define MHal_FRC_IPM_SoftwareReset(args...)
#define MHal_FRC_IPM_RWEn(args...)
#define MHal_FRC_IPM_RW_CEN_Select(args...)
#define MHal_FRC_IPM_SetYuv10Bit(args...)
#define MHal_FRC_IPM_SetMr(args...)
#define MHal_FRC_IPM_SetMemoryMode(args...)
#define MHal_FRC_IPM_YC444To422Control(args...)
#define MHal_FRC_IPM_SetFrameBufferNum(args...)
#define MHal_FRC_IPM_CeLineCountEn(args...)
#define MHal_FRC_IPM_SetBaseAddr(args...)
#define MHal_FRC_IPM_R_SetBaseAddr(args...)
#define MHal_FRC_IPM_SetIp2Mc(args...)
#define MHal_FRC_IPM_SetYCoutLinePitch(args...)
#define MHal_FRC_IPM_SetReadFetchNumber(args...)
#define MHal_FRC_IPM_SetWriteFetchNumber(args...)
#define MHal_FRC_IPM_SetRfifoThr(args...)
#define MHal_FRC_IPM_SetWfifoThr(args...)
#define MHal_FRC_IPM_SetReadLength(args...)
#define MHal_FRC_IPM_SetWriteLength(args...)
#define MHal_FRC_IPM_SetHTotalPixellimit(args...)
#define MHal_FRC_IPM_SetVTotalPixellimit(args...)
#define MHal_FRC_IPM_SetRmaskNum(args...)
#define MHal_FRC_IPM_SetWmaskNum(args...)
#define MHal_FRC_IPM_SetMirrorMode(args...)
#define MHal_FRC_IPM_PacketInitCnt(args...)
#define MHal_FRC_IPM_SetLvdsInputMode(args...)
#define MHal_FRC_IPM_SetOsdWinIdx(args...)
#define MHal_FRC_IPM_SetVPulseLineRst(args...)
#define MHal_FRC_IPM_SetVPulseLoc(args...)
#define MHal_FRC_IPM_SetLockIntCtrl(args...)
#define MHal_FRC_IPM_SetBlankBoundary(args...)
#define MHal_FRC_IPM_GetHTotal(args...) 0
#define MHal_FRC_IPM_GetVTotal(args...) 0
#define MHal_FRC_IPM_GetHde(args...) 0
#define MHal_FRC_IPM_GetVde(args...) 0
#define MHal_FRC_IPM_Csc(args...)
#define MHal_FRC_IPM_CscDither(args...)
#define MHal_FRC_IPM_CscRound(args...)
#define MHal_FRC_IPM_CscSaturation(args...)
#define MHal_FRC_IPM_CheckBoardEn(args...)
#define MHal_FRC_IPM_SetIpCtrl(args...)
#define MHal_FRC_IPM_SetHRefLock(args...)
#define MHal_FRC_IPM_GetHdeCount(args...) 0
#define MHal_FRC_IPM_TestPattern(args...)
#define MHal_FRC_IPM_SetHTotal(args...)
#define MHal_FRC_IPM_SetVTotal(args...)
#define MHal_FRC_IPM_HActive(args...)
#define MHal_FRC_IPM_VActive(args...)
#define MHal_FRC_IPM_GetYcoutLinePitch(args...) 0
#define MHal_FRC_IPM_GetWriteFetchNum(args...) 0
#define MHal_FRC_IPM_GetReadFetchNum(args...) 0
#define MHal_FRC_IPM_GetLineLimit(args...) 0
#define MHal_FRC_IPM_SetPacketCount(args...)
#define MHal_FRC_IPM_GetFrameYcout(args...) 0
#define MHal_FRC_IPM_3DFlag_In_SWMode_En(args...)
#define MHal_FRC_IPM_3DFlag_In_SWMode_SetIdx(args...)
#define MHal_FRC_IPM_3DFlag_In_HWMode_SrcSel(args...)
#define MHal_FRC_IPM_GetIPVfreqX10(args...) 0



#define MHal_FRC_OPM_SetFbLineOffset_Data(args...)
#define MHal_FRC_OPM_SetFbLineOffset_Me3(args...)
#define MHal_FRC_OPM_SetSrcPixNum(args...)
#define MHal_FRC_OPM_SetSrcLineNum(args...)
#define MHal_FRC_OPM_CeLineCountEn(args...)
#define MHal_FRC_OPM_SetLbiSrcPixelNum_Left(args...)
#define MHal_FRC_OPM_SetLbiReadPixelNum_Left(args...)
#define MHal_FRC_OPM_SetLbiSkipEn(args...)
#define MHal_FRC_OPM_SetLbiSkipNum_Left(args...)
#define MHal_FRC_OPM_SetLbiSrcPixelNum_Right(args...)
#define MHal_FRC_OPM_SetLbiReadPixelNum_Right(args...)
#define MHal_FRC_OPM_SetLbiSkipEn3D(args...)
#define MHal_FRC_OPM_SetLbiSkipNum_Right(args...)
#define MHal_FRC_OPM_FuncEn(args...)
#define MHal_FRC_OPM_3dFuncEn(args...)
#define MHal_FRC_OPM_SetBaseOffset_Data0(args...)
#define MHal_FRC_OPM_SetBaseOffset_Data1(args...)
#define MHal_FRC_OPM_SetBaseOffset_Me0(args...)
#define MHal_FRC_OPM_SetBaseOffset_Me1(args...)
#define MHal_FRC_OPM_SetBaseOffset_Me3(args...)
#define MHal_FRC_OPM_SetBaseOffset_Da0_L(args...)
#define MHal_FRC_OPM_SetBaseOffset_Da1_L(args...)
#define MHal_FRC_OPM_SetBaseOffset_Me0_L(args...)
#define MHal_FRC_OPM_SetBaseOffset_Me1_L(args...)
#define MHal_FRC_OPM_SetBaseOffset_Me3_L(args...)
#define MHal_FRC_OPM_SetBaseOffset_Mr1_L(args...)
#define MHal_FRC_OPM_SetBaseOffset_Mr1(args...)
#define MHal_FRC_OPM_SetDebugMask(args...)
#define MHal_FRC_OPM_SwReset(args...)
#define MHal_FRC_OPM_enableBaseAdrMr(args...)
#define MHal_FRC_OPM_SetBaseAddr(args...)
#define MHal_FRC_OPM_R_SetBaseAddr(args...)
#define MHal_FRC_OPM_SetMlbOutRstCycle(args...)
#define MHal_FRC_OPM_SetFifoTrigThr(args...)
#define MHal_FRC_OPM_SetFifoMaxReadReq(args...)
#define MHal_FRC_OPM_SetGatingClk(args...)
#define MHal_FRC_SetMemMode(args...)

#define MHal_FRC_OP2_ColorMatrixEn(args...)
#define MHal_FRC_OP2_CscDitherEn(args...)
#define MHal_FRC_OP2_DataPathEn(args...)
#define MHal_FRC_OP2_DebugFuncEn(args...)
#define MHal_FRC_OP2_SetGain_R(args...)
#define MHal_FRC_OP2_SetGain_G(args...)
#define MHal_FRC_OP2_SetGain_B(args...)
#define MHal_FRC_OP2_SetOffset_R(args...)
#define MHal_FRC_OP2_SetOffset_G(args...)
#define MHal_FRC_OP2_SetOffset_B(args...)
#define MHal_FRC_OP2_SetDither(args...)
#define MHal_FRC_OP2_PAFRC_FuncEn(args...)
#define MHal_FRC_OP2_PAFRC_FuncEn2(args...)
#define MHal_FRC_OP2_PAFRC_FuncEn3(args...)
#define MHal_FRC_OP2_PAFRC_Set2x2BlockRotDir(args...)
#define MHal_FRC_OP2_PAFRC_TopBoxFrSeq(args...)
#define MHal_FRC_OP2_PAFRC_TopBoxFrC2Seq(args...)
#define MHal_FRC_OP2_PAFRC_SetBoxRotDir(args...)
#define MHal_FRC_OP2_PAFRC_Set8x8BoxRotDir(args...)
#define MHal_FRC_OP2_PAFRC_SetBlockEntities(args...)
#define MHal_FRC_OP2_PAFRC_PolarityCtrl(args...)
#define MHal_FRC_OP2_PAFRC_SetBoxLsbValue(args...)

#define MHal_FRC_SCTOP_SCMI_Bypass_Enable(args...)
#define MHal_FRC_SCTOP_FRC_Bypass_Enable(args...)

#define MHal_FRC_SNR_SetPixelHorixontalNum(args...)
#define MHal_FRC_SNR_SetLineVerticalNum(args...)

#define MHal_FRC_SCP_HSU1_HSP(args...)
#define MHal_FRC_SCP_HSU1_Init_Position(args...)
#define MHal_FRC_SCP_HSU1_Scaling_Mode(args...)
#define MHal_FRC_SCP_HSU1_444to422_Mode(args...)
#define MHal_FRC_SCP_HSU1_VSU_Scaling_Mode(args...)
#define MHal_FRC_SCP_HSU1_VSU_Scaling_coef(args...)
#define MHal_FRC_SCP_HSU2_HSP(args...)
#define MHal_FRC_SCP_HSU2_Init_Position(args...)
#define MHal_FRC_SCP_HSU2_Scaling_Mode(args...)

#define MHal_FRC_OD_SetBaseAddr(args...)
#define MHal_FRC_LD_SetBaseAddr(args...)
#define MHal_FRC_LD_Edge2D_SetBaseAddr(args...)
#define MHal_FRC_ME1_SetBaseAddr(args...)
#define MHal_FRC_ME2_SetBaseAddr(args...)
#define MHal_FRC_2D3D_Render_SetBaseAddr(args...)
#define MHal_FRC_2D3D_Render_Detection_SetBaseAddr(args...)
#define MHal_FRC_Halo_SetBaseAddr(args...)
#define MHal_FRC_OverDriverSwitch(args...)
#define MHal_FRC_OD_Init(args...)

// for FRC init
INTERFACE void MHal_FRC_Init(void *pInstance, PMST_PANEL_INFO_t pPanelInfo, PFRC_INFO_t pFRCInfo);
#define MHal_FRC_ByPass_Enable(args...)

#define MHal_FRC_LoadTabelbySrcType(args...)
#define MHal_FRC_Set_3D_QMap(args...)


//FRC R2 Mail Box Control
#define MHal_XC_SendCmdToFRC(args...) FALSE
#define MHal_XC_GetMsgFromFRC(args...) FALSE
#define MHal_XC_GetFrcSwVersion(args...) E_APIXC_RET_FAIL_FUN_NOT_SUPPORT
#define Hal_XC_FRC_R2_Get_SwVersion(args...)
#define Hal_XC_FRC_R2_Get_CmdVersion(args...)
#define Hal_XC_FRC_R2_Init(args...) FALSE
#define Hal_XC_FRC_R2_Set_Timing(args...) FALSE
#define Hal_XC_FRC_R2_Set_InputFrameSize(args...) FALSE
#define Hal_XC_FRC_R2_Set_OutputFrameSize(args...) FALSE
#define Hal_XC_FRC_R2_Set_FPLL_Lockdone(args...) FALSE
#define Hal_XC_FRC_R2_Enable_MEMC(args...) FALSE
#define Hal_XC_FRC_R2_Set_Input3DFormat(args...) FALSE
#define Hal_XC_FRC_R2_Set_32LineModeEnble(args...) FALSE


#define Hal_XC_FRC_R2_Set_MfcMode(args...)
#define Hal_XC_FRC_R2_Set_MfcDemoMode(args...)
#define Hal_XC_FRC_R2_Set_LocalDimmingMode(args...)
#define Hal_XC_FRC_R2_Set_2DTo3DMode(args...) 0

//FRC auto download
#define Hal_FRC_ADLG_set_base_addr(args...)
#define Hal_FRC_ADLG_set_depth(args...)
#define Hal_FRC_ADLG_set_dma(args...)
#define Hal_FRC_ADLG_set_on_off(args...)

#define Hal_FRC_get_table_idx(args...) FRC_NOTSUPPORT_MODE

#define MHal_XC_OC_set_HSyncStartEnd(args...)
#define MHal_XC_OC_set_VSyncStartEnd(args...)
#define MHal_XC_OC_set_HFdeStartEnd(args...)
#define MHal_XC_OC_set_VFdeStartEnd(args...)
#define MHal_XC_OC_set_HTotal(args...)
#define MHal_XC_OC_set_VTotal(args...)

#define MHal_FRC_IPM_SetOffset(args...)
#define MHal_FRC_IPM_SetFetchNum(args...)
#define MHal_FRC_OPM_SetOffset(args...)
#define MHal_FRC_OPM_SetFetchNum(args...)
#define MHal_FRC_HSU_SetScalingSize(args...)
#define MHal_FRC_VSU_SetScalingSize(args...)
#define MHal_FRC_CSC_SelectPath(args...)

#define MHal_FRC_interrupt_mask(args...)
#define MHal_FRC_Mute(args...)
#define MHal_FRC_3DLR_Select(args...)

INTERFACE void MHal_FRC_Composer_User_Mode_Enable(void *pInstance, MS_BOOL bEnable);
INTERFACE void MHal_FRC_Set_Composer_User_Mode(void *pInstance, E_FRC_COMPOSER_SOURCE_MODE eMode, MS_BOOL bMenuload);

#define MHal_FRC_Set_Pipe_Delay_Mode(args...)
#define MHal_FRC_Set_Pipe_Delay_Value(args...)
#define MHal_FRC_Set_Pipe_Delay_Reset(args...)

#define MHal_FRC_Set_STGEN_ODCLK(args...)
INTERFACE void MHal_FRC_Set_FSC_DE_Selection(void *pInstance, E_FRC_FSC_SOURCE_MODE eMode);
#define MHal_FRC_IsFHDToFSC(args...) FALSE
INTERFACE MS_BOOL MHal_FRC_IsSupportFRC_byEfuse(void *pInstance);
INTERFACE MS_BOOL MHal_FRC_Check_Condition(void *pInstance, ST_XC_FRCFSCCTRLPOLICY *pstXCFrcFscCtrlPolicy);
#define MHal_FRC_AdjustGOPPosition(args...)
#define MHal_FRC_GetGOPOffset(args...)
#define MHal_FRC_IsEnableFRC3D(args...) FALSE
INTERFACE void MHal_FRC_Set_Mload_Trig_Mode(void *pInstance, E_FRC_MLOAD_TRIG_MODE eMode);
#define MHal_FRC_Set_FreezeImg(args...)

//----------------- Maserati new API, Maxim no need   ---------------------//
#define MHal_FRC_Set_FO_Path(args...)
#define MHal_FRC_Set_FO_VOP_H_Size(args...)
#define MHal_FRC_Set_FO_SPTP_Setting(args...)
#define MHal_FRC_Set_FO_2Line_Setting(args...)
#define MHal_FRC_Set_FO_OSDDS_Setting(args...)

#define MHal_FRC_FO_TGEN_SetVTotal(args...)
#define MHal_FRC_FO_TGEN_SetHTotal(args...)
#define MHal_FRC_FO_TGEN_SetVTrigY(args...)
#define MHal_FRC_FO_TGEN_SetVTrigX(args...)
#define MHal_FRC_FO_TGEN_SetVSyncStartEndY(args...)
#define MHal_FRC_FO_TGEN_SetHSyncStartEndX(args...)
#define MHal_FRC_FO_TGEN_SetFdeStartEndY(args...)
#define MHal_FRC_FO_TGEN_SetFdeStartEndX(args...)
#define MHal_FRC_FO_TGEN_SetMdeStartEndY(args...)
#define MHal_FRC_FO_TGEN_SetMdeStartEndX(args...)
#define MHal_FRC_FO_TGEN_SetMdeStartEndX_L(args...)
#define MHal_FRC_FO_TGEN_SetMdeStartEndX_R(args...)

#define MHal_FRC_Set_SC2_PLL_Vsync_Ref(args...)
//------------------------------------------------ --------------------//

INTERFACE void MHal_SWDS_AddTGENMdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End, SCALER_WIN eWindow);
INTERFACE void MHal_SWDS_AddTGENMdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End, SCALER_WIN eWindow);
INTERFACE MS_BOOL Hal_XC_Get_Stgen_Lock_Ip_status(void *pInstance);
#define MHal_FRC_Set_TimingStable(args...)
#define MHal_XC_MEMC_NeedPhaseLock(args...)  FALSE

//This chip has no FSC
#define MHal_FRC_GetCapsFSC(args...) FALSE
#define MHal_FRC_Set_Insert_Crop(args...)

//HFR
#define MHal_FRC_HFR_Set_ComposerSelection(args...)
#define MHal_FRC_HFR_Set_Hsv_SrcSelection(args...)
#define MHal_FRC_HFR_Composer_Set_MainOnlyBypass(args...)
#define MHal_FRC_HFR_Composer_Set_MainSubSwap(args...)
#define MHal_FRC_HFR_Composer_Enable_Main(args...)
#define MHal_FRC_HFR_Composer_Enable_Sub(args...)
#define MHal_FRC_HFR_Composer_Enable_InsertMode(args...)
#define MHal_FRC_HFR_Composer_Set_InsertUserMode(args...)
#define MHal_FRC_HFR_Composer_Set_InsertMainMde(args...)
#define MHal_FRC_HFR_Composer_Set_InsertMainFde(args...)
#define MHal_FRC_HFR_Composer_Set_InsertSubDe(args...)
#if (XC_SUPPORT_IOMMU == TRUE)
#define MHal_FRC_GetMMAAddr(args...) XC_INVALID_MEM
#define MHal_FRC_ReleaseMMA(args...) FALSE
#define MHal_FRC_SetBaseAddr(args...) FALSE
#define MHal_FRC_AuthorizeMMA(args...) FALSE
#define MHal_FRC_UnauthorizeMMA(args...) FALSE
#define MHal_FRC_GetFrcLMemorySize(args...) 0
#define MHal_FRC_GetFrcRMemorySize(args...) 0
#define MHal_FRC_GetFrcPQMemorySize(args...) 0
#endif
#define MHal_FRC_GetRwDiff(args...) (0)
#define MHal_FRC_SetMirrorControl(args...)
#define MHal_FRC_IsSupportFRC_ME4XMode(args...) FALSE
#define MHal_FRC_EnableBWCtrl(args...)
#define MHal_FRC_Reset(args...)
#define MHal_FRC_DisableFRCOPMWrite(args...) FALSE
#define MHal_FRC_ControlMemcLevelForHSE(args...)
#define MHal_FRC_IsByPass_MEMC(args...) (FALSE)
#undef INTERFACE
#endif /* MHAL_FRC_H */

