/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef _MTK_TV_LPLL_TBL_H_
#define _MTK_TV_LPLL_TBL_H_

#include "coda/lpll.h"

#define LPLL_REG_NUM         (44)
#define PNL_NUM_VER1         (35)

typedef enum
{
	//======version0100 start======
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz,                           // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz,                           // 1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz,                           // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz,                           // 3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz,                           // 4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz,                           // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz,                        // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz,                        // 7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz,                        // 8
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz,                        // 9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz,                        // 10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz,                        // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_400to600MHz,          // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to400MHz,          // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to300MHz,          // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_400to600MHz,          // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to400MHz,          // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to300MHz,          // 17
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz,          // 18
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz,          // 19
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to300MHz,          // 20
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_400to600MHz,          // 21
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to400MHz,          // 22
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to300MHz,          // 23
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to600MHz,          // 24
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to300MHz,          // 25
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz,          // 26
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz,          // 27
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz,          // 28
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz,          // 29
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to300MHz,          // 30
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz,          // 31
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to300MHz,          // 32
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz,          // 33
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to300MHz,          // 34
	//======version0100 end======

	//======version0200 start======
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2,                           // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2,                           // 1
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2,                           // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2,                           // 3
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2,                        // 4
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2,                        // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2,                        // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2,                        // 7
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2,          // 8
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2,          // 9
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2,          // 10
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2,          // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2,          // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2,          // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2,          // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2,          // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2,          // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2,          // 17
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2,          // 18
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2,              // 19
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2,// 20
	//======version0200 end======

	//======version0300 start=====
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER0300,                          // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER0300,                          // 1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER0300,                          // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER0300,                          // 3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER0300,                          // 4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER0300,                          // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER0300,                       // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER0300,                       // 7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER0300,                       // 8
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER0300,                       // 9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER0300,                       // 10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER0300,                       // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER0300,         // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER0300,         // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER0300,   // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER0300,   // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER0300,   // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER0300,   // 17
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER0300,               // 18
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER0300,// 19
	E_PNL_SUPPORTED_LPLL_CEDS_TEST_0to600MHz_VER0300,                           // 20
	//======version0300 end=====

	//======version0203 start=====
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER0203,                             // 0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER0203,                             // 1
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER0203,                             // 2
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER0203,                             // 3
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER0203,                          // 4
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER0203,                          // 5
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER0203,                          // 6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER0203,                          // 7
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER0203,            // 8
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER0203,            // 9
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER0203,            // 10
	E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER0203,            // 11
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER0203,            // 12
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER0203,            // 13
	E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER0203,            // 14
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER0203,            // 15
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER0203,            // 16
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER0203,            // 17
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER0203,            // 18
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER0203,                // 19
	E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER0203,  // 20
	//======version0203 end=====

	//======version0400 start====
	E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004,		                           // 0
	E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004,		                           // 1
	E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004, 		                           // 2
	E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004,			                           // 3
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004,		                       // 4
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004,		                       // 5
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004,		                       // 6
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004,		                       // 7
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004,		                       // 8
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004,		                       // 9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004,		                   // 10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004,		                   // 11
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004,		                   // 12
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004,		                   // 13
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004,		                   // 14
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004,		                   // 15
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004,		       // 16
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004,		       // 17
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004,		  // 18
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004,		  // 19
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004,		  // 20
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004,		  // 21
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004,		  // 22
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004,		  // 23
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004,		  // 24
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004,		  // 25
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004,		  // 26
	E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004,		  // 27
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004,		  // 28
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004,		  // 29
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004,		  // 30
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004,		  // 31
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004,		   // 32
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004,		   // 33
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004,		   // 34
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004,		   // 35
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004,		   // 36
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004,		   // 37
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004,		   // 38
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004,		   // 39
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004,		   // 40
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004,		   // 41
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004,		   // 42
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004, 		 // 43
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004, 		 // 44
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004, 		 // 45
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004, 		 // 46
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004, 		 // 47
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004, 		 // 48
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004,		  // 49
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004,		  // 50
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004,		   // 51
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004,		   // 52
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004,		   // 53
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004,		   // 54
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004,			// 55
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004,			// 56
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004,			// 57
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004,			// 58
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004,			// 59
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004,			// 60
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004,			// 61
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004,			// 62
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004,			// 63
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004,			// 64
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004,			// 65
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004,			// 66
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004,			// 67
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004,			// 68
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004,		  // 69
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004,		  // 70
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004,		  // 71
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004,		  // 72
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004,		  // 73
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004,		  // 74
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004,		   // 75
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004,		   // 76
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004,			// 77
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004,			// 78
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004,			// 79
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004,			// 80
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004, 		 // 81
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004, 		 // 82
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004, 		 // 83
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004,		   // 84
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004,		   // 85
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004,		   // 86
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004,		   // 87
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004,		   // 88
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004,		   // 89
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004,			// 90
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004,			// 91
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004,			// 92
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004,			// 93
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004,			// 94
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004,			// 95
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004,			// 96
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004, 		 // 97
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004, 		 // 98
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004, 		 // 99
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004, 		 // 100
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004, 		 // 101
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004, 		 // 102
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004, 		 // 103
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004, 		 // 104
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004,		  // 105
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004,		  // 106
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004,		  // 107
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004,		  // 108
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004,		  // 109
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004,		  // 110
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004,		   // 111
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004,		   // 112
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004,		   // 113
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004,		   // 114
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004,		   // 115
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004,		   // 116
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004,		   // 117
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004,		   // 118
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004,		   // 119
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004,		   // 120
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004,		   // 121
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004,		   // 122
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004,		   // 123
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004,			// 124
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004,			// 125
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004,			// 126
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004,			// 127
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004,			// 128
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004,			// 129
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004,			// 130
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004,			// 131
	E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004,			// 132
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004, 		 // 133
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004, 		 // 134
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004, 		 // 135
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004, 		 // 136
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004, 		 //137
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004,			//138
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004,			//139
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004,			//140
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004,			//141
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004,			//142
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004,			//143
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004,			//144
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004, 		 //145
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004, 		 //146
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004, 		 //147
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004, 		 //148
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004, 		 //149
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004, 		 //150
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004, 		 //151
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004,		  //152
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004,		  //153
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004,		  //154
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004,		  //155
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004,		  //156
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004,		   //157
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004,		   //158
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004,		   //159
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004,		   //160
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004,		   //161
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004,		   //162
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004,		   //163
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004,		   //164
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004,		  //165
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004,		  //166
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004,		  //167
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004,		  //168
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004,		  //169
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004,		  //170
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004,		  //171
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004,		  //172
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004,		  //173
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004,		  //174
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004,		  //175
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004,		  //176
	//======version0400 end====
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005,          //0
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005,          //1
	E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005,          //2

	E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005,          //3
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005,          //4
	E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005,          //5

	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005,          //6
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005,          //7
	E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005,          //8

	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005,          //9
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005,          //10
	E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005,          //11

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_360to600MHz_VER005,          //12
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to360MHz_VER005,          //13
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to300MHz_VER005,          //14

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_450to600MHz_VER005,          //15
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to450MHz_VER005,          //16
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to300MHz_VER005,          //17

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to600MHz_VER005,          //18
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to300MHz_VER005,          //19

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_360to600MHz_VER005,          //20
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to360MHz_VER005,          //21
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to300MHz_VER005,          //22

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_450to600MHz_VER005,          //23
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to450MHz_VER005,          //24
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to300MHz_VER005,          //25

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to720MHz_VER005,          //26
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to360MHz_VER005,          //27

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_480to720MHz_VER005,          //28
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to480MHz_VER005,          //29
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to360MHz_VER005,          //30

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to600MHz_VER005,          //31
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to300MHz_VER005,          //32

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to600MHz_VER005,          //33
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to300MHz_VER005,          //34

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to600MHz_VER005,          //35
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to300MHz_VER005,          //36

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_400to600MHz_VER005,          //37
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to400MHz_VER005,          //38
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to300MHz_VER005,          //39

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_360to600MHz_VER005,          //40
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to360MHz_VER005,          //41
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to300MHz_VER005,          //42

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_450to600MHz_VER005,          //43
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to450MHz_VER005,          //44
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to300MHz_VER005,          //45

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to600MHz_VER005,          //46
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to300MHz_VER005,          //47

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_360to600MHz_VER005,          //48
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to360MHz_VER005,          //49
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to300MHz_VER005,          //50

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_450to600MHz_VER005,          //51
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to450MHz_VER005,          //52
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to300MHz_VER005,          //53

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to720MHz_VER005,          //54
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to360MHz_VER005,          //55

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_480to720MHz_VER005,          //56
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to480MHz_VER005,          //57
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to360MHz_VER005,          //58

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to600MHz_VER005,          //59
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to300MHz_VER005,          //60

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to600MHz_VER005,          //61
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to300MHz_VER005,          //62

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to600MHz_VER005,          //63
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to300MHz_VER005,          //64

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_400to600MHz_VER005,          //65
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to400MHz_VER005,          //66
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to300MHz_VER005,          //67

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_400to600MHz_VER005,          //68
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to400MHz_VER005,          //69
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to300MHz_VER005,          //70

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_450to600MHz_VER005,          //71
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to450MHz_VER005,          //72
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to300MHz_VER005,          //73

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to600MHz_VER005,          //74
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to300MHz_VER005,          //75

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_450to600MHz_VER005,          //76
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to450MHz_VER005,          //77
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to300MHz_VER005,          //78

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_400to600MHz_VER005,          //79
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to400MHz_VER005,          //80
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to300MHz_VER005,          //81

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to720MHz_VER005,          //82
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to360MHz_VER005,          //83

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to600MHz_VER005,          //84
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to300MHz_VER005,          //85

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_540to720MHz_VER005,          //86
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to540MHz_VER005,          //87
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to360MHz_VER005,          //88

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to600MHz_VER005,          //89
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to300MHz_VER005,          //90

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to600MHz_VER005,          //91
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to300MHz_VER005,          //92

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to600MHz_VER005,          //93
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to300MHz_VER005,          //94

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_400to600MHz_VER005,          //95
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to400MHz_VER005,          //96
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to300MHz_VER005,          //97

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_400to600MHz_VER005,          //98
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to400MHz_VER005,          //99
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to300MHz_VER005,          //100

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_450to600MHz_VER005,          //101
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to450MHz_VER005,          //102
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to300MHz_VER005,          //103

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to600MHz_VER005,          //104
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to300MHz_VER005,          //105

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_400to600MHz_VER005,          //106
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to400MHz_VER005,          //107
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to300MHz_VER005,          //108

	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to720MHz_VER005,          //109
	E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to360MHz_VER005,          //110

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to600MHz_VER005,          //111
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to300MHz_VER005,          //112

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to600MHz_VER005,          //113
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to300MHz_VER005,          //114

	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_400to600MHz_VER005,          //115
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to400MHz_VER005,          //116
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to300MHz_VER005,          //117

	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to600MHz_VER005,          //118
	E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to300MHz_VER005,          //119

	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_450to600MHz_VER005,          //120
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to450MHz_VER005,          //121
	E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to300MHz_VER005,          //122

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to600MHz_VER005,          //123
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to300MHz_VER005,          //124

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_400to600MHz_VER005,          //125
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to400MHz_VER005,          //126
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to300MHz_VER005,          //127

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to720MHz_VER005,          //128
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to360MHz_VER005,          //129

	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to600MHz_VER005,          //130
	E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to300MHz_VER005,          //131

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to600MHz_VER005,          //132
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to300MHz_VER005,          //133

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to600MHz_VER005,          //134
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to300MHz_VER005,          //135

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to720MHz_VER005,          //136
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to360MHz_VER005,          //137

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to600MHz_VER005,          //138
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to300MHz_VER005,          //139

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to600MHz_VER005,          //140
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to300MHz_VER005,          //141

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_450to600MHz_VER005,          //142
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to450MHz_VER005,          //143
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to300MHz_VER005,          //144

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to600MHz_VER005,          //145
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to300MHz_VER005,          //146

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to600MHz_VER005,          //147
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to300MHz_VER005,          //148

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to720MHz_VER005,          //149
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to360MHz_VER005,          //150

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_360to600MHz_VER005,          //151
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to360MHz_VER005,          //152
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to300MHz_VER005,          //153

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to600MHz_VER005,          //154
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to300MHz_VER005,          //155

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to600MHz_VER005,          //156
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to300MHz_VER005,          //157

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to600MHz_VER005,          //158
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to300MHz_VER005,          //159

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to600MHz_VER005,          //160
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to300MHz_VER005,          //161

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to600MHz_VER005,          //162
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to300MHz_VER005,          //163

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to600MHz_VER005,          //164
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to300MHz_VER005,          //165

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to720MHz_VER005,          //166
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to360MHz_VER005,          //167

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_450to600MHz_VER005,          //168
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to450MHz_VER005,          //169
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to300MHz_VER005,          //170

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_450to600MHz_VER005,          //171
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to450MHz_VER005,          //172
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to300MHz_VER005,          //173

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_450to600MHz_VER005,          //174
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to450MHz_VER005,          //175
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to300MHz_VER005,          //176

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_450to600MHz_VER005,          //177
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to450MHz_VER005,          //178
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to300MHz_VER005,          //179

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_480to720MHz_VER005,          //180
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to480MHz_VER005,          //181
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to360MHz_VER005,          //182

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to405MHz_VER005,          //183
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to202MHz_VER005,          //184

	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to700MHz_VER005,          //185
	E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER005,          //186

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER005,          //187
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER005,          //188

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_270to360MHz_VER005,          //189
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to270MHz_VER005,          //190
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER005,          //191

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to360MHz_VER005,          //192
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to180MHz_VER005,          //193

	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER005,          //194
	E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER005,          //195

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_270to360MHz_VER005,          //196
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to270MHz_VER005,          //197
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER005,          //198

	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to360MHz_VER005,          //199
	E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to180MHz_VER005,          //200

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER005,          //201
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER005,          //202

	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_270to360MHz_VER005,          //203
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to270MHz_VER005,          //204
	E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to180MHz_VER005,          //205

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to360MHz_VER005,          //206
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER005,          //207

	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to360MHz_VER005,          //208
	E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to180MHz_VER005,          //209

	E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to360MHz_VER005,          //210
	E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to180MHz_VER005,          //211

	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_270to360MHz_VER005,          //212
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to270MHz_VER005,          //213
	E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER005,          //214

	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER005,          //215
	E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER005,          //216

	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_270to360MHz_VER005,          //217
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to270MHz_VER005,          //218
	E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER005,          //219

	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER005,          //220
	E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER005,          //221

	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_270to360MHz_VER005,          //222
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to270MHz_VER005,          //223
	E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER005,          //224

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to360MHz_VER005,          //225
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to180MHz_VER005,          //226

	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_240to360MHz_VER005,          //227
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to240MHz_VER005,          //228
	E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to180MHz_VER005,          //229

	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to405MHz_VER005,          //230
	E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to202MHz_VER005,          //231

	//======version5 end======
	E_PNL_SUPPORTED_LPLL_MAX,
} E_PNL_SUPPORTED_LPLL_TYPE;

typedef struct
{
    uint32_t address;
    uint32_t value;
    uint32_t mask;
}TBLStruct,*pTBLStruct;

TBLStruct LPLLSettingTBL[PNL_NUM_VER1][LPLL_REG_NUM]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz    NO.0
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0040,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz    NO.1
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0001,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz    NO.2
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0001,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz    NO.3
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0040,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz    NO.4
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0001,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz    NO.5
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0001,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz    NO.6
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0040,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz    NO.7
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz    NO.8
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz    NO.9
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0040,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz    NO.10
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz    NO.11
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0007,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_400to600MHz    NO.12
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0040,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to400MHz    NO.13
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000E,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0001,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to300MHz    NO.14
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000E,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0001,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_400to600MHz    NO.15
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0040,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to400MHz    NO.16
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to300MHz    NO.17
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz    NO.18
      //Address,Value,Mask
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0041,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz    NO.19
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0041,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to300MHz    NO.20
      //Address,Value,Mask
        {REG_000C_LPLL,0x0002,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000F,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0000,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0041,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_400to600MHz    NO.21
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0040,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to400MHz    NO.22
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0002,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to300MHz    NO.23
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0002,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to600MHz    NO.24
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to300MHz    NO.25
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz    NO.26
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0041,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz    NO.27
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0001,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x000A,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0000,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0041,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz    NO.28
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0040,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz    NO.29
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0002,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to300MHz    NO.30
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0002,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000F,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz    NO.31
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to300MHz    NO.32
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0001,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x000A,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0000,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz    NO.33
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0001,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to300MHz    NO.34
      //Address,Value,Mask
        {REG_000C_LPLL,0x0001,REG_000C_LPLL_REG_LPLL1_IBIAS_ICTRL},//reg_000c_lpll_reg_lpll1_ibias_ictrl
        {REG_0054_LPLL,0x0000,REG_0054_LPLL_REG_LPLL1_INPUT_DIV_FIRST},//reg_0054_lpll_reg_lpll1_input_div_first
        {REG_0004_LPLL,0x0000,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_FIRST},//reg_0004_lpll_reg_lpll1_loop_div_first
        {REG_0004_LPLL,0x0009,REG_0004_LPLL_REG_LPLL1_LOOP_DIV_SECOND},//reg_0004_lpll_reg_lpll1_loop_div_second
        {REG_0008_LPLL,0x0003,REG_0008_LPLL_REG_LPLL1_OUTPUT_DIV_SECOND},//reg_0008_lpll_reg_lpll1_output_div_second
        {REG_00D4_LPLL,0x0007,REG_00D4_LPLL_REG_LPLL1_SKEW_DIV},//reg_00d4_lpll_reg_lpll1_skew_div
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_FIFO_DIV},//reg_00b8_lpll_reg_lpll1_fifo_div
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_FIFO_DIV5_EN},//reg_000c_lpll_reg_lpll1_fifo_div5_en
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_EN_FIX_CLK},//reg_00b8_lpll_reg_lpll1_en_fix_clk
        {REG_00B8_LPLL,0x0001,REG_00B8_LPLL_REG_LPLL1_DUAP_LP_EN},//reg_00b8_lpll_reg_lpll1_duap_lp_en
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_SDIV2P5_EN},//reg_000c_lpll_reg_lpll1_sdiv2p5_en
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_MINI},//reg_00b8_lpll_reg_lpll1_en_mini
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_FIFO},//reg_00b8_lpll_reg_lpll1_en_fifo
        {REG_00D8_LPLL,0x8000,REG_00D8_LPLL_REG_LPLL1_TEST_0},//reg_00d8_lpll_reg_lpll1_test_0
        {REG_00DC_LPLL,0x0041,REG_00DC_LPLL_REG_LPLL1_TEST_1},//reg_00dc_lpll_reg_lpll1_test_1
        {REG_01A0_LPLL,0x0000,REG_01A0_LPLL_REG_LPLL1_EN_VBY1_HS},//reg_01a0_lpll_reg_lpll1_en_vby1_hs
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_PD},//reg_00cc_lpll_reg_lpll2_pd
        {REG_00CC_LPLL,0x0000,REG_00CC_LPLL_REG_LPLL2_IBIAS_ICTRL},//reg_00cc_lpll_reg_lpll2_ibias_ictrl
        {REG_00C0_LPLL,0x0000,REG_00C0_LPLL_REG_LPLL2_INPUT_DIV_FIRST},//reg_00c0_lpll_reg_lpll2_input_div_first
        {REG_00C4_LPLL,0x0001,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_FIRST},//reg_00c4_lpll_reg_lpll2_loop_div_first
        {REG_00C4_LPLL,0x0003,REG_00C4_LPLL_REG_LPLL2_LOOP_DIV_SECOND},//reg_00c4_lpll_reg_lpll2_loop_div_second
        {REG_00C8_LPLL,0x0000,REG_00C8_LPLL_REG_LPLL2_OUTPUT_DIV_FIRST},//reg_00c8_lpll_reg_lpll2_output_div_first
        {REG_00E4_LPLL,0x00C0,REG_00E4_LPLL_REG_LPLL2_TEST},//reg_00e4_lpll_reg_lpll2_test
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_EN},//reg_00e0_lpll_reg_lpll1_scalar2fifo_en
        {REG_00E0_LPLL,0x0000,REG_00E0_LPLL_REG_LPLL1_SCALAR2FIFO_DIV2},//reg_00e0_lpll_reg_lpll1_scalar2fifo_div2
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_ICTRL},//reg_0104_lpll_reg_lpllo_ictrl
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_INPUT_DIV_FIRST},//reg_0104_lpll_reg_lpllo_input_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_LOOP_DIV_FIRST},//reg_0104_lpll_reg_lpllo_loop_div_first
        {REG_0108_LPLL,0x0009,REG_0108_LPLL_REG_LPLLO_LOOP_DIV_SECOND},//reg_0108_lpll_reg_lpllo_loop_div_second
        {REG_0104_LPLL,0x0003,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_FIRST},//reg_0104_lpll_reg_lpllo_scalar_div_first
        {REG_0104_LPLL,0x0000,REG_0104_LPLL_REG_LPLLO_SCALAR_DIV_SECOND},//reg_0104_lpll_reg_lpllo_scalar_div_second
        {REG_0108_LPLL,0x0007,REG_0108_LPLL_REG_LPLLO_SKEW_DIV},//reg_0108_lpll_reg_lpllo_skew_div
        {REG_0108_LPLL,0x0000,REG_0108_LPLL_REG_LPLLO_FIFO_DIV},//reg_0108_lpll_reg_lpllo_fifo_div
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_FIFO_DIV5_EN},//reg_0100_lpll_reg_lpllo_fifo_div5_en
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_DUAL_LP_EN},//reg_0100_lpll_reg_lpllo_dual_lp_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_SDIV2P5_EN},//reg_0100_lpll_reg_lpllo_sdiv2p5_en
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_MINI},//reg_0100_lpll_reg_lpllo_en_mini
        {REG_0100_LPLL,0x0000,REG_0100_LPLL_REG_LPLLO_EN_FIFO},//reg_0100_lpll_reg_lpllo_en_fifo
        {REG_0110_LPLL,0x8000,REG_0110_LPLL_REG_LPLLO_TEST_0},//reg_0110_lpll_reg_lpllo_test_0
        {REG_0114_LPLL,0x0001,REG_0114_LPLL_REG_LPLLO_TEST_1},//reg_0114_lpll_reg_lpllo_test_1
        {REG_0100_LPLL,0x0001,REG_0100_LPLL_REG_LPLLO_PD},//reg_0100_lpll_reg_lpllo_pd
        {REG_00D4_LPLL,0x0001,REG_00D4_LPLL_REG_LPLL_2NDPLL_CLK_SEL},//reg_00d4_lpll_reg_lpll_2ndpll_clk_sel
        {REG_00B8_LPLL,0x0000,REG_00B8_LPLL_REG_LPLL1_EN_SCALAR},//reg_00b8_lpll_reg_lpll1_en_scalar
        {REG_000C_LPLL,0x0000,REG_000C_LPLL_REG_LPLL1_TEST_EN_SDIV},//reg_000c_lpll_reg_lpll1_test_en_sdiv
    },

};
uint16_t lpll_LoopGain[PNL_NUM_VER1]=
{
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz    NO.0
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz    NO.1
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz    NO.2
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz    NO.3
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz    NO.4
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz    NO.5
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz    NO.6
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz    NO.7
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz    NO.8
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz    NO.9
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz    NO.10
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz    NO.11
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_400to600MHz    NO.12
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to400MHz    NO.13
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to300MHz    NO.14
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_400to600MHz    NO.15
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to400MHz    NO.16
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to300MHz    NO.17
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz    NO.18
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz    NO.19
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to300MHz    NO.20
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_400to600MHz    NO.21
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to400MHz    NO.22
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to300MHz    NO.23
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to600MHz    NO.24
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to300MHz    NO.25
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz    NO.26
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz    NO.27
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz    NO.28
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz    NO.29
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to300MHz    NO.30
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz    NO.31
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to300MHz    NO.32
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz    NO.33
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to300MHz    NO.34
};
uint16_t lpll_LoopDiv[PNL_NUM_VER1]=
{
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz    NO.0
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz    NO.1
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz    NO.2
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz    NO.3
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz    NO.4
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz    NO.5
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz    NO.6
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz    NO.7
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz    NO.8
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz    NO.9
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz    NO.10
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz    NO.11
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_400to600MHz    NO.12
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to400MHz    NO.13
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_300to300MHz    NO.14
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_400to600MHz    NO.15
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to400MHz    NO.16
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_300to300MHz    NO.17
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz    NO.18
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz    NO.19
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to300MHz    NO.20
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_400to600MHz    NO.21
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to400MHz    NO.22
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_300to300MHz    NO.23
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to600MHz    NO.24
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_300to300MHz    NO.25
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz    NO.26
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz    NO.27
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz    NO.28
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz    NO.29
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to300MHz    NO.30
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz    NO.31
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to300MHz    NO.32
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz    NO.33
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to300MHz    NO.34
};




//======version2 start======


#define LPLL_REG_NUM_VER0200    (37)
#define MODA_REG_NUM_VER0200    (29)
#define MPLL_REG_NUM_VER0200    (7)
#define PNL_NUM_VER0200         (21)

TBLStruct LPLLSettingTBL_VER0200[PNL_NUM_VER0200][LPLL_REG_NUM_VER0200]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x4,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x4,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x5,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x5,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x4,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x4,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x2,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x4,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x5,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x2,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x4,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x3,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x1,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x6,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x1,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

};
TBLStruct MODASettingTBL_VER0200[PNL_NUM_VER0200][MODA_REG_NUM_VER0200]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

};
TBLStruct MPLLSettingTBL_VER0200[PNL_NUM_VER0200][MPLL_REG_NUM_VER0200]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

};
uint16_t lpll_LoopGain_VER0200[PNL_NUM_VER0200]=
{
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
    15,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
    18,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
};
uint16_t lpll_LoopDiv_VER0200[PNL_NUM_VER0200]=
{
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
    4,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
};


//======version2 end======

//======version3 start======

#define LPLL_REG_NUM_VER0300    (53)
#define MODA_REG_NUM_VER0300    (74)
#define MPLL_REG_NUM_VER0300    (7)
#define PNL_NUM_VER0300         (21)

TBLStruct LPLLSettingTBL_VER0300[PNL_NUM_VER0300][LPLL_REG_NUM_VER0300]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER2    NO.2
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.3
      //Address,Value,Mask
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.4
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER2    NO.5
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER2    NO.8
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.9
      //Address,Value,Mask
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.10
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER2    NO.11
      //Address,Value,Mask
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x1,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.12
      //Address,Value,Mask
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0xA,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x9,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x1,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER2    NO.13
      //Address,Value,Mask
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0xA,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x9,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x1,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER2    NO.14
      //Address,Value,Mask
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0xA,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xA,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER2    NO.15
      //Address,Value,Mask
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0xA,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xA,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER2    NO.16
      //Address,Value,Mask
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0xA,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xA,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER2    NO.17
      //Address,Value,Mask
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0xA,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xA,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER2    NO.18
      //Address,Value,Mask
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x8,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x1,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x2,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x8,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xF,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x1,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER2    NO.19
      //Address,Value,Mask
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x8,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x1,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x2,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x8,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xF,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x1,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

    { //E_PNL_SUPPORTED_LPLL_CEDS_TEST _0to600MHz_VER2    NO.20
      //Address,Value,Mask
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_output_div_second[13:12]
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_output_div_second[11:8]
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860B8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x4861A0,0x1,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_output_div_first
        {0x4860E4,0x6,Fld(3,5,AC_MSKW10)},//reg_lpll2_test[7:5]
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,4,AC_MSKW10)},//reg_lpllo_input_div_first
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x9,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486104,0x3,Fld(2,6,AC_MSKW10)},//reg_lpllo_scalar_div_first
        {0x486104,0x0,Fld(4,8,AC_MSKW10)},//reg_lpllo_scalar_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486108,0x0,Fld(3,4,AC_MSKW10)},//reg_lpllo_fifo_div
        {0x486100,0x0,Fld(1,5,AC_MSKW10)},//reg_lpllo_fifo_div5_en
        {0x486100,0x0,Fld(1,9,AC_MSKW10)},//reg_lpllo_skew_en_fixclk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486100,0x0,Fld(1,7,AC_MSKW10)},//reg_lpllo_sdiv2p5_en
        {0x486100,0x0,Fld(1,2,AC_MSKW10)},//reg_lpllo_en_mini
        {0x486100,0x0,Fld(1,1,AC_MSKW10)},//reg_lpllo_en_fifo
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x1,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[22]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860B8,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x48600C,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_test_en_sdiv
        {0x4860D8,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_test[11]
        {0x4860D8,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_test[9]
        {0x4860E4,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll2_test[0]
        {0x4860E4,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
    },

};
TBLStruct MODASettingTBL_VER0300[PNL_NUM_VER0300][MODA_REG_NUM_VER0300]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER2    NO.2
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.3
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.4
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER2    NO.5
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER2    NO.8
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.9
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.10
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER2    NO.11
      //Address,Value,Mask
        {0x484740,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xC,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xC,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xC,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xC,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.12
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER2    NO.13
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER2    NO.14
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER2    NO.15
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER2    NO.16
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER2    NO.17
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER2    NO.18
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER2    NO.19
      //Address,Value,Mask
        {0x484740,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0xA,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0xA,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0xA,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0xA,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

    { //E_PNL_SUPPORTED_LPLL_CEDS_TEST _0to600MHz_VER2    NO.20
      //Address,Value,Mask
        {0x484740,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch00
        {0x484740,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch01
        {0x484740,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch02
        {0x484740,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch03
        {0x484744,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch04
        {0x484744,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch05
        {0x484744,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch06
        {0x484744,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch07
        {0x484748,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch08
        {0x484748,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch09
        {0x484748,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch10
        {0x484748,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch11
        {0x48474C,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch12
        {0x48474C,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch13
        {0x48474C,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch14
        {0x48474C,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch15
        {0x484750,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch16
        {0x484750,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch17
        {0x484750,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch18
        {0x484750,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch19
        {0x484940,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch20
        {0x484940,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch21
        {0x484940,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch22
        {0x484940,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch23
        {0x484944,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch24
        {0x484944,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch25
        {0x484944,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch26
        {0x484944,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch27
        {0x484948,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch28
        {0x484948,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch29
        {0x484948,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch30
        {0x484948,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch31
        {0x48494C,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch32
        {0x48494C,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch33
        {0x48494C,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch34
        {0x48494C,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch35
        {0x484950,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch36
        {0x484950,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch37
        {0x484950,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch38
        {0x484950,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch39
        {0x484B40,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch40
        {0x484B40,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch41
        {0x484B40,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch42
        {0x484B40,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch43
        {0x484B44,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch44
        {0x484B44,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch45
        {0x484B44,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch46
        {0x484B44,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch47
        {0x484B48,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch48
        {0x484B48,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch49
        {0x484B48,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch50
        {0x484B48,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch51
        {0x484B4C,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch52
        {0x484B4C,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch53
        {0x484B4C,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch54
        {0x484B4C,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch55
        {0x484B50,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch56
        {0x484B50,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch57
        {0x484B50,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch58
        {0x484B50,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch59
        {0x484D40,0x0,Fld(4,0,AC_MSKW10)},//reg_gcr_vby1_vreg_ch60
        {0x484D40,0x0,Fld(4,4,AC_MSKW10)},//reg_gcr_vby1_vreg_ch61
        {0x484D40,0x0,Fld(4,8,AC_MSKW10)},//reg_gcr_vby1_vreg_ch62
        {0x484D40,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_vby1_vreg_ch63
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484604,0x1,Fld(1,11,AC_MSKW10)},//reg_gcr_en_reg[3]
        {0x484604,0x1,Fld(1,12,AC_MSKW10)},//reg_gcr_en_reg[4]
        {0x484604,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_reg[5]
        {0x484604,0x1,Fld(1,14,AC_MSKW10)},//reg_gcr_en_reg[6]
        {0x484604,0x1,Fld(1,15,AC_MSKW10)},//reg_gcr_en_reg[7]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
    },

};
TBLStruct MPLLSettingTBL_VER0300[PNL_NUM_VER0300][MPLL_REG_NUM_VER0300]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER2    NO.2
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.3
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.4
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER2    NO.5
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER2    NO.8
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.9
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.10
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER2    NO.11
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.12
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER2    NO.13
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER2    NO.14
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER2    NO.15
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER2    NO.16
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER2    NO.17
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER2    NO.18
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER2    NO.19
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_CEDS_TEST _0to600MHz_VER2    NO.20
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x12,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x133,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

};
uint16_t lpll_LoopGain_VER0300[PNL_NUM_VER0300]=
{
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER2    NO.2
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.3
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.4
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER2    NO.5
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.6
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.7
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER2    NO.8
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.9
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.10
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER2    NO.11
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.12
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER2    NO.13
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER2    NO.14
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER2    NO.15
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER2    NO.16
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER2    NO.17
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER2    NO.18
    6,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER2    NO.19
    6,           //E_PNL_SUPPORTED_LPLL_CEDS_TEST _0to600MHz_VER2    NO.20
};
uint16_t lpll_LoopDiv_VER0300[PNL_NUM_VER0300]=
{
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER2    NO.2
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.3
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.4
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER2    NO.5
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.6
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.7
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER2    NO.8
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.9
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.10
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER2    NO.11
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.12
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to300MHz_VER2    NO.13
    4,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to360MHz_VER2    NO.14
    4,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_4K144_180to180MHz_VER2    NO.15
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to720MHz_VER2    NO.16
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_8K144_360to360MHz_VER2    NO.17
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to576MHz_VER2    NO.18
    2,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode__0to576MHz_VER2    NO.19
    2,           //E_PNL_SUPPORTED_LPLL_CEDS_TEST _0to600MHz_VER2    NO.20
};

//======version3 end======



//======version302 start======

#define LPLL_REG_NUM_VER0203    (37)
#define MODA_REG_NUM_VER0203    (29)
#define MPLL_REG_NUM_VER0203    (7)
#define PNL_NUM_VER0203         (21)

TBLStruct LPLLSettingTBL_VER0203[PNL_NUM_VER0203][LPLL_REG_NUM_VER0203]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x1,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x7,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x3,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x7,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x1,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x0,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0xE,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x1,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x4,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x4,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x5,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x5,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x4,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x4,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x2,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x4,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x5,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x2,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x1,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x2,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x0,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x0,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x0,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x4,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x0,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x1,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x3,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x1,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x5,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
      //Address,Value,Mask
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x48600C,0x1,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x6,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_dual_lp_en
        {0x4861A0,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_en_vby1_hs
        {0x4860B8,0x0,Fld(1,14,AC_MSKW10)},//reg_lpll1_en_mini
        {0x4860D8,0x0,Fld(1,15,AC_MSKW10)},//reg_lpll1_test[15]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_master_slave_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860D8,0x1,Fld(1,1,AC_MSKW10)},//reg_lpll1_test[1]
        {0x486054,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(3,2,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(8,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E4,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll2_test[12]
        {0x4860E4,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll2_test[11]
        {0x4860E4,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll2_test[8]
        {0x486100,0x1,Fld(1,13,AC_MSKW10)},//reg_lpllo_pd
        {0x486104,0x3,Fld(3,0,AC_MSKW10)},//reg_lpllo_ictrl
        {0x486104,0x1,Fld(2,12,AC_MSKW10)},//reg_lpllo_loop_div_first
        {0x486108,0x3,Fld(4,0,AC_MSKW10)},//reg_lpllo_loop_div_second
        {0x486108,0x7,Fld(3,8,AC_MSKW10)},//reg_lpllo_skew_div
        {0x486100,0x1,Fld(1,4,AC_MSKW10)},//reg_lpllo_dual_lp_en
        {0x486110,0x0,Fld(1,15,AC_MSKW10)},//reg_lpllo_test[15]
        {0x486114,0x0,Fld(1,6,AC_MSKW10)},//reg_lpllo_test[16]
        {0x486114,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[22]
        {0x4860D8,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[0] (Retiming Bypass)
        {0x486110,0x0,Fld(1,0,AC_MSKW10)},//reg_lpllo_test[0] (Retiming Bypass)
    },

};
TBLStruct MODASettingTBL_VER0203[PNL_NUM_VER0203][MODA_REG_NUM_VER0203]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x3,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x3,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x3,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x3,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x3,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x3,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x3,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x3,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x0,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x0,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x0,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x0,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x0,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x0,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x0,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x0,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
      //Address,Value,Mask
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg[0]
        {0x484604,0x1,Fld(1,9,AC_MSKW10)},//reg_gcr_en_reg[1]
        {0x484604,0x1,Fld(1,10,AC_MSKW10)},//reg_gcr_en_reg[2]
        {0x484644,0x0,Fld(1,9,AC_MSKW10)},//reg_gcr_en_vby1_diff
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484754,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch00
        {0x484754,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch01
        {0x484754,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch02
        {0x484754,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch03
        {0x484754,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch04
        {0x484754,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch05
        {0x484754,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch06
        {0x484754,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch07
        {0x484758,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch08
        {0x484758,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch09
        {0x484758,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch10
        {0x484758,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch11
        {0x484758,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch12
        {0x484758,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch13
        {0x484758,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch14
        {0x484758,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch15
        {0x484958,0x1,Fld(2,8,AC_MSKW10)},//reg_drv_mod_ch32
        {0x484958,0x1,Fld(2,10,AC_MSKW10)},//reg_drv_mod_ch33
        {0x484958,0x1,Fld(2,12,AC_MSKW10)},//reg_drv_mod_ch34
        {0x484958,0x1,Fld(2,14,AC_MSKW10)},//reg_drv_mod_ch35
        {0x48495C,0x1,Fld(2,0,AC_MSKW10)},//reg_drv_mod_ch36
        {0x48495C,0x1,Fld(2,2,AC_MSKW10)},//reg_drv_mod_ch37
        {0x48495C,0x1,Fld(2,4,AC_MSKW10)},//reg_drv_mod_ch38
        {0x48495C,0x1,Fld(2,6,AC_MSKW10)},//reg_drv_mod_ch39
    },

};
TBLStruct MPLLSettingTBL_VER0203[PNL_NUM_VER0203][MPLL_REG_NUM_VER0203]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
      //Address,Value,Mask
        {0x4861B4,0x2,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x1B,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B0,0x3,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861BC,0x1,Fld(1,4,AC_MSKW10)},//reg_en_mpll_prdt
        {0x4861B0,0x0,Fld(1,8,AC_MSKW10)},//reg_en_mpll_test
        {0x4861B8,0x33,Fld(16,0,AC_MSKW10)},//reg_mpll_test
    },

};
uint16_t lpll_LoopGain_VER0203[PNL_NUM_VER0203]=
{
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
    6,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
    6,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
    15,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
    18,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
};
uint16_t lpll_LoopDiv_VER0203[PNL_NUM_VER0203]=
{
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER2    NO.0
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER2    NO.1
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER2    NO.2
    2,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER2    NO.3
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER2    NO.4
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER2    NO.5
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER2    NO.6
    2,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER2    NO.7
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_3BYTE_340to720MHz_VER2    NO.8
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_4BYTE_340to720MHz_VER2    NO.9
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_400to600MHz_VER2    NO.10
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_3BYTE_OSD_5BYTE_300to400MHz_VER2    NO.11
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_3BYTE_340to720MHz_VER2    NO.12
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_4BYTE_340to720MHz_VER2    NO.13
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_4BYTE_OSD_5BYTE_300to600MHz_VER2    NO.14
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_400to600MHz_VER2    NO.15
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_3BYTE_300to400MHz_VER2    NO.16
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_4BYTE_300to600MHz_VER2    NO.17
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_300to600MHz_VER2    NO.18
    4,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_Xtal_mode_0to607_5MHz_VER2    NO.19
    10,           //E_PNL_SUPPORTED_LPLL_Vx1_Video_5BYTE_OSD_5BYTE_Xtal_mode_0to583_2MHz_VER2    NO.20
};


//======version004 start======

#define LPLL_REG_NUM_VER004    (34)
#define MODA_REG_NUM_VER004    (11)
#define MPLL_REG_NUM_VER004    (8)
#define PNL_NUM_VER004         (177)

TBLStruct LPLLSettingTBL_VER004[PNL_NUM_VER004][LPLL_REG_NUM_VER004]=
{
    { //E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004    NO.0
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004    NO.1
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004    NO.2
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004    NO.3
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004    NO.4
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004    NO.5
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004    NO.6
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004    NO.7
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004    NO.8
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004    NO.9
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004    NO.10
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004    NO.11
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004    NO.12
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004    NO.13
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004    NO.14
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004    NO.15
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004    NO.16
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004    NO.17
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004    NO.18
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x3,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x2,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004    NO.19
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x3,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x2,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004    NO.20
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004    NO.21
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004    NO.22
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x3,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x2,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004    NO.23
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x3,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x2,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004    NO.24
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004    NO.25
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004    NO.26
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004    NO.27
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004    NO.28
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004    NO.29
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004    NO.30
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004    NO.31
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x2,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x1,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x5,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004    NO.32
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004    NO.33
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004    NO.34
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004    NO.35
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004    NO.36
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004    NO.37
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004    NO.38
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004    NO.39
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004    NO.40
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004    NO.41
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004    NO.42
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004    NO.43
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004    NO.44
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004    NO.45
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004    NO.46
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004    NO.47
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004    NO.48
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004    NO.49
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004    NO.50
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004    NO.51
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.52
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004    NO.53
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004    NO.54
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004    NO.55
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004    NO.56
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.57
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004    NO.58
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004    NO.59
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004    NO.60
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004    NO.61
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004    NO.62
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004    NO.63
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004    NO.64
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004    NO.65
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004    NO.66
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004    NO.67
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004    NO.68
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004    NO.69
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004    NO.70
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004    NO.71
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004    NO.72
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004    NO.73
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004    NO.74
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004    NO.75
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004    NO.76
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004    NO.77
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.78
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004    NO.79
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004    NO.80
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004    NO.81
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004    NO.82
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.83
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004    NO.84
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004    NO.85
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004    NO.86
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004    NO.87
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004    NO.88
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004    NO.89
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004    NO.90
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004    NO.91
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004    NO.92
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004    NO.93
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004    NO.94
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004    NO.95
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004    NO.96
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004    NO.97
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004    NO.98
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004    NO.99
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004    NO.100
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004    NO.101
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004    NO.102
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004    NO.103
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004    NO.104
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004    NO.105
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004    NO.106
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004    NO.107
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004    NO.108
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004    NO.109
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004    NO.110
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004    NO.111
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x2,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004    NO.112
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x2,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004    NO.113
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004    NO.114
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x2,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004    NO.115
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x2,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004    NO.116
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004    NO.117
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004    NO.118
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004    NO.119
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004    NO.120
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004    NO.121
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004    NO.122
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004    NO.123
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004    NO.124
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004    NO.125
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004    NO.126
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004    NO.127
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004    NO.128
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004    NO.129
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004    NO.130
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x9,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x8,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004    NO.131
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x9,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x8,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004    NO.132
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x9,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x8,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004    NO.133
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004    NO.134
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004    NO.135
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004    NO.136
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004    NO.137
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004    NO.138
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004    NO.139
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004    NO.140
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004    NO.141
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004    NO.142
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004    NO.143
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004    NO.144
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004    NO.145
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004    NO.146
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004    NO.147
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004    NO.148
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004    NO.149
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004    NO.150
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004    NO.151
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004    NO.152
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004    NO.153
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004    NO.154
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004    NO.155
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004    NO.156
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004    NO.157
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004    NO.158
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004    NO.159
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004    NO.160
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004    NO.161
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004    NO.162
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004    NO.163
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004    NO.164
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004    NO.165
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004    NO.166
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004    NO.167
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004    NO.168
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004    NO.169
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004    NO.170
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004    NO.171
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004    NO.172
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004    NO.173
      //Address,Value,Mask
        {0x48600C,0x7,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004    NO.174
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004    NO.175
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004    NO.176
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0xF,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0xF,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

};
TBLStruct MODASettingTBL_VER004[PNL_NUM_VER004][MODA_REG_NUM_VER004]=
{
    { //E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004    NO.0
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004    NO.1
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004    NO.2
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004    NO.3
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004    NO.4
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004    NO.5
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004    NO.6
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004    NO.7
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004    NO.8
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004    NO.9
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004    NO.10
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004    NO.11
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004    NO.12
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004    NO.13
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004    NO.14
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004    NO.15
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004    NO.16
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004    NO.17
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004    NO.18
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004    NO.19
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004    NO.20
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004    NO.21
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004    NO.22
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004    NO.23
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004    NO.24
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004    NO.25
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004    NO.26
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004    NO.27
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004    NO.28
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004    NO.29
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004    NO.30
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004    NO.31
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004    NO.32
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004    NO.33
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004    NO.34
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004    NO.35
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004    NO.36
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004    NO.37
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004    NO.38
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004    NO.39
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004    NO.40
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004    NO.41
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004    NO.42
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004    NO.43
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004    NO.44
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004    NO.45
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004    NO.46
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004    NO.47
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004    NO.48
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004    NO.49
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004    NO.50
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004    NO.51
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.52
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004    NO.53
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004    NO.54
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004    NO.55
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004    NO.56
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.57
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004    NO.58
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004    NO.59
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004    NO.60
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004    NO.61
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004    NO.62
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004    NO.63
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004    NO.64
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004    NO.65
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004    NO.66
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004    NO.67
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004    NO.68
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004    NO.69
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004    NO.70
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004    NO.71
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004    NO.72
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004    NO.73
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004    NO.74
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004    NO.75
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004    NO.76
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004    NO.77
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.78
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004    NO.79
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004    NO.80
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004    NO.81
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004    NO.82
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.83
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004    NO.84
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004    NO.85
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004    NO.86
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004    NO.87
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004    NO.88
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004    NO.89
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004    NO.90
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004    NO.91
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004    NO.92
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004    NO.93
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004    NO.94
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004    NO.95
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004    NO.96
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004    NO.97
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004    NO.98
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004    NO.99
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004    NO.100
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004    NO.101
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004    NO.102
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004    NO.103
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004    NO.104
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004    NO.105
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004    NO.106
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004    NO.107
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004    NO.108
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004    NO.109
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004    NO.110
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004    NO.111
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004    NO.112
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004    NO.113
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004    NO.114
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004    NO.115
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004    NO.116
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004    NO.117
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004    NO.118
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004    NO.119
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004    NO.120
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004    NO.121
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004    NO.122
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004    NO.123
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004    NO.124
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004    NO.125
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004    NO.126
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004    NO.127
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004    NO.128
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004    NO.129
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004    NO.130
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004    NO.131
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004    NO.132
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004    NO.133
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004    NO.134
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004    NO.135
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004    NO.136
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004    NO.137
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004    NO.138
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004    NO.139
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004    NO.140
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004    NO.141
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004    NO.142
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004    NO.143
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004    NO.144
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004    NO.145
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004    NO.146
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004    NO.147
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004    NO.148
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004    NO.149
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004    NO.150
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004    NO.151
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004    NO.152
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004    NO.153
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004    NO.154
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004    NO.155
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004    NO.156
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004    NO.157
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004    NO.158
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004    NO.159
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004    NO.160
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004    NO.161
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004    NO.162
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004    NO.163
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004    NO.164
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004    NO.165
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004    NO.166
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004    NO.167
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004    NO.168
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004    NO.169
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004    NO.170
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004    NO.171
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004    NO.172
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004    NO.173
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004    NO.174
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004    NO.175
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004    NO.176
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x3FFF,Fld(14,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484760,0x400,Fld(15,0,AC_MSKW10)},//reg_hw_rint_th
        {0x484618,0x0,Fld(14,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484DF8,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x48463C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

};
TBLStruct MPLLSettingTBL_VER004[PNL_NUM_VER004][MPLL_REG_NUM_VER004]=
{
    { //E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004    NO.0
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004    NO.1
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004    NO.2
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004    NO.3
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004    NO.4
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004    NO.5
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004    NO.6
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004    NO.7
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004    NO.8
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004    NO.9
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004    NO.10
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004    NO.11
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004    NO.12
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004    NO.13
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004    NO.14
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004    NO.15
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004    NO.16
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004    NO.17
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004    NO.18
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004    NO.19
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004    NO.20
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004    NO.21
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004    NO.22
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004    NO.23
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004    NO.24
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004    NO.25
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004    NO.26
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004    NO.27
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004    NO.28
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004    NO.29
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004    NO.30
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004    NO.31
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004    NO.32
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004    NO.33
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004    NO.34
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004    NO.35
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004    NO.36
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004    NO.37
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004    NO.38
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004    NO.39
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004    NO.40
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004    NO.41
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004    NO.42
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004    NO.43
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004    NO.44
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004    NO.45
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004    NO.46
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004    NO.47
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004    NO.48
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004    NO.49
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004    NO.50
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004    NO.51
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.52
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004    NO.53
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004    NO.54
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004    NO.55
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004    NO.56
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.57
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004    NO.58
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004    NO.59
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004    NO.60
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004    NO.61
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004    NO.62
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004    NO.63
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004    NO.64
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004    NO.65
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004    NO.66
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004    NO.67
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004    NO.68
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004    NO.69
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004    NO.70
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004    NO.71
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004    NO.72
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004    NO.73
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004    NO.74
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004    NO.75
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004    NO.76
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004    NO.77
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.78
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004    NO.79
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004    NO.80
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004    NO.81
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004    NO.82
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.83
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004    NO.84
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004    NO.85
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004    NO.86
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004    NO.87
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004    NO.88
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004    NO.89
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004    NO.90
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004    NO.91
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004    NO.92
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004    NO.93
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004    NO.94
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004    NO.95
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004    NO.96
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004    NO.97
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004    NO.98
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004    NO.99
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004    NO.100
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004    NO.101
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004    NO.102
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004    NO.103
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004    NO.104
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004    NO.105
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004    NO.106
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004    NO.107
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004    NO.108
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004    NO.109
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004    NO.110
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004    NO.111
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004    NO.112
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004    NO.113
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004    NO.114
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004    NO.115
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004    NO.116
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004    NO.117
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004    NO.118
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004    NO.119
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004    NO.120
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004    NO.121
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004    NO.122
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004    NO.123
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004    NO.124
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004    NO.125
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004    NO.126
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004    NO.127
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004    NO.128
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004    NO.129
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004    NO.130
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004    NO.131
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004    NO.132
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004    NO.133
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004    NO.134
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004    NO.135
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004    NO.136
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004    NO.137
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004    NO.138
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004    NO.139
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004    NO.140
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004    NO.141
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004    NO.142
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004    NO.143
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004    NO.144
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004    NO.145
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004    NO.146
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004    NO.147
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004    NO.148
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004    NO.149
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004    NO.150
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004    NO.151
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004    NO.152
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004    NO.153
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004    NO.154
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004    NO.155
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004    NO.156
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004    NO.157
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004    NO.158
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004    NO.159
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004    NO.160
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004    NO.161
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004    NO.162
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004    NO.163
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004    NO.164
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004    NO.165
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004    NO.166
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004    NO.167
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004    NO.168
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004    NO.169
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004    NO.170
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004    NO.171
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004    NO.172
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004    NO.173
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004    NO.174
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004    NO.175
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004    NO.176
      //Address,Value,Mask
        {0x4861BC,0x1,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x0,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x51,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x31,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

};

uint16_t lpll_LoopGain_VER004[PNL_NUM_VER004]=
{
    3,           //E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004    NO.0
    2,           //E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004    NO.1
    1,           //E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004    NO.2
    1,           //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004    NO.3
    24,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004    NO.4
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004    NO.5
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004    NO.6
    24,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004    NO.7
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004    NO.8
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004    NO.9
    24,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004    NO.10
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004    NO.11
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004    NO.12
    24,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004    NO.13
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004    NO.14
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004    NO.15
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004    NO.16
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004    NO.17
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004    NO.18
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004    NO.19
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004    NO.20
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004    NO.21
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004    NO.22
    4,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004    NO.23
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004    NO.24
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004    NO.25
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004    NO.26
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004    NO.27
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004    NO.28
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004    NO.29
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004    NO.30
    3,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004    NO.31
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004    NO.32
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004    NO.33
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004    NO.34
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004    NO.35
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004    NO.36
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004    NO.37
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004    NO.38
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004    NO.39
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004    NO.40
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004    NO.41
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004    NO.42
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004    NO.43
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004    NO.44
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004    NO.45
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004    NO.46
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004    NO.47
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004    NO.48
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004    NO.49
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004    NO.50
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004    NO.51
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.52
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004    NO.53
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004    NO.54
    2,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004    NO.55
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004    NO.56
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.57
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004    NO.58
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004    NO.59
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004    NO.60
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004    NO.61
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004    NO.62
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004    NO.63
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004    NO.64
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004    NO.65
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004    NO.66
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004    NO.67
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004    NO.68
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004    NO.69
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004    NO.70
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004    NO.71
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004    NO.72
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004    NO.73
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004    NO.74
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004    NO.75
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004    NO.76
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004    NO.77
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.78
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004    NO.79
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004    NO.80
    2,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004    NO.81
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004    NO.82
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.83
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004    NO.84
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004    NO.85
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004    NO.86
    32,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004    NO.87
    64,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004    NO.88
    64,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004    NO.89
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004    NO.90
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004    NO.91
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004    NO.92
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004    NO.93
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004    NO.94
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004    NO.95
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004    NO.96
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004    NO.97
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004    NO.98
    2,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004    NO.99
    1,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004    NO.100
    1,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004    NO.101
    27,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004    NO.102
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004    NO.103
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004    NO.104
    27,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004    NO.105
    27,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004    NO.106
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004    NO.107
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004    NO.108
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004    NO.109
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004    NO.110
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004    NO.111
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004    NO.112
    54,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004    NO.113
    36,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004    NO.114
    36,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004    NO.115
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004    NO.116
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004    NO.117
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004    NO.118
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004    NO.119
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004    NO.120
    32,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004    NO.121
    64,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004    NO.122
    64,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004    NO.123
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004    NO.124
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004    NO.125
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004    NO.126
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004    NO.127
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004    NO.128
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004    NO.129
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004    NO.130
    256,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004    NO.131
    256,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004    NO.132
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004    NO.133
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004    NO.134
    32,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004    NO.135
    64,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004    NO.136
    64,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004    NO.137
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004    NO.138
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004    NO.139
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004    NO.140
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004    NO.141
    16,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004    NO.142
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004    NO.143
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004    NO.144
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004    NO.145
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004    NO.146
    8,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004    NO.147
    8,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004    NO.148
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004    NO.149
    128,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004    NO.150
    128,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004    NO.151
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004    NO.152
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004    NO.153
    48,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004    NO.154
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004    NO.155
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004    NO.156
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004    NO.157
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004    NO.158
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004    NO.159
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004    NO.160
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004    NO.161
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004    NO.162
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004    NO.163
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004    NO.164
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004    NO.165
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004    NO.166
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004    NO.167
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004    NO.168
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004    NO.169
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004    NO.170
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004    NO.171
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004    NO.172
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004    NO.173
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004    NO.174
    4,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004    NO.175
    4,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004    NO.176
};
uint16_t lpll_LoopDiv_VER004[PNL_NUM_VER004]=
{
    1,           //E_PNL_SUPPORTED_LPLL_TTL_450to600MHz_VER004    NO.0
    1,           //E_PNL_SUPPORTED_LPLL_TTL_225to450MHz_VER004    NO.1
    1,           //E_PNL_SUPPORTED_LPLL_TTL_75to225MHz_VER004    NO.2
    1,           //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz_VER004    NO.3
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER004    NO.4
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER004    NO.5
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER004    NO.6
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER004    NO.7
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER004    NO.8
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER004    NO.9
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER004    NO.10
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER004    NO.11
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER004    NO.12
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER004    NO.13
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER004    NO.14
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER004    NO.15
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to600MHz_VER004    NO.16
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_6bit_300to300MHz_VER004    NO.17
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to600MHz_VER004    NO.18
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_6bit_300to300MHz_VER004    NO.19
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to600MHz_VER004    NO.20
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_6bit_300to300MHz_VER004    NO.21
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to600MHz_VER004    NO.22
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_6bit_300to300MHz_VER004    NO.23
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to600MHz_VER004    NO.24
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_3pair_8bit_300to300MHz_VER004    NO.25
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to600MHz_VER004    NO.26
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_1bk_6pair_8bit_300to300MHz_VER004    NO.27
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to600MHz_VER004    NO.28
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER004    NO.29
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to600MHz_VER004    NO.30
    1,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_6pair_8bit_300to300MHz_VER004    NO.31
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_450to600MHz_VER004    NO.32
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to450MHz_VER004    NO.33
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_CML_300to300MHz_VER004    NO.34
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_450to600MHz_VER004    NO.35
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to450MHz_VER004    NO.36
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_CML_300to300MHz_VER004    NO.37
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to600MHz_VER004    NO.38
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_CML_300to300MHz_VER004    NO.39
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_450to600MHz_VER004    NO.40
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to450MHz_VER004    NO.41
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_CML_300to300MHz_VER004    NO.42
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_350to600MHz_VER004    NO.43
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to350MHz_VER004    NO.44
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_CML_300to300MHz_VER004    NO.45
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_450to600MHz_VER004    NO.46
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to450MHz_VER004    NO.47
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_CML_300to300MHz_VER004    NO.48
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to600MHz_VER004    NO.49
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_CML_300to300MHz_VER004    NO.50
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER004    NO.51
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.52
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to600MHz_VER004    NO.53
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_CML_300to300MHz_VER004    NO.54
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_250to360MHz_VER004    NO.55
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to250MHz_VER004    NO.56
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER004    NO.57
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_450to600MHz_VER004    NO.58
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to450MHz_VER004    NO.59
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_2pair_2K_LVDS_300to300MHz_VER004    NO.60
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_450to600MHz_VER004    NO.61
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to450MHz_VER004    NO.62
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4pair_2K_LVDS_300to300MHz_VER004    NO.63
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to600MHz_VER004    NO.64
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6pair_2K_LVDS_300to300MHz_VER004    NO.65
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_450to600MHz_VER004    NO.66
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to450MHz_VER004    NO.67
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8pair_2K_LVDS_300to300MHz_VER004    NO.68
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_350to600MHz_VER004    NO.69
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to350MHz_VER004    NO.70
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K_LVDS_300to300MHz_VER004    NO.71
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_450to600MHz_VER004    NO.72
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to450MHz_VER004    NO.73
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K_LVDS_300to300MHz_VER004    NO.74
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to600MHz_VER004    NO.75
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K_LVDS_300to300MHz_VER004    NO.76
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER004    NO.77
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.78
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to600MHz_VER004    NO.79
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K_LVDS_300to300MHz_VER004    NO.80
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_250to360MHz_VER004    NO.81
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to250MHz_VER004    NO.82
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER004    NO.83
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_400to600MHz_VER004    NO.84
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to400MHz_VER004    NO.85
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_300to300MHz_VER004    NO.86
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_450to600MHz_VER004    NO.87
    27,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to450MHz_VER004    NO.88
    27,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_300to300MHz_VER004    NO.89
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to600MHz_VER004    NO.90
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_300to300MHz_VER004    NO.91
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to360MHz_VER004    NO.92
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K1K144_180to180MHz_VER004    NO.93
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_400to600MHz_VER004    NO.94
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to400MHz_VER004    NO.95
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_8x1_300to300MHz_VER004    NO.96
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to600MHz_VER004    NO.97
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_300to300MHz_VER004    NO.98
    1,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_250to360MHz_VER004    NO.99
    1,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to250MHz_VER004    NO.100
    1,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER004    NO.101
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_400to600MHz_VER004    NO.102
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to400MHz_VER004    NO.103
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_300to300MHz_VER004    NO.104
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to600MHz_VER004    NO.105
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_300to300MHz_VER004    NO.106
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER004    NO.107
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER004    NO.108
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to600MHz_VER004    NO.109
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_6x1_300to300MHz_VER004    NO.110
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to600MHz_VER004    NO.111
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_300to300MHz_VER004    NO.112
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_300to360MHz_VER004    NO.113
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to300MHz_VER004    NO.114
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER004    NO.115
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_400to600MHz_VER004    NO.116
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to400MHz_VER004    NO.117
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_300to300MHz_VER004    NO.118
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to600MHz_VER004    NO.119
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_300to300MHz_VER004    NO.120
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_450to600MHz_VER004    NO.121
    27,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to450MHz_VER004    NO.122
    27,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_300to300MHz_VER004    NO.123
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to600MHz_VER004    NO.124
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_300to300MHz_VER004    NO.125
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER004    NO.126
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER004    NO.127
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to600MHz_VER004    NO.128
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_300to300MHz_VER004    NO.129
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_400to600MHz_VER004    NO.130
    135,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to400MHz_VER004    NO.131
    135,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_8x1_300to300MHz_VER004    NO.132
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to600MHz_VER004    NO.133
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_300to300MHz_VER004    NO.134
    15,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_300to360MHz_VER004    NO.135
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to300MHz_VER004    NO.136
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER004    NO.137
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to600MHz_VER004    NO.138
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_300to300MHz_VER004    NO.139
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to600MHz_VER004    NO.140
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_300to300MHz_VER004    NO.141
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_450to600MHz_VER004    NO.142
    15,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to450MHz_VER004    NO.143
    15,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_300to300MHz_VER004    NO.144
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to600MHz_VER004    NO.145
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_300to300MHz_VER004    NO.146
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER004    NO.147
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER004    NO.148
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_350to600MHz_VER004    NO.149
    75,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to350MHz_VER004    NO.150
    75,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_300to300MHz_VER004    NO.151
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to600MHz_VER004    NO.152
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_300to300MHz_VER004    NO.153
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_250to360MHz_VER004    NO.154
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to250MHz_VER004    NO.155
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER004    NO.156
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to600MHz_VER004    NO.157
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_300to300MHz_VER004    NO.158
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to600MHz_VER004    NO.159
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_300to300MHz_VER004    NO.160
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to600MHz_VER004    NO.161
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_300to300MHz_VER004    NO.162
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to360MHz_VER004    NO.163
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1K144_180to180MHz_VER004    NO.164
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_450to600MHz_VER004    NO.165
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to450MHz_VER004    NO.166
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_300to300MHz_VER004    NO.167
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_450to600MHz_VER004    NO.168
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to450MHz_VER004    NO.169
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_300to300MHz_VER004    NO.170
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_450to600MHz_VER004    NO.171
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to450MHz_VER004    NO.172
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_300to300MHz_VER004    NO.173
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_200to360MHz_VER004    NO.174
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to200MHz_VER004    NO.175
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1K144_180to180MHz_VER004    NO.176
};

//======version004 end======

//======version4 end======

//======version005 start======

#define LPLL_REG_NUM_VER005    (36)
#define MODA_REG_NUM_VER005    (10)
#define MPLL_REG_NUM_VER005    (8)
#define PNL_NUM_VER005         (232)

TBLStruct LPLLSettingTBL_VER005[PNL_NUM_VER005][LPLL_REG_NUM_VER005]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005    NO.0
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005    NO.1
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005    NO.2
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005    NO.3
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005    NO.4
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005    NO.5
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x1,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005    NO.6
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005    NO.7
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005    NO.8
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005    NO.9
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005    NO.10
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005    NO.11
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_360to600MHz_VER005    NO.12
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to360MHz_VER005    NO.13
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to300MHz_VER005    NO.14
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_450to600MHz_VER005    NO.15
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to450MHz_VER005    NO.16
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to300MHz_VER005    NO.17
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to600MHz_VER005    NO.18
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to300MHz_VER005    NO.19
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_360to600MHz_VER005    NO.20
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to360MHz_VER005    NO.21
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to300MHz_VER005    NO.22
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_450to600MHz_VER005    NO.23
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to450MHz_VER005    NO.24
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to300MHz_VER005    NO.25
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to720MHz_VER005    NO.26
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to360MHz_VER005    NO.27
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_480to720MHz_VER005    NO.28
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to480MHz_VER005    NO.29
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to360MHz_VER005    NO.30
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to600MHz_VER005    NO.31
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to300MHz_VER005    NO.32
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to600MHz_VER005    NO.33
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to300MHz_VER005    NO.34
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to600MHz_VER005    NO.35
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to300MHz_VER005    NO.36
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_400to600MHz_VER005    NO.37
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to400MHz_VER005    NO.38
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to300MHz_VER005    NO.39
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_360to600MHz_VER005    NO.40
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to360MHz_VER005    NO.41
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to300MHz_VER005    NO.42
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_450to600MHz_VER005    NO.43
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to450MHz_VER005    NO.44
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to300MHz_VER005    NO.45
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.46
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.47
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_360to600MHz_VER005    NO.48
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to360MHz_VER005    NO.49
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.50
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_450to600MHz_VER005    NO.51
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to450MHz_VER005    NO.52
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.53
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to720MHz_VER005    NO.54
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to360MHz_VER005    NO.55
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_480to720MHz_VER005    NO.56
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to480MHz_VER005    NO.57
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to360MHz_VER005    NO.58
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.59
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.60
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to600MHz_VER005    NO.61
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to300MHz_VER005    NO.62
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to600MHz_VER005    NO.63
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.64
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_400to600MHz_VER005    NO.65
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to400MHz_VER005    NO.66
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.67
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_400to600MHz_VER005    NO.68
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to400MHz_VER005    NO.69
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to300MHz_VER005    NO.70
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_450to600MHz_VER005    NO.71
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to450MHz_VER005    NO.72
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to300MHz_VER005    NO.73
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to600MHz_VER005    NO.74
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to300MHz_VER005    NO.75
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_450to600MHz_VER005    NO.76
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to450MHz_VER005    NO.77
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to300MHz_VER005    NO.78
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_400to600MHz_VER005    NO.79
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to400MHz_VER005    NO.80
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to300MHz_VER005    NO.81
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to720MHz_VER005    NO.82
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to360MHz_VER005    NO.83
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to600MHz_VER005    NO.84
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to300MHz_VER005    NO.85
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_540to720MHz_VER005    NO.86
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to540MHz_VER005    NO.87
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to360MHz_VER005    NO.88
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to600MHz_VER005    NO.89
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x2,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to300MHz_VER005    NO.90
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x2,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to600MHz_VER005    NO.91
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x3,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to300MHz_VER005    NO.92
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x3,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to600MHz_VER005    NO.93
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to300MHz_VER005    NO.94
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_400to600MHz_VER005    NO.95
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to400MHz_VER005    NO.96
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to300MHz_VER005    NO.97
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_400to600MHz_VER005    NO.98
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to400MHz_VER005    NO.99
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to300MHz_VER005    NO.100
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_450to600MHz_VER005    NO.101
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to450MHz_VER005    NO.102
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to300MHz_VER005    NO.103
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to600MHz_VER005    NO.104
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to300MHz_VER005    NO.105
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_400to600MHz_VER005    NO.106
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to400MHz_VER005    NO.107
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to300MHz_VER005    NO.108
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to720MHz_VER005    NO.109
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to360MHz_VER005    NO.110
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to600MHz_VER005    NO.111
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to300MHz_VER005    NO.112
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to600MHz_VER005    NO.113
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to300MHz_VER005    NO.114
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x3,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_400to600MHz_VER005    NO.115
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to400MHz_VER005    NO.116
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to300MHz_VER005    NO.117
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to600MHz_VER005    NO.118
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to300MHz_VER005    NO.119
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_450to600MHz_VER005    NO.120
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to450MHz_VER005    NO.121
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to300MHz_VER005    NO.122
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to600MHz_VER005    NO.123
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to300MHz_VER005    NO.124
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_400to600MHz_VER005    NO.125
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to400MHz_VER005    NO.126
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to300MHz_VER005    NO.127
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to720MHz_VER005    NO.128
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to360MHz_VER005    NO.129
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to600MHz_VER005    NO.130
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to300MHz_VER005    NO.131
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to600MHz_VER005    NO.132
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to300MHz_VER005    NO.133
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to600MHz_VER005    NO.134
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to300MHz_VER005    NO.135
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to720MHz_VER005    NO.136
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to360MHz_VER005    NO.137
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to600MHz_VER005    NO.138
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to300MHz_VER005    NO.139
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to600MHz_VER005    NO.140
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to300MHz_VER005    NO.141
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_450to600MHz_VER005    NO.142
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to450MHz_VER005    NO.143
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to300MHz_VER005    NO.144
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to600MHz_VER005    NO.145
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to300MHz_VER005    NO.146
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to600MHz_VER005    NO.147
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to300MHz_VER005    NO.148
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to720MHz_VER005    NO.149
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to360MHz_VER005    NO.150
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_360to600MHz_VER005    NO.151
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to360MHz_VER005    NO.152
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to300MHz_VER005    NO.153
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to600MHz_VER005    NO.154
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to300MHz_VER005    NO.155
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to600MHz_VER005    NO.156
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to300MHz_VER005    NO.157
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to600MHz_VER005    NO.158
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to300MHz_VER005    NO.159
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to600MHz_VER005    NO.160
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to300MHz_VER005    NO.161
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to600MHz_VER005    NO.162
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to300MHz_VER005    NO.163
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to600MHz_VER005    NO.164
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to300MHz_VER005    NO.165
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to720MHz_VER005    NO.166
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to360MHz_VER005    NO.167
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_450to600MHz_VER005    NO.168
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to450MHz_VER005    NO.169
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to300MHz_VER005    NO.170
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_450to600MHz_VER005    NO.171
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to450MHz_VER005    NO.172
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to300MHz_VER005    NO.173
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_450to600MHz_VER005    NO.174
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to450MHz_VER005    NO.175
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to300MHz_VER005    NO.176
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_450to600MHz_VER005    NO.177
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to450MHz_VER005    NO.178
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to300MHz_VER005    NO.179
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_480to720MHz_VER005    NO.180
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to480MHz_VER005    NO.181
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to360MHz_VER005    NO.182
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to405MHz_VER005    NO.183
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to202MHz_VER005    NO.184
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x5,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to700MHz_VER005    NO.185
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER005    NO.186
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x1,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x0,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER005    NO.187
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.188
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_270to360MHz_VER005    NO.189
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to270MHz_VER005    NO.190
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.191
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x1,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to360MHz_VER005    NO.192
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to180MHz_VER005    NO.193
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER005    NO.194
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.195
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x7,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_270to360MHz_VER005    NO.196
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to270MHz_VER005    NO.197
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.198
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to360MHz_VER005    NO.199
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to180MHz_VER005    NO.200
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER005    NO.201
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER005    NO.202
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_270to360MHz_VER005    NO.203
      //Address,Value,Mask
        {0x48600C,0x6,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to270MHz_VER005    NO.204
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to180MHz_VER005    NO.205
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to360MHz_VER005    NO.206
      //Address,Value,Mask
        {0x48600C,0x6,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER005    NO.207
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x9,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to360MHz_VER005    NO.208
      //Address,Value,Mask
        {0x48600C,0x6,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x3,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to180MHz_VER005    NO.209
      //Address,Value,Mask
        {0x48600C,0x6,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x0,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x3,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to360MHz_VER005    NO.210
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to180MHz_VER005    NO.211
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_270to360MHz_VER005    NO.212
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to270MHz_VER005    NO.213
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER005    NO.214
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x0,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER005    NO.215
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER005    NO.216
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x3,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_270to360MHz_VER005    NO.217
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to270MHz_VER005    NO.218
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER005    NO.219
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x4,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x4,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x9,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x4,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER005    NO.220
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER005    NO.221
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x1,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_270to360MHz_VER005    NO.222
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to270MHz_VER005    NO.223
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER005    NO.224
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x1,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x1,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x1,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x1,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to360MHz_VER005    NO.225
      //Address,Value,Mask
        {0x48600C,0x6,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to180MHz_VER005    NO.226
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_240to360MHz_VER005    NO.227
      //Address,Value,Mask
        {0x48600C,0x4,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x3,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to240MHz_VER005    NO.228
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to180MHz_VER005    NO.229
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x2,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x1,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x0,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to405MHz_VER005    NO.230
      //Address,Value,Mask
        {0x48600C,0x6,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to202MHz_VER005    NO.231
      //Address,Value,Mask
        {0x48600C,0x5,Fld(3,2,AC_MSKW10)},//reg_lpll1_ibias_ictrl
        {0x486054,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_input_div_first
        {0x486004,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll1_loop_div_first
        {0x486004,0x2,Fld(5,8,AC_MSKW10)},//reg_lpll1_loop_div_second
        {0x486008,0x0,Fld(2,0,AC_MSKW10)},//reg_lpll1_scalar_div_first
        {0x486008,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_scalar_div_second
        {0x4860D4,0x7,Fld(3,12,AC_MSKW10)},//reg_lpll1_skew_div
        {0x4860B8,0x0,Fld(3,0,AC_MSKW10)},//reg_lpll1_fifo_div
        {0x48600C,0x0,Fld(1,11,AC_MSKW10)},//reg_lpll1_fifo_div5_en
        {0x4860B8,0x1,Fld(1,12,AC_MSKW10)},//reg_lpll1_en_fix_clk
        {0x4860D4,0x1,Fld(1,5,AC_MSKW10)},//reg_lpll_2ndpll_clk_sel
        {0x4860AC,0x3,Fld(2,12,AC_MSKW10)},//reg_lpll1_mode_sel
        {0x4860D0,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_fine_phsel1
        {0x4860D0,0x0,Fld(4,8,AC_MSKW10)},//reg_lpll1_fine_phsel2
        {0x48619C,0x0,Fld(4,0,AC_MSKW10)},//reg_lpll1_coarse_phsel1
        {0x48619C,0x0,Fld(4,4,AC_MSKW10)},//reg_lpll1_coarse_phsel2
        {0x4860DC,0x0,Fld(1,4,AC_MSKW10)},//reg_lpll1_test[20]
        {0x486010,0x0,Fld(1,13,AC_MSKW10)},//reg_lpll1_sdiv3p5_en
        {0x48600C,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_sdiv2p5_en
        {0x4860B8,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_en_fifo
        {0x4860B8,0x1,Fld(1,4,AC_MSKW10)},//reg_lpll1_en_scalar
        {0x4860DC,0x0,Fld(1,2,AC_MSKW10)},//reg_lpll1_test[18]
        {0x4860DC,0x0,Fld(1,0,AC_MSKW10)},//reg_lpll1_test[16]
        {0x4860DC,0x0,Fld(1,6,AC_MSKW10)},//reg_lpll1_test[22]
        {0x4860BC,0x2,Fld(2,8,AC_MSKW10)},//reg_lpll1_master_slave_div_first
        {0x4860BC,0x0,Fld(1,12,AC_MSKW10)},//reg_lpll1_master_slave_div3_en
        {0x4860BC,0x0,Fld(1,10,AC_MSKW10)},//reg_lpll1_master_slave_div5_en
        {0x4860CC,0x0,Fld(1,5,AC_MSKW10)},//reg_lpll2_pd
        {0x4860CC,0x0,Fld(4,9,AC_MSKW10)},//reg_lpll2_ibias_ictrl
        {0x4860CC,0x1,Fld(1,13,AC_MSKW10)},//reg_lpll2_ibias_ctrl_extra
        {0x4860C0,0x5,Fld(5,0,AC_MSKW10)},//reg_lpll2_input_div_first
        {0x4860C4,0x3,Fld(2,0,AC_MSKW10)},//reg_lpll2_loop_div_first
        {0x4860C4,0x0,Fld(5,8,AC_MSKW10)},//reg_lpll2_loop_div_second
        {0x4860C8,0x1,Fld(4,0,AC_MSKW10)},//reg_lpll2_post_div
        {0x4860E0,0x0,Fld(1,9,AC_MSKW10)},//reg_lpll1_scalar2fifo_en
        {0x4860E0,0x0,Fld(1,8,AC_MSKW10)},//reg_lpll1_scalar2fifo_div2
    },

};

TBLStruct MODASettingTBL_VER005[PNL_NUM_VER005][MODA_REG_NUM_VER005]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005    NO.0
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005    NO.1
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005    NO.2
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005    NO.3
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005    NO.4
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005    NO.5
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005    NO.6
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005    NO.7
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005    NO.8
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005    NO.9
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005    NO.10
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005    NO.11
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 6x1_4K60_CML_360to600MHz_VER005    NO.12
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 6x1_4K60_CML_300to360MHz_VER005    NO.13
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 6x1_4K60_CML_300to300MHz_VER005    NO.14
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 8x1_4K60_CML_450to600MHz_VER005    NO.15
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 8x1_4K60_CML_300to450MHz_VER005    NO.16
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 8x1_4K60_CML_300to300MHz_VER005    NO.17
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K60_CML_300to600MHz_VER005    NO.18
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K60_CML_300to300MHz_VER005    NO.19
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K120_CML_360to600MHz_VER005    NO.20
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K120_CML_300to360MHz_VER005    NO.21
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K120_CML_300to300MHz_VER005    NO.22
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K120_CML_450to600MHz_VER005    NO.23
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K120_CML_300to450MHz_VER005    NO.24
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K120_CML_300to300MHz_VER005    NO.25
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K144_CML_360to720MHz_VER005    NO.26
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K144_CML_360to360MHz_VER005    NO.27
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K144_CML_480to720MHz_VER005    NO.28
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K144_CML_360to480MHz_VER005    NO.29
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K144_CML_360to360MHz_VER005    NO.30
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K60_CML_300to600MHz_VER005    NO.31
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K60_CML_300to300MHz_VER005    NO.32
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K60_CML_300to600MHz_VER005    NO.33
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K60_CML_300to300MHz_VER005    NO.34
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K120_CML_300to600MHz_VER005    NO.35
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K120_CML_300to300MHz_VER005    NO.36
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K120_CML_400to600MHz_VER005    NO.37
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K120_CML_300to400MHz_VER005    NO.38
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K120_CML_300to300MHz_VER005    NO.39
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 6x1_4K60_LVDS_360to600MHz_VER005    NO.40
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 6x1_4K60_LVDS_300to360MHz_VER005    NO.41
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 6x1_4K60_LVDS_300to300MHz_VER005    NO.42
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 8x1_4K60_LVDS_450to600MHz_VER005    NO.43
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 8x1_4K60_LVDS_300to450MHz_VER005    NO.44
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 8x1_4K60_LVDS_300to300MHz_VER005    NO.45
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K60_LVDS_300to600MHz_VER005    NO.46
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K60_LVDS_300to300MHz_VER005    NO.47
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K120_LVDS_360to600MHz_VER005    NO.48
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K120_LVDS_300to360MHz_VER005    NO.49
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K120_LVDS_300to300MHz_VER005    NO.50
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K120_LVDS_450to600MHz_VER005    NO.51
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K120_LVDS_300to450MHz_VER005    NO.52
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K120_LVDS_300to300MHz_VER005    NO.53
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K144_LVDS_360to720MHz_VER005    NO.54
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K144_LVDS_360to360MHz_VER005    NO.55
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K144_LVDS_480to720MHz_VER005    NO.56
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K144_LVDS_360to480MHz_VER005    NO.57
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 16x1_4K144_LVDS_360to360MHz_VER005    NO.58
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K60_LVDS_300to600MHz_VER005    NO.59
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K60_LVDS_300to300MHz_VER005    NO.60
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K60_LVDS_300to600MHz_VER005    NO.61
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K60_LVDS_300to300MHz_VER005    NO.62
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K120_LVDS_300to600MHz_VER005    NO.63
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K120_LVDS_300to300MHz_VER005    NO.64
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K120_LVDS_400to600MHz_VER005    NO.65
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K120_LVDS_300to400MHz_VER005    NO.66
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K120_LVDS_300to300MHz_VER005    NO.67
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 6x1_4K60_400to600MHz_VER005    NO.68
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 6x1_4K60_300to400MHz_VER005    NO.69
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 6x1_4K60_300to300MHz_VER005    NO.70
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 8x1_4K60_450to600MHz_VER005    NO.71
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 8x1_4K60_300to450MHz_VER005    NO.72
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 8x1_4K60_300to300MHz_VER005    NO.73
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K60_300to600MHz_VER005    NO.74
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K60_300to300MHz_VER005    NO.75
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K60_450to600MHz_VER005    NO.76
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K60_300to450MHz_VER005    NO.77
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K60_300to300MHz_VER005    NO.78
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K120_400to600MHz_VER005    NO.79
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K120_300to400MHz_VER005    NO.80
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K120_300to300MHz_VER005    NO.81
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K144_360to720MHz_VER005    NO.82
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K144_360to360MHz_VER005    NO.83
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K120_300to600MHz_VER005    NO.84
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K120_300to300MHz_VER005    NO.85
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K144_540to720MHz_VER005    NO.86
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K144_360to540MHz_VER005    NO.87
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K144_360to360MHz_VER005    NO.88
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 12x1_4K60_300to600MHz_VER005    NO.89
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 12x1_4K60_300to300MHz_VER005    NO.90
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K60_300to600MHz_VER005    NO.91
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K60_300to300MHz_VER005    NO.92
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 12x1_4K120_300to600MHz_VER005    NO.93
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 12x1_4K120_300to300MHz_VER005    NO.94
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K120_400to600MHz_VER005    NO.95
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K120_300to400MHz_VER005    NO.96
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K120_300to300MHz_VER005    NO.97
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 6x1_4K60_400to600MHz_VER005    NO.98
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 6x1_4K60_300to400MHz_VER005    NO.99
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 6x1_4K60_300to300MHz_VER005    NO.100
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 8x1_4K60_450to600MHz_VER005    NO.101
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 8x1_4K60_300to450MHz_VER005    NO.102
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 8x1_4K60_300to300MHz_VER005    NO.103
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K60_300to600MHz_VER005    NO.104
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K60_300to300MHz_VER005    NO.105
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K120_400to600MHz_VER005    NO.106
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K120_300to400MHz_VER005    NO.107
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K120_300to300MHz_VER005    NO.108
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K144_360to720MHz_VER005    NO.109
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27 8bit 12x1_4K144_360to360MHz_VER005    NO.110
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K60_300to600MHz_VER005    NO.111
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K60_300to300MHz_VER005    NO.112
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K120_300to600MHz_VER005    NO.113
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K120_300to300MHz_VER005    NO.114
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 6x1_4K60_400to600MHz_VER005    NO.115
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 6x1_4K60_300to400MHz_VER005    NO.116
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 6x1_4K60_300to300MHz_VER005    NO.117
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 6x2_4K60_300to600MHz_VER005    NO.118
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 6x2_4K60_300to300MHz_VER005    NO.119
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 8x1_4K60_450to600MHz_VER005    NO.120
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 8x1_4K60_300to450MHz_VER005    NO.121
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 8x1_4K60_300to300MHz_VER005    NO.122
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K60_300to600MHz_VER005    NO.123
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K60_300to300MHz_VER005    NO.124
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K120_400to600MHz_VER005    NO.125
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K120_300to400MHz_VER005    NO.126
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K120_300to300MHz_VER005    NO.127
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K144_360to720MHz_VER005    NO.128
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K144_360to360MHz_VER005    NO.129
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 6x2_4K60_300to600MHz_VER005    NO.130
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 6x2_4K60_300to300MHz_VER005    NO.131
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K60_300to600MHz_VER005    NO.132
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K60_300to300MHz_VER005    NO.133
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K120_300to600MHz_VER005    NO.134
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K120_300to300MHz_VER005    NO.135
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K144_360to720MHz_VER005    NO.136
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K144_360to360MHz_VER005    NO.137
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 6x1_4K60_300to600MHz_VER005    NO.138
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 6x1_4K60_300to300MHz_VER005    NO.139
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 6x2_4K60_300to600MHz_VER005    NO.140
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 6x2_4K60_300to300MHz_VER005    NO.141
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 8x1_4K60_450to600MHz_VER005    NO.142
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 8x1_4K60_300to450MHz_VER005    NO.143
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 8x1_4K60_300to300MHz_VER005    NO.144
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K60_300to600MHz_VER005    NO.145
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K60_300to300MHz_VER005    NO.146
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K120_300to600MHz_VER005    NO.147
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K120_300to300MHz_VER005    NO.148
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K144_360to720MHz_VER005    NO.149
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K144_360to360MHz_VER005    NO.150
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 8x1_4K60_360to600MHz_VER005    NO.151
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 8x1_4K60_300to360MHz_VER005    NO.152
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 8x1_4K60_300to300MHz_VER005    NO.153
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K60_300to600MHz_VER005    NO.154
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K60_300to300MHz_VER005    NO.155
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K120_300to600MHz_VER005    NO.156
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K120_300to300MHz_VER005    NO.157
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 2_lane_2K60_300to600MHz_VER005    NO.158
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 2_lane_2K60_300to300MHz_VER005    NO.159
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 4_lane_4K30_300to600MHz_VER005    NO.160
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 4_lane_4K30_300to300MHz_VER005    NO.161
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane_4K60_300to600MHz_VER005    NO.162
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane_4K60_300to300MHz_VER005    NO.163
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 16_lane_4K120_300to600MHz_VER005    NO.164
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 16_lane_4K120_300to300MHz_VER005    NO.165
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 16_lane_4K144_360to720MHz_VER005    NO.166
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 16_lane_4K144_360to360MHz_VER005    NO.167
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 2_lane_2K60_450to600MHz_VER005    NO.168
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 2_lane_2K60_300to450MHz_VER005    NO.169
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 2_lane_2K60_300to300MHz_VER005    NO.170
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 4_lane_4K30_450to600MHz_VER005    NO.171
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 4_lane_4K30_300to450MHz_VER005    NO.172
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 4_lane_4K30_300to300MHz_VER005    NO.173
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 8_lane_4K60_450to600MHz_VER005    NO.174
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 8_lane_4K60_300to450MHz_VER005    NO.175
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 8_lane_4K60_300to300MHz_VER005    NO.176
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 16_lane_4K120_450to600MHz_VER005    NO.177
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 16_lane_4K120_300to450MHz_VER005    NO.178
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 16_lane_4K120_300to300MHz_VER005    NO.179
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 16_lane_4K144_480to720MHz_VER005    NO.180
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 16_lane_4K144_360to480MHz_VER005    NO.181
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 16_lane_4K144_360to360MHz_VER005    NO.182
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane 4K1k144 test_202.5to405MHz_VER005    NO.183
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane 4K1k144 test_202.5to202.5MHz_VER005    NO.184
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS 2bk_3pair 8bit_300to700MHz_VER005    NO.185
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS 2bk_3pair 8bit_300to300MHz_VER005    NO.186
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K1K144_CML_180to360MHz_VER005    NO.187
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K1K144_CML_180to180MHz_VER005    NO.188
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K1K144_CML_270to360MHz_VER005    NO.189
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K1K144_CML_180to270MHz_VER005    NO.190
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K1K144_CML_180to180MHz_VER005    NO.191
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K1K144_CML_180to360MHz_VER005    NO.192
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K1K144_CML_180to180MHz_VER005    NO.193
      //Address,Value,Mask
        {0x484600,0x1,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x500,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x10,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K1K144_LVDS_180to360MHz_VER005    NO.194
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28 8bit 12x1_4K1K144_LVDS_180to180MHz_VER005    NO.195
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K1K144_LVDS_270to360MHz_VER005    NO.196
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K1K144_LVDS_180to270MHz_VER005    NO.197
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 12x1_4K1K144_LVDS_180to180MHz_VER005    NO.198
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K1K144_LVDS_180to360MHz_VER005    NO.199
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24 10bit 16x1_4K1K144_LVDS_180to180MHz_VER005    NO.200
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x1,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K1K144_180to360MHz_VER005    NO.201
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 12x1_4K1K144_180to180MHz_VER005    NO.202
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K1K144_270to360MHz_VER005    NO.203
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K1K144_180to270MHz_VER005    NO.204
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 8bit 16x1_4K1K144_180to180MHz_VER005    NO.205
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 12x1_4K1K144_180to360MHz_VER005    NO.206
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 12x1_4K1K144_180to180MHz_VER005    NO.207
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K1K144_180to360MHz_VER005    NO.208
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T 10bit 16x1_4K1K144_180to180MHz_VER005    NO.209
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 8bit 12x1_4K1K144_180to360MHz_VER005    NO.210
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 8bit 12x1_4K1K144_180to180MHz_VER005    NO.211
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K1K144_270to360MHz_VER005    NO.212
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K1K144_180to270MHz_VER005    NO.213
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24 10bit 12x1_4K1K144_180to180MHz_VER005    NO.214
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x2,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K1K144_180to360MHz_VER005    NO.215
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 8bit 12x1_4K1K144_180to180MHz_VER005    NO.216
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K1K144_270to360MHz_VER005    NO.217
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K1K144_180to270MHz_VER005    NO.218
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_ISP 10bit 12x1_4K1K144_180to180MHz_VER005    NO.219
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K1K144_180to360MHz_VER005    NO.220
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 8bit 12x1_4K1K144_180to180MHz_VER005    NO.221
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K1K144_270to360MHz_VER005    NO.222
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K1K144_180to270MHz_VER005    NO.223
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI 10bit 12x1_4K1K144_180to180MHz_VER005    NO.224
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x3,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x1,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x8000,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane 4K1k144_180to360MHz_VER005    NO.225
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane 4K1k144_180to180MHz_VER005    NO.226
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 8_lane 4K1k144_240to360MHz_VER005    NO.227
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 8_lane 4K1k144_180to240MHz_VER005    NO.228
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 8bit 8_lane 4K1k144_180to180MHz_VER005    NO.229
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane 4K1k144 test_202.5to405MHz_VER005    NO.230
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1 10bit 8_lane 4K1k144 test_202.5to202.5MHz_VER005    NO.231
      //Address,Value,Mask
        {0x484600,0x0,Fld(1,13,AC_MSKW10)},//reg_gcr_en_cml
        {0x484600,0x0,Fld(2,14,AC_MSKW10)},//reg_gcr_vcm_sel
        {0x484620,0xFFFF,Fld(16,0,AC_MSKW10)},//reg_gcr_en_vby1_ch19_00
        {0x484604,0x1,Fld(1,8,AC_MSKW10)},//reg_gcr_en_reg
        {0x484604,0x0,Fld(1,0,AC_MSKW10)},//reg_pd_mod
        {0x484760,0x0,Fld(1,15,AC_MSKW10)},//reg_hw_rint_en
        {0x484618,0x0,Fld(16,0,AC_MSKW10)},//reg_gcr_en_rint_ch19_00
        {0x484C38,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[15:0]
        {0x484C3C,0x0,Fld(16,0,AC_MSKW10)},//reg_test_mod[31:16]
        {0x484604,0x0,Fld(1,1,AC_MSKW10)},//reg_pd_xtalrx
    },

};

TBLStruct MPLLSettingTBL_VER005[PNL_NUM_VER005][MPLL_REG_NUM_VER005]=
{
    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005    NO.0
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005    NO.1
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005    NO.2
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005    NO.3
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005    NO.4
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005    NO.5
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005    NO.6
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005    NO.7
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005    NO.8
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005    NO.9
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005    NO.10
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005    NO.11
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_360to600MHz_VER005    NO.12
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to360MHz_VER005    NO.13
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to300MHz_VER005    NO.14
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_450to600MHz_VER005    NO.15
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to450MHz_VER005    NO.16
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to300MHz_VER005    NO.17
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to600MHz_VER005    NO.18
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to300MHz_VER005    NO.19
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_360to600MHz_VER005    NO.20
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to360MHz_VER005    NO.21
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to300MHz_VER005    NO.22
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_450to600MHz_VER005    NO.23
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to450MHz_VER005    NO.24
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to300MHz_VER005    NO.25
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to720MHz_VER005    NO.26
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to360MHz_VER005    NO.27
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_480to720MHz_VER005    NO.28
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to480MHz_VER005    NO.29
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to360MHz_VER005    NO.30
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to600MHz_VER005    NO.31
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to300MHz_VER005    NO.32
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to600MHz_VER005    NO.33
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to300MHz_VER005    NO.34
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to600MHz_VER005    NO.35
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to300MHz_VER005    NO.36
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_400to600MHz_VER005    NO.37
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to400MHz_VER005    NO.38
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to300MHz_VER005    NO.39
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_360to600MHz_VER005    NO.40
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to360MHz_VER005    NO.41
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to300MHz_VER005    NO.42
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_450to600MHz_VER005    NO.43
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to450MHz_VER005    NO.44
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to300MHz_VER005    NO.45
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.46
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.47
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_360to600MHz_VER005    NO.48
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to360MHz_VER005    NO.49
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.50
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_450to600MHz_VER005    NO.51
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to450MHz_VER005    NO.52
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.53
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to720MHz_VER005    NO.54
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to360MHz_VER005    NO.55
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_480to720MHz_VER005    NO.56
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to480MHz_VER005    NO.57
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to360MHz_VER005    NO.58
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.59
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.60
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to600MHz_VER005    NO.61
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to300MHz_VER005    NO.62
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to600MHz_VER005    NO.63
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.64
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_400to600MHz_VER005    NO.65
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to400MHz_VER005    NO.66
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.67
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_400to600MHz_VER005    NO.68
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to400MHz_VER005    NO.69
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to300MHz_VER005    NO.70
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_450to600MHz_VER005    NO.71
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to450MHz_VER005    NO.72
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to300MHz_VER005    NO.73
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to600MHz_VER005    NO.74
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to300MHz_VER005    NO.75
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_450to600MHz_VER005    NO.76
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to450MHz_VER005    NO.77
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to300MHz_VER005    NO.78
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_400to600MHz_VER005    NO.79
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to400MHz_VER005    NO.80
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to300MHz_VER005    NO.81
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to720MHz_VER005    NO.82
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to360MHz_VER005    NO.83
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to600MHz_VER005    NO.84
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to300MHz_VER005    NO.85
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_540to720MHz_VER005    NO.86
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to540MHz_VER005    NO.87
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to360MHz_VER005    NO.88
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to600MHz_VER005    NO.89
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to300MHz_VER005    NO.90
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to600MHz_VER005    NO.91
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to300MHz_VER005    NO.92
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to600MHz_VER005    NO.93
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to300MHz_VER005    NO.94
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_400to600MHz_VER005    NO.95
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to400MHz_VER005    NO.96
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to300MHz_VER005    NO.97
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_400to600MHz_VER005    NO.98
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to400MHz_VER005    NO.99
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to300MHz_VER005    NO.100
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_450to600MHz_VER005    NO.101
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to450MHz_VER005    NO.102
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to300MHz_VER005    NO.103
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to600MHz_VER005    NO.104
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to300MHz_VER005    NO.105
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_400to600MHz_VER005    NO.106
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to400MHz_VER005    NO.107
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to300MHz_VER005    NO.108
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to720MHz_VER005    NO.109
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to360MHz_VER005    NO.110
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to600MHz_VER005    NO.111
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to300MHz_VER005    NO.112
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to600MHz_VER005    NO.113
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to300MHz_VER005    NO.114
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_400to600MHz_VER005    NO.115
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to400MHz_VER005    NO.116
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to300MHz_VER005    NO.117
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to600MHz_VER005    NO.118
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to300MHz_VER005    NO.119
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_450to600MHz_VER005    NO.120
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to450MHz_VER005    NO.121
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to300MHz_VER005    NO.122
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to600MHz_VER005    NO.123
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to300MHz_VER005    NO.124
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_400to600MHz_VER005    NO.125
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to400MHz_VER005    NO.126
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to300MHz_VER005    NO.127
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to720MHz_VER005    NO.128
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to360MHz_VER005    NO.129
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to600MHz_VER005    NO.130
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to300MHz_VER005    NO.131
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to600MHz_VER005    NO.132
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to300MHz_VER005    NO.133
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to600MHz_VER005    NO.134
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to300MHz_VER005    NO.135
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to720MHz_VER005    NO.136
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to360MHz_VER005    NO.137
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to600MHz_VER005    NO.138
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to300MHz_VER005    NO.139
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to600MHz_VER005    NO.140
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to300MHz_VER005    NO.141
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_450to600MHz_VER005    NO.142
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to450MHz_VER005    NO.143
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to300MHz_VER005    NO.144
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to600MHz_VER005    NO.145
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to300MHz_VER005    NO.146
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to600MHz_VER005    NO.147
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to300MHz_VER005    NO.148
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to720MHz_VER005    NO.149
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to360MHz_VER005    NO.150
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_360to600MHz_VER005    NO.151
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to360MHz_VER005    NO.152
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to300MHz_VER005    NO.153
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to600MHz_VER005    NO.154
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to300MHz_VER005    NO.155
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to600MHz_VER005    NO.156
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to300MHz_VER005    NO.157
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to600MHz_VER005    NO.158
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to300MHz_VER005    NO.159
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to600MHz_VER005    NO.160
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to300MHz_VER005    NO.161
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to600MHz_VER005    NO.162
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to300MHz_VER005    NO.163
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to600MHz_VER005    NO.164
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to300MHz_VER005    NO.165
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to720MHz_VER005    NO.166
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to360MHz_VER005    NO.167
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_450to600MHz_VER005    NO.168
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to450MHz_VER005    NO.169
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to300MHz_VER005    NO.170
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_450to600MHz_VER005    NO.171
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to450MHz_VER005    NO.172
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to300MHz_VER005    NO.173
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_450to600MHz_VER005    NO.174
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to450MHz_VER005    NO.175
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to300MHz_VER005    NO.176
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_450to600MHz_VER005    NO.177
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to450MHz_VER005    NO.178
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to300MHz_VER005    NO.179
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_480to720MHz_VER005    NO.180
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to480MHz_VER005    NO.181
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to360MHz_VER005    NO.182
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to405MHz_VER005    NO.183
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to202MHz_VER005    NO.184
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to700MHz_VER005    NO.185
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER005    NO.186
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER005    NO.187
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.188
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_270to360MHz_VER005    NO.189
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to270MHz_VER005    NO.190
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.191
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to360MHz_VER005    NO.192
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to180MHz_VER005    NO.193
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER005    NO.194
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.195
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_270to360MHz_VER005    NO.196
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to270MHz_VER005    NO.197
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.198
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to360MHz_VER005    NO.199
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to180MHz_VER005    NO.200
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER005    NO.201
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER005    NO.202
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_270to360MHz_VER005    NO.203
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to270MHz_VER005    NO.204
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to180MHz_VER005    NO.205
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to360MHz_VER005    NO.206
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER005    NO.207
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to360MHz_VER005    NO.208
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to180MHz_VER005    NO.209
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to360MHz_VER005    NO.210
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to180MHz_VER005    NO.211
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_270to360MHz_VER005    NO.212
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to270MHz_VER005    NO.213
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER005    NO.214
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER005    NO.215
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER005    NO.216
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_270to360MHz_VER005    NO.217
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to270MHz_VER005    NO.218
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER005    NO.219
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER005    NO.220
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER005    NO.221
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_270to360MHz_VER005    NO.222
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to270MHz_VER005    NO.223
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER005    NO.224
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to360MHz_VER005    NO.225
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to180MHz_VER005    NO.226
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_240to360MHz_VER005    NO.227
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to240MHz_VER005    NO.228
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to180MHz_VER005    NO.229
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to405MHz_VER005    NO.230
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

    { //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to202MHz_VER005    NO.231
      //Address,Value,Mask
        {0x4861BC,0x0,Fld(4,12,AC_MSKW10)},//reg_gcr_mpll_ictrl
        {0x4861B4,0x1,Fld(2,0,AC_MSKW10)},//reg_gcr_mpll_input_div
        {0x4861B4,0x1,Fld(2,6,AC_MSKW10)},//reg_gcr_mpll_loop_div_first
        {0x4861B4,0x36,Fld(8,8,AC_MSKW10)},//reg_gcr_mpll_loop_div_second
        {0x4861BC,0x4,Fld(3,0,AC_MSKW10)},//reg_gcr_mpll_output_div
        {0x4861B8,0x431,Fld(16,0,AC_MSKW10)},//reg_mpll_test
        {0x4861A8,0x0,Fld(1,2,AC_MSKW10)},//reg_mpll_vco_bypass
        {0x4861A8,0x0,Fld(1,1,AC_MSKW10)},//reg_mpll_cp_hbw
    },

};
uint16_t lpll_LoopGain_VER005[PNL_NUM_VER005]=
{
    24,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005    NO.0
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005    NO.1
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005    NO.2
    24,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005    NO.3
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005    NO.4
    16,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005    NO.5
    24,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005    NO.6
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005    NO.7
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005    NO.8
    24,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005    NO.9
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005    NO.10
    16,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005    NO.11
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_360to600MHz_VER005    NO.12
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to360MHz_VER005    NO.13
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to300MHz_VER005    NO.14
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_450to600MHz_VER005    NO.15
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to450MHz_VER005    NO.16
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to300MHz_VER005    NO.17
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to600MHz_VER005    NO.18
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to300MHz_VER005    NO.19
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_360to600MHz_VER005    NO.20
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to360MHz_VER005    NO.21
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to300MHz_VER005    NO.22
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_450to600MHz_VER005    NO.23
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to450MHz_VER005    NO.24
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to300MHz_VER005    NO.25
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to720MHz_VER005    NO.26
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to360MHz_VER005    NO.27
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_480to720MHz_VER005    NO.28
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to480MHz_VER005    NO.29
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to360MHz_VER005    NO.30
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to600MHz_VER005    NO.31
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to300MHz_VER005    NO.32
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to600MHz_VER005    NO.33
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to300MHz_VER005    NO.34
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to600MHz_VER005    NO.35
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to300MHz_VER005    NO.36
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_400to600MHz_VER005    NO.37
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to400MHz_VER005    NO.38
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to300MHz_VER005    NO.39
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_360to600MHz_VER005    NO.40
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to360MHz_VER005    NO.41
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to300MHz_VER005    NO.42
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_450to600MHz_VER005    NO.43
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to450MHz_VER005    NO.44
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to300MHz_VER005    NO.45
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.46
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.47
    18,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_360to600MHz_VER005    NO.48
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to360MHz_VER005    NO.49
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.50
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_450to600MHz_VER005    NO.51
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to450MHz_VER005    NO.52
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.53
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to720MHz_VER005    NO.54
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to360MHz_VER005    NO.55
    24,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_480to720MHz_VER005    NO.56
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to480MHz_VER005    NO.57
    16,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to360MHz_VER005    NO.58
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.59
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.60
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to600MHz_VER005    NO.61
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to300MHz_VER005    NO.62
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to600MHz_VER005    NO.63
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.64
    8,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_400to600MHz_VER005    NO.65
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to400MHz_VER005    NO.66
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.67
    54,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_400to600MHz_VER005    NO.68
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to400MHz_VER005    NO.69
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to300MHz_VER005    NO.70
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_450to600MHz_VER005    NO.71
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to450MHz_VER005    NO.72
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to300MHz_VER005    NO.73
    54,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to600MHz_VER005    NO.74
    54,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to300MHz_VER005    NO.75
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_450to600MHz_VER005    NO.76
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to450MHz_VER005    NO.77
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to300MHz_VER005    NO.78
    54,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_400to600MHz_VER005    NO.79
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to400MHz_VER005    NO.80
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to300MHz_VER005    NO.81
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to720MHz_VER005    NO.82
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to360MHz_VER005    NO.83
    12,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to600MHz_VER005    NO.84
    12,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to300MHz_VER005    NO.85
    18,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_540to720MHz_VER005    NO.86
    12,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to540MHz_VER005    NO.87
    12,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to360MHz_VER005    NO.88
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to600MHz_VER005    NO.89
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to300MHz_VER005    NO.90
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to600MHz_VER005    NO.91
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to300MHz_VER005    NO.92
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to600MHz_VER005    NO.93
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to300MHz_VER005    NO.94
    72,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_400to600MHz_VER005    NO.95
    48,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to400MHz_VER005    NO.96
    48,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to300MHz_VER005    NO.97
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_400to600MHz_VER005    NO.98
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to400MHz_VER005    NO.99
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to300MHz_VER005    NO.100
    32,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_450to600MHz_VER005    NO.101
    64,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to450MHz_VER005    NO.102
    64,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to300MHz_VER005    NO.103
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to600MHz_VER005    NO.104
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to300MHz_VER005    NO.105
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_400to600MHz_VER005    NO.106
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to400MHz_VER005    NO.107
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to300MHz_VER005    NO.108
    32,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to720MHz_VER005    NO.109
    32,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to360MHz_VER005    NO.110
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to600MHz_VER005    NO.111
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to300MHz_VER005    NO.112
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to600MHz_VER005    NO.113
    8,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to300MHz_VER005    NO.114
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_400to600MHz_VER005    NO.115
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to400MHz_VER005    NO.116
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to300MHz_VER005    NO.117
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to600MHz_VER005    NO.118
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to300MHz_VER005    NO.119
    32,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_450to600MHz_VER005    NO.120
    64,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to450MHz_VER005    NO.121
    64,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to300MHz_VER005    NO.122
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to600MHz_VER005    NO.123
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to300MHz_VER005    NO.124
    8,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_400to600MHz_VER005    NO.125
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to400MHz_VER005    NO.126
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to300MHz_VER005    NO.127
    32,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to720MHz_VER005    NO.128
    32,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to360MHz_VER005    NO.129
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to600MHz_VER005    NO.130
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to300MHz_VER005    NO.131
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to600MHz_VER005    NO.132
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to300MHz_VER005    NO.133
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to600MHz_VER005    NO.134
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to300MHz_VER005    NO.135
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to720MHz_VER005    NO.136
    128,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to360MHz_VER005    NO.137
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to600MHz_VER005    NO.138
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to300MHz_VER005    NO.139
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to600MHz_VER005    NO.140
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to300MHz_VER005    NO.141
    16,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_450to600MHz_VER005    NO.142
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to450MHz_VER005    NO.143
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to300MHz_VER005    NO.144
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to600MHz_VER005    NO.145
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to300MHz_VER005    NO.146
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to600MHz_VER005    NO.147
    12,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to300MHz_VER005    NO.148
    16,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to720MHz_VER005    NO.149
    16,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to360MHz_VER005    NO.150
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_360to600MHz_VER005    NO.151
    128,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to360MHz_VER005    NO.152
    128,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to300MHz_VER005    NO.153
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to600MHz_VER005    NO.154
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to300MHz_VER005    NO.155
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to600MHz_VER005    NO.156
    64,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to300MHz_VER005    NO.157
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to600MHz_VER005    NO.158
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to300MHz_VER005    NO.159
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to600MHz_VER005    NO.160
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to300MHz_VER005    NO.161
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to600MHz_VER005    NO.162
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to300MHz_VER005    NO.163
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to600MHz_VER005    NO.164
    12,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to300MHz_VER005    NO.165
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to720MHz_VER005    NO.166
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to360MHz_VER005    NO.167
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_450to600MHz_VER005    NO.168
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to450MHz_VER005    NO.169
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to300MHz_VER005    NO.170
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_450to600MHz_VER005    NO.171
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to450MHz_VER005    NO.172
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to300MHz_VER005    NO.173
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_450to600MHz_VER005    NO.174
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to450MHz_VER005    NO.175
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to300MHz_VER005    NO.176
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_450to600MHz_VER005    NO.177
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to450MHz_VER005    NO.178
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to300MHz_VER005    NO.179
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_480to720MHz_VER005    NO.180
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to480MHz_VER005    NO.181
    32,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to360MHz_VER005    NO.182
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to405MHz_VER005    NO.183
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to202MHz_VER005    NO.184
    6,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to700MHz_VER005    NO.185
    6,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER005    NO.186
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER005    NO.187
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.188
    2,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_270to360MHz_VER005    NO.189
    4,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to270MHz_VER005    NO.190
    4,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.191
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to360MHz_VER005    NO.192
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to180MHz_VER005    NO.193
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER005    NO.194
    12,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.195
    2,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_270to360MHz_VER005    NO.196
    4,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to270MHz_VER005    NO.197
    4,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.198
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to360MHz_VER005    NO.199
    16,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to180MHz_VER005    NO.200
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER005    NO.201
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER005    NO.202
    9,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_270to360MHz_VER005    NO.203
    6,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to270MHz_VER005    NO.204
    6,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to180MHz_VER005    NO.205
    36,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to360MHz_VER005    NO.206
    36,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER005    NO.207
    36,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to360MHz_VER005    NO.208
    36,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to180MHz_VER005    NO.209
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to360MHz_VER005    NO.210
    16,           //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to180MHz_VER005    NO.211
    2,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_270to360MHz_VER005    NO.212
    4,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to270MHz_VER005    NO.213
    4,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER005    NO.214
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER005    NO.215
    16,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER005    NO.216
    32,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_270to360MHz_VER005    NO.217
    64,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to270MHz_VER005    NO.218
    64,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER005    NO.219
    8,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER005    NO.220
    8,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER005    NO.221
    48,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_270to360MHz_VER005    NO.222
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to270MHz_VER005    NO.223
    32,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER005    NO.224
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to360MHz_VER005    NO.225
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to180MHz_VER005    NO.226
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_240to360MHz_VER005    NO.227
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to240MHz_VER005    NO.228
    16,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to180MHz_VER005    NO.229
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to405MHz_VER005    NO.230
    8,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to202MHz_VER005    NO.231
};
uint16_t lpll_LoopDiv_VER005[PNL_NUM_VER005]=
{
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_450to600MHz_VER005    NO.0
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to450MHz_VER005    NO.1
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_1ch_300to300MHz_VER005    NO.2
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_450to600MHz_VER005    NO.3
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to450MHz_VER005    NO.4
    7,           //E_PNL_SUPPORTED_LPLL_LVDS_2ch_300to300MHz_VER005    NO.5
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_450to600MHz_VER005    NO.6
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to450MHz_VER005    NO.7
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_1ch_300to300MHz_VER005    NO.8
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_450to600MHz_VER005    NO.9
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to450MHz_VER005    NO.10
    7,           //E_PNL_SUPPORTED_LPLL_HS_LVDS_2ch_300to300MHz_VER005    NO.11
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_360to600MHz_VER005    NO.12
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to360MHz_VER005    NO.13
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_CML_300to300MHz_VER005    NO.14
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_450to600MHz_VER005    NO.15
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to450MHz_VER005    NO.16
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_CML_300to300MHz_VER005    NO.17
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to600MHz_VER005    NO.18
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_CML_300to300MHz_VER005    NO.19
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_360to600MHz_VER005    NO.20
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to360MHz_VER005    NO.21
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_CML_300to300MHz_VER005    NO.22
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_450to600MHz_VER005    NO.23
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to450MHz_VER005    NO.24
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_CML_300to300MHz_VER005    NO.25
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to720MHz_VER005    NO.26
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_CML_360to360MHz_VER005    NO.27
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_480to720MHz_VER005    NO.28
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to480MHz_VER005    NO.29
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_CML_360to360MHz_VER005    NO.30
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to600MHz_VER005    NO.31
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_CML_300to300MHz_VER005    NO.32
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to600MHz_VER005    NO.33
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_CML_300to300MHz_VER005    NO.34
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to600MHz_VER005    NO.35
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_CML_300to300MHz_VER005    NO.36
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_400to600MHz_VER005    NO.37
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to400MHz_VER005    NO.38
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_CML_300to300MHz_VER005    NO.39
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_360to600MHz_VER005    NO.40
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to360MHz_VER005    NO.41
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6x1_4K60_LVDS_300to300MHz_VER005    NO.42
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_450to600MHz_VER005    NO.43
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to450MHz_VER005    NO.44
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8x1_4K60_LVDS_300to300MHz_VER005    NO.45
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.46
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.47
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_360to600MHz_VER005    NO.48
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to360MHz_VER005    NO.49
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.50
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_450to600MHz_VER005    NO.51
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to450MHz_VER005    NO.52
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.53
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to720MHz_VER005    NO.54
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K144_LVDS_360to360MHz_VER005    NO.55
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_480to720MHz_VER005    NO.56
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to480MHz_VER005    NO.57
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_16x1_4K144_LVDS_360to360MHz_VER005    NO.58
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to600MHz_VER005    NO.59
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K60_LVDS_300to300MHz_VER005    NO.60
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to600MHz_VER005    NO.61
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K60_LVDS_300to300MHz_VER005    NO.62
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to600MHz_VER005    NO.63
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K120_LVDS_300to300MHz_VER005    NO.64
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_400to600MHz_VER005    NO.65
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to400MHz_VER005    NO.66
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K120_LVDS_300to300MHz_VER005    NO.67
    20,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_400to600MHz_VER005    NO.68
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to400MHz_VER005    NO.69
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_6x1_4K60_300to300MHz_VER005    NO.70
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_450to600MHz_VER005    NO.71
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to450MHz_VER005    NO.72
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_8x1_4K60_300to300MHz_VER005    NO.73
    20,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to600MHz_VER005    NO.74
    20,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K60_300to300MHz_VER005    NO.75
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_450to600MHz_VER005    NO.76
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to450MHz_VER005    NO.77
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K60_300to300MHz_VER005    NO.78
    20,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_400to600MHz_VER005    NO.79
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to400MHz_VER005    NO.80
    10,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K120_300to300MHz_VER005    NO.81
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to720MHz_VER005    NO.82
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K144_360to360MHz_VER005    NO.83
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to600MHz_VER005    NO.84
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K120_300to300MHz_VER005    NO.85
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_540to720MHz_VER005    NO.86
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to540MHz_VER005    NO.87
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K144_360to360MHz_VER005    NO.88
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to600MHz_VER005    NO.89
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K60_300to300MHz_VER005    NO.90
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to600MHz_VER005    NO.91
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K60_300to300MHz_VER005    NO.92
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to600MHz_VER005    NO.93
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K120_300to300MHz_VER005    NO.94
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_400to600MHz_VER005    NO.95
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to400MHz_VER005    NO.96
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K120_300to300MHz_VER005    NO.97
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_400to600MHz_VER005    NO.98
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to400MHz_VER005    NO.99
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_6x1_4K60_300to300MHz_VER005    NO.100
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_450to600MHz_VER005    NO.101
    27,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to450MHz_VER005    NO.102
    27,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_8x1_4K60_300to300MHz_VER005    NO.103
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to600MHz_VER005    NO.104
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K60_300to300MHz_VER005    NO.105
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_400to600MHz_VER005    NO.106
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to400MHz_VER005    NO.107
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K120_300to300MHz_VER005    NO.108
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to720MHz_VER005    NO.109
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_27_8bit_12x1_4K144_360to360MHz_VER005    NO.110
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to600MHz_VER005    NO.111
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K60_300to300MHz_VER005    NO.112
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to600MHz_VER005    NO.113
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K120_300to300MHz_VER005    NO.114
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_400to600MHz_VER005    NO.115
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to400MHz_VER005    NO.116
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x1_4K60_300to300MHz_VER005    NO.117
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to600MHz_VER005    NO.118
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_6x2_4K60_300to300MHz_VER005    NO.119
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_450to600MHz_VER005    NO.120
    27,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to450MHz_VER005    NO.121
    27,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_8x1_4K60_300to300MHz_VER005    NO.122
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to600MHz_VER005    NO.123
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K60_300to300MHz_VER005    NO.124
    3,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_400to600MHz_VER005    NO.125
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to400MHz_VER005    NO.126
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K120_300to300MHz_VER005    NO.127
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to720MHz_VER005    NO.128
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K144_360to360MHz_VER005    NO.129
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to600MHz_VER005    NO.130
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_6x2_4K60_300to300MHz_VER005    NO.131
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to600MHz_VER005    NO.132
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K60_300to300MHz_VER005    NO.133
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to600MHz_VER005    NO.134
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K120_300to300MHz_VER005    NO.135
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to720MHz_VER005    NO.136
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K144_360to360MHz_VER005    NO.137
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to600MHz_VER005    NO.138
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x1_4K60_300to300MHz_VER005    NO.139
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to600MHz_VER005    NO.140
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_6x2_4K60_300to300MHz_VER005    NO.141
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_450to600MHz_VER005    NO.142
    15,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to450MHz_VER005    NO.143
    15,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_8x1_4K60_300to300MHz_VER005    NO.144
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to600MHz_VER005    NO.145
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K60_300to300MHz_VER005    NO.146
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to600MHz_VER005    NO.147
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K120_300to300MHz_VER005    NO.148
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to720MHz_VER005    NO.149
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K144_360to360MHz_VER005    NO.150
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_360to600MHz_VER005    NO.151
    75,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to360MHz_VER005    NO.152
    75,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_8x1_4K60_300to300MHz_VER005    NO.153
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to600MHz_VER005    NO.154
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K60_300to300MHz_VER005    NO.155
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to600MHz_VER005    NO.156
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K120_300to300MHz_VER005    NO.157
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to600MHz_VER005    NO.158
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_2_lane_2K60_300to300MHz_VER005    NO.159
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to600MHz_VER005    NO.160
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_4_lane_4K30_300to300MHz_VER005    NO.161
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to600MHz_VER005    NO.162
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K60_300to300MHz_VER005    NO.163
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to600MHz_VER005    NO.164
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K120_300to300MHz_VER005    NO.165
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to720MHz_VER005    NO.166
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_16_lane_4K144_360to360MHz_VER005    NO.167
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_450to600MHz_VER005    NO.168
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to450MHz_VER005    NO.169
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_2_lane_2K60_300to300MHz_VER005    NO.170
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_450to600MHz_VER005    NO.171
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to450MHz_VER005    NO.172
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_4_lane_4K30_300to300MHz_VER005    NO.173
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_450to600MHz_VER005    NO.174
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to450MHz_VER005    NO.175
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K60_300to300MHz_VER005    NO.176
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_450to600MHz_VER005    NO.177
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to450MHz_VER005    NO.178
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K120_300to300MHz_VER005    NO.179
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_480to720MHz_VER005    NO.180
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to480MHz_VER005    NO.181
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_16_lane_4K144_360to360MHz_VER005    NO.182
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to405MHz_VER005    NO.183
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test1_202to202MHz_VER005    NO.184
    2,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to700MHz_VER005    NO.185
    2,           //E_PNL_SUPPORTED_LPLL_MINILVDS_2bk_3pair_8bit_300to300MHz_VER005    NO.186
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to360MHz_VER005    NO.187
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.188
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_270to360MHz_VER005    NO.189
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to270MHz_VER005    NO.190
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_CML_180to180MHz_VER005    NO.191
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to360MHz_VER005    NO.192
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_CML_180to180MHz_VER005    NO.193
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to360MHz_VER005    NO.194
    7,           //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.195
    1,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_270to360MHz_VER005    NO.196
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to270MHz_VER005    NO.197
    3,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_12x1_4K1K144_LVDS_180to180MHz_VER005    NO.198
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to360MHz_VER005    NO.199
    9,           //E_PNL_SUPPORTED_LPLL_EPI_24_10bit_16x1_4K1K144_LVDS_180to180MHz_VER005    NO.200
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to360MHz_VER005    NO.201
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_12x1_4K1K144_180to180MHz_VER005    NO.202
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_270to360MHz_VER005    NO.203
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to270MHz_VER005    NO.204
    5,           //E_PNL_SUPPORTED_LPLL_USI_T_8bit_16x1_4K1K144_180to180MHz_VER005    NO.205
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to360MHz_VER005    NO.206
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_12x1_4K1K144_180to180MHz_VER005    NO.207
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to360MHz_VER005    NO.208
    25,           //E_PNL_SUPPORTED_LPLL_USI_T_10bit_16x1_4K1K144_180to180MHz_VER005    NO.209
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to360MHz_VER005    NO.210
    9,           //E_PNL_SUPPORTED_LPLL_CMPI_24_8bit_12x1_4K1K144_180to180MHz_VER005    NO.211
    1,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_270to360MHz_VER005    NO.212
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to270MHz_VER005    NO.213
    3,           //E_PNL_SUPPORTED_LPLL_CMPI_24_10bit_12x1_4K1K144_180to180MHz_VER005    NO.214
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to360MHz_VER005    NO.215
    9,           //E_PNL_SUPPORTED_LPLL_ISP_8bit_12x1_4K1K144_180to180MHz_VER005    NO.216
    15,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_270to360MHz_VER005    NO.217
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to270MHz_VER005    NO.218
    45,           //E_PNL_SUPPORTED_LPLL_ISP_10bit_12x1_4K1K144_180to180MHz_VER005    NO.219
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to360MHz_VER005    NO.220
    5,           //E_PNL_SUPPORTED_LPLL_CHPI_8bit_12x1_4K1K144_180to180MHz_VER005    NO.221
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_270to360MHz_VER005    NO.222
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to270MHz_VER005    NO.223
    25,           //E_PNL_SUPPORTED_LPLL_CHPI_10bit_12x1_4K1K144_180to180MHz_VER005    NO.224
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to360MHz_VER005    NO.225
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_180to180MHz_VER005    NO.226
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_240to360MHz_VER005    NO.227
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to240MHz_VER005    NO.228
    15,           //E_PNL_SUPPORTED_LPLL_Vx1_8bit_8_lane_4K1k144_180to180MHz_VER005    NO.229
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to405MHz_VER005    NO.230
    5,           //E_PNL_SUPPORTED_LPLL_Vx1_10bit_8_lane_4K1k144_test2_202to202MHz_VER005    NO.231
};

//======version5 end======
#endif //_LPLL_TBL_H_
