/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * MediaTek Inc. (C) 2018. All rights reserved.
 *
 * Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein is
 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
 * the prior written permission of MediaTek inc. and/or its licensors, any
 * reproduction, modification, use or disclosure of MediaTek Software, and
 * information contained herein, in whole or in part, shall be strictly
 * prohibited.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
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 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 *
 * The following software/firmware and/or related documentation ("MediaTek
 * Software") have been modified by MediaTek Inc. All revisions are subject to
 * any receiver's applicable license agreements with MediaTek Inc.
 */

#ifndef _MTK_DTV_PWM_PM_H_
#define _MTK_DTV_PWM_PM_H_

////////////////////////////////////////////////////////////////////////////////
// Header Files
////////////////////////////////////////////////////////////////////////////////

//############################
//
//PWM pm control registers
//
//############################
#define REG_PM_PWM0_IS_GPIO         (0x1C)	//bit5, 0: PWM_PM0, 1: GPIO
#define REG_PM_PWM0_IS_GPIO_MASK    BIT(5)

#define REG_PWM0_PM_SW_RST          (0x31)	//bit10
#define REG_PWM0_PM_SW_RST_MASK     BIT(10)

#define REG_PWM0_PM_DIV             (0x68)	//bit0~7
#define REG_PWM0_PM_DUTY            (0x69)	//bit0~15
#define REG_PWM0_PM_PERIOD          (0x6A)	//bit0~15
#define REG_PWM0_PM_POLARITY        (0x6B)	//bit0
#define REG_PWM0_PM_DBEN            (0x6B)	//bit1

#define REG_GPIO_IS_PWM1            (0x76)	//bit11~12

#define REG_PWM1_PM_DIV             (0x78)	//bit0~7
#define REG_PWM1_PM_DUTY            (0x79)	//bit0~15
#define REG_PWM1_PM_PERIOD          (0x7A)	//bit0~15
#define REG_PWM1_PM_POLARITY        (0x7B)	//bit0
#define REG_PWM1_PM_DBEN            (0x7B)	//bit1

#define REG_PWM_PM_POLARITY_MASK    BIT(0)
#define REG_PWM_PM_DBEN_MASK        BIT(1)

#define REG_PWM1_PM_SW_RST          (0x7B)	//bit8
#define REG_PWM1_PM_SW_RST_MASK     BIT(8)

#endif // _MTK_DTV_PWM_PM_H_
