#define DISP_MISC_V004 0x484200

//Page DISP_MISC_V004
#define REG_0100_DISP_MISC_V004 (DISP_MISC_V004 + 0x100)
	#define REG_0100_DISP_MISC_V004_REG_ODCLK_ROOT_EN_0100 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0100_DISP_MISC_V004_REG_V1_MOD_SR_WCLK_GATE_DISABLE_0100 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0100_DISP_MISC_V004_REG_MOD_CH40TO63_EN_0100 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0104_DISP_MISC_V004 (DISP_MISC_V004 + 0x104)
	#define REG_0104_DISP_MISC_V004_REG_CLK_SHIFT_0104 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_0108_DISP_MISC_V004 (DISP_MISC_V004 + 0x108)
	#define REG_0108_DISP_MISC_V004_REG_SERI_CH_CKEN_BITMAP_0_0108 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_010C_DISP_MISC_V004 (DISP_MISC_V004 + 0x10C)
	#define REG_010C_DISP_MISC_V004_REG_SERI_CH_CKEN_BITMAP_1_010C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0110_DISP_MISC_V004 (DISP_MISC_V004 + 0x110)
	#define REG_0110_DISP_MISC_V004_REG_SERI_CH_CKEN_BITMAP_2_0110 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0140_DISP_MISC_V004 (DISP_MISC_V004 + 0x140)
	#define REG_0140_DISP_MISC_V004_REG_TCON_CLKEN_BITMAP_0140 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_01E0_DISP_MISC_V004 (DISP_MISC_V004 + 0x1E0)
	#define REG_01E0_DISP_MISC_V004_REG_TESTBUS_MUX_01E0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_01E4_DISP_MISC_V004 (DISP_MISC_V004 + 0x1E4)
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL00_01E4 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL01_01E4 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL02_01E4 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL03_01E4 Fld(2,6,AC_MSKB0)//[7:6]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL04_01E4 Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL05_01E4 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL06_01E4 Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_01E4_DISP_MISC_V004_REG_TESTBUS_BIT_SEL07_01E4 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01E8_DISP_MISC_V004 (DISP_MISC_V004 + 0x1E8)
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL08_01E8 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL09_01E8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL10_01E8 Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL11_01E8 Fld(2,6,AC_MSKB0)//[7:6]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL12_01E8 Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL13_01E8 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL14_01E8 Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_01E8_DISP_MISC_V004_REG_TESTBUS_BIT_SEL15_01E8 Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01EC_DISP_MISC_V004 (DISP_MISC_V004 + 0x1EC)
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL16_01EC Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL17_01EC Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL18_01EC Fld(2,4,AC_MSKB0)//[5:4]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL19_01EC Fld(2,6,AC_MSKB0)//[7:6]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL20_01EC Fld(2,8,AC_MSKB1)//[9:8]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL21_01EC Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL22_01EC Fld(2,12,AC_MSKB1)//[13:12]
	#define REG_01EC_DISP_MISC_V004_REG_TESTBUS_BIT_SEL23_01EC Fld(2,14,AC_MSKB1)//[15:14]
#define REG_01F0_DISP_MISC_V004 (DISP_MISC_V004 + 0x1F0)
	#define REG_01F0_DISP_MISC_V004_REG_TESTBUS_CONT_DE_01F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_01FC_DISP_MISC_V004 (DISP_MISC_V004 + 0x1FC)
	#define REG_01FC_DISP_MISC_V004_REG_DISP_MISC_V004_DUMMY_01FC Fld(16,0,AC_FULLW10)//[15:0]
