#ifndef _TRIGGER_GEN_A3A5_H
#define _TRIGGER_GEN_A3A5_H

#define TRIGGER_GEN_BKA3A5 0x01474A00

//Page TRIGGER_GEN_BKA3A5
#define REG_0004_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x004)
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_INPUT_SRC_SEL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_COMMON_TRIG_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_TRIG_GEN_SEL_SEP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UP_TRIG_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_DS_TRIG_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_ML_TRIG_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_VS_TRIG_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_STR_TRIG_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_SW_IRQ_TRIG_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0004_TRIGGER_GEN_BKA3A5_REG_OP1_PQ_IRQ_TRIG_SEL Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0008_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x008)
    #define REG_0008_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UP_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_000C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x00C)
    #define REG_000C_TRIGGER_GEN_BKA3A5_REG_OP1_DS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0010_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x010)
    #define REG_0010_TRIGGER_GEN_BKA3A5_REG_OP1_ML_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0014_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x014)
    #define REG_0014_TRIGGER_GEN_BKA3A5_REG_OP1_VS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0018_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x018)
    #define REG_0018_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_001C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x01C)
    #define REG_001C_TRIGGER_GEN_BKA3A5_REG_OP1_STR_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0020_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x020)
    #define REG_0020_TRIGGER_GEN_BKA3A5_REG_OP1_SW_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0024_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x024)
    #define REG_0024_TRIGGER_GEN_BKA3A5_REG_OP1_PQ_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0028_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x028)
    #define REG_0028_TRIGGER_GEN_BKA3A5_REG_OP1_DUMMY0_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_002C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x02C)
    #define REG_002C_TRIGGER_GEN_BKA3A5_REG_OP1_DUMMY1_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0038_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x038)
    #define REG_0038_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_003C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x03C)
    #define REG_003C_TRIGGER_GEN_BKA3A5_REG_OP1_VS_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0040_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x040)
    #define REG_0040_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_004C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x04C)
    #define REG_004C_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_004C_TRIGGER_GEN_BKA3A5_REG_OP1_VS_TRIG_LEN Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0050_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x050)
    #define REG_0050_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0058_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x058)
    #define REG_0058_TRIGGER_GEN_BKA3A5_REG_OP1_RW_BK_UPD_TRIG_REP_INTERVAL Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_0058_TRIGGER_GEN_BKA3A5_REG_OP1_DMA_RD_TRIG_REP_INTERVAL Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0060_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x060)
    #define REG_0060_TRIGGER_GEN_BKA3A5_REG_OP1_AUTO_TRIG_VS_POS_RPT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0064_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x064)
    #define REG_0064_TRIGGER_GEN_BKA3A5_REG_OP1_VCNT_UPD_MASK_RANGE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0064_TRIGGER_GEN_BKA3A5_REG_OP1_VCNT_OF_KEEP_EN Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0068_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x068)
    #define REG_0068_TRIGGER_GEN_BKA3A5_REG_OP1_VCNT_INI_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define REG_006C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x06C)
    #define REG_006C_TRIGGER_GEN_BKA3A5_REG_OP1_SW_HCNT_INI_VAL Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0070_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x070)
    #define REG_0070_TRIGGER_GEN_BKA3A5_REG_OP1_SW_HTT_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0074_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x074)
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_SW_H_USR_MD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_VS_SW_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_SEQ_STATUS_ERROR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_SEQ_STATUS_ERROR_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_SEQ_STATUS Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_SW_V_USR_MD Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0074_TRIGGER_GEN_BKA3A5_REG_OP1_DIST_ST_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0078_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x078)
    #define REG_0078_TRIGGER_GEN_BKA3A5_REG_OP1_P2P_DIST Fld(13,0,AC_MSKW10)//[12:0]
#define REG_007C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x07C)
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_DUMMY0_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_DUMMY1_TRIG Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_AUTO_TRIG_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_AUTO_TRIG_LENGTH Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_AUTO_TRIG_INTERVAL Fld(4,10,AC_MSKB1)//[13:10]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_NO_SIG_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_007C_TRIGGER_GEN_BKA3A5_REG_OP1_VS_NO_SIG_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0084_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x084)
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_INPUT_SRC_SEL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_COMMON_TRIG_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_TRIG_GEN_SEL_SEP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UP_TRIG_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_DS_TRIG_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_ML_TRIG_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_VS_TRIG_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_STR_TRIG_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_SW_IRQ_TRIG_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0084_TRIGGER_GEN_BKA3A5_REG_OP2_PQ_IRQ_TRIG_SEL Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0088_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x088)
    #define REG_0088_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UP_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_008C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x08C)
    #define REG_008C_TRIGGER_GEN_BKA3A5_REG_OP2_DS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0090_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x090)
    #define REG_0090_TRIGGER_GEN_BKA3A5_REG_OP2_ML_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0094_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x094)
    #define REG_0094_TRIGGER_GEN_BKA3A5_REG_OP2_VS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0098_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x098)
    #define REG_0098_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_009C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x09C)
    #define REG_009C_TRIGGER_GEN_BKA3A5_REG_OP2_STR_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0A0)
    #define REG_00A0_TRIGGER_GEN_BKA3A5_REG_OP2_SW_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A4_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0A4)
    #define REG_00A4_TRIGGER_GEN_BKA3A5_REG_OP2_PQ_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00A8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0A8)
    #define REG_00A8_TRIGGER_GEN_BKA3A5_REG_OP2_DUMMY0_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00AC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0AC)
    #define REG_00AC_TRIGGER_GEN_BKA3A5_REG_OP2_DUMMY1_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00B8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0B8)
    #define REG_00B8_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UPD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00BC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0BC)
    #define REG_00BC_TRIGGER_GEN_BKA3A5_REG_OP2_VS_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00C0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0C0)
    #define REG_00C0_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00CC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0CC)
    #define REG_00CC_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UPD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_00CC_TRIGGER_GEN_BKA3A5_REG_OP2_VS_TRIG_LEN Fld(8,8,AC_FULLB1)//[15:8]
#define REG_00D0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0D0)
    #define REG_00D0_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
#define REG_00D8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0D8)
    #define REG_00D8_TRIGGER_GEN_BKA3A5_REG_OP2_RW_BK_UPD_TRIG_REP_INTERVAL Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_00D8_TRIGGER_GEN_BKA3A5_REG_OP2_DMA_RD_TRIG_REP_INTERVAL Fld(8,0,AC_FULLB0)//[7:0]
#define REG_00E0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0E0)
    #define REG_00E0_TRIGGER_GEN_BKA3A5_REG_OP2_AUTO_TRIG_VS_POS_RPT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00E4_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0E4)
    #define REG_00E4_TRIGGER_GEN_BKA3A5_REG_OP2_VCNT_UPD_MASK_RANGE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_00E4_TRIGGER_GEN_BKA3A5_REG_OP2_VCNT_OF_KEEP_EN Fld(1,12,AC_MSKB1)//[12:12]
#define REG_00E8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0E8)
    #define REG_00E8_TRIGGER_GEN_BKA3A5_REG_OP2_VCNT_INI_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00EC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0EC)
    #define REG_00EC_TRIGGER_GEN_BKA3A5_REG_OP2_SW_HCNT_INI_VAL Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00F0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0F0)
    #define REG_00F0_TRIGGER_GEN_BKA3A5_REG_OP2_SW_HTT_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_00F4_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0F4)
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_SW_H_USR_MD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_VS_SW_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_SEQ_STATUS_ERROR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_SEQ_STATUS_ERROR_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_SEQ_STATUS Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_SW_V_USR_MD Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00F4_TRIGGER_GEN_BKA3A5_REG_OP2_DIST_ST_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_00F8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0F8)
    #define REG_00F8_TRIGGER_GEN_BKA3A5_REG_OP2_P2P_DIST Fld(13,0,AC_MSKW10)//[12:0]
#define REG_00FC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x0FC)
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_DUMMY0_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_DUMMY1_TRIG Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_AUTO_TRIG_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_AUTO_TRIG_LENGTH Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_AUTO_TRIG_INTERVAL Fld(4,10,AC_MSKB1)//[13:10]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_NO_SIG_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_00FC_TRIGGER_GEN_BKA3A5_REG_OP2_VS_NO_SIG_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0104_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x104)
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_INPUT_SRC_SEL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_COMMON_TRIG_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_TRIG_GEN_SEL_SEP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UP_TRIG_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_DS_TRIG_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_ML_TRIG_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_VS_TRIG_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_STR_TRIG_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_SW_IRQ_TRIG_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0104_TRIGGER_GEN_BKA3A5_REG_DISP_PQ_IRQ_TRIG_SEL Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0108_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x108)
    #define REG_0108_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UP_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_010C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x10C)
    #define REG_010C_TRIGGER_GEN_BKA3A5_REG_DISP_DS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0110_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x110)
    #define REG_0110_TRIGGER_GEN_BKA3A5_REG_DISP_ML_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0114_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x114)
    #define REG_0114_TRIGGER_GEN_BKA3A5_REG_DISP_VS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0118_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x118)
    #define REG_0118_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_011C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x11C)
    #define REG_011C_TRIGGER_GEN_BKA3A5_REG_DISP_STR_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0120_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x120)
    #define REG_0120_TRIGGER_GEN_BKA3A5_REG_DISP_SW_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0124_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x124)
    #define REG_0124_TRIGGER_GEN_BKA3A5_REG_DISP_PQ_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0128_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x128)
    #define REG_0128_TRIGGER_GEN_BKA3A5_REG_DISP_DUMMY0_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_012C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x12C)
    #define REG_012C_TRIGGER_GEN_BKA3A5_REG_DISP_DUMMY1_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0138_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x138)
    #define REG_0138_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UPD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_013C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x13C)
    #define REG_013C_TRIGGER_GEN_BKA3A5_REG_DISP_VS_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0140_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x140)
    #define REG_0140_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_014C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x14C)
    #define REG_014C_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UPD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_014C_TRIGGER_GEN_BKA3A5_REG_DISP_VS_TRIG_LEN Fld(8,8,AC_FULLB1)//[15:8]
#define REG_0150_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x150)
    #define REG_0150_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0158_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x158)
    #define REG_0158_TRIGGER_GEN_BKA3A5_REG_DISP_RW_BK_UPD_TRIG_REP_INTERVAL Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_0158_TRIGGER_GEN_BKA3A5_REG_DISP_DMA_RD_TRIG_REP_INTERVAL Fld(8,0,AC_FULLB0)//[7:0]
#define REG_0160_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x160)
    #define REG_0160_TRIGGER_GEN_BKA3A5_REG_DISP_AUTO_TRIG_VS_POS_RPT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0164_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x164)
    #define REG_0164_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_UPD_MASK_RANGE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_0164_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_OF_KEEP_EN Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0168_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x168)
    #define REG_0168_TRIGGER_GEN_BKA3A5_REG_DISP_VCNT_INI_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define REG_016C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x16C)
    #define REG_016C_TRIGGER_GEN_BKA3A5_REG_DISP_SW_HCNT_INI_VAL Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0170_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x170)
    #define REG_0170_TRIGGER_GEN_BKA3A5_REG_DISP_SW_HTT_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_0174_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x174)
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SW_H_USR_MD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_VS_SW_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SEQ_STATUS_ERROR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SEQ_STATUS_ERROR_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SEQ_STATUS Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_SW_V_USR_MD Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0174_TRIGGER_GEN_BKA3A5_REG_DISP_DIST_ST_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0178_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x178)
    #define REG_0178_TRIGGER_GEN_BKA3A5_REG_DISP_P2P_DIST Fld(13,0,AC_MSKW10)//[12:0]
#define REG_017C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x17C)
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_DUMMY0_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_DUMMY1_TRIG Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_AUTO_TRIG_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_AUTO_TRIG_LENGTH Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_AUTO_TRIG_INTERVAL Fld(4,10,AC_MSKB1)//[13:10]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_NO_SIG_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_017C_TRIGGER_GEN_BKA3A5_REG_DISP_VS_NO_SIG_FLAG Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x184)
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_INPUT_SRC_SEL Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_COMMON_TRIG_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_TRIG_GEN_SEL_SEP Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UP_TRIG_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_DS_TRIG_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_ML_TRIG_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_VS_TRIG_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_STR_TRIG_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_IRQ_TRIG_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0184_TRIGGER_GEN_BKA3A5_REG_FRC1_PQ_IRQ_TRIG_SEL Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0188_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x188)
    #define REG_0188_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UP_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_018C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x18C)
    #define REG_018C_TRIGGER_GEN_BKA3A5_REG_FRC1_DS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0190_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x190)
    #define REG_0190_TRIGGER_GEN_BKA3A5_REG_FRC1_ML_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0194_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x194)
    #define REG_0194_TRIGGER_GEN_BKA3A5_REG_FRC1_VS_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0198_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x198)
    #define REG_0198_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_019C_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x19C)
    #define REG_019C_TRIGGER_GEN_BKA3A5_REG_FRC1_STR_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01A0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1A0)
    #define REG_01A0_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01A4_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1A4)
    #define REG_01A4_TRIGGER_GEN_BKA3A5_REG_FRC1_PQ_IRQ_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01A8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1A8)
    #define REG_01A8_TRIGGER_GEN_BKA3A5_REG_FRC1_DUMMY0_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01AC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1AC)
    #define REG_01AC_TRIGGER_GEN_BKA3A5_REG_FRC1_DUMMY1_TRIG_DLY_V Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01B8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1B8)
    #define REG_01B8_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UPD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01BC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1BC)
    #define REG_01BC_TRIGGER_GEN_BKA3A5_REG_FRC1_VS_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01C0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1C0)
    #define REG_01C0_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_DLY_H Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01CC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1CC)
    #define REG_01CC_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UPD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_01CC_TRIGGER_GEN_BKA3A5_REG_FRC1_VS_TRIG_LEN Fld(8,8,AC_FULLB1)//[15:8]
#define REG_01D0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1D0)
    #define REG_01D0_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_LEN Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01D8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1D8)
    #define REG_01D8_TRIGGER_GEN_BKA3A5_REG_FRC1_RW_BK_UPD_TRIG_REP_INTERVAL Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_01D8_TRIGGER_GEN_BKA3A5_REG_FRC1_DMA_RD_TRIG_REP_INTERVAL Fld(8,0,AC_FULLB0)//[7:0]
#define REG_01E0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1E0)
    #define REG_01E0_TRIGGER_GEN_BKA3A5_REG_FRC1_AUTO_TRIG_VS_POS_RPT Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01E4_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1E4)
    #define REG_01E4_TRIGGER_GEN_BKA3A5_REG_FRC1_VCNT_UPD_MASK_RANGE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_01E4_TRIGGER_GEN_BKA3A5_REG_FRC1_VCNT_OF_KEEP_EN Fld(1,12,AC_MSKB1)//[12:12]
#define REG_01E8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1E8)
    #define REG_01E8_TRIGGER_GEN_BKA3A5_REG_FRC1_VCNT_INI_VAL Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01EC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1EC)
    #define REG_01EC_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_HCNT_INI_VAL Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01F0_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1F0)
    #define REG_01F0_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_HTT_SIZE Fld(14,0,AC_MSKW10)//[13:0]
#define REG_01F4_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1F4)
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_H_USR_MD Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_VS_SW_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_SEQ_STATUS_ERROR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_SEQ_STATUS_ERROR_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_SEQ_STATUS Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_V_USR_MD Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01F4_TRIGGER_GEN_BKA3A5_REG_FRC1_DIST_ST_SEL Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01F8_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1F8)
    #define REG_01F8_TRIGGER_GEN_BKA3A5_REG_FRC1_P2P_DIST Fld(13,0,AC_MSKW10)//[12:0]
#define REG_01FC_TRIGGER_GEN_BKA3A5 (TRIGGER_GEN_BKA3A5 + 0x1FC)
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_DUMMY0_TRIG Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_DUMMY1_TRIG Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_AUTO_TRIG_MD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_AUTO_TRIG_LENGTH Fld(6,4,AC_MSKW10)//[9:4]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_AUTO_TRIG_INTERVAL Fld(4,10,AC_MSKB1)//[13:10]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_NO_SIG_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_01FC_TRIGGER_GEN_BKA3A5_REG_FRC1_VS_NO_SIG_FLAG Fld(1,15,AC_MSKB1)//[15:15]

#endif
