#ifndef _SCTCON_MISC_BK_H
#define _SCTCON_MISC_BK_H

#define SCTCON_MISC_BKA3E0 0x0147C000

//Page SCTCON_MISC_BKA3E0
#define REG_0004_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x004)
    #define REG_0004_SCTCON_MISC_BKA3E0_REG_SCTCON_MISC_BYPASS_ALL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0004_SCTCON_MISC_BKA3E0_REG_R2Y_BYPASS Fld(1,4,AC_MSKB0)//[4:4]
#define REG_0008_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x008)
    #define REG_0008_SCTCON_MISC_BKA3E0_REG_CSC_RA_Y_OFFSET Fld(12,0,AC_MSKW10)//[11:0]
#define REG_000C_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x00C)
    #define REG_000C_SCTCON_MISC_BKA3E0_REG_CSC_RA_Y_GAIN Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0010_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x010)
    #define REG_0010_SCTCON_MISC_BKA3E0_REG_CSC_RA_C_IS_UV Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_0010_SCTCON_MISC_BKA3E0_REG_CSC_RA_C_OFFSET Fld(12,0,AC_MSKW10)//[11:0]
#define REG_0014_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x014)
    #define REG_0014_SCTCON_MISC_BKA3E0_REG_CSC_RA_C_GAIN Fld(12,0,AC_MSKW10)//[11:0]
    #define REG_0014_SCTCON_MISC_BKA3E0_REG_PROTECT_DATA_MODE Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0018_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x018)
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_RANGE3 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_RANGE2 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_RANGE1 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_Y_SUB16_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_COL3X3_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_COL3X3_DITHER_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_COL3X3_ROUNDING_TRUNCATE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_B_SUB16_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_R_SUB16_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_B_ADD_16_POST_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_R_ADD_16_POST_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_CR_ADD_128_POST_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_CB_ADD_128_POST_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_0018_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_Y_ADD_16_POST_EN Fld(1,15,AC_MSKB1)//[15:15]
#define REG_001C_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x01C)
    #define REG_001C_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB11 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0020_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x020)
    #define REG_0020_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB12 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0024_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x024)
    #define REG_0024_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB13 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0028_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x028)
    #define REG_0028_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB21 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_002C_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x02C)
    #define REG_002C_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB22 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0030_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x030)
    #define REG_0030_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB23 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0034_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x034)
    #define REG_0034_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB31 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0038_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x038)
    #define REG_0038_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB32 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_003C_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x03C)
    #define REG_003C_SCTCON_MISC_BKA3E0_REG_MAIN_R2Y_SRGB33 Fld(13,0,AC_MSKW10)//[12:0]
#define REG_0040_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x040)
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_DROP_SEL Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_121_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_AVG_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_44TO42_DITH_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_BYPASS Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_444TO422_SWAP Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_0040_SCTCON_MISC_BKA3E0_REG_MOD_REORDER Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0044_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x044)
    #define REG_0044_SCTCON_MISC_BKA3E0_REG_SCTCON_CHK_SUM_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_0044_SCTCON_MISC_BKA3E0_REG_SCTCON_CHK_SUM_CH_SEL Fld(4,4,AC_MSKB0)//[7:4]
#define REG_0048_SCTCON_MISC_BKA3E0 (SCTCON_MISC_BKA3E0 + 0x048)
    #define REG_0048_SCTCON_MISC_BKA3E0_REG_SCTCON_CHK_SUM_VALUE Fld(16,0,AC_FULLW10)//[15:0]

#endif
