/*------------------------------------------------------------------------------
* MediaTek Inc. (C) 2020. All rights reserved.
*
* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to MediaTek Inc. and/or its licensors. Without
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*----------------------------------------------------------------------------*/

#ifndef _HAL_MVOP_H_
#define _HAL_MVOP_H_

//-------------------------------------------------------------------------------------------------
//  Macro and Define
//-------------------------------------------------------------------------------------------------
#define STB_DC                      0 // 0 for TV series MVOP; 1 for STB DC.

#define MVOP_MIU_CLIENT_MAIN        MIU_CLIENT_MVOP_128BIT_R
#define MVOP_MIU_CLIENT_SUB         MIU_CLIENT_MVOP1_R

#define _MVOP_128BIT_BUS            0 // 128-bit MIU bus
#define _MVOP_64BIT_BUS             1 // 64-bit MIU bus
#define MVOP_BUS_WIDTH              _MVOP_128BIT_BUS

#define HAL_MVOP_MODULE_CNT         1
#if (HAL_MVOP_MODULE_CNT >= 2)
#define MVOP_SUPPORT_SUB            1
#else
#define MVOP_SUPPORT_SUB            0
#endif
#if (HAL_MVOP_MODULE_CNT >= 3)
#define MVOP_SUPPORT_3RD            1
#else
#define MVOP_SUPPORT_3RD            0
#endif

#define HAL_MFDEC_MODULE_CNT        1
#if (HAL_MFDEC_MODULE_CNT >= 2)
#define MVOP_SUPPORT_MFDEC1         1
#else
#define MVOP_SUPPORT_MFDEC1         0
#endif

#define ENABLE_3D_LR_MODE           1 // Enable 3D L/R feature
#define SUPPORT_3DLR_INST_VBLANK    0
#define SUPPORT_3DLR_ALT_SBS        1

#define SUPPORT_EVD_MODE            1
#define SUPPORT_VP9_MODE            1

#define SUPPORT_FILED_DB            0
#define SUPPORT_INT_VSIZE_EX        0

#if (STB_DC == 0)
#define MVOP_BASE_ADD_BITS          31 // 29 - 1 (MSB is signed bit) + 3 (unit in 8-byte)
#endif

#define SUPPORT_KERNAL_STR          1
#define SUPPORT_DDR4_REMAP          0
#define SUPPORT_BACK_DRI_FWD        0
#define MFDEC_DB_PATCH              1 // M7322 no sharing sram
#define MVOP_10B_H128_PATCH         1
#define GOP_BACKPORCH_PATCH         1
#define IOMMU_MFDEC_CTRL            1
#define MFDEC_HSIZE_LIMIT_PATCH     1
#define I_GEN_FIELD_TIMING          1
#define MFDEC_HCROP_ALIGN           1
#define OPTIMIZED_BLANK             0
#define MFDEC_ROTATE_INTERLACE      1
#define DDR4_CH_BALANCE_PATCH       1
#define AUDIO_VIDEO_DELAY_PATCH     1
#define MAIN_SUB_MVOP_DIFF          0
#define SUPPORT_MFDEC_ROTATE        0

#define MVOP_BANK_REGNUM            0x80UL
#define MVOP_CLK_REGNUM             0x10UL

#define FHD_SRAM_SIZE               2048

#define ADDRESS_4GB                 0x100000000ULL

#define MFD_FLUSH_TIMEOUT_DEFAULT   0x3f3f
#define MFD_FLUSH_TIMEOUT_BOUND     0x3f07

// Blanking related define
#define HSIZE_UHD                           3840
#define VSIZE_UHD                           2160
#define HSIZE_FHD0                          1920
#define VSIZE_FHD0                          1080
#define VSIZE_FHD1                          1088

#define FRAMERATE_60000                     60000
#define FRAMERATE_59940                     59940
#define FRAMERATE_50000                     50000
#define FRAMERATE_48000                     48000
#define FRAMERATE_30000                     30000
#define FRAMERATE_29970                     29970
#define FRAMERATE_25000                     25000
#define FRAMERATE_24000                     24000
#define FRAMERATE_23976                     23976

#define OPTIMIZED_HBLANK_FHD_23976          320

#define OPTIMIZED_VBLANK_UHD_FRONT_60000    53
#define OPTIMIZED_VBLANK_UHD_FRONT_59940    70
#define OPTIMIZED_VBLANK_UHD_FRONT_50000    340
#define OPTIMIZED_VBLANK_UHD_FRONT_48000    282
#define OPTIMIZED_VBLANK_UHD_FRONT_23976    257

#define OPTIMIZED_VBLANK_FHD0_FRONT_60000   49
#define OPTIMIZED_VBLANK_FHD0_FRONT_59940   53
#define OPTIMIZED_VBLANK_FHD0_FRONT_50000   45
#define OPTIMIZED_VBLANK_FHD0_BACK_50000    125
#define OPTIMIZED_VBLANK_FHD0_FRONT_48000   75
#define OPTIMIZED_VBLANK_FHD0_FRONT_30000   254
#define OPTIMIZED_VBLANK_FHD0_FRONT_29970   291
#define OPTIMIZED_VBLANK_FHD0_FRONT_25000   45
#define OPTIMIZED_VBLANK_FHD0_FRONT_24000   45

#define OPTIMIZED_VBLANK_FHD1_FRONT_60000   41
#define OPTIMIZED_VBLANK_FHD1_FRONT_59940   45
#define OPTIMIZED_VBLANK_FHD1_FRONT_50000   45
#define OPTIMIZED_VBLANK_FHD1_BACK_50000    117
#define OPTIMIZED_VBLANK_FHD1_FRONT_48000   67
#define OPTIMIZED_VBLANK_FHD1_FRONT_30000   246
#define OPTIMIZED_VBLANK_FHD1_FRONT_29970   283
#define OPTIMIZED_VBLANK_FHD1_FRONT_25000   37
#define OPTIMIZED_VBLANK_FHD1_FRONT_24000   37
#define OPTIMIZED_VBLANK_FHD1_FRONT_23976   37

#define IP2_PATCH_HOFFSET                   256
//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------
typedef struct
{
    MS_U8 u8Gp: 4;
    MS_U8 u8BitPos: 4;
} HALMVOPMIUCLIENTINFO;

typedef enum
{
    E_MVOP_SEL_MIU0         = 0,
    E_MVOP_SEL_MIU1         = 0x01,
    E_MVOP_SEL_MIU2         = 0x02,
    E_MVOP_SEL_MIU3         = 0x03,
    E_MVOP_SEL_NONE         = 0xFF,
} HALMVOPMIUSEL;

typedef struct
{
    MS_BOOL bMVOP0;
    MS_BOOL bMVOP1;
    MS_BOOL bMFDEC0;
    MS_BOOL bMFDEC1;
} MVOP_SCIPSel;

typedef struct
{
    MS_U16 MVOP_BANK[3][0x80];
    MS_U16 CLK_BANK[0x10];
} MVOP_STR_SAVE_AREA;

typedef enum
{
    E_MVOP_POWER_SUSPEND     = 1,    // State is backup in DRAM, components power off.
    E_MVOP_POWER_RESUME      = 2,    // Resume from Suspend or Hibernate mode
    E_MVOP_POWER_MECHANICAL  = 3,    // Full power off mode. System return to working state only after full reboot
    E_MVOP_POWER_SOFT_OFF    = 4,    // The system appears to be off, but some components remain powered for trigging boot-up.
} EN_MVOP_POWER_MODE;

typedef struct
{
    MVOP_DrvMirror enMirror;
    EN_MVOP_Output_3D_TYPE en3D;
    MS_BOOL bHSK;
    MS_BOOL bXCGenTiming;
    MVOP_SetCropPos stCropSt;
    MVOP_SetImageWH stCropSize;
    MS_BOOL bOneField;
    MS_BOOL b2P;
    MS_BOOL bForceP;
    MS_U32 u32Framerate;
    MS_BOOL b422YUVOutput;
    MS_U8 u8DMAThreshold;
    MS_U8 u8DMABurstLen;
    MS_U8 u8MFDECBurstLen;
    MS_BOOL bIsEnLSB;
} MVOP_FeatureMdb;

typedef struct
{
    MS_PHY u32RegYoffset;
    MS_PHY u32RegUVoffset;
    MS_U16 u16RegHsize;
    MS_U16 u16RegVsize;
    MS_U16 u16RegStrip;
    MS_BOOL bReg422;
    MS_BOOL bRegPMode;
    MS_BOOL bRegDramContd;
    MS_BOOL bRegField;
    MS_BOOL bReg422Pack;
    MS_U8 u8RegDSIndex;
    MS_BOOL bRegFDMask;
    MS_BOOL bRegMfdecEn;
    MS_U32 u32RegBitenAdd;
    MS_BOOL bUncompress;
} MVOP_RegInputMdb;

typedef struct
{
    MS_U32 u32RegVtt;
    MS_U32 u32RegHtt;
    MS_U16 u16RegVImgst;
    MS_U16 u16RegHImgst;
    MS_BOOL bRegInterlace;
    MS_U8 u8RegFPS;
    MS_U16 u16RegExpFPS;
    MS_U16 u16RegWidth;
    MS_U16 u16RegHeight;
    MS_BOOL bRegHDup;
    MS_BOOL bReg2P;
    MVOP_FREQUENCY enRegCLOCK;
    MS_U16 u16RegVsForward;
    MS_U32 u32SyncClockVal;
} MVOP_RegOutputMdb;

typedef struct
{
    MS_BOOL bMFDEC_EN;
    MS_U8   u8MFDEC_ID;
    MS_U32  u32UNCOMPRESS_MODE;
    MS_PHY  u32BITLEN_FB_ADDR;         ///<0:8 bit EL y address, 1:8 bit EL uv address
    MS_U8   u8BITLEN_FB_MIU;           ///<0:8 bit EL y address, 1:8 bit EL uv address
    MS_U32  u32BITLEN_FB_PITCH;
    MS_BOOL bBITLEN_SHT_8;
    MS_BOOL bAV1Mode;                  ///<AV1 + mfdec compress mode
    MS_BOOL bAllowIntrabc;             ///<AV1 + intrabc stream
} HALMVOPMFDECINFO;

typedef struct
{
    MS_U16 u16Width;                   ///<MSB/Dual DV BL width
    MS_U16 u16Height;                  ///<MSB/Dual DV BL height
    MS_U16 u16Pitch[2];                ///<MSB/Dual DV BL pitch
    MS_U8  U8DSIndex;                  ///<DS index
    MS_BOOL bHDup;
    MS_BOOL bVDup;
    MS_BOOL bHSD;                      ///< HSD enable
    MS_U16  u16OutputWidth;            ///< mvop output width
} HALMVOPDISPSize;

typedef struct
{
    MS_BOOL bDualDV_EN;
    MS_U16 u16Width_EL;                ///<Dual DV EL width
    MS_U16 u16Height_EL;               ///<Dual DV EL height
    MS_U16 u16Pitch_EL[2];             ///<Dual DV EL pitch
} HALMVOPDISPDualDVSize;

typedef struct
{
    MS_BOOL bOutputIMode;
    MS_U8   u8FDMask;
    MS_U8   u8BotFlag;
    MS_BOOL bXCBOB_EN;
    MVOP_OutputImodeType eIModeType;
} HALMVOPInterlace;

typedef struct
{
    MVOP_TileFormat eTileFormat;
    MS_BOOL bIs422Mode;
    MS_BOOL bIsDRAMCont;
    MS_BOOL bDDR4_REMAP;
    MS_BOOL bDS_EN;
} HALMVOStreamINFO;

typedef enum
{
    E_SW_CTL_MIU_0      = 1,
    E_SW_CTL_MIU_1      = 2,
    E_HW_CTL_MIU        = 3,
    E_SW_CTL_MIU_DEF    = 4,
    E_NONE_CTL_MIU      = 0xff,
} EN_MVOP_MIU_SEL;

typedef struct
{
    MS_U16 u16VBlankFront;
    MS_U16 u16VBlankBack;
    MS_U16 u16HBlankHD;
    MS_U16 u16HBlankSD;
} MVOP_Blank;

//-------------------------------------------------------------------------------------------------
//  Function and Variable
//-------------------------------------------------------------------------------------------------
void HAL_MVOP_RegSetBase(MS_VIRT u32Base);
void HAL_MVOP_Init(MVOP_DevID eDevID);
void HAL_MVOP_SetFieldInverse(MVOP_DevID eDevID, MS_BOOL b2MVD, MS_BOOL b2IP);
void HAL_MVOP_SetChromaWeighting(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_LoadReg(MVOP_DevID eDevID);
void HAL_MVOP_SetMIUReqMask(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_Enable(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetEnableState(MVOP_DevID eDevID);
MVOP_FREQUENCY HAL_MVOP_GetMaxFreerunClk(MVOP_DevID eDevID);
void HAL_MVOP_SetFrequency(MVOP_DevID eDevID, MVOP_FREQUENCY enFrequency);
MVOP_FREQUENCY HAL_MVOP_GetMaximumClk(MVOP_DevID eDevID);
MVOP_FREQUENCY HAL_MVOP_GetCurrentClk(MVOP_DevID eDevID);
void HAL_MVOP_Rst(MVOP_DevID eDevID);
void HAL_MVOP_SetBlackBG(MVOP_DevID eDevID);
void HAL_MVOP_SetOutputInterlace(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetCropWindow(MVOP_DevID eDevID, MVOP_InputCfg* pparam);
void HAL_MVOP_SetInputMode(MVOP_DevID eDevID, VOPINPUTMODE mode,
                           MVOP_InputCfg* pparam);
void HAL_MVOP_EnableUVShift(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetVSyncMode(MVOP_DevID eDevID, MS_U8 u8Mode);
void HAL_MVOP_SetOutputTiming(MVOP_DevID eDevID, MVOP_Timing* ptiming);
void HAL_MVOP_SetDCClk(MVOP_DevID eDevID, MS_U8 clkNum, MS_BOOL bEnable);
void HAL_MVOP_SetSynClk(MVOP_DevID eDevID, MVOP_Timing* ptiming);
void HAL_MVOP_SetMonoMode(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetH264HardwireMode(MVOP_DevID eDevID);
void HAL_MVOP_SetH264HardwireMode_DV(MVOP_DevID eDevID);
void HAL_MVOP_SetRMHardwireMode(MVOP_DevID eDevID);
void HAL_MVOP_SetJpegHardwireMode(MVOP_DevID eDevID);
void HAL_MVOP_SetEVDHardwireMode(MVOP_DevID eDevI);
void HAL_MVOP_SetEVDHardwireMode_DV(void);
void HAL_MVOP_SetEVDHardwireMode_TCH(MVOP_DevID eDevID);
void HAL_MVOP_SetVP9HardwireMode(MVOP_DevID eDevID);
void HAL_MVOP_SetAVS2HardwireMode(MVOP_DevID eDevID);
void HAL_MVOP_SetEVDFeature(MVOP_DevID eID, MVOP_EVDFeature* stEVDInput);
void HAL_MVOP_SetPattern(MVOP_DevID eDevID, MVOP_Pattern enMVOPPattern);
MS_BOOL HAL_MVOP_SetTileFormat(MVOP_DevID eDevID, MVOP_TileFormat eTileFormat);
MS_BOOL HAL_MVOP_SetRgbFormat(MVOP_DevID eDevID, MVOP_RgbFormat eRgbFmt);
MS_BOOL HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt);
MS_BOOL HAL_MVOP_Enable3DLR(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_Get3DLRMode(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_GetTimingInfoFromRegisters(MVOP_DevID eDevID, MVOP_TimingInfo_FromRegisters* mvopTimingInfo);
void HAL_MVOP_SetHorizontallMirrorMode(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetVerticalMirrorMode(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetYUVBaseAdd(MVOP_DevID eDevID, MS_PHY u32YOffset,
                            MS_PHY u32UVOffset, MS_BOOL bProgressive,
                            MS_BOOL b422pack);
void HAL_MVOP_SetRepeatField(MVOP_DevID eDevID, MVOP_RptFldMode eMode);
MS_PHY HAL_MVOP_GetYBaseAdd(MVOP_DevID eDevID);
MS_PHY HAL_MVOP_GetUVBaseAdd(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_Set3DLRAltOutput(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_Set3DLRAltSBSOutput(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_Get3DLRAltOutput(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_Get3DLRAltSBSOutput(MVOP_DevID eDevID);
EN_MVOP_Output_3D_TYPE HAL_MVOP_GetOutput3DType(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable);
MS_BOOL HAL_MVOP_Get3DLR2ndCfg(void);
MVOP_DrvMirror HAL_MVOP_GetMirrorMode(MVOP_DevID eID);
MS_BOOL HAL_MVOP_SetVerDup(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetVerDup(void);
MS_BOOL HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetVerx4Dup(void);
MS_BOOL HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetHorx4Dup(void);
MS_BOOL HAL_MVOP_SetYUVBaseAddMultiView(MVOP_DevID eID, MVOP_BaseAddInput* stBaseAddInfo);
MS_BOOL HAL_MVOP_SetEVDYUVBaseAdd(MVOP_DevID eDevID, MVOP_EVDBaseAddInput* stEVDBaseAddInfo, MS_BOOL bMFEnable);
MS_PHY HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView);
MS_PHY HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView);
MS_U16 HAL_MVOP_GetTopVStart(MVOP_DevID eID);
MS_U16 HAL_MVOP_GetBottomVStart(MVOP_DevID eID);
MS_U16 HAL_MVOP_GetVCount(MVOP_DevID eID);
void HAL_MVOP_SetStartX(MVOP_DevID eID, MS_U16 u16Length);
void HAL_MVOP_SetStartY(MVOP_DevID eID, MS_U16 u16Length, MS_BOOL bIsInterlace);
void HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID, MS_U16 u16Sizes, MS_U16 u16Width);
void HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID, MS_U16 u16Sizes, MS_U16 u16Height);
MS_BOOL HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID, MVOP_VC1RangeMapInfo* stVC1RangeMapInfo);
MS_BOOL HAL_MVOP_Set420BWSaveMode(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID, MS_BOOL bEnable);
void HAL_MVOP_PowerStateSuspend(void);
MVOP_HSMode HAL_MVOP_GetHandShakeMode(MVOP_DevID eID);
MS_BOOL HAL_MVOP_CheckSTCCW(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo);
void HAL_MVOP_SelMIU(MVOP_DevID eDevID, HALMVOPMIUSEL eMiuMSB0, HALMVOPMIUSEL eMiuMSB1, HALMVOPMIUSEL eMiuLSB0, HALMVOPMIUSEL eMiuLSB1);
EN_MVOP_MIU_SEL HAL_MVOP_GetIsOnlyMiuIPControl(void);
void HAL_MVOP_SetDCSRAMClk(MVOP_DevID eDevID, MS_U8 clkNum, MS_BOOL bEnable);
void HAL_MVOP_Set2PMode(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID, MVOP_GetMaxFps* stStreamInfo);
void HAL_MVOP_ResetReg(MVOP_DevID eDevID);
void HAL_MVOP_SetHandShakeMode(MVOP_DevID eID, MS_BOOL bEnable, MS_U8 u8Framerate);
void HAL_MVOP_SetCropforXC(MVOP_DevID eID, MVOP_XCGetCrop* stXCCrop, MS_U16 u16Width, MS_U16 u16Height);
MS_BOOL HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID);
MS_BOOL HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID);
MS_U16 HAL_MVOP_ReadBank(MVOP_DevID eID, MS_U16 u16Length);
void HAL_MVOP_WriteBank(MVOP_DevID eID, MS_U16 u16Length, MS_U16 u16Data);
MS_U16 HAL_MVOP_ReadClkBank(MS_U16 u16Length);
void HAL_MVOP_WriteClkBank(MS_U16 u16Length, MS_U16 u16Data);
void HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID, MS_U8 u8Interlace);
void HAL_MVOP_Enable2DCTimingSync(MS_BOOL bEnable);
void HAL_MVOP_EnableHDRSetting(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetByTiming(MVOP_DevID eID, MVOP_VidStat* pstVideoStatus);
MS_BOOL HAL_MVOP_IsSupport2PMode(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_AutoTimingHDS(MVOP_DevID eID);
MS_BOOL HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID);
MS_BOOL HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID);
void HAL_MVOP_SetTimingFromXC(MVOP_DevID eID, MS_BOOL bEnable);
void HAL_MVOP_SetMiuSaveArea(MVOP_DevID eID, MVOP_MIUReadPrct stMiuSave);
void HAL_MVOP_Exit(MVOP_DevID eID);
void HAL_MVOP_UVSwapEnable(MVOP_DevID eID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_SetMFDECRotate(MVOP_DevID eID, MVOP_MFDECRotate eRotate);
void HAL_MVOP_EnableFODtoWB(MVOP_DevID eID, MS_BOOL bEnable);
void HAL_MVOP_SetECONumber(MS_U16 u16ChipRev, MS_U16 u16ChipVer);
void HAL_MVOP_MDBRegInputCfg(MVOP_DevID eID, MVOP_InputSel _eInputSel, MVOP_RegInputMdb* stRegInput);
void HAL_MVOP_MDBRegOutputCfg(MVOP_DevID eID, MVOP_RegOutputMdb* stRegOutput);
void HAL_MVOP_MDBRegFeature(MVOP_DevID eID, MVOP_FeatureMdb* pstFeature);
MS_BOOL HAL_MVOP_Get2PMode(MVOP_DevID eDevID);
void HAL_MVOP_GetCropInfo(MVOP_DevID eID, MVOP_SetCropPos* stCropStart, MVOP_SetImageWH* stCropSize);
void HAL_MVOP_MDBSetVsyncFwdLine(MS_U64* pu64ReqHdl, MVOP_DevID eID, MS_U32 u32VsyncLines);
MS_BOOL HAL_MVOP_GetDCClkIsOn(MVOP_DevID eID);
void HAL_MVOP_SetbyInputTiming(MVOP_DevID eID, MVOP_VidStat* pstVideoStatus);
MS_BOOL HAL_MVOP_SetHorDup(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_SetMFDECInfo(MVOP_DevID eID, HALMVOPMFDECINFO* pMFDECInfo, MS_BOOL bOutputIMode);
void HAL_MVOP_SetFrameInterlace(MVOP_DevID eID, HALMVOPInterlace* pIModeInfo);
void HAL_MVOP_SetDISPSize(MVOP_DevID eID, HALMVOPDISPSize* pDispSize);
void HAL_MVOP_SetDISPDVSize(MVOP_DevID eID, HALMVOPDISPDualDVSize* pDispSize);
void HAL_MVOP_SetStreamInfo(MVOP_DevID eID, HALMVOStreamINFO* pStreamInfo);
void HAL_MVOP_ForceWriteReg(MVOP_DevID eDevID);
void HAL_MVOP_EnableTCHSetting(MVOP_DevID eID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetIsBotField(MVOP_DevID eID);
void HAL_MVOP_SetForcePMode(MVOP_DevID eID, MS_BOOL bEnable);
void HAL_MVOP_SetBankSwitch(MS_BOOL bEnable);
void HAL_MVOP_SetFBDecClk(MVOP_DevID eID, MS_BOOL bEnable);
void HAL_MVOP_SetSingleDV(MVOP_DevID eID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetHVTTforDynamicFPS(MVOP_DevID eID, MVOP_Timing* pMVOPTiming, MVOP_DYNAMIC_FPS* pTiming);
MVOP_Pattern HAL_MVOP_GetPattern(MVOP_DevID eID);
void HAL_MVOP_EnableDMSMode(MVOP_DevID eID, MS_BOOL bEnable);
MS_U32 HAL_MVOP_GetVideoDelay(MVOP_DevID eID, MS_U32 u32FPS);
MS_U16 HAL_MVOP_GetHStart(MVOP_Timing* pTiming);
MS_U16 HAL_MVOP_GetVStart(MVOP_Timing* pTiming);
void HAL_MVOP_SetFrameSync(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_IsForce1PTiming(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_SetDMSInterrupt(MVOP_DevID eID, MVOP_IntType eIntType);
MS_BOOL HAL_MVOP_GetDMSInterrupt(MVOP_DevID eID, MVOP_DMSIntStatus* eDMSIntStatus);
MS_BOOL HAL_MVOP_SetTimeStamp(MVOP_DevID eDevID, MS_U64 u64TimeStamp, MS_BOOL bForceTimeStamp);
void HAL_MVOP_InitMirrorMode(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_GetIsFireOnTime(MVOP_DevID eID, MVOP_DMSFireOnTime* pFireTime, MS_U32 u32FPS);
MVOP_RgbFormat HAL_MVOP_GetRGBFormat(MVOP_DevID eID);
MS_BOOL HAL_MVOP_SetFrameReset(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_SetClock(MVOP_DevID eDevID, MVOP_FREQUENCY eFrequency);
MVOP_FREQUENCY HAL_MVOP_GetClock(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_SetHSDIndex(MVOP_DevID eDevID, MS_BOOL bEnable, MS_U16 u16SourceWdh, MS_U16 u16OutputWdh);
MS_BOOL HAL_MVOP_GetHSDCap(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_GetIsDMSMode(MVOP_DevID eID);
void HAL_MVOP_GetDataSize(MVOP_DevID eID, MVOP_SetImageWH* stDataSize);
MS_U64 HAL_MVOP_GetHardwareClock(MVOP_DevID eDevID, MVOP_FREQUENCY eClock);
MS_BOOL HAL_MVOP_SetFineTune(MVOP_DevID eDevID, MS_U16 u16FineTuneCount);
MS_BOOL HAL_MVOP_GetOptimizedBlank(MVOP_DevID eDevID, MVOP_VidStat* pVidStat, MVOP_Blank* pBlank);
MS_BOOL HAL_MVOP_SupportPatDB(void);
MS_BOOL HAL_MVOP_SetOneField(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOP_SetFDMask(MVOP_DevID eDevID, MS_BOOL bEnable);
void HAL_MVOP_CheckFieldInverse(MVOP_DevID eDevID);
MS_BOOL HAL_MVOP_SetAverageMode(MVOP_DevID eDevID, MS_BOOL bEnable);
MS_BOOL HAL_MVOPGetDSRegVal(MVOP_DevID eDevID, MVOP_DSGetValue* pDSVal);

void HAL_MVOP_SubRegSetBase(MS_VIRT u32Base);
void HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable);

void HAL_SetSCFEMIUIPSel(MVOP_SCIPSel* stIPSel);
void HAL_MVOP_ResetMVOPSetting(MVOP_DevID eDevID);
void HAL_MVOP_SetSramPower(MVOP_DevID eID, MS_BOOL bEnable);
void HAL_MVOP_SetFBDecClk(MVOP_DevID eID, MS_BOOL bEnable);

#endif // _HAL_MVOP_H_
