#define PQ_MM_DS_rule_ID_Main_Ex 0
#define PQ_MM_DS_rule_IP_NUM_Main_Ex 10
#define PQ_MM_DS_rule_NUM_Main_Ex 14

#define PQ_MM_DS_RULE_L_SD_I_MAIN_EX 1
#define PQ_MM_DS_RULE_SD_I_MAIN_EX 1
#define PQ_MM_DS_RULE_H_SD_I_MAIN_EX 1
#define PQ_MM_DS_RULE_FHD_I_MAIN_EX 1
#define PQ_MM_DS_RULE_H_FHD_I_MAIN_EX 1
#define PQ_MM_DS_RULE_4K_1K_I_MAIN_EX 1
#define PQ_MM_DS_RULE_4K_I_MAIN_EX 1
#define PQ_MM_DS_RULE_L_SD_P_MAIN_EX 1
#define PQ_MM_DS_RULE_SD_P_MAIN_EX 1
#define PQ_MM_DS_RULE_H_SD_P_MAIN_EX 1
#define PQ_MM_DS_RULE_FHD_P_MAIN_EX 1
#define PQ_MM_DS_RULE_H_FHD_P_MAIN_EX 1
#define PQ_MM_DS_RULE_4K_1K_P_MAIN_EX 1
#define PQ_MM_DS_RULE_4K_P_MAIN_EX 1

typedef enum
{
PQ_MM_DS_rule_L_SD_I_Main_Ex,
PQ_MM_DS_rule_SD_I_Main_Ex,
PQ_MM_DS_rule_H_SD_I_Main_Ex,
PQ_MM_DS_rule_FHD_I_Main_Ex,
PQ_MM_DS_rule_H_FHD_I_Main_Ex,
PQ_MM_DS_rule_4K_1K_I_Main_Ex,
PQ_MM_DS_rule_4K_I_Main_Ex,
PQ_MM_DS_rule_L_SD_P_Main_Ex,
PQ_MM_DS_rule_SD_P_Main_Ex,
PQ_MM_DS_rule_H_SD_P_Main_Ex,
PQ_MM_DS_rule_FHD_P_Main_Ex,
PQ_MM_DS_rule_H_FHD_P_Main_Ex,
PQ_MM_DS_rule_4K_1K_P_Main_Ex,
PQ_MM_DS_rule_4K_P_Main_Ex,
}
MST_MM_DS_rule_Index_Main_Ex;
extern U8 MST_MM_DS_rule_IP_Index_Main_Ex[PQ_MM_DS_rule_IP_NUM_Main_Ex];
extern U8 MST_MM_DS_rule_Array_Main_Ex[PQ_MM_DS_rule_NUM_Main_Ex][PQ_MM_DS_rule_IP_NUM_Main_Ex];

