#define CKGEN00_V004 0x204000

//Page CKGEN00_V004
#define REG_0000_CKGEN00_V004 (CKGEN00_V004 + 0x000)
	#define REG_0000_CKGEN00_V004_REG_CKG_G_CALC_0000 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0000_CKGEN00_V004_REG_CKG_I_CALC_0000 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0000_CKGEN00_V004_REG_CKG_S_CALC_0000 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0008_CKGEN00_V004 (CKGEN00_V004 + 0x008)
	#define REG_0008_CKGEN00_V004_REG_CKG_G_CORECLK_0008 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0008_CKGEN00_V004_REG_CKG_I_CORECLK_0008 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0008_CKGEN00_V004_REG_CKG_S_CORECLK_0008 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0010_CKGEN00_V004 (CKGEN00_V004 + 0x010)
	#define REG_0010_CKGEN00_V004_REG_CKG_G_CORECLK_MID_0010 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0010_CKGEN00_V004_REG_CKG_I_CORECLK_MID_0010 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0010_CKGEN00_V004_REG_CKG_S_CORECLK_MID_0010 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0018_CKGEN00_V004 (CKGEN00_V004 + 0x018)
	#define REG_0018_CKGEN00_V004_REG_CKG_G_SCLK_0018 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0018_CKGEN00_V004_REG_CKG_I_SCLK_0018 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0018_CKGEN00_V004_REG_CKG_S_SCLK_0018 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0020_CKGEN00_V004 (CKGEN00_V004 + 0x020)
	#define REG_0020_CKGEN00_V004_REG_CKG_G_SCLK_MID_0020 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0020_CKGEN00_V004_REG_CKG_I_SCLK_MID_0020 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0020_CKGEN00_V004_REG_CKG_S_SCLK_MID_0020 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0028_CKGEN00_V004 (CKGEN00_V004 + 0x028)
	#define REG_0028_CKGEN00_V004_REG_CKG_I_BIU_0028 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0028_CKGEN00_V004_REG_CKG_S_BIU_0028 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0030_CKGEN00_V004 (CKGEN00_V004 + 0x030)
	#define REG_0030_CKGEN00_V004_REG_CKG_G_CALC_MCUSYS_0030 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0030_CKGEN00_V004_REG_CKG_I_CALC_MCUSYS_0030 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0030_CKGEN00_V004_REG_CKG_S_CALC_MCUSYS_0030 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0038_CKGEN00_V004 (CKGEN00_V004 + 0x038)
	#define REG_0038_CKGEN00_V004_REG_CKG_I_EMI0_MCUSYS_0038 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0038_CKGEN00_V004_REG_CKG_S_EMI0_MCUSYS_0038 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0040_CKGEN00_V004 (CKGEN00_V004 + 0x040)
	#define REG_0040_CKGEN00_V004_REG_CKG_S_EMI1_MCUSYS_0040 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0050_CKGEN00_V004 (CKGEN00_V004 + 0x050)
	#define REG_0050_CKGEN00_V004_REG_CKG_S_MIPS_SYN_ARMPLL_0050 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_0058_CKGEN00_V004 (CKGEN00_V004 + 0x058)
	#define REG_0058_CKGEN00_V004_REG_CKG_I_XTAL_MPLL_0058 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0058_CKGEN00_V004_REG_CKG_S_XTAL_MPLL_0058 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0060_CKGEN00_V004 (CKGEN00_V004 + 0x060)
	#define REG_0060_CKGEN00_V004_REG_CKG_PTP_0060 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0068_CKGEN00_V004 (CKGEN00_V004 + 0x068)
	#define REG_0068_CKGEN00_V004_REG_CKG_I_LZMA_MCUSYS_0068 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0068_CKGEN00_V004_REG_CKG_S_LZMA_MCUSYS_0068 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0070_CKGEN00_V004 (CKGEN00_V004 + 0x070)
	#define REG_0070_CKGEN00_V004_REG_CKG_S_MPU_MCUSYS_0070 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_00C8_CKGEN00_V004 (CKGEN00_V004 + 0x0C8)
	#define REG_00C8_CKGEN00_V004_REG_CKG_I_GPU_GPU_PAR_GP_00C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_00CC_CKGEN00_V004 (CKGEN00_V004 + 0x0CC)
	#define REG_00CC_CKGEN00_V004_REG_FLOW_CTRL_RATE_GPU_PAR_GP_00CC Fld(5,0,AC_MSKB0)//[4:0]
	#define REG_00CC_CKGEN00_V004_REG_FLOW_CTRL_RATE_GPU_PAR_GP_SLD_00CC Fld(1,12,AC_MSKB1)//[12:12]
#define REG_0118_CKGEN00_V004 (CKGEN00_V004 + 0x118)
	#define REG_0118_CKGEN00_V004_REG_CKG_G_ZDEC_LZD_0118 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0118_CKGEN00_V004_REG_CKG_I_ZDEC_LZD_0118 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0118_CKGEN00_V004_REG_CKG_S_ZDEC_LZD_0118 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0118_CKGEN00_V004_REG_CKG_G_ZDEC_VLD_0118 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0118_CKGEN00_V004_REG_CKG_I_ZDEC_VLD_0118 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0118_CKGEN00_V004_REG_CKG_S_ZDEC_VLD_0118 Fld(2,10,AC_MSKB1)//[11:10]
#define REG_0120_CKGEN00_V004 (CKGEN00_V004 + 0x120)
	#define REG_0120_CKGEN00_V004_REG_CKG_G_DRAMC_CH0_0120 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0120_CKGEN00_V004_REG_CKG_I_DRAMC_CH0_0120 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0120_CKGEN00_V004_REG_CKG_S_DRAMC_CH0_0120 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0128_CKGEN00_V004 (CKGEN00_V004 + 0x128)
	#define REG_0128_CKGEN00_V004_REG_CKG_G_DRAMC_CH2_0128 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0128_CKGEN00_V004_REG_CKG_I_DRAMC_CH2_0128 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0128_CKGEN00_V004_REG_CKG_S_DRAMC_CH2_0128 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0130_CKGEN00_V004 (CKGEN00_V004 + 0x130)
	#define REG_0130_CKGEN00_V004_REG_CKG_DRAMC_CH4_0130 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0138_CKGEN00_V004 (CKGEN00_V004 + 0x138)
	#define REG_0138_CKGEN00_V004_REG_CKG_G_DRAMC0_CGCLK_FAST_CHA_0138 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0138_CKGEN00_V004_REG_CKG_I_DRAMC0_CGCLK_FAST_CHA_0138 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0138_CKGEN00_V004_REG_CKG_S_DRAMC0_CGCLK_FAST_CHA_0138 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0138_CKGEN00_V004_REG_CKG_G_DRAMC0_CGCLK_FAST_CHB_0138 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0138_CKGEN00_V004_REG_CKG_I_DRAMC0_CGCLK_FAST_CHB_0138 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0138_CKGEN00_V004_REG_CKG_S_DRAMC0_CGCLK_FAST_CHB_0138 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0138_CKGEN00_V004_REG_CKG_G_DRAMC1_CGCLK_FAST_CHA_0138 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0138_CKGEN00_V004_REG_CKG_I_DRAMC1_CGCLK_FAST_CHA_0138 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0138_CKGEN00_V004_REG_CKG_G_DRAMC1_CGCLK_FAST_CHB_0138 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0138_CKGEN00_V004_REG_CKG_I_DRAMC1_CGCLK_FAST_CHB_0138 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0138_CKGEN00_V004_REG_CKG_S_DRAMC1_CGCLK_FAST_CHB_0138 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_013C_CKGEN00_V004 (CKGEN00_V004 + 0x13C)
	#define REG_013C_CKGEN00_V004_REG_CKG_G_MCU_NONPM_DRAMC0_013C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_013C_CKGEN00_V004_REG_CKG_I_MCU_NONPM_DRAMC0_013C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_013C_CKGEN00_V004_REG_CKG_S_MCU_NONPM_DRAMC0_013C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_013C_CKGEN00_V004_REG_CKG_G_MCU_NONPM_DRAMC1_013C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_013C_CKGEN00_V004_REG_CKG_I_MCU_NONPM_DRAMC1_013C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_013C_CKGEN00_V004_REG_CKG_S_MCU_NONPM_DRAMC1_013C Fld(1,10,AC_MSKB1)//[10:10]
#define REG_0140_CKGEN00_V004 (CKGEN00_V004 + 0x140)
	#define REG_0140_CKGEN00_V004_REG_CKG_G_XTAL_24M_DRAMC0_0140 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0140_CKGEN00_V004_REG_CKG_I_XTAL_24M_DRAMC0_0140 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0140_CKGEN00_V004_REG_CKG_G_XTAL_24M_DRAMC1_0140 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0140_CKGEN00_V004_REG_CKG_I_XTAL_24M_DRAMC1_0140 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0148_CKGEN00_V004 (CKGEN00_V004 + 0x148)
	#define REG_0148_CKGEN00_V004_REG_CKG_G_MPLL_208M_CHA_DRAMC0_0148 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0148_CKGEN00_V004_REG_CKG_I_MPLL_208M_CHA_DRAMC0_0148 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0148_CKGEN00_V004_REG_CKG_G_MPLL_208M_CHB_DRAMC0_0148 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0148_CKGEN00_V004_REG_CKG_I_MPLL_208M_CHB_DRAMC0_0148 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0148_CKGEN00_V004_REG_CKG_G_MPLL_208M_CHA_DRAMC1_0148 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0148_CKGEN00_V004_REG_CKG_I_MPLL_208M_CHA_DRAMC1_0148 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0148_CKGEN00_V004_REG_CKG_G_MPLL_208M_CHB_DRAMC1_0148 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0148_CKGEN00_V004_REG_CKG_I_MPLL_208M_CHB_DRAMC1_0148 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0150_CKGEN00_V004 (CKGEN00_V004 + 0x150)
	#define REG_0150_CKGEN00_V004_REG_CKG_G_MPLL_208M_MD32_DRAMC0_0150 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0150_CKGEN00_V004_REG_CKG_I_MPLL_208M_MD32_DRAMC0_0150 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0150_CKGEN00_V004_REG_CKG_G_MPLL_432M_DRAMC0_0150 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0150_CKGEN00_V004_REG_CKG_I_MPLL_432M_DRAMC0_0150 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0150_CKGEN00_V004_REG_CKG_G_MPLL_208M_MD32_DRAMC1_0150 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0150_CKGEN00_V004_REG_CKG_I_MPLL_208M_MD32_DRAMC1_0150 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0150_CKGEN00_V004_REG_CKG_G_MPLL_432M_DRAMC1_0150 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0150_CKGEN00_V004_REG_CKG_I_MPLL_432M_DRAMC1_0150 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0168_CKGEN00_V004 (CKGEN00_V004 + 0x168)
	#define REG_0168_CKGEN00_V004_REG_CKG_G_EMI0_IP_WRAP_0168 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0168_CKGEN00_V004_REG_CKG_I_EMI0_IP_WRAP_0168 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0170_CKGEN00_V004 (CKGEN00_V004 + 0x170)
	#define REG_0170_CKGEN00_V004_REG_CKG_G_EMI1_IP_WRAP_0170 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0170_CKGEN00_V004_REG_CKG_I_EMI1_IP_WRAP_0170 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0178_CKGEN00_V004 (CKGEN00_V004 + 0x178)
	#define REG_0178_CKGEN00_V004_REG_CKG_G_EMI2_IP_WRAP_0178 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0178_CKGEN00_V004_REG_CKG_I_EMI2_IP_WRAP_0178 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0180_CKGEN00_V004 (CKGEN00_V004 + 0x180)
	#define REG_0180_CKGEN00_V004_REG_CKG_G_IP_WRAP_0180 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0180_CKGEN00_V004_REG_CKG_I_IP_WRAP_0180 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0188_CKGEN00_V004 (CKGEN00_V004 + 0x188)
	#define REG_0188_CKGEN00_V004_REG_CKG_G_EMI0_DEB_IP_WRAP_0188 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0188_CKGEN00_V004_REG_CKG_I_EMI0_DEB_IP_WRAP_0188 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0190_CKGEN00_V004 (CKGEN00_V004 + 0x190)
	#define REG_0190_CKGEN00_V004_REG_CKG_G_EMI1_DEB_IP_WRAP_0190 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0190_CKGEN00_V004_REG_CKG_I_EMI1_DEB_IP_WRAP_0190 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0198_CKGEN00_V004 (CKGEN00_V004 + 0x198)
	#define REG_0198_CKGEN00_V004_REG_CKG_G_EMI2_DEB_IP_WRAP_0198 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0198_CKGEN00_V004_REG_CKG_I_EMI2_DEB_IP_WRAP_0198 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01A0_CKGEN00_V004 (CKGEN00_V004 + 0x1A0)
	#define REG_01A0_CKGEN00_V004_REG_CKG_G_XTAL_12M_IP_WRAP_01A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01A0_CKGEN00_V004_REG_CKG_I_XTAL_12M_IP_WRAP_01A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01A8_CKGEN00_V004 (CKGEN00_V004 + 0x1A8)
	#define REG_01A8_CKGEN00_V004_REG_CKG_G_XTAL_24M_IP_WRAP_01A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01A8_CKGEN00_V004_REG_CKG_I_XTAL_24M_IP_WRAP_01A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01B0_CKGEN00_V004 (CKGEN00_V004 + 0x1B0)
	#define REG_01B0_CKGEN00_V004_REG_CKG_G_DRAMC0_PLL54M_108M_01B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01B0_CKGEN00_V004_REG_CKG_I_DRAMC0_PLL54M_108M_01B0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01B0_CKGEN00_V004_REG_CKG_G_DRAMC1_PLL54M_108M_01B0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01B0_CKGEN00_V004_REG_CKG_I_DRAMC1_PLL54M_108M_01B0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_01D8_CKGEN00_V004 (CKGEN00_V004 + 0x1D8)
	#define REG_01D8_CKGEN00_V004_REG_CKG_G_SMI_01D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01D8_CKGEN00_V004_REG_CKG_I_SMI_01D8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01D8_CKGEN00_V004_REG_CKG_S_SMI_01D8 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_01D8_CKGEN00_V004_REG_CKG_G_SMI_DEMOD0_01D8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01D8_CKGEN00_V004_REG_CKG_I_SMI_DEMOD0_01D8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_01DC_CKGEN00_V004 (CKGEN00_V004 + 0x1DC)
	#define REG_01DC_CKGEN00_V004_REG_CKG_G_SMI_SCIP_01DC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_01DC_CKGEN00_V004_REG_CKG_I_SMI_SCIP_01DC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01DC_CKGEN00_V004_REG_CKG_G_SMI_SCBE_01DC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01DC_CKGEN00_V004_REG_CKG_I_SMI_SCBE_01DC Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01DC_CKGEN00_V004_REG_CKG_G_SMI_SCTC_01DC Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_01DC_CKGEN00_V004_REG_CKG_I_SMI_SCTC_01DC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_01E0_CKGEN00_V004 (CKGEN00_V004 + 0x1E0)
	#define REG_01E0_CKGEN00_V004_REG_CKG_G_SMI_VDEC_CORE0_01E0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_01E0_CKGEN00_V004_REG_CKG_I_SMI_VDEC_CORE0_01E0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_01E0_CKGEN00_V004_REG_CKG_G_SMI_VDEC_GCE_01E0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01E0_CKGEN00_V004_REG_CKG_I_SMI_VDEC_GCE_01E0 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_01E8_CKGEN00_V004 (CKGEN00_V004 + 0x1E8)
	#define REG_01E8_CKGEN00_V004_REG_CKG_G_VIVA_SMI_01E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01E8_CKGEN00_V004_REG_CKG_I_VIVA_SMI_01E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01E8_CKGEN00_V004_REG_CKG_G_SMI_MHEG5_01E8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01E8_CKGEN00_V004_REG_CKG_I_SMI_MHEG5_01E8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01E8_CKGEN00_V004_REG_CKG_G_SMI_HDMIRX_01E8 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_01E8_CKGEN00_V004_REG_CKG_I_SMI_HDMIRX_01E8 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_01E8_CKGEN00_V004_REG_CKG_G_SMI_TSP_01E8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01E8_CKGEN00_V004_REG_CKG_I_SMI_TSP_01E8 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_01EC_CKGEN00_V004 (CKGEN00_V004 + 0x1EC)
	#define REG_01EC_CKGEN00_V004_REG_CKG_G_SMI_FRCCORE1_01EC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01EC_CKGEN00_V004_REG_CKG_I_SMI_FRCCORE1_01EC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01EC_CKGEN00_V004_REG_CKG_G_SMI_FRCCORE2_01EC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_01EC_CKGEN00_V004_REG_CKG_I_SMI_FRCCORE2_01EC Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01EC_CKGEN00_V004_REG_CKG_G_SMI_FRCCORE3_01EC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01EC_CKGEN00_V004_REG_CKG_I_SMI_FRCCORE3_01EC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01EC_CKGEN00_V004_REG_CKG_G_SMI_FRCMISC_01EC Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_01EC_CKGEN00_V004_REG_CKG_I_SMI_FRCMISC_01EC Fld(1,7,AC_MSKB0)//[7:7]
#define REG_01F0_CKGEN00_V004 (CKGEN00_V004 + 0x1F0)
	#define REG_01F0_CKGEN00_V004_REG_CKG_G_SMI_AURV55_01F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01F0_CKGEN00_V004_REG_CKG_I_SMI_AURV55_01F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_01F4_CKGEN00_V004 (CKGEN00_V004 + 0x1F4)
	#define REG_01F4_CKGEN00_V004_REG_CKG_VIVA_SMI_BRG_01F4 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_01F8_CKGEN00_V004 (CKGEN00_V004 + 0x1F8)
	#define REG_01F8_CKGEN00_V004_REG_CKG_G_GCE_F26M_01F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01F8_CKGEN00_V004_REG_CKG_I_GCE_F26M_01F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01F8_CKGEN00_V004_REG_CKG_G_VDEC_SYS_F_VDEC_CORE0_01F8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01F8_CKGEN00_V004_REG_CKG_I_VDEC_SYS_F_VDEC_CORE0_01F8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01F8_CKGEN00_V004_REG_CKG_G_VDEC_SYS_S_VDEC_CORE0_01F8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01F8_CKGEN00_V004_REG_CKG_I_VDEC_SYS_S_VDEC_CORE0_01F8 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01F8_CKGEN00_V004_REG_CKG_G_XIU_VDEC_SOC_01F8 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01F8_CKGEN00_V004_REG_CKG_I_XIU_VDEC_SOC_01F8 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_01FC_CKGEN00_V004 (CKGEN00_V004 + 0x1FC)
	#define REG_01FC_CKGEN00_V004_REG_CKG_G_SMI_VDEC_CORE0_MERGE_01FC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_01FC_CKGEN00_V004_REG_CKG_I_SMI_VDEC_CORE0_MERGE_01FC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_01FC_CKGEN00_V004_REG_CKG_G_VDEC_SYS_F_VDEC_CORE0_MERGE_01FC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01FC_CKGEN00_V004_REG_CKG_I_VDEC_SYS_F_VDEC_CORE0_MERGE_01FC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_01FC_CKGEN00_V004_REG_CKG_G_VDEC_SYS_S_VDEC_CORE0_MERGE_01FC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_01FC_CKGEN00_V004_REG_CKG_I_VDEC_SYS_S_VDEC_CORE0_MERGE_01FC Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_01FC_CKGEN00_V004_REG_CKG_G_VDEC_BUS_VDEC_CORE0_MERGE_01FC Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_01FC_CKGEN00_V004_REG_CKG_I_VDEC_BUS_VDEC_CORE0_MERGE_01FC Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0260_CKGEN00_V004 (CKGEN00_V004 + 0x260)
	#define REG_0260_CKGEN00_V004_REG_CKG_FRC_IMI_0260 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_0268_CKGEN00_V004 (CKGEN00_V004 + 0x268)
	#define REG_0268_CKGEN00_V004_REG_CKG_G_IMI_0268 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0268_CKGEN00_V004_REG_CKG_I_IMI_0268 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0268_CKGEN00_V004_REG_CKG_S_IMI_0268 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0268_CKGEN00_V004_REG_CKG_G_IMI_TSP_0268 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0268_CKGEN00_V004_REG_CKG_I_IMI_TSP_0268 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0270_CKGEN00_V004 (CKGEN00_V004 + 0x270)
	#define REG_0270_CKGEN00_V004_REG_CKG_G_LZMA_0270 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0270_CKGEN00_V004_REG_CKG_I_LZMA_0270 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0270_CKGEN00_V004_REG_CKG_S_LZMA_0270 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0278_CKGEN00_V004 (CKGEN00_V004 + 0x278)
	#define REG_0278_CKGEN00_V004_REG_CKG_G_XTAL_12M_0278 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0278_CKGEN00_V004_REG_CKG_I_XTAL_12M_0278 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0278_CKGEN00_V004_REG_CKG_G_XTAL_12M_MHEG5_0278 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0278_CKGEN00_V004_REG_CKG_I_XTAL_12M_MHEG5_0278 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0278_CKGEN00_V004_REG_CKG_G_XTAL_12M_GPU_PAR_GP_0278 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0278_CKGEN00_V004_REG_CKG_I_XTAL_12M_GPU_PAR_GP_0278 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_0280_CKGEN00_V004 (CKGEN00_V004 + 0x280)
	#define REG_0280_CKGEN00_V004_REG_CKG_G_XTAL_24M_0280 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0280_CKGEN00_V004_REG_CKG_I_XTAL_24M_0280 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0280_CKGEN00_V004_REG_CKG_G_XTAL_24M_MHEG5_0280 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0280_CKGEN00_V004_REG_CKG_I_XTAL_24M_MHEG5_0280 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0280_CKGEN00_V004_REG_CKG_G_XTAL_24M_GPU_PAR_GP_0280 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_0280_CKGEN00_V004_REG_CKG_I_XTAL_24M_GPU_PAR_GP_0280 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_0284_CKGEN00_V004 (CKGEN00_V004 + 0x284)
	#define REG_0284_CKGEN00_V004_REG_CKG_G_XTAL_24M_TSP_0284 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0284_CKGEN00_V004_REG_CKG_I_XTAL_24M_TSP_0284 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02C0_CKGEN00_V004 (CKGEN00_V004 + 0x2C0)
	#define REG_02C0_CKGEN00_V004_REG_CKG_G_XTAL_12M_DEMOD0_02C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02C0_CKGEN00_V004_REG_CKG_I_XTAL_12M_DEMOD0_02C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02C8_CKGEN00_V004 (CKGEN00_V004 + 0x2C8)
	#define REG_02C8_CKGEN00_V004_REG_CKG_G_XTAL_24M_DEMOD0_02C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02C8_CKGEN00_V004_REG_CKG_I_XTAL_24M_DEMOD0_02C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02D0_CKGEN00_V004 (CKGEN00_V004 + 0x2D0)
	#define REG_02D0_CKGEN00_V004_REG_CKG_G_ACIFIR_02D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02D0_CKGEN00_V004_REG_CKG_I_ACIFIR_02D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02D8_CKGEN00_V004 (CKGEN00_V004 + 0x2D8)
	#define REG_02D8_CKGEN00_V004_REG_CKG_G_ADCD_02D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02D8_CKGEN00_V004_REG_CKG_I_ADCD_02D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02E0_CKGEN00_V004 (CKGEN00_V004 + 0x2E0)
	#define REG_02E0_CKGEN00_V004_REG_CKG_G_ATSC200_PH1_02E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02E0_CKGEN00_V004_REG_CKG_I_ATSC200_PH1_02E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02E8_CKGEN00_V004 (CKGEN00_V004 + 0x2E8)
	#define REG_02E8_CKGEN00_V004_REG_CKG_G_ATSC200_PH3_02E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02E8_CKGEN00_V004_REG_CKG_I_ATSC200_PH3_02E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02F0_CKGEN00_V004 (CKGEN00_V004 + 0x2F0)
	#define REG_02F0_CKGEN00_V004_REG_CKG_G_ATSC25_02F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02F0_CKGEN00_V004_REG_CKG_I_ATSC25_02F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_02F8_CKGEN00_V004 (CKGEN00_V004 + 0x2F8)
	#define REG_02F8_CKGEN00_V004_REG_CKG_G_ATSC400_02F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_02F8_CKGEN00_V004_REG_CKG_I_ATSC400_02F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0300_CKGEN00_V004 (CKGEN00_V004 + 0x300)
	#define REG_0300_CKGEN00_V004_REG_CKG_G_ATSC50_0300 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0300_CKGEN00_V004_REG_CKG_I_ATSC50_0300 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0308_CKGEN00_V004 (CKGEN00_V004 + 0x308)
	#define REG_0308_CKGEN00_V004_REG_CKG_G_ATSC_ADCD_SYNC_0308 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0308_CKGEN00_V004_REG_CKG_I_ATSC_ADCD_SYNC_0308 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0310_CKGEN00_V004 (CKGEN00_V004 + 0x310)
	#define REG_0310_CKGEN00_V004_REG_CKG_G_ATSC_CE25_0310 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0310_CKGEN00_V004_REG_CKG_I_ATSC_CE25_0310 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0318_CKGEN00_V004 (CKGEN00_V004 + 0x318)
	#define REG_0318_CKGEN00_V004_REG_CKG_G_ATSC_EQ25_0318 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0318_CKGEN00_V004_REG_CKG_I_ATSC_EQ25_0318 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0320_CKGEN00_V004 (CKGEN00_V004 + 0x320)
	#define REG_0320_CKGEN00_V004_REG_CKG_G_DMD_DMA_0320 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0320_CKGEN00_V004_REG_CKG_I_DMD_DMA_0320 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0328_CKGEN00_V004 (CKGEN00_V004 + 0x328)
	#define REG_0328_CKGEN00_V004_REG_CKG_G_DTMB_ADC_0328 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0328_CKGEN00_V004_REG_CKG_I_DTMB_ADC_0328 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0330_CKGEN00_V004 (CKGEN00_V004 + 0x330)
	#define REG_0330_CKGEN00_V004_REG_CKG_G_DTMB_BCH_DEMOD0_0330 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0330_CKGEN00_V004_REG_CKG_I_DTMB_BCH_DEMOD0_0330 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0338_CKGEN00_V004 (CKGEN00_V004 + 0x338)
	#define REG_0338_CKGEN00_V004_REG_CKG_G_DTMB_EQ0P25X_0338 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0338_CKGEN00_V004_REG_CKG_I_DTMB_EQ0P25X_0338 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0340_CKGEN00_V004 (CKGEN00_V004 + 0x340)
	#define REG_0340_CKGEN00_V004_REG_CKG_G_DTMB_EQ0P5X_0340 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0340_CKGEN00_V004_REG_CKG_I_DTMB_EQ0P5X_0340 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0348_CKGEN00_V004 (CKGEN00_V004 + 0x348)
	#define REG_0348_CKGEN00_V004_REG_CKG_G_DTMB_EQ1X_0348 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0348_CKGEN00_V004_REG_CKG_I_DTMB_EQ1X_0348 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0350_CKGEN00_V004 (CKGEN00_V004 + 0x350)
	#define REG_0350_CKGEN00_V004_REG_CKG_G_DTMB_EQ2X_0350 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0350_CKGEN00_V004_REG_CKG_I_DTMB_EQ2X_0350 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0358_CKGEN00_V004 (CKGEN00_V004 + 0x358)
	#define REG_0358_CKGEN00_V004_REG_CKG_G_DTMB_EQ2X_INNER12X_0358 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0358_CKGEN00_V004_REG_CKG_I_DTMB_EQ2X_INNER12X_0358 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0360_CKGEN00_V004 (CKGEN00_V004 + 0x360)
	#define REG_0360_CKGEN00_V004_REG_CKG_G_DTMB_EQ2X_INNER2X_12X_0360 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0360_CKGEN00_V004_REG_CKG_I_DTMB_EQ2X_INNER2X_12X_0360 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0368_CKGEN00_V004 (CKGEN00_V004 + 0x368)
	#define REG_0368_CKGEN00_V004_REG_CKG_G_DTMB_EQ2X_INNER4X_0368 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0368_CKGEN00_V004_REG_CKG_I_DTMB_EQ2X_INNER4X_0368 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0370_CKGEN00_V004 (CKGEN00_V004 + 0x370)
	#define REG_0370_CKGEN00_V004_REG_CKG_G_DTMB_INNER12X_0370 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0370_CKGEN00_V004_REG_CKG_I_DTMB_INNER12X_0370 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0378_CKGEN00_V004 (CKGEN00_V004 + 0x378)
	#define REG_0378_CKGEN00_V004_REG_CKG_G_DTMB_INNER12X_EQ0P25X_0378 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0378_CKGEN00_V004_REG_CKG_I_DTMB_INNER12X_EQ0P25X_0378 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0380_CKGEN00_V004 (CKGEN00_V004 + 0x380)
	#define REG_0380_CKGEN00_V004_REG_CKG_G_DTMB_INNER12X_INNER4X_0380 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0380_CKGEN00_V004_REG_CKG_I_DTMB_INNER12X_INNER4X_0380 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0388_CKGEN00_V004 (CKGEN00_V004 + 0x388)
	#define REG_0388_CKGEN00_V004_REG_CKG_G_DTMB_INNER12X_INNER6X_0388 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0388_CKGEN00_V004_REG_CKG_I_DTMB_INNER12X_INNER6X_0388 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0390_CKGEN00_V004 (CKGEN00_V004 + 0x390)
	#define REG_0390_CKGEN00_V004_REG_CKG_G_DTMB_INNER12X_INNER8X_TAP_COM_0390 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0390_CKGEN00_V004_REG_CKG_I_DTMB_INNER12X_INNER8X_TAP_COM_0390 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0398_CKGEN00_V004 (CKGEN00_V004 + 0x398)
	#define REG_0398_CKGEN00_V004_REG_CKG_G_DTMB_INNER1X_0398 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0398_CKGEN00_V004_REG_CKG_I_DTMB_INNER1X_0398 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03A0_CKGEN00_V004 (CKGEN00_V004 + 0x3A0)
	#define REG_03A0_CKGEN00_V004_REG_CKG_G_DTMB_INNER1X_ATSC25_03A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03A0_CKGEN00_V004_REG_CKG_I_DTMB_INNER1X_ATSC25_03A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03A8_CKGEN00_V004 (CKGEN00_V004 + 0x3A8)
	#define REG_03A8_CKGEN00_V004_REG_CKG_G_DTMB_INNER24X_03A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03A8_CKGEN00_V004_REG_CKG_I_DTMB_INNER24X_03A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03B0_CKGEN00_V004 (CKGEN00_V004 + 0x3B0)
	#define REG_03B0_CKGEN00_V004_REG_CKG_G_DTMB_INNER24X_ATSC_400_03B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03B0_CKGEN00_V004_REG_CKG_I_DTMB_INNER24X_ATSC_400_03B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03B8_CKGEN00_V004 (CKGEN00_V004 + 0x3B8)
	#define REG_03B8_CKGEN00_V004_REG_CKG_G_DTMB_INNER2X_03B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03B8_CKGEN00_V004_REG_CKG_I_DTMB_INNER2X_03B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03C0_CKGEN00_V004 (CKGEN00_V004 + 0x3C0)
	#define REG_03C0_CKGEN00_V004_REG_CKG_G_DTMB_INNER2X_4X_SR1X_03C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03C0_CKGEN00_V004_REG_CKG_I_DTMB_INNER2X_4X_SR1X_03C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03C8_CKGEN00_V004 (CKGEN00_V004 + 0x3C8)
	#define REG_03C8_CKGEN00_V004_REG_CKG_G_DTMB_INNER2X_SR0P5X_03C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03C8_CKGEN00_V004_REG_CKG_I_DTMB_INNER2X_SR0P5X_03C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03D0_CKGEN00_V004 (CKGEN00_V004 + 0x3D0)
	#define REG_03D0_CKGEN00_V004_REG_CKG_G_DTMB_INNER4X_03D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03D0_CKGEN00_V004_REG_CKG_I_DTMB_INNER4X_03D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03D8_CKGEN00_V004 (CKGEN00_V004 + 0x3D8)
	#define REG_03D8_CKGEN00_V004_REG_CKG_G_DTMB_INNER4X_ATSC50_03D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03D8_CKGEN00_V004_REG_CKG_I_DTMB_INNER4X_ATSC50_03D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03E0_CKGEN00_V004 (CKGEN00_V004 + 0x3E0)
	#define REG_03E0_CKGEN00_V004_REG_CKG_G_DTMB_INNER4X_SR1X_03E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03E0_CKGEN00_V004_REG_CKG_I_DTMB_INNER4X_SR1X_03E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03E8_CKGEN00_V004 (CKGEN00_V004 + 0x3E8)
	#define REG_03E8_CKGEN00_V004_REG_CKG_G_DTMB_INNER6X_03E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03E8_CKGEN00_V004_REG_CKG_I_DTMB_INNER6X_03E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03F0_CKGEN00_V004 (CKGEN00_V004 + 0x3F0)
	#define REG_03F0_CKGEN00_V004_REG_CKG_G_DTMB_INNER8X_03F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03F0_CKGEN00_V004_REG_CKG_I_DTMB_INNER8X_03F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_03F8_CKGEN00_V004 (CKGEN00_V004 + 0x3F8)
	#define REG_03F8_CKGEN00_V004_REG_CKG_G_DTMB_INNER8X_TAP_COM_03F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_03F8_CKGEN00_V004_REG_CKG_I_DTMB_INNER8X_TAP_COM_03F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0400_CKGEN00_V004 (CKGEN00_V004 + 0x400)
	#define REG_0400_CKGEN00_V004_REG_CKG_G_DTMB_LDPC_0400 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0400_CKGEN00_V004_REG_CKG_I_DTMB_LDPC_0400 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0408_CKGEN00_V004 (CKGEN00_V004 + 0x408)
	#define REG_0408_CKGEN00_V004_REG_CKG_G_DTMB_LDPC2X_0408 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0408_CKGEN00_V004_REG_CKG_I_DTMB_LDPC2X_0408 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0410_CKGEN00_V004 (CKGEN00_V004 + 0x410)
	#define REG_0410_CKGEN00_V004_REG_CKG_G_DTMB_OUTER1X_0410 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0410_CKGEN00_V004_REG_CKG_I_DTMB_OUTER1X_0410 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0418_CKGEN00_V004 (CKGEN00_V004 + 0x418)
	#define REG_0418_CKGEN00_V004_REG_CKG_G_DTMB_OUTER2X_0418 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0418_CKGEN00_V004_REG_CKG_I_DTMB_OUTER2X_0418 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0420_CKGEN00_V004 (CKGEN00_V004 + 0x420)
	#define REG_0420_CKGEN00_V004_REG_CKG_G_DTMB_OUTER8X_0420 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0420_CKGEN00_V004_REG_CKG_I_DTMB_OUTER8X_0420 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0428_CKGEN00_V004 (CKGEN00_V004 + 0x428)
	#define REG_0428_CKGEN00_V004_REG_CKG_G_DTMB_SRAM_DUMP_0428 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0428_CKGEN00_V004_REG_CKG_I_DTMB_SRAM_DUMP_0428 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0430_CKGEN00_V004 (CKGEN00_V004 + 0x430)
	#define REG_0430_CKGEN00_V004_REG_CKG_G_DVBS2_BCH_0430 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0430_CKGEN00_V004_REG_CKG_I_DVBS2_BCH_0430 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0438_CKGEN00_V004 (CKGEN00_V004 + 0x438)
	#define REG_0438_CKGEN00_V004_REG_CKG_G_DVBS2_DISEQC_0438 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0438_CKGEN00_V004_REG_CKG_I_DVBS2_DISEQC_0438 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0440_CKGEN00_V004 (CKGEN00_V004 + 0x440)
	#define REG_0440_CKGEN00_V004_REG_CKG_G_DVBS2_INNER_0440 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0440_CKGEN00_V004_REG_CKG_I_DVBS2_INNER_0440 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0448_CKGEN00_V004 (CKGEN00_V004 + 0x448)
	#define REG_0448_CKGEN00_V004_REG_CKG_G_DVBS2_OPPRO_0448 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0448_CKGEN00_V004_REG_CKG_I_DVBS2_OPPRO_0448 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0450_CKGEN00_V004 (CKGEN00_V004 + 0x450)
	#define REG_0450_CKGEN00_V004_REG_CKG_G_DVBS_OUTER1X_0450 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0450_CKGEN00_V004_REG_CKG_I_DVBS_OUTER1X_0450 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0458_CKGEN00_V004 (CKGEN00_V004 + 0x458)
	#define REG_0458_CKGEN00_V004_REG_CKG_G_DVBS_OUTER2X_0458 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0458_CKGEN00_V004_REG_CKG_I_DVBS_OUTER2X_0458 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0460_CKGEN00_V004 (CKGEN00_V004 + 0x460)
	#define REG_0460_CKGEN00_V004_REG_CKG_G_DVBS_OUTER2X_DVBT_OUTER2X_0460 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0460_CKGEN00_V004_REG_CKG_I_DVBS_OUTER2X_DVBT_OUTER2X_0460 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0468_CKGEN00_V004 (CKGEN00_V004 + 0x468)
	#define REG_0468_CKGEN00_V004_REG_CKG_G_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X_0468 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0468_CKGEN00_V004_REG_CKG_I_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X_0468 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0470_CKGEN00_V004 (CKGEN00_V004 + 0x470)
	#define REG_0470_CKGEN00_V004_REG_CKG_G_DVBS_OUTER2X_DVBT_OUTER2X_MIU_0470 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0470_CKGEN00_V004_REG_CKG_I_DVBS_OUTER2X_DVBT_OUTER2X_MIU_0470 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0478_CKGEN00_V004 (CKGEN00_V004 + 0x478)
	#define REG_0478_CKGEN00_V004_REG_CKG_G_DVBT2_INNER1X_0478 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0478_CKGEN00_V004_REG_CKG_I_DVBT2_INNER1X_0478 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0480_CKGEN00_V004 (CKGEN00_V004 + 0x480)
	#define REG_0480_CKGEN00_V004_REG_CKG_G_DVBT2_INNER2X_0480 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0480_CKGEN00_V004_REG_CKG_I_DVBT2_INNER2X_0480 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0488_CKGEN00_V004 (CKGEN00_V004 + 0x488)
	#define REG_0488_CKGEN00_V004_REG_CKG_G_DVBT2_INNER2X_SRD0P5X_0488 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0488_CKGEN00_V004_REG_CKG_I_DVBT2_INNER2X_SRD0P5X_0488 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0490_CKGEN00_V004 (CKGEN00_V004 + 0x490)
	#define REG_0490_CKGEN00_V004_REG_CKG_G_DVBT2_INNER4X_0490 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0490_CKGEN00_V004_REG_CKG_I_DVBT2_INNER4X_0490 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0498_CKGEN00_V004 (CKGEN00_V004 + 0x498)
	#define REG_0498_CKGEN00_V004_REG_CKG_G_DVBT2_INNER4X_DVBTC_RS_0498 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0498_CKGEN00_V004_REG_CKG_I_DVBT2_INNER4X_DVBTC_RS_0498 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04A0_CKGEN00_V004 (CKGEN00_V004 + 0x4A0)
	#define REG_04A0_CKGEN00_V004_REG_CKG_G_DVBT2_INNER4X_S2_INNER_04A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04A0_CKGEN00_V004_REG_CKG_I_DVBT2_INNER4X_S2_INNER_04A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04A8_CKGEN00_V004 (CKGEN00_V004 + 0x4A8)
	#define REG_04A8_CKGEN00_V004_REG_CKG_G_DVBT_INNER1X_04A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04A8_CKGEN00_V004_REG_CKG_I_DVBT_INNER1X_04A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04B0_CKGEN00_V004 (CKGEN00_V004 + 0x4B0)
	#define REG_04B0_CKGEN00_V004_REG_CKG_G_DVBT_INNER2X_04B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04B0_CKGEN00_V004_REG_CKG_I_DVBT_INNER2X_04B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04B8_CKGEN00_V004 (CKGEN00_V004 + 0x4B8)
	#define REG_04B8_CKGEN00_V004_REG_CKG_G_DVBT_INNER2X_SRD0P5X_04B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04B8_CKGEN00_V004_REG_CKG_I_DVBT_INNER2X_SRD0P5X_04B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04C0_CKGEN00_V004 (CKGEN00_V004 + 0x4C0)
	#define REG_04C0_CKGEN00_V004_REG_CKG_G_DVBT_INNER4X_04C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04C0_CKGEN00_V004_REG_CKG_I_DVBT_INNER4X_04C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04C8_CKGEN00_V004 (CKGEN00_V004 + 0x4C8)
	#define REG_04C8_CKGEN00_V004_REG_CKG_G_DVBT_OUTER1X_DEMOD0_04C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04C8_CKGEN00_V004_REG_CKG_I_DVBT_OUTER1X_DEMOD0_04C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04D0_CKGEN00_V004 (CKGEN00_V004 + 0x4D0)
	#define REG_04D0_CKGEN00_V004_REG_CKG_G_DVBT_OUTER2X_04D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04D0_CKGEN00_V004_REG_CKG_I_DVBT_OUTER2X_04D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04D8_CKGEN00_V004 (CKGEN00_V004 + 0x4D8)
	#define REG_04D8_CKGEN00_V004_REG_CKG_G_DVBTC_ADC_04D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04D8_CKGEN00_V004_REG_CKG_I_DVBTC_ADC_04D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04E0_CKGEN00_V004 (CKGEN00_V004 + 0x4E0)
	#define REG_04E0_CKGEN00_V004_REG_CKG_G_DVBTC_OUTER2X_04E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04E0_CKGEN00_V004_REG_CKG_I_DVBTC_OUTER2X_04E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04E8_CKGEN00_V004 (CKGEN00_V004 + 0x4E8)
	#define REG_04E8_CKGEN00_V004_REG_CKG_G_DVBTC_OUTER2X_ISDBT_OUTER_RS_04E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04E8_CKGEN00_V004_REG_CKG_I_DVBTC_OUTER2X_ISDBT_OUTER_RS_04E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04F0_CKGEN00_V004 (CKGEN00_V004 + 0x4F0)
	#define REG_04F0_CKGEN00_V004_REG_CKG_G_DVBTC_RS_04F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04F0_CKGEN00_V004_REG_CKG_I_DVBTC_RS_04F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_04F8_CKGEN00_V004 (CKGEN00_V004 + 0x4F8)
	#define REG_04F8_CKGEN00_V004_REG_CKG_G_DVBTC_SRAM1_04F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_04F8_CKGEN00_V004_REG_CKG_I_DVBTC_SRAM1_04F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0500_CKGEN00_V004 (CKGEN00_V004 + 0x500)
	#define REG_0500_CKGEN00_V004_REG_CKG_G_DVBTC_SRAM3_0500 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0500_CKGEN00_V004_REG_CKG_I_DVBTC_SRAM3_0500 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0508_CKGEN00_V004 (CKGEN00_V004 + 0x508)
	#define REG_0508_CKGEN00_V004_REG_CKG_G_DVBTC_SRAM4_0508 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0508_CKGEN00_V004_REG_CKG_I_DVBTC_SRAM4_0508 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0510_CKGEN00_V004 (CKGEN00_V004 + 0x510)
	#define REG_0510_CKGEN00_V004_REG_CKG_G_DVBTC_TS_0510 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0510_CKGEN00_V004_REG_CKG_I_DVBTC_TS_0510 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0518_CKGEN00_V004 (CKGEN00_V004 + 0x518)
	#define REG_0518_CKGEN00_V004_REG_CKG_G_DVBTM_ADC0P5X_EQ0P5X_0518 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0518_CKGEN00_V004_REG_CKG_I_DVBTM_ADC0P5X_EQ0P5X_0518 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0520_CKGEN00_V004 (CKGEN00_V004 + 0x520)
	#define REG_0520_CKGEN00_V004_REG_CKG_G_DVBTM_ADC1X_EQ1X_0520 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0520_CKGEN00_V004_REG_CKG_I_DVBTM_ADC1X_EQ1X_0520 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0528_CKGEN00_V004 (CKGEN00_V004 + 0x528)
	#define REG_0528_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_ADC_T22X_0528 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0528_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_ADC_T22X_0528 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0530_CKGEN00_V004 (CKGEN00_V004 + 0x530)
	#define REG_0530_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_ADC_T22X_DVBTC_RS_0530 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0530_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_ADC_T22X_DVBTC_RS_0530 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0538_CKGEN00_V004 (CKGEN00_V004 + 0x538)
	#define REG_0538_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T11X_T22X_0538 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0538_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T11X_T22X_0538 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0540_CKGEN00_V004 (CKGEN00_V004 + 0x540)
	#define REG_0540_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T11X_T24X_0540 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0540_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T11X_T24X_0540 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0548_CKGEN00_V004 (CKGEN00_V004 + 0x548)
	#define REG_0548_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T12X_T22X_0548 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0548_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T12X_T22X_0548 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0550_CKGEN00_V004 (CKGEN00_V004 + 0x550)
	#define REG_0550_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T12X_T24X_0550 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0550_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T12X_T24X_0550 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0558_CKGEN00_V004 (CKGEN00_V004 + 0x558)
	#define REG_0558_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T12X_T24X_S2INNER_0558 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0558_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T12X_T24X_S2INNER_0558 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0560_CKGEN00_V004 (CKGEN00_V004 + 0x560)
	#define REG_0560_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T12X_T24X_SRD1X_0560 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0560_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T12X_T24X_SRD1X_0560 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0568_CKGEN00_V004 (CKGEN00_V004 + 0x568)
	#define REG_0568_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T14X_T24X_0568 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0568_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T14X_T24X_0568 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0570_CKGEN00_V004 (CKGEN00_V004 + 0x570)
	#define REG_0570_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T14X_T24X_S2INNER_0570 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0570_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T14X_T24X_S2INNER_0570 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0578_CKGEN00_V004 (CKGEN00_V004 + 0x578)
	#define REG_0578_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC_0578 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0578_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC_0578 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0580_CKGEN00_V004 (CKGEN00_V004 + 0x580)
	#define REG_0580_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC_0580 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0580_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC_0580 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0588_CKGEN00_V004 (CKGEN00_V004 + 0x588)
	#define REG_0588_CKGEN00_V004_REG_CKG_G_DVBTM_SRAM_T1OUTER1X_T24X_0588 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0588_CKGEN00_V004_REG_CKG_I_DVBTM_SRAM_T1OUTER1X_T24X_0588 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0590_CKGEN00_V004 (CKGEN00_V004 + 0x590)
	#define REG_0590_CKGEN00_V004_REG_CKG_G_ISDBT_INNER1X_0590 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0590_CKGEN00_V004_REG_CKG_I_ISDBT_INNER1X_0590 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0598_CKGEN00_V004 (CKGEN00_V004 + 0x598)
	#define REG_0598_CKGEN00_V004_REG_CKG_G_ISDBT_INNER1X_DVBT_INNER1X_0598 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0598_CKGEN00_V004_REG_CKG_I_ISDBT_INNER1X_DVBT_INNER1X_0598 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05A0_CKGEN00_V004 (CKGEN00_V004 + 0x5A0)
	#define REG_05A0_CKGEN00_V004_REG_CKG_G_ISDBT_INNER2X_05A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05A0_CKGEN00_V004_REG_CKG_I_ISDBT_INNER2X_05A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05A8_CKGEN00_V004 (CKGEN00_V004 + 0x5A8)
	#define REG_05A8_CKGEN00_V004_REG_CKG_G_ISDBT_INNER2X_DVBT_INNER2X_05A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05A8_CKGEN00_V004_REG_CKG_I_ISDBT_INNER2X_DVBT_INNER2X_05A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05B0_CKGEN00_V004 (CKGEN00_V004 + 0x5B0)
	#define REG_05B0_CKGEN00_V004_REG_CKG_G_ISDBT_INNER4X_05B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05B0_CKGEN00_V004_REG_CKG_I_ISDBT_INNER4X_05B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05B8_CKGEN00_V004 (CKGEN00_V004 + 0x5B8)
	#define REG_05B8_CKGEN00_V004_REG_CKG_G_ISDBT_INNER4X_DVBT_INNER4X_05B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05B8_CKGEN00_V004_REG_CKG_I_ISDBT_INNER4X_DVBT_INNER4X_05B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05C0_CKGEN00_V004 (CKGEN00_V004 + 0x5C0)
	#define REG_05C0_CKGEN00_V004_REG_CKG_G_ISDBT_INNER4X_DVBT_INNER4X_ADC_05C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05C0_CKGEN00_V004_REG_CKG_I_ISDBT_INNER4X_DVBT_INNER4X_ADC_05C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05C8_CKGEN00_V004 (CKGEN00_V004 + 0x5C8)
	#define REG_05C8_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER12X_05C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05C8_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER12X_05C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05D0_CKGEN00_V004 (CKGEN00_V004 + 0x5D0)
	#define REG_05D0_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER1X_05D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05D0_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER1X_05D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05D8_CKGEN00_V004 (CKGEN00_V004 + 0x5D8)
	#define REG_05D8_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER1X_DVBT_OUTER1X_05D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05D8_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER1X_DVBT_OUTER1X_05D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05E0_CKGEN00_V004 (CKGEN00_V004 + 0x5E0)
	#define REG_05E0_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER4X_05E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05E0_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER4X_05E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05E8_CKGEN00_V004 (CKGEN00_V004 + 0x5E8)
	#define REG_05E8_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER6X_05E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05E8_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER6X_05E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05F0_CKGEN00_V004 (CKGEN00_V004 + 0x5F0)
	#define REG_05F0_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER6X_DVBT_INNER1X_05F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05F0_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER6X_DVBT_INNER1X_05F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_05F8_CKGEN00_V004 (CKGEN00_V004 + 0x5F8)
	#define REG_05F8_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER6X_DVBT_INNER2X_05F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_05F8_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER6X_DVBT_INNER2X_05F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0600_CKGEN00_V004 (CKGEN00_V004 + 0x600)
	#define REG_0600_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER6X_DVBT_OUTER2X_0600 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0600_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER6X_DVBT_OUTER2X_0600 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0608_CKGEN00_V004 (CKGEN00_V004 + 0x608)
	#define REG_0608_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER6X_DVBT_OUTER2X_C_0608 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0608_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER6X_DVBT_OUTER2X_C_0608 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0610_CKGEN00_V004 (CKGEN00_V004 + 0x610)
	#define REG_0610_CKGEN00_V004_REG_CKG_G_ISDBT_OUTER_RS_0610 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0610_CKGEN00_V004_REG_CKG_I_ISDBT_OUTER_RS_0610 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0640_CKGEN00_V004 (CKGEN00_V004 + 0x640)
	#define REG_0640_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_00_0_0640 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0640_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_00_0_0640 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0648_CKGEN00_V004 (CKGEN00_V004 + 0x648)
	#define REG_0648_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_00_1_0648 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0648_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_00_1_0648 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0650_CKGEN00_V004 (CKGEN00_V004 + 0x650)
	#define REG_0650_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_01_0_0650 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0650_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_01_0_0650 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0658_CKGEN00_V004 (CKGEN00_V004 + 0x658)
	#define REG_0658_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_02_0_0658 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0658_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_02_0_0658 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0660_CKGEN00_V004 (CKGEN00_V004 + 0x660)
	#define REG_0660_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_03_0_0660 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0660_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_03_0_0660 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0668_CKGEN00_V004 (CKGEN00_V004 + 0x668)
	#define REG_0668_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_03_1_0668 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0668_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_03_1_0668 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0670_CKGEN00_V004 (CKGEN00_V004 + 0x670)
	#define REG_0670_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_04_0_0670 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0670_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_04_0_0670 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0678_CKGEN00_V004 (CKGEN00_V004 + 0x678)
	#define REG_0678_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_04_1_0678 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0678_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_04_1_0678 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0680_CKGEN00_V004 (CKGEN00_V004 + 0x680)
	#define REG_0680_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_05_0680 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0680_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_05_0680 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0688_CKGEN00_V004 (CKGEN00_V004 + 0x688)
	#define REG_0688_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_06_0688 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0688_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_06_0688 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0690_CKGEN00_V004 (CKGEN00_V004 + 0x690)
	#define REG_0690_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_07_0690 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0690_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_07_0690 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0698_CKGEN00_V004 (CKGEN00_V004 + 0x698)
	#define REG_0698_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_08_0698 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0698_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_08_0698 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06A0_CKGEN00_V004 (CKGEN00_V004 + 0x6A0)
	#define REG_06A0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_09_06A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06A0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_09_06A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06A8_CKGEN00_V004 (CKGEN00_V004 + 0x6A8)
	#define REG_06A8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_10_06A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06A8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_10_06A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06B0_CKGEN00_V004 (CKGEN00_V004 + 0x6B0)
	#define REG_06B0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_11_06B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06B0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_11_06B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06B8_CKGEN00_V004 (CKGEN00_V004 + 0x6B8)
	#define REG_06B8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_12_06B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06B8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_12_06B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06C0_CKGEN00_V004 (CKGEN00_V004 + 0x6C0)
	#define REG_06C0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_13_06C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06C0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_13_06C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06C8_CKGEN00_V004 (CKGEN00_V004 + 0x6C8)
	#define REG_06C8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_14_R_06C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06C8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_14_R_06C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06D0_CKGEN00_V004 (CKGEN00_V004 + 0x6D0)
	#define REG_06D0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_14_W_06D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06D0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_14_W_06D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06D8_CKGEN00_V004 (CKGEN00_V004 + 0x6D8)
	#define REG_06D8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_15_R_06D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06D8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_15_R_06D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06E0_CKGEN00_V004 (CKGEN00_V004 + 0x6E0)
	#define REG_06E0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_15_W_06E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06E0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_15_W_06E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06E8_CKGEN00_V004 (CKGEN00_V004 + 0x6E8)
	#define REG_06E8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_16_06E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06E8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_16_06E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06F0_CKGEN00_V004 (CKGEN00_V004 + 0x6F0)
	#define REG_06F0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_18_06F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06F0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_18_06F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_06F8_CKGEN00_V004 (CKGEN00_V004 + 0x6F8)
	#define REG_06F8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_19_06F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_06F8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_19_06F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0700_CKGEN00_V004 (CKGEN00_V004 + 0x700)
	#define REG_0700_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_20_0700 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0700_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_20_0700 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0708_CKGEN00_V004 (CKGEN00_V004 + 0x708)
	#define REG_0708_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_21_0708 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0708_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_21_0708 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0710_CKGEN00_V004 (CKGEN00_V004 + 0x710)
	#define REG_0710_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_22_0710 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0710_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_22_0710 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0718_CKGEN00_V004 (CKGEN00_V004 + 0x718)
	#define REG_0718_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_23_0718 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0718_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_23_0718 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0720_CKGEN00_V004 (CKGEN00_V004 + 0x720)
	#define REG_0720_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_24_0720 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0720_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_24_0720 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0728_CKGEN00_V004 (CKGEN00_V004 + 0x728)
	#define REG_0728_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_26_0728 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0728_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_26_0728 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0730_CKGEN00_V004 (CKGEN00_V004 + 0x730)
	#define REG_0730_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_27_0730 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0730_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_27_0730 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0738_CKGEN00_V004 (CKGEN00_V004 + 0x738)
	#define REG_0738_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_28_0738 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0738_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_28_0738 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0740_CKGEN00_V004 (CKGEN00_V004 + 0x740)
	#define REG_0740_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_29_0740 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0740_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_29_0740 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0748_CKGEN00_V004 (CKGEN00_V004 + 0x748)
	#define REG_0748_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_34_0748 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0748_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_34_0748 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0750_CKGEN00_V004 (CKGEN00_V004 + 0x750)
	#define REG_0750_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_35_0750 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0750_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_35_0750 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0750_CKGEN00_V004_REG_CKG_S_SRAM_SHARE_35_0750 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0758_CKGEN00_V004 (CKGEN00_V004 + 0x758)
	#define REG_0758_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_36_0758 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0758_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_36_0758 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0758_CKGEN00_V004_REG_CKG_S_SRAM_SHARE_36_0758 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0760_CKGEN00_V004 (CKGEN00_V004 + 0x760)
	#define REG_0760_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_40_0760 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0760_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_40_0760 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0760_CKGEN00_V004_REG_CKG_S_SRAM_SHARE_40_0760 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0768_CKGEN00_V004 (CKGEN00_V004 + 0x768)
	#define REG_0768_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_42_0768 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0768_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_42_0768 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0770_CKGEN00_V004 (CKGEN00_V004 + 0x770)
	#define REG_0770_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_44_0770 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0770_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_44_0770 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0778_CKGEN00_V004 (CKGEN00_V004 + 0x778)
	#define REG_0778_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_46_0778 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0778_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_46_0778 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0780_CKGEN00_V004 (CKGEN00_V004 + 0x780)
	#define REG_0780_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_47_0780 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0780_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_47_0780 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0780_CKGEN00_V004_REG_CKG_S_SRAM_SHARE_47_0780 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0788_CKGEN00_V004 (CKGEN00_V004 + 0x788)
	#define REG_0788_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_50_0_0788 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0788_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_50_0_0788 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0790_CKGEN00_V004 (CKGEN00_V004 + 0x790)
	#define REG_0790_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_52_0_0790 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0790_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_52_0_0790 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0798_CKGEN00_V004 (CKGEN00_V004 + 0x798)
	#define REG_0798_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_53_0_0798 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0798_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_53_0_0798 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07A0_CKGEN00_V004 (CKGEN00_V004 + 0x7A0)
	#define REG_07A0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_55_0_07A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07A0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_55_0_07A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07A8_CKGEN00_V004 (CKGEN00_V004 + 0x7A8)
	#define REG_07A8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_56_07A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07A8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_56_07A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07B0_CKGEN00_V004 (CKGEN00_V004 + 0x7B0)
	#define REG_07B0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_57_07B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07B0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_57_07B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07B8_CKGEN00_V004 (CKGEN00_V004 + 0x7B8)
	#define REG_07B8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_58_07B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07B8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_58_07B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07C0_CKGEN00_V004 (CKGEN00_V004 + 0x7C0)
	#define REG_07C0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_59_07C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07C0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_59_07C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07C8_CKGEN00_V004 (CKGEN00_V004 + 0x7C8)
	#define REG_07C8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_60_07C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07C8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_60_07C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07D0_CKGEN00_V004 (CKGEN00_V004 + 0x7D0)
	#define REG_07D0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_61_07D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07D0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_61_07D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07D8_CKGEN00_V004 (CKGEN00_V004 + 0x7D8)
	#define REG_07D8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_62_07D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07D8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_62_07D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07E0_CKGEN00_V004 (CKGEN00_V004 + 0x7E0)
	#define REG_07E0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_64_07E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07E0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_64_07E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07E8_CKGEN00_V004 (CKGEN00_V004 + 0x7E8)
	#define REG_07E8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_66_07E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07E8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_66_07E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07F0_CKGEN00_V004 (CKGEN00_V004 + 0x7F0)
	#define REG_07F0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_67_07F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07F0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_67_07F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_07F8_CKGEN00_V004 (CKGEN00_V004 + 0x7F8)
	#define REG_07F8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_68_0_07F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_07F8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_68_0_07F8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_07F8_CKGEN00_V004_REG_CKG_S_SRAM_SHARE_68_0_07F8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0800_CKGEN00_V004 (CKGEN00_V004 + 0x800)
	#define REG_0800_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_68_2_0800 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0800_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_68_2_0800 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0808_CKGEN00_V004 (CKGEN00_V004 + 0x808)
	#define REG_0808_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_69_0_0808 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0808_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_69_0_0808 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0810_CKGEN00_V004 (CKGEN00_V004 + 0x810)
	#define REG_0810_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_70_0810 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0810_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_70_0810 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0810_CKGEN00_V004_REG_CKG_S_SRAM_SHARE_70_0810 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0818_CKGEN00_V004 (CKGEN00_V004 + 0x818)
	#define REG_0818_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_71_0818 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0818_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_71_0818 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0820_CKGEN00_V004 (CKGEN00_V004 + 0x820)
	#define REG_0820_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_77_0820 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0820_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_77_0820 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0828_CKGEN00_V004 (CKGEN00_V004 + 0x828)
	#define REG_0828_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_79_0828 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0828_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_79_0828 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0830_CKGEN00_V004 (CKGEN00_V004 + 0x830)
	#define REG_0830_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_81_0830 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0830_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_81_0830 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0838_CKGEN00_V004 (CKGEN00_V004 + 0x838)
	#define REG_0838_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_85_0838 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0838_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_85_0838 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0840_CKGEN00_V004 (CKGEN00_V004 + 0x840)
	#define REG_0840_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_87_0840 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0840_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_87_0840 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0848_CKGEN00_V004 (CKGEN00_V004 + 0x848)
	#define REG_0848_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_89_0848 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0848_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_89_0848 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0850_CKGEN00_V004 (CKGEN00_V004 + 0x850)
	#define REG_0850_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_91_0850 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0850_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_91_0850 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0858_CKGEN00_V004 (CKGEN00_V004 + 0x858)
	#define REG_0858_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_92_0858 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0858_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_92_0858 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0860_CKGEN00_V004 (CKGEN00_V004 + 0x860)
	#define REG_0860_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_93_0860 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0860_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_93_0860 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0868_CKGEN00_V004 (CKGEN00_V004 + 0x868)
	#define REG_0868_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_94_0868 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0868_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_94_0868 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0870_CKGEN00_V004 (CKGEN00_V004 + 0x870)
	#define REG_0870_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_96_0870 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0870_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_96_0870 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0878_CKGEN00_V004 (CKGEN00_V004 + 0x878)
	#define REG_0878_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_98_0878 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0878_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_98_0878 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0880_CKGEN00_V004 (CKGEN00_V004 + 0x880)
	#define REG_0880_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_99_0880 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0880_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_99_0880 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0888_CKGEN00_V004 (CKGEN00_V004 + 0x888)
	#define REG_0888_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_100_0888 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0888_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_100_0888 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0890_CKGEN00_V004 (CKGEN00_V004 + 0x890)
	#define REG_0890_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_103_0890 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0890_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_103_0890 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0898_CKGEN00_V004 (CKGEN00_V004 + 0x898)
	#define REG_0898_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_105_0898 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0898_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_105_0898 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08A0_CKGEN00_V004 (CKGEN00_V004 + 0x8A0)
	#define REG_08A0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_107_08A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08A0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_107_08A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08A8_CKGEN00_V004 (CKGEN00_V004 + 0x8A8)
	#define REG_08A8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_109_08A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08A8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_109_08A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08B0_CKGEN00_V004 (CKGEN00_V004 + 0x8B0)
	#define REG_08B0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_110_08B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08B0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_110_08B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08B8_CKGEN00_V004 (CKGEN00_V004 + 0x8B8)
	#define REG_08B8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_111_08B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08B8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_111_08B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08C0_CKGEN00_V004 (CKGEN00_V004 + 0x8C0)
	#define REG_08C0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_112_08C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08C0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_112_08C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08C8_CKGEN00_V004 (CKGEN00_V004 + 0x8C8)
	#define REG_08C8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_124_08C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08C8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_124_08C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08D0_CKGEN00_V004 (CKGEN00_V004 + 0x8D0)
	#define REG_08D0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_128_08D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08D0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_128_08D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08D8_CKGEN00_V004 (CKGEN00_V004 + 0x8D8)
	#define REG_08D8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_129_08D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08D8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_129_08D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08E0_CKGEN00_V004 (CKGEN00_V004 + 0x8E0)
	#define REG_08E0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_130_08E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08E0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_130_08E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08E8_CKGEN00_V004 (CKGEN00_V004 + 0x8E8)
	#define REG_08E8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_131_08E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08E8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_131_08E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08F0_CKGEN00_V004 (CKGEN00_V004 + 0x8F0)
	#define REG_08F0_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_132_08F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08F0_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_132_08F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_08F8_CKGEN00_V004 (CKGEN00_V004 + 0x8F8)
	#define REG_08F8_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_134_R_08F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_08F8_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_134_R_08F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0900_CKGEN00_V004 (CKGEN00_V004 + 0x900)
	#define REG_0900_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_134_W_0900 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0900_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_134_W_0900 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0908_CKGEN00_V004 (CKGEN00_V004 + 0x908)
	#define REG_0908_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_136_R_0908 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0908_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_136_R_0908 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0910_CKGEN00_V004 (CKGEN00_V004 + 0x910)
	#define REG_0910_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_136_W_0910 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0910_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_136_W_0910 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0918_CKGEN00_V004 (CKGEN00_V004 + 0x918)
	#define REG_0918_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_137_R_0918 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0918_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_137_R_0918 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0920_CKGEN00_V004 (CKGEN00_V004 + 0x920)
	#define REG_0920_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_137_W_0920 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0920_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_137_W_0920 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0928_CKGEN00_V004 (CKGEN00_V004 + 0x928)
	#define REG_0928_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_138_R_0928 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0928_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_138_R_0928 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0930_CKGEN00_V004 (CKGEN00_V004 + 0x930)
	#define REG_0930_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_138_W_0930 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0930_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_138_W_0930 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0938_CKGEN00_V004 (CKGEN00_V004 + 0x938)
	#define REG_0938_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_139_R_0938 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0938_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_139_R_0938 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0940_CKGEN00_V004 (CKGEN00_V004 + 0x940)
	#define REG_0940_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_139_W_0940 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0940_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_139_W_0940 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0948_CKGEN00_V004 (CKGEN00_V004 + 0x948)
	#define REG_0948_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_140_R_0948 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0948_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_140_R_0948 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0950_CKGEN00_V004 (CKGEN00_V004 + 0x950)
	#define REG_0950_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_140_W_0950 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0950_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_140_W_0950 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0958_CKGEN00_V004 (CKGEN00_V004 + 0x958)
	#define REG_0958_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_141_R_0958 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0958_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_141_R_0958 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0960_CKGEN00_V004 (CKGEN00_V004 + 0x960)
	#define REG_0960_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_141_W_0960 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0960_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_141_W_0960 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0968_CKGEN00_V004 (CKGEN00_V004 + 0x968)
	#define REG_0968_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_142_R_0968 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0968_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_142_R_0968 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0970_CKGEN00_V004 (CKGEN00_V004 + 0x970)
	#define REG_0970_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_142_W_0970 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0970_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_142_W_0970 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0978_CKGEN00_V004 (CKGEN00_V004 + 0x978)
	#define REG_0978_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_143_R_0978 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0978_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_143_R_0978 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0980_CKGEN00_V004 (CKGEN00_V004 + 0x980)
	#define REG_0980_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_143_W_0980 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0980_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_143_W_0980 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0988_CKGEN00_V004 (CKGEN00_V004 + 0x988)
	#define REG_0988_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_144_R_0988 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0988_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_144_R_0988 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0990_CKGEN00_V004 (CKGEN00_V004 + 0x990)
	#define REG_0990_CKGEN00_V004_REG_CKG_G_SRAM_SHARE_144_W_0990 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0990_CKGEN00_V004_REG_CKG_I_SRAM_SHARE_144_W_0990 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0998_CKGEN00_V004 (CKGEN00_V004 + 0x998)
	#define REG_0998_CKGEN00_V004_REG_CKG_G_TDP_JL_INNER1X_0998 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0998_CKGEN00_V004_REG_CKG_I_TDP_JL_INNER1X_0998 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09A0_CKGEN00_V004 (CKGEN00_V004 + 0x9A0)
	#define REG_09A0_CKGEN00_V004_REG_CKG_G_TDP_JL_INNER4X_09A0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09A0_CKGEN00_V004_REG_CKG_I_TDP_JL_INNER4X_09A0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09A8_CKGEN00_V004 (CKGEN00_V004 + 0x9A8)
	#define REG_09A8_CKGEN00_V004_REG_CKG_G_TDP_TEQ_INNER1X_09A8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09A8_CKGEN00_V004_REG_CKG_I_TDP_TEQ_INNER1X_09A8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09B0_CKGEN00_V004 (CKGEN00_V004 + 0x9B0)
	#define REG_09B0_CKGEN00_V004_REG_CKG_G_TDP_TEQ_INNER2X_09B0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09B0_CKGEN00_V004_REG_CKG_I_TDP_TEQ_INNER2X_09B0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09B8_CKGEN00_V004 (CKGEN00_V004 + 0x9B8)
	#define REG_09B8_CKGEN00_V004_REG_CKG_G_TR_09B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09B8_CKGEN00_V004_REG_CKG_I_TR_09B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09C0_CKGEN00_V004 (CKGEN00_V004 + 0x9C0)
	#define REG_09C0_CKGEN00_V004_REG_CKG_G_TS_IN_09C0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09C0_CKGEN00_V004_REG_CKG_I_TS_IN_09C0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09C8_CKGEN00_V004 (CKGEN00_V004 + 0x9C8)
	#define REG_09C8_CKGEN00_V004_REG_CKG_G_VIFDBB_144M_09C8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09C8_CKGEN00_V004_REG_CKG_I_VIFDBB_144M_09C8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09D0_CKGEN00_V004 (CKGEN00_V004 + 0x9D0)
	#define REG_09D0_CKGEN00_V004_REG_CKG_G_VIFDBB_43M_09D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09D0_CKGEN00_V004_REG_CKG_I_VIFDBB_43M_09D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09D8_CKGEN00_V004 (CKGEN00_V004 + 0x9D8)
	#define REG_09D8_CKGEN00_V004_REG_CKG_G_VIFDBB_86M_09D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09D8_CKGEN00_V004_REG_CKG_I_VIFDBB_86M_09D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09E0_CKGEN00_V004 (CKGEN00_V004 + 0x9E0)
	#define REG_09E0_CKGEN00_V004_REG_CKG_G_VIFDBB_DAC_09E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09E0_CKGEN00_V004_REG_CKG_I_VIFDBB_DAC_09E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09E8_CKGEN00_V004 (CKGEN00_V004 + 0x9E8)
	#define REG_09E8_CKGEN00_V004_REG_CKG_G_VIFDBB_VDAC_09E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09E8_CKGEN00_V004_REG_CKG_I_VIFDBB_VDAC_09E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09F0_CKGEN00_V004 (CKGEN00_V004 + 0x9F0)
	#define REG_09F0_CKGEN00_V004_REG_CKG_G_VIFDBB_VDAC_TMP_09F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09F0_CKGEN00_V004_REG_CKG_I_VIFDBB_VDAC_TMP_09F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09F4_CKGEN00_V004 (CKGEN00_V004 + 0x9F4)
	#define REG_09F4_CKGEN00_V004_REG_CKG_G_VIFDBB_DAC_FROM_TOP_09F4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09F4_CKGEN00_V004_REG_CKG_I_VIFDBB_DAC_FROM_TOP_09F4 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_09F8_CKGEN00_V004 (CKGEN00_V004 + 0x9F8)
	#define REG_09F8_CKGEN00_V004_REG_CKG_G_DEINTER_09F8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_09F8_CKGEN00_V004_REG_CKG_I_DEINTER_09F8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A00_CKGEN00_V004 (CKGEN00_V004 + 0xA00)
	#define REG_0A00_CKGEN00_V004_REG_CKG_G_DTMB_BCH_DEMOD1_0A00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A00_CKGEN00_V004_REG_CKG_I_DTMB_BCH_DEMOD1_0A00 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A08_CKGEN00_V004 (CKGEN00_V004 + 0xA08)
	#define REG_0A08_CKGEN00_V004_REG_CKG_G_DTMB_OUTER1X_DEMOD1_0A08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A08_CKGEN00_V004_REG_CKG_I_DTMB_OUTER1X_DEMOD1_0A08 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A10_CKGEN00_V004 (CKGEN00_V004 + 0xA10)
	#define REG_0A10_CKGEN00_V004_REG_CKG_G_DVBS2_DEMAPPER_0A10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A10_CKGEN00_V004_REG_CKG_I_DVBS2_DEMAPPER_0A10 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A18_CKGEN00_V004 (CKGEN00_V004 + 0xA18)
	#define REG_0A18_CKGEN00_V004_REG_CKG_G_DVBS2_DVBT2_DEMAPPER_0A18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A18_CKGEN00_V004_REG_CKG_I_DVBS2_DVBT2_DEMAPPER_0A18 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A20_CKGEN00_V004 (CKGEN00_V004 + 0xA20)
	#define REG_0A20_CKGEN00_V004_REG_CKG_G_DVBS2_OUTER_FIFO_IN_0A20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A20_CKGEN00_V004_REG_CKG_I_DVBS2_OUTER_FIFO_IN_0A20 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A28_CKGEN00_V004 (CKGEN00_V004 + 0xA28)
	#define REG_0A28_CKGEN00_V004_REG_CKG_G_DVBT2_DEMAPPER_0A28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A28_CKGEN00_V004_REG_CKG_I_DVBT2_DEMAPPER_0A28 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A30_CKGEN00_V004 (CKGEN00_V004 + 0xA30)
	#define REG_0A30_CKGEN00_V004_REG_CKG_G_DVBT2_DVBS2_OUTER_FIFO_IN_0A30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A30_CKGEN00_V004_REG_CKG_I_DVBT2_DVBS2_OUTER_FIFO_IN_0A30 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A38_CKGEN00_V004 (CKGEN00_V004 + 0xA38)
	#define REG_0A38_CKGEN00_V004_REG_CKG_G_DVBT2_OUTER_FIFO_IN_0A38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A38_CKGEN00_V004_REG_CKG_I_DVBT2_OUTER_FIFO_IN_0A38 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A40_CKGEN00_V004 (CKGEN00_V004 + 0xA40)
	#define REG_0A40_CKGEN00_V004_REG_CKG_G_DVBT2_S2_BCH_0A40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A40_CKGEN00_V004_REG_CKG_I_DVBT2_S2_BCH_0A40 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A48_CKGEN00_V004 (CKGEN00_V004 + 0xA48)
	#define REG_0A48_CKGEN00_V004_REG_CKG_G_DVBT2_S2_BCH_OUT_0A48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A48_CKGEN00_V004_REG_CKG_I_DVBT2_S2_BCH_OUT_0A48 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A50_CKGEN00_V004 (CKGEN00_V004 + 0xA50)
	#define REG_0A50_CKGEN00_V004_REG_CKG_G_LDPC1X_0A50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A50_CKGEN00_V004_REG_CKG_I_LDPC1X_0A50 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A58_CKGEN00_V004 (CKGEN00_V004 + 0xA58)
	#define REG_0A58_CKGEN00_V004_REG_CKG_G_LDPC2X_0A58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A58_CKGEN00_V004_REG_CKG_I_LDPC2X_0A58 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A60_CKGEN00_V004 (CKGEN00_V004 + 0xA60)
	#define REG_0A60_CKGEN00_V004_REG_CKG_G_SRAM_DVBT2_S2_BCH_ME_0A60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A60_CKGEN00_V004_REG_CKG_I_SRAM_DVBT2_S2_BCH_ME_0A60 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A68_CKGEN00_V004 (CKGEN00_V004 + 0xA68)
	#define REG_0A68_CKGEN00_V004_REG_CKG_G_SRAM_LDPC1X_ME_0A68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A68_CKGEN00_V004_REG_CKG_I_SRAM_LDPC1X_ME_0A68 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A70_CKGEN00_V004 (CKGEN00_V004 + 0xA70)
	#define REG_0A70_CKGEN00_V004_REG_CKG_G_SRAM_LDPC2X_ME_0A70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A70_CKGEN00_V004_REG_CKG_I_SRAM_LDPC2X_ME_0A70 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0A78_CKGEN00_V004 (CKGEN00_V004 + 0xA78)
	#define REG_0A78_CKGEN00_V004_REG_CKG_G_XTAL_24M_DEMOD1_0A78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0A78_CKGEN00_V004_REG_CKG_I_XTAL_24M_DEMOD1_0A78 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0AB8_CKGEN00_V004 (CKGEN00_V004 + 0xAB8)
	#define REG_0AB8_CKGEN00_V004_REG_CKG_G_XTAL_12M_DEMOD1_0AB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0AB8_CKGEN00_V004_REG_CKG_I_XTAL_12M_DEMOD1_0AB8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0B08_CKGEN00_V004 (CKGEN00_V004 + 0xB08)
	#define REG_0B08_CKGEN00_V004_REG_CKG_G_IRS_0B08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B08_CKGEN00_V004_REG_CKG_I_IRS_0B08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B08_CKGEN00_V004_REG_CKG_S_IRS_0B08 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B10_CKGEN00_V004 (CKGEN00_V004 + 0xB10)
	#define REG_0B10_CKGEN00_V004_REG_CKG_G_AESDMA_0B10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B10_CKGEN00_V004_REG_CKG_I_AESDMA_0B10 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B10_CKGEN00_V004_REG_CKG_S_AESDMA_0B10 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0B10_CKGEN00_V004_REG_CKG_G_AESDMA_TSP_0B10 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0B10_CKGEN00_V004_REG_CKG_I_AESDMA_TSP_0B10 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0B18_CKGEN00_V004 (CKGEN00_V004 + 0xB18)
	#define REG_0B18_CKGEN00_V004_REG_CKG_G_PARSER_0B18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B18_CKGEN00_V004_REG_CKG_I_PARSER_0B18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B18_CKGEN00_V004_REG_CKG_S_PARSER_0B18 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0B18_CKGEN00_V004_REG_CKG_G_VIVA_PARSER_0B18 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0B18_CKGEN00_V004_REG_CKG_I_VIVA_PARSER_0B18 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_0B18_CKGEN00_V004_REG_CKG_S_VIVA_PARSER_0B18 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_0B18_CKGEN00_V004_REG_CKG_G_PARSER_TSP_0B18 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0B18_CKGEN00_V004_REG_CKG_I_PARSER_TSP_0B18 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_0B28_CKGEN00_V004 (CKGEN00_V004 + 0xB28)
	#define REG_0B28_CKGEN00_V004_REG_CKG_G_SMART2_0B28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B28_CKGEN00_V004_REG_CKG_I_SMART2_0B28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B28_CKGEN00_V004_REG_CKG_S_SMART2_0B28 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0B28_CKGEN00_V004_REG_CKG_G_SMART2_MHEG5_0B28 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0B28_CKGEN00_V004_REG_CKG_I_SMART2_MHEG5_0B28 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0B30_CKGEN00_V004 (CKGEN00_V004 + 0xB30)
	#define REG_0B30_CKGEN00_V004_REG_CKG_G_SMART_0B30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B30_CKGEN00_V004_REG_CKG_I_SMART_0B30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B30_CKGEN00_V004_REG_CKG_S_SMART_0B30 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0B30_CKGEN00_V004_REG_CKG_G_SMART_MHEG5_0B30 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0B30_CKGEN00_V004_REG_CKG_I_SMART_MHEG5_0B30 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0B38_CKGEN00_V004 (CKGEN00_V004 + 0xB38)
	#define REG_0B38_CKGEN00_V004_REG_CKG_G_TSO2_OUT_DIV_MN_SRC_0B38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B38_CKGEN00_V004_REG_CKG_I_TSO2_OUT_DIV_MN_SRC_0B38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B38_CKGEN00_V004_REG_CKG_S_TSO2_OUT_DIV_MN_SRC_0B38 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B40_CKGEN00_V004 (CKGEN00_V004 + 0xB40)
	#define REG_0B40_CKGEN00_V004_REG_CKG_G_TSO_OUT_DIV_MN_SRC_0B40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B40_CKGEN00_V004_REG_CKG_I_TSO_OUT_DIV_MN_SRC_0B40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B40_CKGEN00_V004_REG_CKG_S_TSO_OUT_DIV_MN_SRC_0B40 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B48_CKGEN00_V004 (CKGEN00_V004 + 0xB48)
	#define REG_0B48_CKGEN00_V004_REG_CKG_G_TSP_0B48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B48_CKGEN00_V004_REG_CKG_I_TSP_0B48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B48_CKGEN00_V004_REG_CKG_S_TSP_0B48 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_0B48_CKGEN00_V004_REG_CKG_G_TSP_TSP_0B48 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0B48_CKGEN00_V004_REG_CKG_I_TSP_TSP_0B48 Fld(1,5,AC_MSKB0)//[5:5]
#define REG_0B50_CKGEN00_V004 (CKGEN00_V004 + 0xB50)
	#define REG_0B50_CKGEN00_V004_REG_CKG_G_FIQ0_27M_0B50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B50_CKGEN00_V004_REG_CKG_I_FIQ0_27M_0B50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B50_CKGEN00_V004_REG_CKG_S_FIQ0_27M_0B50 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B58_CKGEN00_V004 (CKGEN00_V004 + 0xB58)
	#define REG_0B58_CKGEN00_V004_REG_CKG_G_MM0_27M_0B58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B58_CKGEN00_V004_REG_CKG_I_MM0_27M_0B58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B58_CKGEN00_V004_REG_CKG_S_MM0_27M_0B58 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B60_CKGEN00_V004 (CKGEN00_V004 + 0xB60)
	#define REG_0B60_CKGEN00_V004_REG_CKG_G_MM1_27M_0B60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B60_CKGEN00_V004_REG_CKG_I_MM1_27M_0B60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B60_CKGEN00_V004_REG_CKG_S_MM1_27M_0B60 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B68_CKGEN00_V004 (CKGEN00_V004 + 0xB68)
	#define REG_0B68_CKGEN00_V004_REG_CKG_G_PVR1_27M_0B68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B68_CKGEN00_V004_REG_CKG_I_PVR1_27M_0B68 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B68_CKGEN00_V004_REG_CKG_S_PVR1_27M_0B68 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B70_CKGEN00_V004 (CKGEN00_V004 + 0xB70)
	#define REG_0B70_CKGEN00_V004_REG_CKG_G_PVR2_27M_0B70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B70_CKGEN00_V004_REG_CKG_I_PVR2_27M_0B70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B70_CKGEN00_V004_REG_CKG_S_PVR2_27M_0B70 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B78_CKGEN00_V004 (CKGEN00_V004 + 0xB78)
	#define REG_0B78_CKGEN00_V004_REG_CKG_G_PVR3_27M_0B78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B78_CKGEN00_V004_REG_CKG_I_PVR3_27M_0B78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B78_CKGEN00_V004_REG_CKG_S_PVR3_27M_0B78 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B80_CKGEN00_V004 (CKGEN00_V004 + 0xB80)
	#define REG_0B80_CKGEN00_V004_REG_CKG_G_PVR4_27M_0B80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B80_CKGEN00_V004_REG_CKG_I_PVR4_27M_0B80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B80_CKGEN00_V004_REG_CKG_S_PVR4_27M_0B80 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B88_CKGEN00_V004 (CKGEN00_V004 + 0xB88)
	#define REG_0B88_CKGEN00_V004_REG_CKG_G_STAMP_0B88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B88_CKGEN00_V004_REG_CKG_I_STAMP_0B88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B88_CKGEN00_V004_REG_CKG_S_STAMP_0B88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0B90_CKGEN00_V004 (CKGEN00_V004 + 0xB90)
	#define REG_0B90_CKGEN00_V004_REG_CKG_G_SYN_STC0_0B90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B90_CKGEN00_V004_REG_CKG_I_SYN_STC0_0B90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B90_CKGEN00_V004_REG_CKG_S_SYN_STC0_0B90 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0B98_CKGEN00_V004 (CKGEN00_V004 + 0xB98)
	#define REG_0B98_CKGEN00_V004_REG_CKG_G_SYN_STC1_0B98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0B98_CKGEN00_V004_REG_CKG_I_SYN_STC1_0B98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0B98_CKGEN00_V004_REG_CKG_S_SYN_STC1_0B98 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BA0_CKGEN00_V004 (CKGEN00_V004 + 0xBA0)
	#define REG_0BA0_CKGEN00_V004_REG_CKG_G_SYN_STC2_0BA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BA0_CKGEN00_V004_REG_CKG_I_SYN_STC2_0BA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BA0_CKGEN00_V004_REG_CKG_S_SYN_STC2_0BA0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BA8_CKGEN00_V004 (CKGEN00_V004 + 0xBA8)
	#define REG_0BA8_CKGEN00_V004_REG_CKG_G_SYN_STC3_0BA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BA8_CKGEN00_V004_REG_CKG_I_SYN_STC3_0BA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BA8_CKGEN00_V004_REG_CKG_S_SYN_STC3_0BA8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BB0_CKGEN00_V004 (CKGEN00_V004 + 0xBB0)
	#define REG_0BB0_CKGEN00_V004_REG_CKG_G_SYS_TIME0_27M_0BB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BB0_CKGEN00_V004_REG_CKG_I_SYS_TIME0_27M_0BB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BB0_CKGEN00_V004_REG_CKG_S_SYS_TIME0_27M_0BB0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BB8_CKGEN00_V004 (CKGEN00_V004 + 0xBB8)
	#define REG_0BB8_CKGEN00_V004_REG_CKG_G_SYS_TIME1_27M_0BB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BB8_CKGEN00_V004_REG_CKG_I_SYS_TIME1_27M_0BB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BB8_CKGEN00_V004_REG_CKG_S_SYS_TIME1_27M_0BB8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BC0_CKGEN00_V004 (CKGEN00_V004 + 0xBC0)
	#define REG_0BC0_CKGEN00_V004_REG_CKG_G_SYS_TIME2_27M_0BC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BC0_CKGEN00_V004_REG_CKG_I_SYS_TIME2_27M_0BC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BC0_CKGEN00_V004_REG_CKG_S_SYS_TIME2_27M_0BC0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BC8_CKGEN00_V004 (CKGEN00_V004 + 0xBC8)
	#define REG_0BC8_CKGEN00_V004_REG_CKG_G_SYS_TIME3_27M_0BC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BC8_CKGEN00_V004_REG_CKG_I_SYS_TIME3_27M_0BC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BC8_CKGEN00_V004_REG_CKG_S_SYS_TIME3_27M_0BC8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BD0_CKGEN00_V004 (CKGEN00_V004 + 0xBD0)
	#define REG_0BD0_CKGEN00_V004_REG_CKG_G_TLV0_27M_0BD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BD0_CKGEN00_V004_REG_CKG_I_TLV0_27M_0BD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BD0_CKGEN00_V004_REG_CKG_S_TLV0_27M_0BD0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BD8_CKGEN00_V004 (CKGEN00_V004 + 0xBD8)
	#define REG_0BD8_CKGEN00_V004_REG_CKG_G_TLV1_27M_0BD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BD8_CKGEN00_V004_REG_CKG_I_TLV1_27M_0BD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BD8_CKGEN00_V004_REG_CKG_S_TLV1_27M_0BD8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BE0_CKGEN00_V004 (CKGEN00_V004 + 0xBE0)
	#define REG_0BE0_CKGEN00_V004_REG_CKG_G_TLV2_27M_0BE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BE0_CKGEN00_V004_REG_CKG_I_TLV2_27M_0BE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BE0_CKGEN00_V004_REG_CKG_S_TLV2_27M_0BE0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BE8_CKGEN00_V004 (CKGEN00_V004 + 0xBE8)
	#define REG_0BE8_CKGEN00_V004_REG_CKG_G_TSIF0_27M_0BE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BE8_CKGEN00_V004_REG_CKG_I_TSIF0_27M_0BE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BE8_CKGEN00_V004_REG_CKG_S_TSIF0_27M_0BE8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BF0_CKGEN00_V004 (CKGEN00_V004 + 0xBF0)
	#define REG_0BF0_CKGEN00_V004_REG_CKG_G_TSO2_CH1_27M_0BF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BF0_CKGEN00_V004_REG_CKG_I_TSO2_CH1_27M_0BF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BF0_CKGEN00_V004_REG_CKG_S_TSO2_CH1_27M_0BF0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0BF8_CKGEN00_V004 (CKGEN00_V004 + 0xBF8)
	#define REG_0BF8_CKGEN00_V004_REG_CKG_G_TSO2_CH5_27M_0BF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0BF8_CKGEN00_V004_REG_CKG_I_TSO2_CH5_27M_0BF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0BF8_CKGEN00_V004_REG_CKG_S_TSO2_CH5_27M_0BF8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C00_CKGEN00_V004 (CKGEN00_V004 + 0xC00)
	#define REG_0C00_CKGEN00_V004_REG_CKG_G_TSO2_CH6_27M_0C00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C00_CKGEN00_V004_REG_CKG_I_TSO2_CH6_27M_0C00 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C00_CKGEN00_V004_REG_CKG_S_TSO2_CH6_27M_0C00 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C08_CKGEN00_V004 (CKGEN00_V004 + 0xC08)
	#define REG_0C08_CKGEN00_V004_REG_CKG_G_P_TSO2_OUT_0C08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C08_CKGEN00_V004_REG_CKG_I_P_TSO2_OUT_0C08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C08_CKGEN00_V004_REG_CKG_S_P_TSO2_OUT_0C08 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C10_CKGEN00_V004 (CKGEN00_V004 + 0xC10)
	#define REG_0C10_CKGEN00_V004_REG_CKG_G_TSO_CH1_27M_0C10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C10_CKGEN00_V004_REG_CKG_I_TSO_CH1_27M_0C10 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C10_CKGEN00_V004_REG_CKG_S_TSO_CH1_27M_0C10 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C18_CKGEN00_V004 (CKGEN00_V004 + 0xC18)
	#define REG_0C18_CKGEN00_V004_REG_CKG_G_TSO_CH5_27M_0C18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C18_CKGEN00_V004_REG_CKG_I_TSO_CH5_27M_0C18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C18_CKGEN00_V004_REG_CKG_S_TSO_CH5_27M_0C18 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C20_CKGEN00_V004 (CKGEN00_V004 + 0xC20)
	#define REG_0C20_CKGEN00_V004_REG_CKG_G_TSO_CH6_27M_0C20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C20_CKGEN00_V004_REG_CKG_I_TSO_CH6_27M_0C20 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C20_CKGEN00_V004_REG_CKG_S_TSO_CH6_27M_0C20 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C28_CKGEN00_V004 (CKGEN00_V004 + 0xC28)
	#define REG_0C28_CKGEN00_V004_REG_CKG_G_P_TSO_OUT_0C28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C28_CKGEN00_V004_REG_CKG_I_P_TSO_OUT_0C28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C28_CKGEN00_V004_REG_CKG_S_P_TSO_OUT_0C28 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C30_CKGEN00_V004 (CKGEN00_V004 + 0xC30)
	#define REG_0C30_CKGEN00_V004_REG_CKG_G_SMART2_SYNTH_432_0C30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C30_CKGEN00_V004_REG_CKG_I_SMART2_SYNTH_432_0C30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C30_CKGEN00_V004_REG_CKG_G_SMART2_SYNTH_432_MHEG5_0C30 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0C30_CKGEN00_V004_REG_CKG_I_SMART2_SYNTH_432_MHEG5_0C30 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0C38_CKGEN00_V004 (CKGEN00_V004 + 0xC38)
	#define REG_0C38_CKGEN00_V004_REG_CKG_G_SMART2_SYNTH_27_0C38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C38_CKGEN00_V004_REG_CKG_I_SMART2_SYNTH_27_0C38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C38_CKGEN00_V004_REG_CKG_G_SMART2_SYNTH_27_MHEG5_0C38 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0C38_CKGEN00_V004_REG_CKG_I_SMART2_SYNTH_27_MHEG5_0C38 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0C40_CKGEN00_V004 (CKGEN00_V004 + 0xC40)
	#define REG_0C40_CKGEN00_V004_REG_CKG_G_SMART_SYNTH_432_0C40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C40_CKGEN00_V004_REG_CKG_I_SMART_SYNTH_432_0C40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C40_CKGEN00_V004_REG_CKG_G_SMART_SYNTH_432_MHEG5_0C40 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0C40_CKGEN00_V004_REG_CKG_I_SMART_SYNTH_432_MHEG5_0C40 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0C48_CKGEN00_V004 (CKGEN00_V004 + 0xC48)
	#define REG_0C48_CKGEN00_V004_REG_CKG_G_SMART_SYNTH_27_0C48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C48_CKGEN00_V004_REG_CKG_I_SMART_SYNTH_27_0C48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C48_CKGEN00_V004_REG_CKG_G_SMART_SYNTH_27_MHEG5_0C48 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0C48_CKGEN00_V004_REG_CKG_I_SMART_SYNTH_27_MHEG5_0C48 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0C50_CKGEN00_V004 (CKGEN00_V004 + 0xC50)
	#define REG_0C50_CKGEN00_V004_REG_CKG_G_PATH0_27M_0C50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C50_CKGEN00_V004_REG_CKG_I_PATH0_27M_0C50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C50_CKGEN00_V004_REG_CKG_S_PATH0_27M_0C50 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C58_CKGEN00_V004 (CKGEN00_V004 + 0xC58)
	#define REG_0C58_CKGEN00_V004_REG_CKG_G_PATH1_27M_0C58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C58_CKGEN00_V004_REG_CKG_I_PATH1_27M_0C58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C58_CKGEN00_V004_REG_CKG_S_PATH1_27M_0C58 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C60_CKGEN00_V004 (CKGEN00_V004 + 0xC60)
	#define REG_0C60_CKGEN00_V004_REG_CKG_G_PATH2_27M_0C60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C60_CKGEN00_V004_REG_CKG_I_PATH2_27M_0C60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C60_CKGEN00_V004_REG_CKG_S_PATH2_27M_0C60 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C68_CKGEN00_V004 (CKGEN00_V004 + 0xC68)
	#define REG_0C68_CKGEN00_V004_REG_CKG_G_PATH_FI_27M_0C68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C68_CKGEN00_V004_REG_CKG_I_PATH_FI_27M_0C68 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C68_CKGEN00_V004_REG_CKG_S_PATH_FI_27M_0C68 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C70_CKGEN00_V004 (CKGEN00_V004 + 0xC70)
	#define REG_0C70_CKGEN00_V004_REG_CKG_G_MCU_NONPM_USB20_PHY_0C70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C70_CKGEN00_V004_REG_CKG_I_MCU_NONPM_USB20_PHY_0C70 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0C78_CKGEN00_V004 (CKGEN00_V004 + 0xC78)
	#define REG_0C78_CKGEN00_V004_REG_CKG_G_MCU_NONPM_USB_PHY_0C78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C78_CKGEN00_V004_REG_CKG_I_MCU_NONPM_USB_PHY_0C78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C78_CKGEN00_V004_REG_CKG_G_XTAL_12M_USB_PHY_0C78 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_0C78_CKGEN00_V004_REG_CKG_I_XTAL_12M_USB_PHY_0C78 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_0C90_CKGEN00_V004 (CKGEN00_V004 + 0xC90)
	#define REG_0C90_CKGEN00_V004_REG_CKG_G_VIVA_AB_MAC_10CH_0C90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C90_CKGEN00_V004_REG_CKG_I_VIVA_AB_MAC_10CH_0C90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C90_CKGEN00_V004_REG_CKG_S_VIVA_AB_MAC_10CH_0C90 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0C94_CKGEN00_V004 (CKGEN00_V004 + 0xC94)
	#define REG_0C94_CKGEN00_V004_REG_CKG_G_SYNTH_PCM_TRX_256FS_VIVALDI9_0C94 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C94_CKGEN00_V004_REG_CKG_I_SYNTH_PCM_TRX_256FS_VIVALDI9_0C94 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C94_CKGEN00_V004_REG_CKG_S_SYNTH_PCM_TRX_256FS_VIVALDI9_0C94 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0C98_CKGEN00_V004 (CKGEN00_V004 + 0xC98)
	#define REG_0C98_CKGEN00_V004_REG_CKG_G_AUSDM_3M_0C98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0C98_CKGEN00_V004_REG_CKG_I_AUSDM_3M_0C98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0C98_CKGEN00_V004_REG_CKG_S_AUSDM_3M_0C98 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CA0_CKGEN00_V004 (CKGEN00_V004 + 0xCA0)
	#define REG_0CA0_CKGEN00_V004_REG_CKG_G_BCLK_I2S_ENCODER2_0CA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CA0_CKGEN00_V004_REG_CKG_I_BCLK_I2S_ENCODER2_0CA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CA0_CKGEN00_V004_REG_CKG_S_BCLK_I2S_ENCODER2_0CA0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CA8_CKGEN00_V004 (CKGEN00_V004 + 0xCA8)
	#define REG_0CA8_CKGEN00_V004_REG_CKG_G_BCLK_I2S_ENCODER_0CA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CA8_CKGEN00_V004_REG_CKG_I_BCLK_I2S_ENCODER_0CA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CA8_CKGEN00_V004_REG_CKG_S_BCLK_I2S_ENCODER_0CA8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CB0_CKGEN00_V004 (CKGEN00_V004 + 0xCB0)
	#define REG_0CB0_CKGEN00_V004_REG_CKG_G_EARC_TX_PLL_256FS_REF_0CB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CB0_CKGEN00_V004_REG_CKG_I_EARC_TX_PLL_256FS_REF_0CB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CB0_CKGEN00_V004_REG_CKG_S_EARC_TX_PLL_256FS_REF_0CB0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CB4_CKGEN00_V004 (CKGEN00_V004 + 0xCB4)
	#define REG_0CB4_CKGEN00_V004_REG_CKG_S_EARC_TX_PLL_256FS_MUX_0CB4 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0CB8_CKGEN00_V004 (CKGEN00_V004 + 0xCB8)
	#define REG_0CB8_CKGEN00_V004_REG_CKG_G_VIVA_AB3_MAC_0CB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CB8_CKGEN00_V004_REG_CKG_I_VIVA_AB3_MAC_0CB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CB8_CKGEN00_V004_REG_CKG_S_VIVA_AB3_MAC_0CB8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0CC0_CKGEN00_V004 (CKGEN00_V004 + 0xCC0)
	#define REG_0CC0_CKGEN00_V004_REG_CKG_G_VIVA_AB_MAC_0CC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CC0_CKGEN00_V004_REG_CKG_I_VIVA_AB_MAC_0CC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CC0_CKGEN00_V004_REG_CKG_S_VIVA_AB_MAC_0CC0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CC8_CKGEN00_V004 (CKGEN00_V004 + 0xCC8)
	#define REG_0CC8_CKGEN00_V004_REG_CKG_G_VIVA_ADC_512FS_0CC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CC8_CKGEN00_V004_REG_CKG_I_VIVA_ADC_512FS_0CC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CC8_CKGEN00_V004_REG_CKG_S_VIVA_ADC_512FS_0CC8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CD0_CKGEN00_V004 (CKGEN00_V004 + 0xCD0)
	#define REG_0CD0_CKGEN00_V004_REG_CKG_G_VIVA_AUDMA_V2_R1_256FS_0CD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CD0_CKGEN00_V004_REG_CKG_I_VIVA_AUDMA_V2_R1_256FS_0CD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CD0_CKGEN00_V004_REG_CKG_S_VIVA_AUDMA_V2_R1_256FS_0CD0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CD8_CKGEN00_V004 (CKGEN00_V004 + 0xCD8)
	#define REG_0CD8_CKGEN00_V004_REG_CKG_G_VIVA_AUDMA_V2_R1_SYNTH_REF_0CD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CD8_CKGEN00_V004_REG_CKG_I_VIVA_AUDMA_V2_R1_SYNTH_REF_0CD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CD8_CKGEN00_V004_REG_CKG_S_VIVA_AUDMA_V2_R1_SYNTH_REF_0CD8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0CE0_CKGEN00_V004 (CKGEN00_V004 + 0xCE0)
	#define REG_0CE0_CKGEN00_V004_REG_CKG_G_VIVA_AUDMA_V2_R2_256FS_0CE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CE0_CKGEN00_V004_REG_CKG_I_VIVA_AUDMA_V2_R2_256FS_0CE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CE0_CKGEN00_V004_REG_CKG_S_VIVA_AUDMA_V2_R2_256FS_0CE0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0CE8_CKGEN00_V004 (CKGEN00_V004 + 0xCE8)
	#define REG_0CE8_CKGEN00_V004_REG_CKG_G_VIVA_AUDMA_V2_R2_SYNTH_REF_0CE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CE8_CKGEN00_V004_REG_CKG_I_VIVA_AUDMA_V2_R2_SYNTH_REF_0CE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CE8_CKGEN00_V004_REG_CKG_S_VIVA_AUDMA_V2_R2_SYNTH_REF_0CE8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0CF0_CKGEN00_V004 (CKGEN00_V004 + 0xCF0)
	#define REG_0CF0_CKGEN00_V004_REG_CKG_G_VIVA_AUPLL_IN_0CF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CF0_CKGEN00_V004_REG_CKG_I_VIVA_AUPLL_IN_0CF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CF0_CKGEN00_V004_REG_CKG_S_VIVA_AUPLL_IN_0CF0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0CF8_CKGEN00_V004 (CKGEN00_V004 + 0xCF8)
	#define REG_0CF8_CKGEN00_V004_REG_CKG_G_VIVA_BCLK_I2S_DECODER2_0CF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0CF8_CKGEN00_V004_REG_CKG_I_VIVA_BCLK_I2S_DECODER2_0CF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0CF8_CKGEN00_V004_REG_CKG_S_VIVA_BCLK_I2S_DECODER2_0CF8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D00_CKGEN00_V004 (CKGEN00_V004 + 0xD00)
	#define REG_0D00_CKGEN00_V004_REG_CKG_G_VIVA_BCLK_I2S_DECODER_0D00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D00_CKGEN00_V004_REG_CKG_I_VIVA_BCLK_I2S_DECODER_0D00 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D00_CKGEN00_V004_REG_CKG_S_VIVA_BCLK_I2S_DECODER_0D00 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D08_CKGEN00_V004 (CKGEN00_V004 + 0xD08)
	#define REG_0D08_CKGEN00_V004_REG_CKG_G_VIVA_BI2S_SYNTH_REF2_0D08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D08_CKGEN00_V004_REG_CKG_I_VIVA_BI2S_SYNTH_REF2_0D08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D08_CKGEN00_V004_REG_CKG_S_VIVA_BI2S_SYNTH_REF2_0D08 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0D10_CKGEN00_V004 (CKGEN00_V004 + 0xD10)
	#define REG_0D10_CKGEN00_V004_REG_CKG_VIVA_CH1_256FSI_0D10 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D18_CKGEN00_V004 (CKGEN00_V004 + 0xD18)
	#define REG_0D18_CKGEN00_V004_REG_CKG_VIVA_CH2_256FSI_0D18 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D20_CKGEN00_V004 (CKGEN00_V004 + 0xD20)
	#define REG_0D20_CKGEN00_V004_REG_CKG_VIVA_CH3_256FSI_0D20 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D28_CKGEN00_V004 (CKGEN00_V004 + 0xD28)
	#define REG_0D28_CKGEN00_V004_REG_CKG_VIVA_CH4_256FSI_0D28 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0D30_CKGEN00_V004 (CKGEN00_V004 + 0xD30)
	#define REG_0D30_CKGEN00_V004_REG_CKG_G_VIVA_CH5_256FSI_0D30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D30_CKGEN00_V004_REG_CKG_I_VIVA_CH5_256FSI_0D30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D30_CKGEN00_V004_REG_CKG_S_VIVA_CH5_256FSI_0D30 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D38_CKGEN00_V004 (CKGEN00_V004 + 0xD38)
	#define REG_0D38_CKGEN00_V004_REG_CKG_G_VIVA_CH6_256FSI_0D38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D38_CKGEN00_V004_REG_CKG_I_VIVA_CH6_256FSI_0D38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D38_CKGEN00_V004_REG_CKG_S_VIVA_CH6_256FSI_0D38 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D40_CKGEN00_V004 (CKGEN00_V004 + 0xD40)
	#define REG_0D40_CKGEN00_V004_REG_CKG_G_VIVA_CH7_256FSI_0D40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D40_CKGEN00_V004_REG_CKG_I_VIVA_CH7_256FSI_0D40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D40_CKGEN00_V004_REG_CKG_S_VIVA_CH7_256FSI_0D40 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D48_CKGEN00_V004 (CKGEN00_V004 + 0xD48)
	#define REG_0D48_CKGEN00_V004_REG_CKG_G_VIVA_CH8_256FSI_0D48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D48_CKGEN00_V004_REG_CKG_I_VIVA_CH8_256FSI_0D48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D48_CKGEN00_V004_REG_CKG_S_VIVA_CH8_256FSI_0D48 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D50_CKGEN00_V004 (CKGEN00_V004 + 0xD50)
	#define REG_0D50_CKGEN00_V004_REG_CKG_G_VIVA_CH9_256FSI_0D50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D50_CKGEN00_V004_REG_CKG_I_VIVA_CH9_256FSI_0D50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D50_CKGEN00_V004_REG_CKG_S_VIVA_CH9_256FSI_0D50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D58_CKGEN00_V004 (CKGEN00_V004 + 0xD58)
	#define REG_0D58_CKGEN00_V004_REG_CKG_G_VIVA_CODEC_SH_0D58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D58_CKGEN00_V004_REG_CKG_I_VIVA_CODEC_SH_0D58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D58_CKGEN00_V004_REG_CKG_S_VIVA_CODEC_SH_0D58 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D60_CKGEN00_V004 (CKGEN00_V004 + 0xD60)
	#define REG_0D60_CKGEN00_V004_REG_CKG_G_VIVA_DAC_512FS_0D60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D60_CKGEN00_V004_REG_CKG_I_VIVA_DAC_512FS_0D60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D60_CKGEN00_V004_REG_CKG_S_VIVA_DAC_512FS_0D60 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D68_CKGEN00_V004 (CKGEN00_V004 + 0xD68)
	#define REG_0D68_CKGEN00_V004_REG_CKG_G_VIVA_DSP_0D68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D68_CKGEN00_V004_REG_CKG_I_VIVA_DSP_0D68 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D68_CKGEN00_V004_REG_CKG_S_VIVA_DSP_0D68 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0D70_CKGEN00_V004 (CKGEN00_V004 + 0xD70)
	#define REG_0D70_CKGEN00_V004_REG_CKG_G_VIVA_DVB1_SYNTH_REF_0D70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D70_CKGEN00_V004_REG_CKG_I_VIVA_DVB1_SYNTH_REF_0D70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D70_CKGEN00_V004_REG_CKG_S_VIVA_DVB1_SYNTH_REF_0D70 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D78_CKGEN00_V004 (CKGEN00_V004 + 0xD78)
	#define REG_0D78_CKGEN00_V004_REG_CKG_G_VIVA_DVB1_TIMING_GEN_256FS_0D78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D78_CKGEN00_V004_REG_CKG_I_VIVA_DVB1_TIMING_GEN_256FS_0D78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D78_CKGEN00_V004_REG_CKG_S_VIVA_DVB1_TIMING_GEN_256FS_0D78 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D80_CKGEN00_V004 (CKGEN00_V004 + 0xD80)
	#define REG_0D80_CKGEN00_V004_REG_CKG_G_VIVA_DVB2_SYNTH_REF_0D80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D80_CKGEN00_V004_REG_CKG_I_VIVA_DVB2_SYNTH_REF_0D80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D80_CKGEN00_V004_REG_CKG_S_VIVA_DVB2_SYNTH_REF_0D80 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D88_CKGEN00_V004 (CKGEN00_V004 + 0xD88)
	#define REG_0D88_CKGEN00_V004_REG_CKG_G_VIVA_DVB2_TIMING_GEN_256FS_0D88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D88_CKGEN00_V004_REG_CKG_I_VIVA_DVB2_TIMING_GEN_256FS_0D88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D88_CKGEN00_V004_REG_CKG_S_VIVA_DVB2_TIMING_GEN_256FS_0D88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0D90_CKGEN00_V004 (CKGEN00_V004 + 0xD90)
	#define REG_0D90_CKGEN00_V004_REG_CKG_G_VIVA_DVB3_SYNTH_REF_0D90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D90_CKGEN00_V004_REG_CKG_I_VIVA_DVB3_SYNTH_REF_0D90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D90_CKGEN00_V004_REG_CKG_S_VIVA_DVB3_SYNTH_REF_0D90 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0D98_CKGEN00_V004 (CKGEN00_V004 + 0xD98)
	#define REG_0D98_CKGEN00_V004_REG_CKG_G_VIVA_DVB3_TIMING_GEN_256FS_0D98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0D98_CKGEN00_V004_REG_CKG_I_VIVA_DVB3_TIMING_GEN_256FS_0D98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0D98_CKGEN00_V004_REG_CKG_S_VIVA_DVB3_TIMING_GEN_256FS_0D98 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DA0_CKGEN00_V004 (CKGEN00_V004 + 0xDA0)
	#define REG_0DA0_CKGEN00_V004_REG_CKG_G_VIVA_DVB4_SYNTH_REF_0DA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DA0_CKGEN00_V004_REG_CKG_I_VIVA_DVB4_SYNTH_REF_0DA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DA0_CKGEN00_V004_REG_CKG_S_VIVA_DVB4_SYNTH_REF_0DA0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0DA8_CKGEN00_V004 (CKGEN00_V004 + 0xDA8)
	#define REG_0DA8_CKGEN00_V004_REG_CKG_G_VIVA_DVB4_TIMING_GEN_256FS_0DA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DA8_CKGEN00_V004_REG_CKG_I_VIVA_DVB4_TIMING_GEN_256FS_0DA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DA8_CKGEN00_V004_REG_CKG_S_VIVA_DVB4_TIMING_GEN_256FS_0DA8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DB0_CKGEN00_V004 (CKGEN00_V004 + 0xDB0)
	#define REG_0DB0_CKGEN00_V004_REG_CKG_G_VIVA_DVB5_TIMING_GEN_256FS_0DB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DB0_CKGEN00_V004_REG_CKG_I_VIVA_DVB5_TIMING_GEN_256FS_0DB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DB0_CKGEN00_V004_REG_CKG_S_VIVA_DVB5_TIMING_GEN_256FS_0DB0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DB8_CKGEN00_V004 (CKGEN00_V004 + 0xDB8)
	#define REG_0DB8_CKGEN00_V004_REG_CKG_G_VIVA_DVB6_TIMING_GEN_256FS_0DB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DB8_CKGEN00_V004_REG_CKG_I_VIVA_DVB6_TIMING_GEN_256FS_0DB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DB8_CKGEN00_V004_REG_CKG_S_VIVA_DVB6_TIMING_GEN_256FS_0DB8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DC0_CKGEN00_V004 (CKGEN00_V004 + 0xDC0)
	#define REG_0DC0_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_32XCHXFS_0DC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DC0_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_32XCHXFS_0DC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DC0_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_32XCHXFS_0DC0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DC8_CKGEN00_V004 (CKGEN00_V004 + 0xDC8)
	#define REG_0DC8_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_32XFS_0DC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DC8_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_32XFS_0DC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DC8_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_32XFS_0DC8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DD0_CKGEN00_V004 (CKGEN00_V004 + 0xDD0)
	#define REG_0DD0_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_64XCHXFS_0DD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DD0_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_64XCHXFS_0DD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DD0_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_64XCHXFS_0DD0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DD8_CKGEN00_V004 (CKGEN00_V004 + 0xDD8)
	#define REG_0DD8_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_GPA_SYNTH_REF_0DD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DD8_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_GPA_SYNTH_REF_0DD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DD8_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_GPA_SYNTH_REF_0DD8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DE0_CKGEN00_V004 (CKGEN00_V004 + 0xDE0)
	#define REG_0DE0_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_PLL_0DE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DE0_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_PLL_0DE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DE0_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_PLL_0DE0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DE8_CKGEN00_V004 (CKGEN00_V004 + 0xDE8)
	#define REG_0DE8_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_SOURCE_256FS_0DE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DE8_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_SOURCE_256FS_0DE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DE8_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_SOURCE_256FS_0DE8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DF0_CKGEN00_V004 (CKGEN00_V004 + 0xDF0)
	#define REG_0DF0_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_SYNTH_IIR_REF_0DF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DF0_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_SYNTH_IIR_REF_0DF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DF0_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_SYNTH_IIR_REF_0DF0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0DF8_CKGEN00_V004 (CKGEN00_V004 + 0xDF8)
	#define REG_0DF8_CKGEN00_V004_REG_CKG_G_VIVA_EARC_TX_SYNTH_REF_0DF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0DF8_CKGEN00_V004_REG_CKG_I_VIVA_EARC_TX_SYNTH_REF_0DF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0DF8_CKGEN00_V004_REG_CKG_S_VIVA_EARC_TX_SYNTH_REF_0DF8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E00_CKGEN00_V004 (CKGEN00_V004 + 0xE00)
	#define REG_0E00_CKGEN00_V004_REG_CKG_G_VIVA_FM_DEMODULATOR_0E00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E00_CKGEN00_V004_REG_CKG_I_VIVA_FM_DEMODULATOR_0E00 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E00_CKGEN00_V004_REG_CKG_S_VIVA_FM_DEMODULATOR_0E00 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0E08_CKGEN00_V004 (CKGEN00_V004 + 0xE08)
	#define REG_0E08_CKGEN00_V004_REG_CKG_G_VIVA_GPA_240FSO_0E08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E08_CKGEN00_V004_REG_CKG_I_VIVA_GPA_240FSO_0E08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E08_CKGEN00_V004_REG_CKG_S_VIVA_GPA_240FSO_0E08 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E10_CKGEN00_V004 (CKGEN00_V004 + 0xE10)
	#define REG_0E10_CKGEN00_V004_REG_CKG_G_VIVA_GPA_256FSO_0E10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E10_CKGEN00_V004_REG_CKG_I_VIVA_GPA_256FSO_0E10 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E10_CKGEN00_V004_REG_CKG_S_VIVA_GPA_256FSO_0E10 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E18_CKGEN00_V004 (CKGEN00_V004 + 0xE18)
	#define REG_0E18_CKGEN00_V004_REG_CKG_G_VIVA_GPA_480FSO_0E18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E18_CKGEN00_V004_REG_CKG_I_VIVA_GPA_480FSO_0E18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E18_CKGEN00_V004_REG_CKG_S_VIVA_GPA_480FSO_0E18 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E20_CKGEN00_V004 (CKGEN00_V004 + 0xE20)
	#define REG_0E20_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX2_MPLL_432_0E20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E20_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX2_MPLL_432_0E20 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E20_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX2_MPLL_432_0E20 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E28_CKGEN00_V004 (CKGEN00_V004 + 0xE28)
	#define REG_0E28_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX2_S2P_128FS_0E28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E28_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX2_S2P_128FS_0E28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E28_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX2_S2P_128FS_0E28 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E30_CKGEN00_V004 (CKGEN00_V004 + 0xE30)
	#define REG_0E30_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX2_S2P_256FS_0E30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E30_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX2_S2P_256FS_0E30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E30_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX2_S2P_256FS_0E30 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E38_CKGEN00_V004 (CKGEN00_V004 + 0xE38)
	#define REG_0E38_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX2_SYNTH_REF_0E38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E38_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX2_SYNTH_REF_0E38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E38_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX2_SYNTH_REF_0E38 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E40_CKGEN00_V004 (CKGEN00_V004 + 0xE40)
	#define REG_0E40_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX2_V2A_TIME_STAMP_0E40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E40_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX2_V2A_TIME_STAMP_0E40 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0E48_CKGEN00_V004 (CKGEN00_V004 + 0xE48)
	#define REG_0E48_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX_MPLL_432_0E48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E48_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX_MPLL_432_0E48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E48_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX_MPLL_432_0E48 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E50_CKGEN00_V004 (CKGEN00_V004 + 0xE50)
	#define REG_0E50_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX_S2P_128FS_0E50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E50_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX_S2P_128FS_0E50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E50_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX_S2P_128FS_0E50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E58_CKGEN00_V004 (CKGEN00_V004 + 0xE58)
	#define REG_0E58_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX_S2P_256FS_0E58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E58_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX_S2P_256FS_0E58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E58_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX_S2P_256FS_0E58 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E60_CKGEN00_V004 (CKGEN00_V004 + 0xE60)
	#define REG_0E60_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX_SYNTH_REF_0E60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E60_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX_SYNTH_REF_0E60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E60_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_RX_SYNTH_REF_0E60 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E68_CKGEN00_V004 (CKGEN00_V004 + 0xE68)
	#define REG_0E68_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_RX_V2A_TIME_STAMP_0E68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E68_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_RX_V2A_TIME_STAMP_0E68 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0E70_CKGEN00_V004 (CKGEN00_V004 + 0xE70)
	#define REG_0E70_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_TX_128FS_0E70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E70_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_TX_128FS_0E70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E70_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_TX_128FS_0E70 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E78_CKGEN00_V004 (CKGEN00_V004 + 0xE78)
	#define REG_0E78_CKGEN00_V004_REG_CKG_G_VIVA_HDMI_TX_256FS_0E78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E78_CKGEN00_V004_REG_CKG_I_VIVA_HDMI_TX_256FS_0E78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E78_CKGEN00_V004_REG_CKG_S_VIVA_HDMI_TX_256FS_0E78 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E80_CKGEN00_V004 (CKGEN00_V004 + 0xE80)
	#define REG_0E80_CKGEN00_V004_REG_CKG_G_VIVA_I2S_2_BCLK_SYNTH_REF_0E80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E80_CKGEN00_V004_REG_CKG_I_VIVA_I2S_2_BCLK_SYNTH_REF_0E80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E80_CKGEN00_V004_REG_CKG_S_VIVA_I2S_2_BCLK_SYNTH_REF_0E80 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0E88_CKGEN00_V004 (CKGEN00_V004 + 0xE88)
	#define REG_0E88_CKGEN00_V004_REG_CKG_G_VIVA_I2S_BCLK_DG2_0E88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E88_CKGEN00_V004_REG_CKG_I_VIVA_I2S_BCLK_DG2_0E88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E88_CKGEN00_V004_REG_CKG_S_VIVA_I2S_BCLK_DG2_0E88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E90_CKGEN00_V004 (CKGEN00_V004 + 0xE90)
	#define REG_0E90_CKGEN00_V004_REG_CKG_G_VIVA_I2S_BCLK_DG_0E90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E90_CKGEN00_V004_REG_CKG_I_VIVA_I2S_BCLK_DG_0E90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E90_CKGEN00_V004_REG_CKG_S_VIVA_I2S_BCLK_DG_0E90 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0E98_CKGEN00_V004 (CKGEN00_V004 + 0xE98)
	#define REG_0E98_CKGEN00_V004_REG_CKG_G_VIVA_I2S_BCLK_SYNTH_REF_0E98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0E98_CKGEN00_V004_REG_CKG_I_VIVA_I2S_BCLK_SYNTH_REF_0E98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0E98_CKGEN00_V004_REG_CKG_S_VIVA_I2S_BCLK_SYNTH_REF_0E98 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0EA0_CKGEN00_V004 (CKGEN00_V004 + 0xEA0)
	#define REG_0EA0_CKGEN00_V004_REG_CKG_G_VIVA_I2S_MCLK_SYNTH_REF_0EA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EA0_CKGEN00_V004_REG_CKG_I_VIVA_I2S_MCLK_SYNTH_REF_0EA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EA0_CKGEN00_V004_REG_CKG_S_VIVA_I2S_MCLK_SYNTH_REF_0EA0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0EA8_CKGEN00_V004 (CKGEN00_V004 + 0xEA8)
	#define REG_0EA8_CKGEN00_V004_REG_CKG_G_VIVA_I2S_SYNTH_REF_0EA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EA8_CKGEN00_V004_REG_CKG_I_VIVA_I2S_SYNTH_REF_0EA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EA8_CKGEN00_V004_REG_CKG_S_VIVA_I2S_SYNTH_REF_0EA8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0EB0_CKGEN00_V004 (CKGEN00_V004 + 0xEB0)
	#define REG_0EB0_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TRX_BCLK_TIMING_GEN_0EB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EB0_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TRX_BCLK_TIMING_GEN_0EB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EB0_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TRX_BCLK_TIMING_GEN_0EB0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0EB8_CKGEN00_V004 (CKGEN00_V004 + 0xEB8)
	#define REG_0EB8_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TRX_SYNTH_REF_0EB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EB8_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TRX_SYNTH_REF_0EB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EB8_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TRX_SYNTH_REF_0EB8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0EC0_CKGEN00_V004 (CKGEN00_V004 + 0xEC0)
	#define REG_0EC0_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TX_FIFO_256FS_0EC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EC0_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TX_FIFO_256FS_0EC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EC0_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TX_FIFO_256FS_0EC0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0EC8_CKGEN00_V004 (CKGEN00_V004 + 0xEC8)
	#define REG_0EC8_CKGEN00_V004_REG_CKG_G_VIVA_MCLK_I2S_DECODER2_0EC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EC8_CKGEN00_V004_REG_CKG_I_VIVA_MCLK_I2S_DECODER2_0EC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EC8_CKGEN00_V004_REG_CKG_S_VIVA_MCLK_I2S_DECODER2_0EC8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0ED0_CKGEN00_V004 (CKGEN00_V004 + 0xED0)
	#define REG_0ED0_CKGEN00_V004_REG_CKG_G_VIVA_MCLK_I2S_DECODER_0ED0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0ED0_CKGEN00_V004_REG_CKG_I_VIVA_MCLK_I2S_DECODER_0ED0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0ED0_CKGEN00_V004_REG_CKG_S_VIVA_MCLK_I2S_DECODER_0ED0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0ED8_CKGEN00_V004 (CKGEN00_V004 + 0xED8)
	#define REG_0ED8_CKGEN00_V004_REG_CKG_G_VIVA_MCLK_I2S_ENCODER2_0ED8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0ED8_CKGEN00_V004_REG_CKG_I_VIVA_MCLK_I2S_ENCODER2_0ED8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0ED8_CKGEN00_V004_REG_CKG_S_VIVA_MCLK_I2S_ENCODER2_0ED8 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0EE0_CKGEN00_V004 (CKGEN00_V004 + 0xEE0)
	#define REG_0EE0_CKGEN00_V004_REG_CKG_G_VIVA_MCLK_I2S_ENCODER_0EE0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EE0_CKGEN00_V004_REG_CKG_I_VIVA_MCLK_I2S_ENCODER_0EE0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EE0_CKGEN00_V004_REG_CKG_S_VIVA_MCLK_I2S_ENCODER_0EE0 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0EE8_CKGEN00_V004 (CKGEN00_V004 + 0xEE8)
	#define REG_0EE8_CKGEN00_V004_REG_CKG_G_VIVA_NPCM2_SYNTH_REF_0EE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EE8_CKGEN00_V004_REG_CKG_I_VIVA_NPCM2_SYNTH_REF_0EE8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EE8_CKGEN00_V004_REG_CKG_S_VIVA_NPCM2_SYNTH_REF_0EE8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0EF0_CKGEN00_V004 (CKGEN00_V004 + 0xEF0)
	#define REG_0EF0_CKGEN00_V004_REG_CKG_G_VIVA_NPCM3_SYNTH_REF_0EF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EF0_CKGEN00_V004_REG_CKG_I_VIVA_NPCM3_SYNTH_REF_0EF0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EF0_CKGEN00_V004_REG_CKG_S_VIVA_NPCM3_SYNTH_REF_0EF0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0EF8_CKGEN00_V004 (CKGEN00_V004 + 0xEF8)
	#define REG_0EF8_CKGEN00_V004_REG_CKG_G_VIVA_NPCM4_256FS_TIMING_GEN_0EF8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0EF8_CKGEN00_V004_REG_CKG_I_VIVA_NPCM4_256FS_TIMING_GEN_0EF8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0EF8_CKGEN00_V004_REG_CKG_S_VIVA_NPCM4_256FS_TIMING_GEN_0EF8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F00_CKGEN00_V004 (CKGEN00_V004 + 0xF00)
	#define REG_0F00_CKGEN00_V004_REG_CKG_G_VIVA_NPCM4_SYNTH_REF_0F00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F00_CKGEN00_V004_REG_CKG_I_VIVA_NPCM4_SYNTH_REF_0F00 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F00_CKGEN00_V004_REG_CKG_S_VIVA_NPCM4_SYNTH_REF_0F00 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F08_CKGEN00_V004 (CKGEN00_V004 + 0xF08)
	#define REG_0F08_CKGEN00_V004_REG_CKG_G_VIVA_NPCM5_256FS_TIMING_GEN_0F08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F08_CKGEN00_V004_REG_CKG_I_VIVA_NPCM5_256FS_TIMING_GEN_0F08 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F08_CKGEN00_V004_REG_CKG_S_VIVA_NPCM5_256FS_TIMING_GEN_0F08 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F10_CKGEN00_V004 (CKGEN00_V004 + 0xF10)
	#define REG_0F10_CKGEN00_V004_REG_CKG_G_VIVA_NPCM5_SYNTH_REF_0F10 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F10_CKGEN00_V004_REG_CKG_I_VIVA_NPCM5_SYNTH_REF_0F10 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F10_CKGEN00_V004_REG_CKG_S_VIVA_NPCM5_SYNTH_REF_0F10 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F18_CKGEN00_V004 (CKGEN00_V004 + 0xF18)
	#define REG_0F18_CKGEN00_V004_REG_CKG_G_VIVA_NPCM_SYNTH_REF_0F18 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F18_CKGEN00_V004_REG_CKG_I_VIVA_NPCM_SYNTH_REF_0F18 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F18_CKGEN00_V004_REG_CKG_S_VIVA_NPCM_SYNTH_REF_0F18 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F20_CKGEN00_V004 (CKGEN00_V004 + 0xF20)
	#define REG_0F20_CKGEN00_V004_REG_CKG_G_VIVA_PCM_CLK_216_0F20 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F20_CKGEN00_V004_REG_CKG_I_VIVA_PCM_CLK_216_0F20 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F20_CKGEN00_V004_REG_CKG_S_VIVA_PCM_CLK_216_0F20 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F28_CKGEN00_V004 (CKGEN00_V004 + 0xF28)
	#define REG_0F28_CKGEN00_V004_REG_CKG_G_VIVA_PCM_CLK_AUPLL_0F28 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F28_CKGEN00_V004_REG_CKG_I_VIVA_PCM_CLK_AUPLL_0F28 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F28_CKGEN00_V004_REG_CKG_S_VIVA_PCM_CLK_AUPLL_0F28 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F2C_CKGEN00_V004 (CKGEN00_V004 + 0xF2C)
	#define REG_0F2C_CKGEN00_V004_REG_CKG_G_R2_VIVALDI9_0F2C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F2C_CKGEN00_V004_REG_CKG_I_R2_VIVALDI9_0F2C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F30_CKGEN00_V004 (CKGEN00_V004 + 0xF30)
	#define REG_0F30_CKGEN00_V004_REG_CKG_G_VIVA_R2_WB_0F30 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F30_CKGEN00_V004_REG_CKG_I_VIVA_R2_WB_0F30 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F30_CKGEN00_V004_REG_CKG_S_VIVA_R2_WB_0F30 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F34_CKGEN00_V004 (CKGEN00_V004 + 0xF34)
	#define REG_0F34_CKGEN00_V004_REG_CKG_G_MCU_BUS_AURV55_0F34 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F34_CKGEN00_V004_REG_CKG_I_MCU_BUS_AURV55_0F34 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F38_CKGEN00_V004 (CKGEN00_V004 + 0xF38)
	#define REG_0F38_CKGEN00_V004_REG_CKG_G_VIVA_RIU_BRG_R2_0F38 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F38_CKGEN00_V004_REG_CKG_I_VIVA_RIU_BRG_R2_0F38 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F38_CKGEN00_V004_REG_CKG_S_VIVA_RIU_BRG_R2_0F38 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F3C_CKGEN00_V004 (CKGEN00_V004 + 0xF3C)
	#define REG_0F3C_CKGEN00_V004_REG_CKG_G_MCU_NONPM_AURV55_0F3C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F3C_CKGEN00_V004_REG_CKG_I_MCU_NONPM_AURV55_0F3C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0F40_CKGEN00_V004 (CKGEN00_V004 + 0xF40)
	#define REG_0F40_CKGEN00_V004_REG_CKG_G_VIVA_RIU_R2_0F40 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F40_CKGEN00_V004_REG_CKG_I_VIVA_RIU_R2_0F40 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F40_CKGEN00_V004_REG_CKG_S_VIVA_RIU_R2_0F40 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F48_CKGEN00_V004 (CKGEN00_V004 + 0xF48)
	#define REG_0F48_CKGEN00_V004_REG_CKG_G_VIVA_SH_0F48 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F48_CKGEN00_V004_REG_CKG_I_VIVA_SH_0F48 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F48_CKGEN00_V004_REG_CKG_S_VIVA_SH_0F48 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F50_CKGEN00_V004 (CKGEN00_V004 + 0xF50)
	#define REG_0F50_CKGEN00_V004_REG_CKG_G_VIVA_SIF_ADC_CIC_0F50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F50_CKGEN00_V004_REG_CKG_I_VIVA_SIF_ADC_CIC_0F50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F50_CKGEN00_V004_REG_CKG_S_VIVA_SIF_ADC_CIC_0F50 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F58_CKGEN00_V004 (CKGEN00_V004 + 0xF58)
	#define REG_0F58_CKGEN00_V004_REG_CKG_G_VIVA_SIF_ADC_R2B_FIFO_IN_0F58 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F58_CKGEN00_V004_REG_CKG_I_VIVA_SIF_ADC_R2B_FIFO_IN_0F58 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F58_CKGEN00_V004_REG_CKG_S_VIVA_SIF_ADC_R2B_FIFO_IN_0F58 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F60_CKGEN00_V004 (CKGEN00_V004 + 0xF60)
	#define REG_0F60_CKGEN00_V004_REG_CKG_G_VIVA_SIF_ADC_R2B_0F60 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F60_CKGEN00_V004_REG_CKG_I_VIVA_SIF_ADC_R2B_0F60 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F60_CKGEN00_V004_REG_CKG_S_VIVA_SIF_ADC_R2B_0F60 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F68_CKGEN00_V004 (CKGEN00_V004 + 0xF68)
	#define REG_0F68_CKGEN00_V004_REG_CKG_G_SIF_CORDIC_0F68 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F68_CKGEN00_V004_REG_CKG_I_SIF_CORDIC_0F68 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F68_CKGEN00_V004_REG_CKG_S_SIF_CORDIC_0F68 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_0F70_CKGEN00_V004 (CKGEN00_V004 + 0xF70)
	#define REG_0F70_CKGEN00_V004_REG_CKG_G_VIVA_SIF_SYNTH_0F70 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F70_CKGEN00_V004_REG_CKG_I_VIVA_SIF_SYNTH_0F70 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F70_CKGEN00_V004_REG_CKG_S_VIVA_SIF_SYNTH_0F70 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0F78_CKGEN00_V004 (CKGEN00_V004 + 0xF78)
	#define REG_0F78_CKGEN00_V004_REG_CKG_G_VIVA_SIN_GEN_0F78 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F78_CKGEN00_V004_REG_CKG_I_VIVA_SIN_GEN_0F78 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F78_CKGEN00_V004_REG_CKG_S_VIVA_SIN_GEN_0F78 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F80_CKGEN00_V004 (CKGEN00_V004 + 0xF80)
	#define REG_0F80_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_EXTEARC_0F80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F80_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_EXTEARC_0F80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F80_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_EXTEARC_0F80 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F88_CKGEN00_V004 (CKGEN00_V004 + 0xF88)
	#define REG_0F88_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_RX_128FS_0F88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F88_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_RX_128FS_0F88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F88_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_RX_128FS_0F88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F90_CKGEN00_V004 (CKGEN00_V004 + 0xF90)
	#define REG_0F90_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_RX_DG_0F90 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F90_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_RX_DG_0F90 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F90_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_RX_DG_0F90 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0F98_CKGEN00_V004 (CKGEN00_V004 + 0xF98)
	#define REG_0F98_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_RX_SYNTH_REF_0F98 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0F98_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_RX_SYNTH_REF_0F98 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0F98_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_RX_SYNTH_REF_0F98 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0FA0_CKGEN00_V004 (CKGEN00_V004 + 0xFA0)
	#define REG_0FA0_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_TX2_128FS_0FA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FA0_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_TX2_128FS_0FA0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FA0_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_TX2_128FS_0FA0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FA8_CKGEN00_V004 (CKGEN00_V004 + 0xFA8)
	#define REG_0FA8_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_TX2_256FS_0FA8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FA8_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_TX2_256FS_0FA8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FA8_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_TX2_256FS_0FA8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FB0_CKGEN00_V004 (CKGEN00_V004 + 0xFB0)
	#define REG_0FB0_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_TX_128FS_0FB0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FB0_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_TX_128FS_0FB0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FB0_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_TX_128FS_0FB0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FB8_CKGEN00_V004 (CKGEN00_V004 + 0xFB8)
	#define REG_0FB8_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_TX_256FS_0FB8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FB8_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_TX_256FS_0FB8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FB8_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_TX_256FS_0FB8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FC0_CKGEN00_V004 (CKGEN00_V004 + 0xFC0)
	#define REG_0FC0_CKGEN00_V004_REG_CKG_G_VIVA_SPDIF_TX_SYNTH_REF_0FC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FC0_CKGEN00_V004_REG_CKG_I_VIVA_SPDIF_TX_SYNTH_REF_0FC0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FC0_CKGEN00_V004_REG_CKG_S_VIVA_SPDIF_TX_SYNTH_REF_0FC0 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FC8_CKGEN00_V004 (CKGEN00_V004 + 0xFC8)
	#define REG_0FC8_CKGEN00_V004_REG_CKG_G_VIVA_SYNTH_2ND_ORDER_0FC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FC8_CKGEN00_V004_REG_CKG_I_VIVA_SYNTH_2ND_ORDER_0FC8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FC8_CKGEN00_V004_REG_CKG_S_VIVA_SYNTH_2ND_ORDER_0FC8 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0FD0_CKGEN00_V004 (CKGEN00_V004 + 0xFD0)
	#define REG_0FD0_CKGEN00_V004_REG_CKG_G_VIVA_SYNTH_CODEC_0FD0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FD0_CKGEN00_V004_REG_CKG_I_VIVA_SYNTH_CODEC_0FD0 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FD0_CKGEN00_V004_REG_CKG_S_VIVA_SYNTH_CODEC_0FD0 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_0FD8_CKGEN00_V004 (CKGEN00_V004 + 0xFD8)
	#define REG_0FD8_CKGEN00_V004_REG_CKG_G_VIVA_TEST_BUS_0FD8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FD8_CKGEN00_V004_REG_CKG_I_VIVA_TEST_BUS_0FD8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0FD8_CKGEN00_V004_REG_CKG_S_VIVA_TEST_BUS_0FD8 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_0FE0_CKGEN00_V004 (CKGEN00_V004 + 0xFE0)
	#define REG_0FE0_CKGEN00_V004_REG_CKG_VIVA_VBDMA_MCU_0FE0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_0FE8_CKGEN00_V004 (CKGEN00_V004 + 0xFE8)
	#define REG_0FE8_CKGEN00_V004_REG_CKG_G_VIVA_XTAL_12M_0FE8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FE8_CKGEN00_V004_REG_CKG_I_VIVA_XTAL_12M_0FE8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0FF0_CKGEN00_V004 (CKGEN00_V004 + 0xFF0)
	#define REG_0FF0_CKGEN00_V004_REG_CKG_G_VIVA_XTAL_24M_0FF0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FF0_CKGEN00_V004_REG_CKG_I_VIVA_XTAL_24M_0FF0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_0FFC_CKGEN00_V004 (CKGEN00_V004 + 0xFFC)
	#define REG_0FFC_CKGEN00_V004_REG_CKG_G_XTAL_AURV55_0FFC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0FFC_CKGEN00_V004_REG_CKG_I_XTAL_AURV55_0FFC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1020_CKGEN00_V004 (CKGEN00_V004 + 0x1020)
	#define REG_1020_CKGEN00_V004_REG_CKG_S_AUDMA_V2_R1_256FS_1020 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1028_CKGEN00_V004 (CKGEN00_V004 + 0x1028)
	#define REG_1028_CKGEN00_V004_REG_CKG_S_BCLK_I2S_ENCODER2_MUX_1028 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_102C_CKGEN00_V004 (CKGEN00_V004 + 0x102C)
	#define REG_102C_CKGEN00_V004_REG_CKG_G_RV_AUDEC_102C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_102C_CKGEN00_V004_REG_CKG_I_RV_AUDEC_102C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_102C_CKGEN00_V004_REG_CKG_S_RV_AUDEC_102C Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1030_CKGEN00_V004 (CKGEN00_V004 + 0x1030)
	#define REG_1030_CKGEN00_V004_REG_CKG_S_BCLK_I2S_ENCODER_MUX_1030 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1034_CKGEN00_V004 (CKGEN00_V004 + 0x1034)
	#define REG_1034_CKGEN00_V004_REG_CKG_G_RV_AUSND_1034 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1034_CKGEN00_V004_REG_CKG_I_RV_AUSND_1034 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1034_CKGEN00_V004_REG_CKG_S_RV_AUSND_1034 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1058_CKGEN00_V004 (CKGEN00_V004 + 0x1058)
	#define REG_1058_CKGEN00_V004_REG_CKG_S_CH5_256FSI_MUX_1058 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1060_CKGEN00_V004 (CKGEN00_V004 + 0x1060)
	#define REG_1060_CKGEN00_V004_REG_CKG_S_CH6_256FSI_MUX_1060 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1068_CKGEN00_V004 (CKGEN00_V004 + 0x1068)
	#define REG_1068_CKGEN00_V004_REG_CKG_S_CH7_256FSI_MUX_1068 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1070_CKGEN00_V004 (CKGEN00_V004 + 0x1070)
	#define REG_1070_CKGEN00_V004_REG_CKG_S_CH8_256FSI_MUX_1070 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1078_CKGEN00_V004 (CKGEN00_V004 + 0x1078)
	#define REG_1078_CKGEN00_V004_REG_CKG_S_CH9_256FSI_MUX_1078 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1080_CKGEN00_V004 (CKGEN00_V004 + 0x1080)
	#define REG_1080_CKGEN00_V004_REG_CKG_S_DEC1_SYNTH_HDMI_CTSN_DIV_MUX_1080 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1088_CKGEN00_V004 (CKGEN00_V004 + 0x1088)
	#define REG_1088_CKGEN00_V004_REG_CKG_DEC1_SYNTH_SPDIF_CDR_DIV4_MUX_1088 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1090_CKGEN00_V004 (CKGEN00_V004 + 0x1090)
	#define REG_1090_CKGEN00_V004_REG_CKG_S_DEC2_SYNTH_HDMI_CTSN_DIV_MUX_1090 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1098_CKGEN00_V004 (CKGEN00_V004 + 0x1098)
	#define REG_1098_CKGEN00_V004_REG_CKG_DEC2_SYNTH_SPDIF_CDR_DIV4_MUX_1098 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10A0_CKGEN00_V004 (CKGEN00_V004 + 0x10A0)
	#define REG_10A0_CKGEN00_V004_REG_CKG_S_DEC3_SYNTH_HDMI_CTSN_DIV_MUX_10A0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_10A8_CKGEN00_V004 (CKGEN00_V004 + 0x10A8)
	#define REG_10A8_CKGEN00_V004_REG_CKG_DEC3_SYNTH_SPDIF_CDR_DIV4_MUX_10A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10B0_CKGEN00_V004 (CKGEN00_V004 + 0x10B0)
	#define REG_10B0_CKGEN00_V004_REG_CKG_S_DEC4_SYNTH_HDMI_CTSN_DIV_MUX_10B0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_10B8_CKGEN00_V004 (CKGEN00_V004 + 0x10B8)
	#define REG_10B8_CKGEN00_V004_REG_CKG_DEC4_SYNTH_SPDIF_CDR_DIV4_MUX_10B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10C0_CKGEN00_V004 (CKGEN00_V004 + 0x10C0)
	#define REG_10C0_CKGEN00_V004_REG_CKG_S_DECODER1_FUNCTION_MUX_10C0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10C8_CKGEN00_V004 (CKGEN00_V004 + 0x10C8)
	#define REG_10C8_CKGEN00_V004_REG_CKG_S_DECODER2_FUNCTION_MUX_10C8 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10D0_CKGEN00_V004 (CKGEN00_V004 + 0x10D0)
	#define REG_10D0_CKGEN00_V004_REG_CKG_S_DECODER3_FUNCTION_MUX_10D0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10D8_CKGEN00_V004 (CKGEN00_V004 + 0x10D8)
	#define REG_10D8_CKGEN00_V004_REG_CKG_S_DECODER4_FUNCTION_MUX_10D8 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_10E0_CKGEN00_V004 (CKGEN00_V004 + 0x10E0)
	#define REG_10E0_CKGEN00_V004_REG_CKG_S_EARC_TX_GPA_SYNTH_MUX_10E0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_10E8_CKGEN00_V004 (CKGEN00_V004 + 0x10E8)
	#define REG_10E8_CKGEN00_V004_REG_CKG_S_EARC_TX_SOURCE_MUX_10E8 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_10F0_CKGEN00_V004 (CKGEN00_V004 + 0x10F0)
	#define REG_10F0_CKGEN00_V004_REG_CKG_S_HDMI2_PATGEN_EN_10F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_10F8_CKGEN00_V004 (CKGEN00_V004 + 0x10F8)
	#define REG_10F8_CKGEN00_V004_REG_CKG_S_HDMI_PATGEN_EN_10F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1100_CKGEN00_V004 (CKGEN00_V004 + 0x1100)
	#define REG_1100_CKGEN00_V004_REG_CKG_S_HDMI_RX_BYPASS_TO_TX_1100 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1108_CKGEN00_V004 (CKGEN00_V004 + 0x1108)
	#define REG_1108_CKGEN00_V004_REG_CKG_S_HDMI_TX_256FS_MUX0_1108 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1110_CKGEN00_V004 (CKGEN00_V004 + 0x1110)
	#define REG_1110_CKGEN00_V004_REG_CKG_S_HDMI_TX_256FS_MUX1_1110 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1118_CKGEN00_V004 (CKGEN00_V004 + 0x1118)
	#define REG_1118_CKGEN00_V004_REG_CKG_S_HDMI_TX_TO_I2S_TX_1118 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1120_CKGEN00_V004 (CKGEN00_V004 + 0x1120)
	#define REG_1120_CKGEN00_V004_REG_CKG_S_I2S_2_SYNTH_SSC_MUX_1120 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1128_CKGEN00_V004 (CKGEN00_V004 + 0x1128)
	#define REG_1128_CKGEN00_V004_REG_CKG_S_I2S_CH_1128 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1130_CKGEN00_V004 (CKGEN00_V004 + 0x1130)
	#define REG_1130_CKGEN00_V004_REG_CKG_S_I2S_SYNTH_SSC_MUX_1130 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1138_CKGEN00_V004 (CKGEN00_V004 + 0x1138)
	#define REG_1138_CKGEN00_V004_REG_CKG_S_PCM_MODE_1138 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1140_CKGEN00_V004 (CKGEN00_V004 + 0x1140)
	#define REG_1140_CKGEN00_V004_REG_CKG_S_R2_WB_MUX_1140 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1148_CKGEN00_V004 (CKGEN00_V004 + 0x1148)
	#define REG_1148_CKGEN00_V004_REG_CKG_S_SPDIF_EXTEARC_128FS_MUX_1148 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1150_CKGEN00_V004 (CKGEN00_V004 + 0x1150)
	#define REG_1150_CKGEN00_V004_REG_CKG_S_SPDIF_EXTEARC_256FS_MUX_1150 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1158_CKGEN00_V004 (CKGEN00_V004 + 0x1158)
	#define REG_1158_CKGEN00_V004_REG_CKG_S_SPDIF_EXTEARC_MUX_1158 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1160_CKGEN00_V004 (CKGEN00_V004 + 0x1160)
	#define REG_1160_CKGEN00_V004_REG_CKG_S_SPDIF_EXTEARC_MUX0_1160 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1168_CKGEN00_V004 (CKGEN00_V004 + 0x1168)
	#define REG_1168_CKGEN00_V004_REG_CKG_S_SPDIF_TX2_GPA_SYNTH_MUX_1168 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1170_CKGEN00_V004 (CKGEN00_V004 + 0x1170)
	#define REG_1170_CKGEN00_V004_REG_CKG_S_SPDIF_TX2_MUX_1170 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1178_CKGEN00_V004 (CKGEN00_V004 + 0x1178)
	#define REG_1178_CKGEN00_V004_REG_CKG_S_SPDIF_TX_GPA_SYNTH_MUX_1178 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1180_CKGEN00_V004 (CKGEN00_V004 + 0x1180)
	#define REG_1180_CKGEN00_V004_REG_CKG_S_SPDIF_TX_MUX_1180 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1184_CKGEN00_V004 (CKGEN00_V004 + 0x1184)
	#define REG_1184_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TX_2_FIFO_256FS_1184 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1184_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TX_2_FIFO_256FS_1184 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1184_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TX_2_FIFO_256FS_1184 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1188_CKGEN00_V004 (CKGEN00_V004 + 0x1188)
	#define REG_1188_CKGEN00_V004_REG_CKG_G_EARC_AUDIO_EARC_DMACRO_1188 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1188_CKGEN00_V004_REG_CKG_I_EARC_AUDIO_EARC_DMACRO_1188 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1188_CKGEN00_V004_REG_CKG_S_EARC_AUDIO_EARC_DMACRO_1188 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1190_CKGEN00_V004 (CKGEN00_V004 + 0x1190)
	#define REG_1190_CKGEN00_V004_REG_CKG_G_AUSDM_3M_CK_1190 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1190_CKGEN00_V004_REG_CKG_I_AUSDM_3M_CK_1190 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1194_CKGEN00_V004 (CKGEN00_V004 + 0x1194)
	#define REG_1194_CKGEN00_V004_REG_CKG_S_CH10_256FSI_MUX_1194 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_1198_CKGEN00_V004 (CKGEN00_V004 + 0x1198)
	#define REG_1198_CKGEN00_V004_REG_CKG_S_CH_M1_256FSI_MUX_1198 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_119C_CKGEN00_V004 (CKGEN00_V004 + 0x119C)
	#define REG_119C_CKGEN00_V004_REG_CKG_S_CH_M2_256FSI_MUX_119C Fld(5,0,AC_MSKB0)//[4:0]
#define REG_11A0_CKGEN00_V004 (CKGEN00_V004 + 0x11A0)
	#define REG_11A0_CKGEN00_V004_REG_CKG_S_CH_M3_256FSI_MUX_11A0 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_11A4_CKGEN00_V004 (CKGEN00_V004 + 0x11A4)
	#define REG_11A4_CKGEN00_V004_REG_CKG_S_CH_M4_256FSI_MUX_11A4 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_11A8_CKGEN00_V004 (CKGEN00_V004 + 0x11A8)
	#define REG_11A8_CKGEN00_V004_REG_CKG_S_CH_M5_256FSI_MUX_11A8 Fld(5,0,AC_MSKB0)//[4:0]
#define REG_11AC_CKGEN00_V004 (CKGEN00_V004 + 0x11AC)
	#define REG_11AC_CKGEN00_V004_REG_CKG_S_CH_M6_256FSI_MUX_11AC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11B0_CKGEN00_V004 (CKGEN00_V004 + 0x11B0)
	#define REG_11B0_CKGEN00_V004_REG_CKG_S_CH_M7_256FSI_MUX_11B0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11B4_CKGEN00_V004 (CKGEN00_V004 + 0x11B4)
	#define REG_11B4_CKGEN00_V004_REG_CKG_S_CH_M8_256FSI_MUX_11B4 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11B8_CKGEN00_V004 (CKGEN00_V004 + 0x11B8)
	#define REG_11B8_CKGEN00_V004_REG_CKG_S_CH_M9_256FSI_MUX_11B8 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11BC_CKGEN00_V004 (CKGEN00_V004 + 0x11BC)
	#define REG_11BC_CKGEN00_V004_REG_CKG_S_CH_M10_256FSI_MUX_11BC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11C0_CKGEN00_V004 (CKGEN00_V004 + 0x11C0)
	#define REG_11C0_CKGEN00_V004_REG_CKG_S_CH_M11_256FSI_MUX_11C0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11C4_CKGEN00_V004 (CKGEN00_V004 + 0x11C4)
	#define REG_11C4_CKGEN00_V004_REG_CKG_S_CH_M12_256FSI_MUX_11C4 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11C8_CKGEN00_V004 (CKGEN00_V004 + 0x11C8)
	#define REG_11C8_CKGEN00_V004_REG_CKG_S_CH_M13_256FSI_MUX_11C8 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11CC_CKGEN00_V004 (CKGEN00_V004 + 0x11CC)
	#define REG_11CC_CKGEN00_V004_REG_CKG_S_CH_M14_256FSI_MUX_11CC Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11D0_CKGEN00_V004 (CKGEN00_V004 + 0x11D0)
	#define REG_11D0_CKGEN00_V004_REG_CKG_S_CH_M15_256FSI_MUX_11D0 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11D4_CKGEN00_V004 (CKGEN00_V004 + 0x11D4)
	#define REG_11D4_CKGEN00_V004_REG_CKG_S_CH_M16_256FSI_MUX_11D4 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_11D8_CKGEN00_V004 (CKGEN00_V004 + 0x11D8)
	#define REG_11D8_CKGEN00_V004_REG_CKG_G_DAP_TCK_VIVALDI9_11D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11D8_CKGEN00_V004_REG_CKG_I_DAP_TCK_VIVALDI9_11D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_11DC_CKGEN00_V004 (CKGEN00_V004 + 0x11DC)
	#define REG_11DC_CKGEN00_V004_REG_CKG_G_DAP_VIVALDI9_11DC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_11DC_CKGEN00_V004_REG_CKG_I_DAP_VIVALDI9_11DC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_11E0_CKGEN00_V004 (CKGEN00_V004 + 0x11E0)
	#define REG_11E0_CKGEN00_V004_REG_CKG_S_DEC1_SYNTH_HDMI2_CTSN_DIV_MUX_11E0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11E4_CKGEN00_V004 (CKGEN00_V004 + 0x11E4)
	#define REG_11E4_CKGEN00_V004_REG_CKG_S_DEC1_SYNTH_SPDIF_CDR_DIV_MUX_11E4 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11E8_CKGEN00_V004 (CKGEN00_V004 + 0x11E8)
	#define REG_11E8_CKGEN00_V004_REG_CKG_S_DEC2_SYNTH_HDMI2_CTSN_DIV_MUX_11E8 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11EC_CKGEN00_V004 (CKGEN00_V004 + 0x11EC)
	#define REG_11EC_CKGEN00_V004_REG_CKG_S_DEC2_SYNTH_SPDIF_CDR_DIV_MUX_11EC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11F0_CKGEN00_V004 (CKGEN00_V004 + 0x11F0)
	#define REG_11F0_CKGEN00_V004_REG_CKG_S_DEC3_SYNTH_HDMI2_CTSN_DIV_MUX_11F0 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11F4_CKGEN00_V004 (CKGEN00_V004 + 0x11F4)
	#define REG_11F4_CKGEN00_V004_REG_CKG_S_DEC3_SYNTH_SPDIF_CDR_DIV_MUX_11F4 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11F8_CKGEN00_V004 (CKGEN00_V004 + 0x11F8)
	#define REG_11F8_CKGEN00_V004_REG_CKG_S_DEC4_SYNTH_HDMI2_CTSN_DIV_MUX_11F8 Fld(3,0,AC_MSKB0)//[2:0]
#define REG_11FC_CKGEN00_V004 (CKGEN00_V004 + 0x11FC)
	#define REG_11FC_CKGEN00_V004_REG_CKG_S_DEC4_SYNTH_SPDIF_CDR_DIV_MUX_11FC Fld(3,0,AC_MSKB0)//[2:0]
#define REG_1208_CKGEN00_V004 (CKGEN00_V004 + 0x1208)
	#define REG_1208_CKGEN00_V004_REG_CKG_G_VIVA_CH10_256FSI_1208 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1208_CKGEN00_V004_REG_CKG_I_VIVA_CH10_256FSI_1208 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1208_CKGEN00_V004_REG_CKG_S_VIVA_CH10_256FSI_1208 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_120C_CKGEN00_V004 (CKGEN00_V004 + 0x120C)
	#define REG_120C_CKGEN00_V004_REG_CKG_G_VIVA_CH_M1_256FSI_120C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_120C_CKGEN00_V004_REG_CKG_I_VIVA_CH_M1_256FSI_120C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_120C_CKGEN00_V004_REG_CKG_S_VIVA_CH_M1_256FSI_120C Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1210_CKGEN00_V004 (CKGEN00_V004 + 0x1210)
	#define REG_1210_CKGEN00_V004_REG_CKG_G_VIVA_CH_M2_256FSI_1210 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1210_CKGEN00_V004_REG_CKG_I_VIVA_CH_M2_256FSI_1210 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1210_CKGEN00_V004_REG_CKG_S_VIVA_CH_M2_256FSI_1210 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1214_CKGEN00_V004 (CKGEN00_V004 + 0x1214)
	#define REG_1214_CKGEN00_V004_REG_CKG_G_VIVA_CH_M3_256FSI_1214 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1214_CKGEN00_V004_REG_CKG_I_VIVA_CH_M3_256FSI_1214 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1214_CKGEN00_V004_REG_CKG_S_VIVA_CH_M3_256FSI_1214 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1218_CKGEN00_V004 (CKGEN00_V004 + 0x1218)
	#define REG_1218_CKGEN00_V004_REG_CKG_G_VIVA_CH_M4_256FSI_1218 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1218_CKGEN00_V004_REG_CKG_I_VIVA_CH_M4_256FSI_1218 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1218_CKGEN00_V004_REG_CKG_S_VIVA_CH_M4_256FSI_1218 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_121C_CKGEN00_V004 (CKGEN00_V004 + 0x121C)
	#define REG_121C_CKGEN00_V004_REG_CKG_G_VIVA_CH_M5_256FSI_121C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_121C_CKGEN00_V004_REG_CKG_I_VIVA_CH_M5_256FSI_121C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_121C_CKGEN00_V004_REG_CKG_S_VIVA_CH_M5_256FSI_121C Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1220_CKGEN00_V004 (CKGEN00_V004 + 0x1220)
	#define REG_1220_CKGEN00_V004_REG_CKG_G_VIVA_CH_M6_256FSI_1220 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1220_CKGEN00_V004_REG_CKG_I_VIVA_CH_M6_256FSI_1220 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1220_CKGEN00_V004_REG_CKG_S_VIVA_CH_M6_256FSI_1220 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1224_CKGEN00_V004 (CKGEN00_V004 + 0x1224)
	#define REG_1224_CKGEN00_V004_REG_CKG_G_VIVA_CH_M7_256FSI_1224 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1224_CKGEN00_V004_REG_CKG_I_VIVA_CH_M7_256FSI_1224 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1224_CKGEN00_V004_REG_CKG_S_VIVA_CH_M7_256FSI_1224 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1228_CKGEN00_V004 (CKGEN00_V004 + 0x1228)
	#define REG_1228_CKGEN00_V004_REG_CKG_G_VIVA_CH_M8_256FSI_1228 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1228_CKGEN00_V004_REG_CKG_I_VIVA_CH_M8_256FSI_1228 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1228_CKGEN00_V004_REG_CKG_S_VIVA_CH_M8_256FSI_1228 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_122C_CKGEN00_V004 (CKGEN00_V004 + 0x122C)
	#define REG_122C_CKGEN00_V004_REG_CKG_G_VIVA_CH_M9_256FSI_122C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_122C_CKGEN00_V004_REG_CKG_I_VIVA_CH_M9_256FSI_122C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_122C_CKGEN00_V004_REG_CKG_S_VIVA_CH_M9_256FSI_122C Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1230_CKGEN00_V004 (CKGEN00_V004 + 0x1230)
	#define REG_1230_CKGEN00_V004_REG_CKG_G_VIVA_CH_M10_256FSI_1230 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1230_CKGEN00_V004_REG_CKG_I_VIVA_CH_M10_256FSI_1230 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1230_CKGEN00_V004_REG_CKG_S_VIVA_CH_M10_256FSI_1230 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1234_CKGEN00_V004 (CKGEN00_V004 + 0x1234)
	#define REG_1234_CKGEN00_V004_REG_CKG_G_VIVA_CH_M11_256FSI_1234 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1234_CKGEN00_V004_REG_CKG_I_VIVA_CH_M11_256FSI_1234 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1234_CKGEN00_V004_REG_CKG_S_VIVA_CH_M11_256FSI_1234 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1238_CKGEN00_V004 (CKGEN00_V004 + 0x1238)
	#define REG_1238_CKGEN00_V004_REG_CKG_G_VIVA_CH_M12_256FSI_1238 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1238_CKGEN00_V004_REG_CKG_I_VIVA_CH_M12_256FSI_1238 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1238_CKGEN00_V004_REG_CKG_S_VIVA_CH_M12_256FSI_1238 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_123C_CKGEN00_V004 (CKGEN00_V004 + 0x123C)
	#define REG_123C_CKGEN00_V004_REG_CKG_G_VIVA_CH_M13_256FSI_123C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_123C_CKGEN00_V004_REG_CKG_I_VIVA_CH_M13_256FSI_123C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_123C_CKGEN00_V004_REG_CKG_S_VIVA_CH_M13_256FSI_123C Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1240_CKGEN00_V004 (CKGEN00_V004 + 0x1240)
	#define REG_1240_CKGEN00_V004_REG_CKG_G_VIVA_CH_M14_256FSI_1240 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1240_CKGEN00_V004_REG_CKG_I_VIVA_CH_M14_256FSI_1240 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1240_CKGEN00_V004_REG_CKG_S_VIVA_CH_M14_256FSI_1240 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1244_CKGEN00_V004 (CKGEN00_V004 + 0x1244)
	#define REG_1244_CKGEN00_V004_REG_CKG_G_VIVA_CH_M15_256FSI_1244 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1244_CKGEN00_V004_REG_CKG_I_VIVA_CH_M15_256FSI_1244 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1244_CKGEN00_V004_REG_CKG_S_VIVA_CH_M15_256FSI_1244 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1248_CKGEN00_V004 (CKGEN00_V004 + 0x1248)
	#define REG_1248_CKGEN00_V004_REG_CKG_G_VIVA_CH_M16_256FSI_1248 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1248_CKGEN00_V004_REG_CKG_I_VIVA_CH_M16_256FSI_1248 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1248_CKGEN00_V004_REG_CKG_S_VIVA_CH_M16_256FSI_1248 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_124C_CKGEN00_V004 (CKGEN00_V004 + 0x124C)
	#define REG_124C_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TDM_1X16TX32B_BCLK_124C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_124C_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TDM_1X16TX32B_BCLK_124C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_124C_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_124C Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1250_CKGEN00_V004 (CKGEN00_V004 + 0x1250)
	#define REG_1250_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_1250 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1250_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_1250 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1250_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_BCLK_TO_PAD_1250 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1254_CKGEN00_V004 (CKGEN00_V004 + 0x1254)
	#define REG_1254_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TDM_1X16TX32B_FIFO_1254 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1254_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TDM_1X16TX32B_FIFO_1254 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1254_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TDM_1X16TX32B_FIFO_1254 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1258_CKGEN00_V004 (CKGEN00_V004 + 0x1258)
	#define REG_1258_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TDM_6X16TX32B_BCLK_1258 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1258_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TDM_6X16TX32B_BCLK_1258 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1258_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_1258 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_125C_CKGEN00_V004 (CKGEN00_V004 + 0x125C)
	#define REG_125C_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_125C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_125C_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_125C Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_125C_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_BCLK_TO_PAD_125C Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1260_CKGEN00_V004 (CKGEN00_V004 + 0x1260)
	#define REG_1260_CKGEN00_V004_REG_CKG_G_VIVA_I2S_TDM_6X16TX32B_FIFO_1260 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1260_CKGEN00_V004_REG_CKG_I_VIVA_I2S_TDM_6X16TX32B_FIFO_1260 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1260_CKGEN00_V004_REG_CKG_S_VIVA_I2S_TDM_6X16TX32B_FIFO_1260 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1264_CKGEN00_V004 (CKGEN00_V004 + 0x1264)
	#define REG_1264_CKGEN00_V004_REG_CKG_G_VIVA_SRC_MAC_BSPLINE_1264 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1264_CKGEN00_V004_REG_CKG_I_VIVA_SRC_MAC_BSPLINE_1264 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1264_CKGEN00_V004_REG_CKG_S_VIVA_SRC_MAC_BSPLINE_1264 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_1268_CKGEN00_V004 (CKGEN00_V004 + 0x1268)
	#define REG_1268_CKGEN00_V004_REG_CKG_G_DISP_MFDEC_1268 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1268_CKGEN00_V004_REG_CKG_I_DISP_MFDEC_1268 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1268_CKGEN00_V004_REG_CKG_S_DISP_MFDEC_1268 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1268_CKGEN00_V004_REG_CKG_G_DISP_MFDEC_GPU_PAR_GP_1268 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1268_CKGEN00_V004_REG_CKG_I_DISP_MFDEC_GPU_PAR_GP_1268 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1268_CKGEN00_V004_REG_CKG_S_DISP_MFDEC_GPU_PAR_GP_1268 Fld(2,10,AC_MSKB1)//[11:10]
	#define REG_1268_CKGEN00_V004_REG_CKG_G_DISP_MFDEC_GPU_1268 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1268_CKGEN00_V004_REG_CKG_I_DISP_MFDEC_GPU_1268 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_1270_CKGEN00_V004 (CKGEN00_V004 + 0x1270)
	#define REG_1270_CKGEN00_V004_REG_CKG_G_GPD_1270 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1270_CKGEN00_V004_REG_CKG_I_GPD_1270 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1270_CKGEN00_V004_REG_CKG_S_GPD_1270 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1270_CKGEN00_V004_REG_CKG_G_GPD_MHEG5_1270 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1270_CKGEN00_V004_REG_CKG_I_GPD_MHEG5_1270 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1278_CKGEN00_V004 (CKGEN00_V004 + 0x1278)
	#define REG_1278_CKGEN00_V004_REG_CKG_G_NJPD_1278 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1278_CKGEN00_V004_REG_CKG_I_NJPD_1278 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1278_CKGEN00_V004_REG_CKG_S_NJPD_1278 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1278_CKGEN00_V004_REG_CKG_G_NJPD_TSP_1278 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1278_CKGEN00_V004_REG_CKG_I_NJPD_TSP_1278 Fld(1,9,AC_MSKB1)//[9:9]
#define REG_1288_CKGEN00_V004 (CKGEN00_V004 + 0x1288)
	#define REG_1288_CKGEN00_V004_REG_CKG_G_VDEC_LAE_SLOW_1288 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1288_CKGEN00_V004_REG_CKG_I_VDEC_LAE_SLOW_1288 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1288_CKGEN00_V004_REG_CKG_S_VDEC_LAE_SLOW_1288 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1288_CKGEN00_V004_REG_CKG_G_VDEC_BUS_VDEC_CORE0_1288 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1288_CKGEN00_V004_REG_CKG_I_VDEC_BUS_VDEC_CORE0_1288 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1290_CKGEN00_V004 (CKGEN00_V004 + 0x1290)
	#define REG_1290_CKGEN00_V004_REG_CKG_G_VDEC_SYS_1290 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1290_CKGEN00_V004_REG_CKG_I_VDEC_SYS_1290 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1290_CKGEN00_V004_REG_CKG_S_VDEC_SYS_1290 Fld(2,2,AC_MSKB0)//[3:2]
	#define REG_1290_CKGEN00_V004_REG_CKG_G_VDEC_SYS_VDEC_CORE0_1290 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1290_CKGEN00_V004_REG_CKG_I_VDEC_SYS_VDEC_CORE0_1290 Fld(1,11,AC_MSKB1)//[11:11]
#define REG_1298_CKGEN00_V004 (CKGEN00_V004 + 0x1298)
	#define REG_1298_CKGEN00_V004_REG_CKG_G_VDEC_SYS_SLOW_1298 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1298_CKGEN00_V004_REG_CKG_I_VDEC_SYS_SLOW_1298 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1298_CKGEN00_V004_REG_CKG_S_VDEC_SYS_SLOW_1298 Fld(2,2,AC_MSKB0)//[3:2]
#define REG_12B8_CKGEN00_V004 (CKGEN00_V004 + 0x12B8)
	#define REG_12B8_CKGEN00_V004_REG_CKG_G_XTAL_24M_VDEC_CORE0_12B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12B8_CKGEN00_V004_REG_CKG_I_XTAL_24M_VDEC_CORE0_12B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_12D0_CKGEN00_V004 (CKGEN00_V004 + 0x12D0)
	#define REG_12D0_CKGEN00_V004_REG_CKG_G_DAP_AURV55_12D0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12D0_CKGEN00_V004_REG_CKG_I_DAP_AURV55_12D0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_12D8_CKGEN00_V004 (CKGEN00_V004 + 0x12D8)
	#define REG_12D8_CKGEN00_V004_REG_CKG_G_TCK_AUDAP_12D8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12D8_CKGEN00_V004_REG_CKG_I_TCK_AUDAP_12D8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_12E0_CKGEN00_V004 (CKGEN00_V004 + 0x12E0)
	#define REG_12E0_CKGEN00_V004_REG_CKG_G_TCK_AUDEC_12E0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12E0_CKGEN00_V004_REG_CKG_I_TCK_AUDEC_12E0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_12E8_CKGEN00_V004 (CKGEN00_V004 + 0x12E8)
	#define REG_12E8_CKGEN00_V004_REG_CKG_G_TCK_AUSND_12E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12E8_CKGEN00_V004_REG_CKG_I_TCK_AUSND_12E8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_12F0_CKGEN00_V004 (CKGEN00_V004 + 0x12F0)
	#define REG_12F0_CKGEN00_V004_REG_CKG_G_WB_AURV55_12F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_12F0_CKGEN00_V004_REG_CKG_I_WB_AURV55_12F0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1300_CKGEN00_V004 (CKGEN00_V004 + 0x1300)
	#define REG_1300_CKGEN00_V004_REG_CKG_G_ZDEC_LZD_TSP_1300 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1300_CKGEN00_V004_REG_CKG_I_ZDEC_LZD_TSP_1300 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1300_CKGEN00_V004_REG_CKG_S_ZDEC_LZD_TSP_1300 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1300_CKGEN00_V004_REG_CKG_G_ZDEC_VLD_TSP_1300 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1300_CKGEN00_V004_REG_CKG_I_ZDEC_VLD_TSP_1300 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1300_CKGEN00_V004_REG_CKG_S_ZDEC_VLD_TSP_1300 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_1340_CKGEN00_V004 (CKGEN00_V004 + 0x1340)
	#define REG_1340_CKGEN00_V004_REG_CKG_G_BIST_SCBE_1340 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1340_CKGEN00_V004_REG_CKG_I_BIST_SCBE_1340 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1340_CKGEN00_V004_REG_CKG_S_BIST_SCBE_1340 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1340_CKGEN00_V004_REG_CKG_G_BIST_SCFE_1340 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1340_CKGEN00_V004_REG_CKG_I_BIST_SCFE_1340 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1340_CKGEN00_V004_REG_CKG_S_BIST_SCFE_1340 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1348_CKGEN00_V004 (CKGEN00_V004 + 0x1348)
	#define REG_1348_CKGEN00_V004_REG_CKG_G_BIST_SCTC_1348 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1348_CKGEN00_V004_REG_CKG_I_BIST_SCTC_1348 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1348_CKGEN00_V004_REG_CKG_S_BIST_SCTC_1348 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1348_CKGEN00_V004_REG_CKG_G_BIST_FRC_1348 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1348_CKGEN00_V004_REG_CKG_I_BIST_FRC_1348 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1348_CKGEN00_V004_REG_CKG_S_BIST_FRC_1348 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1350_CKGEN00_V004 (CKGEN00_V004 + 0x1350)
	#define REG_1350_CKGEN00_V004_REG_CKG_G_BIST_DEMOD0_1350 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1350_CKGEN00_V004_REG_CKG_I_BIST_DEMOD0_1350 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1350_CKGEN00_V004_REG_CKG_S_BIST_DEMOD0_1350 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1350_CKGEN00_V004_REG_CKG_G_BIST_DEMOD1_1350 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1350_CKGEN00_V004_REG_CKG_I_BIST_DEMOD1_1350 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1350_CKGEN00_V004_REG_CKG_S_BIST_DEMOD1_1350 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1358_CKGEN00_V004 (CKGEN00_V004 + 0x1358)
	#define REG_1358_CKGEN00_V004_REG_CKG_G_BIST_MOD_1358 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1358_CKGEN00_V004_REG_CKG_I_BIST_MOD_1358 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1358_CKGEN00_V004_REG_CKG_S_BIST_MOD_1358 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1358_CKGEN00_V004_REG_CKG_G_BIST_GPU_PAR_GP_1358 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1358_CKGEN00_V004_REG_CKG_I_BIST_GPU_PAR_GP_1358 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1358_CKGEN00_V004_REG_CKG_S_BIST_GPU_PAR_GP_1358 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1360_CKGEN00_V004 (CKGEN00_V004 + 0x1360)
	#define REG_1360_CKGEN00_V004_REG_CKG_G_BIST_DRAMC0_1360 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1360_CKGEN00_V004_REG_CKG_I_BIST_DRAMC0_1360 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1360_CKGEN00_V004_REG_CKG_S_BIST_DRAMC0_1360 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1360_CKGEN00_V004_REG_CKG_G_BIST_DRAMC1_1360 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1360_CKGEN00_V004_REG_CKG_I_BIST_DRAMC1_1360 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1360_CKGEN00_V004_REG_CKG_S_BIST_DRAMC1_1360 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1368_CKGEN00_V004 (CKGEN00_V004 + 0x1368)
	#define REG_1368_CKGEN00_V004_REG_CKG_G_BIST_IP_1368 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1368_CKGEN00_V004_REG_CKG_I_BIST_IP_1368 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1368_CKGEN00_V004_REG_CKG_S_BIST_IP_1368 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1368_CKGEN00_V004_REG_CKG_G_BIST_HDMIRX_1368 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1368_CKGEN00_V004_REG_CKG_I_BIST_HDMIRX_1368 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1368_CKGEN00_V004_REG_CKG_S_BIST_HDMIRX_1368 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1370_CKGEN00_V004 (CKGEN00_V004 + 0x1370)
	#define REG_1370_CKGEN00_V004_REG_CKG_G_BIST_MCUSYS_1370 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1370_CKGEN00_V004_REG_CKG_I_BIST_MCUSYS_1370 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1370_CKGEN00_V004_REG_CKG_S_BIST_MCUSYS_1370 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1370_CKGEN00_V004_REG_CKG_G_BIST_MHEG5_1370 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1370_CKGEN00_V004_REG_CKG_I_BIST_MHEG5_1370 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1370_CKGEN00_V004_REG_CKG_S_BIST_MHEG5_1370 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1378_CKGEN00_V004 (CKGEN00_V004 + 0x1378)
	#define REG_1378_CKGEN00_V004_REG_CKG_G_BIST_TSP_1378 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1378_CKGEN00_V004_REG_CKG_I_BIST_TSP_1378 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1378_CKGEN00_V004_REG_CKG_S_BIST_TSP_1378 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1378_CKGEN00_V004_REG_CKG_G_BIST_VIVA_1378 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1378_CKGEN00_V004_REG_CKG_I_BIST_VIVA_1378 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1378_CKGEN00_V004_REG_CKG_S_BIST_VIVA_1378 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1380_CKGEN00_V004 (CKGEN00_V004 + 0x1380)
	#define REG_1380_CKGEN00_V004_REG_CKG_G_BIST_VDEC_CORE0_1380 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1380_CKGEN00_V004_REG_CKG_I_BIST_VDEC_CORE0_1380 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1380_CKGEN00_V004_REG_CKG_S_BIST_VDEC_CORE0_1380 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1380_CKGEN00_V004_REG_CKG_G_BIST_VDEC_CORE0_MERGE_1380 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1380_CKGEN00_V004_REG_CKG_I_BIST_VDEC_CORE0_MERGE_1380 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1380_CKGEN00_V004_REG_CKG_S_BIST_VDEC_CORE0_MERGE_1380 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1388_CKGEN00_V004 (CKGEN00_V004 + 0x1388)
	#define REG_1388_CKGEN00_V004_REG_CKG_G_BIST_TOP_1388 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1388_CKGEN00_V004_REG_CKG_I_BIST_TOP_1388 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1388_CKGEN00_V004_REG_CKG_S_BIST_TOP_1388 Fld(3,2,AC_MSKB0)//[4:2]
	#define REG_1388_CKGEN00_V004_REG_CKG_G_BIST_AURV55_1388 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1388_CKGEN00_V004_REG_CKG_I_BIST_AURV55_1388 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1388_CKGEN00_V004_REG_CKG_S_BIST_AURV55_1388 Fld(3,10,AC_MSKB1)//[12:10]
#define REG_1390_CKGEN00_V004 (CKGEN00_V004 + 0x1390)
	#define REG_1390_CKGEN00_V004_REG_CKG_G_BIST2_AURV55_1390 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1390_CKGEN00_V004_REG_CKG_I_BIST2_AURV55_1390 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1390_CKGEN00_V004_REG_CKG_S_BIST2_AURV55_1390 Fld(3,2,AC_MSKB0)//[4:2]
#define REG_1400_CKGEN00_V004 (CKGEN00_V004 + 0x1400)
	#define REG_1400_CKGEN00_V004_REG_SW_EN_CALC2CALC_MCUSYS_1400 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1444_CKGEN00_V004 (CKGEN00_V004 + 0x1444)
	#define REG_1444_CKGEN00_V004_REG_SW_EN_GPU2GPU_PAR_GP_1444 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1444_CKGEN00_V004_REG_SW_EN_GPU_DFS2GPU_PAR_GP_1444 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_144C_CKGEN00_V004 (CKGEN00_V004 + 0x144C)
	#define REG_144C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MET_144C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1450_CKGEN00_V004 (CKGEN00_V004 + 0x1450)
	#define REG_1450_CKGEN00_V004_REG_SW_EN_XTAL_24M2SYSCOUNT_1450 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1454_CKGEN00_V004 (CKGEN00_V004 + 0x1454)
	#define REG_1454_CKGEN00_V004_REG_SW_EN_MCU_NONPM2SSUSB_U2_PHY_TOP_1454 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1454_CKGEN00_V004_REG_SW_EN_RIU_NONPM2SSUSB_U2_PHY_TOP_1454 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1454_CKGEN00_V004_REG_SW_EN_XTAL_24M_NONPM2SSUSB_U2_PHY_TOP_1454 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1458_CKGEN00_V004 (CKGEN00_V004 + 0x1458)
	#define REG_1458_CKGEN00_V004_REG_SW_EN_MCU_NONPM2SSUSB_U3_PHY_TOP_1458 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1458_CKGEN00_V004_REG_SW_EN_MCU_NONPM2SSUSB_DIG_PHY_TOP_1458 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1458_CKGEN00_V004_REG_SW_EN_XTAL_12M2SSUSB_DIG_PHY_TOP_1458 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1458_CKGEN00_V004_REG_SW_EN_XTAL_12M2SSUSB_U2_PHY_TOP_1458 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_145C_CKGEN00_V004 (CKGEN00_V004 + 0x145C)
	#define REG_145C_CKGEN00_V004_REG_SW_EN_DRAMC1_CGCLK_FAST_CHB2DRAMC1_145C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1468_CKGEN00_V004 (CKGEN00_V004 + 0x1468)
	#define REG_1468_CKGEN00_V004_REG_SW_EN_MCU_NONPM2DRAMC0_1468 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_146C_CKGEN00_V004 (CKGEN00_V004 + 0x146C)
	#define REG_146C_CKGEN00_V004_REG_SW_EN_DRAMC0_CGCLK_FAST_CHB2DRAMC0_146C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1470_CKGEN00_V004 (CKGEN00_V004 + 0x1470)
	#define REG_1470_CKGEN00_V004_REG_SW_EN_MCU_NONPM2DRAMC1_1470 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1474_CKGEN00_V004 (CKGEN00_V004 + 0x1474)
	#define REG_1474_CKGEN00_V004_REG_SW_EN_DRAMC0_CGCLK_FAST_CHA2DRAMC0_1474 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1478_CKGEN00_V004 (CKGEN00_V004 + 0x1478)
	#define REG_1478_CKGEN00_V004_REG_SW_EN_DRAMC1_CGCLK_FAST_CHA2DRAMC1_1478 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_147C_CKGEN00_V004 (CKGEN00_V004 + 0x147C)
	#define REG_147C_CKGEN00_V004_REG_SW_EN_MPLL_208M_CHA2DRAMC0_147C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1480_CKGEN00_V004 (CKGEN00_V004 + 0x1480)
	#define REG_1480_CKGEN00_V004_REG_SW_EN_MPLL_208M_CHA2DRAMC1_1480 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1484_CKGEN00_V004 (CKGEN00_V004 + 0x1484)
	#define REG_1484_CKGEN00_V004_REG_SW_EN_MPLL_208M_CHB2DRAMC0_1484 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1488_CKGEN00_V004 (CKGEN00_V004 + 0x1488)
	#define REG_1488_CKGEN00_V004_REG_SW_EN_MPLL_208M_CHB2DRAMC1_1488 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_148C_CKGEN00_V004 (CKGEN00_V004 + 0x148C)
	#define REG_148C_CKGEN00_V004_REG_SW_EN_XTAL_24M2DRAMC0_148C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1490_CKGEN00_V004 (CKGEN00_V004 + 0x1490)
	#define REG_1490_CKGEN00_V004_REG_SW_EN_XTAL_24M2DRAMC1_1490 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1498_CKGEN00_V004 (CKGEN00_V004 + 0x1498)
	#define REG_1498_CKGEN00_V004_REG_SW_EN_EMI0_DEB2IP_WRAP_1498 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_149C_CKGEN00_V004 (CKGEN00_V004 + 0x149C)
	#define REG_149C_CKGEN00_V004_REG_SW_EN_EMI02IP_WRAP_149C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B0_CKGEN00_V004 (CKGEN00_V004 + 0x14B0)
	#define REG_14B0_CKGEN00_V004_REG_SW_EN_IP_WRAP2IP_WRAP_14B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B4_CKGEN00_V004 (CKGEN00_V004 + 0x14B4)
	#define REG_14B4_CKGEN00_V004_REG_SW_EN_XTAL_12M2IP_WRAP_14B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14B8_CKGEN00_V004 (CKGEN00_V004 + 0x14B8)
	#define REG_14B8_CKGEN00_V004_REG_SW_EN_XTAL_24M2IP_WRAP_14B8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14B8_CKGEN00_V004_REG_SW_EN_RIU_NONPM2IP_WRAP_14B8 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_14BC_CKGEN00_V004 (CKGEN00_V004 + 0x14BC)
	#define REG_14BC_CKGEN00_V004_REG_SW_EN_DRAMC0_PLL54M_108M2DRAMC0_14BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C0_CKGEN00_V004 (CKGEN00_V004 + 0x14C0)
	#define REG_14C0_CKGEN00_V004_REG_SW_EN_DRAMC1_PLL54M_108M2DRAMC1_14C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C4_CKGEN00_V004 (CKGEN00_V004 + 0x14C4)
	#define REG_14C4_CKGEN00_V004_REG_SW_EN_MPLL_208M_MD322DRAMC0_14C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14C8_CKGEN00_V004 (CKGEN00_V004 + 0x14C8)
	#define REG_14C8_CKGEN00_V004_REG_SW_EN_MPLL_208M_MD322DRAMC1_14C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14CC_CKGEN00_V004 (CKGEN00_V004 + 0x14CC)
	#define REG_14CC_CKGEN00_V004_REG_SW_EN_MPLL_432M2DRAMC0_14CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D0_CKGEN00_V004 (CKGEN00_V004 + 0x14D0)
	#define REG_14D0_CKGEN00_V004_REG_SW_EN_MPLL_432M2DRAMC1_14D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D4_CKGEN00_V004 (CKGEN00_V004 + 0x14D4)
	#define REG_14D4_CKGEN00_V004_REG_SW_EN_RC2DRAMC0_14D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14D8_CKGEN00_V004 (CKGEN00_V004 + 0x14D8)
	#define REG_14D8_CKGEN00_V004_REG_SW_EN_RC2DRAMC1_14D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14E4_CKGEN00_V004 (CKGEN00_V004 + 0x14E4)
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2CMDQ_14E4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2CORE0_14E4 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2SMI_DEMOD0_14E4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2DSCRMB_14E4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2GE_14E4 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2GMAC_14E4 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2GPD_14E4 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_14E4_CKGEN00_V004_REG_SW_EN_SMI2JPD_14E4 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14E8_CKGEN00_V004 (CKGEN00_V004 + 0x14E8)
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MAC_14E8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_BDMA_14E8 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_DEMURA_14E8 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_FUART_14E8 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_M2MCU_14E8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_MIIC0_14E8 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_MIIC1_14E8 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_MIIC2_14E8 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_MIIC3_14E8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MCU_XD2MIU_14E8 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_14E8_CKGEN00_V004_REG_SW_EN_SMI2MHEG5_SMI_14E8 Fld(1,10,AC_MSKB1)//[10:10]
#define REG_14EC_CKGEN00_V004 (CKGEN00_V004 + 0x14EC)
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCIP_14EC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCM_14EC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCMO_14EC Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCNR_14EC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCBE_14EC Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SCTC_14EC Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SMI_14EC Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2SSUSB_14EC Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2TSO_14EC Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2TSO2_14EC Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2TSP_14EC Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_14EC_CKGEN00_V004_REG_SW_EN_SMI2VD_14EC Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14F0_CKGEN00_V004 (CKGEN00_V004 + 0x14F0)
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2VD_PES_PARSER_14F0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2LARB_TSP_14F0 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI_AESDMA2DSCRMB_14F0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI_TSP2TSP_14F0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI_FCIE2FCIE_14F0 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI_UHC2UHC_14F0 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_VIVA_SMI2SMI_14F0 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2DEMOD0_14F0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2DEMOD0_DVBTM_14F0 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2DEMOD0_ISDBT_14F0 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2DEMOD0_DTMB_14F0 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2DEMOD0_ADC_DUMP_14F0 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI0_14F0 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI1_14F0 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_14F0_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI2_14F0 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_14F4_CKGEN00_V004 (CKGEN00_V004 + 0x14F4)
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI3_14F4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI4_14F4 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI5_14F4 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI6_14F4 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI7_14F4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2MCU_MSPI_CILINK_14F4 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2PEXTP_14F4 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2UFS_14F4 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_VIVA_SMI2SMI_BRG_14F4 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCCORE1_14F4 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCCORE2_14F4 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCCORE3_14F4 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI2FRCMISC_14F4 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_14F4_CKGEN00_V004_REG_SW_EN_SMI_SSUSB2SSUSB_14F4 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_14F8_CKGEN00_V004 (CKGEN00_V004 + 0x14F8)
	#define REG_14F8_CKGEN00_V004_REG_SW_EN_SMI2SMI_FRCCORE1_14F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_14FC_CKGEN00_V004 (CKGEN00_V004 + 0x14FC)
	#define REG_14FC_CKGEN00_V004_REG_SW_EN_SMI2AUDEC_14FC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_14FC_CKGEN00_V004_REG_SW_EN_SMI2AUSND_14FC Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_14FC_CKGEN00_V004_REG_SW_EN_SMI2AURV55SMI_14FC Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1504_CKGEN00_V004 (CKGEN00_V004 + 0x1504)
	#define REG_1504_CKGEN00_V004_REG_SW_EN_SMI2FRC_GALS_1504 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1504_CKGEN00_V004_REG_SW_EN_SMI2SCBE_GALS_1504 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1504_CKGEN00_V004_REG_SW_EN_SMI2SCFE_GALS_1504 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1504_CKGEN00_V004_REG_SW_EN_SMI2SCTC_GALS_1504 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1508_CKGEN00_V004 (CKGEN00_V004 + 0x1508)
	#define REG_1508_CKGEN00_V004_REG_SW_EN_SMI2SCFE_EMI_1508 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1508_CKGEN00_V004_REG_SW_EN_SMI2SCFE_SMI_IP_1508 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1508_CKGEN00_V004_REG_SW_EN_SMI2FRC_EMI_1508 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1508_CKGEN00_V004_REG_SW_EN_SMI2FRC_R2_1508 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1524_CKGEN00_V004 (CKGEN00_V004 + 0x1524)
	#define REG_1524_CKGEN00_V004_REG_SW_EN_IMI2SHARE_SRAM_IMI_1524 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1524_CKGEN00_V004_REG_SW_EN_IMI2UFS_1524 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1524_CKGEN00_V004_REG_SW_EN_IMI2TSP_1524 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_153C_CKGEN00_V004 (CKGEN00_V004 + 0x153C)
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2CODEC_RIU_BRIDGE_TOP_153C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2DIG_DFT_DUMMY_153C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_BDMA_153C Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_DEMURA_153C Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_FUART_153C Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_M2MCU_153C Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_M2RIU_153C Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MCUIF_153C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MIIC0_153C Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MIIC1_153C Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MIIC2_153C Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MIIC3_153C Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_XD2MIU_153C Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2PAD_TOP_153C Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_153C_CKGEN00_V004_REG_SW_EN_XTAL_12M2PREARB2PMRIU_153C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_1540_CKGEN00_V004 (CKGEN00_V004 + 0x1540)
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2RIU_BRIDGE_TOP_1540 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2SECURE_TOP_NONPM_1540 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2TEST_CLK_CALCULATE_1540 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2TEST_CTRL_1540 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2VD_1540 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI0_1540 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI1_1540 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI2_1540 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI3_1540 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI4_1540 Fld(1,9,AC_MSKB1)//[9:9]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI5_1540 Fld(1,10,AC_MSKB1)//[10:10]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI6_1540 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI7_1540 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1540_CKGEN00_V004_REG_SW_EN_XTAL_12M2MCU_MSPI_CILINK_1540 Fld(1,13,AC_MSKB1)//[13:13]
#define REG_1558_CKGEN00_V004 (CKGEN00_V004 + 0x1558)
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2DMD_RST_CTRL_1558 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2DSCRMB_1558 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2GMAC_1558 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2PEXTP_1558 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2SSUSB_1558 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2TOP_1558 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_1558_CKGEN00_V004_REG_SW_EN_XTAL_24M2USB20_1558 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1574_CKGEN00_V004 (CKGEN00_V004 + 0x1574)
	#define REG_1574_CKGEN00_V004_REG_SW_EN_ICLAMP2DMD_ANA_1574 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1578_CKGEN00_V004 (CKGEN00_V004 + 0x1578)
	#define REG_1578_CKGEN00_V004_REG_SW_EN_ADCD_I_IN_DIV22DMD_ANA_1578 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_157C_CKGEN00_V004 (CKGEN00_V004 + 0x157C)
	#define REG_157C_CKGEN00_V004_REG_SW_EN_DVBTC_ADC_I_P2DMD_ANA_157C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1580_CKGEN00_V004 (CKGEN00_V004 + 0x1580)
	#define REG_1580_CKGEN00_V004_REG_SW_EN_DVBTC_ADC_Q_P2DMD_ANA_1580 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1584_CKGEN00_V004 (CKGEN00_V004 + 0x1584)
	#define REG_1584_CKGEN00_V004_REG_SW_EN_ACIFIR2DEMOD0_1584 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1588_CKGEN00_V004 (CKGEN00_V004 + 0x1588)
	#define REG_1588_CKGEN00_V004_REG_SW_EN_ADCD_I_IN2DMD_ANA_1588 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_158C_CKGEN00_V004 (CKGEN00_V004 + 0x158C)
	#define REG_158C_CKGEN00_V004_REG_SW_EN_ADCD_I_OUT2DMD_ANA_158C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1590_CKGEN00_V004 (CKGEN00_V004 + 0x1590)
	#define REG_1590_CKGEN00_V004_REG_SW_EN_ADCD_Q_IN2DMD_ANA_1590 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1594_CKGEN00_V004 (CKGEN00_V004 + 0x1594)
	#define REG_1594_CKGEN00_V004_REG_SW_EN_ADCD_Q_OUT2DMD_ANA_1594 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1598_CKGEN00_V004 (CKGEN00_V004 + 0x1598)
	#define REG_1598_CKGEN00_V004_REG_SW_EN_ADCD2DEMOD0_1598 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_159C_CKGEN00_V004 (CKGEN00_V004 + 0x159C)
	#define REG_159C_CKGEN00_V004_REG_SW_EN_ATSC_ADCD_SYNC2DEMOD0_159C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A0_CKGEN00_V004 (CKGEN00_V004 + 0x15A0)
	#define REG_15A0_CKGEN00_V004_REG_SW_EN_ATSC_CE252DEMOD0_15A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A4_CKGEN00_V004 (CKGEN00_V004 + 0x15A4)
	#define REG_15A4_CKGEN00_V004_REG_SW_EN_ATSC_EQ252DEMOD0_15A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15A8_CKGEN00_V004 (CKGEN00_V004 + 0x15A8)
	#define REG_15A8_CKGEN00_V004_REG_SW_EN_ATSC200_PH12DEMOD0_15A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15AC_CKGEN00_V004 (CKGEN00_V004 + 0x15AC)
	#define REG_15AC_CKGEN00_V004_REG_SW_EN_ATSC200_PH32DEMOD0_15AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B0_CKGEN00_V004 (CKGEN00_V004 + 0x15B0)
	#define REG_15B0_CKGEN00_V004_REG_SW_EN_ATSC252DEMOD0_15B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B4_CKGEN00_V004 (CKGEN00_V004 + 0x15B4)
	#define REG_15B4_CKGEN00_V004_REG_SW_EN_ATSC4002DEMOD0_15B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15B8_CKGEN00_V004 (CKGEN00_V004 + 0x15B8)
	#define REG_15B8_CKGEN00_V004_REG_SW_EN_ATSC502DEMOD0_15B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15BC_CKGEN00_V004 (CKGEN00_V004 + 0x15BC)
	#define REG_15BC_CKGEN00_V004_REG_SW_EN_DEC_XTAL_I2DMD_ANA_15BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C0_CKGEN00_V004 (CKGEN00_V004 + 0x15C0)
	#define REG_15C0_CKGEN00_V004_REG_SW_EN_DEC_XTAL_Q2DMD_ANA_15C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C4_CKGEN00_V004 (CKGEN00_V004 + 0x15C4)
	#define REG_15C4_CKGEN00_V004_REG_SW_EN_DEINTER2DEMOD1_15C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15C8_CKGEN00_V004 (CKGEN00_V004 + 0x15C8)
	#define REG_15C8_CKGEN00_V004_REG_SW_EN_DEMOD_864M2CLK_VIF_SSC_DIV_15C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15CC_CKGEN00_V004 (CKGEN00_V004 + 0x15CC)
	#define REG_15CC_CKGEN00_V004_REG_SW_EN_DEMOD_ADC_INT2DMD_RST_CTRL_15CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D0_CKGEN00_V004 (CKGEN00_V004 + 0x15D0)
	#define REG_15D0_CKGEN00_V004_REG_SW_EN_DMD_DMA2DEMOD0_15D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D4_CKGEN00_V004 (CKGEN00_V004 + 0x15D4)
	#define REG_15D4_CKGEN00_V004_REG_SW_EN_DMPLLDIV10_INT2DMD_RST_CTRL_15D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15D8_CKGEN00_V004 (CKGEN00_V004 + 0x15D8)
	#define REG_15D8_CKGEN00_V004_REG_SW_EN_DMPLLDIV17_INT2DMD_RST_CTRL_15D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15DC_CKGEN00_V004 (CKGEN00_V004 + 0x15DC)
	#define REG_15DC_CKGEN00_V004_REG_SW_EN_DMPLLDIV2_ATSC_INT2DMD_RST_CTRL_15DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E0_CKGEN00_V004 (CKGEN00_V004 + 0x15E0)
	#define REG_15E0_CKGEN00_V004_REG_SW_EN_DMPLLDIV2_DTMB_INT2DMD_RST_CTRL_15E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E4_CKGEN00_V004 (CKGEN00_V004 + 0x15E4)
	#define REG_15E4_CKGEN00_V004_REG_SW_EN_DMPLLDIV2_INT2DMD_RST_CTRL_15E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15E8_CKGEN00_V004 (CKGEN00_V004 + 0x15E8)
	#define REG_15E8_CKGEN00_V004_REG_SW_EN_DMPLLDIV3_DTMB_INT2DMD_RST_CTRL_15E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15EC_CKGEN00_V004 (CKGEN00_V004 + 0x15EC)
	#define REG_15EC_CKGEN00_V004_REG_SW_EN_DMPLLDIV3_DVBC_INT2DMD_RST_CTRL_15EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F0_CKGEN00_V004 (CKGEN00_V004 + 0x15F0)
	#define REG_15F0_CKGEN00_V004_REG_SW_EN_DMPLLDIV3_DVBT2_INT2DMD_RST_CTRL_15F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F4_CKGEN00_V004 (CKGEN00_V004 + 0x15F4)
	#define REG_15F4_CKGEN00_V004_REG_SW_EN_DMPLLDIV3_INT2DMD_RST_CTRL_15F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15F8_CKGEN00_V004 (CKGEN00_V004 + 0x15F8)
	#define REG_15F8_CKGEN00_V004_REG_SW_EN_DMPLLDIV3_ISDBT_INT2DMD_RST_CTRL_15F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_15FC_CKGEN00_V004 (CKGEN00_V004 + 0x15FC)
	#define REG_15FC_CKGEN00_V004_REG_SW_EN_DMPLLDIV3_ISDBT_OUTER_RS_M_OVER_N_INT2DMD_RST_CTRL_15FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1600_CKGEN00_V004 (CKGEN00_V004 + 0x1600)
	#define REG_1600_CKGEN00_V004_REG_SW_EN_DMPLLDIV4_DVB_OPPRO_M_OVER_N_INT2DMD_RST_CTRL_1600 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1604_CKGEN00_V004 (CKGEN00_V004 + 0x1604)
	#define REG_1604_CKGEN00_V004_REG_SW_EN_DMPLLDIV4_DVBS2_BCH_M_OVER_N_INT2DMD_RST_CTRL_1604 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1608_CKGEN00_V004 (CKGEN00_V004 + 0x1608)
	#define REG_1608_CKGEN00_V004_REG_SW_EN_DMPLLDIV4_DVBTC_RS_M_OVER_N_INT2DMD_RST_CTRL_1608 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_160C_CKGEN00_V004 (CKGEN00_V004 + 0x160C)
	#define REG_160C_CKGEN00_V004_REG_SW_EN_DMPLLDIV4_INT2DMD_RST_CTRL_160C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1610_CKGEN00_V004 (CKGEN00_V004 + 0x1610)
	#define REG_1610_CKGEN00_V004_REG_SW_EN_DMPLLDIV5_INT2DMD_RST_CTRL_1610 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1614_CKGEN00_V004 (CKGEN00_V004 + 0x1614)
	#define REG_1614_CKGEN00_V004_REG_SW_EN_DTMB_ADC2DEMOD0_1614 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1618_CKGEN00_V004 (CKGEN00_V004 + 0x1618)
	#define REG_1618_CKGEN00_V004_REG_SW_EN_DTMB_BCH2DEMOD0_1618 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_161C_CKGEN00_V004 (CKGEN00_V004 + 0x161C)
	#define REG_161C_CKGEN00_V004_REG_SW_EN_DTMB_BCH2DEMOD1_161C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1620_CKGEN00_V004 (CKGEN00_V004 + 0x1620)
	#define REG_1620_CKGEN00_V004_REG_SW_EN_DTMB_EQ0P25X2DEMOD0_1620 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1624_CKGEN00_V004 (CKGEN00_V004 + 0x1624)
	#define REG_1624_CKGEN00_V004_REG_SW_EN_DTMB_EQ0P5X2DEMOD0_1624 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1628_CKGEN00_V004 (CKGEN00_V004 + 0x1628)
	#define REG_1628_CKGEN00_V004_REG_SW_EN_DTMB_EQ1X2DEMOD0_1628 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_162C_CKGEN00_V004 (CKGEN00_V004 + 0x162C)
	#define REG_162C_CKGEN00_V004_REG_SW_EN_DTMB_EQ2X_INNER12X2DEMOD0_162C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1630_CKGEN00_V004 (CKGEN00_V004 + 0x1630)
	#define REG_1630_CKGEN00_V004_REG_SW_EN_DTMB_EQ2X_INNER2X_12X2DEMOD0_1630 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1634_CKGEN00_V004 (CKGEN00_V004 + 0x1634)
	#define REG_1634_CKGEN00_V004_REG_SW_EN_DTMB_EQ2X_INNER4X2DEMOD0_1634 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1638_CKGEN00_V004 (CKGEN00_V004 + 0x1638)
	#define REG_1638_CKGEN00_V004_REG_SW_EN_DTMB_EQ2X2DEMOD0_1638 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_163C_CKGEN00_V004 (CKGEN00_V004 + 0x163C)
	#define REG_163C_CKGEN00_V004_REG_SW_EN_DTMB_INNER12X_EQ0P25X2DEMOD0_163C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1640_CKGEN00_V004 (CKGEN00_V004 + 0x1640)
	#define REG_1640_CKGEN00_V004_REG_SW_EN_DTMB_INNER12X_INNER4X2DEMOD0_1640 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1644_CKGEN00_V004 (CKGEN00_V004 + 0x1644)
	#define REG_1644_CKGEN00_V004_REG_SW_EN_DTMB_INNER12X_INNER6X2DEMOD0_1644 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1648_CKGEN00_V004 (CKGEN00_V004 + 0x1648)
	#define REG_1648_CKGEN00_V004_REG_SW_EN_DTMB_INNER12X_INNER8X_TAP_COM2DEMOD0_1648 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_164C_CKGEN00_V004 (CKGEN00_V004 + 0x164C)
	#define REG_164C_CKGEN00_V004_REG_SW_EN_DTMB_INNER12X2DEMOD0_164C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1650_CKGEN00_V004 (CKGEN00_V004 + 0x1650)
	#define REG_1650_CKGEN00_V004_REG_SW_EN_DTMB_INNER1X_ATSC252DEMOD0_1650 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1654_CKGEN00_V004 (CKGEN00_V004 + 0x1654)
	#define REG_1654_CKGEN00_V004_REG_SW_EN_DTMB_INNER1X2DEMOD0_1654 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1658_CKGEN00_V004 (CKGEN00_V004 + 0x1658)
	#define REG_1658_CKGEN00_V004_REG_SW_EN_DTMB_INNER24X_ATSC_4002DEMOD0_1658 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_165C_CKGEN00_V004 (CKGEN00_V004 + 0x165C)
	#define REG_165C_CKGEN00_V004_REG_SW_EN_DTMB_INNER24X2DEMOD0_165C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1660_CKGEN00_V004 (CKGEN00_V004 + 0x1660)
	#define REG_1660_CKGEN00_V004_REG_SW_EN_DTMB_INNER2X_4X_SR1X2DEMOD0_1660 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1664_CKGEN00_V004 (CKGEN00_V004 + 0x1664)
	#define REG_1664_CKGEN00_V004_REG_SW_EN_DTMB_INNER2X_SR0P5X2DEMOD0_1664 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1668_CKGEN00_V004 (CKGEN00_V004 + 0x1668)
	#define REG_1668_CKGEN00_V004_REG_SW_EN_DTMB_INNER2X2DEMOD0_1668 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_166C_CKGEN00_V004 (CKGEN00_V004 + 0x166C)
	#define REG_166C_CKGEN00_V004_REG_SW_EN_DTMB_INNER4X_ATSC502DEMOD0_166C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1670_CKGEN00_V004 (CKGEN00_V004 + 0x1670)
	#define REG_1670_CKGEN00_V004_REG_SW_EN_DTMB_INNER4X_SR1X2DEMOD0_1670 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1674_CKGEN00_V004 (CKGEN00_V004 + 0x1674)
	#define REG_1674_CKGEN00_V004_REG_SW_EN_DTMB_INNER4X2DEMOD0_1674 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1678_CKGEN00_V004 (CKGEN00_V004 + 0x1678)
	#define REG_1678_CKGEN00_V004_REG_SW_EN_DTMB_INNER6X2DEMOD0_1678 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_167C_CKGEN00_V004 (CKGEN00_V004 + 0x167C)
	#define REG_167C_CKGEN00_V004_REG_SW_EN_DTMB_INNER8X_TAP_COM2DEMOD0_167C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1680_CKGEN00_V004 (CKGEN00_V004 + 0x1680)
	#define REG_1680_CKGEN00_V004_REG_SW_EN_DTMB_INNER8X2DEMOD0_1680 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1684_CKGEN00_V004 (CKGEN00_V004 + 0x1684)
	#define REG_1684_CKGEN00_V004_REG_SW_EN_DTMB_LDPC2DEMOD0_1684 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1688_CKGEN00_V004 (CKGEN00_V004 + 0x1688)
	#define REG_1688_CKGEN00_V004_REG_SW_EN_DTMB_LDPC2X2DEMOD0_1688 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_168C_CKGEN00_V004 (CKGEN00_V004 + 0x168C)
	#define REG_168C_CKGEN00_V004_REG_SW_EN_DTMB_OUTER1X2DEMOD0_168C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1690_CKGEN00_V004 (CKGEN00_V004 + 0x1690)
	#define REG_1690_CKGEN00_V004_REG_SW_EN_DTMB_OUTER1X2DEMOD1_1690 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1694_CKGEN00_V004 (CKGEN00_V004 + 0x1694)
	#define REG_1694_CKGEN00_V004_REG_SW_EN_DTMB_OUTER2X2DEMOD0_1694 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1698_CKGEN00_V004 (CKGEN00_V004 + 0x1698)
	#define REG_1698_CKGEN00_V004_REG_SW_EN_DTMB_OUTER8X2DEMOD0_1698 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_169C_CKGEN00_V004 (CKGEN00_V004 + 0x169C)
	#define REG_169C_CKGEN00_V004_REG_SW_EN_DTMB_SRAM_DUMP2DEMOD0_169C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A0_CKGEN00_V004 (CKGEN00_V004 + 0x16A0)
	#define REG_16A0_CKGEN00_V004_REG_SW_EN_DVBS_OUTER1X2DEMOD0_16A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A4_CKGEN00_V004 (CKGEN00_V004 + 0x16A4)
	#define REG_16A4_CKGEN00_V004_REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_DVBT2_INNER2X2DEMOD0_16A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16A8_CKGEN00_V004 (CKGEN00_V004 + 0x16A8)
	#define REG_16A8_CKGEN00_V004_REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X_MIU2DEMOD0_16A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16AC_CKGEN00_V004 (CKGEN00_V004 + 0x16AC)
	#define REG_16AC_CKGEN00_V004_REG_SW_EN_DVBS_OUTER2X_DVBT_OUTER2X2DEMOD0_16AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B0_CKGEN00_V004 (CKGEN00_V004 + 0x16B0)
	#define REG_16B0_CKGEN00_V004_REG_SW_EN_DVBS_OUTER2X2DEMOD0_16B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B4_CKGEN00_V004 (CKGEN00_V004 + 0x16B4)
	#define REG_16B4_CKGEN00_V004_REG_SW_EN_DVBS2_BCH2DEMOD0_16B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16B8_CKGEN00_V004 (CKGEN00_V004 + 0x16B8)
	#define REG_16B8_CKGEN00_V004_REG_SW_EN_DVBS2_DEMAPPER2DEMOD1_16B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16BC_CKGEN00_V004 (CKGEN00_V004 + 0x16BC)
	#define REG_16BC_CKGEN00_V004_REG_SW_EN_DVBS2_DISEQC2DEMOD0_16BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C0_CKGEN00_V004 (CKGEN00_V004 + 0x16C0)
	#define REG_16C0_CKGEN00_V004_REG_SW_EN_DVBS2_DVBT2_DEMAPPER2DEMOD1_16C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C4_CKGEN00_V004 (CKGEN00_V004 + 0x16C4)
	#define REG_16C4_CKGEN00_V004_REG_SW_EN_DVBS2_INNER2DEMOD0_16C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16C8_CKGEN00_V004 (CKGEN00_V004 + 0x16C8)
	#define REG_16C8_CKGEN00_V004_REG_SW_EN_DVBS2_OPPRO2DEMOD0_16C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16CC_CKGEN00_V004 (CKGEN00_V004 + 0x16CC)
	#define REG_16CC_CKGEN00_V004_REG_SW_EN_DVBS2_OUTER_FIFO_IN2DEMOD1_16CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D0_CKGEN00_V004 (CKGEN00_V004 + 0x16D0)
	#define REG_16D0_CKGEN00_V004_REG_SW_EN_DVBT_INNER1X2DEMOD0_16D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D4_CKGEN00_V004 (CKGEN00_V004 + 0x16D4)
	#define REG_16D4_CKGEN00_V004_REG_SW_EN_DVBT_INNER2X_SRD0P5X2DEMOD0_16D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16D8_CKGEN00_V004 (CKGEN00_V004 + 0x16D8)
	#define REG_16D8_CKGEN00_V004_REG_SW_EN_DVBT_INNER2X2DEMOD0_16D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16DC_CKGEN00_V004 (CKGEN00_V004 + 0x16DC)
	#define REG_16DC_CKGEN00_V004_REG_SW_EN_DVBT_INNER4X2DEMOD0_16DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E0_CKGEN00_V004 (CKGEN00_V004 + 0x16E0)
	#define REG_16E0_CKGEN00_V004_REG_SW_EN_DVBT_OUTER1X2DEMOD0_16E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E4_CKGEN00_V004 (CKGEN00_V004 + 0x16E4)
	#define REG_16E4_CKGEN00_V004_REG_SW_EN_DVBT_OUTER2X2DEMOD0_16E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16E8_CKGEN00_V004 (CKGEN00_V004 + 0x16E8)
	#define REG_16E8_CKGEN00_V004_REG_SW_EN_DVBT2_DEMAPPER2DEMOD1_16E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16EC_CKGEN00_V004 (CKGEN00_V004 + 0x16EC)
	#define REG_16EC_CKGEN00_V004_REG_SW_EN_DVBT2_DVBS2_OUTER_FIFO_IN2DEMOD1_16EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F0_CKGEN00_V004 (CKGEN00_V004 + 0x16F0)
	#define REG_16F0_CKGEN00_V004_REG_SW_EN_DVBT2_INNER1X2DEMOD0_16F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F4_CKGEN00_V004 (CKGEN00_V004 + 0x16F4)
	#define REG_16F4_CKGEN00_V004_REG_SW_EN_DVBT2_INNER2X_SRD0P5X2DEMOD0_16F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16F8_CKGEN00_V004 (CKGEN00_V004 + 0x16F8)
	#define REG_16F8_CKGEN00_V004_REG_SW_EN_DVBT2_INNER2X2DEMOD0_16F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_16FC_CKGEN00_V004 (CKGEN00_V004 + 0x16FC)
	#define REG_16FC_CKGEN00_V004_REG_SW_EN_DVBT2_INNER4X_DVBTC_RS2DEMOD0_16FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1700_CKGEN00_V004 (CKGEN00_V004 + 0x1700)
	#define REG_1700_CKGEN00_V004_REG_SW_EN_DVBT2_INNER4X_S2_INNER2DEMOD0_1700 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1704_CKGEN00_V004 (CKGEN00_V004 + 0x1704)
	#define REG_1704_CKGEN00_V004_REG_SW_EN_DVBT2_INNER4X2DEMOD0_1704 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1708_CKGEN00_V004 (CKGEN00_V004 + 0x1708)
	#define REG_1708_CKGEN00_V004_REG_SW_EN_DVBT2_OUTER_FIFO_IN2DEMOD1_1708 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_170C_CKGEN00_V004 (CKGEN00_V004 + 0x170C)
	#define REG_170C_CKGEN00_V004_REG_SW_EN_DVBT2_S2_BCH_OUT2DEMOD1_170C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1710_CKGEN00_V004 (CKGEN00_V004 + 0x1710)
	#define REG_1710_CKGEN00_V004_REG_SW_EN_DVBT2_S2_BCH2DEMOD1_1710 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1718_CKGEN00_V004 (CKGEN00_V004 + 0x1718)
	#define REG_1718_CKGEN00_V004_REG_SW_EN_DVBTC_ADC_I2DMD_ANA_1718 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1720_CKGEN00_V004 (CKGEN00_V004 + 0x1720)
	#define REG_1720_CKGEN00_V004_REG_SW_EN_DVBTC_ADC_Q2DMD_ANA_1720 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1724_CKGEN00_V004 (CKGEN00_V004 + 0x1724)
	#define REG_1724_CKGEN00_V004_REG_SW_EN_DVBTC_ADC2DEMOD0_1724 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1728_CKGEN00_V004 (CKGEN00_V004 + 0x1728)
	#define REG_1728_CKGEN00_V004_REG_SW_EN_DVBTC_OUTER2X_ISDBT_OUTER_RS2DEMOD0_1728 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_172C_CKGEN00_V004 (CKGEN00_V004 + 0x172C)
	#define REG_172C_CKGEN00_V004_REG_SW_EN_DVBTC_OUTER2X2DEMOD0_172C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1730_CKGEN00_V004 (CKGEN00_V004 + 0x1730)
	#define REG_1730_CKGEN00_V004_REG_SW_EN_DVBTC_RS2DEMOD0_1730 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1734_CKGEN00_V004 (CKGEN00_V004 + 0x1734)
	#define REG_1734_CKGEN00_V004_REG_SW_EN_DVBTC_SRAM12DEMOD0_1734 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1738_CKGEN00_V004 (CKGEN00_V004 + 0x1738)
	#define REG_1738_CKGEN00_V004_REG_SW_EN_DVBTC_SRAM32DEMOD0_1738 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_173C_CKGEN00_V004 (CKGEN00_V004 + 0x173C)
	#define REG_173C_CKGEN00_V004_REG_SW_EN_DVBTC_SRAM42DEMOD0_173C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1740_CKGEN00_V004 (CKGEN00_V004 + 0x1740)
	#define REG_1740_CKGEN00_V004_REG_SW_EN_DVBTC_TS2DEMOD0_1740 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1744_CKGEN00_V004 (CKGEN00_V004 + 0x1744)
	#define REG_1744_CKGEN00_V004_REG_SW_EN_DVBTM_ADC0P5X_EQ0P5X2DEMOD0_1744 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1748_CKGEN00_V004 (CKGEN00_V004 + 0x1748)
	#define REG_1748_CKGEN00_V004_REG_SW_EN_DVBTM_ADC1X_EQ1X2DEMOD0_1748 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_174C_CKGEN00_V004 (CKGEN00_V004 + 0x174C)
	#define REG_174C_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_ADC_T22X_DVBTC_RS2DEMOD0_174C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1750_CKGEN00_V004 (CKGEN00_V004 + 0x1750)
	#define REG_1750_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_ADC_T22X2DEMOD0_1750 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1754_CKGEN00_V004 (CKGEN00_V004 + 0x1754)
	#define REG_1754_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T11X_T22X2DEMOD0_1754 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1758_CKGEN00_V004 (CKGEN00_V004 + 0x1758)
	#define REG_1758_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T11X_T24X2DEMOD0_1758 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_175C_CKGEN00_V004 (CKGEN00_V004 + 0x175C)
	#define REG_175C_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T12X_T22X2DEMOD0_175C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1760_CKGEN00_V004 (CKGEN00_V004 + 0x1760)
	#define REG_1760_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T12X_T24X_S2INNER2DEMOD0_1760 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1764_CKGEN00_V004 (CKGEN00_V004 + 0x1764)
	#define REG_1764_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T12X_T24X_SRD1X2DEMOD0_1764 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1768_CKGEN00_V004 (CKGEN00_V004 + 0x1768)
	#define REG_1768_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T12X_T24X2DEMOD0_1768 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_176C_CKGEN00_V004 (CKGEN00_V004 + 0x176C)
	#define REG_176C_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T14X_T24X_S2INNER2DEMOD0_176C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1770_CKGEN00_V004 (CKGEN00_V004 + 0x1770)
	#define REG_1770_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFDAC2DEMOD0_1770 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1774_CKGEN00_V004 (CKGEN00_V004 + 0x1774)
	#define REG_1774_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T14X_T24X_SRD1X_VIFSSC2DEMOD0_1774 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1778_CKGEN00_V004 (CKGEN00_V004 + 0x1778)
	#define REG_1778_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T14X_T24X2DEMOD0_1778 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_177C_CKGEN00_V004 (CKGEN00_V004 + 0x177C)
	#define REG_177C_CKGEN00_V004_REG_SW_EN_DVBTM_SRAM_T1OUTER1X_T24X2DEMOD0_177C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1780_CKGEN00_V004 (CKGEN00_V004 + 0x1780)
	#define REG_1780_CKGEN00_V004_REG_SW_EN_ISDBT_INNER1X_DVBT_INNER1X2DEMOD0_1780 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1784_CKGEN00_V004 (CKGEN00_V004 + 0x1784)
	#define REG_1784_CKGEN00_V004_REG_SW_EN_ISDBT_INNER1X2DEMOD0_1784 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1788_CKGEN00_V004 (CKGEN00_V004 + 0x1788)
	#define REG_1788_CKGEN00_V004_REG_SW_EN_ISDBT_INNER2X_DVBT_INNER2X2DEMOD0_1788 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_178C_CKGEN00_V004 (CKGEN00_V004 + 0x178C)
	#define REG_178C_CKGEN00_V004_REG_SW_EN_ISDBT_INNER2X2DEMOD0_178C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1790_CKGEN00_V004 (CKGEN00_V004 + 0x1790)
	#define REG_1790_CKGEN00_V004_REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X_ADC2DEMOD0_1790 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1794_CKGEN00_V004 (CKGEN00_V004 + 0x1794)
	#define REG_1794_CKGEN00_V004_REG_SW_EN_ISDBT_INNER4X_DVBT_INNER4X2DEMOD0_1794 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1798_CKGEN00_V004 (CKGEN00_V004 + 0x1798)
	#define REG_1798_CKGEN00_V004_REG_SW_EN_ISDBT_INNER4X2DEMOD0_1798 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_179C_CKGEN00_V004 (CKGEN00_V004 + 0x179C)
	#define REG_179C_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER_RS2DEMOD0_179C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A0_CKGEN00_V004 (CKGEN00_V004 + 0x17A0)
	#define REG_17A0_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER12X2DEMOD0_17A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A4_CKGEN00_V004 (CKGEN00_V004 + 0x17A4)
	#define REG_17A4_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER1X_DVBT_OUTER1X2DEMOD0_17A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17A8_CKGEN00_V004 (CKGEN00_V004 + 0x17A8)
	#define REG_17A8_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER1X2DEMOD0_17A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17AC_CKGEN00_V004 (CKGEN00_V004 + 0x17AC)
	#define REG_17AC_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER4X2DEMOD0_17AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B0_CKGEN00_V004 (CKGEN00_V004 + 0x17B0)
	#define REG_17B0_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER1X2DEMOD0_17B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B4_CKGEN00_V004 (CKGEN00_V004 + 0x17B4)
	#define REG_17B4_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER6X_DVBT_INNER2X2DEMOD0_17B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17B8_CKGEN00_V004 (CKGEN00_V004 + 0x17B8)
	#define REG_17B8_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X_C2DEMOD0_17B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17BC_CKGEN00_V004 (CKGEN00_V004 + 0x17BC)
	#define REG_17BC_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER6X_DVBT_OUTER2X2DEMOD0_17BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C0_CKGEN00_V004 (CKGEN00_V004 + 0x17C0)
	#define REG_17C0_CKGEN00_V004_REG_SW_EN_ISDBT_OUTER6X2DEMOD0_17C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C4_CKGEN00_V004 (CKGEN00_V004 + 0x17C4)
	#define REG_17C4_CKGEN00_V004_REG_SW_EN_LDPC1X2DEMOD1_17C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17C8_CKGEN00_V004 (CKGEN00_V004 + 0x17C8)
	#define REG_17C8_CKGEN00_V004_REG_SW_EN_LDPC2X2DEMOD1_17C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E0_CKGEN00_V004 (CKGEN00_V004 + 0x17E0)
	#define REG_17E0_CKGEN00_V004_REG_SW_EN_SRAM_DVBT2_S2_BCH_ME2DEMOD1_17E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E4_CKGEN00_V004 (CKGEN00_V004 + 0x17E4)
	#define REG_17E4_CKGEN00_V004_REG_SW_EN_SRAM_LDPC1X_ME2DEMOD1_17E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17E8_CKGEN00_V004 (CKGEN00_V004 + 0x17E8)
	#define REG_17E8_CKGEN00_V004_REG_SW_EN_SRAM_LDPC2X_ME2DEMOD1_17E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17EC_CKGEN00_V004 (CKGEN00_V004 + 0x17EC)
	#define REG_17EC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_00_02DEMOD0_17EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F0_CKGEN00_V004 (CKGEN00_V004 + 0x17F0)
	#define REG_17F0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_00_12DEMOD0_17F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F4_CKGEN00_V004 (CKGEN00_V004 + 0x17F4)
	#define REG_17F4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_01_02DEMOD0_17F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17F8_CKGEN00_V004 (CKGEN00_V004 + 0x17F8)
	#define REG_17F8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_02_02DEMOD0_17F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_17FC_CKGEN00_V004 (CKGEN00_V004 + 0x17FC)
	#define REG_17FC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_03_02DEMOD0_17FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1800_CKGEN00_V004 (CKGEN00_V004 + 0x1800)
	#define REG_1800_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_03_12DEMOD0_1800 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1804_CKGEN00_V004 (CKGEN00_V004 + 0x1804)
	#define REG_1804_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_04_02DEMOD0_1804 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1808_CKGEN00_V004 (CKGEN00_V004 + 0x1808)
	#define REG_1808_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_04_12DEMOD0_1808 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_180C_CKGEN00_V004 (CKGEN00_V004 + 0x180C)
	#define REG_180C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_052DEMOD0_180C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1810_CKGEN00_V004 (CKGEN00_V004 + 0x1810)
	#define REG_1810_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_062DEMOD0_1810 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1814_CKGEN00_V004 (CKGEN00_V004 + 0x1814)
	#define REG_1814_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_072DEMOD0_1814 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1818_CKGEN00_V004 (CKGEN00_V004 + 0x1818)
	#define REG_1818_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_082DEMOD0_1818 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_181C_CKGEN00_V004 (CKGEN00_V004 + 0x181C)
	#define REG_181C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_092DEMOD0_181C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1820_CKGEN00_V004 (CKGEN00_V004 + 0x1820)
	#define REG_1820_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_102DEMOD0_1820 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1824_CKGEN00_V004 (CKGEN00_V004 + 0x1824)
	#define REG_1824_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_112DEMOD0_1824 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1828_CKGEN00_V004 (CKGEN00_V004 + 0x1828)
	#define REG_1828_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_122DEMOD0_1828 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_182C_CKGEN00_V004 (CKGEN00_V004 + 0x182C)
	#define REG_182C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_132DEMOD0_182C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1830_CKGEN00_V004 (CKGEN00_V004 + 0x1830)
	#define REG_1830_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_14_R2DEMOD0_1830 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1834_CKGEN00_V004 (CKGEN00_V004 + 0x1834)
	#define REG_1834_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_14_W2DEMOD0_1834 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1838_CKGEN00_V004 (CKGEN00_V004 + 0x1838)
	#define REG_1838_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_15_R2DEMOD0_1838 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_183C_CKGEN00_V004 (CKGEN00_V004 + 0x183C)
	#define REG_183C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_15_W2DEMOD0_183C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1840_CKGEN00_V004 (CKGEN00_V004 + 0x1840)
	#define REG_1840_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_162DEMOD0_1840 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1844_CKGEN00_V004 (CKGEN00_V004 + 0x1844)
	#define REG_1844_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_182DEMOD0_1844 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1848_CKGEN00_V004 (CKGEN00_V004 + 0x1848)
	#define REG_1848_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_192DEMOD0_1848 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_184C_CKGEN00_V004 (CKGEN00_V004 + 0x184C)
	#define REG_184C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_202DEMOD0_184C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1850_CKGEN00_V004 (CKGEN00_V004 + 0x1850)
	#define REG_1850_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_212DEMOD0_1850 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1854_CKGEN00_V004 (CKGEN00_V004 + 0x1854)
	#define REG_1854_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_222DEMOD0_1854 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1858_CKGEN00_V004 (CKGEN00_V004 + 0x1858)
	#define REG_1858_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_232DEMOD0_1858 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_185C_CKGEN00_V004 (CKGEN00_V004 + 0x185C)
	#define REG_185C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_242DEMOD0_185C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1860_CKGEN00_V004 (CKGEN00_V004 + 0x1860)
	#define REG_1860_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_262DEMOD0_1860 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1864_CKGEN00_V004 (CKGEN00_V004 + 0x1864)
	#define REG_1864_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_272DEMOD0_1864 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1868_CKGEN00_V004 (CKGEN00_V004 + 0x1868)
	#define REG_1868_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_282DEMOD0_1868 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_186C_CKGEN00_V004 (CKGEN00_V004 + 0x186C)
	#define REG_186C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_292DEMOD0_186C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1870_CKGEN00_V004 (CKGEN00_V004 + 0x1870)
	#define REG_1870_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_342DEMOD0_1870 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1874_CKGEN00_V004 (CKGEN00_V004 + 0x1874)
	#define REG_1874_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_352DEMOD0_1874 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1878_CKGEN00_V004 (CKGEN00_V004 + 0x1878)
	#define REG_1878_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_362DEMOD0_1878 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_187C_CKGEN00_V004 (CKGEN00_V004 + 0x187C)
	#define REG_187C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_402DEMOD0_187C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1880_CKGEN00_V004 (CKGEN00_V004 + 0x1880)
	#define REG_1880_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_422DEMOD0_1880 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1884_CKGEN00_V004 (CKGEN00_V004 + 0x1884)
	#define REG_1884_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_442DEMOD0_1884 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1888_CKGEN00_V004 (CKGEN00_V004 + 0x1888)
	#define REG_1888_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_462DEMOD0_1888 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_188C_CKGEN00_V004 (CKGEN00_V004 + 0x188C)
	#define REG_188C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_472DEMOD0_188C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1890_CKGEN00_V004 (CKGEN00_V004 + 0x1890)
	#define REG_1890_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_50_02DEMOD0_1890 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1894_CKGEN00_V004 (CKGEN00_V004 + 0x1894)
	#define REG_1894_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_52_02DEMOD0_1894 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1898_CKGEN00_V004 (CKGEN00_V004 + 0x1898)
	#define REG_1898_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_53_02DEMOD0_1898 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_189C_CKGEN00_V004 (CKGEN00_V004 + 0x189C)
	#define REG_189C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_55_02DEMOD0_189C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A0_CKGEN00_V004 (CKGEN00_V004 + 0x18A0)
	#define REG_18A0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_562DEMOD0_18A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A4_CKGEN00_V004 (CKGEN00_V004 + 0x18A4)
	#define REG_18A4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_572DEMOD0_18A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18A8_CKGEN00_V004 (CKGEN00_V004 + 0x18A8)
	#define REG_18A8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_582DEMOD0_18A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18AC_CKGEN00_V004 (CKGEN00_V004 + 0x18AC)
	#define REG_18AC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_592DEMOD0_18AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B0_CKGEN00_V004 (CKGEN00_V004 + 0x18B0)
	#define REG_18B0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_602DEMOD0_18B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B4_CKGEN00_V004 (CKGEN00_V004 + 0x18B4)
	#define REG_18B4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_612DEMOD0_18B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18B8_CKGEN00_V004 (CKGEN00_V004 + 0x18B8)
	#define REG_18B8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_622DEMOD0_18B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18BC_CKGEN00_V004 (CKGEN00_V004 + 0x18BC)
	#define REG_18BC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_642DEMOD0_18BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C0_CKGEN00_V004 (CKGEN00_V004 + 0x18C0)
	#define REG_18C0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_662DEMOD0_18C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C4_CKGEN00_V004 (CKGEN00_V004 + 0x18C4)
	#define REG_18C4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_672DEMOD0_18C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18C8_CKGEN00_V004 (CKGEN00_V004 + 0x18C8)
	#define REG_18C8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_68_02DEMOD0_18C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18CC_CKGEN00_V004 (CKGEN00_V004 + 0x18CC)
	#define REG_18CC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_68_22DEMOD0_18CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D0_CKGEN00_V004 (CKGEN00_V004 + 0x18D0)
	#define REG_18D0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_69_02DEMOD0_18D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D4_CKGEN00_V004 (CKGEN00_V004 + 0x18D4)
	#define REG_18D4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_702DEMOD0_18D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18D8_CKGEN00_V004 (CKGEN00_V004 + 0x18D8)
	#define REG_18D8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_712DEMOD0_18D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18DC_CKGEN00_V004 (CKGEN00_V004 + 0x18DC)
	#define REG_18DC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_772DEMOD0_18DC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E0_CKGEN00_V004 (CKGEN00_V004 + 0x18E0)
	#define REG_18E0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_792DEMOD0_18E0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E4_CKGEN00_V004 (CKGEN00_V004 + 0x18E4)
	#define REG_18E4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_812DEMOD0_18E4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18E8_CKGEN00_V004 (CKGEN00_V004 + 0x18E8)
	#define REG_18E8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_852DEMOD0_18E8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18EC_CKGEN00_V004 (CKGEN00_V004 + 0x18EC)
	#define REG_18EC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_872DEMOD0_18EC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F0_CKGEN00_V004 (CKGEN00_V004 + 0x18F0)
	#define REG_18F0_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_892DEMOD0_18F0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F4_CKGEN00_V004 (CKGEN00_V004 + 0x18F4)
	#define REG_18F4_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_912DEMOD0_18F4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18F8_CKGEN00_V004 (CKGEN00_V004 + 0x18F8)
	#define REG_18F8_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_922DEMOD0_18F8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_18FC_CKGEN00_V004 (CKGEN00_V004 + 0x18FC)
	#define REG_18FC_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_932DEMOD0_18FC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1900_CKGEN00_V004 (CKGEN00_V004 + 0x1900)
	#define REG_1900_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_942DEMOD0_1900 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1904_CKGEN00_V004 (CKGEN00_V004 + 0x1904)
	#define REG_1904_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_962DEMOD0_1904 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1908_CKGEN00_V004 (CKGEN00_V004 + 0x1908)
	#define REG_1908_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_982DEMOD0_1908 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_190C_CKGEN00_V004 (CKGEN00_V004 + 0x190C)
	#define REG_190C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_992DEMOD0_190C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1910_CKGEN00_V004 (CKGEN00_V004 + 0x1910)
	#define REG_1910_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1002DEMOD0_1910 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1914_CKGEN00_V004 (CKGEN00_V004 + 0x1914)
	#define REG_1914_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1032DEMOD0_1914 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1918_CKGEN00_V004 (CKGEN00_V004 + 0x1918)
	#define REG_1918_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1052DEMOD0_1918 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_191C_CKGEN00_V004 (CKGEN00_V004 + 0x191C)
	#define REG_191C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1072DEMOD0_191C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1920_CKGEN00_V004 (CKGEN00_V004 + 0x1920)
	#define REG_1920_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1092DEMOD0_1920 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1924_CKGEN00_V004 (CKGEN00_V004 + 0x1924)
	#define REG_1924_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1102DEMOD0_1924 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1928_CKGEN00_V004 (CKGEN00_V004 + 0x1928)
	#define REG_1928_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1112DEMOD0_1928 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_192C_CKGEN00_V004 (CKGEN00_V004 + 0x192C)
	#define REG_192C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1122DEMOD0_192C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1930_CKGEN00_V004 (CKGEN00_V004 + 0x1930)
	#define REG_1930_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1242DEMOD0_1930 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1934_CKGEN00_V004 (CKGEN00_V004 + 0x1934)
	#define REG_1934_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1282DEMOD0_1934 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1938_CKGEN00_V004 (CKGEN00_V004 + 0x1938)
	#define REG_1938_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1292DEMOD0_1938 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_193C_CKGEN00_V004 (CKGEN00_V004 + 0x193C)
	#define REG_193C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1302DEMOD0_193C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1940_CKGEN00_V004 (CKGEN00_V004 + 0x1940)
	#define REG_1940_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1312DEMOD0_1940 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1944_CKGEN00_V004 (CKGEN00_V004 + 0x1944)
	#define REG_1944_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_1322DEMOD0_1944 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1948_CKGEN00_V004 (CKGEN00_V004 + 0x1948)
	#define REG_1948_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_134_R2DEMOD0_1948 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_194C_CKGEN00_V004 (CKGEN00_V004 + 0x194C)
	#define REG_194C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_134_W2DEMOD0_194C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1950_CKGEN00_V004 (CKGEN00_V004 + 0x1950)
	#define REG_1950_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_136_R2DEMOD0_1950 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1954_CKGEN00_V004 (CKGEN00_V004 + 0x1954)
	#define REG_1954_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_136_W2DEMOD0_1954 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1958_CKGEN00_V004 (CKGEN00_V004 + 0x1958)
	#define REG_1958_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_137_R2DEMOD0_1958 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_195C_CKGEN00_V004 (CKGEN00_V004 + 0x195C)
	#define REG_195C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_137_W2DEMOD0_195C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1960_CKGEN00_V004 (CKGEN00_V004 + 0x1960)
	#define REG_1960_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_138_R2DEMOD0_1960 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1964_CKGEN00_V004 (CKGEN00_V004 + 0x1964)
	#define REG_1964_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_138_W2DEMOD0_1964 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1968_CKGEN00_V004 (CKGEN00_V004 + 0x1968)
	#define REG_1968_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_139_R2DEMOD0_1968 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_196C_CKGEN00_V004 (CKGEN00_V004 + 0x196C)
	#define REG_196C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_139_W2DEMOD0_196C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1970_CKGEN00_V004 (CKGEN00_V004 + 0x1970)
	#define REG_1970_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_140_R2DEMOD0_1970 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1974_CKGEN00_V004 (CKGEN00_V004 + 0x1974)
	#define REG_1974_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_140_W2DEMOD0_1974 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1978_CKGEN00_V004 (CKGEN00_V004 + 0x1978)
	#define REG_1978_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_141_R2DEMOD0_1978 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_197C_CKGEN00_V004 (CKGEN00_V004 + 0x197C)
	#define REG_197C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_141_W2DEMOD0_197C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1980_CKGEN00_V004 (CKGEN00_V004 + 0x1980)
	#define REG_1980_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_142_R2DEMOD0_1980 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1984_CKGEN00_V004 (CKGEN00_V004 + 0x1984)
	#define REG_1984_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_142_W2DEMOD0_1984 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1988_CKGEN00_V004 (CKGEN00_V004 + 0x1988)
	#define REG_1988_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_143_R2DEMOD0_1988 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_198C_CKGEN00_V004 (CKGEN00_V004 + 0x198C)
	#define REG_198C_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_143_W2DEMOD0_198C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1990_CKGEN00_V004 (CKGEN00_V004 + 0x1990)
	#define REG_1990_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_144_R2DEMOD0_1990 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1994_CKGEN00_V004 (CKGEN00_V004 + 0x1994)
	#define REG_1994_CKGEN00_V004_REG_SW_EN_SRAM_SHARE_144_W2DEMOD0_1994 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1998_CKGEN00_V004 (CKGEN00_V004 + 0x1998)
	#define REG_1998_CKGEN00_V004_REG_SW_EN_TDP_JL_INNER1X2DEMOD0_1998 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_199C_CKGEN00_V004 (CKGEN00_V004 + 0x199C)
	#define REG_199C_CKGEN00_V004_REG_SW_EN_TDP_JL_INNER4X2DEMOD0_199C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A0_CKGEN00_V004 (CKGEN00_V004 + 0x19A0)
	#define REG_19A0_CKGEN00_V004_REG_SW_EN_TDP_TEQ_INNER1X2DEMOD0_19A0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A4_CKGEN00_V004 (CKGEN00_V004 + 0x19A4)
	#define REG_19A4_CKGEN00_V004_REG_SW_EN_TDP_TEQ_INNER2X2DEMOD0_19A4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19A8_CKGEN00_V004 (CKGEN00_V004 + 0x19A8)
	#define REG_19A8_CKGEN00_V004_REG_SW_EN_TR2DEMOD0_19A8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19AC_CKGEN00_V004 (CKGEN00_V004 + 0x19AC)
	#define REG_19AC_CKGEN00_V004_REG_SW_EN_TS_IN2DEMOD0_19AC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B0_CKGEN00_V004 (CKGEN00_V004 + 0x19B0)
	#define REG_19B0_CKGEN00_V004_REG_SW_EN_VIFDBB_144M2DEMOD0_19B0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B4_CKGEN00_V004 (CKGEN00_V004 + 0x19B4)
	#define REG_19B4_CKGEN00_V004_REG_SW_EN_VIFDBB_43M2DEMOD0_19B4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19B8_CKGEN00_V004 (CKGEN00_V004 + 0x19B8)
	#define REG_19B8_CKGEN00_V004_REG_SW_EN_VIFDBB_86M2DEMOD0_19B8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19BC_CKGEN00_V004 (CKGEN00_V004 + 0x19BC)
	#define REG_19BC_CKGEN00_V004_REG_SW_EN_VIFDBB_DAC2DEMOD0_19BC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C0_CKGEN00_V004 (CKGEN00_V004 + 0x19C0)
	#define REG_19C0_CKGEN00_V004_REG_SW_EN_VIFDBB_VDAC_TMP2DEMOD0_19C0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C4_CKGEN00_V004 (CKGEN00_V004 + 0x19C4)
	#define REG_19C4_CKGEN00_V004_REG_SW_EN_VIFDBB_VDAC2DEMOD0_19C4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19C8_CKGEN00_V004 (CKGEN00_V004 + 0x19C8)
	#define REG_19C8_CKGEN00_V004_REG_SW_EN_XTAL_12M2DEMOD0_19C8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19CC_CKGEN00_V004 (CKGEN00_V004 + 0x19CC)
	#define REG_19CC_CKGEN00_V004_REG_SW_EN_XTAL_24M2DEMOD0_19CC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D0_CKGEN00_V004 (CKGEN00_V004 + 0x19D0)
	#define REG_19D0_CKGEN00_V004_REG_SW_EN_XTAL_24M2DEMOD1_19D0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D4_CKGEN00_V004 (CKGEN00_V004 + 0x19D4)
	#define REG_19D4_CKGEN00_V004_REG_SW_EN_XTAL_12M2DEMOD1_19D4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_19D8_CKGEN00_V004 (CKGEN00_V004 + 0x19D8)
	#define REG_19D8_CKGEN00_V004_REG_SW_EN_VIFDBB_DAC_FROM_TOP2DEMOD0_19D8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A00_CKGEN00_V004 (CKGEN00_V004 + 0x1A00)
	#define REG_1A00_CKGEN00_V004_REG_SW_EN_AESDMA2DSCRMB_1A00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A0C_CKGEN00_V004 (CKGEN00_V004 + 0x1A0C)
	#define REG_1A0C_CKGEN00_V004_REG_SW_EN_CILINK_2B_RX2CILINK_1A0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A10_CKGEN00_V004 (CKGEN00_V004 + 0x1A10)
	#define REG_1A10_CKGEN00_V004_REG_SW_EN_CILINK_2B_TX_EXT2TS_SAMPLE_1A10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A14_CKGEN00_V004 (CKGEN00_V004 + 0x1A14)
	#define REG_1A14_CKGEN00_V004_REG_SW_EN_CILINK_2B_TX2CILINK_1A14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A18_CKGEN00_V004 (CKGEN00_V004 + 0x1A18)
	#define REG_1A18_CKGEN00_V004_REG_SW_EN_CILINK_IF2CILINK_1A18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A24_CKGEN00_V004 (CKGEN00_V004 + 0x1A24)
	#define REG_1A24_CKGEN00_V004_REG_SW_EN_SMART_SYNTH_272PIU_1A24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A28_CKGEN00_V004 (CKGEN00_V004 + 0x1A28)
	#define REG_1A28_CKGEN00_V004_REG_SW_EN_SMART_SYNTH_4322PIU_1A28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A2C_CKGEN00_V004 (CKGEN00_V004 + 0x1A2C)
	#define REG_1A2C_CKGEN00_V004_REG_SW_EN_SMART2_SYNTH_272PIU_1A2C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A30_CKGEN00_V004 (CKGEN00_V004 + 0x1A30)
	#define REG_1A30_CKGEN00_V004_REG_SW_EN_SMART2_SYNTH_4322PIU_1A30 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A34_CKGEN00_V004 (CKGEN00_V004 + 0x1A34)
	#define REG_1A34_CKGEN00_V004_REG_SW_EN_SMART22PIU_1A34 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A38_CKGEN00_V004 (CKGEN00_V004 + 0x1A38)
	#define REG_1A38_CKGEN00_V004_REG_SW_EN_SMART2PIU_1A38 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A48_CKGEN00_V004 (CKGEN00_V004 + 0x1A48)
	#define REG_1A48_CKGEN00_V004_REG_SW_EN_FIQ0_27M2TSP_1A48 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A4C_CKGEN00_V004 (CKGEN00_V004 + 0x1A4C)
	#define REG_1A4C_CKGEN00_V004_REG_SW_EN_MM0_27M2TSP_1A4C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A50_CKGEN00_V004 (CKGEN00_V004 + 0x1A50)
	#define REG_1A50_CKGEN00_V004_REG_SW_EN_MM1_27M2TSP_1A50 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A54_CKGEN00_V004 (CKGEN00_V004 + 0x1A54)
	#define REG_1A54_CKGEN00_V004_REG_SW_EN_PARSER2TSP_1A54 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1A54_CKGEN00_V004_REG_SW_EN_PARSER2VD_PES_PARSER_1A54 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1A54_CKGEN00_V004_REG_SW_EN_VIVA_PARSER2PARSER_1A54 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1A58_CKGEN00_V004 (CKGEN00_V004 + 0x1A58)
	#define REG_1A58_CKGEN00_V004_REG_SW_EN_PVR1_27M2TSP_1A58 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A5C_CKGEN00_V004 (CKGEN00_V004 + 0x1A5C)
	#define REG_1A5C_CKGEN00_V004_REG_SW_EN_PVR2_27M2TSP_1A5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A60_CKGEN00_V004 (CKGEN00_V004 + 0x1A60)
	#define REG_1A60_CKGEN00_V004_REG_SW_EN_PVR3_27M2TSP_1A60 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A64_CKGEN00_V004 (CKGEN00_V004 + 0x1A64)
	#define REG_1A64_CKGEN00_V004_REG_SW_EN_PVR4_27M2TSP_1A64 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A6C_CKGEN00_V004 (CKGEN00_V004 + 0x1A6C)
	#define REG_1A6C_CKGEN00_V004_REG_SW_EN_STAMP2TSO_1A6C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A70_CKGEN00_V004 (CKGEN00_V004 + 0x1A70)
	#define REG_1A70_CKGEN00_V004_REG_SW_EN_STAMP2TSO2_1A70 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A74_CKGEN00_V004 (CKGEN00_V004 + 0x1A74)
	#define REG_1A74_CKGEN00_V004_REG_SW_EN_STAMP2TSP_1A74 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A78_CKGEN00_V004 (CKGEN00_V004 + 0x1A78)
	#define REG_1A78_CKGEN00_V004_REG_SW_EN_SYN_STC02TS_SAMPLE_1A78 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A7C_CKGEN00_V004 (CKGEN00_V004 + 0x1A7C)
	#define REG_1A7C_CKGEN00_V004_REG_SW_EN_SYN_STC12TS_SAMPLE_1A7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A80_CKGEN00_V004 (CKGEN00_V004 + 0x1A80)
	#define REG_1A80_CKGEN00_V004_REG_SW_EN_SYN_STC22TS_SAMPLE_1A80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A84_CKGEN00_V004 (CKGEN00_V004 + 0x1A84)
	#define REG_1A84_CKGEN00_V004_REG_SW_EN_SYN_STC32TS_SAMPLE_1A84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A88_CKGEN00_V004 (CKGEN00_V004 + 0x1A88)
	#define REG_1A88_CKGEN00_V004_REG_SW_EN_SYS_TIME0_27M2TSP_1A88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A8C_CKGEN00_V004 (CKGEN00_V004 + 0x1A8C)
	#define REG_1A8C_CKGEN00_V004_REG_SW_EN_SYS_TIME1_27M2TSP_1A8C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A90_CKGEN00_V004 (CKGEN00_V004 + 0x1A90)
	#define REG_1A90_CKGEN00_V004_REG_SW_EN_SYS_TIME2_27M2TSP_1A90 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A94_CKGEN00_V004 (CKGEN00_V004 + 0x1A94)
	#define REG_1A94_CKGEN00_V004_REG_SW_EN_SYS_TIME3_27M2TSP_1A94 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A98_CKGEN00_V004 (CKGEN00_V004 + 0x1A98)
	#define REG_1A98_CKGEN00_V004_REG_SW_EN_TLV0_27M2TSP_1A98 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1A9C_CKGEN00_V004 (CKGEN00_V004 + 0x1A9C)
	#define REG_1A9C_CKGEN00_V004_REG_SW_EN_TLV1_27M2TSP_1A9C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AA0_CKGEN00_V004 (CKGEN00_V004 + 0x1AA0)
	#define REG_1AA0_CKGEN00_V004_REG_SW_EN_TLV2_27M2TSP_1AA0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AA8_CKGEN00_V004 (CKGEN00_V004 + 0x1AA8)
	#define REG_1AA8_CKGEN00_V004_REG_SW_EN_TS_ALP02TSP_1AA8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AAC_CKGEN00_V004 (CKGEN00_V004 + 0x1AAC)
	#define REG_1AAC_CKGEN00_V004_REG_SW_EN_TS_ALP12TSP_1AAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB4_CKGEN00_V004 (CKGEN00_V004 + 0x1AB4)
	#define REG_1AB4_CKGEN00_V004_REG_SW_EN_TS_SAMPLE2TS_SAMPLE_1AB4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AB8_CKGEN00_V004 (CKGEN00_V004 + 0x1AB8)
	#define REG_1AB8_CKGEN00_V004_REG_SW_EN_TS_TX_C12CILINK_1AB8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ABC_CKGEN00_V004 (CKGEN00_V004 + 0x1ABC)
	#define REG_1ABC_CKGEN00_V004_REG_SW_EN_TS_TX_C22CILINK_1ABC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AC0_CKGEN00_V004 (CKGEN00_V004 + 0x1AC0)
	#define REG_1AC0_CKGEN00_V004_REG_SW_EN_TS0_IN_DFT2TS_SAMPLE_1AC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AC4_CKGEN00_V004 (CKGEN00_V004 + 0x1AC4)
	#define REG_1AC4_CKGEN00_V004_REG_SW_EN_TS02TSP_1AC4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AC8_CKGEN00_V004 (CKGEN00_V004 + 0x1AC8)
	#define REG_1AC8_CKGEN00_V004_REG_SW_EN_TS1_IN_DFT2TS_SAMPLE_1AC8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ACC_CKGEN00_V004 (CKGEN00_V004 + 0x1ACC)
	#define REG_1ACC_CKGEN00_V004_REG_SW_EN_TS12TSP_1ACC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD0_CKGEN00_V004 (CKGEN00_V004 + 0x1AD0)
	#define REG_1AD0_CKGEN00_V004_REG_SW_EN_TS2_IN_DFT2TS_SAMPLE_1AD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD4_CKGEN00_V004 (CKGEN00_V004 + 0x1AD4)
	#define REG_1AD4_CKGEN00_V004_REG_SW_EN_TS22TSP_1AD4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AD8_CKGEN00_V004 (CKGEN00_V004 + 0x1AD8)
	#define REG_1AD8_CKGEN00_V004_REG_SW_EN_TS3_IN_DFT2TS_SAMPLE_1AD8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1ADC_CKGEN00_V004 (CKGEN00_V004 + 0x1ADC)
	#define REG_1ADC_CKGEN00_V004_REG_SW_EN_TS4_IN_DFT2TS_SAMPLE_1ADC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE0_CKGEN00_V004 (CKGEN00_V004 + 0x1AE0)
	#define REG_1AE0_CKGEN00_V004_REG_SW_EN_TS5_IN_DFT2TS_SAMPLE_1AE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE4_CKGEN00_V004 (CKGEN00_V004 + 0x1AE4)
	#define REG_1AE4_CKGEN00_V004_REG_SW_EN_TSFI2TSP_1AE4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AE8_CKGEN00_V004 (CKGEN00_V004 + 0x1AE8)
	#define REG_1AE8_CKGEN00_V004_REG_SW_EN_TSIF0_27M2TSP_1AE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AEC_CKGEN00_V004 (CKGEN00_V004 + 0x1AEC)
	#define REG_1AEC_CKGEN00_V004_REG_SW_EN_TSO_CH1_27M2TSO_1AEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF0_CKGEN00_V004 (CKGEN00_V004 + 0x1AF0)
	#define REG_1AF0_CKGEN00_V004_REG_SW_EN_TSO_CH12TSO_1AF0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF4_CKGEN00_V004 (CKGEN00_V004 + 0x1AF4)
	#define REG_1AF4_CKGEN00_V004_REG_SW_EN_TSO_CH5_27M2TSO_1AF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AF8_CKGEN00_V004 (CKGEN00_V004 + 0x1AF8)
	#define REG_1AF8_CKGEN00_V004_REG_SW_EN_TSO_CH52TSO_1AF8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1AFC_CKGEN00_V004 (CKGEN00_V004 + 0x1AFC)
	#define REG_1AFC_CKGEN00_V004_REG_SW_EN_TSO_CH6_27M2TSO_1AFC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B00_CKGEN00_V004 (CKGEN00_V004 + 0x1B00)
	#define REG_1B00_CKGEN00_V004_REG_SW_EN_TSO_CH62TSO_1B00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B04_CKGEN00_V004 (CKGEN00_V004 + 0x1B04)
	#define REG_1B04_CKGEN00_V004_REG_SW_EN_TSO_OUT_DIV_MN_SRC2TS_SAMPLE_1B04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B08_CKGEN00_V004 (CKGEN00_V004 + 0x1B08)
	#define REG_1B08_CKGEN00_V004_REG_SW_EN_TSO_OUT2TSO_1B08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B0C_CKGEN00_V004 (CKGEN00_V004 + 0x1B0C)
	#define REG_1B0C_CKGEN00_V004_REG_SW_EN_TSO_S2P12TSO_1B0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B10_CKGEN00_V004 (CKGEN00_V004 + 0x1B10)
	#define REG_1B10_CKGEN00_V004_REG_SW_EN_TSO_S2P2TSO_1B10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B14_CKGEN00_V004 (CKGEN00_V004 + 0x1B14)
	#define REG_1B14_CKGEN00_V004_REG_SW_EN_TSO_TRACE_IN2TSO_1B14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B18_CKGEN00_V004 (CKGEN00_V004 + 0x1B18)
	#define REG_1B18_CKGEN00_V004_REG_SW_EN_TSO_TRACE2TSO_1B18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B1C_CKGEN00_V004 (CKGEN00_V004 + 0x1B1C)
	#define REG_1B1C_CKGEN00_V004_REG_SW_EN_TSO2_CH1_27M2TSO2_1B1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B20_CKGEN00_V004 (CKGEN00_V004 + 0x1B20)
	#define REG_1B20_CKGEN00_V004_REG_SW_EN_TSO2_CH12TSO2_1B20 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B24_CKGEN00_V004 (CKGEN00_V004 + 0x1B24)
	#define REG_1B24_CKGEN00_V004_REG_SW_EN_TSO2_CH5_27M2TSO2_1B24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B28_CKGEN00_V004 (CKGEN00_V004 + 0x1B28)
	#define REG_1B28_CKGEN00_V004_REG_SW_EN_TSO2_CH52TSO2_1B28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B2C_CKGEN00_V004 (CKGEN00_V004 + 0x1B2C)
	#define REG_1B2C_CKGEN00_V004_REG_SW_EN_TSO2_CH6_27M2TSO2_1B2C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B30_CKGEN00_V004 (CKGEN00_V004 + 0x1B30)
	#define REG_1B30_CKGEN00_V004_REG_SW_EN_TSO2_CH62TSO2_1B30 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B34_CKGEN00_V004 (CKGEN00_V004 + 0x1B34)
	#define REG_1B34_CKGEN00_V004_REG_SW_EN_TSO2_OUT_DIV_MN_SRC2TS_SAMPLE_1B34 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B38_CKGEN00_V004 (CKGEN00_V004 + 0x1B38)
	#define REG_1B38_CKGEN00_V004_REG_SW_EN_TSO2_OUT2TSO2_1B38 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B3C_CKGEN00_V004 (CKGEN00_V004 + 0x1B3C)
	#define REG_1B3C_CKGEN00_V004_REG_SW_EN_TSO2_S2P12TSO2_1B3C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B40_CKGEN00_V004 (CKGEN00_V004 + 0x1B40)
	#define REG_1B40_CKGEN00_V004_REG_SW_EN_TSO2_S2P2TSO2_1B40 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B44_CKGEN00_V004 (CKGEN00_V004 + 0x1B44)
	#define REG_1B44_CKGEN00_V004_REG_SW_EN_TSO2_TRACE_IN2TSO2_1B44 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B48_CKGEN00_V004 (CKGEN00_V004 + 0x1B48)
	#define REG_1B48_CKGEN00_V004_REG_SW_EN_TSO2_TRACE2TSO2_1B48 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B4C_CKGEN00_V004 (CKGEN00_V004 + 0x1B4C)
	#define REG_1B4C_CKGEN00_V004_REG_SW_EN_TSP2DSCRMB_1B4C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B50_CKGEN00_V004 (CKGEN00_V004 + 0x1B50)
	#define REG_1B50_CKGEN00_V004_REG_SW_EN_TSP2TSO_1B50 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1B50_CKGEN00_V004_REG_SW_EN_TSP2TSO2_1B50 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1B50_CKGEN00_V004_REG_SW_EN_TSP2TSP_1B50 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1B54_CKGEN00_V004 (CKGEN00_V004 + 0x1B54)
	#define REG_1B54_CKGEN00_V004_REG_SW_EN_TS_TLV02TSP_1B54 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B58_CKGEN00_V004 (CKGEN00_V004 + 0x1B58)
	#define REG_1B58_CKGEN00_V004_REG_SW_EN_TS_TLV12TSP_1B58 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B5C_CKGEN00_V004 (CKGEN00_V004 + 0x1B5C)
	#define REG_1B5C_CKGEN00_V004_REG_SW_EN_TS_TLV22TSP_1B5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B60_CKGEN00_V004 (CKGEN00_V004 + 0x1B60)
	#define REG_1B60_CKGEN00_V004_REG_SW_EN_PATH0_27M2TSP_1B60 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B64_CKGEN00_V004 (CKGEN00_V004 + 0x1B64)
	#define REG_1B64_CKGEN00_V004_REG_SW_EN_PATH1_27M2TSP_1B64 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B68_CKGEN00_V004 (CKGEN00_V004 + 0x1B68)
	#define REG_1B68_CKGEN00_V004_REG_SW_EN_PATH2_27M2TSP_1B68 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B6C_CKGEN00_V004 (CKGEN00_V004 + 0x1B6C)
	#define REG_1B6C_CKGEN00_V004_REG_SW_EN_PATH_FI_27M2TSP_1B6C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B78_CKGEN00_V004 (CKGEN00_V004 + 0x1B78)
	#define REG_1B78_CKGEN00_V004_REG_SW_EN_VIVA_AB_MAC_10CH2AB_MAC_10CH_1B78 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B7C_CKGEN00_V004 (CKGEN00_V004 + 0x1B7C)
	#define REG_1B7C_CKGEN00_V004_REG_SW_EN_RIU2EARC_DMACRO_1B7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B80_CKGEN00_V004 (CKGEN00_V004 + 0x1B80)
	#define REG_1B80_CKGEN00_V004_REG_SW_EN_SYNTH_PCM_TRX_256FS2SYNTH_PCM_TRX_256FS_1B80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B90_CKGEN00_V004 (CKGEN00_V004 + 0x1B90)
	#define REG_1B90_CKGEN00_V004_REG_SW_EN_AUSDM_3M2AUSDM_DMACRO_1B90 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B94_CKGEN00_V004 (CKGEN00_V004 + 0x1B94)
	#define REG_1B94_CKGEN00_V004_REG_SW_EN_BCLK_I2S_ENCODER22BCLK_I2S_ENCODER2_1B94 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B98_CKGEN00_V004 (CKGEN00_V004 + 0x1B98)
	#define REG_1B98_CKGEN00_V004_REG_SW_EN_BCLK_I2S_ENCODER2BCLK_I2S_ENCODER_1B98 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1B9C_CKGEN00_V004 (CKGEN00_V004 + 0x1B9C)
	#define REG_1B9C_CKGEN00_V004_REG_SW_EN_EARC_AUDIO2EARC_DMACRO_1B9C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BA0_CKGEN00_V004 (CKGEN00_V004 + 0x1BA0)
	#define REG_1BA0_CKGEN00_V004_REG_SW_EN_VIVA_AB_MAC2AB_MAC_1BA0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BA4_CKGEN00_V004 (CKGEN00_V004 + 0x1BA4)
	#define REG_1BA4_CKGEN00_V004_REG_SW_EN_VIVA_AB3_MAC2AB3_MAC_1BA4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BA8_CKGEN00_V004 (CKGEN00_V004 + 0x1BA8)
	#define REG_1BA8_CKGEN00_V004_REG_SW_EN_VIVA_ADC_512FS2ADC_512_FS_1BA8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BAC_CKGEN00_V004 (CKGEN00_V004 + 0x1BAC)
	#define REG_1BAC_CKGEN00_V004_REG_SW_EN_VIVA_AU_MCU2AU_MCU_1BAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BB0_CKGEN00_V004 (CKGEN00_V004 + 0x1BB0)
	#define REG_1BB0_CKGEN00_V004_REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_256FS_1BB0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BB4_CKGEN00_V004 (CKGEN00_V004 + 0x1BB4)
	#define REG_1BB4_CKGEN00_V004_REG_SW_EN_VIVA_AUDMA_V2_R1_256FS2AUDMA_V2_R1_TIMING_GEN_1BB4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BB8_CKGEN00_V004 (CKGEN00_V004 + 0x1BB8)
	#define REG_1BB8_CKGEN00_V004_REG_SW_EN_VIVA_AUDMA_V2_R1_SYNTH_REF2AUDMA_V2_R1_SYNTH_REF_1BB8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BBC_CKGEN00_V004 (CKGEN00_V004 + 0x1BBC)
	#define REG_1BBC_CKGEN00_V004_REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_256FS_1BBC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC0_CKGEN00_V004 (CKGEN00_V004 + 0x1BC0)
	#define REG_1BC0_CKGEN00_V004_REG_SW_EN_VIVA_AUDMA_V2_R2_256FS2AUDMA_V2_R2_TIMING_GEN_1BC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC4_CKGEN00_V004 (CKGEN00_V004 + 0x1BC4)
	#define REG_1BC4_CKGEN00_V004_REG_SW_EN_VIVA_AUDMA_V2_R2_SYNTH_REF2AUDMA_V2_R2_SYNTH_REF_1BC4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BC8_CKGEN00_V004 (CKGEN00_V004 + 0x1BC8)
	#define REG_1BC8_CKGEN00_V004_REG_SW_EN_VIVA_BCLK_I2S_DECODER22BCLK_I2S_DECODER2_1BC8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BCC_CKGEN00_V004 (CKGEN00_V004 + 0x1BCC)
	#define REG_1BCC_CKGEN00_V004_REG_SW_EN_VIVA_BCLK_I2S_DECODER2BCLK_I2S_DECODER_1BCC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD0_CKGEN00_V004 (CKGEN00_V004 + 0x1BD0)
	#define REG_1BD0_CKGEN00_V004_REG_SW_EN_VIVA_BI2S_SYNTH_REF22I2S_SYNTH_REF2_1BD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD4_CKGEN00_V004 (CKGEN00_V004 + 0x1BD4)
	#define REG_1BD4_CKGEN00_V004_REG_SW_EN_VIVA_CH1_256FSI2CH1_256FSI_1BD4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BD8_CKGEN00_V004 (CKGEN00_V004 + 0x1BD8)
	#define REG_1BD8_CKGEN00_V004_REG_SW_EN_VIVA_CH2_256FSI2CH2_256FSI_1BD8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BDC_CKGEN00_V004 (CKGEN00_V004 + 0x1BDC)
	#define REG_1BDC_CKGEN00_V004_REG_SW_EN_VIVA_CH3_256FSI2CH3_256FSI_1BDC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE0_CKGEN00_V004 (CKGEN00_V004 + 0x1BE0)
	#define REG_1BE0_CKGEN00_V004_REG_SW_EN_VIVA_CH4_256FSI2CH4_256FSI_1BE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE4_CKGEN00_V004 (CKGEN00_V004 + 0x1BE4)
	#define REG_1BE4_CKGEN00_V004_REG_SW_EN_VIVA_CH5_256FSI2CH5_256FSI_1BE4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BE8_CKGEN00_V004 (CKGEN00_V004 + 0x1BE8)
	#define REG_1BE8_CKGEN00_V004_REG_SW_EN_VIVA_CH6_256FSI2CH6_256FSI_1BE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BEC_CKGEN00_V004 (CKGEN00_V004 + 0x1BEC)
	#define REG_1BEC_CKGEN00_V004_REG_SW_EN_VIVA_CH7_256FSI2CH7_256FSI_1BEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF0_CKGEN00_V004 (CKGEN00_V004 + 0x1BF0)
	#define REG_1BF0_CKGEN00_V004_REG_SW_EN_VIVA_CH8_256FSI2CH8_256FSI_1BF0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF4_CKGEN00_V004 (CKGEN00_V004 + 0x1BF4)
	#define REG_1BF4_CKGEN00_V004_REG_SW_EN_VIVA_CH9_256FSI2CH9_256FSI_1BF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BF8_CKGEN00_V004 (CKGEN00_V004 + 0x1BF8)
	#define REG_1BF8_CKGEN00_V004_REG_SW_EN_VIVA_CODEC_SH2CODEC_SH_1BF8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1BFC_CKGEN00_V004 (CKGEN00_V004 + 0x1BFC)
	#define REG_1BFC_CKGEN00_V004_REG_SW_EN_VIVA_DAC_512FS2DAC_512_FS_1BFC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C00_CKGEN00_V004 (CKGEN00_V004 + 0x1C00)
	#define REG_1C00_CKGEN00_V004_REG_SW_EN_VIVA_DSP2DSP_230_1C00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C04_CKGEN00_V004 (CKGEN00_V004 + 0x1C04)
	#define REG_1C04_CKGEN00_V004_REG_SW_EN_VIVA_DSP2DSP_230_1_1C04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C08_CKGEN00_V004 (CKGEN00_V004 + 0x1C08)
	#define REG_1C08_CKGEN00_V004_REG_SW_EN_VIVA_DSP2DSP_230_2_1C08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C0C_CKGEN00_V004 (CKGEN00_V004 + 0x1C0C)
	#define REG_1C0C_CKGEN00_V004_REG_SW_EN_VIVA_DSP2DSP_230_3_1C0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C10_CKGEN00_V004 (CKGEN00_V004 + 0x1C10)
	#define REG_1C10_CKGEN00_V004_REG_SW_EN_VIVA_DSP2DSP_230_DFS_REF_1C10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C14_CKGEN00_V004 (CKGEN00_V004 + 0x1C14)
	#define REG_1C14_CKGEN00_V004_REG_SW_EN_VIVA_DSP2DSP_230_TM_1C14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C18_CKGEN00_V004 (CKGEN00_V004 + 0x1C18)
	#define REG_1C18_CKGEN00_V004_REG_SW_EN_VIVA_DVB1_SYNTH_REF2DVB1_SYNTH_REF_1C18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C1C_CKGEN00_V004 (CKGEN00_V004 + 0x1C1C)
	#define REG_1C1C_CKGEN00_V004_REG_SW_EN_VIVA_DVB1_TIMING_GEN_256FS2DVB1_TIMING_GEN_256FS_1C1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C20_CKGEN00_V004 (CKGEN00_V004 + 0x1C20)
	#define REG_1C20_CKGEN00_V004_REG_SW_EN_VIVA_DVB2_SYNTH_REF2DVB2_SYNTH_REF_1C20 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C24_CKGEN00_V004 (CKGEN00_V004 + 0x1C24)
	#define REG_1C24_CKGEN00_V004_REG_SW_EN_VIVA_DVB2_TIMING_GEN_256FS2DVB2_TIMING_GEN_256FS_1C24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C28_CKGEN00_V004 (CKGEN00_V004 + 0x1C28)
	#define REG_1C28_CKGEN00_V004_REG_SW_EN_VIVA_DVB3_SYNTH_REF2DVB3_SYNTH_REF_1C28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C2C_CKGEN00_V004 (CKGEN00_V004 + 0x1C2C)
	#define REG_1C2C_CKGEN00_V004_REG_SW_EN_VIVA_DVB3_TIMING_GEN_256FS2DVB3_TIMING_GEN_256FS_1C2C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C30_CKGEN00_V004 (CKGEN00_V004 + 0x1C30)
	#define REG_1C30_CKGEN00_V004_REG_SW_EN_VIVA_DVB4_SYNTH_REF2DVB4_SYNTH_REF_1C30 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C34_CKGEN00_V004 (CKGEN00_V004 + 0x1C34)
	#define REG_1C34_CKGEN00_V004_REG_SW_EN_VIVA_DVB4_TIMING_GEN_256FS2DVB4_TIMING_GEN_256FS_1C34 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C38_CKGEN00_V004 (CKGEN00_V004 + 0x1C38)
	#define REG_1C38_CKGEN00_V004_REG_SW_EN_VIVA_DVB5_TIMING_GEN_256FS2DVB5_TIMING_GEN_256FS_1C38 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C3C_CKGEN00_V004 (CKGEN00_V004 + 0x1C3C)
	#define REG_1C3C_CKGEN00_V004_REG_SW_EN_VIVA_DVB6_TIMING_GEN_256FS2DVB6_TIMING_GEN_256FS_1C3C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C40_CKGEN00_V004 (CKGEN00_V004 + 0x1C40)
	#define REG_1C40_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_32XCHXFS2EARC_TX_32XCHXFS_1C40 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C44_CKGEN00_V004 (CKGEN00_V004 + 0x1C44)
	#define REG_1C44_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_32XFS2EARC_TX_32XFS_1C44 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C48_CKGEN00_V004 (CKGEN00_V004 + 0x1C48)
	#define REG_1C48_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_64XCHXFS2EARC_TX_64XCHXFS_1C48 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C4C_CKGEN00_V004 (CKGEN00_V004 + 0x1C4C)
	#define REG_1C4C_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_GPA_SYNTH_REF2EARC_TX_GPA_SYNTH_REF_1C4C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C50_CKGEN00_V004 (CKGEN00_V004 + 0x1C50)
	#define REG_1C50_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_PLL2EARC_TX_PLL_1C50 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C54_CKGEN00_V004 (CKGEN00_V004 + 0x1C54)
	#define REG_1C54_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_SOURCE_256FS2EARC_TX_SOURCE_256FS_1C54 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C58_CKGEN00_V004 (CKGEN00_V004 + 0x1C58)
	#define REG_1C58_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_SYNTH_IIR_REF2EARC_TX_SYNTH_IIR_REF_1C58 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C5C_CKGEN00_V004 (CKGEN00_V004 + 0x1C5C)
	#define REG_1C5C_CKGEN00_V004_REG_SW_EN_VIVA_EARC_TX_SYNTH_REF2EARC_TX_SYNTH_REF_1C5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C60_CKGEN00_V004 (CKGEN00_V004 + 0x1C60)
	#define REG_1C60_CKGEN00_V004_REG_SW_EN_VIVA_FM_DEMODULATOR2FM_DEMODULATOR_1C60 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C64_CKGEN00_V004 (CKGEN00_V004 + 0x1C64)
	#define REG_1C64_CKGEN00_V004_REG_SW_EN_VIVA_GPA_240FSO2GPA_240FSO_1C64 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C68_CKGEN00_V004 (CKGEN00_V004 + 0x1C68)
	#define REG_1C68_CKGEN00_V004_REG_SW_EN_VIVA_GPA_256FSO2GPA_256FSO_1C68 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C6C_CKGEN00_V004 (CKGEN00_V004 + 0x1C6C)
	#define REG_1C6C_CKGEN00_V004_REG_SW_EN_VIVA_GPA_480FSO2GPA_480FSO_1C6C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C70_CKGEN00_V004 (CKGEN00_V004 + 0x1C70)
	#define REG_1C70_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX_MPLL_4322HDMI_RX_MPLL_432_1C70 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C74_CKGEN00_V004 (CKGEN00_V004 + 0x1C74)
	#define REG_1C74_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX_S2P_128FS2HDMI_RX_S2P_128FS_1C74 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C78_CKGEN00_V004 (CKGEN00_V004 + 0x1C78)
	#define REG_1C78_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX_S2P_256FS2HDMI_RX_S2P_256FS_1C78 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C7C_CKGEN00_V004 (CKGEN00_V004 + 0x1C7C)
	#define REG_1C7C_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX_SYNTH_REF2HDMI_RX_SYNTH_REF_1C7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C80_CKGEN00_V004 (CKGEN00_V004 + 0x1C80)
	#define REG_1C80_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX_V2A_TIME_STAMP2HDMI_RX_V2A_TIME_STAMP_1C80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C84_CKGEN00_V004 (CKGEN00_V004 + 0x1C84)
	#define REG_1C84_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX2_MPLL_4322HDMI_RX2_MPLL_432_1C84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C88_CKGEN00_V004 (CKGEN00_V004 + 0x1C88)
	#define REG_1C88_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX2_S2P_128FS2HDMI_RX2_S2P_128FS_1C88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C8C_CKGEN00_V004 (CKGEN00_V004 + 0x1C8C)
	#define REG_1C8C_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX2_S2P_256FS2HDMI_RX2_S2P_256FS_1C8C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C90_CKGEN00_V004 (CKGEN00_V004 + 0x1C90)
	#define REG_1C90_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX2_SYNTH_REF2HDMI_RX2_SYNTH_REF_1C90 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C94_CKGEN00_V004 (CKGEN00_V004 + 0x1C94)
	#define REG_1C94_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_RX2_V2A_TIME_STAMP2HDMI_RX2_V2A_TIME_STAMP_1C94 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C98_CKGEN00_V004 (CKGEN00_V004 + 0x1C98)
	#define REG_1C98_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_TX_128FS2HDMI_TX_128FS_1C98 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1C9C_CKGEN00_V004 (CKGEN00_V004 + 0x1C9C)
	#define REG_1C9C_CKGEN00_V004_REG_SW_EN_VIVA_HDMI_TX_256FS2HDMI_TX_256FS_1C9C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA0_CKGEN00_V004 (CKGEN00_V004 + 0x1CA0)
	#define REG_1CA0_CKGEN00_V004_REG_SW_EN_VIVA_I2S_2_BCLK_SYNTH_REF2I2S_2_BCLK_SYNTH_REF_1CA0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA4_CKGEN00_V004 (CKGEN00_V004 + 0x1CA4)
	#define REG_1CA4_CKGEN00_V004_REG_SW_EN_VIVA_I2S_BCLK_DG22I2S_BCLK_DG2_1CA4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CA8_CKGEN00_V004 (CKGEN00_V004 + 0x1CA8)
	#define REG_1CA8_CKGEN00_V004_REG_SW_EN_VIVA_I2S_BCLK_DG2I2S_BCLK_DG_1CA8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CAC_CKGEN00_V004 (CKGEN00_V004 + 0x1CAC)
	#define REG_1CAC_CKGEN00_V004_REG_SW_EN_VIVA_I2S_BCLK_SYNTH_REF2I2S_BCLK_SYNTH_REF_1CAC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB0_CKGEN00_V004 (CKGEN00_V004 + 0x1CB0)
	#define REG_1CB0_CKGEN00_V004_REG_SW_EN_VIVA_I2S_MCLK_SYNTH_REF2I2S_MCLK_SYNTH_REF_1CB0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB4_CKGEN00_V004 (CKGEN00_V004 + 0x1CB4)
	#define REG_1CB4_CKGEN00_V004_REG_SW_EN_VIVA_I2S_SYNTH_REF2I2S_SYNTH_REF_1CB4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CB8_CKGEN00_V004 (CKGEN00_V004 + 0x1CB8)
	#define REG_1CB8_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TRX_BCLK_TIMING_GEN2I2S_TRX_BCLK_TIMING_GEN_1CB8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CBC_CKGEN00_V004 (CKGEN00_V004 + 0x1CBC)
	#define REG_1CBC_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TRX_SYNTH_REF2I2S_TRX_SYNTH_REF_1CBC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC0_CKGEN00_V004 (CKGEN00_V004 + 0x1CC0)
	#define REG_1CC0_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TX_FIFO_256FS2I2S_TX_FIFO_256FS_1CC0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC4_CKGEN00_V004 (CKGEN00_V004 + 0x1CC4)
	#define REG_1CC4_CKGEN00_V004_REG_SW_EN_VIVA_MCLK_I2S_DECODER22MCLK_I2S_DECODER2_1CC4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CC8_CKGEN00_V004 (CKGEN00_V004 + 0x1CC8)
	#define REG_1CC8_CKGEN00_V004_REG_SW_EN_VIVA_MCLK_I2S_DECODER2MCLK_I2S_DECODER_1CC8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CCC_CKGEN00_V004 (CKGEN00_V004 + 0x1CCC)
	#define REG_1CCC_CKGEN00_V004_REG_SW_EN_VIVA_NPCM_SYNTH_REF2NPCM_SYNTH_REF_1CCC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD0_CKGEN00_V004 (CKGEN00_V004 + 0x1CD0)
	#define REG_1CD0_CKGEN00_V004_REG_SW_EN_VIVA_NPCM2_SYNTH_REF2NPCM2_SYNTH_REF_1CD0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD4_CKGEN00_V004 (CKGEN00_V004 + 0x1CD4)
	#define REG_1CD4_CKGEN00_V004_REG_SW_EN_VIVA_NPCM3_SYNTH_REF2NPCM3_SYNTH_REF_1CD4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CD8_CKGEN00_V004 (CKGEN00_V004 + 0x1CD8)
	#define REG_1CD8_CKGEN00_V004_REG_SW_EN_VIVA_NPCM4_256FS_TIMING_GEN2NPCM4_256FS_TIMING_GEN_1CD8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CDC_CKGEN00_V004 (CKGEN00_V004 + 0x1CDC)
	#define REG_1CDC_CKGEN00_V004_REG_SW_EN_VIVA_NPCM4_SYNTH_REF2NPCM4_SYNTH_REF_1CDC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE0_CKGEN00_V004 (CKGEN00_V004 + 0x1CE0)
	#define REG_1CE0_CKGEN00_V004_REG_SW_EN_VIVA_NPCM5_256FS_TIMING_GEN2NPCM5_256FS_TIMING_GEN_1CE0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE4_CKGEN00_V004 (CKGEN00_V004 + 0x1CE4)
	#define REG_1CE4_CKGEN00_V004_REG_SW_EN_VIVA_NPCM5_SYNTH_REF2NPCM5_SYNTH_REF_1CE4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CE8_CKGEN00_V004 (CKGEN00_V004 + 0x1CE8)
	#define REG_1CE8_CKGEN00_V004_REG_SW_EN_VIVA_PCM_CLK_2162PCM_CLK_216_1CE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CEC_CKGEN00_V004 (CKGEN00_V004 + 0x1CEC)
	#define REG_1CEC_CKGEN00_V004_REG_SW_EN_VIVA_PCM_CLK_AUPLL2PCM_CLK_AUPLL_1CEC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF0_CKGEN00_V004 (CKGEN00_V004 + 0x1CF0)
	#define REG_1CF0_CKGEN00_V004_REG_SW_EN_VIVA_R2_WB2R2_WB_1CF0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF4_CKGEN00_V004 (CKGEN00_V004 + 0x1CF4)
	#define REG_1CF4_CKGEN00_V004_REG_SW_EN_VIVA_RIU_BRG_R22R2_RIU_BRG_1CF4 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CF8_CKGEN00_V004 (CKGEN00_V004 + 0x1CF8)
	#define REG_1CF8_CKGEN00_V004_REG_SW_EN_VIVA_RIU_R22RIU_R2_1CF8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1CFC_CKGEN00_V004 (CKGEN00_V004 + 0x1CFC)
	#define REG_1CFC_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH1_SH_1CFC Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D00_CKGEN00_V004 (CKGEN00_V004 + 0x1D00)
	#define REG_1D00_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH2_SH_1D00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D04_CKGEN00_V004 (CKGEN00_V004 + 0x1D04)
	#define REG_1D04_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH3_SH_1D04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D08_CKGEN00_V004 (CKGEN00_V004 + 0x1D08)
	#define REG_1D08_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH4_SH_1D08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D0C_CKGEN00_V004 (CKGEN00_V004 + 0x1D0C)
	#define REG_1D0C_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH5_SH_1D0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D10_CKGEN00_V004 (CKGEN00_V004 + 0x1D10)
	#define REG_1D10_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH6_SH_1D10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D14_CKGEN00_V004 (CKGEN00_V004 + 0x1D14)
	#define REG_1D14_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH7_SH_1D14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D18_CKGEN00_V004 (CKGEN00_V004 + 0x1D18)
	#define REG_1D18_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH8_SH_1D18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D1C_CKGEN00_V004 (CKGEN00_V004 + 0x1D1C)
	#define REG_1D1C_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH9_SH_1D1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D20_CKGEN00_V004 (CKGEN00_V004 + 0x1D20)
	#define REG_1D20_CKGEN00_V004_REG_SW_EN_VIVA_SIF_ADC_CIC2SIF_ADC_CIC_1D20 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D24_CKGEN00_V004 (CKGEN00_V004 + 0x1D24)
	#define REG_1D24_CKGEN00_V004_REG_SW_EN_VIVA_SIF_ADC_R2B_FIFO_IN2SIF_ADC_R2B_FIFO_IN_1D24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D28_CKGEN00_V004 (CKGEN00_V004 + 0x1D28)
	#define REG_1D28_CKGEN00_V004_REG_SW_EN_VIVA_SIF_ADC_R2B2SIF_ADC_R2B_1D28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D2C_CKGEN00_V004 (CKGEN00_V004 + 0x1D2C)
	#define REG_1D2C_CKGEN00_V004_REG_SW_EN_VIVA_SIF_CORDIC2SIF_CORDIC_1D2C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D30_CKGEN00_V004 (CKGEN00_V004 + 0x1D30)
	#define REG_1D30_CKGEN00_V004_REG_SW_EN_VIVA_SIF_SYNTH2SIF_SYNTH_1D30 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D34_CKGEN00_V004 (CKGEN00_V004 + 0x1D34)
	#define REG_1D34_CKGEN00_V004_REG_SW_EN_VIVA_SIN_GEN2SIN_GEN_1D34 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D38_CKGEN00_V004 (CKGEN00_V004 + 0x1D38)
	#define REG_1D38_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_RX_128FS2SPDIF_RX_128FS_1D38 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D3C_CKGEN00_V004 (CKGEN00_V004 + 0x1D3C)
	#define REG_1D3C_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_RX_DG2SPDIF_RX_DG_1D3C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D40_CKGEN00_V004 (CKGEN00_V004 + 0x1D40)
	#define REG_1D40_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_RX_SYNTH_REF2SPDIF_RX_SYNTH_REF_1D40 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D44_CKGEN00_V004 (CKGEN00_V004 + 0x1D44)
	#define REG_1D44_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_TX_128FS2SPDIF_TX_128FS_1D44 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D48_CKGEN00_V004 (CKGEN00_V004 + 0x1D48)
	#define REG_1D48_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_TX_256FS2SPDIF_TX_256FS_1D48 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D4C_CKGEN00_V004 (CKGEN00_V004 + 0x1D4C)
	#define REG_1D4C_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_TX_SYNTH_REF2SPDIF_TX_SYNTH_REF_1D4C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D50_CKGEN00_V004 (CKGEN00_V004 + 0x1D50)
	#define REG_1D50_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_TX2_128FS2SPDIF_TX2_128FS_1D50 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D54_CKGEN00_V004 (CKGEN00_V004 + 0x1D54)
	#define REG_1D54_CKGEN00_V004_REG_SW_EN_VIVA_SPDIF_TX2_256FS2SPDIF_TX2_256FS_1D54 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D58_CKGEN00_V004 (CKGEN00_V004 + 0x1D58)
	#define REG_1D58_CKGEN00_V004_REG_SW_EN_VIVA_SYNTH_2ND_ORDER2SYNTH_2ND_ORDER_1D58 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D5C_CKGEN00_V004 (CKGEN00_V004 + 0x1D5C)
	#define REG_1D5C_CKGEN00_V004_REG_SW_EN_VIVA_SYNTH_CODEC2SYNTH_CODEC_1D5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D60_CKGEN00_V004 (CKGEN00_V004 + 0x1D60)
	#define REG_1D60_CKGEN00_V004_REG_SW_EN_VIVA_TEST_BUS2TEST_BUS_1D60 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D64_CKGEN00_V004 (CKGEN00_V004 + 0x1D64)
	#define REG_1D64_CKGEN00_V004_REG_SW_EN_VIVA_VBDMA_MCU2VBDMA_MCU_1D64 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D68_CKGEN00_V004 (CKGEN00_V004 + 0x1D68)
	#define REG_1D68_CKGEN00_V004_REG_SW_EN_VIVA_XTAL_12M2XTAL_1D68 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D6C_CKGEN00_V004 (CKGEN00_V004 + 0x1D6C)
	#define REG_1D6C_CKGEN00_V004_REG_SW_EN_VIVA_XTAL_24M2XTAL_1D6C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D7C_CKGEN00_V004 (CKGEN00_V004 + 0x1D7C)
	#define REG_1D7C_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TX_2_FIFO_256FS2I2S_TX_2_FIFO_256FS_1D7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D80_CKGEN00_V004 (CKGEN00_V004 + 0x1D80)
	#define REG_1D80_CKGEN00_V004_REG_SW_EN_RV_AUDEC2AUDEC_1D80 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1D80_CKGEN00_V004_REG_SW_EN_RV_AUDEC2AUDECDFS_1D80 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1D80_CKGEN00_V004_REG_SW_EN_RV_AUSND2AUSND_1D80 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_1D80_CKGEN00_V004_REG_SW_EN_RV_AUSND2AUSNDDFS_1D80 Fld(1,3,AC_MSKB0)//[3:3]
#define REG_1D88_CKGEN00_V004 (CKGEN00_V004 + 0x1D88)
	#define REG_1D88_CKGEN00_V004_REG_SW_EN_TCK_AUDAP2AUDAP_1D88 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1D88_CKGEN00_V004_REG_SW_EN_TCK_AUDEC2AUDEC_1D88 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_1D88_CKGEN00_V004_REG_SW_EN_TCK_AUSND2AUSND_1D88 Fld(1,2,AC_MSKB0)//[2:2]
#define REG_1D90_CKGEN00_V004 (CKGEN00_V004 + 0x1D90)
	#define REG_1D90_CKGEN00_V004_REG_SW_EN_GPD2GPD_1D90 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1D94_CKGEN00_V004 (CKGEN00_V004 + 0x1D94)
	#define REG_1D94_CKGEN00_V004_REG_SW_EN_ZDEC_LZD2ZDEC_1D94 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1D94_CKGEN00_V004_REG_SW_EN_ZDEC_VLD2ZDEC_1D94 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1D98_CKGEN00_V004 (CKGEN00_V004 + 0x1D98)
	#define REG_1D98_CKGEN00_V004_REG_SW_EN_NJPD2JPD_1D98 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1DA0_CKGEN00_V004 (CKGEN00_V004 + 0x1DA0)
	#define REG_1DA0_CKGEN00_V004_REG_SW_EN_VDEC_BUS2CORE0_1DA0 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1DAC_CKGEN00_V004 (CKGEN00_V004 + 0x1DAC)
	#define REG_1DAC_CKGEN00_V004_REG_SW_EN_VDEC_SYS2CORE0_1DAC Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1DB0_CKGEN00_V004 (CKGEN00_V004 + 0x1DB0)
	#define REG_1DB0_CKGEN00_V004_REG_SW_EN_XTAL_24M2CORE0_1DB0 Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1E00_CKGEN00_V004 (CKGEN00_V004 + 0x1E00)
	#define REG_1E00_CKGEN00_V004_REG_SW_EN_VIVA_CH10_256FSI2CH10_256FSI_1E00 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E04_CKGEN00_V004 (CKGEN00_V004 + 0x1E04)
	#define REG_1E04_CKGEN00_V004_REG_SW_EN_VIVA_CH_M1_256FSI2CH_M1_256FSI_1E04 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E08_CKGEN00_V004 (CKGEN00_V004 + 0x1E08)
	#define REG_1E08_CKGEN00_V004_REG_SW_EN_VIVA_CH_M2_256FSI2CH_M2_256FSI_1E08 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E0C_CKGEN00_V004 (CKGEN00_V004 + 0x1E0C)
	#define REG_1E0C_CKGEN00_V004_REG_SW_EN_VIVA_CH_M3_256FSI2CH_M3_256FSI_1E0C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E10_CKGEN00_V004 (CKGEN00_V004 + 0x1E10)
	#define REG_1E10_CKGEN00_V004_REG_SW_EN_VIVA_CH_M4_256FSI2CH_M4_256FSI_1E10 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E14_CKGEN00_V004 (CKGEN00_V004 + 0x1E14)
	#define REG_1E14_CKGEN00_V004_REG_SW_EN_VIVA_CH_M5_256FSI2CH_M5_256FSI_1E14 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E18_CKGEN00_V004 (CKGEN00_V004 + 0x1E18)
	#define REG_1E18_CKGEN00_V004_REG_SW_EN_VIVA_CH_M6_256FSI2CH_M6_256FSI_1E18 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E1C_CKGEN00_V004 (CKGEN00_V004 + 0x1E1C)
	#define REG_1E1C_CKGEN00_V004_REG_SW_EN_VIVA_CH_M7_256FSI2CH_M7_256FSI_1E1C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E20_CKGEN00_V004 (CKGEN00_V004 + 0x1E20)
	#define REG_1E20_CKGEN00_V004_REG_SW_EN_VIVA_CH_M8_256FSI2CH_M8_256FSI_1E20 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E24_CKGEN00_V004 (CKGEN00_V004 + 0x1E24)
	#define REG_1E24_CKGEN00_V004_REG_SW_EN_VIVA_CH_M9_256FSI2CH_M9_256FSI_1E24 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E28_CKGEN00_V004 (CKGEN00_V004 + 0x1E28)
	#define REG_1E28_CKGEN00_V004_REG_SW_EN_VIVA_CH_M10_256FSI2CH_M10_256FSI_1E28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E2C_CKGEN00_V004 (CKGEN00_V004 + 0x1E2C)
	#define REG_1E2C_CKGEN00_V004_REG_SW_EN_VIVA_CH_M11_256FSI2CH_M11_256FSI_1E2C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E30_CKGEN00_V004 (CKGEN00_V004 + 0x1E30)
	#define REG_1E30_CKGEN00_V004_REG_SW_EN_VIVA_CH_M12_256FSI2CH_M12_256FSI_1E30 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E34_CKGEN00_V004 (CKGEN00_V004 + 0x1E34)
	#define REG_1E34_CKGEN00_V004_REG_SW_EN_VIVA_CH_M13_256FSI2CH_M13_256FSI_1E34 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E38_CKGEN00_V004 (CKGEN00_V004 + 0x1E38)
	#define REG_1E38_CKGEN00_V004_REG_SW_EN_VIVA_CH_M14_256FSI2CH_M14_256FSI_1E38 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E3C_CKGEN00_V004 (CKGEN00_V004 + 0x1E3C)
	#define REG_1E3C_CKGEN00_V004_REG_SW_EN_VIVA_CH_M15_256FSI2CH_M15_256FSI_1E3C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E40_CKGEN00_V004 (CKGEN00_V004 + 0x1E40)
	#define REG_1E40_CKGEN00_V004_REG_SW_EN_VIVA_CH_M16_256FSI2CH_M16_256FSI_1E40 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E44_CKGEN00_V004 (CKGEN00_V004 + 0x1E44)
	#define REG_1E44_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_BCLK2VIVA_I2S_TDM_1X16TX32B_BCLK_1E44 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E48_CKGEN00_V004 (CKGEN00_V004 + 0x1E48)
	#define REG_1E48_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TDM_1X16TX32B_FIFO2VIVA_I2S_TDM_1X16TX32B_FIFO_1E48 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E4C_CKGEN00_V004 (CKGEN00_V004 + 0x1E4C)
	#define REG_1E4C_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_BCLK2I2S_TDM_6X16TX32B_BCLK_1E4C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E50_CKGEN00_V004 (CKGEN00_V004 + 0x1E50)
	#define REG_1E50_CKGEN00_V004_REG_SW_EN_VIVA_I2S_TDM_6X16TX32B_FIFO2VIVA_I2S_TDM_6X16TX32B_FIFO_1E50 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E54_CKGEN00_V004 (CKGEN00_V004 + 0x1E54)
	#define REG_1E54_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH10_SH_1E54 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E58_CKGEN00_V004 (CKGEN00_V004 + 0x1E58)
	#define REG_1E58_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M1_SH_1E58 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E5C_CKGEN00_V004 (CKGEN00_V004 + 0x1E5C)
	#define REG_1E5C_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M2_SH_1E5C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E60_CKGEN00_V004 (CKGEN00_V004 + 0x1E60)
	#define REG_1E60_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M3_SH_1E60 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E64_CKGEN00_V004 (CKGEN00_V004 + 0x1E64)
	#define REG_1E64_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M4_SH_1E64 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E68_CKGEN00_V004 (CKGEN00_V004 + 0x1E68)
	#define REG_1E68_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M5_SH_1E68 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E6C_CKGEN00_V004 (CKGEN00_V004 + 0x1E6C)
	#define REG_1E6C_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M6_SH_1E6C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E70_CKGEN00_V004 (CKGEN00_V004 + 0x1E70)
	#define REG_1E70_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M7_SH_1E70 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E74_CKGEN00_V004 (CKGEN00_V004 + 0x1E74)
	#define REG_1E74_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M8_SH_1E74 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E78_CKGEN00_V004 (CKGEN00_V004 + 0x1E78)
	#define REG_1E78_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M9_SH_1E78 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E7C_CKGEN00_V004 (CKGEN00_V004 + 0x1E7C)
	#define REG_1E7C_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M10_SH_1E7C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E80_CKGEN00_V004 (CKGEN00_V004 + 0x1E80)
	#define REG_1E80_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M11_SH_1E80 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E84_CKGEN00_V004 (CKGEN00_V004 + 0x1E84)
	#define REG_1E84_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M12_SH_1E84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E88_CKGEN00_V004 (CKGEN00_V004 + 0x1E88)
	#define REG_1E88_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M13_SH_1E88 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E8C_CKGEN00_V004 (CKGEN00_V004 + 0x1E8C)
	#define REG_1E8C_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M14_SH_1E8C Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E90_CKGEN00_V004 (CKGEN00_V004 + 0x1E90)
	#define REG_1E90_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M15_SH_1E90 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E94_CKGEN00_V004 (CKGEN00_V004 + 0x1E94)
	#define REG_1E94_CKGEN00_V004_REG_SW_EN_VIVA_SH2CH_M16_SH_1E94 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E98_CKGEN00_V004 (CKGEN00_V004 + 0x1E98)
	#define REG_1E98_CKGEN00_V004_REG_SW_EN_VIVA_SRC_MAC_BSPLINE2SRC_MAC_BSPLINE_1E98 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1E9C_CKGEN00_V004 (CKGEN00_V004 + 0x1E9C)
	#define REG_1E9C_CKGEN00_V004_REG_SW_EN_DAP2VIVA_RV55AUDIO_DAP_1E9C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1E9C_CKGEN00_V004_REG_SW_EN_DAP_TCK2VIVA_RV55AUDIO_DAP_TCK_1E9C Fld(1,1,AC_MSKB0)//[1:1]
#define REG_1EC0_CKGEN00_V004 (CKGEN00_V004 + 0x1EC0)
	#define REG_1EC0_CKGEN00_V004_REG_PD_SYS3PLL_1EC0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EC0_CKGEN00_V004_REG_PD_SYS3PLL_CLK_DIV2P5_1EC0 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1EC0_CKGEN00_V004_REG_PD_SYS3PLL_CLK_DIV2_1EC0 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1EC0_CKGEN00_V004_REG_PD_SYS3PLL_CLK_DIV3_1EC0 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1EC4_CKGEN00_V004 (CKGEN00_V004 + 0x1EC4)
	#define REG_1EC4_CKGEN00_V004_REG_PD_SYS3PLL_CLK_DIV5_1EC4 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EC4_CKGEN00_V004_REG_PD_SYS3PLL_POSTDIV_1EC4 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1EC4_CKGEN00_V004_REG_PD_SYS3PLL_CLK_DIV30_1EC4 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1EC8_CKGEN00_V004 (CKGEN00_V004 + 0x1EC8)
	#define REG_1EC8_CKGEN00_V004_REG_EN_SYS3PLL_VCO_DIV3_1EC8 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1EC8_CKGEN00_V004_REG_EN_SYS3PLL_OCC_DIV128_1EC8 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1EC8_CKGEN00_V004_REG_EN_SYS3PLL_XTAL_1EC8 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1EC8_CKGEN00_V004_REG_EN_SYS3PLL_TEST_1EC8 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1ECC_CKGEN00_V004 (CKGEN00_V004 + 0x1ECC)
	#define REG_1ECC_CKGEN00_V004_REG_EN_SYS3PLL_PRDT_1ECC Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1ECC_CKGEN00_V004_REG_EN_SYS3PLL_RST_1ECC Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1ED0_CKGEN00_V004 (CKGEN00_V004 + 0x1ED0)
	#define REG_1ED0_CKGEN00_V004_REG_GC_SYS3PLL_INPUT_DIV_1ED0 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1ED4_CKGEN00_V004 (CKGEN00_V004 + 0x1ED4)
	#define REG_1ED4_CKGEN00_V004_REG_GC_SYS3PLL_CP_SW_1ED4 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_1ED4_CKGEN00_V004_REG_GC_SYS3PLL_ICTRL_1ED4 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1ED8_CKGEN00_V004 (CKGEN00_V004 + 0x1ED8)
	#define REG_1ED8_CKGEN00_V004_REG_GC_SYS3PLL_OUTPUT_DIV_FIRST_1ED8 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_1ED8_CKGEN00_V004_REG_GC_SYS3PLL_OUTPUT_DIV_1ED8 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1EDC_CKGEN00_V004 (CKGEN00_V004 + 0x1EDC)
	#define REG_1EDC_CKGEN00_V004_REG_GC_SYS3PLL_LOOPDIV_FIRST_1EDC Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1EE0_CKGEN00_V004 (CKGEN00_V004 + 0x1EE0)
	#define REG_1EE0_CKGEN00_V004_REG_GC_SYS3PLL_LOOPDIV_SECOND_1EE0 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_1EE8_CKGEN00_V004 (CKGEN00_V004 + 0x1EE8)
	#define REG_1EE8_CKGEN00_V004_REG_RO_SYS3PLL_LOCK_1EE8 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1EF8_CKGEN00_V004 (CKGEN00_V004 + 0x1EF8)
	#define REG_1EF8_CKGEN00_V004_REG_TEST_SYS3PLL_1EF8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F00_CKGEN00_V004 (CKGEN00_V004 + 0x1F00)
	#define REG_1F00_CKGEN00_V004_REG_PD_GPUBRDGPLL_1F00 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F00_CKGEN00_V004_REG_PD_GPUBRDGPLL_CLK_DIV2P5_1F00 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F00_CKGEN00_V004_REG_PD_GPUBRDGPLL_CLK_DIV2_1F00 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F00_CKGEN00_V004_REG_PD_GPUBRDGPLL_CLK_DIV3_1F00 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1F04_CKGEN00_V004 (CKGEN00_V004 + 0x1F04)
	#define REG_1F04_CKGEN00_V004_REG_PD_GPUBRDGPLL_CLK_DIV5_1F04 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F04_CKGEN00_V004_REG_PD_GPUBRDGPLL_POSTDIV_1F04 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F04_CKGEN00_V004_REG_PD_GPUBRDGPLL_CLK_DIV30_1F04 Fld(1,8,AC_MSKB1)//[8:8]
#define REG_1F08_CKGEN00_V004 (CKGEN00_V004 + 0x1F08)
	#define REG_1F08_CKGEN00_V004_REG_EN_GPUBRDGPLL_VCO_DIV3_1F08 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F08_CKGEN00_V004_REG_EN_GPUBRDGPLL_OCC_DIV128_1F08 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_1F08_CKGEN00_V004_REG_EN_GPUBRDGPLL_XTAL_1F08 Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_1F08_CKGEN00_V004_REG_EN_GPUBRDGPLL_TEST_1F08 Fld(1,12,AC_MSKB1)//[12:12]
#define REG_1F0C_CKGEN00_V004 (CKGEN00_V004 + 0x1F0C)
	#define REG_1F0C_CKGEN00_V004_REG_EN_GPUBRDGPLL_PRDT_1F0C Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1F0C_CKGEN00_V004_REG_EN_GPUBRDGPLL_RST_1F0C Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1F10_CKGEN00_V004 (CKGEN00_V004 + 0x1F10)
	#define REG_1F10_CKGEN00_V004_REG_GC_GPUBRDGPLL_INPUT_DIV_1F10 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1F14_CKGEN00_V004 (CKGEN00_V004 + 0x1F14)
	#define REG_1F14_CKGEN00_V004_REG_GC_GPUBRDGPLL_CP_SW_1F14 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_1F14_CKGEN00_V004_REG_GC_GPUBRDGPLL_ICTRL_1F14 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1F18_CKGEN00_V004 (CKGEN00_V004 + 0x1F18)
	#define REG_1F18_CKGEN00_V004_REG_GC_GPUBRDGPLL_OUTPUT_DIV_FIRST_1F18 Fld(2,0,AC_MSKB0)//[1:0]
	#define REG_1F18_CKGEN00_V004_REG_GC_GPUBRDGPLL_OUTPUT_DIV_1F18 Fld(3,8,AC_MSKB1)//[10:8]
#define REG_1F1C_CKGEN00_V004 (CKGEN00_V004 + 0x1F1C)
	#define REG_1F1C_CKGEN00_V004_REG_GC_GPUBRDGPLL_LOOPDIV_FIRST_1F1C Fld(2,0,AC_MSKB0)//[1:0]
#define REG_1F20_CKGEN00_V004 (CKGEN00_V004 + 0x1F20)
	#define REG_1F20_CKGEN00_V004_REG_GC_GPUBRDGPLL_LOOPDIV_SECOND_1F20 Fld(8,0,AC_FULLB0)//[7:0]
#define REG_1F28_CKGEN00_V004 (CKGEN00_V004 + 0x1F28)
	#define REG_1F28_CKGEN00_V004_REG_RO_GPUBRDGPLL_LOCK_1F28 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F38_CKGEN00_V004 (CKGEN00_V004 + 0x1F38)
	#define REG_1F38_CKGEN00_V004_REG_TEST_GPUBRDGPLL_1F38 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1F80_CKGEN00_V004 (CKGEN00_V004 + 0x1F80)
	#define REG_1F80_CKGEN00_V004_REG_CKG_DVBTM_TS_DIVNUM_1F80 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_1F80_CKGEN00_V004_REG_CKG_ATSC_DVB_DIV_SEL_1F80 Fld(3,8,AC_MSKB1)//[10:8]
	#define REG_1F80_CKGEN00_V004_REG_CKG_ATSC_DVBTC_TS_INV_1F80 Fld(1,11,AC_MSKB1)//[11:11]
	#define REG_1F80_CKGEN00_V004_REG_CKG_DVBTM_TS_OUT_MODE_1F80 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_1F80_CKGEN00_V004_REG_CKG_DEMOD_TEST_IN_EN_1F80 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_1F80_CKGEN00_V004_REG_CKG_TSOUT_PH_TUN_EN_1F80 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_1F84_CKGEN00_V004 (CKGEN00_V004 + 0x1F84)
	#define REG_1F84_CKGEN00_V004_REG_ATSC_DVB_DIV_RESET_1F84 Fld(1,0,AC_MSKB0)//[0:0]
#define REG_1F88_CKGEN00_V004 (CKGEN00_V004 + 0x1F88)
	#define REG_1F88_CKGEN00_V004_REG_CKG_ATSC_TS_1F88 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1F8C_CKGEN00_V004 (CKGEN00_V004 + 0x1F8C)
	#define REG_1F8C_CKGEN00_V004_REG_CKG_DVBTC_TS_TOP_1F8C Fld(4,8,AC_MSKB1)//[11:8]
#define REG_1F90_CKGEN00_V004 (CKGEN00_V004 + 0x1F90)
	#define REG_1F90_CKGEN00_V004_REG_CKG_TSOUT_PH_TUN_NUM_1F90 Fld(5,8,AC_MSKB1)//[12:8]
#define REG_1F94_CKGEN00_V004 (CKGEN00_V004 + 0x1F94)
	#define REG_1F94_CKGEN00_V004_REG_CKG_VIFDBB_DAC_TOP_1F94 Fld(4,0,AC_MSKB0)//[3:0]
#define REG_1F98_CKGEN00_V004 (CKGEN00_V004 + 0x1F98)
	#define REG_1F98_CKGEN00_V004_REG_CKG_DACA2_1F98 Fld(5,0,AC_MSKB0)//[4:0]
	#define REG_1F98_CKGEN00_V004_REG_CKG_DACB2_1F98 Fld(4,8,AC_MSKB1)//[11:8]
#define REG_1FA0_CKGEN00_V004 (CKGEN00_V004 + 0x1FA0)
	#define REG_1FA0_CKGEN00_V004_REG_CKG_VD_SEL_1FA0 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_1FA0_CKGEN00_V004_REG_CKG_VD_BUF_SEL_1FA0 Fld(1,4,AC_MSKB0)//[4:4]
#define REG_1FF0_CKGEN00_V004 (CKGEN00_V004 + 0x1FF0)
	#define REG_1FF0_CKGEN00_V004_REG_CKGEN00_V004_DUMMY0_1FF0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF4_CKGEN00_V004 (CKGEN00_V004 + 0x1FF4)
	#define REG_1FF4_CKGEN00_V004_REG_CKGEN00_V004_DUMMY1_1FF4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FF8_CKGEN00_V004 (CKGEN00_V004 + 0x1FF8)
	#define REG_1FF8_CKGEN00_V004_REG_CKGEN00_V004_DUMMY2_1FF8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_1FFC_CKGEN00_V004 (CKGEN00_V004 + 0x1FFC)
	#define REG_1FFC_CKGEN00_V004_REG_CKGEN00_V004_DUMMY3_1FFC Fld(16,0,AC_FULLW10)//[15:0]
