#define MODOSD2_V005 0x485A00

//Page MODOSD2_V005
#define REG_0004_MODOSD2_V005 (MODOSD2_V005 + 0x004)
	#define REG_0004_MODOSD2_V005_REG_VBY1_8PTO16P_EN_0004 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0004_MODOSD2_V005_REG_VBY1_16PTO32P_EN_0004 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0004_MODOSD2_V005_REG_VBY1_32PTO64P_EN_0004 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0004_MODOSD2_V005_REG_VBY1_3D_EN_0004 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0004_MODOSD2_V005_REG_VBY1_HS_INV_0004 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0004_MODOSD2_V005_REG_VBY1_LR_INV_0004 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0004_MODOSD2_V005_REG_VBY1_VS_INV_0004 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0004_MODOSD2_V005_REG_VBY1_MUTE_0004 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0004_MODOSD2_V005_REG_VBY1_MUTE_VDB_0004 Fld(1,14,AC_MSKB1)//[14:14]
	#define REG_0004_MODOSD2_V005_REG_VBY1_MUTE_UPD_0004 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0008_MODOSD2_V005 (MODOSD2_V005 + 0x008)
	#define REG_0008_MODOSD2_V005_REG_FORMAT_MAP_0008 Fld(5,0,AC_MSKB0)//[4:0]
	#define REG_0008_MODOSD2_V005_REG_VBY1_16CH_CKEN_31_16_0008 Fld(1,12,AC_MSKB1)//[12:12]
	#define REG_0008_MODOSD2_V005_REG_VBY1_16CH_CKEN_47_32_0008 Fld(1,13,AC_MSKB1)//[13:13]
	#define REG_0008_MODOSD2_V005_REG_VBY1_16CH_CKEN_63_48_0008 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0018_MODOSD2_V005 (MODOSD2_V005 + 0x018)
	#define REG_0018_MODOSD2_V005_REG_VBY1_CRC_EN_0018 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0018_MODOSD2_V005_REG_VBY1_CRC_CLR_0018 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0018_MODOSD2_V005_REG_VBY1_CRC_ALL_CLR_0018 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0018_MODOSD2_V005_REG_VBY1_CRC_CH_SEL_0018 Fld(6,4,AC_MSKW10)//[9:4]
	#define REG_0018_MODOSD2_V005_REG_VBY1_CRC_ERROR_0018 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_001C_MODOSD2_V005 (MODOSD2_V005 + 0x01C)
	#define REG_001C_MODOSD2_V005_REG_VBY1_CRC_VALUE_001C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0020_MODOSD2_V005 (MODOSD2_V005 + 0x020)
	#define REG_0020_MODOSD2_V005_REG_META_DATA_EN_0020 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0020_MODOSD2_V005_REG_META_TEST_EN_0020 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0020_MODOSD2_V005_REG_META_MODE_0020 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0020_MODOSD2_V005_REG_META_DELAY_AUTO_0020 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0020_MODOSD2_V005_REG_META_DELAY_NUM_0020 Fld(4,8,AC_MSKB1)//[11:8]
#define REG_0024_MODOSD2_V005 (MODOSD2_V005 + 0x024)
	#define REG_0024_MODOSD2_V005_REG_META_DATA_NUM_0024 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0028_MODOSD2_V005 (MODOSD2_V005 + 0x028)
	#define REG_0028_MODOSD2_V005_REG_META_HS_SEL_0028 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_002C_MODOSD2_V005 (MODOSD2_V005 + 0x02C)
	#define REG_002C_MODOSD2_V005_REG_META_DELAY_CHG_CNT_002C Fld(7,0,AC_MSKB0)//[6:0]
	#define REG_002C_MODOSD2_V005_REG_META_DELAY_CHG_CLR_002C Fld(1,7,AC_MSKB0)//[7:7]
#define REG_0030_MODOSD2_V005 (MODOSD2_V005 + 0x030)
	#define REG_0030_MODOSD2_V005_REG_META_REPORT_DELAY_0030 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0034_MODOSD2_V005 (MODOSD2_V005 + 0x034)
	#define REG_0034_MODOSD2_V005_REG_META_DATA_EN_BITMAP_0_0034 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0038_MODOSD2_V005 (MODOSD2_V005 + 0x038)
	#define REG_0038_MODOSD2_V005_REG_META_DATA_EN_BITMAP_1_0038 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_003C_MODOSD2_V005 (MODOSD2_V005 + 0x03C)
	#define REG_003C_MODOSD2_V005_REG_VBY1_CTRL_SW_UPDATE_003C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0040_MODOSD2_V005 (MODOSD2_V005 + 0x040)
	#define REG_0040_MODOSD2_V005_REG_VBY1_CTRL_FIELD_0_0040 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0044_MODOSD2_V005 (MODOSD2_V005 + 0x044)
	#define REG_0044_MODOSD2_V005_REG_VBY1_CTRL_FIELD_1_0044 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0048_MODOSD2_V005 (MODOSD2_V005 + 0x048)
	#define REG_0048_MODOSD2_V005_REG_VBY1_CTRL_FIELD_2_0048 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_004C_MODOSD2_V005 (MODOSD2_V005 + 0x04C)
	#define REG_004C_MODOSD2_V005_REG_VBY1_CTRL_FIELD_3_004C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0050_MODOSD2_V005 (MODOSD2_V005 + 0x050)
	#define REG_0050_MODOSD2_V005_REG_VBY1_CTRL_FIELD_4_0050 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0054_MODOSD2_V005 (MODOSD2_V005 + 0x054)
	#define REG_0054_MODOSD2_V005_REG_VBY1_CTRL_FIELD_5_0054 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0058_MODOSD2_V005 (MODOSD2_V005 + 0x058)
	#define REG_0058_MODOSD2_V005_REG_VBY1_CTRL_FIELD_6_0058 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_005C_MODOSD2_V005 (MODOSD2_V005 + 0x05C)
	#define REG_005C_MODOSD2_V005_REG_VBY1_CTRL_FIELD_7_005C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0060_MODOSD2_V005 (MODOSD2_V005 + 0x060)
	#define REG_0060_MODOSD2_V005_REG_VBY1_CTRL_FIELD_8_0060 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0064_MODOSD2_V005 (MODOSD2_V005 + 0x064)
	#define REG_0064_MODOSD2_V005_REG_VBY1_CTRL_FIELD_9_0064 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0068_MODOSD2_V005 (MODOSD2_V005 + 0x068)
	#define REG_0068_MODOSD2_V005_REG_VBY1_CTRL_FIELD_10_0068 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_006C_MODOSD2_V005 (MODOSD2_V005 + 0x06C)
	#define REG_006C_MODOSD2_V005_REG_VBY1_CTRL_FIELD_11_006C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0070_MODOSD2_V005 (MODOSD2_V005 + 0x070)
	#define REG_0070_MODOSD2_V005_REG_VBY1_CTRL_FIELD_12_0070 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0074_MODOSD2_V005 (MODOSD2_V005 + 0x074)
	#define REG_0074_MODOSD2_V005_REG_VBY1_CTRL_FIELD_13_0074 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0078_MODOSD2_V005 (MODOSD2_V005 + 0x078)
	#define REG_0078_MODOSD2_V005_REG_VBY1_CTRL_FIELD_14_0078 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_007C_MODOSD2_V005 (MODOSD2_V005 + 0x07C)
	#define REG_007C_MODOSD2_V005_REG_VBY1_CTRL_FIELD_15_007C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0080_MODOSD2_V005 (MODOSD2_V005 + 0x080)
	#define REG_0080_MODOSD2_V005_REG_VBY1_CTRL_FIELD_16_0080 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0084_MODOSD2_V005 (MODOSD2_V005 + 0x084)
	#define REG_0084_MODOSD2_V005_REG_VBY1_CTRL_FIELD_17_0084 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0088_MODOSD2_V005 (MODOSD2_V005 + 0x088)
	#define REG_0088_MODOSD2_V005_REG_VBY1_CTRL_FIELD_18_0088 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_008C_MODOSD2_V005 (MODOSD2_V005 + 0x08C)
	#define REG_008C_MODOSD2_V005_REG_VBY1_CTRL_FIELD_19_008C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0090_MODOSD2_V005 (MODOSD2_V005 + 0x090)
	#define REG_0090_MODOSD2_V005_REG_VBY1_CTRL_FIELD_20_0090 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0094_MODOSD2_V005 (MODOSD2_V005 + 0x094)
	#define REG_0094_MODOSD2_V005_REG_VBY1_CTRL_FIELD_21_0094 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0098_MODOSD2_V005 (MODOSD2_V005 + 0x098)
	#define REG_0098_MODOSD2_V005_REG_VBY1_CTRL_FIELD_22_0098 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_009C_MODOSD2_V005 (MODOSD2_V005 + 0x09C)
	#define REG_009C_MODOSD2_V005_REG_VBY1_CTRL_FIELD_23_009C Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A0_MODOSD2_V005 (MODOSD2_V005 + 0x0A0)
	#define REG_00A0_MODOSD2_V005_REG_VBY1_CTRL_FIELD_24_00A0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A4_MODOSD2_V005 (MODOSD2_V005 + 0x0A4)
	#define REG_00A4_MODOSD2_V005_REG_VBY1_CTRL_FIELD_25_00A4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00A8_MODOSD2_V005 (MODOSD2_V005 + 0x0A8)
	#define REG_00A8_MODOSD2_V005_REG_VBY1_CTRL_FIELD_26_00A8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00AC_MODOSD2_V005 (MODOSD2_V005 + 0x0AC)
	#define REG_00AC_MODOSD2_V005_REG_VBY1_CTRL_FIELD_27_00AC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B0_MODOSD2_V005 (MODOSD2_V005 + 0x0B0)
	#define REG_00B0_MODOSD2_V005_REG_VBY1_CTRL_FIELD_28_00B0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B4_MODOSD2_V005 (MODOSD2_V005 + 0x0B4)
	#define REG_00B4_MODOSD2_V005_REG_VBY1_CTRL_FIELD_29_00B4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00B8_MODOSD2_V005 (MODOSD2_V005 + 0x0B8)
	#define REG_00B8_MODOSD2_V005_REG_VBY1_CTRL_FIELD_30_00B8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00BC_MODOSD2_V005 (MODOSD2_V005 + 0x0BC)
	#define REG_00BC_MODOSD2_V005_REG_VBY1_CTRL_FIELD_31_00BC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C0_MODOSD2_V005 (MODOSD2_V005 + 0x0C0)
	#define REG_00C0_MODOSD2_V005_REG_VBY1_CTRL_FIELD_32_00C0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C4_MODOSD2_V005 (MODOSD2_V005 + 0x0C4)
	#define REG_00C4_MODOSD2_V005_REG_VBY1_CTRL_FIELD_33_00C4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00C8_MODOSD2_V005 (MODOSD2_V005 + 0x0C8)
	#define REG_00C8_MODOSD2_V005_REG_VBY1_CTRL_FIELD_34_00C8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00CC_MODOSD2_V005 (MODOSD2_V005 + 0x0CC)
	#define REG_00CC_MODOSD2_V005_REG_VBY1_CTRL_FIELD_35_00CC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D0_MODOSD2_V005 (MODOSD2_V005 + 0x0D0)
	#define REG_00D0_MODOSD2_V005_REG_VBY1_CTRL_FIELD_36_00D0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D4_MODOSD2_V005 (MODOSD2_V005 + 0x0D4)
	#define REG_00D4_MODOSD2_V005_REG_VBY1_CTRL_FIELD_37_00D4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00D8_MODOSD2_V005 (MODOSD2_V005 + 0x0D8)
	#define REG_00D8_MODOSD2_V005_REG_VBY1_CTRL_FIELD_38_00D8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00DC_MODOSD2_V005 (MODOSD2_V005 + 0x0DC)
	#define REG_00DC_MODOSD2_V005_REG_VBY1_CTRL_FIELD_39_00DC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E0_MODOSD2_V005 (MODOSD2_V005 + 0x0E0)
	#define REG_00E0_MODOSD2_V005_REG_VBY1_CTRL_FIELD_40_00E0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E4_MODOSD2_V005 (MODOSD2_V005 + 0x0E4)
	#define REG_00E4_MODOSD2_V005_REG_VBY1_CTRL_FIELD_41_00E4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00E8_MODOSD2_V005 (MODOSD2_V005 + 0x0E8)
	#define REG_00E8_MODOSD2_V005_REG_VBY1_CTRL_FIELD_42_00E8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00EC_MODOSD2_V005 (MODOSD2_V005 + 0x0EC)
	#define REG_00EC_MODOSD2_V005_REG_VBY1_CTRL_FIELD_43_00EC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F0_MODOSD2_V005 (MODOSD2_V005 + 0x0F0)
	#define REG_00F0_MODOSD2_V005_REG_VBY1_CTRL_FIELD_44_00F0 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F4_MODOSD2_V005 (MODOSD2_V005 + 0x0F4)
	#define REG_00F4_MODOSD2_V005_REG_VBY1_CTRL_FIELD_45_00F4 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00F8_MODOSD2_V005 (MODOSD2_V005 + 0x0F8)
	#define REG_00F8_MODOSD2_V005_REG_VBY1_CTRL_FIELD_46_00F8 Fld(16,0,AC_FULLW10)//[15:0]
#define REG_00FC_MODOSD2_V005 (MODOSD2_V005 + 0x0FC)
	#define REG_00FC_MODOSD2_V005_REG_VBY1_CTRL_FIELD_47_00FC Fld(16,0,AC_FULLW10)//[15:0]
#define REG_0100_MODOSD2_V005 (MODOSD2_V005 + 0x100)
	#define REG_0100_MODOSD2_V005_REG_SWAP_BIT_00_0100 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0100_MODOSD2_V005_REG_SWAP_BIT_01_0100 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0104_MODOSD2_V005 (MODOSD2_V005 + 0x104)
	#define REG_0104_MODOSD2_V005_REG_SWAP_BIT_02_0104 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0104_MODOSD2_V005_REG_SWAP_BIT_03_0104 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0108_MODOSD2_V005 (MODOSD2_V005 + 0x108)
	#define REG_0108_MODOSD2_V005_REG_SWAP_BIT_04_0108 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0108_MODOSD2_V005_REG_SWAP_BIT_05_0108 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_010C_MODOSD2_V005 (MODOSD2_V005 + 0x10C)
	#define REG_010C_MODOSD2_V005_REG_SWAP_BIT_06_010C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_010C_MODOSD2_V005_REG_SWAP_BIT_07_010C Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0110_MODOSD2_V005 (MODOSD2_V005 + 0x110)
	#define REG_0110_MODOSD2_V005_REG_SWAP_BIT_08_0110 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0110_MODOSD2_V005_REG_SWAP_BIT_09_0110 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0114_MODOSD2_V005 (MODOSD2_V005 + 0x114)
	#define REG_0114_MODOSD2_V005_REG_SWAP_BIT_10_0114 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0114_MODOSD2_V005_REG_SWAP_BIT_11_0114 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0118_MODOSD2_V005 (MODOSD2_V005 + 0x118)
	#define REG_0118_MODOSD2_V005_REG_SWAP_BIT_12_0118 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0118_MODOSD2_V005_REG_SWAP_BIT_13_0118 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_011C_MODOSD2_V005 (MODOSD2_V005 + 0x11C)
	#define REG_011C_MODOSD2_V005_REG_SWAP_BIT_14_011C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_011C_MODOSD2_V005_REG_SWAP_BIT_15_011C Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0120_MODOSD2_V005 (MODOSD2_V005 + 0x120)
	#define REG_0120_MODOSD2_V005_REG_SWAP_BIT_16_0120 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0120_MODOSD2_V005_REG_SWAP_BIT_17_0120 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0124_MODOSD2_V005 (MODOSD2_V005 + 0x124)
	#define REG_0124_MODOSD2_V005_REG_SWAP_BIT_18_0124 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0124_MODOSD2_V005_REG_SWAP_BIT_19_0124 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0128_MODOSD2_V005 (MODOSD2_V005 + 0x128)
	#define REG_0128_MODOSD2_V005_REG_SWAP_BIT_20_0128 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0128_MODOSD2_V005_REG_SWAP_BIT_21_0128 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_012C_MODOSD2_V005 (MODOSD2_V005 + 0x12C)
	#define REG_012C_MODOSD2_V005_REG_SWAP_BIT_22_012C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_012C_MODOSD2_V005_REG_SWAP_BIT_23_012C Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0130_MODOSD2_V005 (MODOSD2_V005 + 0x130)
	#define REG_0130_MODOSD2_V005_REG_SWAP_BIT_24_0130 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0130_MODOSD2_V005_REG_SWAP_BIT_25_0130 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0134_MODOSD2_V005 (MODOSD2_V005 + 0x134)
	#define REG_0134_MODOSD2_V005_REG_SWAP_BIT_26_0134 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0134_MODOSD2_V005_REG_SWAP_BIT_27_0134 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0138_MODOSD2_V005 (MODOSD2_V005 + 0x138)
	#define REG_0138_MODOSD2_V005_REG_SWAP_BIT_28_0138 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0138_MODOSD2_V005_REG_SWAP_BIT_29_0138 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_013C_MODOSD2_V005 (MODOSD2_V005 + 0x13C)
	#define REG_013C_MODOSD2_V005_REG_SWAP_BIT_30_013C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_013C_MODOSD2_V005_REG_SWAP_BIT_31_013C Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0140_MODOSD2_V005 (MODOSD2_V005 + 0x140)
	#define REG_0140_MODOSD2_V005_REG_SWAP_BIT_32_0140 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0140_MODOSD2_V005_REG_SWAP_BIT_33_0140 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0144_MODOSD2_V005 (MODOSD2_V005 + 0x144)
	#define REG_0144_MODOSD2_V005_REG_SWAP_BIT_34_0144 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0144_MODOSD2_V005_REG_SWAP_BIT_35_0144 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0148_MODOSD2_V005 (MODOSD2_V005 + 0x148)
	#define REG_0148_MODOSD2_V005_REG_SWAP_BIT_36_0148 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_0148_MODOSD2_V005_REG_SWAP_BIT_37_0148 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_014C_MODOSD2_V005 (MODOSD2_V005 + 0x14C)
	#define REG_014C_MODOSD2_V005_REG_SWAP_BIT_38_014C Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_014C_MODOSD2_V005_REG_SWAP_BIT_39_014C Fld(6,8,AC_MSKB1)//[13:8]
#define REG_0180_MODOSD2_V005 (MODOSD2_V005 + 0x180)
	#define REG_0180_MODOSD2_V005_REG_VBY1_SCR_RST_0180 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0180_MODOSD2_V005_REG_VBY1_SCR_EN_0180 Fld(1,1,AC_MSKB0)//[1:1]
	#define REG_0180_MODOSD2_V005_REG_VBY1_SCR_ON_0180 Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_0180_MODOSD2_V005_REG_VBY1_ENC_EN_0180 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_0180_MODOSD2_V005_REG_VBY1_LOCKN_0180 Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_0180_MODOSD2_V005_REG_VBY1_PLL_LOCK_0180 Fld(1,5,AC_MSKB0)//[5:5]
	#define REG_0180_MODOSD2_V005_REG_VBY1_HTPDN_0180 Fld(1,6,AC_MSKB0)//[6:6]
	#define REG_0180_MODOSD2_V005_REG_VBY1_POWER_ON_0180 Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_0180_MODOSD2_V005_REG_VBY1_CTL_MCU_0180 Fld(4,8,AC_MSKB1)//[11:8]
	#define REG_0180_MODOSD2_V005_REG_VBY1_STATE_0180 Fld(3,12,AC_MSKB1)//[14:12]
	#define REG_0180_MODOSD2_V005_REG_VBY1_ST_MCU_0180 Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0184_MODOSD2_V005 (MODOSD2_V005 + 0x184)
	#define REG_0184_MODOSD2_V005_REG_VBY1_ALN_PIX_CNT_0184 Fld(8,0,AC_FULLB0)//[7:0]
	#define REG_0184_MODOSD2_V005_REG_VBY1_ALN_DE_CNT_0184 Fld(6,8,AC_MSKB1)//[13:8]
	#define REG_0184_MODOSD2_V005_REG_VBY1_LOCK_VIDEO_0184 Fld(1,14,AC_MSKB1)//[14:14]
#define REG_0188_MODOSD2_V005 (MODOSD2_V005 + 0x188)
	#define REG_0188_MODOSD2_V005_REG_VBY1_PRBS7_EN_0188 Fld(1,0,AC_MSKB0)//[0:0]
	#define REG_0188_MODOSD2_V005_REG_VBY1_BYTE_MODE_0188 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_018C_MODOSD2_V005 (MODOSD2_V005 + 0x18C)
	#define REG_018C_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE1_018C Fld(10,0,AC_MSKW10)//[9:0]
	#define REG_018C_MODOSD2_V005_REG_VBY1_TEST_EN_018C Fld(1,15,AC_MSKB1)//[15:15]
#define REG_0190_MODOSD2_V005 (MODOSD2_V005 + 0x190)
	#define REG_0190_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE2_0190 Fld(10,0,AC_MSKW10)//[9:0]
	#define REG_0190_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE5_30_0190 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0194_MODOSD2_V005 (MODOSD2_V005 + 0x194)
	#define REG_0194_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE3_0194 Fld(10,0,AC_MSKW10)//[9:0]
	#define REG_0194_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE5_74_0194 Fld(4,12,AC_MSKB1)//[15:12]
#define REG_0198_MODOSD2_V005 (MODOSD2_V005 + 0x198)
	#define REG_0198_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE4_0198 Fld(10,0,AC_MSKW10)//[9:0]
	#define REG_0198_MODOSD2_V005_REG_VBY1_TEST_DATA_BYTE5_98_0198 Fld(2,12,AC_MSKB1)//[13:12]
#define REG_019C_MODOSD2_V005 (MODOSD2_V005 + 0x19C)
	#define REG_019C_MODOSD2_V005_REG_VBY1_HALF_FIFO_019C Fld(1,2,AC_MSKB0)//[2:2]
	#define REG_019C_MODOSD2_V005_REG_VBY1_HW_LOCK_019C Fld(1,7,AC_MSKB0)//[7:7]
	#define REG_019C_MODOSD2_V005_REG_VBY1_FIFO_RPTR_ALIGN_019C Fld(1,8,AC_MSKB1)//[8:8]
	#define REG_019C_MODOSD2_V005_REG_VBY1_VS_MATCH_019C Fld(1,14,AC_MSKB1)//[14:14]
#define REG_01A0_MODOSD2_V005 (MODOSD2_V005 + 0x1A0)
	#define REG_01A0_MODOSD2_V005_REG_VBY1_SWAP_CH00_01A0 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01A0_MODOSD2_V005_REG_VBY1_SWAP_CH01_01A0 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01A4_MODOSD2_V005 (MODOSD2_V005 + 0x1A4)
	#define REG_01A4_MODOSD2_V005_REG_VBY1_SWAP_CH02_01A4 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01A4_MODOSD2_V005_REG_VBY1_SWAP_CH03_01A4 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01A8_MODOSD2_V005 (MODOSD2_V005 + 0x1A8)
	#define REG_01A8_MODOSD2_V005_REG_VBY1_SWAP_CH04_01A8 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01A8_MODOSD2_V005_REG_VBY1_SWAP_CH05_01A8 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01AC_MODOSD2_V005 (MODOSD2_V005 + 0x1AC)
	#define REG_01AC_MODOSD2_V005_REG_VBY1_SWAP_CH06_01AC Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01AC_MODOSD2_V005_REG_VBY1_SWAP_CH07_01AC Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01B0_MODOSD2_V005 (MODOSD2_V005 + 0x1B0)
	#define REG_01B0_MODOSD2_V005_REG_VBY1_SWAP_CH08_01B0 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01B0_MODOSD2_V005_REG_VBY1_SWAP_CH09_01B0 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01B4_MODOSD2_V005 (MODOSD2_V005 + 0x1B4)
	#define REG_01B4_MODOSD2_V005_REG_VBY1_SWAP_CH10_01B4 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01B4_MODOSD2_V005_REG_VBY1_SWAP_CH11_01B4 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01B8_MODOSD2_V005 (MODOSD2_V005 + 0x1B8)
	#define REG_01B8_MODOSD2_V005_REG_VBY1_SWAP_CH12_01B8 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01B8_MODOSD2_V005_REG_VBY1_SWAP_CH13_01B8 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01BC_MODOSD2_V005 (MODOSD2_V005 + 0x1BC)
	#define REG_01BC_MODOSD2_V005_REG_VBY1_SWAP_CH14_01BC Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01BC_MODOSD2_V005_REG_VBY1_SWAP_CH15_01BC Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01C0_MODOSD2_V005 (MODOSD2_V005 + 0x1C0)
	#define REG_01C0_MODOSD2_V005_REG_VBY1_SWAP_CH16_01C0 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01C0_MODOSD2_V005_REG_VBY1_SWAP_CH17_01C0 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01C4_MODOSD2_V005 (MODOSD2_V005 + 0x1C4)
	#define REG_01C4_MODOSD2_V005_REG_VBY1_SWAP_CH18_01C4 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01C4_MODOSD2_V005_REG_VBY1_SWAP_CH19_01C4 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01C8_MODOSD2_V005 (MODOSD2_V005 + 0x1C8)
	#define REG_01C8_MODOSD2_V005_REG_VBY1_SWAP_CH20_01C8 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01C8_MODOSD2_V005_REG_VBY1_SWAP_CH21_01C8 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01CC_MODOSD2_V005 (MODOSD2_V005 + 0x1CC)
	#define REG_01CC_MODOSD2_V005_REG_VBY1_SWAP_CH22_01CC Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01CC_MODOSD2_V005_REG_VBY1_SWAP_CH23_01CC Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01D0_MODOSD2_V005 (MODOSD2_V005 + 0x1D0)
	#define REG_01D0_MODOSD2_V005_REG_VBY1_SWAP_CH24_01D0 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01D0_MODOSD2_V005_REG_VBY1_SWAP_CH25_01D0 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01D4_MODOSD2_V005 (MODOSD2_V005 + 0x1D4)
	#define REG_01D4_MODOSD2_V005_REG_VBY1_SWAP_CH26_01D4 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01D4_MODOSD2_V005_REG_VBY1_SWAP_CH27_01D4 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01D8_MODOSD2_V005 (MODOSD2_V005 + 0x1D8)
	#define REG_01D8_MODOSD2_V005_REG_VBY1_SWAP_CH28_01D8 Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01D8_MODOSD2_V005_REG_VBY1_SWAP_CH29_01D8 Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01DC_MODOSD2_V005 (MODOSD2_V005 + 0x1DC)
	#define REG_01DC_MODOSD2_V005_REG_VBY1_SWAP_CH30_01DC Fld(6,0,AC_MSKB0)//[5:0]
	#define REG_01DC_MODOSD2_V005_REG_VBY1_SWAP_CH31_01DC Fld(6,8,AC_MSKB1)//[13:8]
#define REG_01F0_MODOSD2_V005 (MODOSD2_V005 + 0x1F0)
	#define REG_01F0_MODOSD2_V005_REG_VBY1_FSM_TRACER_STATE_01F0 Fld(3,0,AC_MSKB0)//[2:0]
	#define REG_01F0_MODOSD2_V005_REG_VBY1_FSM_TRACER_EN_01F0 Fld(1,3,AC_MSKB0)//[3:3]
	#define REG_01F0_MODOSD2_V005_REG_VBY1_FSM_TRACER_SEL_01F0 Fld(4,4,AC_MSKB0)//[7:4]
#define REG_01F8_MODOSD2_V005 (MODOSD2_V005 + 0x1F8)
	#define REG_01F8_MODOSD2_V005_REG_UNLOCK_CNT_01F8 Fld(7,0,AC_MSKB0)//[6:0]
	#define REG_01F8_MODOSD2_V005_REG_UNLOCK_CNT_CLR_01F8 Fld(1,7,AC_MSKB0)//[7:7]
#define REG_01FC_MODOSD2_V005 (MODOSD2_V005 + 0x1FC)
	#define REG_01FC_MODOSD2_V005_REG_VBY1_LOCKN_VIDEO_R_01FC Fld(1,4,AC_MSKB0)//[4:4]
	#define REG_01FC_MODOSD2_V005_REG_VBY1_HTPDN_VIDEO_R_01FC Fld(1,5,AC_MSKB0)//[5:5]
