#ifndef _HW_PLLGP_H_
#define _HW_PLLGP_H_

//Page HISTORY
#define IO_LVDSTX_PLL_BASE	(IO_VIRT + 0x60000)
#define IO_PLLGP_BASE 		(IO_VIRT + 0x61000)

//Page VOPLL
#define REG_LVDSTX_PLL_CFG0 (IO_LVDSTX_PLL_BASE + 0x100)
    #define REG_LVDSTX_PLL_CFG0_VPLL_XTAL_DIV Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_TRIM Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_RASEL Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_RBSEL Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_PWD Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_COMP_PWD Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_PRE_PWD Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BG_LVDS_PWD Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_LVDSTX_PLL_CFG0_VPLL_BIAS_BYP Fld(1,0,AC_MSKB0)//[0:0]
#define REG_LVDSTX_PLL_CFG1 (IO_LVDSTX_PLL_BASE + 0x104)
    #define REG_LVDSTX_PLL_CFG1_VPLL_PWD Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV Fld(7,24,AC_MSKB3)//[30:24]
    #define REG_LVDSTX_PLL_CFG1_VPLL_PREDIV Fld(2,22,AC_MSKB2)//[23:22]
    #define REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define REG_LVDSTX_PLL_CFG1_VPLL_POSDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define REG_LVDSTX_PLL_CFG1_VPLL_REFSEL Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_LVDSTX_PLL_CFG1_VPLL_LVDSEN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_LVDSTX_PLL_CFG1_VPLL_VB1EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_LVDSTX_PLL_CFG1_VPLL_MLVDSEN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_LVDSTX_PLL_CFG1_VPLL_EPIEN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_LVDSTX_PLL_CFG1_VPLL_IDPEN Fld(1,11,AC_MSKB1)//[11:11]
    	#define LVDSTX_PLL_POST_SEL Fld(5,11,AC_MSKB1)//[15:11]
        #define LVDSTX_PLL_POST_LVDSEN  (1<<4)
        #define LVDSTX_PLL_POST_VB1EN   (1<<3)
        #define LVDSTX_PLL_POST_MINIEN  (1<<2)  
        #define LVDSTX_PLL_POST_EPIEN   (1<<1)
		#define LVDSTX_PLL_POST_IDPEN   (1<<0)
    #define REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2 Fld(2,0,AC_MSKB0)//[1:0]
#define REG_LVDSTX_PLL_CFG2 (IO_LVDSTX_PLL_BASE + 0x108)
    #define REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL Fld(2,30,AC_MSKB3)//[31:30]
    #define REG_LVDSTX_PLL_CFG2_VPLL_BAND Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_LVDSTX_PLL_CFG2_VPLL_VODEN Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_LVDSTX_PLL_CFG2_VPLL_DLY_DATA Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKA Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKB Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_LVDSTX_PLL_CFG2_VPLL_BIC Fld(3,5,AC_MSKB0)//[7:5]
    #define REG_LVDSTX_PLL_CFG2_VPLL_BC Fld(2,3,AC_MSKB0)//[4:3]
    #define REG_LVDSTX_PLL_CFG2_VPLL_DIVEN Fld(3,0,AC_MSKB0)//[2:0]
#define REG_LVDSTX_PLL_CFG3 (IO_LVDSTX_PLL_BASE + 0x10C)
    #define REG_LVDSTX_PLL_CFG3_VPLL_BIR Fld(4,28,AC_MSKB3)//[31:28]
    #define REG_LVDSTX_PLL_CFG3_VPLL_BP Fld(4,24,AC_MSKB3)//[27:24]
    #define REG_LVDSTX_PLL_CFG3_VPLL_BR Fld(3,21,AC_MSKB2)//[23:21]
    #define REG_LVDSTX_PLL_CFG3_VPLL_MONEN Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_LVDSTX_PLL_CFG3_VPLL_MONENCKEN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_LVDSTX_PLL_CFG3_VPLL_FPEN Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_LVDSTX_PLL_CFG3_VPLL_FMEN Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_LVDSTX_PLL_CFG3_VPLL_TST_CKENB Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_LVDSTX_PLL_CFG3_VPLL_TST_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define REG_LVDSTX_PLL_CFG3_VPLL_CHL_SEL Fld(2,11,AC_MSKB1)//[12:11]
    #define REG_LVDSTX_PLL_CFG3_VPLL_XTAL_MONEN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_LVDSTX_PLL_CFG3_VPLL_BG_MONEN Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_LVDSTX_PLL_CFG3_VPLL_REF_MONEN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_LVDSTX_PLL_CFG3_VPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_LVDSTX_PLL_CFG3_VPLL_RESERVE_bit7 Fld(1, 7, AC_MSKB0) //[7:7] 
#define REG_LVDSTX_PLL_CFG4 (IO_LVDSTX_PLL_BASE + 0x110)
    #define REG_LVDSTX_PLL_CFG4_PPLL_PWD Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV Fld(7,24,AC_MSKB3)//[30:24]
    #define REG_LVDSTX_PLL_CFG4_PPLL_PREDIV Fld(2,22,AC_MSKB2)//[23:22]
    #define REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define REG_LVDSTX_PLL_CFG4_PPLL_POSDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2 Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_LVDSTX_PLL_CFG4_PPLL_REFSEL Fld(2,14,AC_MSKB1)//[15:14]
    	   #define PPLL_REFSEL_IDP 0		
		   #define PPLL_REFSEL_DDDS 1 	 
		   #define PPLL_REFSEL_VPLL 2
    #define REG_LVDSTX_PLL_CFG4_PPLL_DIVEN Fld(3,11,AC_MSKB1)//[13:11]
    #define REG_LVDSTX_PLL_CFG4_PPLL_BP Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_LVDSTX_PLL_CFG4_PPLL_BR Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_LVDSTX_PLL_CFG4_PPLL_LF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_LVDSTX_PLL_CFG4_PPLL_VODEN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_LVDSTX_PLL_CFG4_PPLL_MONEN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_LVDSTX_PLL_CFG4_PPLL_MONCKEN Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_LVDSTX_PLL_CFG4_PPLL_FMEN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_LVDSTX_PLL_CFG4_PPLL_TSTEN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_LVDSTX_PLL_CFG4_PPLL_TST_DIV2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_LVDSTX_PLL_CFG4_PPLL_RESERVE Fld(2,0,AC_MSKB0)//[1:0]
#define RGS_LVDSTX_PLL_CFG0 (IO_LVDSTX_PLL_BASE + 0x114)
    #define REG_LVDSTX_PLL_CFG0_VPLL_CAL_CPLT Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_LVDSTX_PLL_CFG0_VPLL_CAL_FAIL Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_LVDSTX_PLL_CFG0_VPLL_CAL_STATE Fld(6,24,AC_MSKB3)//[29:24]

#define REG_LVDS_TX_PLL_CFG (IO_LVDSTX_PLL_BASE+0x54)
	#define REG_LVDS_TX_PLL_CFG_VPLL_BG_CKEN Fld(1, 7, AC_MSKB0) //7

    
//Page TABLE
#define REG_PLL_GROUP_CFG0 (IO_PLLGP_BASE + 0x000)
    #define FLD_RG_SYSPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_SYSPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_SYSPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_SYSPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_SYSPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_SYSPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_SYSPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_SYSPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_SYSPLL_SDM_PCW_CHG Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_SYSPLL_SDM_PCW Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_RG_SYSPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_SYSPLL_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_SYSPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_SYSPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_PLL_GROUP_CFG1 (IO_PLLGP_BASE + 0x004)
    #define FLD_RG_VDECPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_VDECPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_VDECPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_VDECPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_VDECPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_VDECPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_VDECPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_VDECPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_VDECPLL_SDM_PCW_CHG Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_VDECPLL_SDM_PCW Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_RG_VDECPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_VDECPLL_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_VDECPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_VDECPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_PLL_GROUP_CFG2 (IO_PLLGP_BASE + 0x008)
    #define FLD_RG_G3DPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_G3DPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_G3DPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_G3DPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_G3DPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_G3DPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_G3DPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_G3DPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_G3DPLL_SDM_PCW_CHG Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_G3DPLL_SDM_PCW Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_RG_G3DPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_G3DPLL_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_G3DPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_G3DPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_PLL_GROUP_CFG3 (IO_PLLGP_BASE + 0x00C)
    #define FLD_RG_DMUXPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DMUXPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_DMUXPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_DMUXPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DMUXPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DMUXPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_DMUXPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_DMUXPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_DMUXPLL_SDM_PCW_CHG Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_DMUXPLL_SDM_PCW Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_RG_DMUXPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_DMUXPLL_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_DMUXPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_DMUXPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_PLL_GROUP_CFG4 (IO_PLLGP_BASE + 0x010)
    #define FLD_RG_VGAPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_VGAPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_VGAPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_VGAPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_VGAPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_VGAPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_VGAPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_VGAPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_VGAPLL_SDM_PCW_CHG Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_VGAPLL_SDM_PCW Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_RG_VGAPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_VGAPLL_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_VGAPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_VGAPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_PLL_GROUP_CFG5 (IO_PLLGP_BASE + 0x014)
    #define FLD_RG_APLL2_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_APLL2_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_APLL2_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_APLL2_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_APLL2_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_APLL2_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_APLL2_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_APLL2_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_APLL2_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_APLL2_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RG_APLL2_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_APLL2_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_PLL_GROUP_CFG6 (IO_PLLGP_BASE + 0x018)
    #define FLD_RG_HADDS1_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_HADDS1_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_HADDS1_VSP_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_HADDS1_REFCLK_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_HADDS1_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_HADDS1_PRE_DIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_HADDS1_HF Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_HADDS1_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_HADDS1_RESERVE Fld(4,16,AC_MSKB2)//[19:16]
#define REG_PLL_GROUP_CFG7 (IO_PLLGP_BASE + 0x01C)
    #define FLD_RG_VGAPLL_SDDS_PD_PDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_VGAPLL_SDDS_PD_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_VGATL_BIAS_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_XDDS_PWDB Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_XDDS_CKSEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_VGAPLL_CKO_SEL Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_RG_XDDS_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_XDDS_HF Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_VGAPLL_R_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_VGAPLL_G_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_VGAPLL_B_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_VGAPLL_RTB_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_VGAPLL_ENTL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_RG_VGAPLL_INTH_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_RG_VGAPLL_EXTH_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_RG_VGAPLL_SDDS_FBKSEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_TL_REFCK_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_VGAPLL_SDDS_HSEL Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_RG_VGAPLL_SDDS_HPOR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_VGATL_RESERVE Fld(3,1,AC_MSKB0)//[3:1]
    #define FLD_RG_XDDS_MONEN Fld(1,0,AC_MSKB0)//[0:0]
#define REG_PLL_GROUP_CFG8 (IO_PLLGP_BASE + 0x020)
    #define FLD_RG_VGATL_TSELA Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_RG_VGATL_TSELB Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_RG_XDDS_CKSEL_MON Fld(4,20,AC_MSKB2)//[23:20]
#define REG_PLL_GROUP_CFG9 (IO_PLLGP_BASE + 0x024)
    #define FLD_RG_DDDS1_PWDB Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_DDDS1_MONEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_DDDS1_CKSEL Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_RG_DDDS1_PRE_DIV2 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_DDDS1_HF Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_DDDS2_PWDB Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_DDDS2_MONEN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_DDDS1_PI_C Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_DDDS2_CKSEL Fld(2,18,AC_MSKB2)//[19:18]
    #define FLD_RG_DDDS2_PRE_DIV2 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_DDDS2_HF Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_DDDS2_PI_C Fld(3,13,AC_MSKB1)//[15:13]
    #define FLD_RG_DDDS1_RESERVE Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_RG_DDDS2_RESERVE Fld(4,4,AC_MSKB0)//[7:4]
#define REG_PLL_GROUP_CFG10 (IO_PLLGP_BASE + 0x028)
    #define FLD_RG_PLLGP_BIAS_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_PLLGP_REFLVR_OD_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_PLLGP_REFCK_MON_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_PLLGP_TST_LVROD_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_PLLGP_TST_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_PLLGP_TSTCK_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_PLLGP_TST_SEL Fld(6,20,AC_MSKW32)//[25:20]
    #define FLD_RG_PLLGP_TSTOD_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_PLLGP_A2DCK_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_PLLGP_DIV2_SEL Fld(3,8,AC_MSKB1)//[10:8]
#define REG_PLL_GROUP_CFG11 (IO_PLLGP_BASE + 0x02C)
    #define FLD_RG_PLLGP_RESERVE Fld(32,0,AC_FULLDW)//[31:0]

#endif /* _HW_PLLGP_H_ */
