/******************************************************************************
 *
 * Copyright 2013, Silicon Image, Inc.  All rights reserved.
 * No part of this work may be reproduced, modified, distributed, transmitted,
 * transcribed, or translated into any language or computer format, in any form
 * or by any means without written permission of
 * Silicon Image, Inc., 1140 East Arques Avenue, Sunnyvale, California 94085
 *
 *****************************************************************************/
/**
 * @file sii9777_mhl_data.h
 *
 * @brief Host Driver for SiI9777 MHL device.
 *
 *****************************************************************************/

#ifndef SII9777_MHL_DATA_H
#define SII9777_MHL_DATA_H

#ifdef __cplusplus
extern "C"{
#endif

/***** #include statements ***************************************************/

/***** public macro definitions **********************************************/
#define SII9777_RETVAL_ERR__PARAMETER           0x0001 // need to be removed after clear definition of SiiRetVal_t
#define SII9777_RETVAL_CBUS_ERR__UNAVAILABLE    0x0002 // need to be removed after clear definition of SiiRetVal_t

/***** public type definitions ***********************************************/

typedef enum
{
    BIT0_MASK = 0x01,
    BIT1_MASK = 0x02,
    BIT2_MASK = 0x04,
    BIT3_MASK = 0x08,
    BIT4_MASK = 0x10,
    BIT5_MASK = 0x20,
    BIT6_MASK = 0x40,
    BIT7_MASK = 0x80,
    BIT8_MASK = 0x0100,
    BIT9_MASK = 0x0200,
} BIT_MASK_ENUM;

#define CBUS_MSC_MSG_RCVD_MASK              BIT0_MASK
#define CBUS_DEVCAP_RCVD_MASK               BIT1_MASK
#define CBUS_FEEDBACK_RCVD_MASK             BIT2_MASK
#define CBUS_MSC_SENDING_FAILED_MASK        BIT3_MASK
#define CBUS_MSG_SENDING_SUCCESS_MASK       BIT4_MASK
#define CBUS_NOTIFY_DEVCAP_FAILED_MASK      BIT5_MASK
#define CBUS_NOTIFY_DEVCAP_SUCCESS_MASK     BIT6_MASK
#define CBUS_WRITE_BURST_RCVD_MASK          BIT7_MASK
#define CBUS_WRITE_BURST_SUCCESS_INT        BIT8_MASK
#define CBUS_WRITE_BURST_FAIL_INT           BIT9_MASK

/**
* @brief MHL Version
*
* @see Sii9777MHLVersionGet()
*/

typedef enum
{
    SII9777_MHL_VERSION__NONE  = 0x00,
    //!< No MHL connection is established
    SII9777_MHL_VERSION__MHL12 = 0x01,
    //!< MHL1/2 connection is established
    SII9777_MHL_VERSION__MHL3  = 0x02
    //!< MHL3 connection is established
} Sii9777MhlVersion_t;

/**
* @brief CBUS Mode
*
* @see Sii9777CbusModeGet()
*/
typedef enum
{
    SII9777_CBUS_MODE__NONE		=	0x00,
    //!< No CBUS connection
    SII9777_CBUS_MODE__OCBUS	=	0x01,
    //!< oCBUS is connected
    SII9777_CBUS_MODE__ECBUS_S	=	0x02,
    //!< eCBUS_S is connected
    SII9777_CBUS_MODE__ECBUS_D	=	0x04
    //!< eCBUS_D is connected
}Sii9777CbusMode_t;

/**
* @brief CBUS Event
*
* @see SiiDrvAdaptCbusEventGet()
* @see SII_DRV_ADAPT_EVENT__CBUS_EVENT
*/
typedef enum
{
    SII9777_CBUS_EVT__NO_PENDING_EVENTS               = 0x0001,
    //!< No event pending
    SII9777_CBUS_EVT__MSC_MESSAGE_RECEIVED            = 0x0002,
    //!< RAP or RCP or UCP message received
    SII9777_CBUS_EVT__SCRATCH_PAD_CHANGED             = 0x0004,
    //!< Remote peer wrote into local side Scratch Pad register(s) through Write Burst command
    SII9777_CBUS_EVT__REMOTE_DEVCAP_CHANGED           = 0x0008,
    //!< Remote peer changed its DEVCAP register(s)
    SII9777_CBUS_EVT__FEEDBACK_RECEIVED               = 0x0010,
    //!< RAPK or RCPE or RCPK or UCPK or UCPE received
    SII9777_CBUS_EVT__MSC_SENDING_FAILED              = 0x0020,
    //!< Link level failure on RAP or RCP or UCP message sending
    SII9777_CBUS_EVT__BURST_WRITE_FAILED              = 0x0040,
    //!< Scratch Pad writing initiated by @ref SiiDrvAdaptCbusRemoteScratchPadWrite() failed
    SII9777_CBUS_EVT__BURST_WRITE_SUCCEEDED           = 0x0080,
    //!< Scratch Pad writing initiated by @ref SiiDrvAdaptCbusRemoteScratchPadWrite() succeeded
    SII9777_CBUS_EVT__DEVCAP_NOTIFICATION_FAILED      = 0x0100,
    //!< DEVCAP modification notification initiated by @ref SiiDrvAdaptCbusPowSet() failed
    SII9777_CBUS_EVT__DEVCAP_NOTIFICATION_SUCCEEDED   = 0x0200,
    //!< DEVCAP modification notification initiated by @ref SiiDrvAdaptCbusPowSet() succeeded
    SII9777_CBUS_EVT__MSC_SEND_SUCCESSFULLY           = 0x0400
} Sii9777CbusEvt_t;


/**
* @brief VBUS Power Request
*
* @see Sii9777VbusRequestStatusGet()
* @see 
*/

typedef enum
{
    SII9777_VBUS_REQ__NONE              = 0x00,
    //!< No VBUS power request	 
    SII9777_VBUS_REQ__PROVIDE_POWER     = 0x01,
    //!< VBUS power requests to be provided
    SII9777_VBUS_REQ__REMOVE_POWER      = 0x02,
    //!< VBUS power requests to be removed	 
} Sii9777VbusReq_t;


/**
* @brief offset in DEV_CAP, @refer to MHL spec
*
* The offset in DEV_CAP according to MHL spec
* @see SiiDrvAdaptCbusLocalDevcapVideoLinkModeSet(), SiiDrvAdaptCbusLocalDevcapAudioLinkModeSet(), 
*       SiiDrvAdaptCbusLocalDevcapVidepTypeSet(),  SiiDrvAdaptCbusLocalDevcapFeatureFlagSet()
*/
typedef enum
{
    //SII9777_DEVCAP_OFFSET__DEV_STATE          = 0x00,
    //SII9777_DEVCAP_OFFSET__MHL_VERSION        = 0x01,
    SII9777_DEVCAP_OFFSET__DEV_CAT            = 0x02,
    //SII9777_DEVCAP_OFFSET__ADOPTER_ID_H       = 0x03,
    //SII9777_DEVCAP_OFFSET__ADOPTER_ID_L       = 0x04,
    SII9777_DEVCAP_OFFSET__VID_LINK_MODE      = 0x05,
    SII9777_DEVCAP_OFFSET__AUD_LINK_MODE      = 0x06,
    SII9777_DEVCAP_OFFSET__VIDEO_TYPE         = 0x07,
    //SII9777_DEVCAP_OFFSET__LOG_DEV_MAP        = 0x08,
    //SII9777_DEVCAP_OFFSET__BANDWIDTH          = 0x09,
    SII9777_DEVCAP_OFFSET__FEATURE_FLAG       = 0x0A,
    //SII9777_DEVCAP_OFFSET__DEVICE_ID_H        = 0x0B,
    //SII9777_DEVCAP_OFFSET__DEVICE_ID_L        = 0x0C,
    //SII9777_DEVCAP_OFFSET__SCRATCHPAD_SIZE    = 0x0D,
    //SII9777_DEVCAP_OFFSET__INT_STAT_SIZE      = 0x0E,
    //0x0F reserved
} Sii9777DevCapOffset_t;


/**
* @brief POW bit in DEV_CAP, @refer to MHL spec
*
* The supported video link mode of this device.
* @see Sii9777CbusLocalDevcapPowSet()
*/
typedef enum
{
    SII9777_VBUS_REMOVE_POWER   = 0x00,
    SII9777_VBUS_PROVIDE_POWER  = 0x01
} Sii9777DevCapVbusPow_t;

/**
* @brief VID_LINK_MODE in DEV_CAP, @refer to MHL spec
*
* The supported video link mode of this device.
* @see SiiDrvAdaptCbusLocalDevcapVideoLinkModeSet()
*/
typedef enum
{
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_NONE       = 0x00,
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_RGB444     = 0x01,
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_YCBCR444   = 0x02,
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_YCBCR422   = 0x04,
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_PPIXEL     = 0x08,
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_ISLANDS    = 0x10,
    SII9777_DEVCAP_VID_LINK_MODE__SUPP_VGA        = 0x20
    //bit[7:6]: reserved
} Sii9777DevCapVidLinkMode_t;

/**
* @brief AUD_LINK_MODE in DEV_CAP, @refer to MHL spec
*
* The supported audio link mode of this device.
* @see SiiDrvAdaptCbusLocalDevcapAudioLinkModeSet()
*/
typedef enum
{
    SII9777_DEVCAP_AUD_LINK_MODE__NONE    = 0x00,
    SII9777_DEVCAP_AUD_LINK_MODE__AUD_2CH = 0x01,
    SII9777_DEVCAP_AUD_LINK_MODE__AUD_8CH = 0x02
    //bit[7:2]: reserved
} Sii9777DevCapAudLinkMode_t;

/**
* @brief VIDEO_TYPE in DEV_CAP, @refer to MHL spec
*
* The supported video type of this device.
* @see SiiDrvAdaptCbusLocalDevcapVideoTypeSet()
*/
typedef enum
{
    SII9777_DEVCAP_VIDEO_TYPE__NONE           = 0x00,
    SII9777_DEVCAP_VIDEO_TYPE__VT_GRAPHICS    = 0x01,
    SII9777_DEVCAP_VIDEO_TYPE__VT_PHOTO       = 0x02,
    SII9777_DEVCAP_VIDEO_TYPE__VT_CINEMA      = 0x04,
    SII9777_DEVCAP_VIDEO_TYPE__VT_GAME        = 0x08,    //bit[6:7]: reserved
    SII9777_DEVCAP_VIDEO_TYPE__SUPP_VT        = 0x80
} Sii9777DevCapVideoType_t;

/**
* @brief VIDEO_TYPE in DEV_CAP, @refer to MHL spec
*
* The supported video type of this device.
* @see SiiDrvAdaptCbusLocalDevcapFeatureFlagSet()
*/
typedef enum
{
    SII9777_DEVCAP_FEATURE_FLAG__NONE             = 0x00,
    SII9777_DEVCAP_FEATURE_FLAG__RCP_SUPPORT      = 0x01,
    SII9777_DEVCAP_FEATURE_FLAG__RAP_SUPPORT      = 0x02,
    SII9777_DEVCAP_FEATURE_FLAG__SP_SUPPORT       = 0x04,
    SII9777_DEVCAP_FEATURE_FLAG__UCP_SEND_SUPPORT = 0x08,
    SII9777_DEVCAP_FEATURE_FLAG__UCP_RCVD_SUPPORT = 0x10,  //bit[7:5]: reserved
    SII9777_DEVCAP_FEATURE_FLAG__XVYCC_SUPPORT    = 0x20,
    SII9777_DEVCAP_FEATURE_FLAG__RBP_SUPPORT      = 0x40
} Sii9777DevCapFeatureFlag_t;

/**
* @brief MSC Sub-commands
*/
typedef enum
{
    SII9777_MSC_SUB_COMMAND__NONE,
    SII9777_MSC_SUB_COMMAND__RCP        = 0x10,      //!< RCP  sub-command
    SII9777_MSC_SUB_COMMAND__RCPK       = 0x11,      //!< RCPK sub-command
    SII9777_MSC_SUB_COMMAND__RCPE       = 0x12,      //!< RCPE sub-command
    SII9777_MSC_SUB_COMMAND__RAP        = 0x20,      //!< RAP  sub-command
    SII9777_MSC_SUB_COMMAND__RAPK       = 0x21,      //!< RAPK sub-command
    SII9777_MSC_SUB_COMMAND__RBP        = 0x22,      //!< RBP  sub-command
    SII9777_MSC_SUB_COMMAND__RBPK       = 0x23,      //!< RBPK sub-command
    SII9777_MSC_SUB_COMMAND__RBPE       = 0x24,      //!< RBPE sub-command
    SII9777_MSC_SUB_COMMAND__UCP        = 0x30,      //!< UCP  sub-command
    SII9777_MSC_SUB_COMMAND__UCPK       = 0x31,      //!< UCPK sub-command
    SII9777_MSC_SUB_COMMAND__UCPE       = 0x32       //!< UCPE sub-command
} Sii9777MscSubCmd_t;

typedef struct
{
    Sii9777MscSubCmd_t subCmd;
    uint8_t            codeValue;
} Sii9777MscCmd_t;

typedef enum
{
    SII9777_CD_SENSE__NONE              = 0x00,
    SII9777_CD_SENSE__MHL_CABLE         = 0x01,
}Sii9777CdSense_t;

#ifdef __cplusplus
}
#endif

#endif // SII9777_MHL_DATA_H

