#ifndef _HW_HPCPLL_H_
#define _HW_HPCPLL_H_

//Page HISTORY
#define IO_HPCPLL_BASE (IO_VIRT + 0x60000)
#define IO_ARMPLL_BASE (IO_VIRT + 0x60000)
#define IO_LPCPLL_BASE (IO_VIRT + 0x64000)

//Page TABLE
// HPCPLL
#define REG_HPCPLL_CFG0 (IO_HPCPLL_BASE + 0x300)
    #define FLD_RG_HPCPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_HPCPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_HPCPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_HPCPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_HPCPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_HPCPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_HPCPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_HPCPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
#define REG_HPCPLL_CFG2 (IO_HPCPLL_BASE + 0x308)
    #define FLD_RG_HPCPLL_BIAS_LPF_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_HPCPLL_BIAS_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_HPCPLL_CKSEL_MON Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_RG_HPCPLL_REFLVR_OD_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_HPCPLL_REFCK_MON_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_HPCPLL_TST_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_HPCPLL_TST_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_HPCPLL_TST_SEL Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_HPCPLL_TSTCK_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_HPCPLL_TSTOD_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_HPCPLL_A2DCK_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_HPCPLL_DIV2_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_RG_HPCPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]

//ARMPLL
#define REG_ARMPLL_CFG0 (IO_ARMPLL_BASE + 0x200)
    #define FLD_RG_ARMPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_ARMPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_ARMPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_ARMPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_ARMPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_ARMPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_ARMPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_ARMPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
#define REG_ARMPLL_CFG1 (IO_ARMPLL_BASE + 0x204)
    #define FLD_RG_ARMPLL_SDM_PCW Fld(31,1,AC_MSKDW)//[31:1]
    #define FLD_RG_ARMPLL_SDM_PCW_INTEGER Fld(7,25,AC_MSKDW)//[31:25]
    #define FLD_RG_ARMPLL_SDM_PCW_CHG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_ARMPLL_CFG2 (IO_ARMPLL_BASE + 0x208)
    #define FLD_RG_ARMPLL_BIAS_LPF_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_ARMPLL_BIAS_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_ARMPLL_CKSEL_MON Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_RG_ARMPLL_REFLVR_OD_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_ARMPLL_REFCK_MON_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_ARMPLL_TST_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_ARMPLL_TST_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_ARMPLL_TST_SEL Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_ARMPLL_TSTCK_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_ARMPLL_TSTOD_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_ARMPLL_A2DCK_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_ARMPLL_DIV2_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_RG_ARMPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]

//LPCPLL
#define REG_LPCPLL_CFG0 (IO_LPCPLL_BASE + 0x000)
    #define FLD_RG_LPCPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_LPCPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_LPCPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_LPCPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_LPCPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_LPCPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_LPCPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_LPCPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
#define REG_LPCPLL_CFG1 (IO_LPCPLL_BASE + 0x004)
    #define FLD_RG_LPCPLL_SDM_PCW Fld(31,1,AC_MSKDW)//[31:1]
    #define FLD_RG_LPCPLL_SDM_PCW_INTEGER Fld(7,25,AC_MSKDW)//[31:25]
    #define FLD_RG_LPCPLL_SDM_PCW_CHG Fld(1,0,AC_MSKB0)//[0:0]
#define REG_LPCPLL_CFG2 (IO_LPCPLL_BASE + 0x008)
    #define FLD_RG_LPCPLL_BIAS_LPF_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_LPCPLL_BIAS_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_LPCPLL_CKSEL_MON Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_RG_LPCPLL_REFLVR_OD_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_LPCPLL_REFCK_MON_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_LPCPLL_TST_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_LPCPLL_TST_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_LPCPLL_TST_SEL Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_LPCPLL_TSTCK_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_LPCPLL_TSTOD_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_RG_LPCPLL_A2DCK_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_LPCPLL_DIV2_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_RG_LPCPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#endif /* _HW_HPCPLL_H_ */

