/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: drv_display.h $
 *
 * Project:
 * --------
 *
 *
 * Description:
 * ------------
 *
 *
 * Author:
 * -------
 *
 *
 * Last changed:
 * -------------
 * $Author: dtvbm11 $
 *
 * $Modtime: 04/03/23 7:08p $
 *
 * $Revision: #1 $
*************************************************************************/

#ifndef _DRV_DISPLAY_H_
#define _DRV_DISPLAY_H_

#include "typedef.h"
#include "feature.h"
#include "drv_scaler.h"

enum eSyncLockMode {
    eSYNCLOCK_OFF,
    eSYNCLOCK_ON,
    eSYNCLOCK_IGNORED
};

enum eDisplayShiftMode {
    eDisplayShift_Line,
    eDisplayShift_Frame
};

enum eDispRFieldAlign_Source{
    eDispRFieldAlign_S_Field,
	eDispRFieldAlign_S_DispR
};

enum eDispRFieldAlign_Mode{
    eDispRFieldAlign_M_VSFall,
	eDispRFieldAlign_M_VSRise,
	eDispRFieldAlign_M_Delay,	
	eDispRFieldAlign_M_Bypass
};

enum e3DGlasses_Pin{
    e3DGlasses_P_3DR,
	e3DGlasses_P_3DL,
	e3DGlasses_P_3DBL
};

enum e3DGlasses_Source{
    e3DGlasses_S_2EYE,
	e3DGlasses_S_REYE,
	e3DGlasses_S_LEYE,
	e3DGlasses_S_BL,	
	e3DGlasses_S_DISPR,
	e3DGlasses_S_FIELD,
	e3DGlasses_S_IV_VS,
	e3DGlasses_S_IV_HS,
	e3DGlasses_S_BL2,		
};

enum e3DGlasses_Pos{
    e3DGlasses_POS_1stR,
	e3DGlasses_POS_2ndR
};

enum e3DGlasses_Pol{
    e3DGlasses_POl_Bypass,
	e3DGlasses_POl_Reverse
};

enum ePanel_PDP_Type{
	ePanel_PDP_L1R1 = 0,
	ePanel_PDP_L12R12
};

enum eVB1_ControlBit_Edge{
	eVB1_ControlBit_FALLING = 0,
	eVB1_ControlBit_RISING
};

typedef enum {
    E_TIMEGEN_PATH_PQ = 0,
    E_TIMEGEN_PATH_BYPASS_HDMI,
    E_TIMEGEN_PATH_BYPASS_MM,
    E_TIMEGEN_PATH_GFX,
	E_TIMEGEN_PATH_MAX,
}E_TIMEGEN_PATH;

typedef enum {
    E_VB1_PATH_PQ = 0,
    E_VB1_PATH_BYPASS,
	E_VB1_PATH_MAX,
}E_VB1_PATH;
typedef struct
{
	UINT8  u1SetData;
	UINT32 u4HTotal;
	UINT32 u4HActive;
	UINT32 u4HFP;
	UINT32 u4HSyncWidth;	
	UINT32 u4HBP;
	UINT32 u4VTotal;
	UINT32 u4VActive;
	UINT32 u4VFP;
	UINT32 u4VSyncWidth;	
	UINT32 u4VBP;
}LCDTIMING_INFO_T;

typedef enum {
    E_TIMING_TRIGGER_STATE_IDLE     = 0,
    E_TIMING_TRIGGER_STATE_CTRL_BIT = 1,
    E_TIMING_TRIGGER_STATE_TIMING   = 2,
    E_TIMING_TRIGGER_STATE_WAITING  = 3,
    E_TIMING_TRIGGER_STATE_VALID    = 4,
}E_TIMING_TRIGGER_STATE;

typedef enum {
	E_TIMEGEN_TRIGGER_STATE_WAITING =0,
    E_TIMEGEN_TRIGGER_VB1_PATH_WAITING =1,
    E_TIMEGEN_TRIGGER_VB1_PATH = 2,
    E_TIMEGEN_TRIGGER_DECODE_TIMEGEN_WAINTING  = 3,
    E_TIMEGEN_TRIGGER_DECODE_TIMEGEN   = 4,
}E_TIMEGEN_TRIGGER_STATE;

typedef struct
{
    UINT8  u1TriggerState;
    UINT8  u1DCLKType;
    UINT8  u1FrameRate;
    UINT32 u4HTotal;
    UINT32 u4HActive;
    UINT32 u4HFP;
    UINT32 u4HSyncWidth;	
    UINT32 u4HBP;
    UINT32 u4VTotal;
    UINT32 u4VActive;
    UINT32 u4VFP;
    UINT32 u4VSyncWidth;	
    UINT32 u4VBP;
}TIMING_INFO_T;

typedef void (*vDisplayTimingCB)(UINT16 u2Arg);

typedef enum {
    E_DISPLAY_TIMING_CB_H_ACTIVE = 0,
    E_DISPLAY_TIMING_CB_H_TOTAL  = 1,
    E_DISPLAY_TIMING_CB_H_FP     = 2,
    E_DISPLAY_TIMING_CB_H_BP     = 3,
    E_DISPLAY_TIMING_CB_V_ACTIVE = 4,
    E_DISPLAY_TIMING_CB_V_TOTAL  = 5,
    E_DISPLAY_TIMING_CB_V_FP     = 6,
    E_DISPLAY_TIMING_CB_V_BP     = 7,
    E_DISPLAY_TIMING_NUM_OF_CB
}E_DISPLAY_TIMING_CB;


typedef enum {
    E_CONTROL_BIT_CB_3DST = 0,  // 3D Structure
    E_CONTROL_BIT_CB_HSZ,       // H Size
    E_CONTROL_BIT_CB_VSZ,       // V Size
    E_CONTROL_BIT_CB_CRHP,      // Crop H Position
    E_CONTROL_BIT_CB_CRVP,      // Crop V Position
    E_CONTROL_BIT_CB_CRHSZ,     // Crop H Size
    E_CONTROL_BIT_CB_CRVSZ,     // Crop V Size
    E_CONTROL_BIT_CB_AT,        // Aspect Type
    E_CONTROL_BIT_CB_AR,        // Aspect Ratio
    E_CONTROL_BIT_CB_SHSZ,      // SAR H Size
    E_CONTROL_BIT_CB_SVSZ,      // SAR V Size
    E_CONTROL_BIT_CB_CT,        // Codec Type
    E_CONTROL_BIT_CB_RF,        // Double Repeat Flag
    E_CONTROL_BIT_CB_VP,        // Video Path
    E_CONTROL_BIT_CB_CF,        // Color Format
    E_CONTROL_BIT_CB_RA,        // Range
    E_CONTROL_BIT_CB_CBV,       // Contro Bit Valid Flag
    E_CONTROL_BIT_NUM_OF_CB
}E_CONTROL_BIT_VB1_CB;

typedef enum {
    E_CONTROL_BIT_CB_HTOTAL = 0,   // HTOTAL
    E_CONTROL_BIT_CB_VTOTAL,       // V TOTAL
    E_CONTROL_BIT_CB_HSPos,        // H START POS
    E_CONTROL_BIT_CB_VSPos,        // H START POS
    E_CONTROL_BIT_CB_GF,           // Graphic format
    E_CONTROL_BIT_CB_VF,           // valid flag
    E_CONTROL_BIT_NUM_OF_GFX_CB
}E_CONTROL_BIT_GFX_CB;


typedef struct
{
    UINT8  u13DStructure;  //2D:0 SBS:01 TAB:10 FS:11
    UINT32 u4PicHSize;
    UINT32 u4PicVSize;
    UINT32 u4CropHPosition;
    UINT32 u4CropVPosition;
    UINT32 u4CropHSize;
    UINT32 u4CropVSize;
    UINT8  u1AspectType;    //SAR:0  DAR:1
    UINT8  u1AspectRatio;   //0:invalid 1:1.000 2:0.6735.....
    UINT32 u4SarHSize;      //SAR Hsize (valid only when aspect type == 0(SAR) && aspect ratio ==0(invalid) )
    UINT32 u4SarVSize;      //SAR Hsize (valid only when aspect type == 0(SAR) && aspect ratio ==0(invalid) )
    UINT8  u1CodeType;      //0:inknow 1:MPEG 2:MPEG2/AVS 3:MPEG4/Xvid 4:AVC/MVC 5:VC-1 6:RealVideo/VP8/MotionJPEG 7:HEVC 8:VP9
    UINT8  u1DoubleRF;      //1:24hz to 48 0:other
    UINT8  u1VideoPath;     // 0:PQ Path 1:Bypass Path
    UINT8  u1ColorFormat;   // 0:YUV 709 1:YUV 601 2:YUV2020 3:RGB
    UINT8  u1Range;         // 0:limit Range 1:full Range
    UINT8  u1CtrlBitValid;  // 0:invalid 1:valid
    
}CONTROL_BIT_VB1_T;

typedef struct
    {
    UINT32 u4CBHTOTAL;       // HTOTAL
    UINT32 u4CBVTOTAL;       // V TOTAL
    UINT32 u4CBHSPos;        // H START POS
    UINT32 u4CBVSPos;        // H START POS
    UINT32 u4CBGF;           // Graphic format
    UINT32 u4CBVF;           // valid flag
}CONTROL_BIT_GFX_T;

extern BOOL fgPhotoRasterModeIn4k;//4k photo in video path
extern BOOL fg4KSeamlessEnable;
extern void vDrvDisplayInit(void) ;
extern void vDrvRegisterDisplayCB(void);
extern void vDrvSetPanelTiming(void);
extern void vDrvApplyPanelTiming(void);
extern void vDrvVB1VideoMuteTiming(void);
extern void vDrvOutputStageInit(void);
extern void vDrvLCDSetFrame(UINT16 wFrameRate);
extern UINT8 vDrvGetLCDFreq(void) ; 
extern void vDrvCalPanelTiming(UINT8 u1DCLKType, UINT32 u4FrameRate);
extern void vDrvTubeFreqSet(UINT8 bDCLKType) ;
extern void vDrvSetMTKGoodDclk(UINT16 wVERT_LINE, UINT8 bFrameRate) ;
extern void vScanGoodDclkRegion(UINT16 u2StartHsyncFreg, UINT16 u2EndHsyncFreg, UINT16 u2step);
//extern void vSetMTKGoodDclkNSTD(void) ; // for non-std signal
extern void vDrvSwitchMTKGoodDclk(UINT8 bOn_Off) ;
extern UINT8 bDrvCheckMTKGoodStatus(void) ;
extern UINT16 wDrvGetOutputHTotal(void) ;
extern UINT16 wDrvGetOutputVTotal(void) ;
extern void vDrvLVDSPowerOnOff(BOOL fgOnOff);
void vDrvVsyncISRPositionTrigger(UINT16 u2INTRLine);
extern void vDrvLVDSSignalOnOff(BOOL fgOnOff);
extern void vDrvVByOneSignalOnOff(BOOL fgOnOff);
extern void vDrvSetErrorLimit(UINT32 u4Error);

extern void vDrvSetAllMute(UINT8 bOnOff);

extern void vDrvVideoSetMuteColor(UINT8 bPath, UINT32 u4Bg);

extern void vOstgNormProc(void);
extern void OSTG_OnOutputVSync(void);

extern void vDrvSwitchImportProtection(UINT8 bOn_Off);
extern void vDrvFireImportPortection(void);
#ifdef CC_FAST_INIT
extern void vDrvDisplayInit_pm_resume(void);
#endif
extern void vDrvSetDisplayFreeRun(UINT8 bOn_Off);
extern void vDrvSetDDDSCloseloop(UINT8 bOn_Off);
vDisplayTimingCB fpDrvRegisterDisplayTimingUpdateCB(E_TIMEGEN_PATH ePath, E_DISPLAY_TIMING_CB eType, vDisplayTimingCB fpDispTimingCB);

#if defined(CC_MT5890) && defined(CC_SUPPORT_4KBE)
void vDrvVB1ControlBitInit(void);
void vDrvSetVB1ControlBit(void);
void vDrvUpdateVB1ControlBit(CONTROL_BIT_VB1_T* ptVB1ControlBit);
void vDrvdumpControlBitinfo(void);
void vDrvControlBitinfoTrigger(UINT8 u1sel);
void vDrvSetControlBitinfo(UINT8 u1path,UINT8 u1sel2,UINT32 u4value);
#endif

#if defined(SUPPORT_PANEL_GRAPH_MODE)
void vDrvGFXInit(void);
void vDrvSetGFXControlBit(void);
void vDrvSwitchGFXTiming(UINT32 u4Type);
void vDrvSetGFXTiming(UINT8 u1GfxDclkType);
void vDrvApplyGFXTiming(void);
void vDrvSetGFXTimingTriggerState(E_TIMING_TRIGGER_STATE eTriggerState);
void vDrvUpdateGFXControlBit(void);
void vGetGraphModeScalerStatus(void);
void vDrvSetGfxTimingForceUpdated(BOOL fgOnOff);
void vDrvSetGFXScalingRatio(UINT8 u1Path);


extern TIMING_INFO_T GFXTimingInfo;

#endif
extern void vDrvSetVB1ControlBit_Valid(BOOL fgValid);
extern void vDrvSetVB1ControlBit(void);
extern void vDrvTconTopVdoSel(UINT8 u1Mode);
extern UINT8 vDrvGetTconTopVdoSel(void);

void vDrvTurnOnPanel(void);
void vDrvTurnOffPanel(void);

#ifndef CC_MTK_LOADER
#ifdef SUPPORT_DDDS_STEP_TRACKING
void vDrvDDDSStepTrackingOnOff(UINT16 u2OnOff);
void vDrvUpdateDisplayCenterCW(UINT32 u4CW);
#endif
#ifdef CC_SCPOS_3DTV_SUPPORT 
UINT32 u4DrvGetDisp3DModeDclk(void);
UINT8 u1DrvGetDisp3DModeRefreshRate(void);
#endif

#define SUPPORT_50TO60
#define SUPPORT_60TO50
#define SUPPORT_20TO60

#define SUPPORT_50TO60_2D       (1U << 0)
#define SUPPORT_50TO60_3D       (1U << 1)
#define SUPPORT_60TO50_2D       (1U << 2)
#define SUPPORT_60TO50_3D       (1U << 3)
#define SUPPORT_FILM22_48TO120_2D   (1U << 4)
#define SUPPORT_3D_OUTPUT_60   		(1U << 5)
void vDrvSetMotionFlow(UINT8 u1MotionFlow);
void VDP_SetBrowserInput(UINT8 uEnable);
void VDP_SetSpeIPTVS(UINT8 uEnable);
void  vDrvCheck3DOuputFrameRate(void);
UINT32 u4DrvSetCustFRC(UINT32 u4Mask);
UINT32 u4DrvGetCustFRC(void);
void vDrvSetFixedFrameRate(UINT8 u1FrameRate);
UINT8 fgDrvIsFixedFrameRate(void);
UINT32 fgIsSupportFixMode(void);
void vDrvCalPanelFrameRate(UINT16 u2VdoVTotal, UINT32 u4VdoFrameRat);
void vDddsSettingCheck(void);
BOOL fgIs60Hz4KBE(void);
#endif
void vDrvDDDSLockStatus(UINT32 u4Count);
UINT32 u4DrvCalPanelRatio(void);


//extern UINT16   wDISPLAY_WIDTH;
//extern UINT16   wDISPLAY_HEIGHT;
extern UINT8   bDISPLAY_INTERLACE_ENABLE;
//extern UINT32   dwSI_DISPLAY_DCLK_TYPICAL;
//extern UINT32   dwSI_DISPLAY_DCLK_50HZ;
extern UINT8   bSI_DISPLAY_DCLK_TYPE;


extern UINT8 u1SetFlipMirrorConfig(BOOL fgMirrorEn, BOOL fgFlipEn);
extern UINT8 u1GetFlipMirrorConfig(void);
extern UINT32 u4GetFlipMirrorModule(UINT32 u4VdpId);

//Flag for system flip/mirror config
#define SYS_FLIP_CONFIG_ON (1U << 0)
#define	SYS_MIRROR_CONFIG_ON (1U << 1)

#define CC_OSD_MUTE_WA    1

#define INTR_TWO_EYE_RISING     (1U << 0)
#define INTR_TWO_EYE_FALLING    (1U << 1)
#define INTR_LEFT_EYE_RISING    (1U << 2)
#define INTR_LEFT_EYE_FALLING   (1U << 3)
#define INTR_RIGHT_EYE_RISING   (1U << 4)
#define INTR_RIGHT_EYE_FALLING  (1U << 5)
#define INTR_OUTPUT_LINE        (1U << 6)

#define FORCE_DCLK_NORMAL          (0U << 0)
#define FORCE_DCLK_FORCE_48HZ      (1U << 0)
#define FORCE_DCLK_FORCE_2D_50HZ   (1U << 1)
#define FORCE_DCLK_FORCE_3D_50HZ   (1U << 2)
#define FORCE_DCLK_FORCE_2D_60HZ   (1U << 3)
#define FORCE_DCLK_FORCE_3D_60HZ   (1U << 4)

void vDrvSetTCONIrqClear(UINT32 u4INTRSource);
void vDrvGetTCONIrqStatus(UINT32 * u4INTRStatus);
extern void vDrvVsyncISRSetting(UINT16 u2Line, UINT16 u2Mask);
extern void vDrvVsyncISRStatus(void);
UINT8 u1DrvGetVsyncISRFCNTStatus(void);

#if CC_OSD_MUTE_WA
extern UINT8 _bDddsDelayFlag;
#endif

extern UINT32 _u4NSDHTotal;
extern UINT32 _u4NSDVTotal;
extern UINT32 _u4NSDFrameRate;

extern BOOL _fgFRS_ENA;
extern BOOL _fgPanelDynamicChg;

void vVdoOutISRCheckApplyPanelTiming(void);

UINT16 u2DrvGetInternalFrameRate(void);
void vDrvSetInternalFrameRate(UINT16 frameRate);
UINT8 bDrvUpdateInternalFrameRate(void);
UINT8 fgDrvSupport24Hz(void);
UINT32 fgDrvSetMJCToOSTG(UINT32 fgOnOff);
UINT32 fgIsMJCToOSTG(void);
void Panel_SetDisplayShift(BOOL fgEnable, UINT8 u1ShiftMode,UINT8 u1L1DisplayShift, UINT8 u1R2DisplayShift);
void Panel_SetDisplayShiftColor(UINT8 u1ShiftColorB,UINT8 u1ShiftColorG, UINT8 u1ShiftColorR);
void Panel_DISPR_FIELD_Delay(UINT8 u1Tpye, UINT8 u1AlignType,UINT16 u1DelayLine);
void Panel_3DGlassesCTL(UINT8 u1Pin, UINT8 u1Tpye, BOOL fgPol,BOOL fgPos, UINT8 u1DelayFrame, UINT16 u2DelayLine);
void Panel_3DGlassesDelay(UINT8 u1Pin, UINT16 u2DelayLine);
void Panel_3DGlassesRSTCTL(UINT8 u1Tpye, BOOL fgOnOff, UINT16 u2RSTLine);
void Panel_3DGlassesDutyCTL(UINT8 u1Tpye, UINT8 u1DutyH);
void Panel_3DGlassesCTLEn(UINT8 u1Pin, BOOL fgonfff);
void Panel_2ndChannelOnOff(BOOL fgOnfff);
void vDrvDisplaySetPentouchMode(UINT32 fgOnOff);
UINT32 fgDrvDisplayGetPentouchMode(void);
void PanelSupportDynamicChg(BOOL fgEnable);
extern void vDrvVideoDitherInit(void);
extern UINT16 wDrvGetOutputHTotal(void);
extern void wDrvSetOutputHTotal(UINT16 u2HTotal);
extern UINT16 wDrvGetOutputVTotal(void);
extern void wDrvSetOutputVTotal(UINT16 u2VToal);
extern void wDrvSetOutputHActive(UINT16 u2HActive);
extern UINT16 wDrvGetOutputHActive(void);
extern void wDrvSetOutputVActive(UINT16 u2VActive);
extern UINT16 wDrvGetOutputVActive(void);
extern void vDrvSetHsyncFp(UINT16 u2Fp);
extern void vDrvSetHsyncBp(UINT16 u2Bp); 
extern UINT16 wDrvGetHsyncBp(void); 
extern UINT16 wDrvGetHsyncFp(void);
extern void vDrvSetVsyncFp(UINT16 u2VFp);
extern void vDrvSetVsyncBp(UINT16 u2VBp);
extern UINT16 wDrvGetVsyncFp(void);
extern UINT16 wDrvGetVsyncBp(void);
extern UINT16 wDrvGetHsyncWidth(void);
extern UINT16 wDrvGetVsyncWidth(void);
extern void vGetPostScalerStatus(void);
extern void vGetDISP_RStatus(void);
extern void u1SetDISP_REncodeEn(UINT8 u1Enable);
extern void vGetLVDS_HVEncodeStatus(void);
extern void u1SetLVDS_HVEncodeValue(UINT8 u1Enable);
extern void vDrvDisp3DModeChg(UINT8 u13DMode);
extern void vSavePanelAttribute_PDP(void);

extern void vDrvSetSyncLockMode(enum eSyncLockMode eMode);

extern void vDrvSetDDDSFrameTrackTarget(UINT8 u1SlowFast, UINT32 u4TargetVTotal) ;
extern void vDrvSetDDDSFrameTrackMode(UINT8 u1Mode) ;
extern void vDDDSInit_uboot(void);
UINT32 GetPANEL4K2K_TYPE(void);
#ifdef CC_MT5890
void vDrvSwitchOSDRoute(void);
#endif
UINT32 vDrvCal4K2KPanelType(void);
void vDrvSwitchVideoType(UINT32 u4Type);
UINT8 fgIsOSDFromGFX(void);
void vDrvVB1ES3_DEBUG(UINT8 bOn_Off);


enum
{
    E_4K2K_NORMAL = 0,
    E_4K2K_NATIVE,       // 1
    E_4K2K_SPLIT_VDO,    // 2
    E_4K2K_SPLIT_PHOTO,  // 3
    E_4K2K_NORMAL_3D,    // 4
    E_4K2K_PQ_4K1K       // 5
};

enum
{
    E_MLOOP = 0,
    E_MODE_DONE,       // 1
};

#ifdef CC_SUPPORT_4K2K
#define SPLIT_PHOTO_BYP 1

extern UINT8 _u14K2KMode;
extern UINT8 _u1Force4K2KTiming ;
void SetPanel_4k2k(UINT8 u1Mode);
void vExt4k2kFrcInit(void);
void vSend4k2kFrcPanelTypeCmd(UINT32 u4PanelType);
void vSend4k2kFrcModeCmd(UINT8 u1Mode);
UINT16 u2Ext4k2kGetMuteTime(void);
extern void vExt4k2kFrcMute(UINT8 bOn);
extern void vExt4k2kFrcUmMuteTimer(UINT16 u2Timer) ;
extern void Panel4K2KStatus(void);
extern void vPanelAttribute_Status_4k2k(void);

#if defined( CC_MT5861 )   //hybrid mode
extern MDDI_FBM_POOL_T* GetMibFbmPoolPara( UINT8 u1VdpId );
#endif

typedef struct _r4k2kHandler
{
	UINT8 u1Tag;
	UINT8 u1I2CChn ;
	UINT8 u1I2cAddr ;
	UINT8 u1CmdLen;
	UINT8 u13D2DTimingChg;
	UINT16 u2CmdInterval;
	UINT16 u2MuteTime;
	void (*frc_init) (void);
	void (*frc_send_cmd) (UINT8 *pBuf, UINT16 u2Len);
	void (*frc_snd_pnl_type) (UINT32 u4PanelType);
	void (*frc_snd_pnl_mode) (UINT8 u1Mode);
	void (*frc_snd_mute) (UINT8 bOn)   ;
	void  (*frc_snd_protect_window) (UINT8 bWId, UINT16 u2Width, UINT16 u2Height,  UINT16 u2StartX,  UINT16 u2StartY);
	UINT8 *pu1FhdBuf;
	UINT8 u1FhdBufSize;
	UINT8 *pu14k2kBuf;	
	UINT8 u14k2kBufSize;
	UINT8 *pu1VdoModeBuf;		
	UINT8 u1VdoBufSize;	
	UINT8 *pu1PhotoModeBuf;		
	UINT8 u1PhotoBufSize;		
	UINT8 *pu1ResumeBuf;	
	UINT8 u1ResumeBufSize;	
	UINT8 *pu1Fhd3DBuf;	
	UINT8 u1Fhd3DBufSize;		
}r4k2kHandler;

enum
{
    E_4K2K_CMI_RTK = 0,
   	E_4K2K_CMI_MST ,
   	E_4K2K_AUO_MST , 
   	E_4K2K_CSOT_NTK,
};

#endif
#endif
