/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: dtvbm11 $
 * $Date: 2015/11/10 $
 * $RCSfile: hal_io.c,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

/** @file hal_io.c
 *  hal_1176.c provides functions of register access
 */


#include "x_hal_io.h"
#include "x_assert.h"

#if defined(CC_MT5890)
#include "x_hal_5381.h"
#include "hw_mlvds.h"
#include "hw_vbyone.h"
#include "hw_tg.h"
#endif

#ifdef CC_MTK_LOADER
    #undef x_crit_start
    #undef x_crit_end
    #define x_crit_start() 0
    #define x_crit_end(x) UNUSED(x)
    #define CRIT_STATE_T UINT8
#else
    #include "x_os.h"
#endif

#if defined(CC_MT5890)
static UINT32 VByOne_Register_Mapping_E3(UINT32 u4Register)
{

    switch (u4Register)
    {
    case VB1SYS0: return(MLVDS_CTRL_32);
        break;
    case VB1SYS1: return(MLVDS_CTRL_33);
        break;
    case VB1SYS2: return(MLVDS_CTRL_34);
        break;
	case VB1SYS3: return(MLVDS_CTRL_35);
		break;
	case VB1SYS4: return(MLVDS_CTRL_36);
		break;
	case VB1SYS6: return(MLVDS_CTRL_37);
		break;
	case VB1SYS8: return(MLVDS_CTRL_38);
		break;
	case VB1ANA0: return(MLVDS_CTRL_39);
		break;
	case VB1RES:  return(MLVDS_CTRL_40);
		break;
	case VB1ANA2: return(MLVDS_CTRL_41);
		break;
	case VB1ANA3: return(MLVDS_CTRL_42);
		break;
	case VB1ANA4: return(MLVDS_CTRL_43);
		break;
	case VB1ANA5: return(MLVDS_CTRL_44);
		break;
	case VB1ANA6: return(MLVDS_CTRL_45);
		break;
	case VB1ANA7: return(MLVDS_CTRL_46);
		break;
	case VB1ANA8: return(MLVDS_CTRL_47);
		break;
	case VB1OSDSYS0: return(MLVDS_CTRL_48);
		break;
	case VB1OSDSYS1: return(MLVDS_CTRL_49);
		break;
	case VB1OSDSYS2: return(MLVDS_CTRL_50);
		break;
	case VB1OSDSYS3: return(MLVDS_CTRL_51);
		break;
	case VB1OSDSYS4: return(MLVDS_CTRL_52);
		break;
	case VB1OSDSYS6: return(MLVDS_CTRL_53);
		break;
	case VB1OSDSYS8: return(MLVDS_CTRL_54);
		break;
	case VB1OSDANA0: return(MLVDS_CTRL_55);
		break;
	case VB1OSDRES:  return(MLVDS_CTRL_56);
		break;
	case VB1OSDANA2: return(MLVDS_CTRL_57);
		break;
	case VB1OSDANA3: return(MLVDS_CTRL_58);
		break;
	case VB1OSDANA4: return(MLVDS_CTRL_59);
		break;			
	case GR0: return(MLVDS_CTRL_60);
		break;	
	case GR1: return(MLVDS_CTRL_61);
		break;	
	case GR12: return(MLVDS_CTRL_62);
		break;	
		
    default:
        return (u4Register);		
    }
}
#endif

UINT16 u2IO32Read2B(UINT32 reg32)
{
    UINT32 addr=reg32&~3;
    switch(reg32&3)
    {
        default:
        case 0:
        case 2:
            return (*(volatile UINT16 *)(reg32));
        case 1:
            return  ((*(volatile UINT32 *)(addr))>>8)&0xffff;
        case 3:
            ASSERT((reg32&3)<3);
            return  ((*(volatile UINT32 *)(addr))>>24)&0xff;
    }
}

#if defined(FORCE_IO32_1BMSK_FUNCTION) || defined(CC_MTK_LOADER) || defined(CC_UBOOT) || !defined(__KERNEL__)
void vIO32Write1BMsk(UINT32 reg32, UINT32 val8, UINT8 msk8)
{
    CRIT_STATE_T csState;
    UINT32 u4Val, u4Msk;
    UINT8 bByte;
	#if defined(CC_MT5890)
	UINT32 u4MapAddress;
	#endif

    bByte = reg32&3;
    reg32 &= ~3;
    val8 &= msk8;
    u4Msk = ~(UINT32)(msk8<<((UINT32)bByte<<3));

    csState = x_crit_start();
	#if defined(CC_MT5890)
	if((((reg32>=VB1SYS0)&&(reg32<=VB1OSDANA4))||((reg32>=GR0)&&(reg32<=TIM5R7))) && IS_IC_5890_ES3())
	{
		u4MapAddress = VByOne_Register_Mapping_E3(reg32);
		u4MapAddress &= ~3;
	    u4Val = (*(volatile UINT32 *)(u4MapAddress));
	    u4Val = ((u4Val & u4Msk) | ((UINT32)val8 << (bByte<<3)));		
	    (*(volatile UINT32 *)(u4MapAddress)=(u4Val));
	}
	else
	#endif
	{
    u4Val = (*(volatile UINT32 *)(reg32));
    u4Val = ((u4Val & u4Msk) | ((UINT32)val8 << (bByte<<3)));
	}	
    (*(volatile UINT32 *)(reg32)=(u4Val));
    x_crit_end(csState);

}
#endif

void vIO32Write2BMsk(UINT32 reg32, UINT32 val16, UINT16 msk16)
{
    CRIT_STATE_T csState;
    UINT32 u4Val, u4Msk;
    UINT8 bByte;
	#if defined(CC_MT5890)
	UINT32 u4MapAddress;
	#endif

    bByte = reg32&3;
    ASSERT(bByte<3);

    reg32 &= ~3;
    val16 &= msk16;
    u4Msk = ~(UINT32)(msk16<<((UINT32)bByte<<3));

    csState = x_crit_start();
	#if defined(CC_MT5890)
	if((((reg32>=VB1SYS0)&&(reg32<=VB1OSDANA4))||((reg32>=GR0)&&(reg32<=TIM5R7))) && IS_IC_5890_ES3())
	{
		u4MapAddress = VByOne_Register_Mapping_E3(reg32);
		u4MapAddress &= ~3;
	    u4Val = (*(volatile UINT32 *)(u4MapAddress));
	    u4Val = ((u4Val & u4Msk) | ((UINT32)val16 << (bByte<<3)));
	    (*(volatile UINT32 *)(u4MapAddress)=(u4Val));	
	}
	else
	#endif
	{
    u4Val = (*(volatile UINT32 *)(reg32));
    u4Val = ((u4Val & u4Msk) | ((UINT32)val16 << (bByte<<3)));
	}
    (*(volatile UINT32 *)(reg32)=(u4Val));
    x_crit_end(csState);

}

void vIO32Write4BMsk(UINT32 reg32, UINT32 val32, UINT32 msk32)
{
    CRIT_STATE_T csState;
	#if defined(CC_MT5890)
	UINT32 u4MapAddress;
	#endif

    ASSERT((reg32&3)==0);
    val32 &=msk32;

    csState = x_crit_start();
	#if defined(CC_MT5890)
	if((((reg32>=VB1SYS0)&&(reg32<=VB1OSDANA4))||((reg32>=GR0)&&(reg32<=TIM5R7))) && IS_IC_5890_ES3())
	{
		u4MapAddress = VByOne_Register_Mapping_E3(reg32);
		
    	(*(volatile UINT32 *)(reg32)=((*(volatile UINT32 *)(u4MapAddress))&~msk32)|val32);		
    	(*(volatile UINT32 *)(u4MapAddress)=((*(volatile UINT32 *)(u4MapAddress))&~msk32)|val32);				
	}
	else
	#endif
	{
    (*(volatile UINT32 *)(reg32)=((*(volatile UINT32 *)(reg32))&~msk32)|val32);
	}
    x_crit_end(csState);
}

