/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


#include "x_typedef.h"
#include "x_bim.h"
#include "x_dram.h"
#include "drvcust_if.h"
#if defined(CC_SUPPORT_STR_CORE_OFF)
#include "hw_pdwnc.h"
#endif

EXTERN VOID INT_Reset(VOID);
EXTERN VOID INT_Vectors(VOID);

EXTERN VOID CHIP_BootEntry0(VOID);
EXTERN VOID CHIP_BootEntry1(VOID);
EXTERN VOID CHIP_BootEntry2(VOID);
EXTERN VOID CHIP_BootEntry3(VOID);


VOID BSP_Start(VOID);
UINT32 au4BSS[4];
#if defined(CC_NAND_BOOT) || defined(CC_EMMC_BOOT)
EXTERN VOID ARM_InvalidateICache(VOID);
EXTERN VOID __aeabi_llsl(VOID);
EXTERN VOID __aeabi_memclr4(VOID);
EXTERN VOID __aeabi_uidivmod(VOID);
EXTERN VOID x_memcpy(VOID);
EXTERN VOID CHIP_NANDCopyToDRAM(UINT32 *pu4DRAMBuf, UINT32 u4StartOffset, UINT32 u4Len);
#endif /* CC_NANDBOOT */

VOID BSPLinkSymbol(UINT32 fgDisplay)
{
    if (fgDisplay)
    {
        INT_Reset();
        INT_Vectors();
        BSPLinkSymbol(au4BSS[0]);
#if defined(CC_NAND_BOOT) || defined(CC_EMMC_BOOT)
        __aeabi_llsl();     // for llshl.o(c_5.l)
        x_memcpy();         // mem_mgr.o
        __aeabi_uidivmod(); // aeabi_sdiv.o(.text_udiv)
        __aeabi_memclr4();  // rt_memclr_w.o
#endif /* CC_NANDBOOT */
    }
}

#define TIME_START(x) \
    BIM_WRITE32((x), 0x12345678); \
    IO_WRITE32MSK(BIM_BASE, REG_RW_TIMER_CTRL, 0, TMR1_CNTDWN_EN | TMR1_AUTOLD_EN); \
    BIM_WRITE32(REG_RW_TIMER1_LLMT, 0xffffffff); \
    BIM_WRITE32(REG_RW_TIMER1_LOW , 0xffffffff); \
    IO_WRITE32MSK(BIM_BASE, REG_RW_TIMER_CTRL, TMR1_CNTDWN_EN | TMR1_AUTOLD_EN, TMR1_CNTDWN_EN | TMR1_AUTOLD_EN);

#define TIME_END(x) \
    IO_WRITE32MSK(BIM_BASE, REG_RW_TIMER_CTRL, 0, TMR1_CNTDWN_EN | TMR1_AUTOLD_EN); \
    BIM_WRITE32((x), ~BIM_READ32(REG_RW_TIMER1_LOW));

VOID BSP_Start()
{
#ifdef CC_FPGA_SIM

    HalInitMMU(TCMGET_CHANNELA_SIZE() * 0x100000 - 0x4000);
    DhrystoneTest(10);
    do
    {
    }
    while (1);

#endif

    CHIP_BootEntry0();

#if defined(CC_SUPPORT_STR_CORE_OFF) && defined(CC_MTK_PRELOADER)
    // Check for resume from suspend to dram
    extern void CHIP_ResumeFormSuspendMode();
	CHIP_ResumeFormSuspendMode();
#endif   /* CC_SUPPORT_STR_CORE_OFF && CC_MTK_PRELOADER */

    if (!BSP_IsFPGA())
    {
        CHIP_BootEntry1();
        CHIP_BootEntry2();
    }
    CHIP_BootEntry3();
}

