/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: wenming.wu $
 * $Date  $
 * $RCSfile: drv_hdmi.h,v $
 * $Revision: #21 $
 *
 *---------------------------------------------------------------------------*/
#ifndef _DRV_HDMI2_H_
#define _DRV_HDMI2_H_

#include "typedef.h"
#include "x_timer.h"

#define HDMI_RX_NEW_AVI (1<<16)
#define HDMI_RX_NEW_SP (1<<17)
#define HDMI_RX_NEW_AUD (1<<18)
#define HDMI_RX_NEW_MPEG (1<<19)
#define HDMI_RX_NEW_UNREC (1<<20)
#define HDMI_RX_NEW_CP (1<<23)
#define HDMI_RX_INVALID_AVI (1<<28)


#define HDMI_RX_AAC_MUTE (1<<6)
#define HDMI_RX_NEW_ACP (1<<10)
#define HDMI_RX_NEW_VSIF (1<<22)

#define HDMI_RX_NEW_ISRC1 (1<<2)
#define HDMI_RX_NEW_ISRC2 (1<<3)
#define HDMI_RX_NEW_GCP   (1<<4)
#define HDMI_RX_NEW_HF_VSIF (1<<9)

#define HDMI_RX_HDCP2X_INT_AUTH_DONE      (1)
#define HDMI_RX_HDCP2X_INT_AKE_SENT_RCVD  (1<<18)

#define HDMI_RST_ALL    1
#define HDMI_RST_EQ        2
#define HDMI_RST_DEEPCOLOR    3
#define HDMI_RST_FIXEQ        4
#define HDMI_RST_RTCK        5
#define HDMI_RST_DIGITALPHY 6

#define HDMI_AUD_Length_Unknown      0
#define HDMI_AUD_Length_16bits      1
#define HDMI_AUD_Length_17bits      2
#define HDMI_AUD_Length_18bits      3
#define HDMI_AUD_Length_19bits      4
#define HDMI_AUD_Length_20bits      5
#define HDMI_AUD_Length_21bits      6
#define HDMI_AUD_Length_22bits      7
#define HDMI_AUD_Length_23bits      8
#define HDMI_AUD_Length_24bits      9

#define HDMI_ENABLE_EQ_TRACKING_6G 1

enum
{
    HDMI_3D_Structure_FramePacking=0,
    HDMI_3D_Structure_FieldAlternative,
    HDMI_3D_Structure_LineAlternative,
    HDMI_3D_Structure_SideBySideFull,
    HDMI_3D_Structure_LDepth,
    HDMI_3D_Structure_LDepthGraph,
    HDMI_3D_Structure_TopBottom,
    HDMI_3D_Structure_SideBySideHalf=8,
    HDMI_3D_Structure_Unknow
};

enum
{
    HDMI_NOSIGNAL_STATE=0,
    HDMI_WAIT_CONNECT_STATE,
    HDMI_WAIT_STABLE_STATE,
    HDMI_STABLE_STATE
};
typedef enum
{
    HDMI_RX_MODE_DVI,
    HDMI_RX_MODE_HDMI1X,
    HDMI_RX_MODE_HDMI2X,
    HDMI_RX_MODE_MHL
}HdmiRxMode_t;

typedef enum eHDMI_SWITCH_NO {
    HDMI_SWITCH_INIT = 0,
    HDMI_SWITCH_1,
    HDMI_SWITCH_2,
    HDMI_SWITCH_3,
    HDMI_SWITCH_4,
    HDMI_SWITCH_MAX
}E_HDMI_SWITCH_NUM;

typedef enum
{
    HDMI_RX_PORT_Init=0,
    HDMI_RX_PORT_1,
    HDMI_RX_PORT_2,
    HDMI_RX_PORT_3,
    HDMI_RX_PORT_4,
    HDMI_RX_PORT_MAX
}HdmiRxPort;

typedef enum
{
    HDMI_RX_INPUT_TYPE_NONE,
    HDMI_RX_INPUT_TYPE_HDMI,
    HDMI_RX_INPUT_TYPE_MHL,
}HdmiRxInputType_t;


typedef enum
{
    HDMI_RX_CLRSPC_UNKNOW,
    HDMI_RX_CLRSPC_YC444_601,
    HDMI_RX_CLRSPC_YC422_601,
    HDMI_RX_CLRSPC_YC420_601,

    HDMI_RX_CLRSPC_YC444_709,
    HDMI_RX_CLRSPC_YC422_709,
    HDMI_RX_CLRSPC_YC420_709,

    HDMI_RX_CLRSPC_XVYC444_601,
    HDMI_RX_CLRSPC_XVYC422_601,
    HDMI_RX_CLRSPC_XVYC420_601,

    HDMI_RX_CLRSPC_XVYC444_709,
    HDMI_RX_CLRSPC_XVYC422_709,
    HDMI_RX_CLRSPC_XVYC420_709,

    HDMI_RX_CLRSPC_sYCC444_601,
    HDMI_RX_CLRSPC_sYCC422_601,
    HDMI_RX_CLRSPC_sYCC420_601,

    HDMI_RX_CLRSPC_Adobe_YCC444_601,
    HDMI_RX_CLRSPC_Adobe_YCC422_601,
    HDMI_RX_CLRSPC_Adobe_YCC420_601,

    HDMI_RX_CLRSPC_RGB,
    HDMI_RX_CLRSPC_Adobe_RGB,

    HDMI_RX_CLRSPC_BT_2020_RGB_non_const_luminous,
    HDMI_RX_CLRSPC_BT_2020_RGB_const_luminous,

    HDMI_RX_CLRSPC_BT_2020_YCC444_non_const_luminous,
    HDMI_RX_CLRSPC_BT_2020_YCC422_non_const_luminous,
    HDMI_RX_CLRSPC_BT_2020_YCC420_non_const_luminous,

    HDMI_RX_CLRSPC_BT_2020_YCC444_const_luminous,
    HDMI_RX_CLRSPC_BT_2020_YCC422_const_luminous,
    HDMI_RX_CLRSPC_BT_2020_YCC420_const_luminous

}HdmiRxClrSpc_t;

typedef enum
{
    HDMI_RX_BIT_DEPTH_8_BIT,
    HDMI_RX_BIT_DEPTH_10_BIT,
    HDMI_RX_BIT_DEPTH_12_BIT,
    HDMI_RX_BIT_DEPTH_16_BIT
}HdmiRxBitDepth_t;

typedef enum
{
    HDMI_RX_RGB_FULL,
    HDMI_RX_RGB_LIMT,
    HDMI_RX_YCC_FULL,
    HDMI_RX_YCC_LIMT
}HdmiRxRange_t;
typedef enum
{
    HDMI_RX_OVERSCAN=1,
    HDMI_RX_UNDERSCAN
}HdmiRxScanInfo_t;

typedef enum
{
    HDMI_RX_ASPECT_RATIO_4_3=1,
    HDMI_RX_ASPECT_RATIO_16_9
}HdmiRxAspectRatio_t;

typedef enum
{
    HDMI_RX_AFD_SAME=8,
    HDMI_RX_AFD_4_3,
    HDMI_RX_AFD_16_9,
    HDMI_RX_AFD_14_9
}HdmiRxAFDInfo_t;

typedef enum
{
    HDMI_RX_ITC_GRAPHICS=0,
    HDMI_RX_ITC_PHOTO,
    HDMI_RX_ITC_CINEMA,
    HDMI_RX_ITC_GAME
}HdmiRxITCInfo_t;

typedef enum
{
    HDMI_RX_HDCP_LINK_VER_NONE,
    HDMI_RX_HDCP_LINK_VER_HDCP1X,
    HDMI_RX_HDCP_LINK_VER_HDCP22,
}HdmiRxHdcpLinkVer_t;

typedef enum
{
    HDMI_RX_HDCP2_STATUS_OFF=0x0,
    HDMI_RX_HDCP2_STATUS_AUTH_DONE =0x1,
    HDMI_RX_HDCP2_STATUS_AUTH_FAIL=0x2,
    HDMI_RX_HDCP2_STATUS_CCHK_DONE=0x4,
    HDMI_RX_HDCP2_STATUS_CCHK_FAIL=0x8,
    HDMI_RX_HDCP2_STATUS_AKE_SENT_RCVD=0x10,
    HDMI_RX_HDCP2_STATUS_SKE_SENT_RCVD=0x20,
    HDMI_RX_HDCP2_STATUS_CERT_SENT_RCVD=0x40,
    HDMI_RX_HDCP2_STATUS_DECRYPT_SUCCESS=0x80,
    HDMI_RX_HDCP2_STATUS_DECRYPT_FAIL=0x100
}HdmiRxHdcp2Status_t;

typedef enum
{
    HDMI_RX_HDCP1_STATUS_OFF =0x0,
    HDMI_RX_HDCP1_STATUS_AUTH_DONE =0x1,
    HDMI_RX_HDCP1_STATUS_AUTH_FAIL =0x2,
    HDMI_RX_HDCP1_STATUS_DECRYPT_SUCCESS=0x4,
    HDMI_RX_HDCP1_STATUS_DECRYPT_FAIL=0x8
}HdmiRxHdcp1Status_t;

typedef enum
{
    HDMI_RX_AUDIO_FS_24KHZ,
    HDMI_RX_AUDIO_FS_32KHZ,
    HDMI_RX_AUDIO_FS_44_1KHZ,
    HDMI_RX_AUDIO_FS_48KHZ,
    HDMI_RX_AUDIO_FS_88_2KHZ,
    HDMI_RX_AUDIO_FS_96KHZ,
    HDMI_RX_AUDIO_FS_176_4KHZ,
    HDMI_RX_AUDIO_FS_192KHZ,
    HDMI_RX_AUDIO_FS_768KHZ
}HdmiRxAudioFs_t;

typedef enum
{
    HDMI_TMDS_CLOCK_UNKNOW,
    HDMI_TMDS_CLOCK_25,
    HDMI_TMDS_CLOCK_25_35,
    HDMI_TMDS_CLOCK_35_40,
    HDMI_TMDS_CLOCK_40_50,
    HDMI_TMDS_CLOCK_50_80,
    HDMI_TMDS_CLOCK_80_100,
    HDMI_TMDS_CLOCK_100_120,
    HDMI_TMDS_CLOCK_120_140,
    HDMI_TMDS_CLOCK_140_200,
    HDMI_TMDS_CLOCK_200_300
}HdmiTmdsClkRate_t;

typedef enum
{
    MHL_TMDS_CLOCK_UNKNOW,
//    MHL_TMDS_CLOCK_25_37,
    MHL_TMDS_CLOCK_25_35,
    MHL_TMDS_CLOCK_35_37,
//    MHL_TMDS_CLOCK_37_50,
    MHL_TMDS_CLOCK_37_40,
    MHL_TMDS_CLOCK_40_50,
    MHL_TMDS_CLOCK_50_60,
    MHL_TMDS_CLOCK_60_67,
    MHL_TMDS_CLOCK_67_75
}MhlTmdsClkRate_t;


typedef enum
{
    HDMI_AUDIO_FIFO_NORMAL= 0x1,
    HDMI_AUDIO_FIFO_UNDERRUN= 0x2,
    HDMI_AUDIO_FIFO_OVERRUN= 0x4
}HdmiAudFifoStatus_t;

typedef enum
{
    HDMI_TMDS_DATA_CHANNEL_0,
    HDMI_TMDS_DATA_CHANNEL_1,
    HDMI_TMDS_DATA_CHANNEL_2
}HdmiTmdsDataChannel_t;

typedef enum
{
    HDMI_INFO_FRAME_UNKNOWN,
    HDMI_INFO_FRAME_ID_AVI,
    HDMI_INFO_FRAME_ID_SPD,
    HDMI_INFO_FRAME_ID_AUD,
    HDMI_INFO_FRAME_ID_MPEG,
    HDMI_INFO_FRAME_ID_UNREC,
    HDMI_INFO_FRAME_ID_ACP,
    HDMI_INFO_FRAME_ID_VSI,
    HDMI_INFO_FRAME_ID_ISRC0,
    HDMI_INFO_FRAME_ID_ISRC1,
    HDMI_INFO_FRAME_ID_GCP,
    HDMI_INFO_FRAME_ID_HFVSI
}HdmiInfoFrameID_t;

enum
{
    HDMI_SPD_NONE_CHG,
    HDMI_SPD_CLEAR,//no SPD
    HDMI_SPD_CHG_TOUP,
    HDMI_SPD_CHG_TONONUP,
    HDMI_SPD_CHG_TOSV,
    HDMI_SPD_CHG_TONONSV,
};

enum
{
    HDMI_SPD_NONE_STATUS,
    HDMI_SPD_UP_UNDET,//Without specific pattern
    HDMI_SPD_UP_DETED,//With specific pattern
    HDMI_SPD_SV_UNDET,
    HDMI_SPD_SV_DETED,
};

typedef struct
{
    HdmiRxClrSpc_t clrSpc;
    HdmiRxRange_t range;
}HdmiVideoInfo_t;

typedef struct
{
    BOOL fgItc;
    HdmiRxITCInfo_t ItcContent;
}HdmiItcInfo_t;

typedef struct
{
    UINT8 HDMI_3D_Enable;
    UINT8 HDMI_3D_Video_Format;
    UINT8 HDMI_3D_Structure;
    UINT8 HDMI_3D_EXTDATA;
}HdmiVideo3DInfo_t;

typedef struct
{
    UINT8 layout;
    UINT8 dsd;
    UINT8 hbrA;
    HdmiRxAudioFs_t audioFs;
}HdmiRxAudioFormat_t;

typedef struct
{
    UINT8 u1CategoryCode;
    UINT8 u1WordLength;
    UINT8 u1b1;
    UINT8 u1b2;
    UINT8 u1b3;
    BOOL fgCopyRight;
    BOOL fgIsPCM;
}HdmiRxAudioChannelStatus_t;

typedef struct
{
    BOOL fgIsAudMute;
    HdmiRxAudioFormat_t audFormat;
    HdmiRxAudioChannelStatus_t chlStatus;
}HdmiRxAudioInfomation_t;

typedef struct
{
    HdmiInfoFrameID_t u1InfoID;
    UINT8 u1InfoData[32];
}HdmiRxInfo_t;

typedef struct
{
    UINT32 u4Header;
    UINT32 au4VdrName[2];//Vendor Name Chacter VN1 TO VN8, 8 bytes.
    UINT32 au4PrdDspt[4];//Product Description Chacter PD1 TO PD16,16 bytes.
    UINT8 u1SrcInfo;
}HdmiSpdParse_t;

typedef struct
{
    UINT32 _u4HTotal;
    UINT32 _u4VTotal;
    UINT32 _u4Width;
    UINT32 _u4Height;
}HdmiRxRes_t;

typedef struct
{
    UINT8 u1ScramblingOn;
    UINT8 u1ClkRatio;
}HdmiScdcStatus_t;

typedef enum
{
    HDMI_RX_HDCP2X_AUTH_OFF=0,
    HDMI_RX_HDCP2X_AUTH_AKE_SENT_RCVD,
    HDMI_RX_HDCP2X_AUTH_AUTH_DONE
}HDMI_RX_HDCP2X_AUTH_STATUS_T;

typedef struct
{
  UINT8 _bHdmiCmd;
  UINT8 _bHDMIState;
  UINT8 _bHDMIStateOld;
  UINT8 _bHDMIPower5vStatus;
  UINT8 _bHdmiPlug;
  UINT8 _bUnplugFlag;
  UINT8 _bHDMIAvMute;
  UINT16 _bHDMIRxBaseAddr;
  UINT16 _bHDMIAnaBaseAddr;
  UINT8 _bHDMICkdt;
  UINT8 _bHDMIScdt;
  UINT8 _bHDMIScdtLose;
  UINT8 _bHDMIHpdTimerCnt;
  UINT8 _bHDMIHdcp1xGood;
  UINT8 _bHDMIHdcp2xNoExistCnt;
  BOOL _fgIsHDMIHdcp2xExist;
  UINT8 _bSCDTdelay;
  UINT8 _bHDMIResStableCnt;
  UINT8 _bHDMIResUnStableCnt;
  UINT8 _bIs422;
  UINT8 _bHDMIFastSW;
  UINT8 _bResv1;
  UINT8 _bNoVsiCount;
  UINT8 _bNoSpdCount;
  UINT8 _bNo4KPsCount;
  UINT8 _bHDMIEqTracking;
  UINT8 _bHDMIEqCh0;
  UINT8 _bHDMIEqCh1;
  UINT8 _bHDMIEqCh2;
  UINT16 _bHDMIEqTrackingWaitCnt;
  UINT16 _bHDMIEqTrackingStableCnt;
  UINT32 _dwHDMIClkKhz;
  BOOL _fgHDMI40xMode;
  UINT8 _bSpdStatus;
  UINT8 _bSpdUpStaChg;
  UINT8 _b4KPsStatus;
  UINT8 _bNoAcpCount;
  UINT8 _bHdrEOTF;
  BOOL _fgFirstAnaSetting;
  HAL_TIME_T _rHdrReceiveTime;
  HAL_TIME_T _rHDMIEqTrackingStart;
  UINT8 _bDolbyVision;
  UINT8 _bDolbyVisionOld;

  HdmiRxMode_t _HdmiMode;
  HdmiRxInputType_t _ConnectType;
  HdmiRxClrSpc_t _HdmiClrSpc;
  HdmiRxBitDepth_t _HdmiDepth;
  HdmiRxRange_t _HdmiRange;
  HdmiRxScanInfo_t _HdmiScan;
  HdmiRxAspectRatio_t _HdmiAspect;
  HdmiRxAFDInfo_t    _HdmiAFD;
  HdmiItcInfo_t     _HdmiITC;
  HdmiVideo3DInfo_t _Hdmi3DInfo;
  HdmiRxHdcpLinkVer_t _HdcpLinkVer;
  HdmiRxHdcp1Status_t _Hdcp1xState;

  HdmiRxRes_t    _ResInfo;
  HdmiScdcStatus_t _ScdcInfo;
  HdmiRxInfo_t _AviInfo;
  HdmiRxInfo_t _SpdInfo;
  HdmiRxInfo_t _AudInfo;
  HdmiRxInfo_t _MpegInfo;
  HdmiRxInfo_t _UnrecInfo;
  HdmiRxInfo_t _AcpInfo;
  HdmiRxInfo_t _VsiInfo;
  HdmiRxInfo_t _Isrc0Info;
  HdmiRxInfo_t _Isrc1Info;
  HdmiRxInfo_t _GcpInfo;
  HdmiRxInfo_t _HfVsiInfo;
  HdmiRxAudioInfomation_t _AudStatus;
  BOOL _fgFirstEnterAuthDone;
  UINT8 _bHDMIHDCP2xHandlerCnt;
  UINT8 _bHDMIHDCP2xErrCnt;
  HDMI_RX_HDCP2X_AUTH_STATUS_T _eHdcp2xAuthStatus;
} HdmiRxObject_t;

typedef struct HDMI_PORT_INFO_T
{
    UINT8 u1UIPortId;           ///< HDMI UI Port ID, Port ID should start from 1 which corresponds to HDMI "port 1".
    UINT8 u1DriverPortId;       ///< HDMI  Driver Port ID
    BOOL bEnable;               ///<HDMI Driver Port Enable
    BOOL bCECSupport;           ///<CEC Support
    BOOL bARCSupport;           ///<ARC Support
} HDMI_PORT_INFO_T;

typedef struct HDMI_PORTS_INFO_T
{
    UINT8 u1PortNum;           ///< the number of HDMI ports in the system
    HDMI_PORT_INFO_T rHdmiPortInfo[HDMI_RX_PORT_MAX-1];
} HDMI_PORTS_INFO_T;

typedef void (*DRIVER_HDMI_ACP_CHG_CB)(UINT8 u1HdmiAcp,void* pvTag);

extern HdmiRxPort eHDMICurrSwitch;
extern void vHDMIHPDHigh(HdmiRxPort eSwitch);
extern void vHDMIHPDLow(HdmiRxPort eSwitch);
extern UINT8 bHDMIPort5VStatus(HdmiRxPort ePort);
extern void vHDMI2Init(void);
extern void vHDMI2RxInit(HdmiRxPort ePort);
extern void vHDMI2HwInit(HdmiRxPort ePort);
extern void vHDMI2MainLoop(void);
extern void vHDMI2TMDSCTRL(HdmiRxPort ePort,BOOL bOnOff);
extern void vHDMI2DDCBusCTRL(HdmiRxPort ePort,BOOL bOnOff);
extern UINT16 u2HDMI2GetDigBaseAddr(HdmiRxPort ePort);
extern UINT16 u2HDMI2GetAnaBaseAddr(HdmiRxPort ePort);
extern UINT8 u1HDMI2_Get5VStatus(HdmiRxPort ePort);
extern void vHDMI2PortSel(HdmiRxPort ePort,UINT8 u1Type);
extern void vHDMI2PllSel(HdmiRxPort ePort,UINT8 u1Type);
extern void vHDMI2SetLateResumeFlag(BOOL fgLateResume);
extern BOOL bHDMI2IsSupport6G(HdmiRxPort ePort);
extern UINT8 u1HDMI2GetMhlPortId(void);
extern UINT32 u4GetHdmi2RegBase(HdmiRxPort ePort);
extern UINT32 u4GetHdmi2AnalogRegBase(HdmiRxPort ePort);
extern void vHDMI2SetStateMachine(HdmiRxPort ePort,UINT8 u1HdmiSta);
extern UINT8 bHDMI2GetStateMachine(HdmiRxPort ePort);
extern void vHDMI2StopFw(HdmiRxPort ePort);
extern void vHDMI2ResumeFw(HdmiRxPort ePort);
extern UINT8 u1HDMI2IsUnplug(HdmiRxPort ePort);
extern void vHDMI2ClrUnplug(HdmiRxPort ePort);
extern void vHDMI2SetUnplug(HdmiRxPort ePort);
extern UINT8 u1HDMI2IsHpdPulse(HdmiRxPort ePort);
extern void vHDMI2SetHpdPulse(HdmiRxPort ePort,UINT8 u1Val);
extern UINT8 u1HDMI2IsSyncLose(HdmiRxPort ePort);
extern void vHDMI2SetSyncLose(HdmiRxPort ePort,UINT8 u1Val);
extern void vHDMI2EQCIRCUITCTRL(HdmiRxPort ePort,BOOL bOnOff);
extern BOOL fgHDMI2GetDuleMode(HdmiRxPort ePort);
extern BOOL fgHDMI2SignalPresent(HdmiRxPort ePort);
extern BOOL fgHDMI2Get420Mode(HdmiRxPort ePort);
extern void vHDMI2SetSplit(HdmiRxPort eHdmiPort, UINT8 u1En);
extern BOOL fgHDMI2IsPixelRepeate(HdmiRxPort ePort);
extern UINT8 bHDMI2AudStatus(void);
extern BOOL fgHDMI2IsPCM(HdmiRxPort ePort);
extern UINT8 bHDMI2InputType(HdmiRxPort ePort);
extern UINT8 bHDMI2Clocrimetry(HdmiRxPort ePort);
extern UINT8 bGetHDMIRangeMode(void);
extern void vSetHDMIRangeMode(UINT8 bMode);
extern HdmiRxBitDepth_t bHDMI2DeepColorStatus(HdmiRxPort ePort);
extern BOOL fgHDMISupportAudio(void);
extern UINT8 bHDMI2RgbRange(HdmiRxPort ePort);
extern void vHDMI2AudStatusSet(HdmiRxPort ePort,UINT8 u1On);
extern UINT8 bHDMI2AudBitWidth(HdmiRxPort ePort);
extern UINT8 u1HDMI2GetAudioSamplingFreq(void);
extern UINT8 bHDMI2ScanInfo(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2AspectRatio(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2AFD(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2422Input(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2ITCFlag(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2ITCContent(HdmiRxPort eHdmiPort);
extern UINT8 bHDMIHDCP1StatusGet(HdmiRxPort eHdmiPort);
extern UINT8 bHDMIHDCP2StatusGet(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2GetInfoFrameToIF(HdmiRxPort eHdmiPort,HdmiRxInfo_t *ptInfo,UINT8 u1Type);
extern UINT8 u1HDMI2GetUPStatus(HdmiRxPort eHdmiPort);
extern UINT8 u1HDMI2GetUPStaChg(HdmiRxPort eHdmiPort);
extern UINT8 u1HDMI2Get4KPStatus(HdmiRxPort eHdmiPort);
extern void vHDMI2SetAcpChgCallback(DRIVER_HDMI_ACP_CHG_CB pfAcpChgCb,void *tag);
extern UINT8 u1HDMI2GetHdrEOTF(HdmiRxPort eHdmiPort);
#ifdef __MODEL_slt__
extern BOOL bHDMI2SltCRCSample(HdmiRxPort eHdmiPort);
extern BOOL bHDMI2SltCRCCheck(HdmiRxPort eHdmiPort);
#endif
extern void vHDMI2PrintHdcp14Status(HdmiRxPort eHdmiPort);
extern void vHDMI2PrintHdcp22Status(HdmiRxPort eHdmiPort);
extern void vHDMI2PrintHdmiGeneralStatus(HdmiRxPort eHdmiPort);
extern void vHDMI2PrintHdmiVideoStatus(HdmiRxPort eHdmiPort);
extern void vHDMI2PrintHdmiAudioStatus(HdmiRxPort eHdmiPort);
extern void vHDMI2PrintHdmiStatus(HdmiRxPort eHdmiPort);
extern void vHDMI2ClrStableStatus(HdmiRxPort ePort);
extern UINT8 u1IsHDMI2Stable(HdmiRxPort ePort);
extern void vHDMI2PhyReset(HdmiRxPort ePort, UINT8 resettype);
extern void vHDMI2VideoMute(HdmiRxPort ePort,UINT8 u1En);
extern void HDMI2_pm_suspend(void);
extern void HDMI2_pm_resume(void);
extern void vHDMISpdifOutEnable(BOOL fgEnable);
extern BOOL fgIsHDMI2HDCP2xExist(HdmiRxPort ePort);
extern void vSetHdmi2FastSw(HdmiRxPort ePort, UINT8 u1Val);
extern UINT8 u1IsHdmi2FastSw(HdmiRxPort ePort);
extern UINT32 u4HDMI2GetCurrentTmdsClkKhz(HdmiRxPort ePort);
extern HdmiTmdsClkRate_t bHDMI2GetRefClkRate(HdmiRxPort ePort);
extern void vHDMISetSwitch(HdmiRxPort eSwitch,UINT8 u1Type);
extern HdmiRxClrSpc_t eHDMI2GetHdmiClrSpc(HdmiRxPort eHdmiPort);
extern UINT8 bHDMI2GetHdmiMode(HdmiRxPort eHdmiPort);
extern void vHDMI2AudChannelStatus(HdmiRxPort ePort, BOOL *pfgCopyright, UINT8 *pu1CategoryCode,
                           UINT8 *p1WordLength, BOOL *pfgIsPcm);
extern UINT8 bHDMI2GetAudChannelNum(HdmiRxPort ePort);
extern BOOL fgHDMI2AudioPCMMode(void);
#ifdef CC_HDMI_PORTID_PHY_VIR_MAPPING
extern void vHDMIPortInfoInit(void);
extern void vHDMIGetPortsInfo(HDMI_PORTS_INFO_T* prPortsInfo);
extern E_HDMI_SWITCH_NUM eHDMIGetPhysicalPortId(E_HDMI_SWITCH_NUM eVirPort);
extern E_HDMI_SWITCH_NUM eHDMIGetVirtualPortId(E_HDMI_SWITCH_NUM ePhyPort);
#endif//CC_HDMI_PORTID_PHY_VIR_MAPPING
extern UINT8 u1HDMI2GetDolbyVision(HdmiRxPort eHdmiPort);
#endif

