/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


#ifndef _HW_MHL_H_
#define _HW_MHL_H_
#include "x_hal_5381.h"

//ecbus analog regs
#define IO_MHL3_ECBUS_BASE 0x62400

#define REG_ECBUSNORM_CFG0 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x00)
    #define RG_ECBUS_0_PWD Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_ECBUS_0_LDO_IBIAS Fld(2,13,AC_MSKB1)//[14:13]
    #define RG_ECBUS_0_LDO_IBIAS_SEL Fld(2,11,AC_MSKB1)//[12:11]
    #define RG_ECBUS_0_LDO_VREF Fld(3,8,AC_MSKB1)//[10:8]
    #define RG_ECBUS_0_LDO_VREF_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define RG_ECBUS_0_LDO_RESERVE Fld(7,0,AC_MSKB0)//[6:0]
#define REG_ECBUSNORM_CFG1 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x04)
    #define RG_ECBUS_0_CBUS_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_ECBUS_0_COC_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_ECBUS_0_COC_DR_SLEW Fld(4,24,AC_MSKB3)//[27:24]
    #define RG_ECBUS_0_COC_CLAMP_CTL Fld(8,16,AC_FULLB2)//[23:16]
	#define RG_ECBUS_0_COC_CLAMP_CTL_4 Fld(1,20,AC_MSKB2)//[20]    
    #define RG_ECBUS_0_COC_ICTL Fld(3,8,AC_MSKB1)//[10:8]
    #define RG_ECBUS_0_COC_FILTER_BW Fld(2,6,AC_MSKB0)//[7:6]
    #define RG_ECBUS_0_COC_IGEN_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define RG_ECBUS_0_COC_INIT_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define RG_ECBUS_0_COC_FILTER_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define RG_ECBUS_0_COC_TERM_CTL Fld(3,0,AC_MSKB0)//[2:0]
#define REG_ECBUSNORM_CFG2 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x08)
    #define RG_ECBUS_0_GATE_CLK_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_ECBUS_0_INT_OSC_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RG_ECBUS_0_FM_SEL Fld(6,8,AC_MSKB1)//[13:8]
    #define RG_ECBUS_0_EN_5MEG Fld(1,7,AC_MSKB0)//[7:7]
    #define RG_ECBUS_0_DAC_ICTRL Fld(2,5,AC_MSKB0)//[6:5]
    #define RG_ECBUS_0_OSC_5M_CTL Fld(5,0,AC_MSKB0)//[4:0]
#define REG_ECBUSNORM_CFG3 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x0C)
    #define RG_ECBUS_0_PLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_ECBUS_0_PLL_FBKDIV Fld(7,24,AC_MSKB3)//[30:24]
    #define RG_ECBUS_0_PLL_DDSFBK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define RG_ECBUS_0_PLL_RLH_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define RG_ECBUS_0_PLL_FBKSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define RG_ECBUS_0_PLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define RG_ECBUS_0_PLL_POSDIV Fld(2,16,AC_MSKB2)//[17:16]
    #define RG_ECBUS_0_PLL_IC Fld(4,12,AC_MSKB1)//[15:12]
    #define RG_ECBUS_0_PLL_IR Fld(4,8,AC_MSKB1)//[11:8]
    #define RG_ECBUS_0_PLL_BP Fld(4,4,AC_MSKB0)//[7:4]
    #define RG_ECBUS_0_PLL_BC Fld(2,2,AC_MSKB0)//[3:2]
    #define RG_ECBUS_0_PLL_BR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_ECBUSNORM_CFG4 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x10)
    #define RG_ECBUS_0_PLL_AUTOK_LOAD Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_ECBUS_0_PLL_DIVEN Fld(3,28,AC_MSKB3)//[30:28]
    #define RG_ECBUS_0_PLL_AUTOK_KS Fld(2,26,AC_MSKB3)//[27:26]
    #define RG_ECBUS_0_PLL_AUTOK_KF Fld(2,24,AC_MSKB3)//[25:24]
    #define RG_ECBUS_0_PLL_AUTOK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define RG_ECBUS_0_PLL_BAND Fld(7,16,AC_MSKB2)//[22:16]
    #define RG_ECBUS_0_PLL_MONCK_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define RG_ECBUS_0_PLL_MONVC_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define RG_ECBUS_0_PLL_MONREF_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define RG_ECBUS_0_PLL_LVROD_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RG_ECBUS_0_PLL_BIAS_LPF_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define RG_ECBUS_0_PLL_BIAS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define RG_ECBUS_0_PLL_RST_DLY Fld(2,8,AC_MSKB1)//[9:8]
    #define RG_ECBUS_0_PLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_ECBUSNORM_CFG5 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x14)
    #define RG_ECBUS_0_PLL_BRA Fld(1,28,AC_MSKB3)//[28:28]
    #define RG_ECBUS_0_PLL_BCA Fld(1,24,AC_MSKB3)//[24:24]
    #define RG_ECBUS_0_PLL_DIVENA Fld(3,20,AC_MSKB2)//[22:20]
    #define RG_ECBUS_0_PLL_ICADJ Fld(2,18,AC_MSKB2)//[19:18]
    #define RG_ECBUS_0_PLL_KVSEL Fld(2,16,AC_MSKB2)//[17:16]
    #define RG_ECBUS_0_PLL_VCO_BAND Fld(5,8,AC_MSKB1)//[12:8]
    #define RG_ECBUS_0_3G_CLK_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define RG_ECBUS_0_REF_CLK_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define RG_ECBUS_0_PLL_DIVCTRL Fld(2,4,AC_MSKB0)//[5:4]
    #define RG_ECBUS_0_PLL_DETEN Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_ECBUS_0_PLL_DIV2_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define REG_ECBUSNORM_CFG6 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x18)
    #define RG_ECBUS_0_DEEPPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define RG_ECBUS_0_DEEPPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define RG_ECBUS_0_DEEPPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define RG_ECBUS_0_DEEPPLL_LVROD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define RG_ECBUS_0_DEEPPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define RG_ECBUS_0_DEEPPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define RG_ECBUS_0_DEEPPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define RG_ECBUS_0_DEEPPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define RG_ECBUS_0_DEEPPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define RG_ECBUS_0_DEEPPLL_CKSEL_MON Fld(2,10,AC_MSKB1)//[11:10]
    #define RG_ECBUS_0_DEEPPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define RG_ECBUS_0_DEEPPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define REG_ECBUSNORM_CFG7 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x1C)
    #define RG_ECBUS_0_REV Fld(32,0,AC_FULLDW)//[31:0]
    #define RG_ECBUS_0_REV_31 Fld(1,31,AC_MSKB3)
    #define RG_ECBUS_0_REV_30 Fld(1,30,AC_MSKB3)    
    #define RG_ECBUS_0_REV_29 Fld(1,29,AC_MSKB3) 
    #define RG_ECBUS_0_REV_28 Fld(1,28,AC_MSKB3) 
    #define RG_ECBUS_0_REV_27 Fld(1,27,AC_MSKB3)
    #define RG_ECBUS_0_REV_26 Fld(1,26,AC_MSKB3)
    #define RG_ECBUS_0_REV_25_23 Fld(3,23,AC_MSKW32)   
    #define RG_ECBUS_0_REV_22 Fld(1,22,AC_MSKB2)  
    #define RG_ECBUS_0_REV_21_14 Fld(8,14,AC_MSKW21)  
    #define RG_ECBUS_0_REV_13_10 Fld(4,10,AC_MSKB1)    
    #define RG_ECBUS_0_REV_9 Fld(1,9,AC_MSKB1)
    #define RG_ECBUS_0_REV_8 Fld(1,8,AC_MSKB1)
    #define RG_ECBUS_0_REV_7_6 Fld(2,6,AC_MSKB0)
    #define RG_ECBUS_0_REV_5 Fld(1,5,AC_MSKB0)
    #define RG_ECBUS_0_REV_4 Fld(1,4,AC_MSKB0)    
    #define RG_ECBUS_0_REV_3 Fld(1,3,AC_MSKB0)   
    #define RG_ECBUS_0_REV_2 Fld(1,2,AC_MSKB0)  
    #define RG_ECBUS_0_REV_1_0 Fld(2,0,AC_MSKB0) 
#define RGS_ECBUSNORM_CFG0 (IO_VIRT + IO_MHL3_ECBUS_BASE + 0x20)
    #define RGS_ECBUS_0_PLL_AUTOK_PASS Fld(1,9,AC_MSKB1)//[9:9]
    #define RGS_ECBUS_0_PLL_AUTOK_FAIL Fld(1,8,AC_MSKB1)//[8:8]
    #define RGS_ECBUS_0_PLL_AUTOK_BAND Fld(7,0,AC_MSKB0)//[6:0]


#define IO_VIRT_MHL (IO_VIRT)
#define IO_MHL_BASE (0x40000)

//Page CBUS
#define ECBUS_TOP_REV (IO_VIRT_MHL + IO_MHL_BASE + 0x000)
    #define ECBUS_TOP_VER Fld(32,0,AC_FULLDW)//[31:0]
#define ECBUS_TOP_CLK_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x004)
    #define REG_OCLK_DIV Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_CLK_5M_DIV Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_COC_CLK_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_FREQUENCY_METER_RST Fld(1,14,AC_MSKB1)//[14:14]
#define ECBUS_TOP_RST_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x008)
    #define REG_TDM_LCLK_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_TDM_LCLK_TX_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_TDM_LCLK_RX_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_OCLK_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_COC_CLK_RST Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_EMSC_LCLK_RST Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_EMSC_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_EDID_RST Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_DIV20SYNC_RST Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_RCKOUT_RST Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_CBUS_CLK_RST Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_CBUS_DISC_RST Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_CBUS_LCLK_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_FQM_RST Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_IMP_CALIB_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_SWING_CALIB_RST Fld(1,16,AC_MSKB2)//[16:16]
#define ECBUS_TOP_MISC_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x00C)
    #define RG_COCSNK_GAIN_CTRL Fld(4,0,AC_MSKB0)//[3:0]
    #define ECBUS_MON_SEL Fld(4,28,AC_MSKB3)//[31:28]
#define ECBUS_EDID_DEV0 (IO_VIRT_MHL + IO_MHL_BASE + 0x010)
    #define SW_RST0 Fld(1,31,AC_MSKB3)//[31:31]
    #define DE_CNT0 Fld(8,20,AC_MSKW32)//[27:20]
    #define DEGLITCH0_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EDID0_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define DEVICE_ADDR0 Fld(7,1,AC_MSKB0)//[7:1]
#define ECBUS_EDID_DEV1 (IO_VIRT_MHL + IO_MHL_BASE + 0x014)
    #define SW_RST1 Fld(1,31,AC_MSKB3)//[31:31]
    #define DE_CNT1 Fld(8,20,AC_MSKW32)//[27:20]
    #define DEGLITCH1_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EDID1_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define DEVICE_ADDR1 Fld(7,1,AC_MSKB0)//[7:1]
#define ECBUS_EDID_DEV2 (IO_VIRT_MHL + IO_MHL_BASE + 0x018)
    #define SW_RST2 Fld(1,31,AC_MSKB3)//[31:31]
    #define DE_CNT2 Fld(8,20,AC_MSKW32)//[27:20]
    #define DEGLITCH2_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EDID2_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define DEVICE_ADDR2 Fld(7,1,AC_MSKB0)//[7:1]
#define ECBUS_EDID_DEV3 (IO_VIRT_MHL + IO_MHL_BASE + 0x01C)
    #define SW_RST3 Fld(1,31,AC_MSKB3)//[31:31]
    #define DE_CNT3 Fld(8,20,AC_MSKW32)//[27:20]
    #define DEGLITCH3_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define EDID3_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define DEVICE_ADDR3 Fld(7,1,AC_MSKB0)//[7:1]
#define ECBUS_EDID_CTL1 (IO_VIRT_MHL + IO_MHL_BASE + 0x024)
    #define PHY_ADDR1 Fld(16,16,AC_FULLW32)//[31:16]
    #define OFFSET1 Fld(8,8,AC_FULLB1)//[15:8]
    #define CHKSUM1 Fld(8,0,AC_FULLB0)//[7:0]
#define ECBUS_EDID_CTL2 (IO_VIRT_MHL + IO_MHL_BASE + 0x028)
    #define PHY_ADDR2 Fld(16,16,AC_FULLW32)//[31:16]
    #define OFFSET2 Fld(8,8,AC_FULLB1)//[15:8]
    #define CHKSUM2 Fld(8,0,AC_FULLB0)//[7:0]
#define ECBUS_EDID_CTL3 (IO_VIRT_MHL + IO_MHL_BASE + 0x02C)
    #define PHY_ADDR3 Fld(16,16,AC_FULLW32)//[31:16]
    #define OFFSET3 Fld(8,8,AC_FULLB1)//[15:8]
    #define CHKSUM3 Fld(8,0,AC_FULLB0)//[7:0]
#define ECBUS_EDID_ADDR (IO_VIRT_MHL + IO_MHL_BASE + 0x030)
    #define ADDR_FIX Fld(1,8,AC_MSKB1)//[8:8]
    #define EDID_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define ECBUS_EDID_DATA (IO_VIRT_MHL + IO_MHL_BASE + 0x034)
    #define EDID_DATA Fld(8,0,AC_FULLB0)//[7:0]
#define ECBUS_EDID_SDA_SEL (IO_VIRT_MHL + IO_MHL_BASE + 0x03C)
    #define STOP_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define START_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define ECBUS_EDID_DET (IO_VIRT_MHL + IO_MHL_BASE + 0x040)
    #define DEV3 Fld(7,25,AC_MSKB3)//[31:25]
    #define DEV2 Fld(7,17,AC_MSKB2)//[23:17]
    #define DEV1 Fld(7,9,AC_MSKB1)//[15:9]
    #define DEV0 Fld(7,1,AC_MSKB0)//[7:1]
#define ECBUS_EDID_INTSTA (IO_VIRT_MHL + IO_MHL_BASE + 0x044)
    #define DEV3_DET_INT Fld(1,3,AC_MSKB0)//[3:3]
    #define DEV2_DET_INT Fld(1,2,AC_MSKB0)//[2:2]
    #define DEV1_DET_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define DEV0_DET_INT Fld(1,0,AC_MSKB0)//[0:0]
#define ECBUS_EDID_INTEN (IO_VIRT_MHL + IO_MHL_BASE + 0x048)
    #define DEV3_DET_INTEN Fld(1,3,AC_MSKB0)//[3:3]
    #define DEV2_DET_INTEN Fld(1,2,AC_MSKB0)//[2:2]
    #define DEV1_DET_INTEN Fld(1,1,AC_MSKB0)//[1:1]
    #define DEV0_DET_INTEN Fld(1,0,AC_MSKB0)//[0:0]
#define ECBUS_EDID_INTCLR (IO_VIRT_MHL + IO_MHL_BASE + 0x04C)
    #define DEV3_DET_INTCLR Fld(1,3,AC_MSKB0)//[3:3]
    #define DEV2_DET_INTCLR Fld(1,2,AC_MSKB0)//[2:2]
    #define DEV1_DET_INTCLR Fld(1,1,AC_MSKB0)//[1:1]
    #define DEV0_DET_INTCLR Fld(1,0,AC_MSKB0)//[0:0]
#define ECBUS_TOP_CKDT_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x070)
    #define RG_FREQCMP_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
    #define RG_SALLY_LOCK_DET_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_SALLY_MHL_PP_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_SALLY_MHL_TEST Fld(1,3,AC_MSKB0)//[3:3]
    #define RG_SALLY_REF_CK_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define RG_SALLY_REF_CK_VAL Fld(1,5,AC_MSKB0)//[5:5]
    #define RG_CLKDETECT_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define RG_CLKDETECT_VAL Fld(1,7,AC_MSKB0)//[7:7]
    #define RG_COC_LOCK_SEL1 Fld(1,8,AC_MSKB1)//[8:8]
    #define RG_COC_LOCK_VAL Fld(1,9,AC_MSKB1)//[9:9]
    #define RG_COC_LOCK_SEL0 Fld(1,10,AC_MSKB1)//[10:10]
    #define RG_SALLY_LDET_CONTROL Fld(8,16,AC_FULLB2)//[23:16]
    #define RG_SALLY_LDET_CONFIG Fld(8,24,AC_FULLB3)//[31:24]
#define ECBUS_TOP_FQM_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x074)
    #define RG_FQM_TRI_CAL Fld(1,0,AC_MSKB0)//[0:0]
    #define RG_FQM_CLK_EXC Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_FQM_PERIOD_CNT_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_FQM_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define RG_FQM_LOAD_CNT Fld(10,16,AC_MSKW32)//[25:16]
#define ECBUS_TOP_FQM_STA (IO_VIRT_MHL + IO_MHL_BASE + 0x078)
    #define RGS_FQM_PERIOD_CNT Fld(16,0,AC_FULLW10)//[15:0]
    #define RGS_FQM_CAL_CNT Fld(15,16,AC_MSKW32)//[30:16]
    #define RGS_FQM_CALC_OK Fld(1,31,AC_MSKB3)//[31:31]
#define ECBUS_TOP_INT_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x080)
    #define CLK_DETECT_INT_CLR Fld(1,31,AC_MSKB3)//[31:31]
    #define DOCCOC_LOCK_INT_CLR Fld(1,30,AC_MSKB3)//[30:30]
    #define MHL_CABLE_CONNECT_INT_CLR Fld(1,29,AC_MSKB3)//[29:29]
    #define WAKEUP_DETECT_INT_CLR Fld(1,28,AC_MSKB3)//[28:28]
    #define CBUS_CONNECTED_INT_CLR Fld(1,27,AC_MSKB3)//[27:27]
    #define LINK_CONT_CHECK_INT_CLR Fld(1,26,AC_MSKB3)//[26:26]
    #define CBUS_INTR_INT_CLR Fld(1,25,AC_MSKB3)//[25:25]
    #define TDM_INTR_INT_CLR Fld(1,24,AC_MSKB3)//[24:24]
    #define EMSC_INTR_INT_CLR Fld(1,23,AC_MSKB2)//[23:23]
    #define MHL_EDID_INTR_INT_CLR Fld(1,22,AC_MSKB2)//[22:22]
    #define RESERV0_INT_CLR Fld(1,21,AC_MSKB2)//[21:21]
    #define RESERV1_INT_CLR Fld(1,20,AC_MSKB2)//[20:20]
    #define RESERV2_INT_CLR Fld(1,19,AC_MSKB2)//[19:19]
    #define RESERV3_INT_CLR Fld(1,18,AC_MSKB2)//[18:18]
    #define RESERV4_INT_CLR Fld(1,17,AC_MSKB2)//[17:17]
    #define RESERV5_INT_CLR Fld(1,16,AC_MSKB2)//[16:16]
    #define CLK_DETECT_INT_MASK Fld(1,15,AC_MSKB1)//[15:15]
    #define DOCCOC_LOCK_INT_MASK Fld(1,14,AC_MSKB1)//[14:14]
    #define MHL_CABLE_CONNECT_INT_MASK Fld(1,13,AC_MSKB1)//[13:13]
    #define WAKEUP_DETECT_INT_MASK Fld(1,12,AC_MSKB1)//[12:12]
    #define CBUS_CONNECTED_INT_MASK Fld(1,11,AC_MSKB1)//[11:11]
    #define LINK_CONT_CHECK_INT_MASK Fld(1,10,AC_MSKB1)//[10:10]
    #define CBUS_INTR_INT_MASK Fld(1,9,AC_MSKB1)//[9:9]
    #define TDM_INTR_INT_MASK Fld(1,8,AC_MSKB1)//[8:8]
    #define EMSC_INTR_INT_MASK Fld(1,7,AC_MSKB0)//[7:7]
    #define MHL_EDID_INTR_INT_MASK Fld(1,6,AC_MSKB0)//[6:6]
    #define RESERV0_INT_MASK Fld(1,5,AC_MSKB0)//[5:5]
    #define RESERV1_INT_MASK Fld(1,4,AC_MSKB0)//[4:4]
    #define RESERV2_INT_MASK Fld(1,3,AC_MSKB0)//[3:3]
    #define RESERV3_INT_MASK Fld(1,2,AC_MSKB0)//[2:2]
    #define RESERV4_INT_MASK Fld(1,1,AC_MSKB0)//[1:1]
    #define RESERV5_INT_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define ECBUS_TOP_INT_STA (IO_VIRT_MHL + IO_MHL_BASE + 0x084)
 #define ECBUS_TOP_INT_STA_0 (IO_VIRT_MHL + IO_MHL_BASE + 0x084)
 #define ECBUS_TOP_INT_STA_1 (IO_VIRT_MHL + IO_MHL_BASE + 0x085)
 #define ECBUS_TOP_INT_STA_2 (IO_VIRT_MHL + IO_MHL_BASE + 0x086)
 #define ECBUS_TOP_INT_STA_3 (IO_VIRT_MHL + IO_MHL_BASE + 0x087)
    #define CLK_DETECT_INT Fld(1,31,AC_MSKB3)//[31:31]
    #define DOCCOC_LOCK_INT Fld(1,30,AC_MSKB3)//[30:30]
    #define MHL_CABLE_CONNECT_INT Fld(1,29,AC_MSKB3)//[29:29]
    #define WAKEUP_DETECT_INT Fld(1,28,AC_MSKB3)//[28:28]
    #define CBUS_CONNECTED_INT Fld(1,27,AC_MSKB3)//[27:27]
    #define LINK_CONT_CHECK_INT Fld(1,26,AC_MSKB3)//[26:26]
    #define CBUS_INTR_INT Fld(1,25,AC_MSKB3)//[25:25]
    #define TDM_INTR_INT Fld(1,24,AC_MSKB3)//[24:24]
    #define EMSC_INTR_INT Fld(1,23,AC_MSKB2)//[23:23]
    #define MHL_EDID_INTR_INT Fld(1,22,AC_MSKB2)//[22:22]
    #define RESERV0_INT Fld(1,21,AC_MSKB2)//[21:21]
    #define RESERV1_INT Fld(1,20,AC_MSKB2)//[20:20]
    #define RESERV2_INT Fld(1,19,AC_MSKB2)//[19:19]
    #define RESERV3_INT Fld(1,18,AC_MSKB2)//[18:18]
    #define RESERV4_INT Fld(1,17,AC_MSKB2)//[17:17]
    #define RESERV5_INT Fld(1,16,AC_MSKB2)//[16:16]
    #define CLK_DETECT_INT_STA Fld(1,15,AC_MSKB1)//[15:15]
    #define DOCCOC_LOCK_INT_STA Fld(1,14,AC_MSKB1)//[14:14]
    #define MHL_CABLE_CONNECT_INT_STA Fld(1,13,AC_MSKB1)//[13:13]
    #define WAKEUP_DETECT_INT_STA Fld(1,12,AC_MSKB1)//[12:12]
    #define CBUS_CONNECTED_INT_STA Fld(1,11,AC_MSKB1)//[11:11]
    #define LINK_CONT_CHECK_INT_STA Fld(1,10,AC_MSKB1)//[10:10]
    #define CBUS_INTR_INT_STA Fld(1,9,AC_MSKB1)//[9:9]
    #define TDM_INTR_INT_STA Fld(1,8,AC_MSKB1)//[8:8]
    #define EMSC_INTR_INT_STA Fld(1,7,AC_MSKB0)//[7:7]
    #define MHL_EDID_INTR_INT_STA Fld(1,6,AC_MSKB0)//[6:6]
    #define RESERV0_INT_STA Fld(1,5,AC_MSKB0)//[5:5]
    #define RESERV1_INT_STA Fld(1,4,AC_MSKB0)//[4:4]
    #define RESERV2_INT_STA Fld(1,3,AC_MSKB0)//[3:3]
    #define RESERV3_INT_STA Fld(1,2,AC_MSKB0)//[2:2]
    #define RESERV4_INT_STA Fld(1,1,AC_MSKB0)//[1:1]
    #define RESERV5_INT_STA Fld(1,0,AC_MSKB0)//[0:0]
#define ECBUS_TOP_PAD_CFG (IO_VIRT_MHL + IO_MHL_BASE + 0x088)
    #define REG_CBUS_PU_SW Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_CBUS_PU_VAL Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_CBUS_PE_SW Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_CBUS_PE_VAL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_CBUS_O_SW Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_CBUS_O_VAL Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_CBUS_OE_SE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_CBUS_OE_VAL Fld(1,7,AC_MSKB0)//[7:7]
#define ECBUS_ANA_CALIB_CTRL (IO_VIRT_MHL + IO_MHL_BASE + 0x0D0)
    #define RG_SWING_CALIB_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define RG_SWING_CALIB_RE_GEN Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_SWING_CALIB_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define RG_SWING_CAL_SET_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define RG_SWING_CAL_SAMPLE_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define RG_SWING_CALIB_DATA Fld(4,8,AC_MSKB1)//[11:8]
    #define RG_IMP_CALIB_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define RG_IMP_CALIB_RE_GEN Fld(1,17,AC_MSKB2)//[17:17]
    #define RG_IMP_CALIB_SEL Fld(1,18,AC_MSKB2)//[18:18]
    #define RG_IMP_CAL_SET_SEL Fld(2,20,AC_MSKB2)//[21:20]
    #define RG_IMP_CAL_SAMPLE_SEL Fld(2,22,AC_MSKB2)//[23:22]
    #define RG_IMP_CALIB_DATA Fld(4,24,AC_MSKB3)//[27:24]
#define ECBUS_ANA_CALIB_STA (IO_VIRT_MHL + IO_MHL_BASE + 0x0D4)
    #define RGS_DA_SWING_OUT Fld(4,0,AC_MSKB0)//[3:0]
    #define RGS_DA_IMP_OUT Fld(4,4,AC_MSKB0)//[7:4]
#define ECBUS_ANA_PLL_LOCK_CTRL (IO_VIRT_MHL + IO_MHL_BASE  + 0x0D8)
    #define RG_PLL_LOCK_TRI_CAL Fld(1,0,AC_MSKB0)//[0:0]
    #define RG_PLL_LOCK_TRI_CAL_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_PLL_LOCK_CNT_THRESHOLD_TRIM Fld(8,8,AC_FULLB1)//[15:8]
    #define RG_PLL_LOCK_CNT_THRESHOLD Fld(16,16,AC_FULLW32)//[31:16]
#define ECBUS_ANA_PLL_LOCK_STA (IO_VIRT_MHL + IO_MHL_BASE + 0x0DC)
    #define RGS_PLL_LOCK_CNT Fld(16,0,AC_FULLW10)//[15:0]
    #define RGS_PLL_LOCK_BY_FQM Fld(1,31,AC_MSKB3)//[31:31]
#define COC_MISC0 (IO_VIRT_MHL + IO_MHL_BASE + 0x200)
    #define COCSNK_VIH_CTL Fld(8,0,AC_FULLB0)//[7:0]
    #define COCSNK_VIL_CTL Fld(8,8,AC_FULLB1)//[15:8]
    #define DOCSRC_DEBUG_AV Fld(1,16,AC_MSKB2)//[16:16]
    #define DOCCOC_CTS Fld(1,17,AC_MSKB2)//[17:17]
    #define DOCCOC_CTS_TCK_PHASE Fld(1,18,AC_MSKB2)//[18:18]
#define COC_CTL0 (IO_VIRT_MHL + IO_MHL_BASE + 0x204)
    #define REG_COCSNK_CONTROL0_1 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_COCSNK_CONTROL0_2 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_COCSNK_CONTROL0_3 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_COCSNK_CONTROL0_4 Fld(2,3,AC_MSKB0)//[4:3]
    #define REG_COCSNK_CONTROL0_5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_COCSNK_CONTROL0_6 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_COCSNK_CONTROL1_1 Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_COCSNK_CONTROL1_2 Fld(2,14,AC_MSKB1)//[15:14]
    #define REG_COCSNK_CONTROL2_1 Fld(6,16,AC_MSKB2)//[21:16]
    #define REG_COCSNK_CONTROL2_2 Fld(2,22,AC_MSKB2)//[23:22]
    #define REG_COCSNK_CONTROL3 Fld(8,24,AC_FULLB3)//[31:24]
#define COC_CTL4 (IO_VIRT_MHL + IO_MHL_BASE + 0x208)
    #define REG_COCSNK_CONTROL4_1 Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_COCSNK_CONTROL4_2 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_COCSNK_CONTROL5_1 Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_COCSNK_CONTROL5_2 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_COCSNK_CONTROL5_3 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_COCSNK_CONTROL6_1 Fld(6,16,AC_MSKB2)//[21:16]
    #define REG_COCSNK_CONTROL6_2 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_COCSNK_CONTROL6_3 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_COCSNK_CONTROL7_1 Fld(3,24,AC_MSKB3)//[26:24]
    #define REG_COCSNK_CONTROL7_2 Fld(2,27,AC_MSKB3)//[28:27]
    #define REG_COCSNK_CONTROL7_3 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_COCSNK_CONTROL7_4 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_COCSNK_CONTROL7_5 Fld(1,31,AC_MSKB3)//[31:31]
#define COC_CTL8 (IO_VIRT_MHL + IO_MHL_BASE + 0x20C)
    #define REG_COCSNK_CONTROL8_1 Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_COCSNK_CONTROL8_2 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_COCSNK_CONTROL8_3 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_COCSNK_CONTROL9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_COCSNK_CONTROLA Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_COCSNK_CONTROLB Fld(8,24,AC_FULLB3)//[31:24]
#define COC_CTLC (IO_VIRT_MHL + IO_MHL_BASE + 0x210)
    #define REG_COCSNK_CONTROLC Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_COCSNK_CONTROLD_1 Fld(7,8,AC_MSKB1)//[14:8]
    #define REG_COCSNK_CONTROLD_2 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_COCSNK_CONTROLE_1 Fld(7,16,AC_MSKB2)//[22:16]
    #define REG_COCSNK_CONTROLE_2 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_COCSNK_CONTROLF_1 Fld(7,24,AC_MSKB3)//[30:24]
    #define REG_COCSNK_CONTROLF_2 Fld(1,31,AC_MSKB3)//[31:31]
#define COC_CTL10 (IO_VIRT_MHL + IO_MHL_BASE + 0x214)
    #define REG_COCSNK_CONTROL10_1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_COCSNK_CONTROL10_2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_COCSNK_CONTROL11_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_COCSNK_CONTROL11_2 Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_COCSNK_CONTROL12_1 Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_COCSNK_CONTROL12_2 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_COCSNK_CONTROL12_3 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_COCSNK_CONTROL12_4 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_COCSNK_CONTROL12_5 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_COCSNK_CONTROL13 Fld(8,24,AC_FULLB3)//[31:24]
#define COC_CTL14 (IO_VIRT_MHL + IO_MHL_BASE + 0x218)
    #define REG_COCSNK_CONTROL14_1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_COCSNK_CONTROL14_2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_COCSNK_CONTROL15_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_COCSNK_CONTROL15_2 Fld(3,12,AC_MSKB1)//[14:12]
    #define REG_COCSNK_CONTROL15_3 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_COCSNK_CONTROL16_1 Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_COCSNK_CONTROL16_2 Fld(3,20,AC_MSKB2)//[22:20]
    #define REG_COCSNK_CONTROL16_3 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_COCSNK_CONTROL17_1 Fld(4,24,AC_MSKB3)//[27:24]
    #define REG_COCSNK_CONTROL17_2 Fld(4,28,AC_MSKB3)//[31:28]
#define COC_CTL18 (IO_VIRT_MHL + IO_MHL_BASE + 0x21C)
    #define REG_COCSNK_CONTROL18_1 Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_COCSNK_CONTROL18_2 Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_COCSNK_CONTROL19_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_COCSNK_CONTROL19_2 Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_COCSNK_CONTROL1A_1 Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_COCSNK_CONTROL1A_2 Fld(6,18,AC_MSKB2)//[23:18]
    #define REG_COCSNK_CONTROL1B Fld(8,24,AC_FULLB3)//[31:24]
#define COC_STAT0 (IO_VIRT_MHL + IO_MHL_BASE + 0x220)
    #define COCSNK_STATUS0_A Fld(32,0,AC_FULLDW)//[31:0]
    #define COCSNK_STATUS0 Fld(8,0,AC_FULLB0)//[7:0]
    #define COCSNK_STATUS1 Fld(8,8,AC_FULLB1)//[15:8]
    #define COCSNK_STATUS2 Fld(8,16,AC_FULLB2)//[23:16]
    #define COCSNK_STATUS3 Fld(8,24,AC_FULLB3)//[31:24]
    #define COCSNK_STATUS0_FSM Fld(4,0,AC_MSKB0)//[3:0]
#define COC_STAT4 (IO_VIRT_MHL + IO_MHL_BASE + 0x224)
    #define COCSNK_STATUS4_A Fld(32,0,AC_FULLDW)//[31:0]
    #define COCSNK_STATUS4 Fld(8,0,AC_FULLB0)//[7:0]
    #define COCSNK_STATUS5 Fld(8,8,AC_FULLB1)//[15:8]
    #define COCSNK_STATUS6 Fld(8,16,AC_FULLB2)//[23:16]
    #define COCSNK_STATUS7 Fld(8,24,AC_FULLB3)//[31:24]
    #define COCSNK_STATUS6_CAL_DONE Fld(1,23,AC_MSKB2)//[23:23]
#define COC_STAT8 (IO_VIRT_MHL + IO_MHL_BASE + 0x228)
    #define COCSNK_STATUS8_A Fld(32,0,AC_FULLDW)//[31:0]
    #define COCSNK_STATUS8 Fld(8,0,AC_FULLB0)//[7:0]
    #define COCSNK_STATUS9 Fld(8,8,AC_FULLB1)//[15:8]
    #define COCSNK_STATUSA Fld(8,16,AC_FULLB2)//[23:16]
    #define COCSNK_STATUSB Fld(8,24,AC_FULLB3)//[31:24]
#define COC_STATc (IO_VIRT_MHL + IO_MHL_BASE + 0x22C)
    #define COCSNK_STATUSC Fld(8,0,AC_FULLB0)//[7:0]
    #define COCSNK_STATUSD Fld(8,8,AC_FULLB1)//[15:8]
    #define COCSNK_STATUSE Fld(8,16,AC_FULLB2)//[23:16]
    #define COCSNK_STATUSF Fld(8,24,AC_FULLB3)//[31:24]
#define TDMSRST (IO_VIRT_MHL + IO_MHL_BASE + 0x400)
    #define REG_TTX_SRST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_TRX_SRST Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_INTR Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_AGGRINTR Fld(4,4,AC_MSKB0)//[7:4]
#define TTXINTL (IO_VIRT_MHL + IO_MHL_BASE + 0x404)
    #define REG_TTX_INTR0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_TTX_INTR1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_TTX_INTR2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_TTX_INTR3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_TTX_INTR4 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_TTX_INTR5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_TTX_INTR6 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_TTX_INTR7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_TTX_INTR8 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_TTX_INTR9 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_TTX_INTR10 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_TTX_INTR11 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_TTX_INTR12 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_TTX_INTR13 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_TTX_INTR14 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_TTX_INTR15 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_TRX_INTR0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_TRX_INTR1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_TRX_INTR2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_TRX_INTR3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_TRX_INTR4 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_TRX_INTR5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_TRX_INTR6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_TRX_INTR7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_TRX_INTR8 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_TRX_INTR9 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_TRX_INTR10 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_TRX_INTR11 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_TRX_INTR12 Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_TRX_INTR13 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_TRX_INTR14 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_TRX_INTR15 Fld(1,31,AC_MSKB3)//[31:31]
#define TTXINTML (IO_VIRT_MHL + IO_MHL_BASE + 0x408)
    #define REG_TTX_INTRMASK0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_TTX_INTRMASK1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_TTX_INTRMASK2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_TTX_INTRMASK3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_TTX_INTRMASK4 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_TTX_INTRMASK5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_TTX_INTRMASK6 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_TTX_INTRMASK7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_TTX_INTRMASK8 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_TTX_INTRMASK9 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_TTX_INTRMASK10 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_TTX_INTRMASK11 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_TTX_INTRMASK12 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_TTX_INTRMASK13 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_TTX_INTRMASK14 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_TTX_INTRMASK15 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_TRX_INTRMASK0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_TRX_INTRMASK1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_TRX_INTRMASK2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_TRX_INTRMASK3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_TRX_INTRMASK4 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_TRX_INTRMASK5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_TRX_INTRMASK6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_TRX_INTRMASK7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_TRX_INTRMASK8 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_TRX_INTRMASK9 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_TRX_INTRMASK10 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_TRX_INTRMASK11 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_TRX_INTRMASK12 Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_TRX_INTRMASK13 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_TRX_INTRMASK14 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_TRX_INTRMASK15 Fld(1,31,AC_MSKB3)//[31:31]
#define TTXBUF (IO_VIRT_MHL + IO_MHL_BASE + 0x40C)
    #define REG_TTX_BUFFER Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TTX_NUMBPS Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_TTX_COM1_AT_SYNC_WAIT Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_TTX_NUMSPISYM Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TTX_NUMHSICSYM Fld(8,24,AC_FULLB3)//[31:24]
#define TTXTOTNUMS (IO_VIRT_MHL + IO_MHL_BASE + 0x410)
    #define REG_TTX_NUMTOTSYM Fld(8,0,AC_FULLB0)//[7:0]
#define TTXSCOM1L (IO_VIRT_MHL + IO_MHL_BASE + 0x414)
    #define REG_TTX_SYMCOM1_LOW Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TTX_SYMCOM1_HIGH Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_TTX_SYMCOM2_LOW Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TTX_SYMCOM2_HIGH Fld(2,24,AC_MSKB3)//[25:24]
#define TTXSIDLEL (IO_VIRT_MHL + IO_MHL_BASE + 0x418)
    #define REG_TTX_SYMIDLE_LOW Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TTX_SYMIDLE_HIGH Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_TTX_SYMCBUS_LOW Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TTX_SYMCBUS_HIGH Fld(2,24,AC_MSKB3)//[25:24]
#define TTXSCBUSAL (IO_VIRT_MHL + IO_MHL_BASE + 0x41C)
    #define REG_TTX_SYMCBUSA_LOW Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TTX_SYMCBUSA_HIGH Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_TTX_SYMCBUSN_LOW Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TTX_SYMCBUSN_HIGH Fld(2,24,AC_MSKB3)//[25:24]
#define TTXSTA1 (IO_VIRT_MHL + IO_MHL_BASE + 0x420)
    #define REG_TTX_STATUS_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TTX_STATUS_2 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_TTX_STATUS_3 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TTX_STATUS_4 Fld(8,24,AC_FULLB3)//[31:24]
#define TTXOVRL (IO_VIRT_MHL + IO_MHL_BASE + 0x424)
    #define REG_TTX_OVERRIDE_HSIC_IN_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TTX_OVERRIDE_HSIC_IN_2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_TTX_IGNORE_CBUS_IN Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_TTX_IGNORE_SPI_IN Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_TTX_ALLOC_HSIC_THEN_SPI Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_TRX_OUT_EN Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_TRX_ALLOC_HSIC_THEN_SPI Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_STATUS_EN Fld(1,31,AC_MSKB3)//[31:31]
#define TRXCTRL (IO_VIRT_MHL + IO_MHL_BASE + 0x428)
    #define REG_TRX_NUMBPS Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_TRX_FROM_SE_COC Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_TRX_CLR_WVALLOW Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_TRX_NUMSPISYM Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_TRX_NUMHSICSYM Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TRX_NUMTOTSYM Fld(8,24,AC_FULLB3)//[31:24]
#define TRXMIN12 (IO_VIRT_MHL + IO_MHL_BASE + 0x42C)
    #define REG_TRX_MIN12MP Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TRX_MIN2MP Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_TRX_MAX12MP Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TRX_MAX2MP Fld(8,24,AC_FULLB3)//[31:24]
#define TRXSTA1 (IO_VIRT_MHL + IO_MHL_BASE + 0x430)
    #define REG_TRX_STATUS_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TRX_STATUS_2 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_TRX_STATUS_3 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TRX_STATUS_4 Fld(8,24,AC_FULLB3)//[31:24]
#define TRXSTA5 (IO_VIRT_MHL + IO_MHL_BASE + 0x434)
    #define REG_TRX_STATUS_5 Fld(8,0,AC_FULLB0)//[7:0]
#define TDMLLCTL (IO_VIRT_MHL + IO_MHL_BASE + 0x438)
    #define REG_TTX_LL_SEL_MODE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_TTX_LL_TIE_LOW Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_TTX_LL_SEL_MANUAL Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_TRX_LL_SEL_MODE Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_TRX_LL_SEL_MANUAL Fld(2,6,AC_MSKB0)//[7:6]
    #define REG_TTX_8BIT_CBUS_IF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_TRX_8BIT_CBUS_IF Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_TTX_SLOT0_INTERLEAVING Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_TTX_S0_TARGET Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_TTX_S0_ALLOWANCE Fld(8,24,AC_FULLB3)//[31:24]
#define GENCTL (IO_VIRT_MHL + IO_MHL_BASE + 0x500)
    #define REG_EMSC_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_START_TRAIN_SEQ Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_CLR_XFIFO Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_CLR_RFIFO Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_EMSC_RST1 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_DIS_XMIT_ERR_STATE Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_COMMA_CHAR1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_COMMA_CHAR2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_NULL_CHAR Fld(8,24,AC_FULLB3)//[31:24]
#define TRAINCH (IO_VIRT_MHL + IO_MHL_BASE + 0x504)
    #define REG_TRAIN_CHAR Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_COMMA_CHAR_ERR_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_I2C_TO_EMSC_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_COMMA_CHAR_WIN Fld(8,16,AC_FULLB2)//[23:16]
#define TXTRAINBCNTL (IO_VIRT_MHL + IO_MHL_BASE + 0x508)
    #define REG_TX_TRAIN_CHAR_CNT_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TX_TRAIN_CHAR_CNT_2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_SKIP_BYTE_CNT_1 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_SKIP_BYTE_CNT_2 Fld(1,24,AC_MSKB3)//[24:24]
#define EMSCRCVTOUT (IO_VIRT_MHL + IO_MHL_BASE + 0x50C)
    #define REG_RECV_TOUT_MSB Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_XMIT_TOUT_MSB Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_XMIT_RETRY_MAX_MSB_1 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_XMIT_RETRY_MAX_MSB_2 Fld(3,24,AC_MSKB3)//[26:24]
#define EMSCXMITRETRYLMT (IO_VIRT_MHL + IO_MHL_BASE + 0x510)
    #define REG_XMIT_RETRY_LIMIT Fld(8,0,AC_FULLB0)//[7:0]
#define EMSCSPCHK (IO_VIRT_MHL + IO_MHL_BASE + 0x514)
    #define REG_SPACE_CHECK_NUM Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WAIT_CHECK_SPACE_CNT Fld(8,8,AC_FULLB1)//[15:8]
#define EMSCXMITSTAT (IO_VIRT_MHL + IO_MHL_BASE + 0x518)
    #define REG_XMIT_STATUS Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_RECV_STATUS Fld(8,8,AC_FULLB1)//[15:8]
#define EMSCBURSTCNT (IO_VIRT_MHL + IO_MHL_BASE + 0x520)
    #define REG_EMSC_BURST_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_XMIT_TIMEOUT_STATE Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_EMSC_INTR_STAT_0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_EMSC_INTR_STAT_1 Fld(1,17,AC_MSKB2)//[17:17]
#define EMSCSTAT (IO_VIRT_MHL + IO_MHL_BASE + 0x524)
    #define REG_EMSC_NORMAL_MODE Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_EMSC_RFIFO_NOT_EMPTY Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_XMIT_GNT_TOUT_ Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_XMIT_DONE Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_COMMA_CHAR_ERR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_XFIFO_WRITE_ERR Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_RFIFO_READ_ERR Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_XMIT_ACK_TOUT Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_XFIFO_EMPTY Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_EMSC_INTR0_MASK0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_EMSC_INTR0_MASK1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_EMSC_INTR0_MASK2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_EMSC_INTR0_MASK3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_EMSC_INTR0_MASK4 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_EMSC_INTR0_MASK5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_EMSC_INTR0_MASK6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_EMSC_INTR0_MASK7 Fld(1,23,AC_MSKB2)//[23:23]
#define RXTRAINBCNTL (IO_VIRT_MHL + IO_MHL_BASE + 0x528)
    #define REG_RX_TRAIN_CHAR_CNT_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_RX_TRAIN_CHAR_CNT_2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_GNT_RETRY_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_ACK_RETRY_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define SPIEMSCFIFOSTAT (IO_VIRT_MHL + IO_MHL_BASE + 0x52C)
    #define REG_EMSC_FIFO_STATUS Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_TRAINING_COMMA_ERR Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_EMSC_INTR1_MASK0 Fld(1,16,AC_MSKB2)//[16:16]
#define EMSCXFIFOBCNTL (IO_VIRT_MHL + IO_MHL_BASE + 0x530)
    #define REG_EMSC_XFIFO_BYTE_CNT_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_EMSC_XFIFO_BYTE_CNT_2 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_EMSC_RFIFO_BYTE_CNT_1 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_EMSC_RFIFO_BYTE_CNT_2 Fld(1,24,AC_MSKB3)//[24:24]
#define EMSCXFIFOSPACEL (IO_VIRT_MHL + IO_MHL_BASE + 0x534)
    #define REG_EMSC_XFIFO_SPACE_1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_EMSC_XFIFO_SPACE_2 Fld(1,8,AC_MSKB1)//[8:8]
#define EMSC_XMIT_WRITE_PORT (IO_VIRT_MHL + IO_MHL_BASE + 0x538)
    #define REG_EMSC_XMIT_WRITE_DATA Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_EMSC_XMIT_WRITE_ENABLE Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_EMSC_XMIT_WRITE_START Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_EMSC_LOAD_XFIFO_STATUS Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_EMSC_LOAD_XFIFO_WPTR Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_XFIFO_FULL_LATCH Fld(1,31,AC_MSKB3)//[31:31]
#define EMSC_RCV_READ_PORT (IO_VIRT_MHL + IO_MHL_BASE + 0x53C)
    #define REG_EMSC_RCV_READ_DATA Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_EMSC_RCV_RD_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_EMSC_RCV_READ_START Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_EMSC_RCV_LOAD_RFIFO_STATUS Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_EMSC_RCV_READ_STOP Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_EMSC_RCV_PEEK_BURST_CNT Fld(1,12,AC_MSKB1)//[12:12]
#define WB_XMIT_DATA1 (IO_VIRT_MHL + IO_MHL_BASE + 0x600)
    #define REG_WB_XMIT_DATA_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WB_XMIT_DATA_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_WB_XMIT_DATA_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_WB_XMIT_DATA_3 Fld(8,24,AC_FULLB3)//[31:24]
#define WB_XMIT_DATA2 (IO_VIRT_MHL + IO_MHL_BASE + 0x604)
    #define REG_WB_XMIT_DATA_4 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WB_XMIT_DATA_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_WB_XMIT_DATA_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_WB_XMIT_DATA_7 Fld(8,24,AC_FULLB3)//[31:24]
#define WB_XMIT_DATA3 (IO_VIRT_MHL + IO_MHL_BASE + 0x608)
    #define REG_WB_XMIT_DATA_8 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WB_XMIT_DATA_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_WB_XMIT_DATA_A Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_WB_XMIT_DATA_B Fld(8,24,AC_FULLB3)//[31:24]
#define WB_XMIT_DATA4 (IO_VIRT_MHL + IO_MHL_BASE + 0x60C)
    #define REG_WB_XMIT_DATA_C Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WB_XMIT_DATA_D Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_WB_XMIT_DATA_E Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_WB_XMIT_DATA_F Fld(8,24,AC_FULLB3)//[31:24]
#define DBG_CTL_L (IO_VIRT_MHL + IO_MHL_BASE + 0x610)
    #define REG_DBG_CTL_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_DBG_CTL_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_DBG_EXT_STAT Fld(8,16,AC_FULLB2)//[23:16]
#define DBG_INT_STAT_SEL (IO_VIRT_MHL + IO_MHL_BASE + 0x614)
    #define REG_DBG_INT_STAT_SEL Fld(2,0,AC_MSKB0)//[1:0]
    #define REG_DBG_INT_STAT_0 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_DBG_INT_STAT_1 Fld(8,16,AC_FULLB2)//[23:16]
#define CBUS_SYS_CTL (IO_VIRT_MHL + IO_MHL_BASE + 0x618)
    #define REG_CBUS_RST Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_CBUS_INTR_STAT_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_CBUS_INTR_STAT_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_CBUS_INTR_STAT_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_CBUS_INTR_STAT_3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_CBUS_INTR_STAT_4 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_CBUS_INTR_STAT_5 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_CBUS_INTR_STAT_6 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_CBUS_INTR_STAT_7 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_CBUS_INTR_STAT_8 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_CBUS_INTR_STAT_9 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_CBUS_INTR_STAT_10 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_CBUS_INTR_STAT_11 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_CBUS_INTR_STAT_12 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_CBUS_INTR_STAT_13 Fld(1,21,AC_MSKB2)//[21:21]
#define CBUS_DISC_CLK_RATIO_L (IO_VIRT_MHL + IO_MHL_BASE + 0x61C)
    #define REG_RATIO_60KHZ_2_DISC_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_RATIO_60KHZ_2_DISC_1 Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_SEL_60KHZ_4_DISC Fld(1,15,AC_MSKB1)//[15:15]
#define MHL_INT_0_MASK (IO_VIRT_MHL + IO_MHL_BASE + 0x620)
  #define MHL_INT_0_MASK_0_0 (IO_VIRT_MHL + IO_MHL_BASE + 0x620)
  #define MHL_INT_0_MASK_0_1 (IO_VIRT_MHL + IO_MHL_BASE + 0x621)
  #define MHL_INT_0_MASK_0_2 (IO_VIRT_MHL + IO_MHL_BASE + 0x622)
  #define MHL_INT_0_MASK_0_3 (IO_VIRT_MHL + IO_MHL_BASE + 0x623)
    #define REG_MHL_INT_0_MASK0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_MHL_INT_0_MASK1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_MHL_INT_0_MASK2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_MHL_INT_0_MASK3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_MHL_INT_0_MASK4 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_MHL_INT_0_MASK5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_MHL_INT_0_MASK6 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_MHL_INT_0_MASK7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_MHL_INT_1_MASK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_MHL_INT_1_MASK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_MHL_INT_1_MASK2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_MHL_INT_1_MASK3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_MHL_INT_1_MASK4 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_MHL_INT_1_MASK5 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_MHL_INT_1_MASK6 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_MHL_INT_1_MASK7 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_MHL_INT_2_MASK0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_MHL_INT_2_MASK1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_MHL_INT_2_MASK2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_MHL_INT_2_MASK3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_MHL_INT_2_MASK4 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_MHL_INT_2_MASK5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_MHL_INT_2_MASK6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_MHL_INT_2_MASK7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_MHL_INT_3_MASK0 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_MHL_INT_3_MASK1 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_MHL_INT_3_MASK2 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_MHL_INT_3_MASK3 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_MHL_INT_3_MASK4 Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_MHL_INT_3_MASK5 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_MHL_INT_3_MASK6 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_MHL_INT_3_MASK7 Fld(1,31,AC_MSKB3)//[31:31]
#define MDT_RCV_TIMEOUT (IO_VIRT_MHL + IO_MHL_BASE + 0x624)
    #define REG_MDT_RCV_TIMEOUT_MAX_MSB Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MDT_XMIT_TIMEOUT_MAX_MSB Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MDT_RFIFO_CLR_CUR Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_MDT_RFIFO_CLR_ALL Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_MDT_DISABLE Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_MDT_XFIFO_OVER_WR_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_MDT_RFIFO_OVER_WR_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_MDT_DELAY_RCV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_MDT_RCV_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_MDT_XFIFO_CLR_CUR Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_MDT_XFIFO_CLR_ALL Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_MDT_CLR_ABORT_WAIT Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_MDT_XMIT_SINGLE_RUN_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_MDT_XMIT_FIXED_AID Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_MDT_XMIT_FIXED_BURST_LEN Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_MDT_XMIT_CMD_MERGE_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_MDT_XMIT_EN Fld(1,31,AC_MSKB3)//[31:31]
#define MDT_RFIFO_STAT (IO_VIRT_MHL + IO_MHL_BASE + 0x628)
    #define REG_MDT_RFIFO_CUR_BYTE_CNT Fld(5,0,AC_MSKB0)//[4:0]
    #define REG_MDT_RFIFO_CNT Fld(3,5,AC_MSKB0)//[7:5]
    #define REG_MDT_WRITE_BURST_LEN Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_MDT_XMIT_PRE_HS_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_MDT_XFIFO_LEVEL_AVAIL Fld(3,13,AC_MSKB1)//[15:13]
#define MDT_INT (IO_VIRT_MHL + IO_MHL_BASE + 0x62C)
    #define REG_MDT_INT_0_0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_MDT_INT_0_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_MDT_INT_0_2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_MDT_INT_0_3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_MDT_INT_0_MASK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_MDT_INT_0_MASK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_MDT_INT_0_MASK2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_MDT_INT_0_MASK3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_MDT_INT_1_0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_MDT_INT_1_1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_MDT_INT_1_2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_MDT_INT_1_5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_MDT_INT_1_6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_MDT_INT_1_7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_MDT_INT_1_MASK0 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_MDT_INT_1_MASK1 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_MDT_INT_1_MASK2 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_MDT_INT_1_MASK5 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_MDT_INT_1_MASK6 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_MDT_INT_1_MASK7 Fld(1,31,AC_MSKB3)//[31:31]
#define CBUS_VENDOR_ID (IO_VIRT_MHL + IO_MHL_BASE + 0x630)
    #define REG_CBUS_VENDOR_ID Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_CBUS_CONNECTED Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_MHL_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_CBUS_HPD Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_MSC_HB_SUCCESS Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_MHL_CABLE_PRESENT Fld(1,12,AC_MSKB1)//[12:12]
#define CBUS_INT (IO_VIRT_MHL + IO_MHL_BASE + 0x634)
  #define CBUS_INT_0 (IO_VIRT_MHL + IO_MHL_BASE + 0x634)
  #define CBUS_INT_1 (IO_VIRT_MHL + IO_MHL_BASE + 0x635)
  #define CBUS_INT_2 (IO_VIRT_MHL + IO_MHL_BASE + 0x636)
  #define CBUS_INT_3 (IO_VIRT_MHL + IO_MHL_BASE + 0x637)
    #define REG_CBUS_INT_0_STAT0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_CBUS_INT_0_STAT1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_CBUS_INT_0_STAT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_CBUS_INT_0_STAT3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_CBUS_INT_0_STAT4 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_CBUS_INT_0_STAT5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_CBUS_INT_0_STAT6 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_CBUS_INT_0_STAT7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_CBUS_INT_0_MASK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_CBUS_INT_0_MASK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_CBUS_INT_0_MASK2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_CBUS_INT_0_MASK3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_CBUS_INT_0_MASK4 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_CBUS_INT_0_MASK5 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_CBUS_INT_0_MASK6 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_CBUS_INT_0_MASK7 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_CBUS_INT_1_STAT0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_CBUS_INT_1_STAT2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_CBUS_INT_1_STAT3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_CBUS_INT_1_STAT5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_CBUS_INT_1_STAT6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_CBUS_INT_1_STAT7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_CBUS_INT_1_MASK0 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_CBUS_INT_1_MASK2 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_CBUS_INT_1_MASK3 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_CBUS_INT_1_MASK5 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_CBUS_INT_1_MASK6 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_CBUS_INT_1_MASK7 Fld(1,31,AC_MSKB3)//[31:31]
#define DDC_ABORT_INT (IO_VIRT_MHL + IO_MHL_BASE + 0x638)
    #define REG_DDC_ABORT_INT_STAT0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_DDC_ABORT_INT_STAT1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_DDC_ABORT_INT_STAT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_DDC_ABORT_INT_STAT7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_DDC_ABORT_INT_MASK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_DDC_ABORT_INT_MASK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_DDC_ABORT_INT_MASK2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_DDC_ABORT_INT_MASK7 Fld(1,15,AC_MSKB1)//[15:15]
#define MSC_MT_ABORT_INT (IO_VIRT_MHL + IO_MHL_BASE + 0x63C)
    #define REG_MSC_MT_ABORT_INT_STAT0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_MSC_MT_ABORT_INT_STAT1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_MSC_MT_ABORT_INT_STAT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_MSC_MT_ABORT_INT_STAT3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_MSC_MT_ABORT_INT_STAT5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_MSC_MT_ABORT_INT_STAT7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_MSC_MT_ABORT_INT_MASK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_MSC_MT_ABORT_INT_MASK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_MSC_MT_ABORT_INT_MASK2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_MSC_MT_ABORT_INT_MASK3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_MSC_MT_ABORT_INT_MASK5 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_MSC_MT_ABORT_INT_MASK7 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_MSC_MR_ABORT_INT_STAT0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_MSC_MR_ABORT_INT_STAT1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_MSC_MR_ABORT_INT_STAT2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_MSC_MR_ABORT_INT_STAT3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_MSC_MR_ABORT_INT_STAT4 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_MSC_MR_ABORT_INT_STAT5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_MSC_MR_ABORT_INT_STAT7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_MSC_MR_ABORT_INT_MASK0 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_MSC_MR_ABORT_INT_MASK1 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_MSC_MR_ABORT_INT_MASK2 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_MSC_MR_ABORT_INT_MASK3 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_MSC_MR_ABORT_INT_MASK4 Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_MSC_MR_ABORT_INT_MASK5 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_MSC_MR_ABORT_INT_MASK7 Fld(1,31,AC_MSKB3)//[31:31]
#define CBUS_LINK_CONTROL0 (IO_VIRT_MHL + IO_MHL_BASE + 0x640)
    #define REG_LNK_PACKET_LIMIT Fld(6,0,AC_MSKB0)//[5:0]
    #define REG_LNK_INI_TIMEOUT_MAX Fld(4,7,AC_MSKW10)//[10:7]
    #define REG_LNK_GLITCH_FILTER_SEL Fld(5,11,AC_MSKB1)//[15:11]
    #define REG_LNK_RCV_BIT_CHECK_OPT Fld(3,16,AC_MSKB2)//[18:16]
    #define REG_LNK_FWR_ACK_OFFSET Fld(3,19,AC_MSKB2)//[21:19]
    #define REG_LNK_SYNC_FILTER_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_LNK_XMIT_OPP_TIMEOUT_MAX Fld(3,24,AC_MSKB3)//[26:24]
    #define REG_LNK_RCV_OPP_TIMEOUT_MAX Fld(5,27,AC_MSKB3)//[31:27]
#define CBUS_LINK_CONTROL1 (IO_VIRT_MHL + IO_MHL_BASE + 0x644)
    #define REG_LNK_HIGH_TIMEOUT_MAX_MSB Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_LNK_LOW_TIMEOUT_MAX_MSB Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_LNK_DRV_HIGH_LIMIT Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_LNK_CHECK_HIGH_LIMIT Fld(2,11,AC_MSKB1)//[12:11]
    #define REG_LNK_XMIT_IDLE_TIMEOUT Fld(5,16,AC_MSKB2)//[20:16]
    #define REG_LNK_XMIT_BIT_TIME_SEL0 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_LNK_XMIT_BIT_TIME Fld(8,24,AC_FULLB3)//[31:24]
#define CBUS_LINK_CONTROL2 (IO_VIRT_MHL + IO_MHL_BASE + 0x648)
    #define REG_LNK_CAL_BYTE_CNT_MIN Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_LNK_CAL_FIFO_DEPTH Fld(3,3,AC_MSKB0)//[5:3]
    #define REG_LNK_INV_POLARITY Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_LNK_XMIT_BIT_TIME_SEL1 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_LNK_CAL_SYNC_OFFSET Fld(3,8,AC_MSKB1)//[10:8]
    #define REG_LNK_CAL_BIT_OFFSET Fld(3,11,AC_MSKB1)//[13:11]
    #define REG_LNK_RCV_BIT_TIME_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_LNK_CAL_ERROR_CHECK Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_LNK_CAL_BDY_CTL Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_LNK_NORM_BDY_CTL Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_LNK_XMIT_RETRY_LIMIT Fld(6,18,AC_MSKB2)//[23:18]
#define CBUS_ACK_CONTROL3 (IO_VIRT_MHL + IO_MHL_BASE + 0x64C)
    #define REG_LNK_ACK_WIN_WIDTH Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_LNK_NACK_CNT_MAX Fld(6,8,AC_MSKB1)//[13:8]
    #define REG_LNK_EN_CAL_BY_NACK Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_LNK_RCV_BIT_TIME Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_LNK_XMIT_ERR_COUNT Fld(7,24,AC_MSKB3)//[30:24]
#define CBUS_BIPHZ_ERR_CNT (IO_VIRT_MHL + IO_MHL_BASE + 0x650)
    #define REG_LNK_CAL_BIPHZ_ERR_CNT Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_LNK_NORM_BIPHZ_ERR_CNT Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_LNK_CAL_PARITY_ERR_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_LNK_RCV_ERR_COUNT Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_LNK_SYNC_LOW_MIN_OFFSET Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_LNK_SYNC_LOW_MAX_OFFSET Fld(4,20,AC_MSKB2)//[23:20]
    #define REG_LNK_SYNC_BIT_MIN_OFFSET Fld(4,24,AC_MSKB3)//[27:24]
    #define REG_LNK_SYNC_BIT_MAX_OFFSET Fld(4,28,AC_MSKB3)//[31:28]
#define MDT_SM_STAT (IO_VIRT_MHL + IO_MHL_BASE + 0x654)
    #define REG_MDT_XMIT_STATE Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_MDT_RCV_STATE Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_PEER_ADOPTER_ID_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_PEER_ADOPTER_ID_2 Fld(8,16,AC_FULLB2)//[23:16]
#define MSC_2ND_TRANSMIT_DATA (IO_VIRT_MHL + IO_MHL_BASE + 0x658)
  #define MSC_2ND_TRANSMIT_DATA_0 (IO_VIRT_MHL + IO_MHL_BASE + 0x658)
  #define MSC_2ND_TRANSMIT_DATA_1 (IO_VIRT_MHL + IO_MHL_BASE + 0x659)
  #define MSC_2ND_TRANSMIT_DATA_2 (IO_VIRT_MHL + IO_MHL_BASE + 0x660)
  #define MSC_2ND_TRANSMIT_DATA_3 (IO_VIRT_MHL + IO_MHL_BASE + 0x661)
    #define REG_MSC_MT_DATA1 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MSC_MT_DATA0 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MSC_MT_CMD_OR_OFFSET Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MSC_PEER_CMD Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_MSC_MSC_MSG_CMD Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_MSC_READ_DEVCAP_CMD Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_MSC_WRITE_STAT_CMD Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_MSC_WRITE_BURST_CMD Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_MSC_DEBUG_CMD Fld(1,29,AC_MSKB3)//[29:29]
#define MSC_MT_RCVD_DATA0 (IO_VIRT_MHL + IO_MHL_BASE + 0x65C)
    #define REG_MSC_MT_RCVD_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MSC_MT_RCVD_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MSC_MT_RCVD_STATE Fld(8,16,AC_FULLB2)//[23:16]
#define MSC_MR_MSC_MSG_RCVD_1ST_DATA (IO_VIRT_MHL + IO_MHL_BASE + 0x660)
    #define REG_MSC_MR_MSC_MSG_RCVD_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MSC_MR_MSC_MSG_RCVD_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MSC_MR_RCVD_OFFSET Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MSC_MR_RCVD_DATA Fld(8,24,AC_FULLB3)//[31:24]
#define MSC_HEARTBEAT_CONTROL (IO_VIRT_MHL + IO_MHL_BASE + 0x664)
    #define REG_MSC_HB_PERIOD_MSB Fld(4,0,AC_MSKB0)//[3:0]
    #define REG_MSC_HB_FAIL_LIMIT Fld(3,4,AC_MSKB0)//[6:4]
    #define REG_MSC_HB_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_MSC_HB_FAIL_CNT Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_HW_HB_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_MSC_WRITE_BURST_LEN Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_DISABLE_GET_VS1_ERRORCODE Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_DISABLE_GET_DDC_ERRORCODE Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_DISABLE_DDC_ON_CBUS Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_DISABLE_MSC_ON_CBUS Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_XDEVCAP_EN Fld(1,31,AC_MSKB3)//[31:31]
#define DDC_ERRORCODE (IO_VIRT_MHL + IO_MHL_BASE + 0x668)
    #define REG_DDC_ERRORCODE Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MSC_ERRORCODE Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_DDC_RETRY_FAIL_LIMIT Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_MSC_RETRY_FAIL_LIMIT Fld(4,24,AC_MSKB3)//[27:24]
#define DDC_TIMEOUT (IO_VIRT_MHL + IO_MHL_BASE + 0x670)
    #define REG_DDC_TIMEOUT_MAX_MSB Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MSC_TIMEOUT_MAX_MSB Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_DDC_RETRY_MAX_MSB Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MSC_RETRY_MAX_MSB Fld(8,24,AC_FULLB3)//[31:24]
#define CBUS_DDC_SPEED_CONTROL (IO_VIRT_MHL + IO_MHL_BASE + 0x674)
    #define REG_DDC_SPEED_CTRL Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_DDC_ST_TIMING_CTRL Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_DDC_SP_TIMING_CTRL Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_RI_PREFETCH_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_DEV_CAT_OVR Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_SLOW_SL_ENH Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_CBUS_RCVD_PAYLOAD Fld(8,24,AC_FULLB3)//[31:24]
#define CBUS_RCVD_HC (IO_VIRT_MHL + IO_MHL_BASE + 0x678)
    #define REG_CBUS_RCVD_HC Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_CBUS_DDC_EDID_ADDR Fld(8,8,AC_FULLB1)//[15:8]
#define CBUS1_CNVT (IO_VIRT_MHL + IO_MHL_BASE + 0x67C)
    #define REG_CBUS1CNVT_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_TEARCBUS_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_CBUS1_PEERTOUT_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_CBUS1_RETRYLMT Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_CBUS1_INTR_0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_CBUS1_INTR_1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_CBUS1_INTR_2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_CBUS1_INTRMASK_0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_CBUS1_INTRMASK_1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_CBUS1_INTRMASK_2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_CBUS1_STATE Fld(6,24,AC_MSKB3)//[29:24]
    #define REG_TDM8BIF_EN Fld(1,31,AC_MSKB3)//[31:31]
#define MSC_RCVD_DATA_CNT (IO_VIRT_MHL + IO_MHL_BASE + 0x680)
    #define REG_MSC_MR_RCVD_DATA_CNT Fld(5,0,AC_MSKB0)//[4:0]
#define MDT_RCV_READ_PORT (IO_VIRT_MHL + IO_MHL_BASE + 0x684)
    #define MDT_RFIFO_DATA Fld(8,0,AC_FULLB0)//[7:0]
#define MDT_XMIT_WRITE_PORT (IO_VIRT_MHL + IO_MHL_BASE + 0x688)
    #define MDT_XFIFO_WDATA Fld(8,0,AC_FULLB0)//[7:0]
#define RX_DISC_CONTROL1 (IO_VIRT_MHL + IO_MHL_BASE + 0x690)
    #define REG_DISC_CBUSLO_TOUT_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_DISC_CBUSRDY_ASST_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_DISC_WAKEUP_SRCSEL Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_DISC_WAKEUP_SWVAL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_HW_CABLE_CONN Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_SW_CONNOVRD_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_SW_CONNOVRD_VAL Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_DISCONN_GOFF Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_DISC_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_DISC_MODE_CNT Fld(2,10,AC_MSKB1)//[11:10]
    #define REG_MHL_MODE_OVWR Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_MHL_MODE_VAL Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_RXCONN_OVWR Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_RXCONN_VAL Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_DISC_LOW_TIMEOUT_MAX Fld(5,16,AC_MSKB2)//[20:16]
#define RX_DISC_PULSE_WIDTH_MIN (IO_VIRT_MHL + IO_MHL_BASE + 0x694)
    #define REG_DISC_PULSE_WIDTH_MIN_MSB Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_DISC_PULSE_WIDTH_MAX_MSB Fld(8,8,AC_FULLB1)//[15:8]
#define RX_DISC_WAKE_PULSE1_WIDTH_MIN_L (ecbus + 0x698)
    #define REG_WAKE_PULSE1_MIN_MSB_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WAKE_PULSE1_MIN_MSB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_WAKE_PULSE1_MAX_MSB_0 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_WAKE_PULSE1_MAX_MSB_1 Fld(8,24,AC_FULLB3)//[31:24]
#define RX_DISC_WAKE_PULSE2_WIDTH_MIN_L (ecbus + 0x69C)
    #define REG_WAKE_PULSE2_MIN_MSB_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_WAKE_PULSE2_MIN_MSB_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_WAKE_PULSE2_MAX_MSB_0 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_WAKE_PULSE2_MAX_MSB_1 Fld(8,24,AC_FULLB3)//[31:24]
#define CBUS_RX_DISC_INT0 (IO_VIRT_MHL + IO_MHL_BASE + 0x6A0)
    #define REG_CBUS_DISC_INTR0_STAT2 Fld(3,0,AC_MSKB0)//[2:0]
    #define REG_CBUS_DISC_INTR0_STAT3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_CBUS_DISC_INTR0_MASK2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_CBUS_DISC_INTR0_MASK3 Fld(1,11,AC_MSKB1)//[11:11]
#define RX_DISC_AGGREGATED_INTR_STAT (IO_VIRT_MHL + IO_MHL_BASE + 0x6A4)
    #define REG_CBUS_DISC_RX_INTR_STAT Fld(1,0,AC_MSKB0)//[0:0]
#define CBUS_RX_DISC_BIT_TIME (IO_VIRT_MHL + IO_MHL_BASE + 0x6A8)
    #define REG_DISC_BIT_TIME Fld(7,0,AC_MSKB0)//[6:0]
    #define REG_CBUS_DISC_RST1 Fld(1,7,AC_MSKB0)//[7:7]
#define MHL_DEVCAP1 (IO_VIRT_MHL + IO_MHL_BASE + 0x700)
    #define REG_MHL_DEVCAP_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_DEVCAP_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_DEVCAP_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_DEVCAP_3 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_DEVCAP2 (IO_VIRT_MHL + IO_MHL_BASE + 0x704)
    #define REG_MHL_DEVCAP_4 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_DEVCAP_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_DEVCAP_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_DEVCAP_7 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_DEVCAP3 (IO_VIRT_MHL + IO_MHL_BASE + 0x708)
    #define REG_MHL_DEVCAP_8 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_DEVCAP_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_DEVCAP_A Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_DEVCAP_B Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_DEVCAP4 (IO_VIRT_MHL + IO_MHL_BASE + 0x70C)
    #define REG_MHL_DEVCAP_C Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_DEVCAP_D Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_DEVCAP_E Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_DEVCAP_F Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_INT_0 (IO_VIRT_MHL + IO_MHL_BASE + 0x720)
    #define REG_MHL_INT_0_STAT0 Fld(1,0,AC_MSKB0)//[0:0]
    #define REG_MHL_INT_0_STAT1 Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_MHL_INT_0_STAT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_MHL_INT_0_STAT3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_MHL_INT_0_STAT4 Fld(1,4,AC_MSKB0)//[4:4]
    #define REG_MHL_INT_0_STAT5 Fld(1,5,AC_MSKB0)//[5:5]
    #define REG_MHL_INT_0_STAT6 Fld(1,6,AC_MSKB0)//[6:6]
    #define REG_MHL_INT_0_STAT7 Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_MHL_INT_1_STAT0 Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_MHL_INT_1_STAT1 Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_MHL_INT_1_STAT2 Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_MHL_INT_1_STAT3 Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_MHL_INT_1_STAT4 Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_MHL_INT_1_STAT5 Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_MHL_INT_1_STAT6 Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_MHL_INT_1_STAT7 Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_MHL_INT_2_STAT0 Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_MHL_INT_2_STAT1 Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_MHL_INT_2_STAT2 Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_MHL_INT_2_STAT3 Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_MHL_INT_2_STAT4 Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_MHL_INT_2_STAT5 Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_MHL_INT_2_STAT6 Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_MHL_INT_2_STAT7 Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_MHL_INT_3_STAT0 Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_MHL_INT_3_STAT1 Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_MHL_INT_3_STAT2 Fld(1,26,AC_MSKB3)//[26:26]
    #define REG_MHL_INT_3_STAT3 Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_MHL_INT_3_STAT4 Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_MHL_INT_3_STAT5 Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_MHL_INT_3_STAT6 Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_MHL_INT_3_STAT7 Fld(1,31,AC_MSKB3)//[31:31]
#define MHL_STAT_0 (IO_VIRT_MHL + IO_MHL_BASE + 0x730)
    #define REG_MHL_STAT_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_STAT_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_STAT_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_STAT_3 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_SCRPAD1 (IO_VIRT_MHL + IO_MHL_BASE + 0x740)
    #define REG_MHL_SCRPAD_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_SCRPAD_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_SCRPAD_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_SCRPAD_3 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_SCRPAD2 (IO_VIRT_MHL + IO_MHL_BASE + 0x744)
    #define REG_MHL_SCRPAD_4 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_SCRPAD_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_SCRPAD_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_SCRPAD_7 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_SCRPAD3 (IO_VIRT_MHL + IO_MHL_BASE + 0x748)
    #define REG_MHL_SCRPAD_8 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_SCRPAD_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_SCRPAD_A Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_SCRPAD_B_ Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_SCRPAD4 (IO_VIRT_MHL + IO_MHL_BASE + 0x74C)
    #define REG_MHL_SCRPAD_C Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_SCRPAD_D Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_SCRPAD_E Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_SCRPAD_F Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTDEVCAP1 (IO_VIRT_MHL + IO_MHL_BASE + 0x780)
    #define REG_MHL_EXTDEVCAP_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTDEVCAP_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTDEVCAP_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTDEVCAP_3 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTDEVCAP2 (IO_VIRT_MHL + IO_MHL_BASE + 0x784)
    #define REG_MHL_EXTDEVCAP_4 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTDEVCAP_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTDEVCAP_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTDEVCAP_7 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTDEVCAP3 (IO_VIRT_MHL + IO_MHL_BASE + 0x788)
    #define REG_MHL_EXTDEVCAP_8 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTDEVCAP_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTDEVCAP_A Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTDEVCAP_B Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTDEVCAP4 (IO_VIRT_MHL + IO_MHL_BASE + 0x78C)
    #define REG_MHL_EXTDEVCAP_C Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTDEVCAP_D Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTDEVCAP_E Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTDEVCAP_F Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT1 (IO_VIRT_MHL + IO_MHL_BASE + 0x790)
    #define REG_MHL_EXTSTAT_0 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_3 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT2 (IO_VIRT_MHL + IO_MHL_BASE + 0x794)
    #define REG_MHL_EXTSTAT_4 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_5 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_6 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_7 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT3 (IO_VIRT_MHL + IO_MHL_BASE + 0x798)
    #define REG_MHL_EXTSTAT_8 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_9 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_A Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_B Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT4 (IO_VIRT_MHL + IO_MHL_BASE + 0x79C)
    #define REG_MHL_EXTSTAT_C Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_D Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_E Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_F Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT5 (IO_VIRT_MHL + IO_MHL_BASE + 0x7A0)
    #define REG_MHL_EXTSTAT_10 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_11 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_12 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_13 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT6 (IO_VIRT_MHL + IO_MHL_BASE + 0x7A4)
    #define REG_MHL_EXTSTAT_14 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_15 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_16 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_17 Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT7 (IO_VIRT_MHL + IO_MHL_BASE + 0x7A8)
    #define REG_MHL_EXTSTAT_18 Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_19 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_1A Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_1B Fld(8,24,AC_FULLB3)//[31:24]
#define MHL_EXTSTAT8 (IO_VIRT_MHL + IO_MHL_BASE + 0x7AC)
    #define REG_MHL_EXTSTAT_1C Fld(8,0,AC_FULLB0)//[7:0]
    #define REG_MHL_EXTSTAT_1D Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_MHL_EXTSTAT_1E Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_MHL_EXTSTAT_1F Fld(8,24,AC_FULLB3)//[31:24]

#endif
