/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
* $Author: brianpc.huang $
* $Date: 2015/05/29 $
* $RCSfile: avl_reg.h,v $
* $Revision: #1 $
*
* Description:
*         AV.link register settings
*---------------------------------------------------------------------------*/
#ifndef _HW_AVLINK_H
#define _HW_AVLINK_H

#define REG_BASE                    0x20000
#define AVLINK_BASE			        0x8580
#define AVLINK_IO_BASE              (IO_BASE + REG_BASE + AVLINK_BASE)

#define AVL_OFFSET_TR_CONFIG        0x0000
#define AVL_OFFSET_CKGEN            0x0004
#define AVL_OFFSET_RX_T_START_R     0x0008
#define AVL_OFFSET_RX_T_START_F     0x000c
#define AVL_OFFSET_RX_T_DATA        0x0010
#define AVL_OFFSET_RX_T_ACK         0x0014
#define AVL_OFFSET_RX_T_ERROR       0x0018
#define AVL_OFFSET_TX_T_START       0x001c
#define AVL_OFFSET_TX_T_DATA_R      0x0020
#define AVL_OFFSET_TX_T_DATA_F      0x0024
#define AVL_OFFSET_TX_ARB           0x0028
#define AVL_OFFSET_RX_HEADER        0x002c
#define AVL_OFFSET_RX_DATA          0x0030
#define AVL_OFFSET_RX_HD_NEXT       0x0034
#define AVL_OFFSET_RX_DATA_NEXT     0x0038
#define AVL_OFFSET_RX_CAP           0x003c
#define AVL_OFFSET_RX_EVENT         0x0040
#define AVL_OFFSET_RX_FAIL          0x0044
#define AVL_OFFSET_RX_STATUS        0x0048
#define AVL_OFFSET_TX_HD_NEXT       0x004c
#define AVL_OFFSET_TX_DATA_NEXT     0x0050
#define AVL_OFFSET_TX_HEADER        0x0054
#define AVL_OFFSET_TX_DATA          0x0058
#define AVL_OFFSET_TX_CAP           0x005c
#define AVL_OFFSET_TX_EVENT         0x0060
#define AVL_OFFSET_TX_FAIL          0x0064
#define AVL_OFFSET_TX_STATUS        0x0068
#define AVL_OFFSET_TR_TEST          0x006c

#define AVL_TR_CONFIG               (AVLINK_BASE + AVL_OFFSET_TR_CONFIG)
#define AVL_CKGEN                   (AVLINK_BASE + AVL_OFFSET_CKGEN)
#define AVL_RX_T_START_R            (AVLINK_BASE + AVL_OFFSET_RX_T_START_R)
#define AVL_RX_T_START_F            (AVLINK_BASE + AVL_OFFSET_RX_T_START_F)
#define AVL_RX_T_DATA               (AVLINK_BASE + AVL_OFFSET_RX_T_DATA)
#define AVL_RX_T_ACK                (AVLINK_BASE + AVL_OFFSET_RX_T_ACK)
#define AVL_RX_T_ERROR              (AVLINK_BASE + AVL_OFFSET_RX_T_ERROR)
#define AVL_TX_T_START              (AVLINK_BASE + AVL_OFFSET_TX_T_START)
#define AVL_TX_T_DATA_R             (AVLINK_BASE + AVL_OFFSET_TX_T_DATA_R)
#define AVL_TX_T_DATA_F             (AVLINK_BASE + AVL_OFFSET_TX_T_DATA_F)
#define AVL_TX_ARB                  (AVLINK_BASE + AVL_OFFSET_TX_ARB)
#define AVL_RX_HEADER               (AVLINK_BASE + AVL_OFFSET_RX_HEADER)
#define AVL_RX_DATA                 (AVLINK_BASE + AVL_OFFSET_RX_DATA)
#define AVL_RX_HD_NEXT              (AVLINK_BASE + AVL_OFFSET_RX_HD_NEXT)
#define AVL_RX_DATA_NEXT            (AVLINK_BASE + AVL_OFFSET_RX_DATA_NEXT)
#define AVL_RX_CAP                  (AVLINK_BASE + AVL_OFFSET_RX_CAP)
#define AVL_RX_EVENT                (AVLINK_BASE + AVL_OFFSET_RX_EVENT)
#define AVL_RX_FAIL                 (AVLINK_BASE + AVL_OFFSET_RX_FAIL)
#define AVL_RX_STATUS               (AVLINK_BASE + AVL_OFFSET_RX_STATUS)
#define AVL_TX_HD_NEXT              (AVLINK_BASE + AVL_OFFSET_TX_HD_NEXT)
#define AVL_TX_DATA_NEXT            (AVLINK_BASE + AVL_OFFSET_TX_DATA_NEXT)
#define AVL_TX_HEADER               (AVLINK_BASE + AVL_OFFSET_TX_HEADER)
#define AVL_TX_DATA                 (AVLINK_BASE + AVL_OFFSET_TX_DATA)
#define AVL_TX_CAP                  (AVLINK_BASE + AVL_OFFSET_TX_CAP)
#define AVL_TX_EVENT                (AVLINK_BASE + AVL_OFFSET_TX_EVENT)
#define AVL_TX_FAIL                 (AVLINK_BASE + AVL_OFFSET_TX_FAIL)
#define AVL_TX_STATUS               (AVLINK_BASE + AVL_OFFSET_TX_STATUS)
#define AVL_TR_TEST                 (AVLINK_BASE + AVL_OFFSET_TR_TEST)

#define RXING_H_ACK                 Fld(1, 14, AC_MSKB1) //14
#define RXING_D_ACK                 Fld(1, 12, AC_MSKB1) //12
#define WTX_M3_ID                   Fld(3, 8, AC_MSKB1) //10:8
#define WTX_M1_DIR                  Fld(1, 7, AC_MSKB0) //7
#define WTX_M1_PAS                  Fld(1, 6, AC_MSKB0) //6
#define WTX_M1_NAS                  Fld(1, 5, AC_MSKB0) //5
#define WTX_M1_DES                  Fld(1, 4, AC_MSKB0) //4
#define WTX_MODE                    Fld(2, 0, AC_MSKB0) //1:0
#define I_EN_OV                     Fld(1, 4, AC_MSKB0) //4
#define I_EN_BR                     Fld(1, 0, AC_MSKB0) //0
#define I_EN_HEADER                 Fld(1, 6, AC_MSKB0) //6
#define I_EN_UN                     Fld(1, 4, AC_MSKB0) //4
#define I_EN_LOW                    Fld(1, 2, AC_MSKB0) //2
#define I_EN_FAIL                   Fld(1, 3, AC_MSKB0) //3
#define I_EN_BS                     Fld(1, 1, AC_MSKB0) //1
#define I_EN_RB                     Fld(1, 0, AC_MSKB0) //0
#define AVL_TX_INPUT_DELAY          Fld(5, 0, AC_MSKB0) //0:4
#define PDN                         Fld(1, 16, AC_MSKB2) //16
#define DIV_SEL                     Fld(16, 0, AC_FULLW10) //15:0
#define BCNT_NEW_INIT               Fld(4, 0, AC_MSKB0) //3:0
#define BCNT_NEW_MSG                Fld(4, 4, AC_MSKB0) //7:4
#define BCNT_RETRANSMIT             Fld(4, 8, AC_MSKB1) //11:8
#define MAX_RETRANSMIT              Fld(4, 12, AC_MSKB1) //15:12


#define AVL_ENABLE_INT_OV(onoff)        vIO32WriteFldAlign(AVL_RX_EVENT, onoff, I_EN_OV)
#define AVL_ENABLE_INT_BR_RDY(onoff)    vIO32WriteFldAlign(AVL_RX_EVENT, onoff, I_EN_BR)
#define AVL_ENABLE_INT_HEADER_RDY(onoff) vIO32WriteFldAlign(AVL_RX_EVENT, onoff, I_EN_HEADER)
#define AVL_ENABLE_INT_UN(onoff)        vIO32WriteFldAlign(AVL_TX_EVENT, onoff, I_EN_UN)
#define AVL_ENABLE_INT_LOW(onoff)       vIO32WriteFldAlign(AVL_TX_EVENT, onoff, I_EN_LOW)
#define AVL_ENABLE_INT_FAIL(onoff)      vIO32WriteFldAlign(AVL_TX_EVENT, onoff, I_EN_FAIL)
#define AVL_ENABLE_INT_BS(onoff)        vIO32WriteFldAlign(AVL_TX_EVENT, onoff, I_EN_BS)
#define AVL_ENABLE_INT_RB(onoff)        vIO32WriteFldAlign(AVL_TX_EVENT, onoff, I_EN_RB)

#define ENABLE_PINMUX_TO_AVLINK()   BSP_PinSet(PINMUX_OPCTRL_0, PINMUX_FUNCTION1)


#define AVL_FLOW_CONTROL_ACK(onoff) \
do {\
	vIO32WriteFldAlign(AVL_RX_HD_NEXT, (!(onoff)), RXING_H_ACK);\
	vIO32WriteFldAlign(AVL_RX_HD_NEXT, (!(onoff)), RXING_D_ACK);\
} while (0)



#endif /* _HW_AVLINK_H */

