/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
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 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
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 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
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 * This program is free software; you can redistribute it and/or modify
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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 * BSD LICENSE
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 * Copyright(C) 2019 MediaTek Inc.
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/*-----------------------------------------------------------------------------
 *
 * $Author: jiewen.zhou $
 * $Date  $
 * $RCSfile: drv_vbyone.h,v $
 * $Revision: #2 $
 *
 *---------------------------------------------------------------------------*/

#include "hw_vbyone.h" 
#include "hw_mlvds.h" 

extern BOOL _fgVB1UseFixTERM;
extern UINT8 _u1VB1FixTERMVal;

// Data Path
// Control
#define vDrvVByOneCrtlBitTRIG(bfg) vIO32WriteFldAlign(VB1ANA0,bfg,VB1ANA0_TRIG_CTL_BIT)
#define vDrvVByOneCrtlBitEnable(bEn) vIO32WriteFldAlign(VB1ANA0,bEn,VB1ANA0_SN_CTL_BIT)
#define vDrvVByOneCrtlBitDisTRIG(bDisEn) vIO32WriteFldAlign(VB1ANA0,bDisEn,VB1ANA0_DISABLE_TRIG)
#define vDrvVByOneCrtlBitVEDGE(bEdge) vIO32WriteFldAlign(VB1ANA0,bEdge,VB1ANA0_VEDGE_SEL)
// Encode
#define vDrvVByOneCrtlBitVP(bVP) vIO32WriteFldAlign(VB1ANA0,bVP,VB1ANA0_CTL_BIT_LANE0_VP)
#define vDrvVByOneCrtlBitRA(bRA) vIO32WriteFldAlign(VB1ANA0,bRA,VB1ANA0_CTL_BIT_LANE0_RA)
#define vDrvVByOneCrtlBit3DST(u13DST) vIO32WriteFldAlign(VB1ANA0,u13DST,VB1ANA0_CTL_BIT_LANE0_3DST)
#define vDrvVByOneCrtlBitPICHSize(u2PIC_HSize) vIO32WriteFldAlign(VB1ANA0,u2PIC_HSize,VB1ANA0_CTL_BIT_LANE0_PIC_HSIZE)

#define vDrvVByOneCrtlBitCBV(bCBV) vIO32WriteFldAlign(VB1ANA2,bCBV,VB1ANA2_CTL_BIT_LANE1_CBV)
#define vDrvVByOneCrtlBitCF(u1CF) vIO32WriteFldAlign(VB1ANA2,u1CF,VB1ANA2_CTL_BIT_LANE1_CF)
#define vDrvVByOneCrtlBitRF(bRF) vIO32WriteFldAlign(VB1ANA2,bRF,VB1ANA2_CTL_BIT_LANE1_RF)
#define vDrvVByOneCrtlBitPICVSize(u2PIC_VSize) vIO32WriteFldAlign(VB1ANA2,u2PIC_VSize,VB1ANA2_CTL_BIT_LANE1_PIC_VSIZE)

#define vDrvVByOneCrtlBitAT(bAT) vIO32WriteFldAlign(VB1ANA3,bAT,VB1ANA3_CTL_BIT_LANE2_AT)
#define vDrvVByOneCrtlBitCROPHPos(u2CROP_HPos) vIO32WriteFldAlign(VB1ANA3,u2CROP_HPos,VB1ANA3_CTL_BIT_LANE2_CROP_HPOS)

#define vDrvVByOneCrtlBitARLsb(u1ARLSB) vIO32WriteFldAlign(VB1ANA4,u1ARLSB,VB1ANA4_CTL_BIT_LANE3_AR_LSB)
#define vDrvVByOneCrtlBitCROPVPos(u2CROP_VPos) vIO32WriteFldAlign(VB1ANA4,u2CROP_VPos,VB1ANA4_CTL_BIT_LANE3_CROP_VPOS)

#define vDrvVByOneCrtlBitARMsb(bARMSB) vIO32WriteFldAlign(VB1ANA5,bARMSB,VB1ANA5_CTL_BIT_LANE4_AR_MSB)
#define vDrvVByOneCrtlBitCROPHSize(u2CROP_HSize) vIO32WriteFldAlign(VB1ANA5,u2CROP_HSize,VB1ANA5_CTL_BIT_LANE4_CROP_HSIZE)

#define vDrvVByOneCrtlBitCTLsb(u1CTLSB) vIO32WriteFldAlign(VB1ANA6,u1CTLSB,VB1ANA6_CTL_BIT_LANE5_CT_LSB)
#define vDrvVByOneCrtlBitCROPVSize(u2CROP_VSize) vIO32WriteFldAlign(VB1ANA6,u2CROP_VSize,VB1ANA6_CTL_BIT_LANE5_CROP_VSIZE)

#define vDrvVByOneCrtlBitCTMsb(bCTMSB) vIO32WriteFldAlign(VB1ANA7,bCTMSB,VB1ANA7_CTL_BIT_LANE6_CT_MSB)
#define vDrvVByOneCrtlBitSARHSize(u2SAR_HSize) vIO32WriteFldAlign(VB1ANA7,u2SAR_HSize,VB1ANA7_CTL_BIT_LANE6_SAR_HSIZE)

#define vDrvVByOneCrtlBitSARVSize(u2SAR_VSize) vIO32WriteFldAlign(VB1ANA8,u2SAR_VSize,VB1ANA8_CTL_BIT_LANE7_SAR_VSIZE)

#define VB1_8LANE_00112233SWAP 1  // need to remove after verification

void vDrvVByOneOn(void);
void vDrvVByOneOff(void);
void vVByOneInit(void);
void vDrvVByOneGFXClkSet(void);
void vDrvVByOneOSDOn(void);
void vDrvVByOneOSDOff(void);
void vDrvVByOneOSDCRCCheck(void);
void vVByOneOSDFormatConfig(void);
void vVByOneLane4_8bit_script(void);
void vVByOneLane4_10bit_script(void);
void vVByOneLane4_12bit_script(void);
void vVByOne_Impedance_Cal(void);
void vVByOneAnalogOffSetting(void);
void vGetVByOneStatus(void);
void vDrvVByOneCRCCheck(void);
#ifdef __MODEL_slt__
void vDrvGetVByOneCRC(UINT32 *u4VB1Lane, UINT32 *pu4Crc);
#endif
void vVByOneTestMode(void);
void vVByOneFormatConfig(void);
void vGetVByOneUnLock(void);
void vGetVByOneUnLockCnt(void);
void vSetVByOneUnLockChk(UINT8 u1En);
void vDrvVB14K2KPanelInterfaceConfig(void);
void vDrvVB1LockCtrl(UINT8 bOnOff, UINT8 bValue);
void vVByOneLaneSwapForTest(UINT8 u1Mode);
void vVByOneSingleLanePadEn(UINT8 u1LaneEn);
void vVByOneVPLLBandwidthSet(UINT8 u1Bandwidth);
void vVByOnePreEmphasisOnOff(UINT8 u1OnOff);
void vVByOnePreEmphasisSet(UINT8 value);
UINT8 vVByOneGetPreEmphasis(void);
void vVByOneOSDYSEnable(UINT8 u1OnOff);
void VByOne2SecPattern(void);
void VByOne4SecPattern(void);
void VByOne8SecPattern(void);

// OSD Path
// Control
#define vDrvVByOneGMCrtlBitTRIG(bfg) vIO32WriteFldAlign(VB1OSDANA0,bfg,VB1OSDANA0_OSD_TRIG_CTL_BIT)
#define vDrvVByOneGMCrtlBitEnable(bEn) vIO32WriteFldAlign(VB1OSDANA0,bEn,VB1OSDANA0_OSD_SN_CTL_BIT)
#define vDrvVByOneGMCrtlBitDisTRIG(bDisEn) vIO32WriteFldAlign(VB1OSDANA0,bDisEn,VB1OSDANA0_OSD_DISABLE_TRIG)
#define vDrvVByOneGMCrtlBitVEDGE(bEdge) vIO32WriteFldAlign(VB1OSDANA0,bEdge,VB1OSDANA0_OSD_VEDGE_SEL)
// Encode
#define vDrvVByOneGMCrtlBitVF(bVF) vIO32WriteFldAlign(VB1OSDANA0,bVF,VB1OSDANA0_CTL_BIT_OSD_LANE0_VF)
#define vDrvVByOneGMCrtlBitGF(bGF) vIO32WriteFldAlign(VB1OSDANA0,bGF,VB1OSDANA0_CTL_BIT_OSD_LANE0_GF)
#define vDrvVByOneGMCrtlBitHTotal(u2HTotal) vIO32WriteFldAlign(VB1OSDANA0,u2HTotal,VB1OSDANA0_CTL_BIT_OSD_LANE0_HTOTAL)
#define vDrvVByOneGMCrtlBitVTotal(u2VTotal) vIO32WriteFldAlign(VB1OSDANA2,u2VTotal,VB1OSDANA2_CTL_BIT_OSD_LANE1_VTOTAL)
#define vDrvVByOneGMCrtlBitHDEStart(u2HDEStart) vIO32WriteFldAlign(VB1OSDANA3,u2HDEStart,VB1OSDANA3_CTL_BIT_OSD_LANE2_HDEStart)
#define vDrvVByOneGMCrtlBitVDEStart(u2VDEStart) vIO32WriteFldAlign(VB1OSDANA4,u2VDEStart,VB1OSDANA4_CTL_BIT_OSD_LANE3_VDEStart)

// 2/4/8 Section
// Enable/Disable
#define vDrvVByOne2SecOnOff(bfg) vIO32WriteFldAlign(VINTF_P19, bfg, VINTF_2SEC_EN)
#define vDrvVByOne4SecOnOff(bfg) vIO32WriteFldAlign(VINTF_P19, bfg, VINTF_4SEC_EN)
#define vDrvVByOne8SecOnOff(bfg) vIO32WriteFldAlign(VINTF_P19, bfg, VINTF_8SEC_EN)
