/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_HDMI14ANA_H_
#define _HW_HDMI14ANA_H_
#include "x_hal_5381.h"

//---------------------------HDMI Rx1.4 PHY ---------------------------//
#define IO_HDMI1_RX_BASE 0x62000

//Page TABLE
#define HDMI1_REG_HDMIRX14_CFG0 (IO_VIRT + IO_HDMI1_RX_BASE + 0x000)
    #define REG_HDMIRX14_CFG0_RG_HDMI_CDR_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_HDMIRX14_CFG0_RG_HDMI_CDR_STOP Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_HDMIRX14_CFG0_RG_HDMI_ATEST_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_HDMIRX14_CFG0_RG_HDMI_ANAMON Fld(3,24,AC_MSKB3)//[26:24]
    #define REG_HDMIRX14_CFG0_RG_HDMI_CH0_CDRLPI Fld(7,16,AC_MSKB2)//[22:16]
    #define REG_HDMIRX14_CFG0_RG_HDMI_CH1_CDRLPI Fld(7,8,AC_MSKB1)//[14:8]
    #define REG_HDMIRX14_CFG0_RG_HDMI_CH2_CDRLPI Fld(7,0,AC_MSKB0)//[6:0]
#define HDMI1_REG_HDMIRX14_CFG1 (IO_VIRT + IO_HDMI1_RX_BASE + 0x004)
    #define REG_HDMIRX14_CFG1_RG_HDMI_CKDT_AEN Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_HDMIRX14_CFG1_RG_HDMI_CKDT_SET Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_HDMIRX14_CFG1_RG_HDMI_HYBIAS Fld(2,25,AC_MSKB3)//[26:25]
    #define REG_HDMIRX14_CFG1_RG_HDMI_CLKBUF_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_HDMIRX14_CFG1_RG_HDMI_DATA_RST Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_PD Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_HDMIRX14_CFG1_RG_HDMI_D2SBIAS Fld(2,20,AC_MSKB2)//[21:20]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_FILT Fld(4,16,AC_MSKB2)//[19:16]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_FIL_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_PRBSCK_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_SWRSTSEL Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_RST Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_HDMIRX14_CFG1_RG_HDMI_HY Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQ_PATTERN_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define REG_HDMIRX14_CFG1_RG_HDMI_EQBIAS Fld(2,5,AC_MSKB0)//[6:5]
    #define REG_HDMIRX14_CFG1_RG_HDMI_FULL_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_HDMIRX14_CFG1_RG_HDMI_VREF Fld(3,0,AC_MSKB0)//[2:0]
#define HDMI1_REG_HDMIRX14_CFG2 (IO_VIRT + IO_HDMI1_RX_BASE + 0x008)
    #define REG_HDMIRX14_CFG2_RG_HDMI_MHLEN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_HDMIRX14_CFG2_RG_HDMI_MHLMODE Fld(1,30,AC_MSKB3)//[30:30]
    #define REG_HDMIRX14_CFG2_RG_HDMI_FTMODE Fld(1,29,AC_MSKB3)//[29:29]
    #define REG_HDMIRX14_CFG2_RG_HDMI_PI_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_HDMIRX14_CFG2_RG_HDMI_R2R_CK_SEL Fld(1,27,AC_MSKB3)//[27:27]
    #define REG_HDMIRX14_CFG2_RG_HDMI_KPGAIN Fld(3,24,AC_MSKB3)//[26:24]
    #define REG_HDMIRX14_CFG2_RG_HDMI_PLLCK_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_HDMIRX14_CFG2_RG_HDMI_RXAFE_EN_SW Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_HDMIRX14_CFG2_RG_HDMI_RXAFECH0_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_HDMIRX14_CFG2_RG_HDMI_RXAFECH1_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_HDMIRX14_CFG2_RG_HDMI_RXAFECH2_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_HDMIRX14_CFG2_RG_HDMI_TERM_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_HDMIRX14_CFG2_RG_HDMI_ZSEN_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_HDMIRX14_CFG2_RG_HDMI_TERM_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_HDMIRX14_CFG2_RG_HDMI_RXMODE Fld(2,12,AC_MSKB1)//[13:12]
    #define REG_HDMIRX14_CFG2_RG_HDMI_EQBAND Fld(2,9,AC_MSKB1)//[10:9]
    #define REG_HDMIRX14_CFG2_RG_HDMI_TEST_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_HDMIRX14_CFG2_RG_HDMI_EQ_GAIN Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_HDMIRX14_CFG2_RG_HDMI_TERM_MHL_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define REG_HDMIRX14_CFG2_RG_HDMI_TERM_CM_ENB Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_HDMIRX14_CFG2_RG_HDMI_DEEPCLRCLK_PDB Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_HDMIRX14_CFG2_RG_HDMI_DEEPCLRCLK_RSTN Fld(1,0,AC_MSKB0)//[0:0]
#define HDMI1_REG_HDMIRX14_CFG3 (IO_VIRT + IO_HDMI1_RX_BASE + 0x00C)
    #define REG_HDMIRX14_CFG3_RG_HDMI_FM_SEL Fld(12,0,AC_MSKW10)//[11:0]
#define HDMI1_REG_HDMIRX14_CFG4 (IO_VIRT + IO_HDMI1_RX_BASE + 0x010)
    #define REG_HDMIRX14_CFG4_RG_HDMI_TESTE Fld(1,0,AC_MSKB0)//[0:0]
#define HDMI1_REG_HDMIRX14_CFG5 (IO_VIRT + IO_HDMI1_RX_BASE + 0x014)
    #define REG_HDMIRX14_CFG5_RG_HDMI_CKMON_JITSEL Fld(1,25,AC_MSKB3)//[25:25]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CKMON_DIV4EN Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CKMON_JITEN Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_HDMIRX14_CFG5_RG_HDMI_FLAG_SEL Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_HDMIRX14_CFG5_RG_HDMI_ABIST_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_HDMIRX14_CFG5_RG_HDMI_ABISTCK_SEL Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CKMON_CKSET Fld(2,17,AC_MSKB2)//[18:17]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CH0_MONEN Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CH1_MONEN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CH2_MONEN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CKMON_PLLSEL Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_HDMIRX14_CFG5_RG_HDMI_EQ_CALEN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CH2_EQMC Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CH1_EQMC Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_HDMIRX14_CFG5_RG_HDMI_CH0_EQMC Fld(4,0,AC_MSKB0)//[3:0]
#define HDMI1_REG_HDMIRX14_CFG6 (IO_VIRT + IO_HDMI1_RX_BASE + 0x018)
    #define REG_HDMIRX14_CFG6_RG_HDMI_REV Fld(32,0,AC_FULLDW)//[31:0]
#define HDMI1_REG_HDMIRX14_CFG7 (IO_VIRT + IO_HDMI1_RX_BASE + 0x01C)
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_FBKDIV Fld(7,24,AC_MSKB3)//[30:24]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_DDSFBK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_RLH_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_FBKSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_POSDIV Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_IC Fld(4,12,AC_MSKB1)//[15:12]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_IR Fld(4,8,AC_MSKB1)//[11:8]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_BP Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_BC Fld(2,2,AC_MSKB0)//[3:2]
    #define REG_HDMIRX14_CFG7_RG_HDMI_PLL_BR Fld(2,0,AC_MSKB0)//[1:0]
#define HDMI1_REG_HDMIRX14_CFG8 (IO_VIRT + IO_HDMI1_RX_BASE + 0x020)
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_AUTOK_LOAD Fld(1,31,AC_MSKB3)//[31:31]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_DIVEN Fld(3,28,AC_MSKB3)//[30:28]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_AUTOK_KS Fld(2,26,AC_MSKB3)//[27:26]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_AUTOK_KF Fld(2,24,AC_MSKB3)//[25:24]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_AUTOK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_BAND Fld(7,16,AC_MSKB2)//[22:16]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_MONCK_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_MONVC_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_MONREF_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_LVROD_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_BIAS_LPF_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_BIAS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_RST_DLY Fld(2,8,AC_MSKB1)//[9:8]
    #define REG_HDMIRX14_CFG8_RG_HDMI_PLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define HDMI1_REG_HDMIRX14_CFG9 (IO_VIRT + IO_HDMI1_RX_BASE + 0x024)
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_BRA Fld(1,28,AC_MSKB3)//[28:28]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_BCA Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_DIVENA Fld(3,20,AC_MSKB2)//[22:20]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_ICADJ Fld(2,18,AC_MSKB2)//[19:18]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_KVSEL Fld(2,16,AC_MSKB2)//[17:16]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_VCO_BAND Fld(5,8,AC_MSKB1)//[12:8]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_DIVCTRL Fld(2,4,AC_MSKB0)//[5:4]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_DETEN Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_HDMIRX14_CFG9_RG_HDMI_PLL_DIV2_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define HDMI1_RGS_HDMIRX14_CFG0 (IO_VIRT + IO_HDMI1_RX_BASE + 0x028)
    #define RGS_HDMIRX14_CFG0_RGS_HDMI_CH0_CDRLPO Fld(7,24,AC_MSKB3)//[30:24]
    #define RGS_HDMIRX14_CFG0_RGS_HDMI_CH0_ABIST_FLAG1 Fld(1,21,AC_MSKB2)//[21:21]
    #define RGS_HDMIRX14_CFG0_RGS_HDMI_CH0_ABIST_FLAG2 Fld(1,20,AC_MSKB2)//[20:20]
    #define RGS_HDMIRX14_CFG0_RGS_HDMI_CH0_EQERR Fld(4,16,AC_MSKB2)//[19:16]
    #define RGS_HDMIRX14_CFG0_RGS_HDMI_CH0_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HDMI1_RGS_HDMIRX14_CFG1 (IO_VIRT + IO_HDMI1_RX_BASE + 0x02C)
    #define RGS_HDMIRX14_CFG1_RGS_HDMI_CH1_CDRLPO Fld(7,24,AC_MSKB3)//[30:24]
    #define RGS_HDMIRX14_CFG1_RGS_HDMI_CH1_ABIST_FLAG1 Fld(1,21,AC_MSKB2)//[21:21]
    #define RGS_HDMIRX14_CFG1_RGS_HDMI_CH1_ABIST_FLAG2 Fld(1,20,AC_MSKB2)//[20:20]
    #define RGS_HDMIRX14_CFG1_RGS_HDMI_CH1_EQERR Fld(4,16,AC_MSKB2)//[19:16]
    #define RGS_HDMIRX14_CFG1_RGS_HDMI_CH1_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HDMI1_RGS_HDMIRX14_CFG2 (IO_VIRT + IO_HDMI1_RX_BASE + 0x030)
    #define RGS_HDMIRX14_CFG2_RGS_HDMI_CH2_CDRLPO Fld(7,24,AC_MSKB3)//[30:24]
    #define RGS_HDMIRX14_CFG2_RGS_HDMI_CH2_ABIST_FLAG1 Fld(1,21,AC_MSKB2)//[21:21]
    #define RGS_HDMIRX14_CFG2_RGS_HDMI_CH2_ABIST_FLAG2 Fld(1,20,AC_MSKB2)//[20:20]
    #define RGS_HDMIRX14_CFG2_RGS_HDMI_CH2_EQERR Fld(4,16,AC_MSKB2)//[19:16]
    #define RGS_HDMIRX14_CFG2_RGS_HDMI_CH2_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define HDMI1_RGS_HDMIRX14_CFG3 (IO_VIRT + IO_HDMI1_RX_BASE + 0x034)
    #define RGS_HDMIRX14_CFG3_RGS_HDMI_CH0_EQMM Fld(1,30,AC_MSKB3)//[30:30]
    #define RGS_HDMIRX14_CFG3_RGS_HDMI_CH1_EQMM Fld(1,29,AC_MSKB3)//[29:29]
    #define RGS_HDMIRX14_CFG3_RGS_HDMI_CH2_EQMM Fld(1,28,AC_MSKB3)//[28:28]
    #define RGS_HDMIRX14_CFG3_RGS_HDMI_PLL_AUTOK_PASS Fld(1,25,AC_MSKB3)//[25:25]
    #define RGS_HDMIRX14_CFG3_RGS_HDMI_PLL_AUTOK_FAIL Fld(1,24,AC_MSKB3)//[24:24]
    #define RGS_HDMIRX14_CFG3_RGS_HDMI_PLL_AUTOK_BAND Fld(7,16,AC_MSKB2)//[22:16]
#endif

