/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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 *****************************************************************************/


/*****************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: hw_tddc.h $
 *
 * Project:
 * --------
 *   MT5381
 *
 * Description:
 * ------------
 *   LCPROC register definition
 *
 * Author:
 * -------
 *   Jeffrey Xuan
 *
 * Last changed:
 * -------------
 * $Author: fu-hsi.huang $
 *
 * $Modtime: 07/04/06 1:22p $
 *
 * $Revision: #2 $
****************************************************************************/

#ifndef _HW_TDDC_H_
#define _HW_TDDC_H_

#include "hw_vdoin.h"

#define IO_TDDC_BASE (IO_VIRT+0x5D000)


//Page TDDC
#define TDDC_00 (IO_TDDC_BASE + 0xE00)
    #define C_TDDC_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define C_TDDC_FW_TRIG Fld(1,30,AC_MSKB3)//[30:30]
    #define C_TDDC_FW_DIRECTION_Y_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define C_TDDC_FW_DIRECTION_Y Fld(1,28,AC_MSKB3)//[28:28]
    #define C_TDDC_HW_TRIG_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define C_TDDC_TRIG_NUM Fld(3,24,AC_MSKB3)//[26:24]
    #define C_TDDC_IMG_WIDTH Fld(12,12,AC_MSKW21)//[23:12]
    #define C_TDDC_IMG_HEIGHT Fld(12,0,AC_MSKW10)//[11:0]
#define TDDC_01 (IO_TDDC_BASE + 0xE04)
    #define C_TDDC_POWER_SAVE_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define C_TDDC_POWER_INI_NUM Fld(7,24,AC_MSKB3)//[30:24]
    #define C_TDDC_SA_ACCESS_INTERVAL Fld(8,0,AC_FULLB0)//[7:0]
#define TDDC_02 (IO_TDDC_BASE + 0xE08)
    #define C_TDDC_SR_H Fld(9,8,AC_MSKW21)//[16:8]
    #define C_TDDC_SR_V Fld(5,0,AC_MSKB0)//[4:0]
#define TDDC_03 (IO_TDDC_BASE + 0xE0C)
    #define C_TDDC_DRAM_WT_MV_ZERO Fld(1,31,AC_MSKB3)//[31:31]
    #define C_TDDC_DRAM_WT_MV_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define C_TDDC_DRAM_RD_MV_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define C_TDDC_DRAM_RD_SA_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define C_TDDC_MV_TEST Fld(1,24,AC_MSKB3)//[24:24]
    #define C_TDDC_MV_WT_STR_ADR Fld(24,0,AC_MSKDW)//[23:0]
#define TDDC_04 (IO_TDDC_BASE + 0xE10)
    #define C_TDDC_MV_END_ADR Fld(24,0,AC_MSKDW)//[23:0]
#define TDDC_05 (IO_TDDC_BASE + 0xE14)
    #define C_TDDC_SA_STR_ADR_L Fld(24,0,AC_MSKDW)//[23:0]
#define TDDC_06 (IO_TDDC_BASE + 0xE18)
    #define C_TDDC_SA_STR_ADR_R Fld(24,0,AC_MSKDW)//[23:0]
#define TDDC_07 (IO_TDDC_BASE + 0xE1C)
    #define C_TDDC_MV_RD_STR_ADR Fld(24,0,AC_MSKDW)//[23:0]
#define TDDC_08 (IO_TDDC_BASE + 0xE20)
    #define C_TDDC_DBG_SEL Fld(4,17,AC_MSKB2)//[20:17]
    #define SAMPLE_MV_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define SAMPLE_BLK_X Fld(7,8,AC_MSKB1)//[14:8]
    #define SAMPLE_BLK_Y Fld(7,0,AC_MSKB0)//[6:0]
#define TDDC_STATUS1 (IO_TDDC_BASE + 0xE30)
    #define RD_TDDC_CAL_READY Fld(1,31,AC_MSKB3)//[31:31]
    #define RD_DIRECTION_X Fld(1,29,AC_MSKB3)//[29:29]
    #define RD_DIRECTION_Y Fld(1,28,AC_MSKB3)//[28:28]
    #define RD_CUR_BLK_X Fld(8,20,AC_MSKW32)//[27:20]
    #define RD_CUR_BLK_Y Fld(8,12,AC_MSKW21)//[19:12]
    #define RD_MV_READY Fld(1,8,AC_MSKB1)//[8:8]
    #define RD_SA_READY Fld(1,7,AC_MSKB0)//[7:7]
    #define RD_TRIG_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define RD_TDDC_CUR_STATE Fld(4,0,AC_MSKB0)//[3:0]
#define TDDC_STATUS2 (IO_TDDC_BASE + 0xE34)
    #define RD_SAMPLE_MV_X_L Fld(10,22,AC_MSKW32)//[31:22]
    #define RD_SAMPLE_MV_Y_L Fld(6,16,AC_MSKB2)//[21:16]
    #define RD_SAMPLE_MV_X_R Fld(10,6,AC_MSKW10)//[15:6]
    #define RD_SAMPLE_MV_Y_R Fld(6,0,AC_MSKB0)//[5:0]
#define TDDC_ATPG (IO_TDDC_BASE + 0xE3C)
    #define C_TDDC_RESERVED Fld(30,2,AC_MSKDW)//[31:2]
    #define TDDC_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define TDDC_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]

//Page TDDCDS
#define TDDCDS_00 (IO_TDDC_BASE + 0xE40)
    #define C_DIA_OB_MODE Fld(1,27,AC_MSKB3)//[27:27]
    #define C_DV_MODE Fld(2,25,AC_MSKB3)//[26:25]
    #define C_ORD_OB_MODE Fld(1,21,AC_MSKB2)//[21:21]
    #define C_OBDE_MODE Fld(1,20,AC_MSKB2)//[20:20]
    #define C_ORD_CORING Fld(4,16,AC_MSKB2)//[19:16]
    #define C_ORD_TH Fld(8,8,AC_FULLB1)//[15:8]
    #define C_ORD_PNLTY_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define C_DV_CAND_NUM Fld(4,0,AC_MSKB0)//[3:0]
#define TDDCDS_01 (IO_TDDC_BASE + 0xE44)
    #define C_SM_DV_PNLTY_STN Fld(1,31,AC_MSKB3)//[31:31]
    #define C_SM_DV_TH2 Fld(4,22,AC_MSKW32)//[25:22]
    #define C_SM_DV_TH Fld(8,14,AC_MSKW21)//[21:14]
    #define C_SM_DV_VAR_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define C_SM_DV_ADA_BASE Fld(4,8,AC_MSKB1)//[11:8]
    #define C_SM_DV_Y_PNLTY_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define C_SM_DV_X_PNLTY_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define TDDCDS_02 (IO_TDDC_BASE + 0xE48)
    #define C_REFINE_PNLTY_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define C_GMV_PNLTY_SEL Fld(4,24,AC_MSKB3)//[27:24]
    #define C_PREV_PNLTY_SEL Fld(4,20,AC_MSKB2)//[23:20]
    #define C_NBR_PNLTY_SEL Fld(4,16,AC_MSKB2)//[19:16]
    #define C_VAR_PNLTY_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define C_RAND_PNLTY_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define C_TMPR_PNLTY_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define C_SPTL_PNLTY_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define TDDCDS_03 (IO_TDDC_BASE + 0xE4C)
    #define C_RAND_COST Fld(6,24,AC_MSKB3)//[29:24]
    #define C_GMV_COST Fld(4,20,AC_MSKB2)//[23:20]
    #define C_PREV_COST Fld(4,16,AC_MSKB2)//[19:16]
    #define C_NBR_COST Fld(4,12,AC_MSKB1)//[15:12]
    #define C_REFINE_COST Fld(4,8,AC_MSKB1)//[11:8]
    #define C_TMPR_COST Fld(4,4,AC_MSKB0)//[7:4]
    #define C_SPTL_COST Fld(4,0,AC_MSKB0)//[3:0]
#define TDDCDS_04 (IO_TDDC_BASE + 0xE50)
    #define C_VAR_BLK_TH Fld(4,20,AC_MSKB2)//[23:20]
    #define C_VAR_FRM_TH Fld(4,16,AC_MSKB2)//[19:16]
    #define C_VAR_CNT_TH Fld(16,0,AC_FULLW10)//[15:0]
#define TDDCDS_05 (IO_TDDC_BASE + 0xE54)
    #define C_UL_C05 Fld(5,25,AC_MSKB3)//[29:25]
    #define C_UL_C04 Fld(5,20,AC_MSKW32)//[24:20]
    #define C_UL_C03 Fld(5,15,AC_MSKW21)//[19:15]
    #define C_UL_C02 Fld(5,10,AC_MSKB1)//[14:10]
    #define C_UL_C01 Fld(5,5,AC_MSKW10)//[9:5]
    #define C_UL_C00 Fld(5,0,AC_MSKB0)//[4:0]
#define TDDCDS_06 (IO_TDDC_BASE + 0xE58)
    #define C_UL_C11 Fld(5,25,AC_MSKB3)//[29:25]
    #define C_UL_C10 Fld(5,20,AC_MSKW32)//[24:20]
    #define C_UL_C09 Fld(5,15,AC_MSKW21)//[19:15]
    #define C_UL_C08 Fld(5,10,AC_MSKB1)//[14:10]
    #define C_UL_C07 Fld(5,5,AC_MSKW10)//[9:5]
    #define C_UL_C06 Fld(5,0,AC_MSKB0)//[4:0]
#define TDDCDS_07 (IO_TDDC_BASE + 0xE5C)
    #define C_TYPE_C09 Fld(3,27,AC_MSKB3)//[29:27]
    #define C_TYPE_C08 Fld(3,24,AC_MSKB3)//[26:24]
    #define C_TYPE_C07 Fld(3,21,AC_MSKB2)//[23:21]
    #define C_TYPE_C06 Fld(3,18,AC_MSKB2)//[20:18]
    #define C_TYPE_C05 Fld(3,15,AC_MSKW21)//[17:15]
    #define C_TYPE_C04 Fld(3,12,AC_MSKB1)//[14:12]
    #define C_TYPE_C03 Fld(3,9,AC_MSKB1)//[11:9]
    #define C_TYPE_C02 Fld(3,6,AC_MSKW10)//[8:6]
    #define C_TYPE_C01 Fld(3,3,AC_MSKB0)//[5:3]
    #define C_TYPE_C00 Fld(3,0,AC_MSKB0)//[2:0]
#define TDDCDS_08 (IO_TDDC_BASE + 0xE60)
    #define C_TYPE_C11 Fld(3,3,AC_MSKB0)//[5:3]
    #define C_TYPE_C10 Fld(3,0,AC_MSKB0)//[2:0]
#define TDDCDS_09 (IO_TDDC_BASE + 0xE64)
    #define C_GMV_Y1 Fld(6,10,AC_MSKB1)//[15:10]
    #define C_GMV_X1 Fld(10,0,AC_MSKW10)//[9:0]
#define TDDCDS_10 (IO_TDDC_BASE + 0xE68)
    #define STA_SHIFT_V Fld(6,20,AC_MSKW32)//[25:20]
    #define STA_SHIFT_H Fld(10,10,AC_MSKW21)//[19:10]
    #define STA_HW_GLOBAL_SHIFT Fld(10,0,AC_MSKW10)//[9:0]
#define TDDCDS_11 (IO_TDDC_BASE + 0xE6C)
    #define C_LBOX_BND_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define C_LPBOX_DN Fld(12,12,AC_MSKW21)//[23:12]
    #define C_LPBOX_UP Fld(12,0,AC_MSKW10)//[11:0]
#define TDDCDS_12 (IO_TDDC_BASE + 0xE70)
    #define C_PBOX_BND_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define C_LPBOX_RT Fld(12,12,AC_MSKW21)//[23:12]
    #define C_LPBOX_LF Fld(12,0,AC_MSKW10)//[11:0]
#define TDDCDS_13 (IO_TDDC_BASE + 0xE74)
    #define STA_VAR_FRM_R Fld(16,16,AC_FULLW32)//[31:16]
    #define STA_VAR_FRM_L Fld(16,0,AC_FULLW10)//[15:0]
#define TDDCDS_15 (IO_TDDC_BASE + 0xE7C)
    #define C_SM_LUMA_TH2 Fld(4,22,AC_MSKW32)//[25:22]
    #define C_SM_LUMA_TH Fld(8,14,AC_MSKW21)//[21:14]
    #define C_SM_LUMA_VAR_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define C_SM_LUMA_ADA_BASE Fld(4,8,AC_MSKB1)//[11:8]
    #define C_SM_LUMA_Y_PNLTY_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define C_SM_LUMA_X_PNLTY_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define TDDCDS_16 (IO_TDDC_BASE + 0xE80)
    #define RAND_DV4 Fld(6,18,AC_MSKB2)//[23:18]
    #define RAND_DV3 Fld(6,12,AC_MSKW21)//[17:12]
    #define RAND_DV2 Fld(6,6,AC_MSKW10)//[11:6]
    #define RAND_DV1 Fld(6,0,AC_MSKB0)//[5:0]
#define TDDCDS_17 (IO_TDDC_BASE + 0xE84)
    #define C_DMAP_INTPL_STRNGTH Fld(4,11,AC_MSKB1)//[14:11]
    #define C_DMAP_FILTER_STRNGTH Fld(4,7,AC_MSKW10)//[10:7]
    #define C_V_EDGE_THR Fld(7,0,AC_MSKB0)//[6:0]
#define TDDCDS_18 (IO_TDDC_BASE + 0xE88)
    #define SEL_STA_PBOX Fld(1,31,AC_MSKB3)//[31:31]
    #define PBOX_STR_X Fld(12,12,AC_MSKW21)//[23:12]
    #define PBOX_END_X Fld(12,0,AC_MSKW10)//[11:0]
#define TDDCDS_19 (IO_TDDC_BASE + 0xE92)
    #define PBOX_STR_Y Fld(12,12,AC_MSKW21)//[23:12]
    #define PBOX_END_Y Fld(12,0,AC_MSKW10)//[11:0]
#define TDDCDS_ATPG (IO_TDDC_BASE + 0xEDC)
    #define C_TDDCDS_RESERVED Fld(30,2,AC_MSKDW)//[31:2]
    #define C_GMV_X1_R Fld(10,8,AC_MSKW21)
    #define C_GMV_Y1_R Fld(6,2,AC_MSKB0)
    #define TDDCDS_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define TDDCDS_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]

//Page TDDCDV
#define TDDCDV_00 (IO_TDDC_BASE + 0xEE0)
    #define C_TTD_FSAMPLE_ENABLE Fld(1,8,AC_MSKB1)//[8:8]
    #define C_TTD_CONVERGENCE_DEPTH Fld(8,0,AC_FULLB0)//[7:0]
#define TDDCDV_01 (IO_TDDC_BASE + 0xEE4)
    #define C_TTD_OUT_LR_DLY Fld(2,15,AC_MSKW21)//[16:15]
    #define STA_DMAP_ERR_OVER Fld(1,5,AC_MSKB0)//[5:5]
#define TDDCDV_ATPG (IO_TDDC_BASE + 0xEFC)
    #define C_TDDCDV_RESERVED Fld(30,2,AC_MSKDW)//[31:2]
    #define TDDCDV_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define TDDCDV_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]

#endif
