/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: robin.zhang $
 * $Date: 2015/10/09 $
 * $RCSfile: drv_nr.h,v $
 * $Revision: #3 $
 *
 *---------------------------------------------------------------------------*/
#ifndef _DRV_NR_H_
#define _DRV_NR_H_

#include "typedef.h"

#define NR_R(u4Addr, u4Fld) IO32ReadFldAlign((u4Addr), (u4Fld))

#define NR_R4B(u4Addr) u4IO32Read4B((u4Addr))

#define NR_W4B(u4Addr, u4Value) vIO32Write4B((u4Addr), (u4Value))

#define NR_W(u4Addr, u4Value, u4Fld) \
    vIO32WriteFldAlign((u4Addr), (u4Value), (u4Fld))

#define NR_WM(u4Addr, list) \
    vIO32WriteFldMulti((u4Addr), (list))

#define NR_WMSK(u4Addr, u4Value, u4Msk) \
    vIO32Write4BMsk((u4Addr), (u4Value), (u4Msk))

#define _SWR_4B(addr) u4IO32Read4B(addr)
#define _SWR(addr, fld) IO32ReadFldAlign((addr), (fld))
#define _SWW_4B(addr, val) vIO32Write4B((addr), (val))
#define _SWW(addr,val,fld) vIO32WriteFldAlign((addr), (val), (fld))
#define _SWWM(addr,list) vIO32WriteFldMulti((addr),(list))

#define NR_DEMO_MASK        (4)
#define NR_NM_SAD_HIST      (1)
#define NR_NM_TDF_BASE      (2)
#define PQL_DB_ON   0
enum
{
    NM_LEVEL1_0,
    NM_LEVEL1_1,
    NM_LEVEL1_2,
    NM_LEVEL1_3,
    NM_LEVEL2,
    NM_LEVEL3,
    NM_LEVEL4,
    NM_LEVEL5,
    NM_LEVEL6,
    NM_LEVEL7,
    NM_LEVEL8,
    NM_INVALIDLEVEL
};

typedef enum
{
    E_NR_FB_MANR = 0,
    E_NR_FB_MCNR = 1
} E_NR_FB_TYPE;

typedef enum
{
    MCNR_MODE_OFF = 0, 
    MCNR_MODE_MC  = 1,
    MCNR_MODE_MV  = 2,
    MCNR_MODE_NM  = 3,
    MCNR_MODE_MA  = 4
} E_3DNR_MODE;

typedef enum
{
    NXNR_MODE_OFF = 0,
    NXNR_MODE_ON = 1
} E_2DNR_MODE;

typedef enum
{
    E_BNM_DFT = 0,
    E_BNM_CVBS,
    E_BNM_COMP_I,
    E_BNM_COMP_P,
    E_BNM_HDMI_I,
    E_BNM_HDMI_P
} E_BNM_MODE;

typedef enum
{
    MCNR_IIR_TBL_MA = 0,
    MCNR_IIR_TBL_MC = 1,
    MCNR_IIR_TBL_C  = 2
} E_3DNR_IIR_TBL;

typedef struct
{    
    E_3DNR_MODE eMCNRMode;
    E_2DNR_MODE eNXNRMode;
    UINT8 u1Ver;
    UINT8 u1Timing;
    UINT8 u1ParamUpdate;
    UINT8 u1NoiseMeterEn;
    UINT8 u1Interlace;
    UINT8 u1IsFhdP;
    UINT8 u1MCNROnOff;
    UINT8 u1BNRSNROnOff;
    UINT8 u1SNRMNROnOff;
    UINT8 u1SADWindowH;
    UINT8 u1SADWindowV;
    UINT8 u1NormFact;       /* Normalized factor based on FHD resolution, fractional 2bit*/
    UINT16 u2Width;
    UINT16 u2Height;
    UINT32 u4ConflictCnt;
    UINT32 u4TolBlks;
} NR_PARAM_T;

EXTERN void vDrvNRPQInit(void);
EXTERN void vDrvNRISR(void);
EXTERN void vDrvNRVBlankProc(void);
EXTERN void vDrvNXNRWritePos(BOOL u1IsH, UINT32 u4Pos, UINT8 u1OnOff);
EXTERN void vDrvNXNRWritePosLR(BOOL u1IsR, UINT32 u4Pos, UINT8 u1OnOff);
EXTERN UINT8 u1DrvNXNRReadPos(BOOL u1IsH, UINT32 u4Pos);
EXTERN void vDrvNXNRResetPos(void);
EXTERN void vDrvNXNRResetPosH(void);
EXTERN void vDrvNXNRResetPosV(void);
EXTERN UINT16 u2DrvNXNRGetVBlkLineSum(BOOL fgR, UINT32 u4Pos);
EXTERN UINT16 u2DrvNXNRGetHBlkLineSum(BOOL fgR, UINT32 u4Pos);
EXTERN UINT16 u2DrvNXNRGetVBlkPxCnt(BOOL fgR);
EXTERN UINT16 u2DrvNXNRGetHBlkPxCnt(BOOL fgR);
EXTERN void vDrvMCNRSetDftDcnrAlpha(void);
EXTERN void vDrvMCNRSetWeiTbl(E_3DNR_IIR_TBL eIIRTbl, const UINT8 arTbl[8]);
EXTERN void vDrvMCNRSetTblThd(const UINT8 arTbl[8]);
EXTERN void vDrvNRSetNMDebugInk(UINT32 u4Enable);

E_3DNR_MODE eDrvNRGet3DNRMode(void);
void vDrvNRSet3DNRMode(E_3DNR_MODE e3DMode);
void vDrvNRSet2DNRMode(E_2DNR_MODE e2DMode);
void vDrvNRSetChromaUpSample(BOOL fgOnOff);
void vDrvNRSetQuality(UINT8 u1Interlace, UINT16 u2Width, UINT16 u2Height);
void vDrvNRSetWindow(UINT16 u2Width, UINT16 u2Height);
void vDrvNRSetMoANRParamByTiming(UINT32 u4VdoTiming,E_BNM_MODE eBnmMode);

void vDrvNRSetBNRFWMode(UINT8 u1FWMode);

void vDrvNRSet3DNRParam(void);
void vDrvNRSetSNRParam(void);
void vDrvNRSetMpegNRParam(void);
void vDrvNRSetDotNRParam(void);
void vDrvNRSet2DNRBNROnOff(UINT8 u1OnOff);
void vDrvNRSet2DNRMNROnOff(UINT8 u1OnOff);
void vDrvNRSet2DNRSNROnOff(UINT8 u1OnOff);
void vDrvNRSet2DNRAuto(UINT8 u1OnOff);
void vDrvNRSet3DNROnOff(UINT8 u1OnOff);
void vDrvNRSet2DDotCrawlNROnOff(UINT8 u1OnOff);
void vDrvNRSet3DDotCrawlNROnOff(UINT8 u1OnOff);
void vDrvNRSet3DNRStrength(UINT8 u1Strength);
void vDrvNRSet3DNRMaxNoiseLvl(UINT8 u1MaxLvl);
void vDrvNRSet3DNRAuto(UINT8 u1OnOff);
void vDrvNRSet3DNRAutoStrength(INT8 bStrength);

void vDrvNRSet3DNRChromaPath(UINT8 u1OnOff);
void vDrvNRSetBitRes(UINT8 u18bit);

void vDrvNRSet2DNRDemo(UINT8 bOnOff, UINT8 bRegion, UINT16 wXCenter);
void vDrvNRSet3DNRDemo(UINT8 bOnOff, UINT8 bRegion, UINT16 wXCenter);

void vDrvNRSetForceBypass(UINT8 u1OnOff);
void vDrvNRGetNRStatus(void);
UINT8 u1DrvNRGetBlockMeterSupport(void);
UINT8 u1DrvNRBNMISR(void);

UINT8 u1DrvNRGetNoiseLevel(void);
UINT8 u1DrvNXNRGetBlkConf(void);

void vDrvNRInit(void);
void vDrvNRProc(void);

//=================== To be removed===============================

typedef enum 
{
	NR_CHROMA_LINE_AVERAGE_MODE_OFF,
	NR_CHROMA_LINE_AVERAGE_MODE_DYN,
	NR_CHROMA_LINE_AVERAGE_MODE_121,
}NR_CHROMA_LINE_AVERAGE_MODE;

void vDrvNRSetChromaLineAvgMode(UINT8 bPath, NR_CHROMA_LINE_AVERAGE_MODE bMode);
void vDrvNRSetInk(UINT8 u1Mode, UINT8 u1Type);
void vDrvNRSetChromaLineAvgModeReg(UINT8 bPath, NR_CHROMA_LINE_AVERAGE_MODE bMode);
void vDrvNRChromaLineAvgCfg(UINT8 bPath);
#ifdef CC_MAPLE_CUST_DRV
UINT8 u1DrvNRGetOriNoiseLevel(void);
void vDrvNRGetBNRBlockSize(UINT16* u2BlockH, UINT16* u2BlockV);
#endif
#endif //_DRV_NR_H_

