/*----------------------------------------------------------------------------*
 * No Warranty                                                                *
 * Except as may be otherwise agreed to in writing, no warranties of any      *
 * kind, whether express or implied, are given by MTK with respect to any MTK *
 * Deliverables or any use thereof, and MTK Deliverables are provided on an   *
 * "AS IS" basis.  MTK hereby expressly disclaims all such warranties,        *
 * including any implied warranties of merchantability, non-infringement and  *
 * fitness for a particular purpose and any warranties arising out of course  *
 * of performance, course of dealing or usage of trade.  Parties further      *
 * acknowledge that Company may, either presently and/or in the future,       *
 * instruct MTK to assist it in the development and the implementation, in    *
 * accordance with Company's designs, of certain softwares relating to        *
 * Company's product(s) (the "Services").  Except as may be otherwise agreed  *
 * to in writing, no warranties of any kind, whether express or implied, are  *
 * given by MTK with respect to the Services provided, and the Services are   *
 * provided on an "AS IS" basis.  Company further acknowledges that the       *
 * Services may contain errors, that testing is important and Company is      *
 * solely responsible for fully testing the Services and/or derivatives       *
 * thereof before they are used, sublicensed or distributed.  Should there be *
 * any third party action brought against MTK, arising out of or relating to  *
 * the Services, Company agree to fully indemnify and hold MTK harmless.      *
 * If the parties mutually agree to enter into or continue a business         *
 * relationship or other arrangement, the terms and conditions set forth      *
 * hereunder shall remain effective and, unless explicitly stated otherwise,  *
 * shall prevail in the event of a conflict in the terms in any agreements    *
 * entered into between the parties.                                          *
 *---------------------------------------------------------------------------*/
/******************************************************************************
* [File]			msdc_host_hw.h
* [Version]			v1.0
* [Revision Date]	2011-05-04
* [Author]			Shunli Wang, shunli.wang@mediatek.inc, 82896, 2011-05-04
* [Description]
*	MSDC Driver Header File
* [Copyright]
*	Copyright (C) 2011 MediaTek Incorporation. All Rights Reserved.
******************************************************************************/

#ifndef _MSDC_HOST_HW_H_
#define _MSDC_HOST_HW_H_

//---------------------------------------------------------------------------
// Configurations
//---------------------------------------------------------------------------
#define MSDC_BASE_ADDR            (UINT32) (0xF0012000)
#define MSDC_VECTOR               (UINT32) (28)


//---------------------------------------------------------------------------
// MSDC Register definitions
//---------------------------------------------------------------------------
#define MSDC_CH_NUM               (UINT32) (2)
#if defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)
#define MSDC_CH_OFFSET            (UINT32) (0x00000000)
#else
#define MSDC_CH_OFFSET            (UINT32) (0x0005B000)
#endif

#define MSDC_CFG              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x00)
#define MSDC_IOCON            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x04)
#define MSDC_PS               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x08)
#define MSDC_INT              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x0C)
#define MSDC_INTEN            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x10)
#define MSDC_FIFOCS           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x14)
#define MSDC_TXDATA           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x18)
#define MSDC_RXDATA           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x1C)
#define SDC_CFG               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x30)
#define SDC_CMD               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x34)
#define SDC_ARG               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x38)
#define SDC_STS               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x3C)
#define SDC_RESP0             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x40)
#define SDC_RESP1             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x44)
#define SDC_RESP2             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x48)
#define SDC_RESP3             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x4C)
#define SDC_BLK_NUM           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x50)
#if defined(CC_MT5882) || \
	 defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define SDC_VOL_CHG           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x54)
#endif
#define SDC_CSTS              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x58)
#define SDC_CSTS_EN           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x5C)
#define SDC_DATCRC_STS        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x60)

#if defined(CC_MT5882)
#define SDC_CMD_STS           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x64)
#endif

#define EMMC_CFG0             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x70)
#define EMMC_CFG1             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x74)
#define EMMC_STS              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x78)
#define EMMC_IOCON            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x7C)
#define ACMD_RESP             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x80)
#define ACMD19_TRG            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x84)
#define ACMD19_STS            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x88)

#if defined(CC_MT5882) || \
	 defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define DMA_SA_HIGH4BIT       (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x8C)
#endif

#define DMA_SA                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x90)
#define DMA_CA                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x94)
#define DMA_CTRL              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x98)
#define DMA_CFG               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x9C)
#define DBG_SEL               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA0)
#define DBG_OUT               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA4)
#if defined(CC_MT5399) || defined(CONFIG_ARCH_MT5399)|| \
    defined(CC_MT5890) || defined(CONFIG_ARCH_MT5890)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)|| \
    defined(CC_MT5882) || defined(CONFIG_ARCH_MT5882)|| \
    defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define DMA_LENGTH            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xA8)
#endif
#if defined(CC_MT5399) || defined(CONFIG_ARCH_MT5399)|| \
    defined(CC_MT5890) || defined(CONFIG_ARCH_MT5890)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)|| \
    defined(CC_MT5882) || defined(CONFIG_ARCH_MT5882)|| \
    defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define PATCH_BIT0            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB0)
#define PATCH_BIT1            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB4)
#else
#define PATCH_BIT             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB0)
#endif


#define PATCH_BIT2            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xB8)
#define DAT0_TUNE_CRC         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xC0)
#define DAT1_TUNE_CRC         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xC4)
#define DAT2_TUNE_CRC         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xC8)
#define DAT3_TUNE_CRC         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xCC)
#define CMD_TUNE_CRC          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xD0)
#define SDIO_TUNE_WIND        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xD4)

#if defined(CC_MT5399) || defined(CONFIG_ARCH_MT5399)|| \
    defined(CC_MT5890) || defined(CONFIG_ARCH_MT5890)|| \
    defined(CC_MT5882) || defined(CONFIG_ARCH_MT5882)|| \
    defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)
    //5891 not use these 3 regs, ignore it!!
#define SD30_PAD_CTL0         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE0)
#define SD30_PAD_CTL1         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE4)
#define SD30_PAD_CTL2         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE8)
#else
#define SD20_PAD_CTL0         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE0)
#define SD20_PAD_CTL1         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE4)
#define SD20_PAD_CTL2         (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xE8)
#endif
#if defined(CC_MT5882) || \
	 defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)

	#if defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)      
      #define HW_DBG_SEL            (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x110)
	#endif

#if defined(CC_MT5882)
#define PAD_TUNE				((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xEC) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0)) 
#define DAT_RD_DLY0			((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8))
#define DAT_RD_DLY1			((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF4) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xFC))
#define HW_DBG					((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8) :(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x110))
#define VERSION					((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x100):(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x114))
#define ECO_VER					((IS_IC_5882())? (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x104):(MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x118))
#else
#define PAD_TUNE              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0)
#define DAT_RD_DLY0           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8)
#define DAT_RD_DLY1           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xFC)
#define VERSION               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x114)//MAIN_VERSION
#define ECO_VER               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x118)
#endif

#else
#define GPIO_DBG_OUT          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xEB)//mt5883 don't use
#define PAD_TUNE              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xEC)
#define DAT_RD_DLY0           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF0)
#define DAT_RD_DLY1           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF4)
#define HW_DBG                (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF8)
#define VERSION               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xFC)
#define ECO_VER               (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x104)
#endif

#define PAD_TUNE1             (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0xF4)
#define DAT_RD_DLY2           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x100)
#define DAT_RD_DLY3           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x104)

//Following for MT5891 EMMC Only
#if 1//defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891) || defined(CC_MT5882)
#define EMMC50_PAD_CTL0              (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x180)
#define EMMC50_PAD_DS_CTL0           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x184)
#define EMMC50_PAD_DS_TUNE           (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x188)
#define EMMC50_PAD_CMD_TUNE          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x18C)
#define EMMC50_PAD_DAT01_TUNE        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x190)
#define EMMC50_PAD_DAT23_TUNE        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x194)
#define EMMC50_PAD_DAT45_TUNE        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x198)
#define EMMC50_PAD_DAT67_TUNE        (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x19C)
#define EMMC50_CFG0                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x208)
#define EMMC50_CFG1                  (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x20C)
#define EMMC50_BLOCK_LENGTH          (MSDC_BASE_ADDR + (ch * MSDC_CH_OFFSET) + 0x228)
#endif

/* MSDC_CFG */
#define MSDC_CFG_SD                     (((UINT32)0x01) << 0)
#define MSDC_CFG_CK_EN                  (((UINT32)0x01) << 1)
#define MSDC_CFG_RST                    (((UINT32)0x01) << 2)
#define MSDC_CFG_PIO_MODE               (((UINT32)0x01) << 3)
#define MSDC_CFG_BUS_VOL_START          (((UINT32)0x01) << 5)
#define MSDC_CFG_BUS_VOL_PASS           (((UINT32)0x01) << 6)
#define MSDC_CFG_CARD_CK_STABLE         (((UINT32)0x01) << 7)
#define MSDC_CFG_CK_DIV_SHIFT           (8)

#if defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define MSDC_CFG_CK_MODE_DIVIDER        (((UINT32)0x00) << 20)
#define MSDC_CFG_CK_MODE_DIRECT         (((UINT32)0x01) << 20)
#define MSDC_CFG_CK_MODE_DDR            (((UINT32)0x02) << 20)
#define MSDC_CFG_CK_MODE_HS400          (((UINT32)0x03) << 20)

#define MSDC_CFG_HS400_CK_MODE_SHIFT    (22)
#define MSDC_CFG_HS400_CK_MODE          (((UINT32)0x01) << MSDC_CFG_HS400_CK_MODE_SHIFT)//emmc only
#define MSDC_CFG_START_BIT_SHIFT        (23)
#define MSDC_CFG_START_BIT              (((UINT32)0x03) << MSDC_CFG_START_BIT_SHIFT)//emmc only
#define MSDC_CFG_SCLK_STOP_SEL_SHIFT    (25)
#define MSDC_CFG_SCLK_STOP_SEL          (((UINT32)0x01) << MSDC_CFG_SCLK_STOP_SEL_SHIFT)

#else

#if defined(CC_MT5882)
#define MSDC_CFG_CK_MODE_SHFIT		((IS_IC_5882())? (16) : (20))
#define MSDC_CFG_CK_MODE_DIVIDER        ((IS_IC_5882())? (((UINT32)0x00) << 16) : (((UINT32)0x00) << 20))
#define MSDC_CFG_CK_MODE_DIRECT         ((IS_IC_5882())? (((UINT32)0x01) << 16) : (((UINT32)0x01) << 20))
#define MSDC_CFG_CK_MODE_DDR            ((IS_IC_5882())? (((UINT32)0x02) << 16) : (((UINT32)0x02) << 20))
#define MSDC_CFG_CK_MODE_HS400          (((UINT32)0x03) << 20)
#define MSDC_CFG_SCLK_STOP_SEL_SHIFT    (25)
#define MSDC_CFG_SCLK_STOP_SEL          (((UINT32)0x01) << MSDC_CFG_SCLK_STOP_SEL_SHIFT)
#define MSDC_CFG_BW_SEL			(((UINT32)0x01) << 29)

#else
#define MSDC_CFG_CK_MODE_DIVIDER        (((UINT32)0x00) << 16)
#define MSDC_CFG_CK_MODE_DIRECT         (((UINT32)0x01) << 16)
#define MSDC_CFG_CK_MODE_DDR            (((UINT32)0x02) << 16)
#endif

#endif

/* MSDC_IOCON */
#define MSDC_IOCON_RISC_SIZE_MASK       (((UINT32)0x03) << 24)
#define MSDC_IOCON_RISC_SIZE_BYTE       (((UINT32)0x00) << 24)
#define MSDC_IOCON_RISC_SIZE_WORD       (((UINT32)0x01) << 24)
#define MSDC_IOCON_RISC_SIZE_DWRD       (((UINT32)0x02) << 24)
#define MSDC_IOCON_R_SMPL_SHIFT         (1)    
#define MSDC_IOCON_R_SMPL               (((UINT32)0x01) << MSDC_IOCON_R_SMPL_SHIFT)
#define MSDC_IOCON_D_SMPL_SHIFT         (2) 
#define MSDC_IOCON_D_SMPL               (((UINT32)0x01) << MSDC_IOCON_D_SMPL_SHIFT)
#define MSDC_IOCON_D_DLYLINE_SEL_SHIFT  (3)
#define MSDC_IOCON_D_DLYLINE_SEL        (((UINT32)0x01) << MSDC_IOCON_D_DLYLINE_SEL_SHIFT)
#define MSDC_IOCON_R_D_SMPL_SEL_SHIFT   (5)
#define MSDC_IOCON_R_D_SMPL_SEL         (((UINT32)0x01) << MSDC_IOCON_R_D_SMPL_SEL_SHIFT)
#define MSDC_IOCON_W_D_SMPL_SHIFT       (8)
#define MSDC_IOCON_W_D_SMPL_SEL         (((UINT32)0x01) << MSDC_IOCON_W_D_SMPL_SHIFT)
#define MSDC_IOCON_W_D_SMPL_SEL_SHIFT   (9)
#define MSDC_IOCON_W_D_SMPL_SEL_SEL     (((UINT32)0x01) << MSDC_IOCON_W_D_SMPL_SEL_SHIFT)
#define MSDC_IOCON_R_D0_SMPL_SHIFT      (16)
#define MSDC_IOCON_R_D0_SMPL            (((UINT32)0x01) << MSDC_IOCON_R_D0_SMPL_SHIFT)


#define MSDC_DAT_RD_DLY0_SHIFT			(24)
#define MSDC_DAT_RD_DLY0					(((UINT32)0x1F) << MSDC_DAT_RD_DLY0_SHIFT)
#define MSDC_IOCON_W_D0SPL_SHIFT        (10)     
#define MSDC_IOCON_W_D0SPL              (((UINT32)0x01) << MSDC_IOCON_W_D0SPL_SHIFT)


/* MSDC_INT */
#define INT_MMC_IRQ                     (((UINT32)0x01) << 0)           
#define INT_MSDC_CDSC                   (((UINT32)0x01) << 1) 
#define INT_SD_AUTOCMD_RDY              (((UINT32)0x01) << 3) 
#define INT_SD_AUTOCMD_TO               (((UINT32)0x01) << 4) 
#define INT_SD_AUTOCMD_RESP_CRCERR      (((UINT32)0x01) << 5) 
#define INT_DMA_Q_EMPTY                 (((UINT32)0x01) << 6) 
#define INT_SD_SDIOIRQ                  (((UINT32)0x01) << 7) 
#define INT_SD_CMDRDY                   (((UINT32)0x01) << 8) 
#define INT_SD_CMDTO                    (((UINT32)0x01) << 9) 
#define INT_SD_RESP_CRCERR              (((UINT32)0x01) << 10)
#define INT_SD_CSTA                     (((UINT32)0x01) << 11)
#define INT_SD_XFER_COMPLETE            (((UINT32)0x01) << 12)
#define INT_DMA_XFER_DONE               (((UINT32)0x01) << 13)
#define INT_SD_DATTO                    (((UINT32)0x01) << 14)
#define INT_SD_DATA_CRCERR              (((UINT32)0x01) << 15)
#define INT_AUTOCMD19_DONE              (((UINT32)0x01) << 16)
#define INT_BD_CS_ERR                   (((UINT32)0x01) << 17)
#define INT_GPD_CS_CRCERR               (((UINT32)0x01) << 18)
#define INT_DMA_PROTECT                 (((UINT32)0x01) << 19)
#if 1//defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define INT_GEAR_OUT_BOUND                (((UINT32)0x01) << 20)//sd only
#define INT_AUTOCMD53_DONE                (((UINT32)0x01) << 21)//sd only
#define INT_AUTOCMD53_FAIL                (((UINT32)0x01) << 22)//sd only
#define INT_AXI_RESP_ERR                (((UINT32)0x01) << 23)//emmc only
#endif

#define INT_MS_RDY                      (((UINT32)0x01) << 24)
#define INT_MS_SIF                      (((UINT32)0x01) << 25)
#define INT_MS_TOER                     (((UINT32)0x01) << 26)
#define INT_MS_CRCERR                   (((UINT32)0x01) << 27)
#define INT_MS_CED                      (((UINT32)0x01) << 28)
#define INT_MS_ERR                      (((UINT32)0x01) << 29)
#define INT_MS_BREQ                     (((UINT32)0x01) << 30)
#define INT_CMDNK                       (((UINT32)0x01) << 31)

/* SDC_CFG */
#define SDC_CFG_BW_SHIFT                (16)         
#define SDC_CFG_BW_MASK                 (((UINT32)0x03) << 16) 
#define SDC_CFG_SDIO                    (((UINT32)0x01) << 19) 
#define SDC_CFG_INTAT_BLK_GAP           (((UINT32)0x01) << 21) 
#define SDC_CFG_DTOC_SHIFT              (24)         

/* SDC_STS */                                        
#define SDC_STS_SDCBUSY                 (((UINT32)0x01) << 0x0)  
#define SDC_STS_CMDBUSY                 (((UINT32)0x01) << 0x1)  
#if 1//defined(CC_MT5882) || defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define SDC_CMD_WR_BUSY                 (((UINT32)0x01) << 16)  
#endif
                                 
/* SDC_CMD */                                        
#define SDC_CMD_BREAK                   (((UINT32)0x01) << 6)  
#if 1//defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define SDC_CMD_ACMD53_EN               (((UINT32)0x01) << 31) //sd only 
#endif

/* SDC_DCRC_STS mask */
#define SDC_DCRC_STS_NEG        (0xff << 8)     /* RO */
#define SDC_DCRC_STS_POS        (0xff << 0)     /* RO */

/*SDC_CMD_STS*/
#if defined(CC_MT5882)
#define SDC_CMD_STS_RSP_CRC			(0x7F << 0)		/* RU */
#define SDC_CMD_STS_RSP_INDEX		(0x3F << 7)		/* RU */
#define SDC_CMD_STS_RSP_ENDBIT		(((UINT32)0x1)  << 13)		/* RU */
#define SDC_CMD_STS_INDEX_CHECK		(((UINT32)0x1)  << 14)		/* RW */
#define SDC_CMD_STS_ENDBIT_CHECK	(((UINT32)0x1)  << 15)		/* RW */
#endif

/* Response Type */                                                     
#define SDC_CMD_RSPTYPE_NO              (((UINT32)0x00) << 7)  
#define SDC_CMD_RSPTYPE_R1              (((UINT32)0x01) << 7)  
#define SDC_CMD_RSPTYPE_R2              (((UINT32)0x02) << 7)  
#define SDC_CMD_RSPTYPE_R3              (((UINT32)0x03) << 7)  
#define SDC_CMD_RSPTYPE_R4              (((UINT32)0x04) << 7)  
#define SDC_CMD_RSPTYPE_R5              (((UINT32)0x01) << 7)  
#define SDC_CMD_RSPTYPE_R6              (((UINT32)0x01) << 7)  
#define SDC_CMD_RSPTYPE_R7              (((UINT32)0x01) << 7)  
#define SDC_CMD_RSPTYPE_R1B             (((UINT32)0x07) << 7)  

/* Data Type */                                                     
#define DTYPE_NONE                      (((UINT32)0x00) << 11) 
#define DTYPE_SINGLE_BLK                (((UINT32)0x01) << 11) 
#define DTYPE_MULTI_BLK                 (((UINT32)0x02) << 11) 
#define DTYPE_STREAM                    (((UINT32)0x03) << 11) 
                                                     
#define SDC_CMD_READ                    (((UINT32)0x00) << 13) 
#define SDC_CMD_WRITE                   (((UINT32)0x01) << 13) 
                                                     
#define SDC_CMD_STOP                    (((UINT32)0x01) << 14) 
                                                     
#define SDC_CMD_GO_IRQ                  (((UINT32)0x01) << 15) 
                                                     
#define SDC_CMD_LEN_SHIFT               (16)         
                                                     
#define SDC_CMD_AUTO_CMD_NONE           (((UINT32)0x0) << 28)  
#define SDC_CMD_AUTO_CMD12              (((UINT32)0x1) << 28)  
#define SDC_CMD_AUTO_CMD23              (((UINT32)0x2) << 28)  
#define SDC_CMD_AUTO_CMD19              (((UINT32)0x3) << 28)  
                                                     
#define SDC_CMD_VOL_SWITCH              (((UINT32)0x1) << 30)  
                                                     
/* MSDC_FIFOCS */                                    
#define MSDC_FIFOCS_FIFOCLR             (((UINT32)0x1) << 31)  
#define MSDC_FIFO_LEN                   (128)        
#define MSDC_FIFOCS_TXFIFOCNT_SHIFT     (16)         
#define MSDC_FIFOCS_TXFIFOCNT_MASK      (0x00FF0000) 
#define MSDC_FIFOCS_RXFIFOCNT_SHIFT     (0)          
#define MSDC_FIFOCS_RXFIFOCNT_MASK      (0x000000FF)

/* SDC_DATCRC_STS */
#define SDC_DATCRC_STS_POS              (((unsigned int)0xFF) << 0)    
#define SDC_DATCRC_STS_NEG              (((unsigned int)0x0F) << 8) 

/* DMA_CTRL */
#define DMA_CTRL_BST_SHIFT              (12)
#define DMA_CTRL_BST_8                  (3 << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_BST_16                 (4 << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_BST_32                 (5 << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_BST_64                 (6 << DMA_CTRL_BST_SHIFT)
#define DMA_CTRL_START                  (((UINT32)0x01) << 0)
#define DMA_CTRL_STOP                   (((UINT32)0x01) << 1)
#define DMA_CTRL_RESUME                 (((UINT32)0x01) << 2)
#define DMA_CTRL_LAST_BUF               (((UINT32)0x01) << 10)
#define DMA_CTRL_XFER_SIZE_SHIFT        (16)
#define DMA_CTRL_DESC_MODE              (((UINT32)0x01) << 8)
#if 1//defined(CC_MT5882) || defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define DMA_CTRL_SPLIT_1K               (((UINT32)0x01) << 11)
#define DMA_CTRL_ALIGN                  (((UINT32)0x01) << 9)
#define DMA_CTRL_AHB_READYM             (((UINT32)0x01) << 3)
#endif

/* DMA_CFG */
#define DMA_CFG_DMA_STATUS              (((UINT32)0x01) << 0)
#define DMA_CFG_CHKSUM                  (((UINT32)0x01) << 1)
#define DMA_CFG_BD_CS_ERR               (((UINT32)0x01) << 4)
#define DMA_CFG_GPD_CS_ERR              (((UINT32)0x01) << 5)
#if 1//defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
#define DMA_CFG_OUTBOUND_STOP_DMA       (((UINT32)0x01) << 17)//sd only
#define DMA_CFG_LOCK_DISABLE            (((UINT32)0x01) << 2)//emmc only
#endif

/* PAD_TUNE */
#define PAD_CLK_TXDLY_SHIFT        		(27)
#define PAD_CLK_TXDLY              		(((unsigned int)0x1F) << PAD_CLK_TXDLY_SHIFT)
#define MSDC_DAT_RDDLY0_D0_SHIFT          (24)
#define MSDC_DAT_RDDLY0_D0              (((unsigned int)0x1F) << MSDC_DAT_RDDLY0_D0_SHIFT)

#define PAD_CMD_RESP_RXDLY_SHIFT        (22)
#define PAD_CMD_RESP_RXDLY              (((unsigned int)0x1F) << PAD_CMD_RESP_RXDLY_SHIFT)

#define PAD_CMD_RD_RX_DLY_SEL_SHIFT     (21)
#define PAD_CMD_RD_RX_DLY_SEL           (((unsigned int)0x1) << PAD_CMD_RD_RX_DLY_SEL_SHIFT)

#define PAD_CMD_RXDLY_SHIFT             (16)
#define PAD_CMD_RXDLY                   (((unsigned int)0x1F) << PAD_CMD_RXDLY_SHIFT)
#define PAD_DAT_RD_RXDLY_SHIFT          (8)
#define PAD_DAT_RD_RXDLY                (((unsigned int)0x1F) << PAD_DAT_RD_RXDLY_SHIFT)
#define PAD_DAT_WR_RXDLY_SHIFT          (0)
#define PAD_DAT_WR_RXDLY                (((unsigned int)0x1F) << PAD_DAT_WR_RXDLY_SHIFT)


#if 1//defined(CC_MT5882) || defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
/*PAD_TUNE0*/
#define PAD_CMD_RD_RXDLY_SEL_SHIFT				(21)
#define PAD_CMD_RD_RXDLY_SEL						(((UINT32)0x1) << PAD_CMD_RD_RXDLY_SEL_SHIFT)
#define PAD_RXDLY_SEL_SHIFT						(15)
#define PAD_RXDLY_SEL								(((UINT32)0x1) << PAD_RXDLY_SEL_SHIFT)
#define PAD_DAT_RD_RXDLY_SEL_SHIFT				(13)
#define PAD_DAT_RD_RXDLY_SEL						(((UINT32)0x1) << PAD_DAT_RD_RXDLY_SEL_SHIFT)
#define DELAY_EN_SHIFT								(7)
#define DELAY_EN									(((UINT32)0x1) << DELAY_EN_SHIFT)

/*PAD_TUNE1*/
#define PAD_TUNE1_CMD_RD_RX_DLY2_SE_SHIFT	(21)
#define PAD_TUNE1_CMD_RD_RX_DLY2_SE		(0x1 << MSDC_PAD_TUNE1_CMD_RD_RX_DLY2_SE_SHIFT)
#define PAD_TUNE1_CMD_RXDLY2_SHIFT			(16)
#define PAD_TUNE1_CMD_RXDLY2					(0x1F << MSDC_PAD_TUNE1_CMD_RXDLY2_SHIFT)
#define PAD_TUNE1_DAT_RD_RXDLY2_SEL_SHIFT	(13)
#define PAD_TUNE1_DAT_RD_RXDLY2_SEL		(0x1  << MSDC_PAD_TUNE1_DAT_RD_RXDLY2_SEL_SHIFT)
#define PAD_TUNE1_DAT_RD_RXDLY2_SHIFT		(8)
#define PAD_TUNE1_DAT_RD_RXDLY2				(0x1F << MSDC_PAD_TUNE1_DAT_RD_RXDLY2_SHIFT)
#define PAD_CMD_RD_RX_DLY2_SE_SHIFTL        	(21)
#define PAD_CMD_RXDLY2_SHIFT        	        (16)
#define PAD_DAT_RD_RXDLY2_SEL_SHIFT        	    (13)
#define PAD_DAT_RD_RXDLY2_SHIFT        	        (8)
#define PAD_TUNE1_DATRRDLY2     (0x1F <<  8)     /* RW */
#define PAD_TUNE1_DATRRDLY2SEL  (0x1  << 13)     /* RW */
#define PAD_TUNE1_CMDRDLY2      (0x1F << 16)     /* RW */
#define PAD_TUNE1_CMDRRDLY2SEL  (0x1  << 21)     /* RW */

/* EMMC50_PAD_DS_TUNE mask */
#define MSDC_EMMC50_PAD_DS_TUNE_DLYSEL  (0x1 << 0)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY2SEL (0x1 << 1)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY1    (0x1f << 2)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY2    (0x1f << 7)
#define MSDC_EMMC50_PAD_DS_TUNE_DLY3    (0x1F << 12)

#endif
/* EMMC50_PAD_CMD_TUNE mask */
#define MSDC_EMMC50_PAD_CMD_TUNE_DLY3SEL (0x1 << 0)
#define MSDC_EMMC50_PAD_CMD_TUNE_RXDLY3  (0x1f << 1)
#define MSDC_EMMC50_PAD_CMD_TUNE_TXDLY   (0x1f << 6)

#if 1 //defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)
/* DAT_RD_DLY 0/1/2/3 mask */
#define MSDC_DAT_RDDLY0_D0_LINE1_SHIFT          (24)
#define MSDC_DAT_RDDLY0_D0_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY0_D0_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D1_LINE1_SHIFT         (16)
#define MSDC_DAT_RDDLY0_D1_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY0_D1_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D2_LINE1_SHIFT         (8)
#define MSDC_DAT_RDDLY0_D2_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY0_D2_LINE1_SHIFT)
#define MSDC_DAT_RDDLY0_D3_LINE1_SHIFT         (0)
#define MSDC_DAT_RDDLY0_D3_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY0_D3_LINE1_SHIFT)

#define MSDC_DAT_RDDLY1_D4_LINE1_SHIFT          (24)
#define MSDC_DAT_RDDLY1_D4_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY1_D4_LINE1_SHIFT)
#define MSDC_DAT_RDDLY1_D5_LINE1_SHIFT         (16)
#define MSDC_DAT_RDDLY1_D5_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY1_D5_LINE1_SHIFT)
#define MSDC_DAT_RDDLY1_D6_LINE1_SHIFT         (8)
#define MSDC_DAT_RDDLY1_D6_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY1_D6_LINE1_SHIFT)
#define MSDC_DAT_RDDLY1_D7_LINE1_SHIFT         (0)
#define MSDC_DAT_RDDLY1_D7_LINE1              (((unsigned int)0x1F) << MSDC_DAT_RDDLY1_D7_LINE1_SHIFT)

#define MSDC_DAT_RDDLY2_D0_LINE2_SHIFT          (24)
#define MSDC_DAT_RDDLY2_D0_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY2_D0_LINE2_SHIFT)
#define MSDC_DAT_RDDLY2_D1_LINE2_SHIFT         (16)
#define MSDC_DAT_RDDLY2_D1_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY2_D1_LINE2_SHIFT)
#define MSDC_DAT_RDDLY2_D2_LINE2_SHIFT         (8)
#define MSDC_DAT_RDDLY2_D2_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY2_D2_LINE2_SHIFT)
#define MSDC_DAT_RDDLY2_D3_LINE2_SHIFT         (0)
#define MSDC_DAT_RDDLY2_D3_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY2_D3_LINE2_SHIFT)

#define MSDC_DAT_RDDLY3_D4_LINE2_SHIFT          (24)
#define MSDC_DAT_RDDLY3_D4_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY3_D4_LINE2_SHIFT)
#define MSDC_DAT_RDDLY3_D5_LINE2_SHIFT         (16)
#define MSDC_DAT_RDDLY3_D5_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY3_D5_LINE2_SHIFT)
#define MSDC_DAT_RDDLY3_D6_LINE2_SHIFT         (8)
#define MSDC_DAT_RDDLY3_D6_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY3_D6_LINE2_SHIFT)
#define MSDC_DAT_RDDLY3_D7_LINE2_SHIFT         (0)
#define MSDC_DAT_RDDLY3_D7_LINE2              (((unsigned int)0x1F) << MSDC_DAT_RDDLY3_D7_LINE2_SHIFT)

/* EMMC50_PAD_DAT01_TUNE mask */
#define MSDC_EMMC50_PAD_DAT0_RXDLY3SEL   (0x1 << 0)
#define MSDC_EMMC50_PAD_DAT0_RXDLY3      (0x1f << 1)
#define MSDC_EMMC50_PAD_DAT0_TXDLY       (0x1f << 6)
#define MSDC_EMMC50_PAD_DAT1_RXDLY3SEL   (0x1 << 16)
#define MSDC_EMMC50_PAD_DAT1_RXDLY3      (0x1f << 17)
#define MSDC_EMMC50_PAD_DAT1_TXDLY       (0x1f << 22)

/* EMMC50_PAD_DAT23_TUNE mask */
#define MSDC_EMMC50_PAD_DAT2_RXDLY3SEL   (0x1 << 0)
#define MSDC_EMMC50_PAD_DAT2_RXDLY3      (0x1f << 1)
#define MSDC_EMMC50_PAD_DAT2_TXDLY       (0x1f << 6)
#define MSDC_EMMC50_PAD_DAT3_RXDLY3SEL   (0x1 << 16)
#define MSDC_EMMC50_PAD_DAT3_RXDLY3      (0x1f << 17)
#define MSDC_EMMC50_PAD_DAT3_TXDLY       (0x1f << 22)

/* EMMC50_PAD_DAT45_TUNE mask */
#define MSDC_EMMC50_PAD_DAT4_RXDLY3SEL   (0x1 << 0)
#define MSDC_EMMC50_PAD_DAT4_RXDLY3      (0x1f << 1)
#define MSDC_EMMC50_PAD_DAT4_TXDLY       (0x1f << 6)
#define MSDC_EMMC50_PAD_DAT5_RXDLY3SEL   (0x1 << 16)
#define MSDC_EMMC50_PAD_DAT5_RXDLY3      (0x1f << 17)
#define MSDC_EMMC50_PAD_DAT5_TXDLY       (0x1f << 22)

/* EMMC50_PAD_DAT67_TUNE mask */
#define MSDC_EMMC50_PAD_DAT6_RXDLY3SEL   (0x1 << 0)
#define MSDC_EMMC50_PAD_DAT6_RXDLY3      (0x1f << 1)
#define MSDC_EMMC50_PAD_DAT6_TXDLY       (0x1f << 6)
#define MSDC_EMMC50_PAD_DAT7_RXDLY3SEL   (0x1 << 16)
#define MSDC_EMMC50_PAD_DAT7_RXDLY3      (0x1f << 17)
#define MSDC_EMMC50_PAD_DAT7_TXDLY       (0x1f << 22)


/*THE Tuning for emmc5.0*/
#endif

#define MSDC_PB0_INT_DAT_LATCH_CK_SEL (0x7 << 7)

/* EMMC_CFG0 */
#define BTSUP                           (((UINT32)0x01) << 15)
#define BTWDLY_0x32                     (((UINT32)0x00) << 12)
#define BTWDLY_1x32                     (((UINT32)0x01) << 12)
#define BTWDLY_2x32                     (((UINT32)0x02) << 12)
#define BTWDLY_7x32                     (((UINT32)0x07) << 12)
#define BTACHKDIS                       (((UINT32)0x01) << 3)
#define BTMOD_0                         (((UINT32)0x00) << 2)
#define BTMOD_1                         (((UINT32)0x01) << 2)
#define BTSTOP                          (((UINT32)0x01) << 1)
#define BTSTART                         (((UINT32)0x01) << 0)

/* EMMC_CFG1 */
#define BTATOC_SHIFT                    (20)
#define BTDTOC_SHIFT                    (0)

/* EMMC_STS */
#define BTDRCV                          (((UINT32)0x01) << 6)
#define BTARCV                          (((UINT32)0x01) << 5)
#define BTSTS                           (((UINT32)0x01) << 4)
#define BTATO                           (((UINT32)0x01) << 3)
#define BTDTO                           (((UINT32)0x01) << 2)
#define BTAERR                          (((UINT32)0x01) << 1)
#define BTDERR                          (((UINT32)0x01) << 0)

#if 1
/* PATCH_BIT0 */
#define CKGEN_MSDC_DLY_SEL_SHIFT        (10)
#define CKGEN_MSDC_DLY_SEL              (((UINT32)0x1F) << CKGEN_MSDC_DLY_SEL_SHIFT)
#define INT_DAT_LATCH_CK_SEL_SHIFT      (7)
#define INT_DAT_LATCH_CK_SEL            (((UINT32)0x7)  << INT_DAT_LATCH_CK_SEL_SHIFT)
#if defined(CC_MT5882)
#define RD_RAT_SEL_SHIFT					  (3)
#define MSDC_BIT0_RD_RAT_SEL				  (0x1  <<  RD_RAT_SEL_SHIFT)
#define DESC_UP_SEL_SHIFT					  (6)
#define MSDC_BIT0_DESC_UP_SEL			  (0x1  <<  DESC_UP_SEL_SHIFT) 
#define SDC_CFG_WDOD_SHIFT				  (22)
#define MSDC_BIT0_SDC_CFG_WDOD			  (0XF  << SDC_CFG_WDOD_SHIFT)
#endif
/* PATCH_BIT1 */
#define WRDAT_CRCS_TA_CNTR_SHIFT        (0)
#define WRDAT_CRCS_TA_CNTR              (((UINT32)0x7) << WRDAT_CRCS_TA_CNTR_SHIFT)
#define CMD_RSP_TA_CNTR_SHIFT           (3)
#define CMD_RSP_TA_CNTR                 (((UINT32)0x7) << CMD_RSP_TA_CNTR_SHIFT)

//really exist??
#define MSDC_PB1_GET_BUSY_MA     (0x1 << 6)
#define MSDC_PB1_GET_CRC_MA      (0x1 << 7)

#if defined(CC_MT5882)
#define MSDC_BIT1_DCM_EN				(0x1  << 21)
#define MSDC_BIT1_SINGAL_BURST		(0x1  << 16)
#define MSDC_BIT1_RESET_GDMA			(0x1  << 15)
#define MSDC_BIT1_CRC_MARGIN			(0x1  <<  7)
#define MSDC_BIT1_BUSY_MARGIN		(0x1  <<  6)
#define MSDC_PB1_GET_BUSY_MA     	(0x1  <<  6)
#define MSDC_PB1_GET_CRC_MA      	(0x1  <<  7)
#endif

/* MSDC_PATCH_BIT2 mask */
#define MSDC_BIT2_ENHANCE_WAIT_GPD	(0x1  <<  0)
#define MSDC_BIT2_SUPPORT_64G		(0x1  <<  1)
#define MSDC_BIT2_RESP_WAIT_CNT		(0x3  <<  2)
#define MSDC_BIT2_CFG_RDAT_CNT		(0xF  <<  4)
#define MSDC_BIT2_CFG_RDAT			(0x1  <<  9)
#define MSDC_BIT2_INTC_RESP_SEL		(0x1  << 11)
#define MSDC_BIT2_CFG_RESP_CNT		(0x7  << 12)
#define MSDC_BIT2_CFG_RESP			(0x1  << 15)
#define MSDC_BIT2_RESP_LATCH_ENSEL	(0x7  << 16)
#define MSDC_BIT2_DDR5O_SEL			(0x1  << 19)
#define MSDC_BIT2_POP_EN_CNT			(0xF  << 20)
#define MSDC_BIT2_CFG_CRCSTS_SEL	(0x1  << 24)
#define MSDC_BIT2_CFG_CRCSTS_EDGE	(0x1  << 25)
#define MSDC_BIT2_CFG_CRCSTS_CNT	(0x3  << 26)
#define MSDC_BIT2_CFG_CRCSTS			(0x1  << 28)
#define MSDC_BIT2_CRCSTS_LATCH_SEL	(0x7  << 29)

#else
/* PATCH_BIT0 */
#define R1B_DELAY_CYCLE                 (((UINT32)0x0F) << 18)
#endif

#if defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891) || defined(CC_MT5882)
#define SDC_CFG_WDOD_SHIFT        (22)
#define SDC_CFG_WDOD              (((UINT32)0xF) << SDC_CFG_WDOD_SHIFT)

#define DESC_UP_SEL_SHIFT         (6)
#define DESC_UP_SEL                (((UINT32)0x1) << DESC_UP_SEL_SHIFT)

//SD ONLY
#define RD_DAT_SEL_SHIFT          (3)
#define RD_DAT_SEL                (((UINT32)0x1) << RD_DAT_SEL_SHIFT)

#define MASK_ACMD53_CRC_ERR_INTR_SHIFT          (4)
#define MASK_ACMD53_CRC_ERR_INTR                (((UINT32)0x1) << MASK_ACMD53_CRC_ERR_INTR_SHIFT)

#define ACMD53_FAIL_ONE_SHOT_SHIFT          (5)
#define ACMD53_FAIL_ONE_SHOT                (((UINT32)0x1) << ACMD53_FAIL_ONE_SHOT_SHIFT)

#endif

/* PATCH_BIT1 */
#if 1 //defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)|| defined(CC_MT5882)
#define AXI_WRAP_CKEN_SHIFT          (22)
#define DCM_EN_SHIFT                 (21)
#define DCM_DIV_SEL1_SHIFT           (20)
#define DCM_DIV_SEL2_SHIFT           (18)
#define FORCE_STOP_GDMA_SHIFT        (17)
#define ENABLE_SINGLE_BURST_SHIFT    (16)
#define RESET_DGMA_SHIFT             (15)
#define GET_CRC_MARGIN_SHIFT         (7)
#define GET_BUSY_MARGIN_SHIFT        (6)

/* PATCH_BIT2 */
#define CRCSTS_LATCH_EN_SEL_SHIFT    (29)
#define CFG_CRCSTS_SHIFT             (28)
#define CFG_CRCSTS                   (((UINT32)0x1) << CFG_CRCSTS_SHIFT)
#define CFG_RDAT_SHIFT             (9)
#define CFG_RDAT                   (((UINT32)0x1) << CFG_RDAT_SHIFT)
#define RESP_WAIT_CNT              (((UINT32)0x3) << 2)


#define CFG_CRCSTC_CNT_SHIFT          (26)
#define CFG_CRCSTS_EDGE_SHIFT         (25)
#define CFG_CRCSTS_EDGE               (((UINT32)0x1) << CFG_CRCSTS_EDGE_SHIFT)

#define CFG_CRCSTS_SEL_SHIFT          (24)
#define POP_EN_CNT_SHIFT              (20)
#define RESP_LATCH_CN_SEL_SHIFT       (16)

#define CFG_RESP_SHIFT                 (15)
#define CFG_RESP                       (((UINT32)0x1) << CFG_RESP_SHIFT)



#define CFG_RESP_CNT_SHIFT             (12)
#define INTC_RESP_SEL_SHIFT            (11)

#define CFG_RDAT_SHIFT                 (9)
#define CFG_RDAT_CNT_SHIFT             (4)
#define RESP_WAIT_CNT_SHIFT            (2)

#define SUPPORT_64G_SHIFT              (1)
#define ENHANCE_WAIT_GPD_SHIFT         (0)

/*EMMC50_CFG0*/
#define CRC_STS_EDGE_SHIFT          (3)
#define CRC_STS_EDGE                (((UINT32)0x1) << CRC_STS_EDGE_SHIFT)

#define CRC_STS_SEL_SHIFT          (4)
#define CRC_STS_SEL                (((UINT32)0x1) << CRC_STS_SEL_SHIFT)
#define CFG_CMD_RESP_SEL           ((UINT32)0x1 << 9)

#define PAD_DAT_RX_DLY3_MUX_SEL_SHIFT   (16)
#define PAD_DAT_RX_DLY3_MUX_SEL         (((UINT32)0x1) << PAD_DAT_RX_DLY3_MUX_SEL_SHIFT)

#define PAD_DAT_RX_DLY3_SHIFT   (17)
#define PAD_DAT_RX_DLY3         (((UINT32)0x1F) << PAD_DAT_RX_DLY3_SHIFT)

#endif
/* 8bit Mode */
#define SUPPORT_8_BIT					(1)

/* Host OCR */
#define BUSY_MASK               ((UINT32)(0x1<<31))
#define HCS_MASK                ((UINT32)(0x1<<30))
#define CCS_MASK                ((UINT32)(0x1<<30))
#define XPC_MASK                ((UINT32)(0x1<<28))
#define S18R_MASK               ((UINT32)(0x1<<24))
#define S18A_MASK               ((UINT32)(0x1<<24))
#define OCR_MASK                ((UINT32)(0xFF8000))
#if defined(CC_MT5399) || defined(CONFIG_ARCH_MT5399)|| \
    defined(CC_MT5890) || defined(CONFIG_ARCH_MT5890)|| \
    defined(CC_MT5891) || defined(CONFIG_ARCH_MT5891)|| \
    defined(CC_MT5882) || defined(CONFIG_ARCH_MT5882)|| \
    defined(CC_MT5883) || defined(CONFIG_ARCH_MT5883)
#define HOST_OCR_ATTRIBUTE      (HCS_MASK | XPC_MASK | S18R_MASK)
#define HOST_OCR_VOLTAGE        (OCR_MASK)
#else
#define HOST_OCR_ATTRIBUTE      (HCS_MASK)
#define HOST_OCR_VOLTAGE        (OCR_MASK)
#endif
#define HOST_OCR                (HOST_OCR_ATTRIBUTE | HOST_OCR_VOLTAGE)


/* Transaction Type */
#define NULL_DATA_MODE          (0)
#define PIO_DATA_MODE           (1)
#define BASIC_DMA_DATA_MODE     (2)
#define DESC_DMA_DATA_MODE      (3)
#define ENHANCED_DMA_DATA_MODE  (4)

/* DMA Burst */
#define DMA_BST_8               (3)
#define DMA_BST_16              (4)
#define DMA_BST_32              (5)
#define DMA_BST_64              (6)

/* DMA Data Structure */
#define BASIC_DMA_MAX_LEN       (0xFFFF)
#define GPD_MAX_LEN             (0xFFFF)
#define BD_MAX_LEN              (0xFFFF)
#define MAX_BD_NUM              (1024)
#define MAX_BD_PER_GPD          (MAX_BD_NUM)
#define MAX_GPD_PER_QUEUE       (MAX_BD_NUM)

struct __msdc_gpd_s__
{
	UINT32 hwo	:1;
	UINT32 bdp	:1;
	UINT32 resv0	:6;
	UINT32 chksum	:8;
	UINT32 intr	:1;
	UINT32 resv1	:15;

	void *pNext;
	void *pBuff;

	UINT32 buffLen:16;
	UINT32 extLen	:8;
	UINT32 resv3	:8;

	// Enhanced DMA fields
	UINT32 arg;
	UINT32 blkNum;
	UINT32 cmd;
};
typedef struct __msdc_gpd_s__ msdc_gpd_t;

struct __msdc_bd_s__
{	
	UINT32 eol	:1;
	UINT32 resv0	:7;
	UINT32 chksum	:8;
	UINT32 resv1	:1;
	UINT32 blkPad	:1;
	UINT32 dwPad	:1;			// DWORD is 4 bytes
	UINT32 resv2	:13;

	void *pNext;
	void *pBuff;

	UINT32 buffLen:16;
	UINT32 resv3	:16;
};
typedef struct __msdc_bd_s__ msdc_bd_t;

#endif // #ifndef _MSDC_HOST_HW_H_
