/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef _HW_PREDOWN_H_
#define _HW_PREDOWN_H_

#include "x_hal_5381.h"

#define IO_PRE_DS_BASE  (IO_VIRT+ 0x23000)


//Page PREDSMAIN
#define PRE_DS_MAIN_00 (IO_PRE_DS_BASE + 0x150)
    #define PRE_DS_MAIN_00_PRE_DSCALE_H_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_00_PRE_DSCALER_V_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_01 (IO_PRE_DS_BASE + 0x154)
    #define PRE_DS_MAIN_01_PRE_DSCALE_H_INIT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_01_PRE_DSCALE_V_INIT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_02 (IO_PRE_DS_BASE + 0x158)
    #define PRE_DS_MAIN_02_PRE_DSCALE_H_INIT_RIGHT_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_02_PRE_DSCALE_V_INIT_RIGHT_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_03 (IO_PRE_DS_BASE + 0x15C)
    #define PRE_DS_MAIN_03_PREDS_MAIN_OUT_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_03_PREDS_MAIN_OUT_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_04 (IO_PRE_DS_BASE + 0x160)
    #define PRE_DS_MAIN_04_PREDS_MAIN_IN_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_04_PREDS_MAIN_IN_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_05 (IO_PRE_DS_BASE + 0x164)
    #define PRE_DS_MAIN_05_PREDSMAIN_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_MAIN_05_PREDSMAIN_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_CLEAR_O Fld(1,27,AC_MSKB3)//[27:27]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_CLEAR_I Fld(1,26,AC_MSKB3)//[26:26]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_FINISH_O Fld(1,25,AC_MSKB3)//[25:25]
    #define PRE_DS_MAIN_05_MAIN_SET_RES_FINISH_I Fld(1,24,AC_MSKB3)//[24:24]
    #define PRE_DS_MAIN_05_MAIN_SETRES_ACT_LINE Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_DS_MAIN_05_MAIN_SEL_HVCNT Fld(1,15,AC_MSKB1)//[15:15]
    #define PRE_DS_MAIN_05_MAIN_CLR_HVCNT Fld(1,14,AC_MSKB1)//[14:14]
    #define PRE_DS_MAIN_05_MAIN_VCEN_ACT_AT_SYNC Fld(1,13,AC_MSKB1)//[13:13]
    #define PRE_DS_MAIN_05_MAIN_HCEN_ACT_AT_SYNC Fld(1,12,AC_MSKB1)//[12:12]
    #define PRE_DS_MAIN_05_PREDS_3DTV_MODE_1 Fld(4,8,AC_MSKB1)//[11:8]
    #define PRE_DS_MAIN_05_PREDS_LR_PAIR_CTRL Fld(2,6,AC_MSKB0)//[7:6]
    #define PRE_DS_MAIN_05_PREDS_3DTV_INV Fld(1,5,AC_MSKB0)//[5:5]
    #define PRE_DS_MAIN_05_PREDS_MAIN_SETRES Fld(1,4,AC_MSKB0)//[4:4]
    #define PRE_DS_MAIN_05_PREDS_MAIN_SETRES_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define PRE_DS_MAIN_05_PRE_DSCALE_H_BYPASS_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define PRE_DS_MAIN_05_PRE_DSCALE_V_BYPASS_1 Fld(1,0,AC_MSKB0)//[0:0]
#define PRE_DS_MAIN_06 (IO_PRE_DS_BASE + 0x168)
    #define PRE_DS_MAIN_06_MAIN_H_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_06_MAIN_H_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_07 (IO_PRE_DS_BASE + 0x16C)
    #define PRE_DS_MAIN_07_MAIN_V_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_07_MAIN_V_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_08 (IO_PRE_DS_BASE + 0x170)
    #define PRE_DS_MAIN_08_PRE_DSCALE_V_INIT_BTM_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_MAIN_08_PRE_DSCALE_V_INIT_RIGHT_BTM_1 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_MAIN_09 (IO_PRE_DS_BASE + 0x174)
    #define PRE_DS_MAIN_09_PREDS_3D_FIELD_EN_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_MAIN_09_PREDS_3D_FIELD_INV_1 Fld(1,30,AC_MSKB3)//[30:30]
#define PRE_DS_MAIN_0A (IO_PRE_DS_BASE + 0x178)
    #define PRE_DS_MAIN_0A_PREDS_H_PHASE_INIT_SIGN_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_MAIN_0A_PREDS_H_PHASE_INIT_INTG_1 Fld(3,28,AC_MSKB3)//[30:28]
    #define PRE_DS_MAIN_0A_PREDS_H_PHASE_INIT_FRAC_1 Fld(20,8,AC_MSKDW)//[27:8]
#define PRE_DS_MAIN_0B (IO_PRE_DS_BASE + 0x17C)
    #define PRE_DS_MAIN_0B_PREDS_H_PHASE_DELTA_INTG_1 Fld(3,28,AC_MSKB3)//[30:28]
    #define PRE_DS_MAIN_0B_PREDS_H_PHASE_DELTA_FRAC_1 Fld(20,8,AC_MSKDW)//[27:8]
    #define PRE_DS_MAIN_0B_PREDS_FIR_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define PRE_DS_MAIN_0B_PREDS_FIR_DLY_SEL Fld(4,3,AC_MSKB0)//[6:3]



//Page PREDSPIP
#define PRE_DS_PIP_00 (IO_PRE_DS_BASE + 0x350)
    #define PRE_DS_PIP_00_PRE_DSCALE_H_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_00_PRE_DSCALER_V_2 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_01 (IO_PRE_DS_BASE + 0x354)
    #define PRE_DS_PIP_01_PRE_DSCALE_H_INIT_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_01_PRE_DSCALE_V_INIT_2 Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_02 (IO_PRE_DS_BASE + 0x358)
    #define PRE_DS_PIP_02_PREDS_PIP_OUT_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_02_PREDS_PIP_OUT_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_03 (IO_PRE_DS_BASE + 0x35C)
    #define PRE_DS_PIP_03_PREDS_PIP_IN_H Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_03_PREDS_PIP_IN_V Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_04 (IO_PRE_DS_BASE + 0x360)
    #define PRE_DS_PIP_04_PREDSPIP_ATPG_CT Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_PIP_04_PREDSPIP_ATPG_OB Fld(1,30,AC_MSKB3)//[30:30]
    #define PRE_DS_PIP_04_PIP_SET_RES_CLEAR_O Fld(1,27,AC_MSKB3)//[27:27]
    #define PRE_DS_PIP_04_PIP_SET_RES_CLEAR_I Fld(1,26,AC_MSKB3)//[26:26]
    #define PRE_DS_PIP_04_PIP_SET_RES_FINISH_O Fld(1,25,AC_MSKB3)//[25:25]
    #define PRE_DS_PIP_04_PIP_SET_RES_FINISH_I Fld(1,24,AC_MSKB3)//[24:24]
    #define PRE_DS_PIP_04_PIP_SETRES_ACT_LINE Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_DS_PIP_04_PIP_SEL_HVCNT Fld(1,15,AC_MSKB1)//[15:15]
    #define PRE_DS_PIP_04_PIP_CLR_HVCNT Fld(1,14,AC_MSKB1)//[14:14]
    #define PRE_DS_PIP_04_PIP_VCEN_ACT_AT_SYNC Fld(1,13,AC_MSKB1)//[13:13]
    #define PRE_DS_PIP_04_PIP_HCEN_ACT_AT_SYNC Fld(1,12,AC_MSKB1)//[12:12]
    #define PRE_DS_PIP_04_PREDS_PIP_SETRES Fld(1,4,AC_MSKB0)//[4:4]
    #define PRE_DS_PIP_04_PREDS_PIP_SETRES_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define PRE_DS_PIP_04_PRE_DSCALE_H_BYPASS_2 Fld(1,1,AC_MSKB0)//[1:1]
    #define PRE_DS_PIP_04_PRE_DSCALE_V_BYPASS_2 Fld(1,0,AC_MSKB0)//[0:0]
#define PRE_DS_PIP_06 (IO_PRE_DS_BASE + 0x368)
    #define PRE_DS_PIP_06_PIP_H_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_06_PIP_H_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_07 (IO_PRE_DS_BASE + 0x36C)
    #define PRE_DS_PIP_07_PIP_V_ACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define PRE_DS_PIP_07_PIP_V_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define PRE_DS_PIP_08 (IO_PRE_DS_BASE + 0x370)
    #define PRE_DS_PIP_08_PRE_DSCALE_V_INIT_BTM_2 Fld(16,16,AC_FULLW32)//[31:16]
#define PRE_DS_PIP_09 (IO_PRE_DS_BASE + 0x374)
    #define PRE_DS_PIP_09_PREDS_3D_FIELD_EN_2 Fld(1,31,AC_MSKB3)//[31:31]
    #define PRE_DS_PIP_09_PREDS_3D_FIELD_INV_2 Fld(1,30,AC_MSKB3)//[30:30]
    #define PRE_DS_PIP_09_PREDS_PIP_10BIT_BYPASS Fld(1,29,AC_MSKB3)//[29:29]   //gazelle only

    
#endif    
