#ifndef _HW_CKGEN_H_
#define _HW_CKGEN_H_

#include "hw_pll_group.h"

#define IO_CKGEN_BASE (IO_VIRT + 0xD000)

#define CKGEN_STRAP_OP (IO_CKGEN_BASE + 0x000)
    #define FLD_RS232_FORCE_JTAG_PIN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_STRAP_0 Fld(3,11,AC_MSKB1)//[13:11]
#define CKGEN_CHIPID (IO_CKGEN_BASE + 0x060)
    #define FLD_CHIP_ID Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_CKG_SWID (IO_CKGEN_BASE + 0x064)
    #define FLD_SOFTWARE_ID Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_APLLCFG (IO_CKGEN_BASE + 0x080)
    #define FLD_APLL_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_APLL_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_APLL_K2 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_APLL_K1 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_APLL2CFG (IO_CKGEN_BASE + 0x084)
    #define FLD_APLL2_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_APLL2_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_APLL2_K2 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_APLL2_K1 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_MISCCFG (IO_CKGEN_BASE + 0x088)
    #define FLD_SYSPLL_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SYSPLL_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_VOPLL_DIV_RST Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_VOPLL_BP Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SAWLESSPLL_DIV_RST Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SAWLESSPLL_BP Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_USBPLL_DIV_RST Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_USBPLL_BP Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_TAPLL_DIV_RST Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_TAPLL_BP Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_CPUPLL_DIV_RST Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CPUPLL_BP Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_ENETPLL_DIV_RST Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_ENETPLL_BP Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_G3DPLL_DIV_RST Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_G3DPLL_BP Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMUXPLL_DIV_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMUXPLL_BP Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_VDECPLL_DIV_RST Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_VDECPLL_BP Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_ARMPLL_DIV_RST Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_ARMPLL_BP Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DMAD_CK216M_CTS_DIV_RST Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DMAD_CK216M_CTS_BP Fld(1,8,AC_MSKB1)//[8:8]
#define CKGEN_APLL3CFG (IO_CKGEN_BASE + 0x08C)
    #define FLD_APLL3_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_APLL3_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_APLL3_K2 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_APLL3_K1 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_APLL4CFG (IO_CKGEN_BASE + 0x0A0)
    #define FLD_APLL4_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_APLL4_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_APLL4_K2 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_APLL4_K1 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_APLL5CFG (IO_CKGEN_BASE + 0x0A4)
    #define FLD_APLL5_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_APLL5_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_APLL5_K2 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_APLL5_K1 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PLLCALIB (IO_CKGEN_BASE + 0x0C0)
    #define FLD_CALI_FAIL Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SOFT_RST_CAL Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_CAL_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define FLD_CAL_TRI Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DBGCKSEL Fld(7,8,AC_MSKB1)//[14:8]
    #define FLD_CAL_MODE Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_PLLCALIBRANGEMIN (IO_CKGEN_BASE + 0x0C4)
    #define FLD_CALI_MIN Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PLLCALIBRANGEMAX (IO_CKGEN_BASE + 0x0C8)
    #define FLD_CALI_MAX Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PLLCALIBCNT (IO_CKGEN_BASE + 0x0CC)
    #define FLD_CALI_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_VPCLK_STOP (IO_CKGEN_BASE + 0x100)
    #define FLD_VDOIN_MPCLK_STOP Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_CCIRL_CLK_STOP Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_R2R_CLK_STOP Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_LLC_DLY_CLK_STOP Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_PIP_CLK_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_PIP_CLK_STOP Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_MAIN_CLK_STOP Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_VBI2_CLK_STOP Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_VBI_CLK_STOP Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_CCH_CLK_STOP Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DVI_CLK_STOP Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_VGA_CLK_STOP Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDTV_CLK_STOP Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_TVD_CK54_STOP Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TVD3D_STOP Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_VPCLK_CFG (IO_CKGEN_BASE + 0x104)
    #define FLD_RST_OCLK_DIV45 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_TCLK_DIV_SEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_TVD_CLK_SEL Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_TCLK_CNT_RST Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_ADC_C54M_SEL Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_TVD_CK54_SEL Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CCD_REV Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_PIP_CLK_INV_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_MAIN_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_MJC_DPLL_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_MJC_DPLL_ICGEN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_TVE_TVD_CLK_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_OCLK_CNT_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_VGA_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PIX_CLK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HDTV_CLK_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_POCLK_DPLL_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCLK_DPLL_CKEN Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_RGBCLK_CFG (IO_CKGEN_BASE + 0x108)
    #define FLD_VGA_CKO_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_C_PIX_CLK_INV Fld(1, 29, AC_MSKB3) //29
    #define FLD_HDMI_CLK_REG_DPCLK_U3 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_HDMI_CLK_REG_PCLK_U3 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_HDMI_CLK_REG_DPCLK_U2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_HDMI_CLK_REG_PCLK_U2 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_HDMI_CLK_REG_DPCLK_U1 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_HDMI_CLK_REG_PCLK_U1 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_HDMI_CLK_REG_DPCLK_U0 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_HDMI_CLK_REG_PCLK_U0 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RGB_DUTY_SET Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_HADDS3_REFERENCE_SEL Fld(2,13,AC_MSKB1)//[14:13]
    #define FLD_RGB_INV_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_HADDS2_REFERENCE_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_RGB_CLK_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_HDMI_ABIST_CLK_EN Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_RGB_DELAY_SET Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_PSWCLK_CFG (IO_CKGEN_BASE + 0x10C)
    #define FLD_VDAC2_SIF_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_TVECK_TST Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_VDAC2_PD Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_VDAC2_SEL Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_VDAC1_PD Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_VDAC1_SEL Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_TVE2FS_SEL Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_TVE54_PD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_TVE27_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_TVE54_NORM_CK_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_OCLK_TVE_27M_PD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DAC2_DTDCK Fld(2,13,AC_MSKB1)//[14:13]
    #define FLD_DEMOD_TVE_CK_SEL Fld(2,11,AC_MSKB1)//[12:11]
    #define FLD_DAC_TST_CK_SEL Fld(2,9,AC_MSKB1)//[10:9]
    #define FLD_ABIST_CK1_D2_TOG Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_LVDS_CLK_CTS_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_LVDS_CLK_CTS_TOG Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_VDAC1_SIF_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DAC1_TST_CK_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_LVDS_CLK_CTS_PD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TVE_ABIST_CK_EN Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_OCLK_TEST (IO_CKGEN_BASE + 0x110)
    #define FLD_OCLK_DIV_SEL Fld(2,30,AC_MSKB3)//[31:30]
    #define FLD_OCLK_DIV2_SEL Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_LVDS_CLKDIG_CTS_D11_SEL Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_HDMI_TST_SEL_U3 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_HDMI_TST_SEL_U2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_HDMI_TST_SEL_U1 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_VB1_CK_INV Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_VB1_CK_SEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_OCLK_TVE_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define FLD_HDMI_TSTSEL Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_HADDS3_FCLK_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_HADDS2_FCLK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_TCLK_TEST (IO_CKGEN_BASE + 0x114)
    #define FLD_CLK75M2_CK_SEL Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_OCLK_DIV4_SEL Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_OCLK_DIV3_SEL Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_TCLK_INV Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_TCLK_PD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_TCLK_TSTSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_TCLK_SEL Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_OSD_OCLK_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_OCLK_TVE_SEL_DIV4 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_POCLK_SEL_DIV4 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_OCLK_INV Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_OCLK_PD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OCLK_TSTSEL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_OCLK_SEL Fld(2,0,AC_MSKB0)//[1:0]
        #define FLD_OCLK_SEL_XTAL 0
        #define FLD_OCLK_SEL_LVDS 1
        #define FLD_OCLK_SEL_PPLL 2
#define CKGEN_DDDSVSP_CFG (IO_CKGEN_BASE + 0x118)
    #define FLD_FS_OCLK_INV Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DDDS2_VSP_TSTCK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DDDS1_VSP_TSTCK_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_FS_OC_PRE2_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_FS_OC_PRE1_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_FS_OC_TSTCK_SEL Fld(2,0,AC_MSKB0)//[1:0]
        #define FS_OC_TSTCK_SEL_DDDS2_NOSS 0
        #define FS_OC_TSTCK_SEL_DDDS1_SS 1
        #define FS_OC_TSTCK_SEL_DDDS1_SRC_CK 2
#define CKGEN_CI_TSIF2_CFG (IO_CKGEN_BASE + 0x120)
    #define FLD_CI_FMR2_GAP_LEN Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_CI_FMR1_GAP_LEN Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_CI_FMR2_O_2BIT_4PIN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_CI_FMR2_O_2BIT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_CI_FMR2_O_P Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_CI_FMR1_O_2BIT_4PIN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_CI_FMR1_O_2BIT Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_CI_FMR1_O_P Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_CI_FMR2_I_2BIT_4PIN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_CI_FMR1_I_2BIT_4PIN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_CI_TSO2_CK_MODEL_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_CI_TSO_CK_MODEL_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_CI_TSO2_MODEL_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_CI_TSO_MODEL_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_CIFM1CR (IO_CKGEN_BASE + 0x124)
    #define FLD_SYNC_PAT Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SYNC_LOCK Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SYNC_LOSS Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_FMR_SOFT_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLK_DIV_RST Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DATA_REPEAT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_FMR_2BIT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_FMR_CKE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_FMR_SYNC Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_FMR_SP Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_FMR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_CIFM2CR (IO_CKGEN_BASE + 0x128)
    #define FLD_SYNC_PAT2 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SYNC_LOCK2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SYNC_LOSS2 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_FMR_SOFT_RST2 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLK_DIV_RST2 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DATA_REPEAT2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_FMR_2BIT2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_FMR_CKE2 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_FMR_SYNC2 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_FMR_SP2 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_FMR_EN2 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_CIFM1SR (IO_CKGEN_BASE + 0x12C)
    #define FLD_TUN_ERR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_TUN_SYV Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_TUN_VALD Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_TUN_DATA Fld(8,21,AC_MSKW32)//[28:21]
    #define FLD_PID_FIFO_EMPTY Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_PID_FIFO_FULL Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_INT_ERR_CODE Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_P_FM_FSM Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_S_FM_FSM Fld(8,0,AC_FULLB0)//[7:0]
#define CKGEN_CIFM2SR (IO_CKGEN_BASE + 0x130)
    #define FLD_TUN_ERR2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_TUN_SYV2 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_TUN_VALD2 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_TUN_DATA2 Fld(8,21,AC_MSKW32)//[28:21]
    #define FLD_PID_FIFO_EMPTY2 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_PID_FIFO_FULL2 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_INT_ERR_CODE2 Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_P_FM_FSM2 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_S_FM_FSM2 Fld(8,0,AC_FULLB0)//[7:0]
#define CKGEN_CI_CK_DEBUG (IO_CKGEN_BASE + 0x134)
    #define FLD_CI_TSO2_CK_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CI_TSO_CK_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define CKGEN_DBGCFG (IO_CKGEN_BASE + 0x140)
    #define FLD_DBGCK_DIV_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DBGCK_BP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_MONCK_DIV_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_MONCK_BP Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_MON_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_ABIST_CKCFG (IO_CKGEN_BASE + 0x144)
    #define FLD_DUTY_HIGH_CNT Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_DUTY_ALL_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_DUTY_METER_TARGET_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_DUTY_METER_DONE Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DUTY_METER_ON Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DUTY_SAMPLE_CLK_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_ABIST_VGA_DIV Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_ABIST_VGA_TOG Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_ABIST_SRAM_CKCFG (IO_CKGEN_BASE + 0x148)
    #define FLD_ABIST_SRAM_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_ABIST_SRAM_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_ABIST_SRAM_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_ABIST_PULSE_CFG (IO_CKGEN_BASE + 0x154)
    #define FLD_ABIST_PULSE_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_ABIST_PULSE_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_CI_TSIF_CFG (IO_CKGEN_BASE + 0x158)
    #define FLD_CI_TSO2_D_DIS_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_CI_TSO_D_DIS_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_CI_TSO2_CK_DIS_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_CI_TSO_CK_DIS_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_CI_ADDR_TRI_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_CI_DATA_TRI_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_CTRL_TRI_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSO2_GCK_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSO2_CK_INV Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSO_GCK_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_CI_TSO_CK_INV Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_CI_TSO2_OE Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_CI_TSO_OE Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_TSO_PRE_CK_INV Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_SYNC_MODE Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_CI_ADR_OE Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_S2P_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DATA_FLIP_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_CK_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_CK_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SYNC_INV Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_VLD_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SOFT_RST Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_MJC_DPLL_DIVCFG (IO_CKGEN_BASE + 0x15C)
    #define FLD_MJC_DPLL_IDEAL_PLL_N Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_MJC_DPLL_IDEAL_PLL_M Fld(16,0,AC_FULLW10)//[15:0]
#define CKGEN_EXTTS_CKCKG (IO_CKGEN_BASE + 0x160)
    #define FLD_EXT4_TS_CK_SEL Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_EXT3_TS_CK_SEL Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_EXT2_TS_CK_SEL Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_EXT1_TS_CK_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define FLD_CI_TSO2_CK_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_CI_TSO_CK_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_PB_TSOUT_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define CKGEN_ETH_DMA_AGENT_SEL (IO_CKGEN_BASE + 0x164)
    #define FLD_ETH_DMA_AGENT_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_ETH_AFE_PWD Fld(1,1,AC_MSKB0)//[1:1]
#define CKGEN_MBIST_CK_CTRL (IO_CKGEN_BASE + 0x16C)
    #define FLD_BIST_OD_CK_SEL Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_BIST_VDEC_SLWCK_SEL Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_BIST_AUD_CK_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_BIST_DISP_CLK_SEL Fld(2,18,AC_MSKB2)//[19:18]
    #define FLD_BIST_CK54_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_BIST_PCLK_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_BIST_RGB_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_BIST_PIP_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_BIST_MAIN_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_BIST_TCLK_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_BIST_OCLK_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_BIST_VPCLK_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_BIST_SS_OCLK_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_BIST_VDOIN_OCLK_SEL Fld(1,1,AC_MSKB0)//[1:1]
#define CKGEN_BUS_DCM_CTRL (IO_CKGEN_BASE + 0x170)
    #define FLD_BUS_DCM_MIB Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_BUS_DCM_VENC Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_BUS_DCM_VDEC Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_BUS_DCM_MJC Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_BUS_DCM_BIM Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_BUS_DCM_VIPROC Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_BUS_DCM_SRE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_BUS_DCM_IP Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_MJC_DPLL_DIVCFG2 (IO_CKGEN_BASE + 0x174)
    #define FLD_MJC_DPLL_IDEAL_PLL_N_2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_MJC_DPLL_IDEAL_PLL_M_2 Fld(16,0,AC_FULLW10)//[15:0]
#define CKGEN_MBIST_PD_CFG0 (IO_CKGEN_BASE + 0x180)
    #define FLD_MBIST_PD_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG1 (IO_CKGEN_BASE + 0x184)
    #define FLD_MBIST_PD_CFG1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG2 (IO_CKGEN_BASE + 0x188)
    #define FLD_MBIST_PD_CFG2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG3 (IO_CKGEN_BASE + 0x18C)
    #define FLD_MBIST_PD_CFG3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG4 (IO_CKGEN_BASE + 0x190)
    #define FLD_MBIST_PD_CFG4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG5 (IO_CKGEN_BASE + 0x194)
    #define FLD_MBIST_PD_CFG5 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG6 (IO_CKGEN_BASE + 0x198)
    #define FLD_MBIST_PD_CFG6 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG7 (IO_CKGEN_BASE + 0x19C)
    #define FLD_MBIST_PD_CFG7 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG8 (IO_CKGEN_BASE + 0x1A0)
    #define FLD_MBIST_PD_CFG8 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG9 (IO_CKGEN_BASE + 0x1A4)
    #define FLD_MBIST_PD_CFG9 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_PD_CFG10 (IO_CKGEN_BASE + 0x1A8)
    #define FLD_MBIST_PD_CFG10 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_BLOCK_RST_CFG0 (IO_CKGEN_BASE + 0x1C0)
    #define FLD_MJC_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_USB_RST Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_HIGH_USB_RST Fld(2,27,AC_MSKB3)//[28:27]
    #define FLD_ETHER_RST Fld(2,25,AC_MSKB3)//[26:25]
    #define FLD_VENC_LT_TOP_RST Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_IMGRZ_RST0 Fld(2,22,AC_MSKB2)//[23:22]
    #define FLD_VENC_RST Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GCPU_RST Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_BIM_RST Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_PERI_RST Fld(9,10,AC_MSKW21)//[18:10]
    #define FLD_RFI_RST Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_JPEG_RST Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_B2R_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GRAPH_RST Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DDRPHY_RST Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DMARB_RST Fld(2,3,AC_MSKB0)//[4:3]
    #define FLD_SIM_HOST_RST Fld(2,1,AC_MSKB0)//[2:1]
    #define FLD_MSDC_RST0 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_BLOCK_RST_CFG1 (IO_CKGEN_BASE + 0x1C4)
    #define FLD_AUDIO_RST_0 Fld(3,29,AC_MSKB3)//[31:29]
    #define FLD_AUDIO_RST_1 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SCALER_RST Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_MSDC_RST1 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_ANA_REG_RST Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_MFG_RST Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_VDEC_SOC_RST Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_DEMUX_RST Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_POD_RST Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_VDEC_CORE1_RST Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_VDEC_CORE0_RST Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_TCON_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_TVE_RST Fld(2,13,AC_MSKB1)//[14:13]
    #define FLD_DEMOD_RST1 Fld(3,10,AC_MSKB1)//[12:10]
    #define FLD_VDOIN_RST Fld(3,7,AC_MSKW10)//[9:7]
    #define FLD_IMGRZ_RST1 Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_AUDIO_RST_2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_MIB_RST Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_OD_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_OSD_RST Fld(1,1,AC_MSKB0)//[1:1]
#define CKGEN_BLOCK_CKEN_CFG0 (IO_CKGEN_BASE + 0x1C8)
    #define FLD_MJC_CKEN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_USB_CKEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_HIGH_USB_CKEN Fld(2,27,AC_MSKB3)//[28:27]
    #define FLD_ETHER_CKEN Fld(2,25,AC_MSKB3)//[26:25]
    #define FLD_VENC_LT_TOP_CKEN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_IMGRZ_CKEN0 Fld(2,22,AC_MSKB2)//[23:22]
    #define FLD_VENC_CKEN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GCPU_CKEN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_BIM_CKEN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_PERI_CKEN Fld(9,10,AC_MSKW21)//[18:10]
    #define FLD_RFI_CKEN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_JPEG_CKEN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_B2R_CKEN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GRAPH_CKEN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DDRPHY_CKEN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DMARB_CKEN Fld(2,3,AC_MSKB0)//[4:3]
    #define FLD_SIM_HOST_CKEN Fld(2,1,AC_MSKB0)//[2:1]
    #define FLD_MSDC_CKEN0 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_BLOCK_CKEN_CFG1 (IO_CKGEN_BASE + 0x1CC)
    #define FLD_AUDIO_CKEN_0 Fld(3,29,AC_MSKB3)//[31:29]
    #define FLD_AUDIO_CKEN_1 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SCALER_CKEN Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_MSDC_CKEN1 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_ANA_REG_CKEN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_MFG_CKEN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_VDEC_SOC_CKEN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_DEMUX_CKEN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_POD_CKEN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_VDEC_CORE1_CKEN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_VDEC_CORE0_CKEN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_TCON_CKEN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_TVE_CKEN Fld(2,13,AC_MSKB1)//[14:13]
    #define FLD_DEMOD_CKEN1 Fld(3,10,AC_MSKB1)//[12:10]
    #define FLD_VDOIN_CKEN Fld(3,7,AC_MSKW10)//[9:7]
    #define FLD_IMGRZ_CKEN1 Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_AUDIO_CKEN_2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_MIB_CKEN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_OD_CKEN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_OSD_CKEN Fld(1,1,AC_MSKB0)//[1:1]
#define CKGEN_BLOCK_RST_CFG2 (IO_CKGEN_BASE + 0x1D0)
    #define FLD_IRT_DMA_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_UFOZIP_RST Fld(3,5,AC_MSKB0)//[7:5]
    #define FLD_DEMOD_RST2 Fld(3,2,AC_MSKB0)//[4:2]
    #define FLD_DMARB_C_RST Fld(1,1,AC_MSKB0)//[1:1]
#define CKGEN_BLOCK_CKEN_CFG2 (IO_CKGEN_BASE + 0x1D4)
    #define FLD_IRT_DMA_CKEN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_UFOZIP_CKEN Fld(3,5,AC_MSKB0)//[7:5]
    #define FLD_DEMOD_CKEN2 Fld(3,2,AC_MSKB0)//[4:2]
    #define FLD_DMARB_C_CKEN Fld(1,1,AC_MSKB0)//[1:1]
#define CKGEN_HDMI_CLK_CFG1 (IO_CKGEN_BASE + 0x1E0)
    #define FLD_CCLK_MIBST_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_ABIST_CLK_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_DACR_REF_CLK_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_CCLK_IN_BF_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_VCOCLK_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_MCLK_PD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_FCLK_PD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_CLK27M_PD Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_HDMI_CLK_CFG2 (IO_CKGEN_BASE + 0x1E4)
    #define FLD_MHL_DPCLK_2X_SEL_A Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_MHL_DPCLK_SEL_A Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_MHL_TMDS_CLK_SEL_A Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_TMDS_MBIST_CLK_SEL_A Fld(2,22,AC_MSKB2)//[23:22]
    #define FLD_CH_CLK_PD_A Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_DACR_REF_CLK_PD_A Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CCLK_PD_A Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_DDC_EN_A Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_SPLIT_CLK_SEL_A Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_SDA_DE_CNT_A Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_SCL_DE_CNT_A Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_DPCLK_2X_PD_A Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DP_CLR_2X_CLK_PRE2_SEL_A Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_DPCLK_PD_A Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DP_CLR_CLK_SEL_A Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_TMDS_CLK_PD_A Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TMDS_CLK_INV_A Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_HDMI_CLK_CFG3 (IO_CKGEN_BASE + 0x1E8)
    #define FLD_TMDS_MBIST_CLK_SEL_B Fld(2,22,AC_MSKB2)//[23:22]
    #define FLD_CH_CLK_PD_B Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_DACR_REF_CLK_PD_B Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CCLK_PD_B Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_DDC_EN_B Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_SPLIT_CLK_SEL_B Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_SDA_DE_CNT_B Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_SCL_DE_CNT_B Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_DPCLK_2X_PD_B Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DP_CLR_2X_CLK_PRE2_SEL_B Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_DPCLK_PD_B Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DP_CLR_CLK_SEL_B Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_TMDS_CLK_PD_B Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TMDS_CLK_INV_B Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_HDMI_CLK_CFG4 (IO_CKGEN_BASE + 0x1EC)
    #define FLD_TMDS_MBIST_CLK_SEL_C Fld(2,22,AC_MSKB2)//[23:22]
    #define FLD_CH_CLK_PD_C Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_DACR_REF_CLK_PD_C Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CCLK_PD_C Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_DDC_EN_C Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_SPLIT_CLK_SEL_C Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_SDA_DE_CNT_C Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_SCL_DE_CNT_C Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_DPCLK_2X_PD_C Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DP_CLR_2X_CLK_PRE2_SEL_C Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_DPCLK_PD_C Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DP_CLR_CLK_SEL_C Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_TMDS_CLK_PD_C Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TMDS_CLK_INV_C Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_HDMI_CLK_CFG5 (IO_CKGEN_BASE + 0x1F0)
    #define FLD_TMDS_MBIST_CLK_SEL_D Fld(2,22,AC_MSKB2)//[23:22]
    #define FLD_CH_CLK_PD_D Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_DACR_REF_CLK_PD_D Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CCLK_PD_D Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_DDC_EN_D Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_SPLIT_CLK_SEL_D Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_SDA_DE_CNT_D Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_SCL_DE_CNT_D Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_DPCLK_2X_PD_D Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DP_CLR_2X_CLK_PRE2_SEL_D Fld(2,5,AC_MSKB0)//[6:5]
    #define FLD_DPCLK_PD_D Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DP_CLR_CLK_SEL_D Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_TMDS_CLK_PD_D Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TMDS_CLK_INV_D Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_HDMI_CLK_CFG6 (IO_CKGEN_BASE + 0x1F4)
    #define FLD_SCL_DE_RSTB_D Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SCL_DE_RSTB_C Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SCL_DE_RSTB_B Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SCL_DE_RSTB_A Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPLIT_CLK_RSTB_D Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPLIT_CLK_RSTB_C Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_SPLIT_CLK_RSTB_B Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_SPLIT_CLK_RSTB_A Fld(1,24,AC_MSKB3)//[24:24]
#define CKGEN_HDMI_CLK_CFG7 (IO_CKGEN_BASE + 0x1F8)
    #define FLD_B2R2_PLL_SEL Fld(2,29,AC_MSKB3)//[30:29]
    #define FLD_B2R1_PLL_SEL Fld(2,27,AC_MSKB3)//[28:27]
    #define FLD_CLK_192M_TMP_SEL Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_CLK_192M_TMP_SEL1 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_NPIP_CLK_SELECT Fld(9,16,AC_MSKW32)//[24:16]
    #define FLD_R2R_PIP_CLK_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_R2R_MAIN_CLK_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_R2R_CCIR0_CLK_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_R2R_CCIR1_CLK_SEL Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_R2R_CLK_SELECT Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_R2R_CLK_SELECT_INV Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_CLK_192M_TMP_SEL0 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_HDMI_R2R_CLK_SEL Fld(3,6,AC_MSKW10)//[8:6]
    #define FLD_CCH_PIP_CLK_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_CCH_CLK_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_W2D_CLK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_MISC_CKCFG (IO_CKGEN_BASE + 0x200)
    #define FLD_TOG Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DLY_SOURCE Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_DLY_PHASE Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_SLOW_CK Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_CPU_CKCFG (IO_CKGEN_BASE + 0x208)
    #define FLD_BUS_CK_TST Fld(3,11,AC_MSKB1)//[13:11]
    #define FLD_BUS_CK_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_CPU_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CPU_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_FLASH_CKCFG (IO_CKGEN_BASE + 0x20C)
    #define FLD_FLASH_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_FLASH_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
#define CKGEN_MEM_CKCFG (IO_CKGEN_BASE + 0x210)
    #define FLD_M_CK_SEL1 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_M_CK_TST Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_MEM_CK_PD Fld(1,3,AC_MSKB0)//[3:3]
#define CKGEN_AUD_CKCFG (IO_CKGEN_BASE + 0x214)
    #define FLD_RST_HDMI_CNT Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_HDMI_CNT Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_TOG_HDMI_CLK Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RST_AO_CNT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_AO_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_TOG_AMOCLK Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_AUD_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_AUD_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_AUD_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_AUD2_CKCFG (IO_CKGEN_BASE + 0x218)
    #define FLD_RST_BO_CNT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_BO_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_TOG_BOMCLK Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_AUD2_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_AUD2_DK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_AUD2_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_AUD3_CKCFG (IO_CKGEN_BASE + 0x21C)
    #define FLD_AUD3_CK_DIVIDE Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_AUD3_CK_RST Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_AUD3_CK_BYPASS Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_AUD3_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_AUD3_DK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_AUD3_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_PWM_CKCFG (IO_CKGEN_BASE + 0x220)
    #define FLD_PWMH_CK_TST Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_PWM_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PWM_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PWM_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_PWM2_CKCFG (IO_CKGEN_BASE + 0x224)
    #define FLD_PWMH2_CK_TST Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_PWM2_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PWM2_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PWM2_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_B2R_HD_CKCFG (IO_CKGEN_BASE + 0x228)
    #define FLD_B2R_HD_CK_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_B2R_HD_CK_SRC Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_B2R_HD_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_B2R_HD_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_B2R_HD_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_B2R_HD_DIVCFG (IO_CKGEN_BASE + 0x22C)
    #define FLD_B2R_HD_CK_IDEAL_PLL_N Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_B2R_HD_CK_IDEAL_PLL_M Fld(16,0,AC_FULLW10)//[15:0]
#define CKGEN_B2R_SD_CKCFG (IO_CKGEN_BASE + 0x230)
    #define FLD_B2R_SD_CK_SEL_2 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_B2R_SD_CK_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_B2R_SD_CK_SRC Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_B2R_SD_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_B2R_SD_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_B2R_SD_CK_PRE_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_B2R_SD_DIVCFG (IO_CKGEN_BASE + 0x234)
    #define FLD_B2R_SD_CK_IDEAL_PLL_N Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_B2R_SD_CK_IDEAL_PLL_M Fld(16,0,AC_FULLW10)//[15:0]
#define CKGEN_TS0_CKCFG (IO_CKGEN_BASE + 0x238)
    #define FLD_TS3_CNT_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_TS3_CNT Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_TS3_CK_PD Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_TS3_CK_TOG Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_TS3_CK_SEL Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_TS2_CNT_RST Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_TS2_CNT Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_TS2_CK_PD Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_TS2_CK_TOG Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_TS2_CK_SEL Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_TS1_CNT_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_TS1_CNT Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_TS1_CK_PD Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_TS1_CK_TOG Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_TS1_CK_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_TS0_CNT_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TS0_CNT Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TS0_CK_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_TS0_CK_TOG Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_TS0_CK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_PWM3_CKCFG (IO_CKGEN_BASE + 0x23C)
    #define FLD_PWMH3_CK_TST Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_PWM3_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PWM3_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PWM3_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_MON_OUT_CKCFG (IO_CKGEN_BASE + 0x240)
    #define FLD_GFX_TIME_GEN_CK Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_REF_TIME_GEN_CK_SEL Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_VDO_OCLK_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define FLD_TTD_CLK_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_UHD_CLK_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_SC_GFX_CK_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_SC_PIP_ICLK_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_MON_OUT_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_AOUT3_AUD_CKCFG (IO_CKGEN_BASE + 0x244)
    #define FLD_AOUT3_AUD_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_AOUT3_AUD_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_AOUT3_AUD_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_SPI_CKCFG (IO_CKGEN_BASE + 0x300)
    #define FLD_SPI_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SPI_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SPI_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_TSOUT_CKCFG (IO_CKGEN_BASE + 0x304)
    #define FLD_TSOUT_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TSOUT_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TSOUT_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_ATDAD_CKCFG (IO_CKGEN_BASE + 0x308)
    #define FLD_ATDAD_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_ATDAD_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_ATDAD_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_CLK54M_CKCFG (IO_CKGEN_BASE + 0x30C)
    #define FLD_CLK54M_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLK54M_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CLK54M_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_DMX_CKCFG (IO_CKGEN_BASE + 0x314)
    #define FLD_DMX_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DMX_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DMX_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_DSP_CKCFG (IO_CKGEN_BASE + 0x31C)
    #define FLD_DSP_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DSP_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DSP_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_AIN_CKCFG (IO_CKGEN_BASE + 0x320)
    #define FLD_AIN_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_AIN_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_AIN_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_USB_CLK_CKCFG (IO_CKGEN_BASE + 0x324)
    #define FLD_USBPHY_DIVIDE_RST Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_USBPHY_CK_DIV9 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_USBPLL_SEL Fld(2,9,AC_MSKB1)//[10:9]
#define CKGEN_REG_NFI_CKCFG (IO_CKGEN_BASE + 0x328)
    #define FLD_NFI_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_NFI_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_NFI_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_SD_CKCFG (IO_CKGEN_BASE + 0x32C)
    #define FLD_SD_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SD_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SD_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_SSUSB_REF_CKCFG (IO_CKGEN_BASE + 0x330)
    #define FLD_SSUSB_REF_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SSUSB_REF_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SSUSB_REF_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_HADDS2_CKCFG (IO_CKGEN_BASE + 0x334)
	#define FLD_HADDS2_ALL Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_HADDS2_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_HADDS2_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HADDS2_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HADDS2_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_HADDS3_CKCFG (IO_CKGEN_BASE + 0x338)
	#define FLD_HADDS3_ALL Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_HADDS3_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_HADDS3_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HADDS3_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HADDS3_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_SC_CKCFG (IO_CKGEN_BASE + 0x340)
    #define FLD_SC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SC_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_CI_CKCFG (IO_CKGEN_BASE + 0x358)
    #define FLD_CI_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CI_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CI_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_HEAC_MDC_CKCFG (IO_CKGEN_BASE + 0x35C)
    #define FLD_HEAC_MDC_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_HEAC_MDC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HEAC_MDC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HEAC_MDC_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_TRACE_CKCFG (IO_CKGEN_BASE + 0x360)
    #define FLD_TRACE_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TRACE_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TRACE_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_DISP_CKCFG (IO_CKGEN_BASE + 0x368)
    #define FLD_OSD_ECLK_SEL Fld(2,30,AC_MSKB3)//[31:30]
    #define FLD_SVPCLK_SEL Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SC_SRAM_PIP_CLK_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_OSD1_PCLK_SEL Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RESYNC_PCLK_TSTSEL Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_RESYNC_PCLK_TOG Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD_PCLK_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_SCPIP_MAIN_CLK_SEL Fld(3,19,AC_MSKB2)//[21:19]
    #define FLD_SCPIP_PIP_CLK_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_SCPIP_PIP_CLK_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_PIP_PS_DISP_CLK_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_PS_DISP_CLK_SEL Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TDDC_CLK_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_POCLK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_ASRC_CKCFG (IO_CKGEN_BASE + 0x36C)
    #define FLD_ASRC_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_ASRC_CK_TSTSEL Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_ASRC_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_VENC_CKCFG (IO_CKGEN_BASE + 0x370)
    #define FLD_VENC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_VENC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_VENC_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_MJC_CKCFG (IO_CKGEN_BASE + 0x374)
    #define FLD_MJC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_MJC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_MJC_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_POCLK_DPLL_DIVCFG (IO_CKGEN_BASE + 0x378)
    #define FLD_POCLK_DPLL_IDEAL_PLL_N Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_POCLK_DPLL_IDEAL_PLL_M Fld(16,0,AC_FULLW10)//[15:0]
#define CKGEN_REG_SD1_CKCFG (IO_CKGEN_BASE + 0x380)
    #define FLD_SD1_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SD1_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SD1_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_HCLK1_CKCFG (IO_CKGEN_BASE + 0x384)
    #define FLD_HCLK1_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HCLK1_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HCLK1_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_CLK216M_CKCFG (IO_CKGEN_BASE + 0x388)
    #define FLD_CLK216M_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLK216M_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CLK216M_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_DVBTCI_CKCFG (IO_CKGEN_BASE + 0x38C)
    #define FLD_DVBTCI_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DVBTCI_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DVBTCI_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_JPEG_CKCFG (IO_CKGEN_BASE + 0x394)
    #define FLD_JPEG_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_JPEG_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_JPEG_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_GCPU_CKCFG (IO_CKGEN_BASE + 0x39C)
    #define FLD_GCPU_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GCPU_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_GCPU_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_HCLK_CKCFG (IO_CKGEN_BASE + 0x3A0)
    #define FLD_HCLK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HCLK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HCLK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_USB_CKCFG (IO_CKGEN_BASE + 0x3A4)
    #define FLD_USB_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_USB_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_USB_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_USB_FREE_CKCFG (IO_CKGEN_BASE + 0x3A8)
    #define FLD_USB_FREE_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_USB_FREE_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_USB_FREE_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_NIC_EXT_CKCFG (IO_CKGEN_BASE + 0x3AC)
    #define FLD_NIC_EXT_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_NIC_EXT_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_NIC_EXT_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_NIC_SLAVE_CKCFG (IO_CKGEN_BASE + 0x3B0)
    #define FLD_NIC_SLAVE_MISC Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_NIC_SLAVE_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_NIC_SLAVE_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_NIC_SLAVE_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_MIB_OCLK_CKCFG (IO_CKGEN_BASE + 0x3B4)
    #define FLD_OCLK_DIV8_PHASE_SEL Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_OCLK_DIV4_PHASE_SEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_OCLK_DIV2_PHASE_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_SC_POCLK_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define FLD_MCVP_CK_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_MCVP_CK_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_MIB_OCLK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_MIB_OCLK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_MIB_OCLK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_XDDS_CKCFG (IO_CKGEN_BASE + 0x3B8)
    #define FLD_XDDS_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_XDDS_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_XDDS_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_XDDS_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_DDDS1_CKCFG (IO_CKGEN_BASE + 0x3C0)
    #define FLD_DDDS1_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DDDS1_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DDDS1_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DDDS1_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_IMGRZ_CKCFG (IO_CKGEN_BASE + 0x3C4)
    #define FLD_IMGRZ_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_IMGRZ_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_IMGRZ_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_GRA2D_CKCFG (IO_CKGEN_BASE + 0x3C8)
    #define FLD_GRA2D_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GRA2D_CK_TSTSEL Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_GRA2D_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_VDEC_MBIST_CKCFG (IO_CKGEN_BASE + 0x3CC)
    #define FLD_VDEC_MBIST_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_VDEC_MBIS_CK_TSTSEL Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_VDEC_MBIS_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_PNG_CKCFG (IO_CKGEN_BASE + 0x3D0)
    #define FLD_PNG_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PNG_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PNG_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_G3D_CORE_CKCFG (IO_CKGEN_BASE + 0x3D4)
    #define FLD_G3D_CORE_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_G3D_CORE_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_G3D_CORE_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_G3D_13M_CKCFG (IO_CKGEN_BASE + 0x3D8)
    #define FLD_G3D_13M_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_G3D_13M_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_G3D_13M_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_DVBTFEC_CKCFG (IO_CKGEN_BASE + 0x3DC)
    #define FLD_DVBTFEC_MISC Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DVBTFEC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DVBTFEC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DVBTFEC_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_C27M_CKCFG (IO_CKGEN_BASE + 0x3E0)
    #define FLD_C27M_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_C27M_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_C27M_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_BIST_CKCFG (IO_CKGEN_BASE + 0x3E4)
    #define FLD_BIST_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_BIST_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_BIST_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_IMGRZ0_CKCFG (IO_CKGEN_BASE + 0x3E8)
    #define FLD_IMGRX0_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_IMGRX0_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_IMGRX0_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_VDEC_SYS_CKCFG (IO_CKGEN_BASE + 0x3F4)
    #define FLD_VDEC_SYS_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_VDEC_SYS_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_VDEC_SYS_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_HADDS1_CKCFG (IO_CKGEN_BASE + 0x3FC)
    #define FLD_HADDS1_ALL Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_HADDS1_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_HADDS1_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HADDS1_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HADDS1_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PWM_PERI_CKCFG (IO_CKGEN_BASE + 0x404)
    #define FLD_PWM_PERI_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PWM_PERI_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PWM_PERI_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_SC1_CKCFG (IO_CKGEN_BASE + 0x408)
    #define FLD_SC1_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SC1_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SC1_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_OSD_CORE_CKCFG (IO_CKGEN_BASE + 0x40C)
    #define FLD_OSD_CORE_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_OSD_CORE_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_OSD_CORE_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_SIFM2_PERI_CKCFG (IO_CKGEN_BASE + 0x410)
    #define FLD_SIFM2_PERI_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SIFM2_PERI_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SIFM2_PERI_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_TDDC_CKCFG (IO_CKGEN_BASE + 0x418)
    #define FLD_TDDC_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TDDC_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TDDC_CK_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_TSOUT2_CKCFG (IO_CKGEN_BASE + 0x41C)
    #define FLD_TSOUT2_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TSOUT2_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TSOUT2_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_SRE_OCLK_CKCFG (IO_CKGEN_BASE + 0x420)
    #define FLD_QPQE_QCLK_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_QPQE_ZCLK_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_QPQE_VOCLK_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_VOCLK_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_SRSCLK_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_VICLK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_IMGRZ1_CKCFG (IO_CKGEN_BASE + 0x424)
    #define FLD_IMGRZ1_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_IMGRZ1_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_IMGRZ1_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_IMGRZ2_CKCFG (IO_CKGEN_BASE + 0x428)
    #define FLD_IMGRZ2_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_IMGRZ2_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_IMGRZ2_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_DEMOD_VDAC_CKCFG (IO_CKGEN_BASE + 0x42C)
    #define FLD_DEMOD_VDAC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_VDAC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DEMOD_VDAC_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_HDMI_MHL340M_CKCFG (IO_CKGEN_BASE + 0x430)
    #define FLD_HDMI_MHL340M_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HDMI_MHL340M_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HDMI_MHL340M_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_HDMI_MHLPIX340M_CKCFG (IO_CKGEN_BASE + 0x434)
    #define FLD_HDMI_MHLPIX340M_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HDMI_MHLPIX340M_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HDMI_MHLPIX340M_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_CT_ADC_CKCFG (IO_CKGEN_BASE + 0x438)
    #define FLD_CT_ADC_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CT_ADC_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CT_ADC_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_TVE_FIFO_CFG (IO_CKGEN_BASE + 0x43C)
    #define FLD_VDAC_CAL_CK_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_TVE_TVD_UP_CK_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_TVE_54_SRC_XOR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_TVE_TVD_UPCK_XOR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TVE_108_CK_TST Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_MHL_CKCFG (IO_CKGEN_BASE + 0x440)
    #define FLD_MHL_DPCLK_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_MHL_PCLK_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_TSOUT3_CKCFG (IO_CKGEN_BASE + 0x444)
    #define FLD_TSOUT3_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TSOUT3_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_TSOUT3_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_CI_FMR_CKCFG (IO_CKGEN_BASE + 0x448)
    #define FLD_CI_FMR_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CI_FMR_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CI_FMR_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_CI_FMR2_CKCFG (IO_CKGEN_BASE + 0x44C)
    #define FLD_CI_FMR2_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CI_FMR2_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CI_FMR2_CK_SEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_REG_XHCI_CKCFG (IO_CKGEN_BASE + 0x450)
    #define FLD_XHCI_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_XHCI_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_XHCI_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_PTP_CKCFG (IO_CKGEN_BASE + 0x454)
    #define FLD_PTP_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PTP_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PTP_CK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_PTP_SLOW_CKCFG (IO_CKGEN_BASE + 0x458)
    #define FLD_PTP_SLOW_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PTP_SLOW_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PTP_SLOW_CK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_VDEC_LAE_CKCFG (IO_CKGEN_BASE + 0x45C)
    #define FLD_VDEC_LAE_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_VDEC_LAE_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_VDEC_LAE_CK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_DSTX_CKCFG (IO_CKGEN_BASE + 0x460)
    #define FLD_DSTX_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DSTX_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_DSTX_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_CLK108M_CKCFG (IO_CKGEN_BASE + 0x464)
    #define FLD_CLK108M_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLK108M_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CLK110M_CK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define CKGEN_REG_CLK57P6M_CKCFG (IO_CKGEN_BASE + 0x468)
    #define FLD_CLK57P6M_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLK57P6M_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_CLK57P6M_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_HDMI2_DPLL_REF_CKCFG (IO_CKGEN_BASE + 0x46C)
    #define FLD_HDMI2_DPLL_REF_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_HDMI2_DPLL_REF_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_HDMI2_DPLL_REF_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_PE2_MAC_CKCFG (IO_CKGEN_BASE + 0x470)
    #define FLD_PE2_MAC_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PE2_MAC_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PE2_MAC_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_UFOZIP_CKCFG (IO_CKGEN_BASE + 0x474)
    #define FLD_UFOZIP_CK_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_UFOZIP_CK_TST Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_UFOZIP_CK_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define CKGEN_REG_MSDCPAD_SR_CFG0 (IO_CKGEN_BASE + 0x480)
    #define FLD_MSDCPAD_SR_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_SR_CFG1 (IO_CKGEN_BASE + 0x484)
    #define FLD_MSDCPAD_SR_CFG1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_DRV_CFG0 (IO_CKGEN_BASE + 0x488)
    #define FLD_MSDCPAD_DRV_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_DRV_CFG1 (IO_CKGEN_BASE + 0x48C)
    #define FLD_MSDCPAD_DRV_CFG1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_DRV_CFG2 (IO_CKGEN_BASE + 0x490)
    #define FLD_MSDCPAD_DRV_CFG2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_RDSEL_CFG0 (IO_CKGEN_BASE + 0x494)
    #define FLD_MSDCPAD_RDSEL_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_RDSEL_CFG1 (IO_CKGEN_BASE + 0x498)
    #define FLD_MSDCPAD_RDSEL_CFG1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_RDSEL_CFG2 (IO_CKGEN_BASE + 0x49C)
    #define FLD_MSDCPAD_RDSEL_CFG2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_RDSEL_CFG3 (IO_CKGEN_BASE + 0x4A0)
    #define FLD_MSDCPAD_RDSEL_CFG3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_TDSEL_CFG0 (IO_CKGEN_BASE + 0x4A4)
    #define FLD_MSDCPAD_TDSEL_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_TDSEL_CFG1 (IO_CKGEN_BASE + 0x4A8)
    #define FLD_MSDCPAD_TDSEL_CFG1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_R0R1_CFG0 (IO_CKGEN_BASE + 0x4AC)
    #define FLD_MSDCPAD_R0R1_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_IES_CFG0 (IO_CKGEN_BASE + 0x4B0)
    #define FLD_MSDCPAD_IES_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_PUPD_CFG0 (IO_CKGEN_BASE + 0x4B4)
    #define FLD_MSDCPAD_PUPD_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_SMT_CFG0 (IO_CKGEN_BASE + 0x4B8)
    #define FLD_MSDCPAD_SMT_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_DRVE_CFG0 (IO_CKGEN_BASE + 0x4BC)
    #define FLD_MSDCPAD_DRVE_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCPAD_DRVP_CFG0 (IO_CKGEN_BASE + 0x4C0)
    #define FLD_MSDCPAD_DRVP_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_MSDCEMMC_GPIO_CFG0 (IO_CKGEN_BASE + 0x4C4)
    #define FLD_MSDCEMMC_SMT_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADPUCFG (IO_CKGEN_BASE + 0x500)
    #define FLD_AOSDATA1_PU Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_AOSDATA0_PU Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_AOBCK_PU Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_AOLRCK_PU Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_AOMCLK_PU Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ASPDIF1_PU Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ASPDIF0_PU Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_ALIN_PU Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_OSD1_PU Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD0_PU Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_UART1_PU Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO72_PU Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO71_PU Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO70_PU Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO69_PU Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO68_PU Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO67_PU Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_OPWM2_PU Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_OPWM1_PU Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_OPWM0_PU Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO60_PU Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO59_PU Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO58_PU Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO57_PU Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO56_PU Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_EMMC_RST_PU Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PARB_PU Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_POCE1_PU Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PDD1_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDD0_PU Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_POOE_PU Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCE0_PU Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPUCFG1 (IO_CKGEN_BASE + 0x504)
    #define FLD_CI_INT_PU Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DEMOD_RST_PU Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SPI_CLE_PU Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SPI_DATA_PU Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPI_CLK1_PU Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPI_CLK_PU Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_PVR_TSDATA1_PU Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_PVR_TSDATA0_PU Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_PVR_TSSYNC_PU Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_PVR_TSVAL_PU Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_PVR_TSCLK_PU Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_TSDATA0_PU Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSSYNC_PU Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSVAL_PU Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSCLK_PU Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DEMOD_TSDATA7_PU Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMOD_TSDATA6_PU Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMOD_TSDATA5_PU Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DEMOD_TSDATA4_PU Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DEMOD_TSDATA3_PU Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_DEMOD_TSDATA2_PU Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_DEMOD_TSDATA1_PU Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DEMOD_TSDATA0_PU Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DEMOD_TSSYNC_PU Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEMOD_TSVAL_PU Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_TSCLK_PU Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OS2_PU Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RF_AGC_PU Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_IF_AGC_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_AOSDATA4_PU Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_AOSDATA3_PU Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_AOSDATA2_PU Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPUCFG2 (IO_CKGEN_BASE + 0x508)
    #define FLD_GPIO31_PU Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO30_PU Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO29_PU Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO28_PU Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO27_PU Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO26_PU Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO25_PU Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO24_PU Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO23_PU Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO22_PU Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO21_PU Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO20_PU Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO19_PU Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO18_PU Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO17_PU Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO16_PU Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO15_PU Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO14_PU Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO13_PU Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO12_PU Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO11_PU Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO10_PU Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO9_PU Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO8_PU Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO7_PU Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO6_PU Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO5_PU Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO4_PU Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO3_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO2_PU Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO1_PU Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO0_PU Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPUCFG3 (IO_CKGEN_BASE + 0x50C)
    #define FLD_DTMB3_PU Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DTMB2_PU Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_DTMB1_PU Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_EEPROM_PU Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO66_PU Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO65_PU Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO64_PU Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO63_PU Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO62_PU Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO61_PU Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO55_PU Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO52_53_54_PU Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO51_PU Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO50_PU Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO49_PU Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO48_PU Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO47_PU Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO46_PU Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO45_PU Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO44_PU Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO43_PU Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO42_PU Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO41_PU Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO40_PU Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO39_PU Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO38_PU Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO37_PU Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO36_PU Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO35_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO34_PU Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO33_PU Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO32_PU Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPDCFG (IO_CKGEN_BASE + 0x510)
    #define FLD_AOSDATA1_PD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_AOSDATA0_PD Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_AOBCK_PD Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_AOLRCK_PD Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_AOMCLK_PD Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ASPDIF1_PD Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ASPDIF0_PD Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_ALIN_PD Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_OSD1_PD Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD0_PD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_UART1_PD Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO72_PD Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO71_PD Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO70_PD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO69_PD Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO68_PD Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO67_PD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_OPWM2_PD Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_OPWM1_PD Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_OPWM0_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO60_PD Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO59_PD Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO58_PD Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO57_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO56_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_EMMC_RST_PD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PARB_PD Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_POCE1_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PDD1_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDD0_PD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_POOE_PD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCE0_PD Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPDCFG1 (IO_CKGEN_BASE + 0x514)
    #define FLD_CI_INT_PD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DEMOD_RST_PD Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SPI_CLE_PD Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SPI_DATA_PD Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPI_CLK1_PD Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPI_CLK_PD Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_PVR_TSDATA1_PD Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_PVR_TSDATA0_PD Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_PVR_TSSYNC_PD Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_PVR_TSVAL_PD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_PVR_TSCLK_PD Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_TSDATA0_PD Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSSYNC_PD Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSVAL_PD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSCLK_PD Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DEMOD_TSDATA7_PD Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMOD_TSDATA6_PD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMOD_TSDATA5_PD Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DEMOD_TSDATA4_PD Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DEMOD_TSDATA3_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_DEMOD_TSDATA2_PD Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_DEMOD_TSDATA1_PD Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DEMOD_TSDATA0_PD Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DEMOD_TSSYNC_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEMOD_TSVAL_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_TSCLK_PD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OS2_PD Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RF_AGC_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_IF_AGC_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_AOSDATA4_PD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_AOSDATA3_PD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_AOSDATA2_PD Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPDCFG2 (IO_CKGEN_BASE + 0x518)
    #define FLD_GPIO31_PD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO30_PD Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO29_PD Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO28_PD Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO27_PD Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO26_PD Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO25_PD Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO24_PD Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO23_PD Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO22_PD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO21_PD Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO20_PD Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO19_PD Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO18_PD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO17_PD Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO16_PD Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO15_PD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO14_PD Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO13_PD Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO12_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO11_PD Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO10_PD Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO9_PD Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO8_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO7_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO6_PD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO5_PD Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO4_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO3_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO2_PD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO1_PD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO0_PD Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADPDCFG3 (IO_CKGEN_BASE + 0x51C)
    #define FLD_DTMB3_PD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DTMB2_PD Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_DTMB1_PD Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_EEPROM_PD Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO66_PD Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO65_PD Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO64_PD Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO63_PD Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO62_PD Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO61_PD Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO55_PD Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO52_53_54_PD Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO51_PD Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO50_PD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO49_PD Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO48_PD Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO47_PD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO46_PD Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO45_PD Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO44_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO43_PD Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO42_PD Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO41_PD Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO40_PD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO39_PD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO38_PD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO37_PD Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO36_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO35_PD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO34_PD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO33_PD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO32_PD Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSMTCFG (IO_CKGEN_BASE + 0x520)
    #define FLD_AOSDATA1_SMT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_AOSDATA0_SMT Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_AOBCK_SMT Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_AOLRCK_SMT Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_AOMCLK_SMT Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ASPDIF1_SMT Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ASPDIF0_SMT Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_ALIN_SMT Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_OSD1_SMT Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD0_SMT Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_UART1_SMT Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO72_SMT Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO71_SMT Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO70_SMT Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO69_SMT Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO68_SMT Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO67_SMT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_OPWM2_SMT Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_OPWM1_SMT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_OPWM0_SMT Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO60_SMT Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO59_SMT Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO58_SMT Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO57_SMT Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO56_SMT Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_EMMC_RST_SMT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PARB_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_POCE1_SMT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PDD1_SMT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDD0_SMT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_POOE_SMT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCE0_SMT Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSMTCFG1 (IO_CKGEN_BASE + 0x524)
    #define FLD_CI_INT_SMT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DEMOD_RST_SMT Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SPI_CLE_SMT Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SPI_DATA_SMT Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPI_CLK1_SMT Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPI_CLK_SMT Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_PVR_TSDATA1_SMT Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_PVR_TSDATA0_SMT Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_PVR_TSSYNC_SMT Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_PVR_TSVAL_SMT Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_PVR_TSCLK_SMT Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_TSDATA0_SMT Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSSYNC_SMT Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSVAL_SMT Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSCLK_SMT Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DEMOD_TSDATA7_SMT Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMOD_TSDATA6_SMT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMOD_TSDATA5_SMT Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DEMOD_TSDATA4_SMT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DEMOD_TSDATA3_SMT Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_DEMOD_TSDATA2_SMT Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_DEMOD_TSDATA1_SMT Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DEMOD_TSDATA0_SMT Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DEMOD_TSSYNC_SMT Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEMOD_TSVAL_SMT Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_TSCLK_SMT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OS2_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RF_AGC_SMT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_IF_AGC_SMT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_AOSDATA4_SMT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_AOSDATA3_SMT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_AOSDATA2_SMT Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSMTCFG2 (IO_CKGEN_BASE + 0x528)
    #define FLD_GPIO31_SMT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO30_SMT Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO29_SMT Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO28_SMT Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO27_SMT Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO26_SMT Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO25_SMT Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO24_SMT Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO23_SMT Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO22_SMT Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO21_SMT Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO20_SMT Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO19_SMT Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO18_SMT Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO17_SMT Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO16_SMT Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO15_SMT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO14_SMT Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO13_SMT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO12_SMT Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO11_SMT Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO10_SMT Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO9_SMT Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO8_SMT Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO7_SMT Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO6_SMT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO5_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO4_SMT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO3_SMT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO2_SMT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO1_SMT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO0_SMT Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSMTCFG3 (IO_CKGEN_BASE + 0x52C)
    #define FLD_DTMB3_SMT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DTMB2_SMT Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_DTMB1_SMT Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_EEPROM_SMT Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO66_SMT Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO65_SMT Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO64_SMT Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO63_SMT Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO62_SMT Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO61_SMT Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO55_SMT Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO52_53_54_SMT Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO51_SMT Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO50_SMT Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO49_SMT Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO48_SMT Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO47_SMT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO46_SMT Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO45_SMT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO44_SMT Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO43_SMT Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO42_SMT Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO41_SMT Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO40_SMT Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO39_SMT Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO38_SMT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO37_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO36_SMT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO35_SMT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO34_SMT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO33_SMT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO32_SMT Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSRCFG (IO_CKGEN_BASE + 0x530)
    #define FLD_AOSDATA1_SR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_AOSDATA0_SR Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_AOBCK_SR Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_AOLRCK_SR Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_AOMCLK_SR Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ASPDIF1_SR Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ASPDIF0_SR Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_ALIN_SR Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_OSD1_SR Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD0_SR Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_UART1_SR Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO72_SR Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO71_SR Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO70_SR Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO69_SR Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO68_SR Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO67_SR Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_OPWM2_SR Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_OPWM1_SR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_OPWM0_SR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO60_SR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO59_SR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO58_SR Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO57_SR Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO56_SR Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_EMMC_RST_SR Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PARB_SR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_POCE1_SR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PDD1_SR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDD0_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_POOE_SR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCE0_SR Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSRCFG1 (IO_CKGEN_BASE + 0x534)
    #define FLD_CI_INT_SR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DEMOD_RST_SR Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SPI_CLE_SR Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SPI_DATA_SR Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPI_CLK1_SR Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPI_CLK_SR Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_PVR_TSDATA1_SR Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_PVR_TSDATA0_SR Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_PVR_TSSYNC_SR Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_PVR_TSVAL_SR Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_PVR_TSCLK_SR Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_TSDATA0_SR Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSSYNC_SR Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSVAL_SR Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSCLK_SR Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DEMOD_TSDATA7_SR Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMOD_TSDATA6_SR Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMOD_TSDATA5_SR Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DEMOD_TSDATA4_SR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DEMOD_TSDATA3_SR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_DEMOD_TSDATA2_SR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_DEMOD_TSDATA1_SR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DEMOD_TSDATA0_SR Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DEMOD_TSSYNC_SR Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEMOD_TSVAL_SR Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_TSCLK_SR Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OS2_SR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RF_AGC_SR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_IF_AGC_SR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_AOSDATA4_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_AOSDATA3_SR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_AOSDATA2_SR Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSRCFG2 (IO_CKGEN_BASE + 0x538)
    #define FLD_GPIO31_SR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO30_SR Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO29_SR Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO28_SR Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO27_SR Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO26_SR Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO25_SR Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO24_SR Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO23_SR Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO22_SR Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO21_SR Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO20_SR Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO19_SR Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO18_SR Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO17_SR Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO16_SR Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO15_SR Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO14_SR Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO13_SR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO12_SR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO11_SR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO10_SR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO9_SR Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO8_SR Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO7_SR Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO6_SR Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO5_SR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO4_SR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO3_SR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO2_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO1_SR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO0_SR Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADSRCFG3 (IO_CKGEN_BASE + 0x53C)
    #define FLD_DTMB3_SR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DTMB2_SR Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_DTMB1_SR Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_EEPROM_SR Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO66_SR Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO65_SR Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO64_SR Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO63_SR Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO62_SR Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO61_SR Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO55_SR Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO52_53_54_SR Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO51_SR Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO50_SR Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO49_SR Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO48_SR Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO47_SR Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO46_SR Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO45_SR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO44_SR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO43_SR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO42_SR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO41_SR Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO40_SR Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO39_SR Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO38_SR Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO37_SR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO36_SR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO35_SR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO34_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO33_SR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO32_SR Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE2_0 (IO_CKGEN_BASE + 0x540)
    #define FLD_AOSDATA1_E2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_AOSDATA0_E2 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_AOBCK_E2 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_AOLRCK_E2 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_AOMCLK_E2 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ASPDIF1_E2 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ASPDIF0_E2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_ALIN_E2 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_OSD1_E2 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD0_E2 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_UART1_E2 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO72_E2 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO71_E2 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO70_E2 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO69_E2 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO68_E2 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO67_E2 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_OPWM2_E2 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_OPWM1_E2 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_OPWM0_E2 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO60_E2 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO59_E2 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO58_E2 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO57_E2 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO56_E2 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_EMMC_RST_E2 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PARB_E2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_POCE1_E2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PDD1_E2 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDD0_E2 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_POOE_E2 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCE0_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE2_1 (IO_CKGEN_BASE + 0x544)
    #define FLD_CI_INT_E2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DEMOD_RST_E2 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SPI_CLE_E2 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SPI_DATA_E2 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPI_CLK1_E2 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPI_CLK_E2 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_PVR_TSDATA1_E2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_PVR_TSDATA0_E2 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_PVR_TSSYNC_E2 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_PVR_TSVAL_E2 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_PVR_TSCLK_E2 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_TSDATA0_E2 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSSYNC_E2 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSVAL_E2 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSCLK_E2 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DEMOD_TSDATA7_E2 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMOD_TSDATA6_E2 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMOD_TSDATA5_E2 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DEMOD_TSDATA4_E2 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DEMOD_TSDATA3_E2 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_DEMOD_TSDATA2_E2 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_DEMOD_TSDATA1_E2 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DEMOD_TSDATA0_E2 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DEMOD_TSSYNC_E2 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEMOD_TSVAL_E2 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_TSCLK_E2 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OS2_E2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RF_AGC_E2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_IF_AGC_E2 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_AOSDATA4_E2 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_AOSDATA3_E2 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_AOSDATA2_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE2_2 (IO_CKGEN_BASE + 0x548)
    #define FLD_GPIO31_E2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO30_E2 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO29_E2 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO28_E2 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO27_E2 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO26_E2 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO25_E2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO24_E2 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO23_E2 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO22_E2 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO21_E2 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO20_E2 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO19_E2 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO18_E2 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO17_E2 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO16_E2 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO15_E2 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO14_E2 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO13_E2 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO12_E2 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO11_E2 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO10_E2 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO9_E2 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO8_E2 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO7_E2 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO6_E2 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO5_E2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO4_E2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO3_E2 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO2_E2 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO1_E2 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO0_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE2_3 (IO_CKGEN_BASE + 0x54C)
    #define FLD_DTMB_CLK_E2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EEPROM_E2 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO66_E2 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO65_E2 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO64_E2 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO63_E2 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO62_E2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO61_E2 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO55_E2 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO54_E2 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO53_E2 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO52_E2 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO51_E2 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO50_E2 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO49_E2 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO48_E2 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO47_E2 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO46_E2 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO45_E2 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO44_E2 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO43_E2 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO42_E2 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO41_E2 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO40_E2 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO39_E2 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO38_E2 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO37_E2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO36_E2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO35_E2 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO34_E2 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO33_E2 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO32_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE4_0 (IO_CKGEN_BASE + 0x550)
    #define FLD_AOSDATA1_E4 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_AOSDATA0_E4 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_AOBCK_E4 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_AOLRCK_E4 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_AOMCLK_E4 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ASPDIF1_E4 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ASPDIF0_E4 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_ALIN_E4 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_OSD1_E4 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_OSD0_E4 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_UART1_E4 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO72_E4 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO71_E4 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO70_E4 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO69_E4 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO68_E4 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO67_E4 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_OPWM2_E4 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_OPWM1_E4 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_OPWM0_E4 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO60_E4 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO59_E4 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO58_E4 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO57_E4 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO56_E4 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_EMMC_RST_E4 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_PARB_E4 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_POCE1_E4 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PDD1_E4 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDD0_E4 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_POOE_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_POCE0_E4 Fld(1,0,AC_MSKB0)//[0:0]
        #define PADDRV_2MA 0
        #define PADDRV_4MA 1
        #define PADDRV_6MA 2
        #define PADDRV_8MA 3
#define CKGEN_REG_PADE4_1 (IO_CKGEN_BASE + 0x554)
    #define FLD_CI_INT_E4 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DEMOD_RST_E4 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SPI_CLE_E4 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SPI_DATA_E4 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SPI_CLK1_E4 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SPI_CLK_E4 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_PVR_TSDATA1_E4 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_PVR_TSDATA0_E4 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_PVR_TSSYNC_E4 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_PVR_TSVAL_E4 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_PVR_TSCLK_E4 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_CI_TSDATA0_E4 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_CI_TSSYNC_E4 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_CI_TSVAL_E4 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_CI_TSCLK_E4 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DEMOD_TSDATA7_E4 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DEMOD_TSDATA6_E4 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_DEMOD_TSDATA5_E4 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DEMOD_TSDATA4_E4 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DEMOD_TSDATA3_E4 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_DEMOD_TSDATA2_E4 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_DEMOD_TSDATA1_E4 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_DEMOD_TSDATA0_E4 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DEMOD_TSSYNC_E4 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEMOD_TSVAL_E4 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DEMOD_TSCLK_E4 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OS2_E4 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RF_AGC_E4 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_IF_AGC_E4 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_AOSDATA4_E4 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_AOSDATA3_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_AOSDATA2_E4 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE4_2 (IO_CKGEN_BASE + 0x558)
    #define FLD_GPIO31_E4 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO30_E4 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO29_E4 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO28_E4 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO27_E4 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO26_E4 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO25_E4 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO24_E4 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO23_E4 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO22_E4 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO21_E4 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO20_E4 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO19_E4 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO18_E4 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO17_E4 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO16_E4 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO15_E4 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO14_E4 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO13_E4 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO12_E4 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO11_E4 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO10_E4 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO9_E4 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO8_E4 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO7_E4 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO6_E4 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO5_E4 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO4_E4 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO3_E4 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO2_E4 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO1_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO0_E4 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE4_3 (IO_CKGEN_BASE + 0x55C)
    #define FLD_DTMB_CLK_E4 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EEPROM_E4 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_GPIO66_E4 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_GPIO65_E4 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_GPIO64_E4 Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_GPIO63_E4 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_GPIO62_E4 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GPIO61_E4 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPIO55_E4 Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPIO54_E4 Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPIO53_E4 Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPIO52_E4 Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPIO51_E4 Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPIO50_E4 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_GPIO49_E4 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPIO48_E4 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPIO47_E4 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPIO46_E4 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPIO45_E4 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_GPIO44_E4 Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPIO43_E4 Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_GPIO42_E4 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_GPIO41_E4 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPIO40_E4 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPIO39_E4 Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_GPIO38_E4 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_GPIO37_E4 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPIO36_E4 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPIO35_E4 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_GPIO34_E4 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_GPIO33_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPIO32_E4 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADRDSEL0 (IO_CKGEN_BASE + 0x560)
    #define FLD_PADRDSEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADRDSEL1 (IO_CKGEN_BASE + 0x564)
    #define FLD_PADRDSEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADRDSEL2 (IO_CKGEN_BASE + 0x568)
    #define FLD_PADRDSEL2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL0 (IO_CKGEN_BASE + 0x56C)
    #define FLD_PADTDSEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL1 (IO_CKGEN_BASE + 0x570)
    #define FLD_PADTDSEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL2 (IO_CKGEN_BASE + 0x574)
    #define FLD_PADTDSEL2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL3 (IO_CKGEN_BASE + 0x578)
    #define FLD_PADTDSEL3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL4 (IO_CKGEN_BASE + 0x57C)
    #define FLD_PADTDSEL4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MONASEL (IO_CKGEN_BASE + 0x580)
    #define FLD_MONA Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MONBSEL (IO_CKGEN_BASE + 0x584)
    #define FLD_MONB Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL5 (IO_CKGEN_BASE + 0x588)
    #define FLD_PADTDSEL5 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL6 (IO_CKGEN_BASE + 0x58C)
    #define FLD_PADTDSEL6 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_TOP_BACKUP0 (IO_CKGEN_BASE + 0x5A0)
    #define FLD_DA_CCC_GPIO_SR Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_DA_CCC_GPIO_G Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_R_DMAGSEL_UART1 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_R_DMBYP_SYNC Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_TOP_BACKUP1 (IO_CKGEN_BASE + 0x5A4)
    #define FLD_USB3CHB_R_DMAG2TIM Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_USB2CHB_R_DMAG1TIM Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_ABTB_R_DMAG0TIM Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_USB3CHA_R_DMAG2TIM Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_USB2CHA_R_DMAG1TIM Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_ABTA_R_DMAG0TIM Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_USB3CHB_R_DMAG2EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_USB2CHB_R_DMAG1EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_ABTB_R_DMAG0EN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_USB3CHA_R_DMAG2EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_USB2CHA_R_DMAG1EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_ABTA_R_DMAG0EN Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_TOP_BACKUP2 (IO_CKGEN_BASE + 0x5A8)
    #define FLD_SSUSB_XHCI_SLEEPB Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_SSUSB_XHCI_PD Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_ABTB_R_DMARBTST Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_ABTB_R_DMTIMARBEN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_ABTA_R_DMARBTST Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_ABTA_R_DMTIMARBEN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_USB3CHB_R_DMFMREQEN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_USB3CHA_R_DMFMREQEN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_USB2CHB_R_DMFMREQEN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_USB2CHA_R_DMFMREQEN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SSUSB_MBIST_CK_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_USB3_MBIST_CKMUX Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SSUSB_I2C_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_TOP_BACKUP3 (IO_CKGEN_BASE + 0x5AC)
    #define FLD_R_DMAGSEL_USB3 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_R_DMMONSEL Fld(4,26,AC_MSKB3)//[29:26]
    #define FLD_R_DMAGSEL_USB2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_R_DMARBRST Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_R_DMTIMARBEN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_R_DMAGBMALL Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_R_DMAGBMAGID Fld(3,17,AC_MSKB2)//[19:17]
    #define FLD_R_DMAGBMEND Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_R_DMAGBMBEG Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_R_DMAG2TIM Fld(4,11,AC_MSKB1)//[14:11]
    #define FLD_R_DMAG1TIM Fld(4,7,AC_MSKW10)//[10:7]
    #define FLD_R_DMAG0TIM Fld(4,3,AC_MSKB0)//[6:3]
    #define FLD_R_DMAG2EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_R_DMAG1EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_R_DMAG0EN Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_G3D_CFG0 (IO_CKGEN_BASE + 0x5B0)
    #define FLD_G3D_MEM_PD Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_G3D_CFG1 (IO_CKGEN_BASE + 0x5B4)
    #define FLD_MFG_PWR_MEM_ACK Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_G3D_PWR_ACK_0 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_G3D_PWR_ACK_1 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_G3D_TOP_ISO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_G3D_PWR_ON_1 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_G3D_PWR_ON_0 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_DRAMC_DEBUG_SEL0 (IO_CKGEN_BASE + 0x5B8)
    #define FLD_DRAMC_DEBUG_SEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_DRAMC_DEBUG_SEL1 (IO_CKGEN_BASE + 0x5BC)
    #define FLD_DRAMC_DEBUG_SEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_DRAMCB_DEBUG_SEL0 (IO_CKGEN_BASE + 0x5C0)
    #define FLD_DRAMCB_DEBUG_SEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_DRAMCB_DEBUG_SEL1 (IO_CKGEN_BASE + 0x5C4)
    #define FLD_DRAMCB_DEBUG_SEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_DRAMCC_DEBUG_SEL0 (IO_CKGEN_BASE + 0x5C8)
    #define FLD_DRAMCC_DEBUG_SEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_DRAMCC_DEBUG_SEL1 (IO_CKGEN_BASE + 0x5CC)
    #define FLD_DRAMCC_DEBUG_SEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_TOP_BACKUP4 (IO_CKGEN_BASE + 0x5D0)
    #define FLD_PTP_SW_RSTB Fld(1,14,AC_MSKB1)//[14:14]
#define CKGEN_ANA_PLLGP_CFG0 (IO_CKGEN_BASE + 0x5E0)
    #define FLD_ANA_PLLPG_CFG0 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_ANA_HPCPLL_SDM_PCW_CHG Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_ANA_HPCPLL_SDM_PCW Fld(31,0,AC_MSKDW)//[30:0]
    #define FLD_ANA_HPCPLL_SDM_PCW_INTEGER Fld(7,24,AC_MSKDW)//[30:24]
#define CKGEN_ANA_PLLGP_CFG1 (IO_CKGEN_BASE + 0x5E4)
    #define FLD_ANA_PLLPG_CFG1 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_DA_LPCPLL_SDM_ISO_EN Fld(1,17,AC_MSKDW)//[17:17]
    #define FLD_DA_LPCPLL_SDM_PWR_ON Fld(1,16,AC_MSKDW)//[16:16]
    #define FLD_DA_HPCPLL_SDM_ISO_EN Fld(1,15,AC_MSKDW)//[15:15]
    #define FLD_DA_HPCPLL_SDM_PWR_ON Fld(1,14,AC_MSKDW)//[14:14]
    #define FLD_DA_ARMPLL_SDM_ISO_EN Fld(1,13,AC_MSKDW)//[13:13]
    #define FLD_DA_ARMPLL_SDM_PWR_ON Fld(1,12,AC_MSKDW)//[12:12]
    #define FLD_DA_VGAPLL_SDM_ISO_EN Fld(1,11,AC_MSKDW)//[11:11]
    #define FLD_DA_VGAPLL_SDM_PWR_ON Fld(1,10,AC_MSKDW)//[10:10]
    #define FLD_DA_VDECPLL_SDM_ISO_EN Fld(1,9,AC_MSKDW)//[9:9]
    #define FLD_DA_VDECPLL_SDM_PWR_ON Fld(1,8,AC_MSKDW)//[8:8]
    #define FLD_DA_SYSPLL_SDM_ISO_EN Fld(1,7,AC_MSKDW)//[7:7]
    #define FLD_DA_SYSPLL_SDM_PWR_ON Fld(1,6,AC_MSKDW)//[6:6]
    #define FLD_DA_G3DPLL_SDM_ISO_EN Fld(1,5,AC_MSKDW)//[5:5]
    #define FLD_DA_G3DPLL_SDM_PWR_ON Fld(1,4,AC_MSKDW)//[4:4]
    #define FLD_DA_DMUXPLL_SDM_ISO_EN Fld(1,3,AC_MSKDW)//[3:3]
    #define FLD_DA_DMUXPLL_SDM_PWR_ON Fld(1,2,AC_MSKDW)//[2:2]
    #define FLD_DA_APPL2_SDM_ISO_EN Fld(1,1,AC_MSKDW)//[1:1]
    #define FLD_DA_APLL2_SDM_PWR_ON Fld(1,0,AC_MSKDW)//[0:0]
#define CKGEN_ANA_PLLGP_CFG2 (IO_CKGEN_BASE + 0x5E8)
    #define FLD_ANA_PLLPG_CFG2 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_ANA_HPCPLL_SDM_PWC_AUTO_STEP Fld(24,8,AC_MSKDW)//[31:8]    
    #define FLD_ANA_HPCPLL_SDM_PWC_AUTO_STATUS Fld(3,2,AC_MSKB0)//[4:2]
    #define FLD_ANA_HPCPLL_SDM_PWC_AUTO_START Fld(1,1,AC_MSKB0)//[1:1]    
    #define FLD_ANA_HPCPLL_SDM_PWC_AUTO_EN Fld(1,0,AC_MSKB0)//[0:0]    
#define CKGEN_ANA_PLLGP_CFG3 (IO_CKGEN_BASE + 0x5EC)
    #define FLD_ANA_PLLPG_CFG3 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_ANA_HPCPLL_SDM_PCW_AUTO_TARGET Fld(31,0,AC_MSKDW)//[30:0]    
    #define FLD_ANA_HPCPLL_SDM_PCW_TARGET_INTEGER Fld(7,24,AC_MSKDW)//[30:24]
#define CKGEN_REG_MJC_CFG0 (IO_CKGEN_BASE + 0x5F0)
    #define FLD_REG_MJC_TOP_SYS_ISO_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_REG_MJC_TOP_SYS_PWR_ON Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_REG_MJC_TOP_SYS_PWR_ON_S Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_REG_MJC_TOP_PWR_ON_RST_B Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_REG_MJC_TOP_PWR_CLK_DIS Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PMUX0 (IO_CKGEN_BASE + 0x600)
    #define FLD_PMUX0 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_PAD_ASPDIF1 Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_PAD_ASPDIF0 Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_PAD_AOLRCK Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_PAD_AOBCK Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_PAD_AOSDATA0 Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_PAD_GPIO56 Fld(3, 0, AC_MSKB0) // [2:0] 
#define CKGEN_PMUX1 (IO_CKGEN_BASE + 0x604)
    #define FLD_PMUX1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PMUX2 (IO_CKGEN_BASE + 0x608)
    #define FLD_PMUX2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PMUX3 (IO_CKGEN_BASE + 0x60C)
    #define FLD_PMUX3 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_PAD_GPIO50 Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_PAD_AOSDATA1 Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_PAD_AOSDATA2 Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_PAD_AOSDATA3 Fld(3,20,AC_MSKB2)//[22:20]
#define CKGEN_PMUX4 (IO_CKGEN_BASE + 0x610)
    #define FLD_PMUX4 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_PAD_GPIO60 Fld(3, 28, AC_MSKB3) // [30:28]
    #define FLD_PAD_GPIO59 Fld(3, 24, AC_MSKB3) // [26:24]
    #define FLD_PAD_GPIO58 Fld(3, 20, AC_MSKB2) // [22:20]
    #define FLD_PAD_GPIO57 Fld(3, 16, AC_MSKB2) // [18:16]
    #define FLD_PAD_GPIO53 Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_PAD_GPIO52 Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_PAD_GPIO55 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PAD_GPIO51 Fld(3,0,AC_MSKB0)//[2:0]        
#define CKGEN_PMUX5 (IO_CKGEN_BASE + 0x614)
    #define FLD_PMUX5 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PMUX_MISC (IO_CKGEN_BASE + 0x620)
    #define FLD_OCLK_27M_HDMI Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_PLL_XCLK_SEL Fld(1,3,AC_MSKB0)//[3:3]
#define CKGEN_PMUX6 (IO_CKGEN_BASE + 0x624)
    #define FLD_PMUX6 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PMUX7 (IO_CKGEN_BASE + 0x628)
    #define FLD_PMUX7 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PMUX8 (IO_CKGEN_BASE + 0x62C)
    #define FLD_PMUX8 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_REG_PADE2_4 (IO_CKGEN_BASE + 0x660)
    #define FLD_DTMB_TSDATA0_E2 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DTMB_TSSYNC_E2 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DTMB_TSVAL_E2 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DTMB_TSCLK_E2 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_DTMB_E2 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_DTMB_PWM_E2 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_DTMB_RST_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_REG_PADE4_4 (IO_CKGEN_BASE + 0x664)
    #define FLD_DTMB_TSDATA0_E4 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_DTMB_TSSYNC_E4 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DTMB_TSVAL_E4 Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DTMB_TSCLK_E4 Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_DTMB_E4 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_DTMB_PWM_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_DTMB_RST_E4 Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_PADRDSEL3 (IO_CKGEN_BASE + 0x668)
    #define FLD_PADRDSEL3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADRDSEL4 (IO_CKGEN_BASE + 0x66C)
    #define FLD_PADRDSEL4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADRDSEL5 (IO_CKGEN_BASE + 0x670)
    #define FLD_PADRDSEL5 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADRDSEL6 (IO_CKGEN_BASE + 0x674)
    #define FLD_PADRDSEL6 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADRDSEL7 (IO_CKGEN_BASE + 0x678)
    #define FLD_PADRDSEL7 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL7 (IO_CKGEN_BASE + 0x67C)
    #define FLD_PADTDSEL7 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL8 (IO_CKGEN_BASE + 0x680)
    #define FLD_PADTDSEL8 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL9 (IO_CKGEN_BASE + 0x684)
    #define FLD_PADTDSEL9 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL10 (IO_CKGEN_BASE + 0x688)
    #define FLD_PADTDSEL10 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL11 (IO_CKGEN_BASE + 0x68C)
    #define FLD_PADTDSEL11 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL12 (IO_CKGEN_BASE + 0x690)
    #define FLD_PADTDSEL12 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL13 (IO_CKGEN_BASE + 0x694)
    #define FLD_PADTDSEL13 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL14 (IO_CKGEN_BASE + 0x698)
    #define FLD_PADTDSEL14 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_PADTDSEL15 (IO_CKGEN_BASE + 0x69C)
    #define FLD_PADTDSEL15 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOOUT0 (IO_CKGEN_BASE + 0x700)
    #define FLD_GPIO_OUT0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOOUT1 (IO_CKGEN_BASE + 0x704)
    #define FLD_GPIO_OUT1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOOUT2 (IO_CKGEN_BASE + 0x708)
    #define FLD_GPIO_OUT2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOOUT3 (IO_CKGEN_BASE + 0x70C)
    #define FLD_GPIO_OUT3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOOUT4 (IO_CKGEN_BASE + 0x710)
    #define FLD_GPIO_OUT4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOOUT5 (IO_CKGEN_BASE + 0x714)
    #define FLD_GPIO_OUT5 Fld(24,0,AC_MSKDW)//[23:0]
#define CKGEN_GPIOEN0 (IO_CKGEN_BASE + 0x720)
    #define FLD_GPIO_EN0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOEN1 (IO_CKGEN_BASE + 0x724)
    #define FLD_GPIO_EN1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOEN2 (IO_CKGEN_BASE + 0x728)
    #define FLD_GPIO_EN2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOEN3 (IO_CKGEN_BASE + 0x72C)
    #define FLD_GPIO_EN3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOEN4 (IO_CKGEN_BASE + 0x730)
    #define FLD_GPIO_EN4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOEN5 (IO_CKGEN_BASE + 0x734)
    #define FLD_GPIO_EN5 Fld(24,0,AC_MSKDW)//[23:0]
#define CKGEN_GPIOIN0 (IO_CKGEN_BASE + 0x740)
    #define FLD_GPIO_IN0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOIN1 (IO_CKGEN_BASE + 0x744)
    #define FLD_GPIO_IN1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOIN2 (IO_CKGEN_BASE + 0x748)
    #define FLD_GPIO_IN2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOIN3 (IO_CKGEN_BASE + 0x74C)
    #define FLD_GPIO_IN3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOIN4 (IO_CKGEN_BASE + 0x750)
    #define FLD_GPIO_IN4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_GPIOIN5 (IO_CKGEN_BASE + 0x754)
    #define FLD_GPIO_IN5 Fld(24,0,AC_MSKDW)//[23:0]
#define CKGEN_ED2INTEN0 (IO_CKGEN_BASE + 0x760)
    #define FLD_ED2INTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ED2INTEN1 (IO_CKGEN_BASE + 0x764)
    #define FLD_ED2INTEN1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ED2INTEN2 (IO_CKGEN_BASE + 0x768)
    #define FLD_ED2INTEN2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_LEVINTEN0 (IO_CKGEN_BASE + 0x76C)
    #define FLD_LEVINTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_LEVINTEN1 (IO_CKGEN_BASE + 0x770)
    #define FLD_LEVINTEN1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_LEVINTEN2 (IO_CKGEN_BASE + 0x774)
    #define FLD_LEVINTEN2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ENTPOL0 (IO_CKGEN_BASE + 0x778)
    #define FLD_INTPOL0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ENTPOL1 (IO_CKGEN_BASE + 0x77C)
    #define FLD_INTPOL1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ENTPOL2 (IO_CKGEN_BASE + 0x780)
    #define FLD_INTPOL2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN0 (IO_CKGEN_BASE + 0x784)
    #define FLD_INTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN1 (IO_CKGEN_BASE + 0x788)
    #define FLD_INTEN1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN2 (IO_CKGEN_BASE + 0x78C)
    #define FLD_INTEN2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT0 (IO_CKGEN_BASE + 0x790)
    #define FLD_EXTINT0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT1 (IO_CKGEN_BASE + 0x794)
    #define FLD_EXTINT1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT2 (IO_CKGEN_BASE + 0x798)
    #define FLD_EXTINT2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ED2INTEN3 (IO_CKGEN_BASE + 0x79C)
    #define FLD_ED2INTEN3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ED2INTEN4 (IO_CKGEN_BASE + 0x7A0)
    #define FLD_ED2INTEN4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_LEVINTEN3 (IO_CKGEN_BASE + 0x7A4)
    #define FLD_LEVINTEN3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_LEVINTEN4 (IO_CKGEN_BASE + 0x7A8)
    #define FLD_LEVINTEN4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_ENTPOL3 (IO_CKGEN_BASE + 0x7AC)
    #define FLD_INTPOL3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_ENTPOL4 (IO_CKGEN_BASE + 0x7B0)
    #define FLD_INTPOL4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_EXTINTEN3 (IO_CKGEN_BASE + 0x7B4)
    #define FLD_INTEN3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN4 (IO_CKGEN_BASE + 0x7B8)
    #define FLD_INTEN4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_EXTINT3 (IO_CKGEN_BASE + 0x7BC)
    #define FLD_EXTINT3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT4 (IO_CKGEN_BASE + 0x7C0)
    #define FLD_EXTINT4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_EXTINTEN0_FIQ (IO_CKGEN_BASE + 0x7C4)
    #define FLD_INTEN_FIQ0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN1_FIQ (IO_CKGEN_BASE + 0x7C8)
    #define FLD_INTEN_FIQ1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN2_FIQ (IO_CKGEN_BASE + 0x7CC)
    #define FLD_INTEN_FIQ2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN3_FIQ (IO_CKGEN_BASE + 0x7D0)
    #define FLD_INTEN_FIQ3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINTEN4_FIQ (IO_CKGEN_BASE + 0x7D4)
    #define FLD_INTEN_FIQ4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_EXTINT0_FIQ (IO_CKGEN_BASE + 0x7D8)
    #define FLD_EXTINT_FIQ0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT1_FIQ (IO_CKGEN_BASE + 0x7DC)
    #define FLD_EXTINT_FIQ1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT2_FIQ (IO_CKGEN_BASE + 0x7E0)
    #define FLD_EXTINT_FIQ2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT3_FIQ (IO_CKGEN_BASE + 0x7E4)
    #define FLD_EXTINT_FIQ3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_EXTINT4_FIQ (IO_CKGEN_BASE + 0x7E8)
    #define FLD_EXTINT_FIQ4 Fld(19,0,AC_MSKDW)//[18:0]
#define CKGEN_MBIST_CTRL (IO_CKGEN_BASE + 0x800)
    #define FLD_PAD_MBIST_FAIL Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_PAD_MBIST_DONE Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_L2C_MBIST_FAIL Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_L2C_MBIST_DONE Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_CA9_MBIST_FAIL Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_CA9_MBIST_DONE Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_MJC_SA_DELSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_MBIST_MON_SEL Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_PAD_DONE_CLEAR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_PAD_FAIL_CLEAR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_PAD_DONE_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_PAD_FAIL_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_L2C_MBIST_ON Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_L2C_MBIST_MODE Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CA9_MBIST_ON Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_CA9_MBIST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_MBIST_DEBUG_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_MBIST_HOLDB Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_MBIST_BKGND_SEL Fld(2,1,AC_MSKB0)//[2:1]
    #define FLD_MBIST_RSTB Fld(1,0,AC_MSKB0)//[0:0]
#define CKGEN_MBIST_BGSEL (IO_CKGEN_BASE + 0x804)
    #define FLD_MBIST_BACKGROUND Fld(16,0,AC_FULLW10)//[15:0]
#define CKGEN_MBIST_EN0 (IO_CKGEN_BASE + 0x810)
    #define FLD_MBIST_MODE0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN1 (IO_CKGEN_BASE + 0x814)
    #define FLD_MBIST_MODE1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN2 (IO_CKGEN_BASE + 0x818)
    #define FLD_MBIST_MODE2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN3 (IO_CKGEN_BASE + 0x81C)
    #define FLD_MBIST_MODE3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN4 (IO_CKGEN_BASE + 0x820)
    #define FLD_MBIST_MODE4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN5 (IO_CKGEN_BASE + 0x824)
    #define FLD_MBIST_MODE5 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN6 (IO_CKGEN_BASE + 0x828)
    #define FLD_MBIST_MODE6 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN7 (IO_CKGEN_BASE + 0x82C)
    #define FLD_MBIST_MODE7 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN8 (IO_CKGEN_BASE + 0x830)
    #define FLD_MBIST_MODE8 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN9 (IO_CKGEN_BASE + 0x834)
    #define FLD_MBIST_MODE9 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN10 (IO_CKGEN_BASE + 0x838)
    #define FLD_MBIST_MODE10 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN11 (IO_CKGEN_BASE + 0x83C)
    #define FLD_MBIST_MODE11 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN12 (IO_CKGEN_BASE + 0x840)
    #define FLD_MBIST_MODE12 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN13 (IO_CKGEN_BASE + 0x844)
    #define FLD_MBIST_MODE13 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN14 (IO_CKGEN_BASE + 0x848)
    #define FLD_MBIST_MODE14 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_EN15 (IO_CKGEN_BASE + 0x84C)
    #define FLD_MBIST_MODE15 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_DELSEL2 (IO_CKGEN_BASE + 0x8B0)
    #define FLD_SPB64M4R_DELSEL Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_SPB2562R_LE_DELSEL Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_SPB2562R_BG_DELSEL Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_SPB512M4RIN_DELSEL Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_SPB512M8RIN_DELSEL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_SPB64M4RIN_DELSEL Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_SPB256M2RIN_LE_DELSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_SPB256M2RIN_BG_DELSEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_MBIST_DELSEL3 (IO_CKGEN_BASE + 0x8B4)
    #define FLD_SPB512M4RRIYN_DELSEL Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_SPB2562RYMN_DELSEL Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_SPB512M4RYN_DELSEL Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_SPB64M4RYN_DELSEL Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_SPB256M2RYN_LE_DELSEL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_TXMHRS_DELSEL Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_TXMRHTD_M1_DELSEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_TXMRHTD_M2_DELSEL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_TXMHRTD_DELSEL Fld(2,2,AC_MSKB0)//[3:2]
#define CKGEN_MBIST_DELSEL (IO_CKGEN_BASE + 0x8BC)
    #define FLD_TXMRHSD_DELSEL Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_TXMRHSIN_DELSEL Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_TXMRVD_LE4K_DELSEL Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_TXMRVD_BG4K_DELSEL Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_RVPB512M16_DELSEL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_SPB512M4R_DELSEL Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_SPB512M8R_DELSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_SPB512M16R_DELSEL Fld(4,0,AC_MSKB0)//[3:0]
#define CKGEN_MBIST_MON0 (IO_CKGEN_BASE + 0x8C0)
    #define FLD_MBIST_MON0 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON1 (IO_CKGEN_BASE + 0x8C4)
    #define FLD_MBIST_MON1 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON2 (IO_CKGEN_BASE + 0x8C8)
    #define FLD_MBIST_MON2 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON3 (IO_CKGEN_BASE + 0x8CC)
    #define FLD_MBIST_MON3 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON4 (IO_CKGEN_BASE + 0x8D0)
    #define FLD_MBIST_MON4 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON5 (IO_CKGEN_BASE + 0x8D4)
    #define FLD_MBIST_MON5 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON6 (IO_CKGEN_BASE + 0x8D8)
    #define FLD_MBIST_MON6 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON7 (IO_CKGEN_BASE + 0x8DC)
    #define FLD_MBIST_MON7 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON8 (IO_CKGEN_BASE + 0x8E0)
    #define FLD_MBIST_MON8 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON9 (IO_CKGEN_BASE + 0x8E4)
    #define FLD_MBIST_MON9 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON10 (IO_CKGEN_BASE + 0x8E8)
    #define FLD_MBIST_MON10 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON11 (IO_CKGEN_BASE + 0x8EC)
    #define FLD_MBIST_MON11 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON12 (IO_CKGEN_BASE + 0x8F0)
    #define FLD_MBIST_MON12 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON13 (IO_CKGEN_BASE + 0x8F4)
    #define FLD_MBIST_MON13 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON14 (IO_CKGEN_BASE + 0x8F8)
    #define FLD_MBIST_MON14 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON15 (IO_CKGEN_BASE + 0x8FC)
    #define FLD_MBIST_MON15 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON16 (IO_CKGEN_BASE + 0x900)
    #define FLD_MBIST_MON16 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON17 (IO_CKGEN_BASE + 0x904)
    #define FLD_MBIST_MON17 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON18 (IO_CKGEN_BASE + 0x908)
    #define FLD_MBIST_MON18 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON19 (IO_CKGEN_BASE + 0x90C)
    #define FLD_MBIST_MON19 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON20 (IO_CKGEN_BASE + 0x910)
    #define FLD_MBIST_MON20 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON21 (IO_CKGEN_BASE + 0x914)
    #define FLD_MBIST_MON21 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON22 (IO_CKGEN_BASE + 0x918)
    #define FLD_MBIST_MON22 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON23 (IO_CKGEN_BASE + 0x91C)
    #define FLD_MBIST_MON23 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON24 (IO_CKGEN_BASE + 0x920)
    #define FLD_MBIST_MON24 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON25 (IO_CKGEN_BASE + 0x924)
    #define FLD_MBIST_MON25 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON26 (IO_CKGEN_BASE + 0x928)
    #define FLD_MBIST_MON26 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON27 (IO_CKGEN_BASE + 0x92C)
    #define FLD_MBIST_MON27 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON28 (IO_CKGEN_BASE + 0x930)
    #define FLD_MBIST_MON28 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON29 (IO_CKGEN_BASE + 0x934)
    #define FLD_MBIST_MON29 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON30 (IO_CKGEN_BASE + 0x938)
    #define FLD_MBIST_MON30 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON31 (IO_CKGEN_BASE + 0x93C)
    #define FLD_MBIST_MON31 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON32 (IO_CKGEN_BASE + 0x940)
    #define FLD_MBIST_MON32 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON33 (IO_CKGEN_BASE + 0x944)
    #define FLD_MBIST_MON33 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON34 (IO_CKGEN_BASE + 0x948)
    #define FLD_MBIST_MON34 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON35 (IO_CKGEN_BASE + 0x94C)
    #define FLD_MBIST_MON35 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON36 (IO_CKGEN_BASE + 0x950)
    #define FLD_MBIST_MON36 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON37 (IO_CKGEN_BASE + 0x954)
    #define FLD_MBIST_MON37 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON38 (IO_CKGEN_BASE + 0x958)
    #define FLD_MBIST_MON38 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON39 (IO_CKGEN_BASE + 0x95C)
    #define FLD_MBIST_MON39 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON40 (IO_CKGEN_BASE + 0x960)
    #define FLD_MBIST_MON40 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON41 (IO_CKGEN_BASE + 0x964)
    #define FLD_MBIST_MON41 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON42 (IO_CKGEN_BASE + 0x968)
    #define FLD_MBIST_MON42 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON43 (IO_CKGEN_BASE + 0x96C)
    #define FLD_MBIST_MON43 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON44 (IO_CKGEN_BASE + 0x970)
    #define FLD_MBIST_MON44 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON45 (IO_CKGEN_BASE + 0x974)
    #define FLD_MBIST_MON45 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON46 (IO_CKGEN_BASE + 0x978)
    #define FLD_MBIST_MON46 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON47 (IO_CKGEN_BASE + 0x97C)
    #define FLD_MBIST_MON47 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON48 (IO_CKGEN_BASE + 0x980)
    #define FLD_MBIST_MON48 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON49 (IO_CKGEN_BASE + 0x984)
    #define FLD_MBIST_MON49 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON50 (IO_CKGEN_BASE + 0x988)
    #define FLD_MBIST_MON50 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON51 (IO_CKGEN_BASE + 0x98C)
    #define FLD_MBIST_MON51 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON52 (IO_CKGEN_BASE + 0x990)
    #define FLD_MBIST_MON52 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON53 (IO_CKGEN_BASE + 0x994)
    #define FLD_MBIST_MON53 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON54 (IO_CKGEN_BASE + 0x998)
    #define FLD_MBIST_MON54 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON55 (IO_CKGEN_BASE + 0x99C)
    #define FLD_MBIST_MON55 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON56 (IO_CKGEN_BASE + 0x9A0)
    #define FLD_MBIST_MON56 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON57 (IO_CKGEN_BASE + 0x9A4)
    #define FLD_MBIST_MON57 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON58 (IO_CKGEN_BASE + 0x9A8)
    #define FLD_MBIST_MON58 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON59 (IO_CKGEN_BASE + 0x9AC)
    #define FLD_MBIST_MON59 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON60 (IO_CKGEN_BASE + 0x9B0)
    #define FLD_MBIST_MON60 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON61 (IO_CKGEN_BASE + 0x9B4)
    #define FLD_MBIST_MON61 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON62 (IO_CKGEN_BASE + 0x9B8)
    #define FLD_MBIST_MON62 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON63 (IO_CKGEN_BASE + 0x9BC)
    #define FLD_MBIST_MON63 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON64 (IO_CKGEN_BASE + 0x9C0)
    #define FLD_MBIST_MON64 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON65 (IO_CKGEN_BASE + 0x9C4)
    #define FLD_MBIST_MON65 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON66 (IO_CKGEN_BASE + 0x9C8)
    #define FLD_MBIST_MON66 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON67 (IO_CKGEN_BASE + 0x9CC)
    #define FLD_MBIST_MON67 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON68 (IO_CKGEN_BASE + 0x9D0)
    #define FLD_MBIST_MON68 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON69 (IO_CKGEN_BASE + 0x9D4)
    #define FLD_MBIST_MON69 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON70 (IO_CKGEN_BASE + 0x9D8)
    #define FLD_MBIST_MON70 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON71 (IO_CKGEN_BASE + 0x9DC)
    #define FLD_MBIST_MON71 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON72 (IO_CKGEN_BASE + 0x9E0)
    #define FLD_MBIST_MON72 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON73 (IO_CKGEN_BASE + 0x9E4)
    #define FLD_MBIST_MON73 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON74 (IO_CKGEN_BASE + 0x9E8)
    #define FLD_MBIST_MON74 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON75 (IO_CKGEN_BASE + 0x9EC)
    #define FLD_MBIST_MON75 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON76 (IO_CKGEN_BASE + 0x9F0)
    #define FLD_MBIST_MON76 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON77 (IO_CKGEN_BASE + 0x9F4)
    #define FLD_MBIST_MON77 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON78 (IO_CKGEN_BASE + 0x9F8)
    #define FLD_MBIST_MON78 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON79 (IO_CKGEN_BASE + 0x9FC)
    #define FLD_MBIST_MON79 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON80 (IO_CKGEN_BASE + 0xA00)
    #define FLD_MBIST_MON80 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON81 (IO_CKGEN_BASE + 0xA04)
    #define FLD_MBIST_MON81 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON82 (IO_CKGEN_BASE + 0xA08)
    #define FLD_MBIST_MON82 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON83 (IO_CKGEN_BASE + 0xA0C)
    #define FLD_MBIST_MON83 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON84 (IO_CKGEN_BASE + 0xA10)
    #define FLD_MBIST_MON84 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON85 (IO_CKGEN_BASE + 0xA14)
    #define FLD_MBIST_MON85 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON86 (IO_CKGEN_BASE + 0xA18)
    #define FLD_MBIST_MON86 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON87 (IO_CKGEN_BASE + 0xA1C)
    #define FLD_MBIST_MON87 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON88 (IO_CKGEN_BASE + 0xA20)
    #define FLD_MBIST_MON88 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON89 (IO_CKGEN_BASE + 0xA24)
    #define FLD_MBIST_MON89 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON90 (IO_CKGEN_BASE + 0xA28)
    #define FLD_MBIST_MON90 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON91 (IO_CKGEN_BASE + 0xA2C)
    #define FLD_MBIST_MON91 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON92 (IO_CKGEN_BASE + 0xA30)
    #define FLD_MBIST_MON92 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON93 (IO_CKGEN_BASE + 0xA34)
    #define FLD_MBIST_MON93 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON94 (IO_CKGEN_BASE + 0xA38)
    #define FLD_MBIST_MON94 Fld(32,0,AC_FULLDW)//[31:0]
#define CKGEN_MBIST_MON95 (IO_CKGEN_BASE + 0xA3C)
    #define FLD_MBIST_MON95 Fld(32,0,AC_FULLDW)//[31:0]

#endif /* _HW_CKGEN_H_ */
