/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#ifndef HW_W2DR2R_H_
#define HW_W2DR2R_H_
#include "x_hal_5381.h"

//HDMI down scaler
#define W2D_DATA_SEL (IO_VIRT + 0x22CB8)
    #define W2D1_DATA_SEL_BIT Fld(1,1,AC_MSKB0)
    #define W2D0_DATA_SEL_BIT Fld(1,0,AC_MSKB0)
#define W2D_CLK_SEL (IO_VIRT + 0x22D30)
    #define W2D1_CLK_SEL_BIT Fld(1,3,AC_MSKB0)
    #define W2D0_CLK_SEL_BIT Fld(1,2,AC_MSKB0)
#define HDMI_DS0 (IO_VIRT + 0x22D34)
    #define HDMI_DS0_BYPASS Fld(1,4,AC_MSKB0) //[4:4]
    #define HDMI_DS0_CLOCK_EN Fld(1,1,AC_MSKB0) //[1:1]
    #define HDMI_DS0_RST Fld(1,0,AC_MSKB0) //[0:0]
#define HDMI_DS1 (IO_VIRT + 0x22D38)
    #define HDMI_DS1_BYPASS Fld(1,4,AC_MSKB0) //[4:4]
    #define HDMI_DS1_CLOCK_EN Fld(1,1,AC_MSKB0) //[1:1]
    #define HDMI_DS1_RST Fld(1,0,AC_MSKB0) //[0:0]

//Page W2D
#define W2D_BASE (IO_VIRT + 0x22000)
#define W2D0_VDOIN_ENABLE (W2D_BASE + 0xE00)
    #define W2D0_VDOIN_ENABLE_BG422MODE Fld(1,25,AC_MSKB3)//[25:25]
    #define W2D0_VDOIN_ENABLE_MTKDATA_ENA Fld(1,21,AC_MSKB2)//[21:21]
    #define W2D0_VDOIN_ENABLE_SD_480I_MIX Fld(1,11,AC_MSKB1)//[11:11]
    #define W2D0_VDOIN_ENABLE_BGENVSYNC601INV Fld(1,10,AC_MSKB1)//[10:10]
    #define W2D0_VDOIN_ENABLE_FRAME_END_NEW_CFG Fld(2,8,AC_MSKB1)//[9:8]
    #define W2D0_VDOIN_ENABLE_BURST4_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define W2D0_VDOIN_ENABLE_BGENEXTEAV Fld(1,6,AC_MSKB0)//[6:6]
    #define W2D0_VDOIN_ENABLE_VDOINDATA_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define W2D0_VDOIN_ENABLE_SRAM_ENA_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define W2D0_VDOIN_ENABLE_PRGS Fld(1,3,AC_MSKB0)//[3:3]
    #define W2D0_VDOIN_ENABLE_BGVDOFORMAT Fld(1,2,AC_MSKB0)//[2:2]
    #define W2D0_VDOIN_ENABLE_VDOINDATA_TEST Fld(1,1,AC_MSKB0)//[1:1]
    #define W2D0_VDOIN_ENABLE_BGENVDOIN_ON Fld(1,0,AC_MSKB0)//[0:0]
#define W2D0_VDOIN_MODE (W2D_BASE + 0xE04)
    #define W2D0_VDOIN_MODE_MON_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define W2D0_VDOIN_MODE_VRST_POS_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define W2D0_VDOIN_MODE_VRST_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define W2D0_VDOIN_MODE_FRAME_END_LR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define W2D0_VDOIN_MODE_VSCALE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define W2D0_VDOIN_Y0ADDR (W2D_BASE + 0xE08)
    #define W2D0_VDOIN_Y0ADDR_BGY0ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_LINE (W2D_BASE + 0xE0C)
    #define W2D0_VDOIN_LINE_BGVSYNC601DET Fld(7,13,AC_MSKW21)//[19:13]
    #define W2D0_VDOIN_LINE_BGACTIVELINE Fld(13,0,AC_MSKW10)//[12:0]
#define W2D0_VDOIN_C0ADDR (W2D_BASE + 0xE10)
    #define W2D0_VDOIN_C0ADDR_BGC0ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_ACTLINE (W2D_BASE + 0xE14)
    #define W2D0_VDOIN_ACTLINE_BGACTIVE_CLINE Fld(13,16,AC_MSKW32)//[28:16]
    #define W2D0_VDOIN_ACTLINE_BGACTIVE_YLINE Fld(13,0,AC_MSKW10)//[12:0]
#define W2D0_VDOIN_HPKCNT (W2D_BASE + 0xE18)
    #define W2D0_VDOIN_HPKCNT_BGNPIXEL Fld(13,0,AC_MSKW10)//[12:0]
#define W2D0_VDOIN_INPUT_CTRL (W2D_BASE + 0xE20)
    #define W2D0_VDOIN_INPUT_CTRL_SD_480I_MIX_ECO Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D0_VDOIN_INPUT_CTRL_SD_444_2FS Fld(1,30,AC_MSKB3)//[30:30]
    #define W2D0_VDOIN_INPUT_CTRL_SD_4FS_OPT Fld(1,23,AC_MSKB2)//[23:23]
    #define W2D0_VDOIN_INPUT_CTRL_C_SAMPLE_INV Fld(1,22,AC_MSKB2)//[22:22]
    #define W2D0_VDOIN_INPUT_CTRL_C_DELAY Fld(1,20,AC_MSKB2) //[20:20]
    #define W2D0_VDOIN_INPUT_CTRL_Y_DELAY Fld(1,18,AC_MSKB2) //[18:18]
    #define W2D0_VDOIN_INPUT_CTRL_BGSCALE_INV Fld(1,17,AC_MSKB2)//[17:17]
    #define W2D0_VDOIN_INPUT_CTRL_BGENHSYNC_INV Fld(1,16,AC_MSKB2)//[16:16]
    #define W2D0_VDOIN_INPUT_CTRL_BGENVSYNC_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define W2D0_VDOIN_INPUT_CTRL_VDOIN_444_MODE Fld(1,9,AC_MSKB1)//[9:9]
#define W2D0_VDOINVPKCNT (W2D_BASE + 0xE24)
    #define W2D0_VDOINVPKCNT_BGBOTTOMLINE Fld(13,16,AC_MSKW32)//[28:16]
    #define W2D0_VDOINVPKCNT_BGTOPLINE Fld(13,0,AC_MSKW10)//[12:0]
#define W2D0_VDOIN_HCNT (W2D_BASE + 0xE34)
    #define W2D0_VDOIN_HCNT_BGACTHCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define W2D0_VDOIN_HCNT_BGHCNT Fld(13,0,AC_MSKW10)//[12:0]
#define W2D0_VDOIN_HCNTEND (W2D_BASE + 0xE38)
    #define W2D0_VDOIN_HCNTEND_BGCHCNTEND Fld(10,16,AC_MSKW32)//[25:16]
    #define W2D0_VDOIN_HCNTEND_BGYHCNTEND Fld(10,0,AC_MSKW10)//[9:0]
#define W2D0_VDOIN_BACKUP2 (W2D_BASE + 0xE3C)
    #define W2D0_VDOIN_BACKUP2_BGHSIZE Fld(10,16,AC_MSKW32)//[25:16]
    #define W2D0_VDOIN_BACKUP2_BGTEST_BAR Fld(1,13,AC_MSKB1)//[13:13]
    #define W2D0_VDOIN_BACKUP2_BGSRAMCS_ENA Fld(1,12,AC_MSKB1)//[12:12]
    #define W2D0_VDOIN_BACKUP2_BGLINEST_ENA Fld(1,10,AC_MSKB1)//[10:10]
#define W2D0_DEBUG1 (W2D_BASE + 0xE4C)
    #define W2D0_DEBUG1_ADDR_IDX Fld(3,28,AC_MSKB3) //[30:28]
#define W2D0_DRAM_PROTECT1 (W2D_BASE + 0xE58)
    #define W2D0_DRAM_PROTECT1_FULL_CLR Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D0_DRAM_PROTECT1_YPROTECT_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define W2D0_DRAM_PROTECT1_YPROTECT_SEL Fld(1,29,AC_MSKB3)//[29:29]
    #define W2D0_DRAM_PROTECT1_YPROTECT_T Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_DRAM_PROTECT2 (W2D_BASE + 0xE5C)
    #define W2D0_DRAM_PROTECT2_YPROTECT_B Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_SRAM_DSEL (W2D_BASE + 0xE60)
    #define W2D0_SRAM_DSEL_ULTRA_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define W2D0_SRAM_DSEL_ULTRA_TH Fld(8,16,AC_FULLB2)//[23:16]
    #define W2D0_SRAM_DSEL_FULL_TH Fld(8,8,AC_FULLB1)//[15:8]
#define W2D0_VDOIN_Y1ADDR (W2D_BASE + 0xE64)
    #define W2D0_VDOIN_Y1ADDR_BGY1ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_C1ADDR (W2D_BASE + 0xE68)
    #define W2D0_VDOIN_C1ADDR_BGC1ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_Y2ADDR (W2D_BASE + 0xE6C)
    #define W2D0_VDOIN_Y2ADDR_BGY2ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_C2ADDR (W2D_BASE + 0xE70)
    #define W2D0_VDOIN_C2ADDR_BGC2ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_Y3ADDR (W2D_BASE + 0xE74)
    #define W2D0_VDOIN_Y3ADDR_BGY3ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_C3ADDR (W2D_BASE + 0xE78)
    #define W2D0_VDOIN_C3ADDR_BGC3ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_REQ_CTL (W2D_BASE + 0xE7C)
    #define W2D0_VDOIN_REQ_CTL_BGYC_LATCH_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define W2D0_VDOIN_REQ_CTL_BGYCADDR_AUTO_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define W2D0_VDOIN_REQ_CTL_BGYCADDR_AUTO_CNT Fld(3,24,AC_MSKB3)//[26:24]
    #define W2D0_VDOIN_REQ_CTL_BGYCADDR_AUTO_CNT_CLR Fld(1,23,AC_MSKB2)//[23:23]
    #define W2D0_VDOIN_REQ_CTL_BGYCADDR_AUTO_CFG Fld(2,21,AC_MSKB2)//[22:21]
    #define W2D0_VDOIN_REQ_CTL_CH_10BIT_PACK Fld(1,20,AC_MSKB2)//[20:20]
    #define W2D0_VDOIN_REQ_CTL_CH_VRST_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define W2D0_VDOIN_REQ_CTL_CH_PROTECT_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define W2D0_VDOIN_REQ_CTL_CH_REQ_THRES Fld(8,8,AC_FULLB1)//[15:8]
    #define W2D0_VDOIN_REQ_CTL_CH_LAST_THRES Fld(8,0,AC_FULLB0)//[7:0]
#define W2D0_VDOIN_REQ_OUT (W2D_BASE + 0xE80)
    #define W2D0_VDOIN_REQ_OUT_INDEX_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D0_VDOIN_REQ_OUT_H_DIS_ACT_SEL Fld(1,29,AC_MSKB3)//[29:29]
    #define W2D0_VDOIN_REQ_OUT_H_DIS_END_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define W2D0_VDOIN_REQ_OUT_CH_C_ACT_SEL Fld(2,26,AC_MSKB3)//[27:26]
    #define W2D0_VDOIN_REQ_OUT_CH_INT_MODE Fld(2,24,AC_MSKB3)//[25:24]
    #define W2D0_VDOIN_REQ_OUT_REQ_PROTECT_DIS Fld(1,23,AC_MSKB2)//[23:23]
    #define W2D0_VDOIN_REQ_OUT_REQ_PROTECT_THRES Fld(23,0,AC_MSKDW)//[22:0]
#define W2D0_DRAM_PROTECT3 (W2D_BASE + 0xE84)
    #define W2D0_DRAM_PROTECT3_CPROTECT_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D0_DRAM_PROTECT3_CPROTECT_T Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_DRAM_PROTECT4 (W2D_BASE + 0xE88)
    #define W2D0_DRAM_PROTECT4_CPROTECT_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D0_DRAM_PROTECT4_CPROTECT_B Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_DRAM_DUMP (W2D_BASE + 0xE8C)
    #define W2D0_DRAM_DUMP_DEBUG_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D0_DRAM_DUMP_PREULTRA_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define W2D0_DRAM_DUMP_PREULTRA_TH Fld(8,0,AC_FULLB0)//[7:0]
#define W2D0_VDOIN_Y4ADDR (W2D_BASE + 0xE90)
    #define W2D0_VDOIN_Y4ADDR_BGY4ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_C4ADDR (W2D_BASE + 0xE94)
    #define W2D0_VDOIN_C4ADDR_BGC4ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_Y5ADDR (W2D_BASE + 0xE98)
    #define W2D0_VDOIN_Y5ADDR_BGY5ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D0_VDOIN_C5ADDR (W2D_BASE + 0xE9C)
    #define W2D0_VDOIN_C5ADDR_BGC5ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_ENABLE (W2D_BASE + 0xF00)
    #define W2D1_VDOIN_ENABLE_BG422MODE Fld(1,25,AC_MSKB3)//[25:25]
    #define W2D1_VDOIN_ENABLE_MTKDATA_ENA Fld(1,21,AC_MSKB2)//[21:21]
    #define W2D1_VDOIN_ENABLE_SD_480I_MIX Fld(1,11,AC_MSKB1)//[11:11]
    #define W2D1_VDOIN_ENABLE_BGENVSYNC601INV Fld(1,10,AC_MSKB1)//[10:10]
    #define W2D1_VDOIN_ENABLE_FRAME_END_NEW_CFG Fld(2,8,AC_MSKB1)//[9:8]
    #define W2D1_VDOIN_ENABLE_BURST4_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define W2D1_VDOIN_ENABLE_BGENEXTEAV Fld(1,6,AC_MSKB0)//[6:6]
    #define W2D1_VDOIN_ENABLE_VDOINDATA_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define W2D1_VDOIN_ENABLE_SRAM_ENA_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define W2D1_VDOIN_ENABLE_PRGS Fld(1,3,AC_MSKB0)//[3:3]
    #define W2D1_VDOIN_ENABLE_BGVDOFORMAT Fld(1,2,AC_MSKB0)//[2:2]
    #define W2D1_VDOIN_ENABLE_VDOINDATA_TEST Fld(1,1,AC_MSKB0)//[1:1]
    #define W2D1_VDOIN_ENABLE_BGENVDOIN_ON Fld(1,0,AC_MSKB0)//[0:0]
#define W2D1_VDOIN_MODE (W2D_BASE + 0xF04)
    #define W2D1_VDOIN_MODE_MON_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define W2D1_VDOIN_MODE_VRST_POS_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define W2D1_VDOIN_MODE_VRST_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define W2D1_VDOIN_MODE_FRAME_END_LR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define W2D1_VDOIN_MODE_VSCALE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define W2D1_VDOIN_Y0ADDR (W2D_BASE + 0xF08)
    #define W2D1_VDOIN_Y0ADDR_BGY0ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_LINE (W2D_BASE + 0xF0C)
    #define W2D1_VDOIN_LINE_BGVSYNC601DET Fld(7,13,AC_MSKW21)//[19:13]
    #define W2D1_VDOIN_LINE_BGACTIVELINE Fld(13,0,AC_MSKW10)//[12:0]
#define W2D1_VDOIN_C0ADDR (W2D_BASE + 0xF10)
    #define W2D1_VDOIN_C0ADDR_BGC0ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_ACTLINE (W2D_BASE + 0xF14)
    #define W2D1_VDOIN_ACTLINE_BGACTIVE_CLINE Fld(13,16,AC_MSKW32)//[28:16]
    #define W2D1_VDOIN_ACTLINE_BGACTIVE_YLINE Fld(13,0,AC_MSKW10)//[12:0]
#define W2D1_VDOIN_HPKCNT (W2D_BASE + 0xF18)
    #define W2D1_VDOIN_HPKCNT_BGNPIXEL Fld(13,0,AC_MSKW10)//[12:0]
#define W2D1_VDOIN_INPUT_CTRL (W2D_BASE + 0xF20)
    #define W2D1_VDOIN_INPUT_CTRL_SD_480I_MIX_ECO Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D1_VDOIN_INPUT_CTRL_SD_444_2FS Fld(1,30,AC_MSKB3)//[30:30]
    #define W2D1_VDOIN_INPUT_CTRL_SD_4FS_OPT Fld(1,23,AC_MSKB2)//[23:23]
    #define W2D1_VDOIN_INPUT_CTRL_C_SAMPLE_INV Fld(1,22,AC_MSKB2)//[22:22]
    #define W2D1_VDOIN_INPUT_CTRL_C_DELAY Fld(1,20,AC_MSKB2) //[20:20]
    #define W2D1_VDOIN_INPUT_CTRL_Y_DELAY Fld(1,18,AC_MSKB2) //[18:18]
    #define W2D1_VDOIN_INPUT_CTRL_BGSCALE_INV Fld(1,17,AC_MSKB2)//[17:17]
    #define W2D1_VDOIN_INPUT_CTRL_BGENHSYNC_INV Fld(1,16,AC_MSKB2)//[16:16]
    #define W2D1_VDOIN_INPUT_CTRL_BGENVSYNC_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define W2D1_VDOIN_INPUT_CTRL_VDOIN_444_MODE Fld(1,9,AC_MSKB1)//[9:9]
#define W2D1_VDOINVPKCNT (W2D_BASE + 0xF24)
    #define W2D1_VDOINVPKCNT_BGBOTTOMLINE Fld(13,16,AC_MSKW32)//[28:16]
    #define W2D1_VDOINVPKCNT_BGTOPLINE Fld(13,0,AC_MSKW10)//[12:0]
#define W2D1_VDOIN_HCNT (W2D_BASE + 0xF34)
    #define W2D1_VDOIN_HCNT_BGACTHCNT Fld(13,16,AC_MSKW32)//[28:16]
    #define W2D1_VDOIN_HCNT_BGHCNT Fld(13,0,AC_MSKW10)//[12:0]
#define W2D1_VDOIN_HCNTEND (W2D_BASE + 0xF38)
    #define W2D1_VDOIN_HCNTEND_BGCHCNTEND Fld(10,16,AC_MSKW32)//[25:16]
    #define W2D1_VDOIN_HCNTEND_BGYHCNTEND Fld(10,0,AC_MSKW10)//[9:0]
#define W2D1_VDOIN_BACKUP2 (W2D_BASE + 0xF3C)
    #define W2D1_VDOIN_BACKUP2_BGHSIZE Fld(10,16,AC_MSKW32)//[25:16]
    #define W2D1_VDOIN_BACKUP2_BGTEST_BAR Fld(1,13,AC_MSKB1)//[13:13]
    #define W2D1_VDOIN_BACKUP2_BGSRAMCS_ENA Fld(1,12,AC_MSKB1)//[12:12]
    #define W2D1_VDOIN_BACKUP2_BGLINEST_ENA Fld(1,10,AC_MSKB1)//[10:10]
#define W2D1_DEBUG1 (W2D_BASE + 0xF4C)
    #define W2D1_DEBUG1_ADDR_IDX Fld(3,28,AC_MSKB3) //[30:28]
#define W2D1_DRAM_PROTECT1 (W2D_BASE + 0xF58)
    #define W2D1_DRAM_PROTECT1_FULL_CLR Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D1_DRAM_PROTECT1_YPROTECT_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define W2D1_DRAM_PROTECT1_YPROTECT_SEL Fld(1,29,AC_MSKB3)//[29:29]
    #define W2D1_DRAM_PROTECT1_YPROTECT_T Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_DRAM_PROTECT2 (W2D_BASE + 0xF5C)
    #define W2D1_DRAM_PROTECT2_YPROTECT_B Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_SRAM_DSEL (W2D_BASE + 0xF60)
    #define W2D1_SRAM_DSEL_ULTRA_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define W2D1_SRAM_DSEL_ULTRA_TH Fld(8,16,AC_FULLB2)//[23:16]
    #define W2D1_SRAM_DSEL_FULL_TH Fld(8,8,AC_FULLB1)//[15:8]
#define W2D1_VDOIN_Y1ADDR (W2D_BASE + 0xF64)
    #define W2D1_VDOIN_Y1ADDR_BGY1ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_C1ADDR (W2D_BASE + 0xF68)
    #define W2D1_VDOIN_C1ADDR_BGC1ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_Y2ADDR (W2D_BASE + 0xF6C)
    #define W2D1_VDOIN_Y2ADDR_BGY2ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_C2ADDR (W2D_BASE + 0xF70)
    #define W2D1_VDOIN_C2ADDR_BGC2ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_Y3ADDR (W2D_BASE + 0xF74)
    #define W2D1_VDOIN_Y3ADDR_BGY3ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_C3ADDR (W2D_BASE + 0xF78)
    #define W2D1_VDOIN_C3ADDR_BGC3ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_REQ_CTL (W2D_BASE + 0xF7C)
    #define W2D1_VDOIN_REQ_CTL_BGYC_LATCH_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define W2D1_VDOIN_REQ_CTL_BGYCADDR_AUTO_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define W2D1_VDOIN_REQ_CTL_BGYCADDR_AUTO_CNT Fld(3,24,AC_MSKB3)//[26:24]
    #define W2D1_VDOIN_REQ_CTL_BGYCADDR_AUTO_CNT_CLR Fld(1,23,AC_MSKB2)//[23:23]
    #define W2D1_VDOIN_REQ_CTL_BGYCADDR_AUTO_CFG Fld(2,21,AC_MSKB2)//[22:21]
    #define W2D1_VDOIN_REQ_CTL_CH_10BIT_PACK Fld(1,20,AC_MSKB2)//[20:20]
    #define W2D1_VDOIN_REQ_CTL_CH_VRST_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define W2D1_VDOIN_REQ_CTL_CH_PROTECT_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define W2D1_VDOIN_REQ_CTL_CH_REQ_THRES Fld(8,8,AC_FULLB1)//[15:8]
    #define W2D1_VDOIN_REQ_CTL_CH_LAST_THRES Fld(8,0,AC_FULLB0)//[7:0]
#define W2D1_VDOIN_REQ_OUT (W2D_BASE + 0xF80)
    #define W2D1_VDOIN_REQ_OUT_INDEX_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D1_VDOIN_REQ_OUT_H_DIS_ACT_SEL Fld(1,29,AC_MSKB3)//[29:29]
    #define W2D1_VDOIN_REQ_OUT_H_DIS_END_SEL Fld(1,28,AC_MSKB3)//[28:28]
    #define W2D1_VDOIN_REQ_OUT_CH_C_ACT_SEL Fld(2,26,AC_MSKB3)//[27:26]
    #define W2D1_VDOIN_REQ_OUT_CH_INT_MODE Fld(2,24,AC_MSKB3)//[25:24]
    #define W2D1_VDOIN_REQ_OUT_REQ_PROTECT_DIS Fld(1,23,AC_MSKB2)//[23:23]
    #define W2D1_VDOIN_REQ_OUT_REQ_PROTECT_THRES Fld(23,0,AC_MSKDW)//[22:0]
#define W2D1_DRAM_PROTECT3 (W2D_BASE + 0xF84)
    #define W2D1_DRAM_PROTECT3_CPROTECT_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D1_DRAM_PROTECT3_CPROTECT_T Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_DRAM_PROTECT4 (W2D_BASE + 0xF88)
    #define W2D1_DRAM_PROTECT4_CPROTECT_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D1_DRAM_PROTECT4_CPROTECT_B Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_DRAM_DUMP (W2D_BASE + 0xF8C)
    #define W2D1_DRAM_DUMP_DEBUG_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define W2D1_DRAM_DUMP_PREULTRA_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define W2D1_DRAM_DUMP_PREULTRA_TH Fld(8,0,AC_FULLB0)//[7:0]
#define W2D1_VDOIN_Y4ADDR (W2D_BASE + 0xF90)
    #define W2D1_VDOIN_Y4ADDR_BGY4ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_C4ADDR (W2D_BASE + 0xF94)
    #define W2D1_VDOIN_C4ADDR_BGC4ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_Y5ADDR (W2D_BASE + 0xF98)
    #define W2D1_VDOIN_Y5ADDR_BGY5ADDR Fld(28,0,AC_MSKDW)//[27:0]
#define W2D1_VDOIN_C5ADDR (W2D_BASE + 0xF9C)
    #define W2D1_VDOIN_C5ADDR_BGC5ADDR Fld(28,0,AC_MSKDW)//[27:0]

//Page R2R
#define R2R_BASE (IO_VIRT + 0x22000)
#define C_R2R_REG00 (R2R_BASE + 0xCC0)
    #define C_R2R_REG00_R2R_SHADOW_CFG Fld(2,30,AC_MSKB3)//[31:30]
    #define C_R2R_REG00_R2R_HSYNC_TOTAL Fld(13,16,AC_MSKW32)//[28:16]
    #define C_R2R_REG00_R2R_VSYNC_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define C_R2R_REG01 (R2R_BASE + 0xCC4)
    #define C_R2R_REG01_R2R_HSYNC_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define C_R2R_REG01_R2R_VDEW Fld(13,0,AC_MSKW10)//[12:0]
#define C_R2R_REG02 (R2R_BASE + 0xCC8)
    #define C_R2R_REG02_R2R_VSYNC_START Fld(13,16,AC_MSKW32)//[28:16]
    #define C_R2R_REG02_R2R_VSYNC_END Fld(13,0,AC_MSKW10)//[12:0]
#define C_R2R_REG03 (R2R_BASE + 0xCCC)
    #define C_R2R_REG03_R2R_HDE_START Fld(13,16,AC_MSKW32)//[28:16]
    #define C_R2R_REG03_R2R_HDE_END Fld(13,0,AC_MSKW10)//[12:0]
#define C_R2R_REG04 (R2R_BASE + 0xCD0)
    #define C_R2R_REG04_R2R_VDE_START Fld(13,16,AC_MSKW32)//[28:16]
    #define C_R2R_REG04_R2R_VDE_END Fld(13,0,AC_MSKW10)//[12:0]
#define C_R2R_REG05 (R2R_BASE + 0xCD4)
    #define C_R2R_REG05_R2R_RST_0 Fld(1,31,AC_MSKB3)//[31:31]
    #define C_R2R_REG05_R2R_HDEW_PITCH Fld(10,20,AC_MSKW32)//[29:20]
    #define C_R2R_REG05_R2R_HSYNC_POLAR Fld(1,19,AC_MSKB2)//[19:19]
    #define C_R2R_REG05_R2R_VSYNC_POLAR Fld(1,18,AC_MSKB2)//[18:18]
    #define C_R2R_REG05_R2R_DE_POLAR Fld(1,17,AC_MSKB2)//[17:17]
    #define C_R2R_REG05_R2R_WORD_MAX Fld(9,8,AC_MSKW21)//[16:8]
    #define C_R2R_REG05_R2R_REQ_TH Fld(8,0,AC_FULLB0)//[7:0]
#define C_R2R_REG06 (R2R_BASE + 0xCD8)
    #define C_R2R_REG06_R2R_PREFETCH_ULTRA_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define C_R2R_REG06_R2R_EMPTY_SEL Fld(1,30,AC_MSKB3)//[30:30]
    #define C_R2R_REG06_R2R_PREULTRA_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define C_R2R_REG06_R2R_PREULTRA_TH Fld(9,20,AC_MSKW32)//[28:20]
    #define C_R2R_REG06_R2R_INT_CLR Fld(1,19,AC_MSKB2)//[19:19]
    #define C_R2R_REG06_R2R_INT_MASK Fld(1,18,AC_MSKB2)//[18:18]
    #define C_R2R_REG06_R2R_ULTRA_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define C_R2R_REG06_R2R_ULTRA_TH Fld(9,8,AC_MSKW21)//[16:8]
    #define C_R2R_REG06_R2R_REF2R2R_VSYNC_PUL_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define C_R2R_REG06_R2R_REF2R2R_VSYNC_PUL_ONCE Fld(1,6,AC_MSKB0)//[6:6]
    #define C_R2R_REG06_R2R_10BIT_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define C_R2R_REG06_R2R_BURST_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define C_R2R_REG06_R2R_BURST_4 Fld(1,3,AC_MSKB0)//[3:3]
    #define C_R2R_REG06_R2R_GREQ0_ENABLE Fld(1,2,AC_MSKB0)//[2:2]
    #define C_R2R_REG06_R2R_GREQ1_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define C_R2R_REG06_R2R_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define C_R2R_REG07 (R2R_BASE + 0xCDC)
    #define C_R2R_REG07_R2R_420_MODE Fld(1,31,AC_MSKB3)//[31:31]
    #define C_R2R_REG07_R2R_420_INIT Fld(1,30,AC_MSKB3)//[30:30]
    #define C_R2R_REG07_R2R_PATTERN_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define C_R2R_REG07_R2R_COLOR_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define C_R2R_REG07_R2R_3D_INV Fld(1,27,AC_MSKB3)//[27:27]
    #define C_R2R_REG07_R2R_3D_MODE Fld(2,25,AC_MSKB3)//[26:25]
    #define C_R2R_REG07_R2R_BND_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define C_R2R_REG07_R2R_EMPTY_CLR0 Fld(1,23,AC_MSKB2)//[23:23]
    #define C_R2R_REG07_R2R_EMPTY_CLR1 Fld(1,22,AC_MSKB2)//[22:22]
    #define C_R2R_REG07_R2R_EMPTY_TH Fld(9,12,AC_MSKW21)//[20:12]
    #define C_R2R_REG07_R2R_DBG_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define C_R2R_REG07_R2R_AUTO_SEL Fld(2,5,AC_MSKB0)//[6:5]
    #define C_R2R_REG07_R2R_AUTO_CNT_CLR Fld(1,4,AC_MSKB0)//[4:4]
    #define C_R2R_REG07_R2R_AUTO_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define C_R2R_REG07_R2R_AUTO_CNT_CFG Fld(3,0,AC_MSKB0)//[2:0]
#define C_R2R_REG08 (R2R_BASE + 0xCE0)
    #define C_R2R_REG08_R2R_BND_W Fld(16,16,AC_FULLW32)//[31:16]
    #define C_R2R_REG08_R2R_BND_H Fld(16,0,AC_FULLW10)//[15:0]
    /**Multi defined register**/
    #define C_R2R_REG08_LEFT_PAT_COLOR_C Fld(10,0,AC_MSKW10) //[9:0]
    #define C_R2R_REG08_LEFT_PAT_COLOR_Y Fld(10,16,AC_FULLW32) //[25:16]
#define C_R2R_REG09 (R2R_BASE + 0xCE4)
    #define C_R2R_REG09_R2R_FREERUN_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define C_R2R_REG09_R2R_FREERUN_SPEED Fld(4,25,AC_MSKB3)//[28:25]
    #define C_R2R_REG09_R2R_PAT_MODE Fld(1,23,AC_MSKB2)//[23:23]
    #define C_R2R_REG09_R2R_COLOR_MODE Fld(2,21,AC_MSKB2)//[22:21]
    #define C_R2R_REG09_R2R_HOR_LINE_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define C_R2R_REG09_R2R_FREQ_SEL Fld(3,17,AC_MSKB2)//[19:17]
    #define C_R2R_REG09_R2R_ANGLE_SEL Fld(3,14,AC_MSKW21)//[16:14]
    #define C_R2R_REG09_R2R_LEFT_SIDE Fld(1,13,AC_MSKB1)//[13:13]
    #define C_R2R_REG09_R2R_PAT_DUTY_CYCLE Fld(5,8,AC_MSKB1)//[12:8]
    #define C_R2R_REG09_R2R_YPAT1 Fld(4,4,AC_MSKB0)//[7:4]
    #define C_R2R_REG09_R2R_YPAT2 Fld(4,0,AC_MSKB0)//[3:0]
    /**Multi defined register**/
    #define C_R2R_REG09_RIGHT_PAT_COLOR_C Fld(10,0,AC_MSKW10) //[9:0]
    #define C_R2R_REG09_RIGHT_PAT_COLOR_Y Fld(10,16,AC_FULLW32) //[25:16]
#define C_R2R_REG10 (R2R_BASE + 0xCE8)
    #define C_R2R_REG10_R2R0_Y_ADR0 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG11 (R2R_BASE + 0xCEC)
    #define C_R2R_REG11_R2R0_C_ADR0 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG12 (R2R_BASE + 0xCF0)
    #define C_R2R_REG12_R2R1_Y_ADR0 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG13 (R2R_BASE + 0xCF4)
    #define C_R2R_REG13_R2R_INT Fld(1,31,AC_MSKB3)//[31:31]
    #define C_R2R_REG13_R2R1_C_ADR0 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG14 (R2R_BASE + 0xCF8)
    #define C_R2R_REG14_R2R0_Y_ADR1 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG15 (R2R_BASE + 0xCFC)
    #define C_R2R_REG15_R2R0_C_ADR1 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG16 (R2R_BASE + 0xD00)
    #define C_R2R_REG16_R2R1_Y_ADR1 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG17 (R2R_BASE + 0xD04)
    #define C_R2R_REG17_R2R1_C_ADR1 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG18 (R2R_BASE + 0xD08)
    #define C_R2R_REG18_R2R0_Y_ADR2 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG19 (R2R_BASE + 0xD0C)
    #define C_R2R_REG19_R2R0_C_ADR2 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG20 (R2R_BASE + 0xD10)
    #define C_R2R_REG20_R2R1_Y_ADR2 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG21 (R2R_BASE + 0xD14)
    #define C_R2R_REG21_R2R1_C_ADR2 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG22 (R2R_BASE + 0xC00)
    #define C_R2R_REG22_R2R0_Y_ADR3 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG23 (R2R_BASE + 0xC04)
    #define C_R2R_REG23_R2R0_C_ADR3 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG24 (R2R_BASE + 0xC08)
    #define C_R2R_REG24_R2R1_Y_ADR3 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG25 (R2R_BASE + 0xC0C)
    #define C_R2R_REG25_R2R1_C_ADR3 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG26 (R2R_BASE + 0xC10)
    #define C_R2R_REG26_R2R0_Y_ADR4 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG27 (R2R_BASE + 0xC14)
    #define C_R2R_REG27_R2R0_C_ADR4 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG28 (R2R_BASE + 0xC18)
    #define C_R2R_REG28_R2R1_Y_ADR4 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG29 (R2R_BASE + 0xC1C)
    #define C_R2R_REG29_R2R1_C_ADR4 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG30 (R2R_BASE + 0xC20)
    #define C_R2R_REG30_R2R0_Y_ADR5 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG31 (R2R_BASE + 0xC24)
    #define C_R2R_REG31_R2R0_C_ADR5 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG32 (R2R_BASE + 0xC28)
    #define C_R2R_REG32_R2R1_Y_ADR5 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG33 (R2R_BASE + 0xC2C)
    #define C_R2R_REG33_R2R1_C_ADR5 Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG34 (R2R_BASE + 0xC30)
    #define C_R2R_REG34_R2R0_CRC_DBG Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG35 (R2R_BASE + 0xC34)
    #define C_R2R_REG35_R2R1_CRC_DBG Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG36 (R2R_BASE + 0xC38)
    #define C_R2R_REG36_R2R_ADDR_IDX Fld(3,28,AC_MSKB3) //[30:28]
    #define C_R2R_REG36_R2R_STAT Fld(28,0,AC_MSKDW)//[27:0]
#define C_R2R_REG37 (R2R_BASE + 0xC3C)
    #define C_R2R_REG37_R2R_DBG Fld(28,0,AC_MSKDW)//[27:0]

#endif
