/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/*-----------------------------------------------------------------------------
 *
 * $Author: xiaojun.zhu $
 * $Date: 2015/08/08 $
 * $RCSfile: setpll.c,v $
 * $Revision: #8 $
 *
 *---------------------------------------------------------------------------*/

#include "x_typedef.h"
#include "x_ckgen.h"
#include "x_timer.h"
#include "sv_const.h"

#include "hw_vdoin.h"
#include "hw_ckgen.h"
#include "hw_ddds.h"
#include "hw_tg.h"
#include "hw_hpcpll.h"
#include "hw_ifpll.h"


#include "util.h"
#ifndef CC_MTK_LOADER
#include "x_util.h"
#include "feature.h"
//#include "drv_display.h"
#else /* CC_MTK_LOADER */
#define u8Div6432(a, b, c)  ((a) / (b))
#endif /* CC_MTK_LOADER */
#include "drv_display.h"

#include "x_bim.h"
#include "hw_lvds.h"
#include "x_pdwnc.h"
#include "hw_pdwnc.h"
#include "drv_vdoclk.h"
#include "drv_tcon.h"
#include "drv_lvds.h"
#include "drv_vbyone.h"
#include "ostg_if.h"
#include "panel.h"
#ifdef CC_MTK_LOADER
#define DEFINE_IS_LOG(level, fmt...)   Printf(fmt)
#endif

#include "x_debug.h"

//=====================================================================
// Configuration

#define VPLL_SPREAD_CW              (0x1fffffff)
#define VPLL_SPREAD_INT_SHIFT       (24)
#ifndef NDEBUG
#define VOPLL_Debug
#define VOPLL_Para_Chk 0
#endif
#define VOPLL_STRESS_TEST 0

#define ENABLE_DDDS2_FEEDBACK 1

#define syspll_d2_ck 0x2
#define AD_DDDS1_VSP 0x14    
#define AD_DDDS2_VSP 0x15    
#define AD_VPLL_TCON_CK 0x16    
#define AD_LVDS_DPIX_CK 0x17    
#define AD_PPLL_DPIX_CK 0x18    
#define AD_CLKDIG_CTS_D11 0x19 
#define DBGCKSEL_tclk 0x1a 
#define DBGCKSEL_tclk_div 0x59
#define DBGCKSEL_oclk 0x1b 
#define DBGCKSEL_oclk_div2 0x5a
#define DBGCKSEL_oclk_div 0x5b
#define DBGCKSEL_lvds_clk_cts 0x1c 
#define DBGCKSEL_mon_clk75m_ck 0x5c 

#define MUSTANG_SYSPLL_CLK 648000000
#define SYSPLLCLK_FREQ MUSTANG_SYSPLL_CLK

#define VOPLLSetRecoverCnt 12

enum 
{
  LVDS_MODE,
  MLVDS_MODE,
  VB1_MODE,
  EPI_MODE,
  iDP_MODE
};

enum 
{
  VCO32PHASE_594M,
  VCO32PHASE_297M,
  VCO32PHASE_148P5M,
  VCO32PHASE_222P8M,
  VCO32PHASE_445P5M  
};


#ifdef CONFIG_OPM
BOOL fgVOPLLInit = FALSE;
#else
static BOOL fgVOPLLInit = FALSE;
#endif
BOOL  _fgVOPLLPowerOn = FALSE;
BOOL  _fgFBNeedSS = FALSE;
static BOOL _fgVopllUseDDDS = TRUE;
UINT8 _Lvds7To4FifoReset = 0;
UINT8 _u1TconMode = 0;

UINT32 _u4VPllFrequency = 0;
#if 0
//Never usage
static UINT8 _u1VCO32PHASE_FREQ = 0;
#endif
static UINT32 _u4SetVopllFreq = 148500000;
static UINT8 u1VOPLLType = LVDS_MODE;
static UINT8 _u1DddsCWMul = 1;
#if 0
//Never usage
static UINT8 TCLK_PCLK_RATION_NUM;
static UINT8 TCLK_PCLK_RATION_DEN;
static UINT8 TCON_TCLK_RATION;
#endif

extern UINT8 fgDDDSInit;

#define PPM_MULTI 1000000
#define StepLimitIndex 5
PRIVATE UINT32 auStepLimit[StepLimitIndex+1] =
{
//  UNIT: ppm
	200, 200, 100, 30, 30, 30,
};
extern UINT8 _u1StepLimitLevel;

/**
 * @brief set VOPLL clock
 *
 * Set video output PLL frequency
 * @param bCLK is the target VOPLL clock rate (MHz)
 * @retval void
 */
static void vDrvPIXPLLPathEnable(UINT8 u1Enable)
{
	if ((_u1TconMode!=LVDS_MODE) && (u1Enable))
	{
		if(_u1TconMode==iDP_MODE)
		{
		}
		else
		{
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, PPLL_REFSEL_VPLL, REG_LVDSTX_PLL_CFG4_PPLL_REFSEL);
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(1, REG_LVDSTX_PLL_CFG3_VPLL_FMEN)|P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_FPEN));
		}
	} 
	else
	{
		vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, PPLL_REFSEL_VPLL, REG_LVDSTX_PLL_CFG4_PPLL_REFSEL);
		//vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_FMEN)|P_Fld(1, REG_LVDSTX_PLL_CFG3_VPLL_FPEN));
		vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3, 1, REG_LVDSTX_PLL_CFG3_VPLL_FPEN);
		if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
		{
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3, 1, REG_LVDSTX_PLL_CFG3_VPLL_FMEN);
		}
		else
		{
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3, 0, REG_LVDSTX_PLL_CFG3_VPLL_FMEN);
		}
	}    
}

static void vDrvPIXPLLInit_VbyOne(void)
{
    vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(2, REG_LVDSTX_PLL_CFG4_PPLL_REFSEL)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_DIVEN)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)
                                      |P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_LF)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_VODEN));

    vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0x20, REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_PREDIV)|P_Fld(2, REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL)
		                              |P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x3, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
}


static void vDrvVOPLLInit_VbyOne(void)
{
	//set d1a4 and d1b4
	UINT32 u4DispBit;
	u4DispBit = DISP_BIT;

	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3, 1, REG_LVDSTX_PLL_CFG3_VPLL_MONEN);
	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 3, REG_LVDSTX_PLL_CFG2_VPLL_BC);
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_FPEN)|P_Fld(1, REG_LVDSTX_PLL_CFG3_VPLL_FMEN));

	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 1, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN);	
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG0, P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD)|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_PRE_PWD)|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_COMP_PWD));
	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 0, REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN);	

	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(3, REG_LVDSTX_PLL_CFG1_VPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_POSDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_REFSEL));

	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2));
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2, P_Fld(0, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL)|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_BAND)
											|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD)|P_Fld(0, REG_LVDSTX_PLL_CFG2_VPLL_VODEN)
											|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_DIVEN));

	switch (u4DispBit)
	{
	    case DISP_36BIT:
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 0x1, REG_LVDSTX_PLL_CFG2_VPLL_BIC);  // 0x5
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(0x01, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(0x09, REG_LVDSTX_PLL_CFG3_VPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_BR));  // 0xD
		break;
		
		case DISP_30BIT:
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 0x1, REG_LVDSTX_PLL_CFG2_VPLL_BIC);  // 0x4
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(0x01, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(0x09, REG_LVDSTX_PLL_CFG3_VPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_BR));  // 0xA, 0xC
		break;
		
		case DISP_24BIT:
		case DISP_18BIT:
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 0x1, REG_LVDSTX_PLL_CFG2_VPLL_BIC);  // 0x3
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(0x01, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(0x0E, REG_LVDSTX_PLL_CFG3_VPLL_BP)|P_Fld(1, REG_LVDSTX_PLL_CFG3_VPLL_BR));  // 0x7, 0xc
		break;
		default:
		break;
	}
	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 0, REG_LVDSTX_PLL_CFG4_PPLL_TSTEN);
	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 0, REG_LVDSTX_PLL_CFG4_PPLL_RESERVE);
	
}

static void vDrvVOPLLInit_LVDS(void)
{
  //  PFD/CHP/LPF/BAND setting
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG0, P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD)|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_PRE_PWD)|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_COMP_PWD));
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x1B, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV)|P_Fld(1, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL)
										|P_Fld(1, REG_LVDSTX_PLL_CFG1_VPLL_POSDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_REFSEL)|P_Fld(1, REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN));
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2, P_Fld(3, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL)|P_Fld(2, REG_LVDSTX_PLL_CFG2_VPLL_BAND)|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN)
										|P_Fld(0, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD)|P_Fld(0, REG_LVDSTX_PLL_CFG2_VPLL_VODEN));

	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2, P_Fld(0x2, REG_LVDSTX_PLL_CFG2_VPLL_BIC)|P_Fld(3, REG_LVDSTX_PLL_CFG2_VPLL_BC)|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_DIVEN));
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(0x6, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(0xC, REG_LVDSTX_PLL_CFG3_VPLL_BP)|P_Fld(3, REG_LVDSTX_PLL_CFG3_VPLL_BR)
	                                	|P_Fld(1, REG_LVDSTX_PLL_CFG3_VPLL_FPEN)|P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_FMEN)|P_Fld(0, REG_LVDSTX_PLL_CFG3_VPLL_RESERVE));

	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0x0F, REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL)
										|P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
	                                    
	vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(2, REG_LVDSTX_PLL_CFG4_PPLL_REFSEL)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_DIVEN)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)
		                                |P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_LF)|P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_VODEN)); 
}
#if 0
//Never usage
static void vDrvVOPLLInit_MINI(void)
{
  if (_u1VCO32PHASE_FREQ == VCO32PHASE_594M)
  {

   vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 3, REG_LVDSTX_PLL_CFG2_VPLL_BIC);
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(9, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(4, REG_LVDSTX_PLL_CFG3_VPLL_BR));
                                        
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)); 

  }
  else if (_u1VCO32PHASE_FREQ == VCO32PHASE_445P5M)
  {
   vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 2, REG_LVDSTX_PLL_CFG2_VPLL_BIC);
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(6, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(3, REG_LVDSTX_PLL_CFG3_VPLL_BR));
      
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)); 
   
  }    
  else if (_u1VCO32PHASE_FREQ == VCO32PHASE_297M)
  {
   vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 1, REG_LVDSTX_PLL_CFG2_VPLL_BIC);
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(4, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(3, REG_LVDSTX_PLL_CFG3_VPLL_BR));
                                                
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)); 

  }  
  else if (_u1VCO32PHASE_FREQ == VCO32PHASE_222P8M)
  {
   vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 1, REG_LVDSTX_PLL_CFG2_VPLL_BIC);
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(3, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(3, REG_LVDSTX_PLL_CFG3_VPLL_BR));
      
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)); 

  }  
  else if (_u1VCO32PHASE_FREQ == VCO32PHASE_148P5M)
  {
   vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 1, REG_LVDSTX_PLL_CFG2_VPLL_BIC);
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG3, P_Fld(2, REG_LVDSTX_PLL_CFG3_VPLL_BIR)|P_Fld(3, REG_LVDSTX_PLL_CFG3_VPLL_BR));
      
   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BP)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_BR)); 

  }  

  vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_LVDSEN)|P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_VB1EN)
                                    |P_Fld(0x01,REG_LVDSTX_PLL_CFG1_VPLL_MLVDSEN)|P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_EPIEN)
			                        |P_Fld(0x01,REG_LVDSTX_PLL_CFG1_VPLL_IDPEN)|P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN)	                        
			                        |P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2)|P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)
			                        |P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2)); 
  vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2, P_Fld(0x03,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL)|P_Fld(0x01,REG_LVDSTX_PLL_CFG2_VPLL_BAND)
  									|P_Fld(0x00,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN)|P_Fld(0x00,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD)
  									|P_Fld(0x00,REG_LVDSTX_PLL_CFG2_VPLL_VODEN)|P_Fld(3, REG_LVDSTX_PLL_CFG2_VPLL_BC)
  									|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_DIVEN));
  
  vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3,0xC,REG_LVDSTX_PLL_CFG3_VPLL_BP);
}
#endif 

static void vDrvVOPLLInit(void)
{

    if(u1VOPLLType != _u1TconMode)
    {
        // re-init vopll if tcon mode changed.
        fgVOPLLInit = 0;
    }

    if ((IO32ReadFldAlign(DDDS_08, FLAG_VOPLL_INITIAL) == 1)&& (!(IS_PANEL_L12R12)))
    {
        fgVOPLLInit = TRUE;
    }
	
	#if VOPLL_STRESS_TEST
		fgVOPLLInit = FALSE;
	#endif
	
    if(!fgVOPLLInit)
    {       
       vIO32WriteFldAlign(CKGEN_TCLK_TEST, 0, FLD_OCLK_SEL);
       vIO32WriteFldAlign(CKGEN_TCLK_TEST, 0, FLD_TCLK_SEL);

       // VOPLL Power Control
       vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 1, REG_LVDSTX_PLL_CFG0_VPLL_BG_LVDS_PWD);       
       vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 1, REG_LVDSTX_PLL_CFG1_VPLL_PWD);      
       vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 1, REG_LVDSTX_PLL_CFG0_VPLL_BG_PWD);       
       HAL_Delay_us(100);
       
       vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 0, REG_LVDSTX_PLL_CFG0_VPLL_BG_PWD);
       HAL_Delay_us(1000);       

	   vIO32WriteFldAlign(REG_LVDS_TX_PLL_CFG,0,REG_LVDS_TX_PLL_CFG_VPLL_BG_CKEN);
	   vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG0, P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_XTAL_DIV)|P_Fld(8, REG_LVDSTX_PLL_CFG0_VPLL_BG_TRIM)
	   										|P_Fld(2, REG_LVDSTX_PLL_CFG0_VPLL_BG_RASEL)|P_Fld(1, REG_LVDSTX_PLL_CFG0_VPLL_BG_RBSEL)
	   										|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_PWD)|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_COMP_PWD)
	   										|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_PRE_PWD)|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD)
	   										|P_Fld(0, REG_LVDSTX_PLL_CFG0_VPLL_BG_LVDS_PWD)|P_Fld(1, REG_LVDSTX_PLL_CFG0_VPLL_BIAS_BYP));


   	   if(_u1TconMode == VB1_MODE)
       {
   		 vDrvVOPLLInit_VbyOne();
   		 vDrvPIXPLLInit_VbyOne();
   		 LOG(0,"###VbyOne VOPLLInit  finsih###");
	   }
       else if(_u1TconMode == iDP_MODE)
       {
       }	
#ifdef SUPPORT_EPI
       else if(_u1TconMode == EPI_MODE)
       {
   	   }
#endif
	   else
	   {
        vDrvVOPLLInit_LVDS();
	   }
    
	   vDrvPIXPLLPathEnable(1);

       // Input clcok type : single-end & VCO Band seclect
       vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 0, REG_LVDSTX_PLL_CFG1_VPLL_REFSEL);
       vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 2, REG_LVDSTX_PLL_CFG2_VPLL_BAND);
    

#ifndef CC_UBOOT
       vDrvSetOCLKClockSchemaInit();
#endif
             
       vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 7, FLD_RG_DDDS1_PI_C);
       vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 7, FLD_RG_DDDS2_PI_C);

       fgVOPLLInit = TRUE;       
       u1VOPLLType = _u1TconMode;       

       vIO32WriteFldAlign(DDDS_08, 1, FLAG_VOPLL_INITIAL);
       
    }
	else
	{
#ifndef CC_UBOOT
      vDrvSetOCLKClockSchemaInit();	
#endif
	}   
}

void vDrvDPIX_CLK_SEL(void)
{
	if (_u1TconMode==MLVDS_MODE)
	{     
	}
	else if (_u1TconMode==LVDS_MODE)
	{
		if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
		{
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, (LVDSTX_PLL_POST_LVDSEN | LVDSTX_PLL_POST_VB1EN), LVDSTX_PLL_POST_SEL);
		}
		else
		{
			vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, LVDSTX_PLL_POST_LVDSEN, LVDSTX_PLL_POST_SEL);
		}
	}
	else if (_u1TconMode==VB1_MODE)
	{
		vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, LVDSTX_PLL_POST_VB1EN, LVDSTX_PLL_POST_SEL);
	}
#ifdef SUPPORT_EPI
	else if (_u1TconMode==EPI_MODE)
	{
	}    
#endif
	else if (_u1TconMode==iDP_MODE)
	{
	}       
}


#define DEFAULT_VCO_PHASE 8
#if 0
//Never usage
static void vDrvVCOPhase_Init(void)
{
    vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2,P_Fld(0x08,REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKA)|P_Fld(0x08,REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKB));
    vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, 0x09, REG_LVDSTX_PLL_CFG2_VPLL_DLY_DATA);
    
//    vIO32WriteFldMulti(REG_LVDS_TX_CFG11, P_Fld(1,RG_LVDSA_CLK_IQ_SEL_E3)|P_Fld(1,RG_LVDSA_CLK_IQ_SEL_O3));
//    vIO32WriteFldMulti(REG_LVDS_TX_CFG2, P_Fld(1,RG_LVDSB_CLK_IQ_SEL_E3)|P_Fld(1,RG_LVDSB_CLK_IQ_SEL_O3));
}
#endif

void vDrvVCOMode_SEL(void)
{
    if (_u1TconMode==MLVDS_MODE) // 32-Phase VCO
    {     
    }
    else // 4-Phase VCO
    {
    }
}

void vDrvVOPLLSet(void)
{
    UINT8 u1PreDiv=0,u1FBKDIV=0;	
    UINT8 u1TclkDiv=0;
	UINT8 u1TclkDiv2=0;
	UINT8 u1Bir=0;
	UINT8 u1Bic=0;
    UINT8 u1VPLLPOSDiv=0;
    UINT8 fgPixelClkDiv2=0;
    UINT8 u1SsOclkDiv = 0;
    UINT32 u4DispBit;
    UINT32 u4VB1Lane;	
#if 0
	// Never usage.
    UINT8 u1TCONDivSel=0; //=MLDVS_output_port * tclk_pclk_ratio
    UINT8 u1FBDiv=0x07;
	UINT8 u1PPLLPOSDiv=0;
#endif	
	UINT32 u4VCOFreq=0;

    u4DispBit = DISP_BIT;
    u4VB1Lane = LVDS_OUTPUT_PORT;
    

    if (_u1TconMode == MLVDS_MODE)
    {      

    }
    else if (_u1TconMode == LVDS_MODE)
    {
    	u1TclkDiv2 = 0;
	    if (LVDS_OUTPUT_PORT == SINGLE_PORT)
	    {
	       if(IS_LVDS_HIGHSPEED)
	       { 
		   	_u1DddsCWMul =2;
			u1TclkDiv=0;
	       }
		   else
		   {
	        _u1DddsCWMul =1;
	        u1TclkDiv=1; //total VOPLL = VCO / 2 
	   	   }	    
	        
	        u1VPLLPOSDiv=1;
	        fgPixelClkDiv2=1;
	        vIO32WriteFldAlign(CKGEN_OCLK_TEST, 0, FLD_OCLK_DIV_SEL);        
	    }
	    else  if (LVDS_OUTPUT_PORT == DUAL_PORT) 
	    {
	        if(IS_LVDS_HIGHSPEED)
	        {    
                _u1DddsCWMul =4;
                u1TclkDiv=0; 		 
	        }
			else
			{
                _u1DddsCWMul =2;
                if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
                {
                    if (IS_IC_5893_ES1())
                    	u1TclkDiv=0; 
                    else
                        u1TclkDiv=2;
                }
                else
                {
                	u1TclkDiv=1;  //total VOPLL = VCO / 2 	 
                }
			}
			if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
			{
				u1VPLLPOSDiv=0;
			}
			else
			{
				u1VPLLPOSDiv=1;  
			}
			fgPixelClkDiv2=0;
	        u1SsOclkDiv = 1; //default lvds clock for dual-port

	        #ifdef DRV_SUPPORT_EXTMJC
	        if (IS_COMPANION_CHIP_ON())
	        {
	            if ((vDrvGetCurLvdsMode() ==  eLvdsVidYuv422OnePort ) || (vDrvGetCurLvdsMode() ==  eLvdsVidRgb444OnePort )
	                || (vDrvGetCurLvdsMode() ==  eLvdsVidYuv422OnePort8Bit ) || (vDrvGetCurLvdsMode() ==  eLvdsVidRgb444OnePort8Bit ))
	            {
	                u1TclkDiv=1;  
	                u1VPLLPOSDiv=1;
	                fgPixelClkDiv2=0;
	                u1SsOclkDiv = 0; //lvds clock for one-port video data
	            }
	        }   
	        #endif
	        
			vIO32WriteFldAlign(CKGEN_OCLK_TEST, u1SsOclkDiv, FLD_OCLK_DIV_SEL);        
	    }
	    else //if (LVDS_OUTPUT_PORT == FOUR_PORT) 
	    {
	        if(IS_LVDS_HIGHSPEED)
	        {
		        _u1DddsCWMul =8;
		        u1SsOclkDiv = 1;
				u1VPLLPOSDiv=1;
	        }
	        else
	        {
		        _u1DddsCWMul =4;
		        u1SsOclkDiv = 2;        
				u1VPLLPOSDiv=2;
				u1TclkDiv2 = 2;
	        }
			
	        u1TclkDiv=0;   //total VOPLL = VCO / 1 
	        fgPixelClkDiv2=0;

	        vIO32WriteFldAlign(CKGEN_OCLK_TEST, u1SsOclkDiv, FLD_OCLK_DIV_SEL);
	    }
	    
	    // 2. setup vpll start -----------------------------------------------------

	    // 2.A FB divider setting + Protect Mode (patch for LVDS VCO double freq. if VCO is lower than 360MHz)

	    // VCO = 74.25  / VPLL_PREDIV * (VPLL_FBDIVBYPEN & VPLL_FBDIV3P5EN) * VPLL01_VPLL_FBDIV
		u4VCOFreq = (_u4SetVopllFreq / _u1DddsCWMul)* 14;

	    if(_fgVopllUseDDDS)
	    {
			if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
			{
				  
                if (IS_IC_5893_ES1())
                {
				    u1FBKDIV = 6;
                    u1PreDiv = 1;
                }
                else
                {
                    u1FBKDIV = 111;
                    u1PreDiv = 2;
                }
			}   
			else
			{
		    	u1PreDiv = 3;  
				u1FBKDIV = 0x1B;
			}
			if(u4VCOFreq < (2*360000000))
			{		
				if((u1TclkDiv < 2)
					&&(u1PreDiv > 0))
				{
					if (LVDS_OUTPUT_PORT == SINGLE_PORT)
					{
						u1PreDiv = 0;  // REG_LVDSTX_PLL_CFG1_VPLL_PREDIV
						u1Bir = 0x3;  // 576p/480p
						u1Bic = 0x1;
						u1FBKDIV = 0xD;
						u1TclkDiv = u1TclkDiv + 1;  // REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV
					}
					else if (LVDS_OUTPUT_PORT == DUAL_PORT || LVDS_OUTPUT_PORT == FOUR_PORT)  // FOUR_PORT: for panel table #90,91,92
					{
						u1PreDiv = 1;  // REG_LVDSTX_PLL_CFG1_VPLL_PREDIV
						u1Bir = 0x6;  // 1440*900
						u1Bic = 0x2;
						u1TclkDiv = u1TclkDiv + 1;  // REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV
					}
				}
				#ifdef VOPLL_Debug
				LOG(0,"For LVDS VCO double freq. if VCO is lower than 360MHz u4VCOFreq = %d\n", u4VCOFreq);		
				#endif
			}
			else
			{
				u1Bir = 0x6;
				u1Bic = 0x2;
			}
	    }
	    else
	    {
	    	u1PreDiv = 0;
	        if(u4VCOFreq < (2*360000000))
	        {
	           if(u1TclkDiv < 2)
	           {
	              u1TclkDiv = u1TclkDiv + 1;
	              u4VCOFreq = u4VCOFreq << 1;
	           }
			   u1Bir = 0x3;
			   u1Bic = 0x1;
	        }
			else
			{
				u1Bir = 0x6;
				u1Bic = 0x2;
			}
	        if(IS_XTAL_24MHZ())
	    		u1FBKDIV = (UINT8)((u4VCOFreq / 24000000) - 1);
	        else
	    		u1FBKDIV = (UINT8)((u4VCOFreq / 27000000) - 1);		
	    }

		// [DDDS] 519.75 = 74.25 / 2 * 1 *14
		if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
		{
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(u1PreDiv, REG_LVDSTX_PLL_CFG1_VPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL)
											 |P_Fld(u1FBKDIV, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV));

            if (BSP_GetIcVersion() >= IC_VER_5893_AB) // >=E2
                vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 2, REG_LVDSTX_PLL_CFG1_VPLL_REFSEL);
		}
		else
		{
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(u1PreDiv, REG_LVDSTX_PLL_CFG1_VPLL_PREDIV)|P_Fld(0x01, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL)
											 |P_Fld(u1FBKDIV, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV));
		}

	    // 2.B Set post divider
	    vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, u1TclkDiv2, REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2);     
	    vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(u1TclkDiv,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)
			                              |P_Fld(fgPixelClkDiv2,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));                                                                     
	    vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3, 0, REG_LVDSTX_PLL_CFG3_VPLL_RESERVE);
		if (IS_IC_5893_ES1() && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
		{
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(16, REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV)|P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL)
												|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
        }
		else
		{
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0x0F, REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL)
												|P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
		}
		vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, u1VPLLPOSDiv, REG_LVDSTX_PLL_CFG1_VPLL_POSDIV);  

		vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2,u1Bic,REG_LVDSTX_PLL_CFG2_VPLL_BIC);
		vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3,u1Bir,REG_LVDSTX_PLL_CFG3_VPLL_BIR);

		vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2, P_Fld(3, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL)|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN)
										|P_Fld(0, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD));
	}           
#ifdef SUPPORT_EPI
    else if (_u1TconMode == EPI_MODE)
    {

    }
#endif
    else if (_u1TconMode == VB1_MODE)    
    {
		if((u4VB1Lane == OCTA_PORT)||(u4VB1Lane == HEXA_PORT))
		{	
			if (PANEL_IsSupport4K2KDD())
			{
				_u1DddsCWMul = 8;
				if (_fgVopllUseDDDS)
				{
					vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x2, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
				}
				else
				{
					vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0x30, REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL)
		                              |P_Fld(1, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x0, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2)|P_Fld(2, REG_LVDSTX_PLL_CFG4_PPLL_REFSEL));
				}
			}
			else
			{
				_u1DddsCWMul = 4;
				vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x3, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
			}
		}                             
		else if(u4VB1Lane == FOUR_PORT)
		{	
			if(IS_LVDS_HIGHSPEED)
			{
				_u1DddsCWMul =8;
			}
			else
			{
				_u1DddsCWMul =4;
			}
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(0,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x3, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
		
		}
		else if (u4VB1Lane == DUAL_PORT)
		{
			_u1DddsCWMul =2;				   
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(1,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x3, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
				   
		}
		else if (u4VB1Lane == SINGLE_PORT)
		{
			_u1DddsCWMul =1;			   
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG4, P_Fld(2,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV)|P_Fld(0x3, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
		}
		
		switch (u4DispBit)
		{
			case DISP_36BIT:
				vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x18, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV)|P_Fld(3, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL));		
			break;
			
			case DISP_30BIT:
				if (_fgVopllUseDDDS)
				{
					vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x13, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV)|P_Fld(3, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL));
				}
				else
				{
					vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x1D, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV)|P_Fld(1, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL));
					
					vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_PREDIV)|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_POSDIV)
															|P_Fld(0, REG_LVDSTX_PLL_CFG1_VPLL_REFSEL));
				}
			break;
			
	 		case DISP_18BIT:
	 		case DISP_24BIT:
				vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x1D, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV)|P_Fld(1, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL));
			break;
			
			default:
			break;
    	}
		vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG2, P_Fld(0, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL)|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN)
										|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD)|P_Fld(1, REG_LVDSTX_PLL_CFG2_VPLL_BAND));
    	#if (!(VOPLL_STRESS_TEST))
    	  LOG(0,"###VbyOne VOPLLSet  finsih###");
    	#endif
    }    
    else if (_u1TconMode == iDP_MODE)
    {

    }

    // 3. set AD_DPIX_CLK output
    vDrvDPIX_CLK_SEL();

    // 4. select VCO mode
    vDrvVCOMode_SEL();    

}

void vDrvVOPLLVCOKBand(void)
{
    if (_u1TconMode==VB1_MODE)
    {
    
    }
}


UINT32 GetPLLCounter(UINT8 u1case)
{
    vIO32WriteFldAlign(CKGEN_PLLCALIB, 0, FLD_CAL_SEL);        
    vIO32WriteFldAlign(CKGEN_PLLCALIB, 0, FLD_CAL_MODE); // 11 bit                   
    
    vIO32WriteFldAlign(CKGEN_PLLCALIB,u1case,FLD_DBGCKSEL);
    vIO32WriteFldAlign(CKGEN_PLLCALIB,0x01,FLD_SOFT_RST_CAL);
    HAL_Delay_us(20);        
    vIO32WriteFldAlign(CKGEN_PLLCALIB,0x01,FLD_CAL_TRI);         
    // Wait calibration finishing.
    while (IO32ReadFldAlign(CKGEN_PLLCALIB, FLD_CAL_TRI)) { }        
    return(IO32ReadFldAlign(CKGEN_PLLCALIBCNT,FLD_CALI_CNT));

}

void u1VOPLLSource(UINT8 u1arg1)
{
    if (u1arg1<2)
    {   
    _fgVopllUseDDDS = !(u1arg1);
    }
}

void vDrvCalDownErrorLimit(UINT32 u4Error)
{
	UINT32 u4ErrUp = 0;
	UINT32 u4ErrDown = 0;
	UINT32 u4CWCent = 0;
	UINT32 u4CWUp = 0;
	UINT32 u4CWDown = 0;
	UINT64 u8ClkDown = 0;

	u4CWCent = IO32ReadFldAlign(DDDS_00, DDDS_00_DDDS_FREQ_CW);
	u4ErrUp = ((u4Error & 0xff)<<16)+(u4Error >> 16);
	u4CWUp = u4CWCent - u4ErrUp;
	u8ClkDown = ((2*(UINT64)_u4SetVopllFreq) - (u8Div6432(((UINT64)SYSPLLCLK_FREQ << 23), u4CWUp, NULL)*_u1DddsCWMul));
	u4CWDown = (UINT32)u8Div6432(((UINT64)SYSPLLCLK_FREQ << 23), u8ClkDown, NULL);
	u4CWDown = u4CWDown * _u1DddsCWMul;
	u4ErrDown = u4CWDown - u4CWCent;
	
	vIO32WriteFldAlign(DDDS_1E, (u4ErrDown>>16), DDDS_1E_DDDS_ERR_LIM_DOWN);
	vIO32WriteFldAlign(DDDS_1E, (u4ErrDown&0xffff), DDDS_1E_DDDS_ERR_LIM_DOWN_LOW);
}

UINT32 u4DrvCalStepValue(UINT8 bLevel)
{
	UINT32 u4StepValue = 0;
	
	bLevel &= 0xf;  //0~15
	if (bLevel > StepLimitIndex) 
	{
		bLevel = DEFAULT_PANEL_STEP_LIMIT_LEVEL;
	}
	_u1StepLimitLevel = bLevel;
	u4StepValue = auStepLimit[bLevel];
	//LOG(3, "level=%d, value=%d\n", bLevel, u4StepValue);

	return (u4StepValue);
}

void vDrvCalStepLimit(UINT32 u4Value)
{
	UINT64 u8CWMax = 0;
	UINT32 u4StepLimit = 0;
	
#if DDDS_OUT_DIV2
	u8CWMax = u8Div6432(((UINT64)SYSPLLCLK_FREQ << 23)*_u1DddsCWMul, _u4SetVopllFreq, NULL);
#else
	u8CWMax = u8Div6432(((UINT64)SYSPLLCLK_FREQ << 24)*_u1DddsCWMul, _u4SetVopllFreq, NULL);
#endif
	u8CWMax = u8Div6432(u8CWMax*PPM_MULTI, (PPM_MULTI+u4Value), NULL);
	//LOG(3, "CW_max=0x%016llx\n", u8CWMax);
	u4StepLimit = IO32ReadFldAlign(DDDS_00, DDDS_00_DDDS_FREQ_CW);
	//LOG(3, "CW_cent=0x%x\n", u4StepLimit);
	u4StepLimit -= (UINT32)u8CWMax;
	//LOG(3, "step_limit=0x%x\n", u4StepLimit);

	vIO32WriteFldAlign(DDDS_25, u4StepLimit, DDDS_25_CW_STEP_LIMIT);
}

void vDrvEnableStepLimit(UINT8 bEnable)
{
	vIO32WriteFldAlign(DDDS_25, bEnable, DDDS_25_CW_STEP_LIMIT_EN);
}

void vSetVOPLLFreq(UINT32 u4Freq)
{
    UINT32 u4Syspll = 0;
    UINT64 u8Cw;
    UINT8 u1ResetCnt=0,u1Mode=0;    
    UINT16 u2Oclk=0, u2Oclk2=0;   
    UINT32 u2Oclk_target=0, u2Oclk2_target=0;
    UINT32 u2Oclk_targetH=0, u2Oclk_targetL=0,u2Oclk2_targetH=0,u2Oclk2_targetL=0;    
    UINT32 u4RefCount=0;
    #ifdef VOPLL_Debug  
      UINT32 CW_Read,CWS_Read;
    #endif
    #if VOPLL_STRESS_TEST
      UINT32 u8TestCnt=1000000;
    #endif
	UINT8 u1StepLimitEn=0, u1StepLevel=0;

    if (u4Freq == 0)
    {
        return;
    }

	if (PANEL_Is4K2K120()||PANEL_Is8K4K30())
	{
		u4Freq = u4Freq>>1;
	}

    _u4VPllFrequency = u4Freq;
	_u4SetVopllFreq = u4Freq;

#ifdef VOPLL_Debug 
 #if (!(VOPLL_STRESS_TEST))
           LOG(0,"[LVDS] u4Freq=%ld \n",u4Freq);     
 #endif
#endif

	#ifdef SUPPORT_PANEL_STEP_LIMIT
	if (PANEL_GetStepLimitEn()!=0xFF)
	{
		u1StepLimitEn = PANEL_GetStepLimitEn();
	}
	else
	{
		u1StepLimitEn = DEFAULT_ENABLE_STEP_LIMIT;
	}
	if (PANEL_GetStepLimitLevel()!=0xFF)
	{
		u1StepLevel = PANEL_GetStepLimitLevel();
	}
	else
	{
		u1StepLevel = DEFAULT_PANEL_STEP_LIMIT_LEVEL;
	}
	#else
	u1StepLimitEn = DEFAULT_ENABLE_STEP_LIMIT;
	u1StepLevel = DEFAULT_PANEL_STEP_LIMIT_LEVEL;
	#endif

    if ((IO32ReadFldAlign(DDDS_08, FLAG_VOPLL_POWERON) == 1)&& (!(IS_PANEL_L12R12)))
    {
        _fgVOPLLPowerOn = TRUE;
    }
      
    #if VOPLL_STRESS_TEST
    do
    {
    #endif    

     if( !_fgVOPLLPowerOn)
     {   
      u1ResetCnt = VOPLLSetRecoverCnt;
     }
     else
     {
      u1ResetCnt = 0;
     }

     #ifdef VOPLL_Debug 
      #if (!(VOPLL_STRESS_TEST))
      LOG(0,"[LVDS] Do Loop=%d \n",u1ResetCnt);     
      #endif
     #endif

     vDrvVOPLLInit();
      
     do
     {
		#ifdef VOPLL_Debug     
		if (u1ResetCnt!=VOPLLSetRecoverCnt)
		{
		LOG(0,"[LVDS] Do Loop=%d \n",u1ResetCnt);     
		} 
		#endif       

      vDrvVOPLLSet();
      
    if(_fgVopllUseDDDS)// use ddds
    {           		
		LOG(0,"[SA7] _fgVopllUseDDDS = True\n");
	        
        // B1. setup ddds start -------------------------------------------------
        vIO32WriteFldAlign(DDDS_03, 1,DDDS_03_SPREAD_INIT);
   
        // B2. calculate control word
        u4Syspll = SYSPLLCLK_FREQ; // _CalGetPLLCounter(syspll_d2_ck)*2000; //SYSPLL = 459MHz in MT5395 //CNTseng check

        u8Cw = u8Div6432(((UINT64)u4Syspll << VPLL_SPREAD_INT_SHIFT), u4Freq, NULL);
		#if DDDS_OUT_DIV2
        u8Cw = ((((UINT32)u8Cw*_u1DddsCWMul) >> 1) & VPLL_SPREAD_CW);
		#else
        u8Cw = (((UINT32)u8Cw*_u1DddsCWMul) & VPLL_SPREAD_CW);
		#endif

        vIO32WriteFldAlign(DDDS_00, (UINT32)u8Cw,DDDS_00_DDDS_FREQ_CW);

		// set Error_Limit_Down
		vDDDSCalErrLimDown(u4DDDSGetErrorLimit());
		// set Step_Limit
		vDDDSCalStepLimit(u4DDDSCalStepValue(u1StepLevel));
		vDDDSEnableStepLimit(u1StepLimitEn);

        // B3. enable init
        vIO32WriteFldAlign(DDDS_03, 0,DDDS_03_SPREAD_INIT);        
        // setup ddds done -----------------------------------------------------

		vIO32WriteFldAlign(DDDS_03, 1, DDDS_03_DATA_SYNC_AUTO); 	

		#if DDDS_OUT_DIV2
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 0, FLD_RG_DDDS1_CKSEL); //VPLL from DDDS1
    	#if ENABLE_DDDS2_FEEDBACK
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 0, FLD_RG_DDDS2_CKSEL); //PIXPLL from DDDS2
    	#endif
		#else
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 1, FLD_RG_DDDS1_CKSEL); //VPLL from DDDS1
    	#if ENABLE_DDDS2_FEEDBACK
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 1, FLD_RG_DDDS2_CKSEL); //PIXPLL from DDDS2
    	#endif
		#endif
    }
    else // use xtal
    {
		
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 2, FLD_RG_DDDS1_CKSEL); //XSTAL from DDDS1
        #if ENABLE_DDDS2_FEEDBACK        
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 2, FLD_RG_DDDS2_CKSEL); //XSTAL from DDDS2
        #endif
    }    

    #ifndef CC_FPGA
    vDrvSetVOPLLClockSchema(VOPLL_CLK_SRC_DDDS);
    #endif 

    // 3. Power on VOPLL and check clock
    if(_fgVOPLLPowerOn)
    {
        u1ResetCnt = 0;
    }
    else
    {
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 1, REG_LVDSTX_PLL_CFG0_VPLL_BG_LVDS_PWD);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 1, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 1, REG_LVDSTX_PLL_CFG1_VPLL_PWD);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 1, REG_LVDSTX_PLL_CFG0_VPLL_BIAS_BYP);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 1, REG_LVDSTX_PLL_CFG4_PPLL_PWD);	   
		 HAL_Delay_us(10);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 0, REG_LVDSTX_PLL_CFG1_VPLL_PWD); 

        if (_u1TconMode != LVDS_MODE) //use PPLL
        {
        	if (_u1TconMode==VB1_MODE)
        	    HAL_Delay_us(200);
            else
        		HAL_Delay_us(100);
        	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 0, REG_LVDSTX_PLL_CFG4_PPLL_PWD);
        }
        else
        {
            if (IS_IC_5893_ES1() && PANEL_IsLVDSDualPort())  // HK_ES1 LVDS FHD60 use VB1 clk
            {
            	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 0, REG_LVDSTX_PLL_CFG4_PPLL_PWD);
            }
        }
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 0, REG_LVDSTX_PLL_CFG0_VPLL_BG_LVDS_PWD);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 0, REG_LVDSTX_PLL_CFG0_VPLL_BG_VB1_TX_PWD);
		 vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG0, 0, REG_LVDSTX_PLL_CFG0_VPLL_BIAS_BYP);
		 HAL_Delay_us(20);
     

		if((u1ResetCnt%4) == 1)
		{      
			#ifdef VOPLL_Debug
			 LOG(0," [LVDS] Toggle DDDS u1ResetCnt=%d  \n",u1ResetCnt);
			#endif
			vIO32WriteFldAlign(DDDS_03,1,DDDS_03_SPREAD_INIT);
			HAL_Delay_us(20);
			vIO32WriteFldAlign(DDDS_03,0,DDDS_03_SPREAD_INIT);            
			if (_u1TconMode!=LVDS_MODE) //use PPLL
			{
				vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 1, REG_LVDSTX_PLL_CFG4_PPLL_PWD);       
				if (_u1TconMode==VB1_MODE)
					HAL_Delay_us(400);
				else
					HAL_Delay_us(200);
				vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 0, REG_LVDSTX_PLL_CFG4_PPLL_PWD);
			}
			else
			{	
				if (IS_IC_5893_ES1() && PANEL_IsLVDSDualPort())  // HK_ES1 LVDS FHD60 use VB1 clk
				{
					vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 1, REG_LVDSTX_PLL_CFG4_PPLL_PWD);
					HAL_Delay_us(200);
					vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG4, 0, REG_LVDSTX_PLL_CFG4_PPLL_PWD);
				}
			}
		}

		if ((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort())  // HK LVDS FHD60 use VB1 clk
		{
		    if (IS_IC_5893_ES1())
			    vIO32WriteFldAlign(CKGEN_TCLK_TEST, FLD_OCLK_SEL_PPLL, FLD_OCLK_SEL);
            else
                vIO32WriteFldAlign(CKGEN_TCLK_TEST, FLD_OCLK_SEL_LVDS, FLD_OCLK_SEL);
		}
		
		vDrvVOPLLVCOKBand();

		if(_u1TconMode==LVDS_MODE)//switch DPIX clock
		{
			u2Oclk =  (UINT16)GetPLLCounter(AD_LVDS_DPIX_CK);      
			u2Oclk2 = (UINT16)GetPLLCounter(AD_VPLL_TCON_CK);
		}
		else
		{
			u2Oclk =  (UINT16)GetPLLCounter(AD_PPLL_DPIX_CK);	  
			u2Oclk2 = (UINT16)GetPLLCounter(AD_VPLL_TCON_CK);
		}

		#ifdef VOPLL_Debug
		#if (!(VOPLL_STRESS_TEST))
		    LOG(0,"[LVDS] u2Oclk2=0x%x  \n",u2Oclk2);
		    LOG(0,"[LVDS] u2Oclk=0x%x  \n",u2Oclk);            
		#endif
		#endif

		#ifdef VOPLL_Debug     
		CW_Read=IO32ReadFldAlign(DDDS_00,DDDS_00_DDDS_FREQ_CW);
		CWS_Read=IO32ReadFldAlign(STA_DDDS_00,STA_DDDS_00_DDDS_FREQ_CW);

		#if (!(VOPLL_STRESS_TEST))       
		LOG(0,"[LVDS]CW_Read=0x%lx \n",CW_Read);
		LOG(0,"[LVDS]CWS_Read=0x%lx \n",CWS_Read);  
		#endif 
		#endif

		u1Mode = (UINT8)IO32ReadFldAlign(CKGEN_PLLCALIB, FLD_CAL_MODE);

		switch(u1Mode) {
		case 0: u4RefCount = 11; break;
		case 1: u4RefCount = 16; break;
		case 2: u4RefCount = 20; break;
		case 3: u4RefCount = 24; break;
		default: u4RefCount = 11; break;
		}

		if (((LVDS_OUTPUT_PORT == FOUR_PORT)&&(IS_LVDS_HIGHSPEED)&&(_u1TconMode==LVDS_MODE))
			  || ((_u1TconMode==VB1_MODE) && (IS_LVDS_HIGHSPEED)))
		{
			u2Oclk_target= ((u4Freq/2/1000000)<<u4RefCount)/(GET_XTAL_CLK()/1000000);
		}
		else
		{
			u2Oclk_target= ((u4Freq/1000000)<<u4RefCount)/(GET_XTAL_CLK()/1000000);
		}
		u2Oclk_targetH= u2Oclk_target + (u2Oclk_target*5/100);
		u2Oclk_targetL= u2Oclk_target - (u2Oclk_target*5/100);

		if(_u1TconMode==MLVDS_MODE)
		{     

		}
		else if (_u1TconMode==LVDS_MODE)
		{
			if ((LVDS_OUTPUT_PORT == FOUR_PORT)&&(IS_LVDS_HIGHSPEED))
			{
				u2Oclk2_target= (u2Oclk_target*7)/(_u1DddsCWMul/2)/5;
			} 
			else if ((LVDS_OUTPUT_PORT == DUAL_PORT)&&(IS_LVDS_HIGHSPEED))
			{
				u2Oclk2_target= (u2Oclk_target*7)/(_u1DddsCWMul/2)/2/5;
			} 
			else if ((LVDS_OUTPUT_PORT == SINGLE_PORT)&&(IS_LVDS_HIGHSPEED))
			{
				u2Oclk2_target= (u2Oclk_target*7)/(_u1DddsCWMul/2)/2/5;
			} 	   
			else
			{
				u2Oclk2_target= (u2Oclk_target*7)/_u1DddsCWMul/2/5;
			} 
			u2Oclk2_targetH= u2Oclk2_target + (u2Oclk2_target*5/100);
			u2Oclk2_targetL= u2Oclk2_target - (u2Oclk2_target*5/100);
		}    
		else if (_u1TconMode==VB1_MODE)
		{
			if(DISP_BIT == DISP_36BIT)
				u2Oclk2_target= (u2Oclk_target*5)/_u1DddsCWMul;
			else if(DISP_BIT == DISP_30BIT)
				u2Oclk2_target= (u2Oclk_target*4)/_u1DddsCWMul;
			else
				u2Oclk2_target= (u2Oclk_target*3)/_u1DddsCWMul;
			u2Oclk2_targetH= u2Oclk2_target + (u2Oclk2_target*5/100);
			u2Oclk2_targetL= u2Oclk2_target - (u2Oclk2_target*5/100);
		}    
		else if (_u1TconMode==EPI_MODE)
		{
		
		}      
		else if (_u1TconMode==iDP_MODE)
		{

		}      

	#if (!(VOPLL_STRESS_TEST))  
		if (_u1TconMode==MLVDS_MODE)
		{

		}
	#endif
		if((((((u2Oclk2>=u2Oclk2_targetL)&&(u2Oclk2<=u2Oclk2_targetH))&&((u2Oclk>=u2Oclk_targetL)&&(u2Oclk<=u2Oclk_targetH)))
		 && ((_u1TconMode == MLVDS_MODE)||(_u1TconMode == LVDS_MODE)))
		 || (((u2Oclk>=u2Oclk_targetL)&&(u2Oclk<=u2Oclk_targetH))&& ((_u1TconMode == VB1_MODE)||(_u1TconMode == EPI_MODE))))
		 || (!_fgVopllUseDDDS )||((BSP_GetIcVersion() >= IC_VER_5893_AA) && PANEL_IsLVDSDualPort()))
		{
			u1ResetCnt=0;
			if(_u1TconMode != VB1_MODE)
			{	   
				_Lvds7To4FifoReset = 2;
			}

		#if (!(VOPLL_STRESS_TEST))
			LOG(0,"[LVDS] VOPLL Initialize successful !\n");
		#endif

			vIO32WriteFldAlign(CKGEN_OCLK_TEST, 1, FLD_LVDS_CLKDIG_CTS_D11_SEL);
		
			if(_u1TconMode==LVDS_MODE)//switch DPIX clock
			{
				if (IS_IC_5893_ES1() && PANEL_IsLVDSDualPort())  // HK_ES1 LVDS FHD60 use VB1 clk
				{
					vIO32WriteFldAlign(CKGEN_TCLK_TEST, FLD_OCLK_SEL_PPLL, FLD_OCLK_SEL);
				}
				else
				{
					vIO32WriteFldAlign(CKGEN_TCLK_TEST, FLD_OCLK_SEL_LVDS, FLD_OCLK_SEL); 
				}

			  	vIO32WriteFldAlign(CKGEN_TCLK_TEST, 1, FLD_TCLK_SEL);	// vpll_tcon_ck	
			}
			else if (_u1TconMode==VB1_MODE)
			{
			  	vIO32WriteFldAlign(CKGEN_TCLK_TEST, FLD_OCLK_SEL_PPLL, FLD_OCLK_SEL);  
				if (PANEL_IsSupport4K2KDD()) // all for 4KDD
				{
					vIO32WriteFldAlign(CKGEN_TCLK_TEST, 1, FLD_OCLK_DIV3_SEL);
					vIO32WriteFldAlign(CKGEN_OCLK_TEST, 1, FLD_OCLK_DIV2_SEL);
					vIO32WriteFldAlign(CKGEN_OCLK_TEST, 1, FLD_OCLK_DIV_SEL);
					vIO32WriteFldAlign(CKGEN_TCLK_TEST, 0, FLD_TCLK_SEL);	// xtal to tclk for tcon isr
					vIO32WriteFldAlign(TMGR4, 1, TMGR4_1CHTO2CH_EN);
					vIO32WriteFldAlign(CKGEN_TCLK_TEST, 1, FLD_OCLK_DIV4_SEL);
				}
				else  // none-4KDD
				{
					vIO32WriteFldAlign(CKGEN_TCLK_TEST, 0, FLD_TCLK_SEL);	// xtal to tclk for tcon isr
				}
			}			
			else
			{
				vIO32WriteFldAlign(CKGEN_TCLK_TEST, FLD_OCLK_SEL_PPLL, FLD_OCLK_SEL);   
				vIO32WriteFldAlign(CKGEN_TCLK_TEST, 1, FLD_TCLK_SEL);	// vpll_tcon_ck	
			}

			vIO32WriteFldAlign(CKGEN_MBIST_CK_CTRL, 0, FLD_BIST_VPCLK_SEL);
		 
			vIO32WriteFldAlign(REG_LVDS_TX_CFG12, 0,RG_LVDSA_EN);	 
			HAL_Delay_us(LVDSA_EN_REST_DELAYTIME);
			vIO32WriteFldAlign(REG_LVDS_TX_CFG12, 1,RG_LVDSA_EN);	
		 
			_fgVOPLLPowerOn = TRUE;
			vIO32WriteFldAlign(DDDS_08, 1, FLAG_VOPLL_POWERON);
		}        
		else
		{
			u1ResetCnt--;      
		#ifdef VOPLL_Debug 
			LOG(0,"[LVDS] u2Oclk2=0x%x \n",u2Oclk2);
			LOG(0,"[LVDS] u2Oclk=0x%x \n",u2Oclk);
			if(u2Oclk2 == u2Oclk)
			{
			LOG(0,"[LVDS] VOPLL Reset Fail- OCLK no clock\n");          
			}
			else
			{
			LOG(0,"[LVDS] VOPLL Reset Fail- OCLK wrong clock \n");          
			}
			LOG(0,"[LVDS] CW_Read=0x%lx \n",CW_Read);
			LOG(0,"[LVDS] CWS_Read=0x%lx \n",CWS_Read);       
			if (u1ResetCnt == 0)
			{
			LOG(0,"[LVDS] VOPLL Rrecover Fail \n");          
			}
		#endif
			if (u1ResetCnt == 0)
			{       
				LOG(0,"[LVDS] u2Oclk2=0x%x \n",u2Oclk2);
				LOG(0,"[LVDS] u2Oclk=0x%x \n",u2Oclk);       
				LOG(0,"[MLVDS]u2Oclk_target=0x%lx \n",u2Oclk_target);  
				LOG(0,"[MLVDS]u2Oclk2_target=0x%lx \n",u2Oclk2_target);          
				LOG(0,"[LVDS] VOPLL Initialize Fail !\n");
			} 
		#if VOPLL_STRESS_TEST
			while(1);
		#endif    
		}
	}      
	}while(u1ResetCnt>0);

	#if VOPLL_STRESS_TEST
	u8TestCnt--;
	LOG(0,"%ld \n",u8TestCnt);	   
	}while(u8TestCnt>0);
	#endif    
 
}

void vPanelPowerSaving(void)
{
	if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_LVDS)
	{
		vIO32WriteFldAlign(TMGR0, 1, CKEN_CFG_TCON);
		vIO32WriteFldAlign(TMGR0, 1, CKEN_CFG_MLVDS);
		vIO32WriteFldAlign(TMGR0, 0, CKEN_CFG_VB1);
		vIO32WriteFldAlign(TMGR0, 0, CKEN_CFG_EPI);
	}
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_MLVDS)
	{
	}
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_VB1)
	{
		vIO32WriteFldAlign(TMGR0, 1, CKEN_CFG_TCON);
		vIO32WriteFldAlign(TMGR0, 1, CKEN_CFG_MLVDS);
		vIO32WriteFldAlign(TMGR0, 1, CKEN_CFG_VB1);
		vIO32WriteFldAlign(TMGR0, 0, CKEN_CFG_EPI);	
	}	 
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_EPI)
	{
	}
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_iDP)
	{
	}  
}

void vDrvResetVOPLLFlowFlag(void)
{
	vIO32WriteFldAlign(DDDS_08, 0, FLAG_VOPLL_INITIAL);
	fgVOPLLInit = FALSE;	   
	vIO32WriteFldAlign(DDDS_08, 0, FLAG_VOPLL_POWERON);
	_fgVOPLLPowerOn = FALSE;
	LOG(0,"vDrvResetVOPLLFlowFlag\n");
}

void vDrvVOPLLFreqSet(UINT32 u4Freq)
{
#if 0
	//Never usage
	PANEL_MINILVDS_ATTRIBUTE_T *pParam;
#endif
	if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_LVDS)
	{
		_u1TconMode = LVDS_MODE;
	}
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_MLVDS)
	{
	}
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_VB1)
	{
		_u1TconMode = VB1_MODE;
	}    
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_EPI)
	{
	}
	else if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_iDP)
	{
	}  

	if (IO32ReadFldAlign(DDDS_08, FLAG_PANEL_TYPE) != _u1TconMode)
	{
		vDrvResetVOPLLFlowFlag();
		vIO32WriteFldAlign(DDDS_08, _u1TconMode, FLAG_PANEL_TYPE);
	}

	vSetVOPLLFreq(u4Freq);
	vPanelPowerSaving();  
}

void vDrvVOFreqSet(UINT32 dwDCLK)   // called by Video
{
    vDrvVOPLLFreqSet(dwDCLK);
}

void vDrvVB1VOPLLFreqSet(UINT32 u4Freq)
{
	_u1TconMode = VB1_MODE;
	vSetVOPLLFreq(u4Freq);
}

void vDrvVOPLLStatus(void)
{
    UINT32 u4Syspll, u4cw, u4dclock, VCO_clk, PPLL_VCO_clk, DPIX_clk, CTS_clk,u4HFreq_ext, u4ErrorLimit_Range;
    UINT8 u1MutFactor1,u1MutFactor2, u1DivFactor1, u1DivFactor2, u1DivFactor4, u1DivFactor5;
    UINT16 u2DivFactor3;    

    LOG(0,"==[TconMode]==\n");
	LOG(0,"_u1TconMode = %d ,",_u1TconMode); 
	if (_u1TconMode == LVDS_MODE)
    	LOG(0,"[0]LVDS \n"); 	
	else if (_u1TconMode == VB1_MODE)
    	LOG(0,"[2]VB1 \n"); 		

    LOG(0,"==[Freq Setting]==\n");  
    LOG(0,"u4Freq=%ld \n",_u4SetVopllFreq);
	
	if(_fgVopllUseDDDS)
	{	
		LOG(0,"==[DVOPLL]==\n");  
		u4cw = IO32ReadFldAlign(DDDS_00,DDDS_00_DDDS_FREQ_CW);
		LOG(0,"Close loop=%d\n",(UINT8)IO32ReadFldAlign(DDDS_00,DDDS_00_DISP_EN));
		LOG(0,"CW=0x%7lx, CWS=0x%7lx, Error Limit=0x%3x, Error Limit Low=0x%4x\n",u4cw,(UINT32)IO32ReadFldAlign(STA_DDDS_00,STA_DDDS_00_DDDS_FREQ_CW),(UINT8)IO32ReadFldAlign(DDDS_03,DDDS_03_DDDS_ERR_LIM),
		(UINT16)IO32ReadFldAlign(DDDS_1C,DDDS_1C_NOR_DDDS_LIM_LOW));
		LOG(0,"Symmetric_error_limit ON/OFF: %d\n", IO32ReadFldAlign(DDDS_1E,DDDS_1E_DDDS_NEW_ERR_LIMIT_SEL));
		LOG(0,"Symmetric_error_limit_Down=0x%3x, Symmetric_error_limit_Down_low=0x%4x\n", (UINT8)IO32ReadFldAlign(DDDS_1E, DDDS_1E_DDDS_ERR_LIM_DOWN),
		(UINT16)IO32ReadFldAlign(DDDS_1E, DDDS_1E_DDDS_ERR_LIM_DOWN_LOW));
		LOG(0,"Step_limit Enable: %d\n", IO32ReadFldAlign(DDDS_25, DDDS_25_CW_STEP_LIMIT_EN));
		LOG(0,"Step_limit=0x%lx\n", IO32ReadFldAlign(DDDS_25, DDDS_25_CW_STEP_LIMIT));
		LOG(0,"Lock Status=%d, Overflow Status=%d\n",(UINT8)IO32ReadFldAlign(STA_DDDS_00,STA_DDDS_00_DDDS_LOCK)
		                                         ,(UINT8)IO32ReadFldAlign(STA_DDDS_00,STA_DDDS_00_FIFO_OFLOW));        
		u4Syspll = _CalGetPLLCounter(syspll_d2_ck)*2000; //SYSPLL = 459MHz in MT5395 //CNTseng check
		LOG(0,"Syspll=%ld \n",u4Syspll);         
		u4dclock = (UINT32)u8Div6432(((UINT64)u4Syspll << VPLL_SPREAD_INT_SHIFT), u4cw, NULL);
		LOG(0,"DVOPLL Clock=%ld Hz \n",u4dclock);     		
		u4HFreq_ext = ((IO32ReadFldAlign(DDDS_02,DDDS_02_HLEN_DEN) * IO32ReadFldAlign(DDDS_01,DDDS_01_HLEN_INT)) + IO32ReadFldAlign(DDDS_01,DDDS_01_HLEN_NUM)) * 10 / IO32ReadFldAlign(DDDS_02,DDDS_02_HLEN_DEN);
	#if DDDS_OUT_DIV2
		u4dclock = u4dclock >> 1;
	#endif
		LOG(0,"DVOPLL Clock_FB_DIV=%ld Hz \n", u4dclock); 	
		u4HFreq_ext = u4dclock / u4HFreq_ext * 10;
		LOG(0,"HFreq_ext_input=%ld Hz \n",u4HFreq_ext);
		if (IO32ReadFldAlign(DDDS_00,DDDS_00_DISP_EN))
		{
		u4cw = IO32ReadFldAlign(STA_DDDS_00,STA_DDDS_00_DDDS_FREQ_CW);
		u4dclock = (UINT32)u8Div6432(((UINT64)u4Syspll << VPLL_SPREAD_INT_SHIFT), u4cw, NULL);
		u4HFreq_ext = ((IO32ReadFldAlign(DDDS_02,DDDS_02_HLEN_DEN) * IO32ReadFldAlign(DDDS_01,DDDS_01_HLEN_INT)) + IO32ReadFldAlign(DDDS_01,DDDS_01_HLEN_NUM)) * 10 / IO32ReadFldAlign(DDDS_02,DDDS_02_HLEN_DEN);
	#if DDDS_OUT_DIV2
		u4dclock = u4dclock >> 1;
	#endif	  
		u4HFreq_ext = u4dclock / u4HFreq_ext * 10;
		LOG(0,"HFreq_int_result=%ld Hz \n",u4HFreq_ext);	  
		}
		u4ErrorLimit_Range = (IO32ReadFldAlign(DDDS_03,DDDS_03_DDDS_ERR_LIM) << 16) * 1000 / IO32ReadFldAlign(DDDS_00,DDDS_00_DDDS_FREQ_CW);
		LOG(0,"ErrorLimit Range Threshold (Permillage)= +/- %ld (0/00) \n",u4ErrorLimit_Range);	
		LOG(0,"ErrorLimit Range (Permillage)= %ld (0/00) \n",u4ErrorLimit_Range*2);		  
	}
	else
	{
		if(IS_XTAL_24MHZ())
		{
			u4dclock = 24000000;
		}
		else
		{
			u4dclock = 27000000;
		}
		LOG(0,"PLL Source : Xtal=%ld \n", u4dclock);     
	}

    // 519.75 = 74.25 / 2 * 1 *14
    u1DivFactor1 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_PREDIV);    
    if (u1DivFactor1==0)
    u1DivFactor1 = 1;
    else if (u1DivFactor1==1)
    u1DivFactor1 = 2;    
    else if (u1DivFactor1==3)
    u1DivFactor1 = 4;    

    u1MutFactor1 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL);

    if (u1MutFactor1 == 0)
    u1MutFactor1 = 10;  // 1.0 * 10
    else if (u1MutFactor1==1)
	u1MutFactor1 = 20;	// 2.0 * 10
    else
    u1MutFactor1 = 40;  // 4.0 * 10

    u1MutFactor2 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV)+1;

    VCO_clk = u4dclock/u1DivFactor1*u1MutFactor1/1000*u1MutFactor2/10;

    LOG(0,"==[AVOPLL]==\n"); 
    LOG(0,"u1DivFactor1=%d, u1MutFactor1=%d,u1MutFactor2=%d \n",u1DivFactor1,u1MutFactor1,u1MutFactor2);         
    LOG(0,"VCO Clock=%ld KHz\n",VCO_clk);

    u4dclock = u4dclock/u1DivFactor1; //VPLL_PREDIV
    u1DivFactor1 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4, REG_LVDSTX_PLL_CFG4_PPLL_PREDIV);    
    if (u1DivFactor1==0)
    u1DivFactor1 = 1;
    else if (u1DivFactor1==1)
    u1DivFactor1 = 2;    
    else if (u1DivFactor1==3)
    u1DivFactor1 = 4;    

    u1MutFactor1 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4, REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL);

    if (u1MutFactor1 == 0)
    u1MutFactor1 = 10;  // 1.0 * 10
    else if (u1MutFactor1==1)
	u1MutFactor1 = 20;	// 2.0 * 10
    else
    u1MutFactor1 = 40;  // 4.0 * 10

    u1MutFactor2 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4, REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV);

    PPLL_VCO_clk = u4dclock/u1DivFactor1*u1MutFactor1/1000*u1MutFactor2/10;

    LOG(0,"==[APIXPLL]==\n"); 
    LOG(0,"u1DivFactor1=%d, u1MutFactor1=%d,u1MutFactor2=%d \n",u1DivFactor1,u1MutFactor1,u1MutFactor2);         
    LOG(0,"PPLL VCO Clock=%ld KHz\n",PPLL_VCO_clk);
	#ifndef CONFIG_TV_DRV_VFY
    LOG(0,"[VOPLLdbg]_u1TconMode = %d, panelID = %ld, VPLL = %ld, PPLL = %ld\n",_u1TconMode,GetCurrentPanelIndex(),VCO_clk,PPLL_VCO_clk); 	
	#endif
    if (_u1TconMode == LVDS_MODE)
    {
     u1DivFactor2 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1, REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV);
     u2DivFactor3 = (UINT16)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1, REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2); 
     u1DivFactor4 = 1;
     u1DivFactor5 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1, REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2);

     if (u2DivFactor3 == 0)
     u2DivFactor3 = 175; // 1.75*100
     else
     u2DivFactor3 = 350; // 3.5*100     

     if (u1DivFactor5 == 1)
     u1DivFactor5 = 2;
     else
     u1DivFactor5 = 1;
     
    }
    else
    {
      u1DivFactor2 = (UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV);    
      u2DivFactor3 = (UINT16)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4, REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2);      
	  if (u2DivFactor3==0)
		  u2DivFactor3 = 1;
	  else if (u2DivFactor3==1)
		  u2DivFactor3 = 2;
	  else if (u2DivFactor3==2)
		  u2DivFactor3 = 4;
	  else
		  u2DivFactor3 = 8;
      u1DivFactor4 = 1;
      u1DivFactor5 = 1;
    }

    if (u1DivFactor2==0)
    u1DivFactor2 = 1;
    else if (u1DivFactor2==1)
    u1DivFactor2 = 2;    
    else
    u1DivFactor2 = 4;  
   
    if (_u1TconMode == LVDS_MODE)
	    DPIX_clk = VCO_clk / u1DivFactor2 / u2DivFactor3 /u1DivFactor4 * 100;
	else
	    DPIX_clk = PPLL_VCO_clk / u1DivFactor2 / u2DivFactor3 /u1DivFactor4 * 100;
    LOG(0,"u1DivFactor2=%d, u2DivFactor3=%d, u1DivFactor4=%d\n",u1DivFactor2,u2DivFactor3,u1DivFactor4);    
    LOG(0,"DPIX_clk=%ld KHz\n",DPIX_clk);

     CTS_clk = VCO_clk / 2;
     LOG(0,"CTS_clk=%ld KHz\n",CTS_clk);

    LOG(0,"==[Clock Measure]==\n"); 

    if (_u1TconMode==MLVDS_MODE)
    {
    } 
 
    LOG(0,"[MLVDS]AD_DDDS1_VSP=%ld \n",_CalGetPLLCounter(AD_DDDS1_VSP));
    LOG(0,"[MLVDS]AD_DDDS2_VSP=%ld \n",_CalGetPLLCounter(AD_DDDS2_VSP));     

    LOG(0,"[LVDS]AD_VPLL_TCON_CK=%ld \n",_CalGetPLLCounter(AD_VPLL_TCON_CK));
    LOG(0,"[LVDS]AD_LVDS_DPIX_CK=%ld \n",_CalGetPLLCounter(AD_LVDS_DPIX_CK));
    LOG(0,"[LVDS]AD_PPLL_DPIX_CK=%ld \n",_CalGetPLLCounter(AD_PPLL_DPIX_CK));

    LOG(0,"[LVDS]AD_CLKDIG_CTS_D11=%ld \n",_CalGetPLLCounter(AD_CLKDIG_CTS_D11));
    LOG(0,"[LVDS]tclk=%ld \n",_CalGetPLLCounter(DBGCKSEL_tclk));
    LOG(0,"[LVDS]oclk=%ld \n",_CalGetPLLCounter(DBGCKSEL_oclk));

	if (IS_VBYONE)
	{
		vIO32WriteFldAlign(TMGR1,1,TMGR1_RG_TCLK_DBGSEL);
	    LOG(0,"[VB1_OSD]oclk_div=%ld \n",_CalGetPLLCounter(DBGCKSEL_oclk_div));
	    LOG(0,"[VB1_OSD]oclk_div2=%ld \n",_CalGetPLLCounter(DBGCKSEL_oclk_div2));
		LOG(0,"[VB1_OSD]mon_clk75m_ck=%ld \n",_CalGetPLLCounter(DBGCKSEL_mon_clk75m_ck));
		LOG(0,"[VB1_OSD]tclk_div=%ld \n",_CalGetPLLCounter(DBGCKSEL_tclk_div));
		if (!((PANEL_IsSupport4K2KDD())&& (IS_IC_5861_ES1())))
		vIO32WriteFldAlign(TMGR1,0,TMGR1_RG_TCLK_DBGSEL);  // FIB not setting
	}
	LOG(0,"[LVDS]oclk_div=%ld \n",_CalGetPLLCounter(DBGCKSEL_oclk_div));
    LOG(0,"[LVDS]oclk_div2=%ld \n",_CalGetPLLCounter(DBGCKSEL_oclk_div2));
	LOG(0,"[LVDS]mon_clk75m_ck=%ld \n",_CalGetPLLCounter(DBGCKSEL_mon_clk75m_ck));
	LOG(0,"[LVDS]tclk_div=%ld \n",_CalGetPLLCounter(DBGCKSEL_tclk_div));
	
    LOG(0,"[LVDS]lvds_clk_cts=%ld \n",_CalGetPLLCounter(DBGCKSEL_lvds_clk_cts));
    

	LOG(0,"\n");	 	
	LOG(0,"[VOPLL]LVDS_OUTPUT_PORT =%ld \n",LVDS_OUTPUT_PORT);
	LOG(0,"[VOPLL]_u1DddsCWMul =%d \n",_u1DddsCWMul);
	if(IS_LVDS_HIGHSPEED)
	LOG(0,"[VOPLL]IS_LVDS_HIGHSPEED==1\n");
	else
	LOG(0,"[VOPLL]IS_LVDS_HIGHSPEED==0\n");

	#ifdef VOPLL_Debug
    #if VOPLL_Para_Chk
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_PREDIV));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_POSDIV));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_REFSEL));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_LVDSEN));				  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_VB1EN));				   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_MLVDSEN)); 			 
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_EPIEN));				   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_IDPEN));				   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN));		  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV));		 
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2));
	  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL));		
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_BAND));				  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN));			
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD));		  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_VODEN));				   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DLY_DATA));		  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKA));		  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKB));		  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_BIC));				   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_BC));						
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DIVEN));				 

	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_BIR)); 				   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_BP));						
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_BR));						
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_FPEN));					
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_FMEN));					
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_RESERVE)); 
	  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_PREDIV));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2)); 		   
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_REFSEL));				
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_DIVEN));				 
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_BP));						  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_BR));						  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_LF));						  
	  LOG(0,"%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_VODEN));				   

	#else
	
	LOG(0,"[VOPLL]RG_VPLL_FBKDIV[6:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV));
	LOG(0,"[VOPLL]RG_VPLL_PREDIV[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_PREDIV));
	LOG(0,"[VOPLL]RG_VPLL_FBKSEL[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL));
	LOG(0,"[VOPLL]RG_VPLL_POSDIV[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_POSDIV));
	LOG(0,"[VOPLL]RG_VPLL_REFSEL[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_REFSEL));
	LOG(0,"[VOPLL]RG_VPLL_LVDSEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_LVDSEN));
	LOG(0,"[VOPLL]RG_VPLL_VB1EN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_VB1EN));
	LOG(0,"[VOPLL]RG_VPLL_MLVDSEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_MLVDSEN));
	LOG(0,"[VOPLL]RG_VPLL_EPIEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_EPIEN));
	LOG(0,"[VOPLL]RG_VPLL_IDPEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_IDPEN));
	LOG(0,"[VOPLL]RG_VPLL_LVDSCHL_EN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_LVDSCHL_EN));
	LOG(0,"[VOPLL]RG_VPLL_LVDS_DPIX_DIV2[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));
	LOG(0,"[VOPLL]RG_VPLL_TXCLK_DIV[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV));
	LOG(0,"[VOPLL]RG_VPLL_TXCLK_DIV2[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG1,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2));
	
	LOG(0,"[VOPLL]RG_VPLL_AUTOK_CTRL[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_CTRL));
	LOG(0,"[VOPLL]RG_VPLL_BAND[5:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_BAND));
	LOG(0,"[VOPLL]RG_VPLL_AUTOK_EN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_EN));
	LOG(0,"[VOPLL]RG_VPLL_AUTOK_LOAD[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_AUTOK_LOAD));
	LOG(0,"[VOPLL]RG_VPLL_VODEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_VODEN));
	LOG(0,"[VOPLL]RG_VPLL_DLY_DATA[3:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DLY_DATA));
	LOG(0,"[VOPLL]RG_VPLL_DLY_CLKA[3:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKA));
	LOG(0,"[VOPLL]RG_VPLL_DLY_CLKB[3:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DLY_CLKB));
    LOG(0,"[VOPLL]RG_VPLL_BIC[2:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_BIC));
	LOG(0,"[VOPLL]RG_VPLL_BC[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_BC));
	LOG(0,"[VOPLL]RG_VPLL_DIVEN[2:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG2,REG_LVDSTX_PLL_CFG2_VPLL_DIVEN));
	
	LOG(0,"[VOPLL]RG_VPLL_BIR[3:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_BIR));
	LOG(0,"[VOPLL]RG_VPLL_BP[3:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_BP));
	LOG(0,"[VOPLL]RG_VPLL_BR[3:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_BR));
	LOG(0,"[VOPLL]RG_VPLL_FPEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_FPEN));
	LOG(0,"[VOPLL]RG_VPLL_FMEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_FMEN));
	LOG(0,"[VOPLL]RG_VPLL_RESERVE[7:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG3,REG_LVDSTX_PLL_CFG3_VPLL_RESERVE));
	
	LOG(0,"[VOPLL]RG_PPLL_FBKDIV[6:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_FBKDIV));
	LOG(0,"[VOPLL]RG_PPLL_PREDIV[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_PREDIV));
	LOG(0,"[VOPLL]RG_PPLL_FBKSEL[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_FBKSEL));
	LOG(0,"[VOPLL]RG_PPLL_POSDIV[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV));
	LOG(0,"[VOPLL]RG_PPLL_POSDIV2[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_POSDIV2));
	LOG(0,"[VOPLL]RG_PPLL_REFSEL[1:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_REFSEL));
	LOG(0,"[VOPLL]RG_PPLL_DIVEN[2:0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_DIVEN));
	LOG(0,"[VOPLL]RG_PPLL_BP[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_BP));
	LOG(0,"[VOPLL]RG_PPLL_BR[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_BR));
	LOG(0,"[VOPLL]RG_PPLL_LF[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_LF));
	LOG(0,"[VOPLL]RG_PPLL_VODEN[0]=%d \n",(UINT8)IO32ReadFldAlign(REG_LVDSTX_PLL_CFG4,REG_LVDSTX_PLL_CFG4_PPLL_VODEN));
	#endif
	#endif	
}

void vDDDSInit_uboot(void)
{
#ifdef CC_UBOOT

    vIO32Write4B(0xF000E004, 0xB0010898);
    vIO32Write4B(0xF000E008, 0x00010000);
    vIO32Write4B(0xF000E014, 0x00000000);
    vIO32Write4B(0xF000E00C, 0x80000000);
    vIO32Write4B(0xF000E014, 0x40000000);

	if(PANEL_GetDisplayType()== PANEL_DISPLAY_TYPE_EPI)
	{
	}
	else
	{
        vIO32Write4B(0xF000E000, 0x45E353F);
	}

    vIO32Write4B(0xF000E008, 0x20010711);

    vIO32Write4B(0xF000E010, 0x00000000);

    vIO32WriteFldAlign(0xF000E000,1,Fld(1, 30, AC_MSKB3));
	
    vIO32WriteFldAlign(0xF000E000, 1, Fld(1, 31, AC_MSKB3));	
	HAL_Delay_us(30);
	vIO32WriteFldAlign(0xF000E000, 1, Fld(1, 29, AC_MSKB3));	

	HAL_Delay_us(30);
    vIO32WriteFldAlign(0xF000E000, 0, Fld(1, 31, AC_MSKB3));	
	vIO32WriteFldAlign(0xF000E000, 0, Fld(1, 29, AC_MSKB3));	

    vIO32Write4B(0xF000E00C, 0x80000103);

    vIO32WriteFldAlign(0xF000D118, 0, Fld(2,0,AC_MSKB0));      

    vIO32Write4B(0xF000D3C0, 0x00000001);

    vIO32WriteFldAlign(DDDS_08, 1, FLAG_DDDS_INIT);
#endif	
}

void vDrvVOPLLDDDS_SS_TestMode(UINT8 u1Mode)
{
	#ifndef NDEBUG
	UINT8 u1BIC = 0, u1BIR = 0;
	
	switch(u1Mode)
	{
		case 1:
		u1BIC = 1;
		u1BIR = 2;
		break;

		case 2:
		u1BIC = 3;
		u1BIR = 3;
		break;

		case 3:
		u1BIC = 5;
		u1BIR = 5;
		break;

		case 4:
		u1BIC = 7;
		u1BIR = 7;
		break;

		default:
		u1BIC = 1;
		u1BIR = 1;
		break;			


	}

	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG2, u1BIC, REG_LVDSTX_PLL_CFG2_VPLL_BIC);
	vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG3, u1BIR, REG_LVDSTX_PLL_CFG3_VPLL_BIR);
	#endif
}

void vDrvLvdsVOPLLAnalogTest(UINT8 u1mode)
{
	if (u1mode==1)//74.25M_DDDS_OpenLoop
	{
		SET_DDDSFreeRun();		
	}
	else if (u1mode==2) //148.5M_DDDS_OpenLoop(Hi-speed)
	{
		vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2)|P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)
											| P_Fld(1,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));
		vUtDelay2us(200);
	}
	else if (u1mode==3)//81M_XSTAL
	{
		vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 2, FLD_RG_DDDS1_CKSEL);  //XSTAL from DDDS1
														   //DDDS1 output clock selection
	                                                       //2'b00: Single-end DDS clock duty <50%
	                                                       //2'b01: DDS clock /2 duty = 50%
	                                                       //2'b1X: from Xtal 27MHz
	#if ENABLE_DDDS2_FEEDBACK
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 2, FLD_RG_DDDS2_CKSEL); //XSTAL from DDDS2
	#endif														  
		vUtDelay2us(200);
		vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_PREDIV)|P_Fld(0x01, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL)
											|P_Fld(0x17, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV));
		vUtDelay2us(200);
	#if 0
		if(LVDS_OUTPUT_PORT == FOUR_PORT)
		{
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1,P_Fld(3,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2)|P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)
			   									|P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));
		}
		else
	#endif
		{
			vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1,P_Fld(2,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2)|P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)
												|P_Fld(1,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));
		}
		vUtDelay2us(200);			
	}	
	else if (u1mode==4)//162M_XSTAL
	{
		vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 2, FLD_RG_DDDS1_CKSEL);  //XSTAL from DDDS1
																//DDDS1 output clock selection
		                                                       //2'b00: Single-end DDS clock duty <50%
		                                                       //2'b01: DDS clock /2 duty = 50%
		                                                           //2'b1X: from Xtal 27MHz
	#if ENABLE_DDDS2_FEEDBACK
        vIO32WriteFldAlign(REG_PLL_GROUP_CFG10, 2, FLD_RG_DDDS2_CKSEL); //XSTAL from DDDS2
	#endif																   
		vUtDelay2us(200);
		vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1, P_Fld(0x00,REG_LVDSTX_PLL_CFG1_VPLL_PREDIV)|P_Fld(0x01, REG_LVDSTX_PLL_CFG1_VPLL_FBKSEL)
											|P_Fld(0x17, REG_LVDSTX_PLL_CFG1_VPLL_FBKDIV));
		vUtDelay2us(200);				
		vIO32WriteFldMulti(REG_LVDSTX_PLL_CFG1,P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV2)|P_Fld(0,REG_LVDSTX_PLL_CFG1_VPLL_TXCLK_DIV)
												|P_Fld(1,REG_LVDSTX_PLL_CFG1_VPLL_LVDS_DPIX_DIV2));
		vUtDelay2us(200);						
	}

}

#ifdef VOPLL_Debug
#define CAL_SRC_APLL2 0x5
#define AD_ARMPLL_CK1500M 0x4d
#define SRC_DMUXPLL_MONCLK 0x53
#define SRC_G3DPLL_MONCLK  0x54
#define SRC_HPCPLL_MONCLK 0x1
#define SRC_SYSPLL_CLK 0x2
#define SRC_VDECPLL_MONCLK 0x55
#define SRC_SAWLESSPLL_CLK 0x0
#define AD_VDECSOCPLL_MONCLK 0x6
#endif

void vDrvChkPLLFreq(void)
{	
	#ifdef VOPLL_Debug
	LOG(0,"[PLL]CAL_SRC_APLL2=%d \n",_CalGetPLLCounter(CAL_SRC_APLL2));	
	LOG(0,"[PLL]AD_ARMPLL_CK1500M=%d \n",_CalGetPLLCounter(AD_ARMPLL_CK1500M));	
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_MONCK_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_MONREF_EN);	
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TSTCK_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_A2DCK_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 0x4, FLD_RG_PLLGP_TST_SEL);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 0x4, FLD_RG_PLLGP_DIV2_SEL);	
	LOG(0,"[PLL]CAL_SRC_DMUXPLL_MONCLK=%d \n",_CalGetPLLCounter(SRC_DMUXPLL_MONCLK));
	LOG(0,"[PLL]CAL_SRC_G3DPLL_MONCLK=%d \n",_CalGetPLLCounter(SRC_G3DPLL_MONCLK));
	LOG(0,"[PLL]CAL_SRC_HPCPLL_MONCLK=%d \n",_CalGetPLLCounter(SRC_HPCPLL_MONCLK));
	LOG(0,"[PLL]SRC_SYSPLL_CLK=%d \n",_CalGetPLLCounter(SRC_SYSPLL_CLK));	
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 0x3, FLD_RG_PLLGP_TST_SEL);	
	LOG(0,"[PLL]CAL_SRC_VDECPLL_MONCLK=%d \n",_CalGetPLLCounter(SRC_VDECPLL_MONCLK));
	LOG(0,"[PLL]SRC_SAWLESSPLL_CLK=%d \n",_CalGetPLLCounter(SRC_SAWLESSPLL_CLK));
	LOG(0,"[PLL]AD_VDECSOCPLL_MONCLK=%d \n",_CalGetPLLCounter(AD_VDECSOCPLL_MONCLK));
	#endif
}


void vPLLVCOMonOff(void)
{
	#ifdef VOPLL_Debug
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG6, 0, FLD_RG_APLL2_MONVC_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 0, FLD_RG_DMUXPLL_MONVC_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG3, 0, FLD_RG_G3DPLL_MONVC_EN);	
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG0, 0, FLD_RG_SYSPLL_MONVC_EN);		
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG1, 0, FLD_RG_VDECPLL_MONVC_EN);			
	vIO32WriteFldAlign(REG_ARMPLL_CFG0, 0, FLD_RG_ARMPLL_MONVC_EN);
	vIO32WriteFldAlign(REG_HPCPLL_CFG0, 0, FLD_RG_HPCPLL_MONVC_EN);	
	vIO32WriteFldAlign(REG_IFPLL_CFG1, 0, FLD_RG_IFPLL_MONVC_EN);
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG2, 0, FLD_RG_VDECSOCPLL_MONVC_EN);
	#endif
}

#define FLD_RG_DMTOP_REV1_2_0 Fld(3,16,AC_MSKB2)//[18:16]

void vDrvPLLVCO_TestMode(UINT8 u1Mode)
{
	#ifdef VOPLL_Debug
	vPLLVCOMonOff();
	vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 0, FLD_RG_PLLGP_TST_EN);
	HAL_Delay_us(400);
	switch(u1Mode)
	{
		case 1:
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG6, 1, FLD_RG_APLL2_MONVC_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG12, 0x10, FLD_RG_PLLGP_RESERVE);
//			vIO32WriteFldAlign(0x10028900, 0x21, FLD_RG_PLLGP_RESERVE);
			vIO32WriteFldAlign(PDWNC_CONCFG0,0x21,FLD_RG_CON_DCMETER_SEL_I);
			LOG(0,"APLL2 VCO Control voltage\n");
		break;

		case 2:
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_MONVC_EN);			
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_MONCK_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG4, 1, FLD_RG_DMUXPLL_MONREF_EN);			
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG12, 0x8, FLD_RG_PLLGP_RESERVE);
//			vIO32WriteFldAlign(0x10028900, 0x21, FLD_RG_PLLGP_RESERVE);	
			vIO32WriteFldAlign(PDWNC_CONCFG0,0x21,FLD_RG_CON_DCMETER_SEL_I);
			LOG(0,"DMUXPLL VCO Control voltage\n");
		break;

		case 3:
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG3, 1, FLD_RG_G3DPLL_MONVC_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG12, 0x4, FLD_RG_PLLGP_RESERVE);
//			vIO32WriteFldAlign(0x10028900, 0x21, FLD_RG_PLLGP_RESERVE);
			vIO32WriteFldAlign(PDWNC_CONCFG0,0x21,FLD_RG_CON_DCMETER_SEL_I);
			LOG(0,"G3DPLL VCO Control voltage\n");
		break;

		case 4:
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG0, 1, FLD_RG_SYSPLL_MONVC_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG12, 0x1, FLD_RG_PLLGP_RESERVE);
//			vIO32WriteFldAlign(0x10028900, 0x21, FLD_RG_PLLGP_RESERVE);
			vIO32WriteFldAlign(PDWNC_CONCFG0,0x21,FLD_RG_CON_DCMETER_SEL_I);			
			LOG(0,"syspll VCO Control voltage\n");
		break;

		case 5:
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG1, 1, FLD_RG_VDECPLL_MONVC_EN);				
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG12, 0x2, FLD_RG_PLLGP_RESERVE);
//			vIO32WriteFldAlign(0x10028900, 0x21, FLD_RG_PLLGP_RESERVE);
			vIO32WriteFldAlign(PDWNC_CONCFG0,0x21,FLD_RG_CON_DCMETER_SEL_I);
			LOG(0,"VDECPLL VCO Control voltage\n");
		break;

		case 6:
			vIO32WriteFldAlign(REG_ARMPLL_CFG0, 0x1, FLD_RG_ARMPLL_MONVC_EN);
			vIO32WriteFldAlign(REG_ARMPLL_CFG2, 0x1, FLD_RG_ARMPLL_TST_EN);			
			vIO32WriteFldAlign(REG_ARMPLL_CFG2, 0x2, FLD_RG_ARMPLL_RESERVE);
			LOG(0,"ARMCPLL VCO Control voltage\n");
		break;

		case 7:
			vIO32WriteFldAlign(REG_HPCPLL_CFG0, 0x1, FLD_RG_HPCPLL_MONVC_EN);
			vIO32WriteFldAlign(REG_HPCPLL_CFG2, 0x1, FLD_RG_HPCPLL_TST_EN);					
			vIO32WriteFldAlign(REG_HPCPLL_CFG2, 0x2, FLD_RG_HPCPLL_RESERVE);				
			LOG(0,"HPCPLL VCO Control voltage\n");
		break;

		case 8:
			vIO32WriteFldAlign(REG_IFPLL_CFG1, 0x1, FLD_RG_IFPLL_MONVC_EN);
			vIO32WriteFldAlign(REG_IFTOP_CFG2, 0x1, FLD_RG_DMTOP_REV1_2_0);					
			vIO32WriteFldAlign(PDWNC_CONCFG0, 0x25, FLD_RG_CON_DCMETER_SEL_I);				
			LOG(0,"IFPLL(SAWLESSPLL) VCO Control voltage\n");
		break;

   		case 9:
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG2, 1, FLD_RG_VDECSOCPLL_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG2, 1, FLD_RG_VDECSOCPLL_MONVC_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_TST_EN);
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG11, 1, FLD_RG_PLLGP_BIAS_EN);			
			vIO32WriteFldAlign(REG_PLL_GROUP_CFG12, 0x40, FLD_RG_PLLGP_RESERVE);
//			vIO32WriteFldAlign(0x10028900, 0x21, FLD_RG_PLLGP_RESERVE);
			vIO32WriteFldAlign(PDWNC_CONCFG0,0x21,FLD_RG_CON_DCMETER_SEL_I);
			LOG(0,"VDECSOCPLL VCO Control voltage\n");
        break;

		
		default:

		break;			


	}	
	#endif
}


#if defined(CC_FAST_INIT) || defined(CC_SUPPORT_STR)
void VOPLL_pm_resume(void)    
{
    fgVOPLLInit = FALSE;
	_fgVOPLLPowerOn = FALSE;
	_fgFBNeedSS = TRUE;
}
#endif

#if defined(CONFIG_OPM) || defined(CC_SUPPORT_STR)
extern UINT8 fgDDDSInit;
extern UINT8 fgLVDSonoff;
extern BOOL fgLVDSInit;
extern BOOL fgVB1Init;
void vDrvVOPLLSuspend(void)
{
    //clear power on/init flag
    vIO32WriteFldAlign(DDDS_08, 0, FLAG_VOPLL_POWERON);	
    vIO32WriteFldAlign(DDDS_08, 0, FLAG_VOPLL_INITIAL);	
    vIO32WriteFldAlign(DDDS_08, 0, FLAG_LVDS_INITIAL);	
    vIO32WriteFldAlign(DDDS_08, 0, FLAG_LVDS_ONOFF);	
    vIO32WriteFldAlign(DDDS_08, 0, FLAG_DDDS_INIT);	
	if(IS_VBYONE)
	{
		vIO32WriteFldAlign(DDDS_08, 0, FLAG_VB1_INITIAL);
		fgVB1Init = FALSE;
	}
    _fgVOPLLPowerOn=FALSE;
    fgVOPLLInit = FALSE;
#ifndef CC_MTK_LOADER
    fgLVDSInit=FALSE;
    fgLVDSonoff=FALSE;
#endif
    fgDDDSInit=FALSE;

    //VOPLL power down
    vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 1, REG_LVDSTX_PLL_CFG1_VPLL_PWD);
    
}
void vDrvVOPLLResume(void)
{
    //VOPLL power on
    vIO32WriteFldAlign(REG_LVDSTX_PLL_CFG1, 0, REG_LVDSTX_PLL_CFG1_VPLL_PWD);

}
#endif
