//
//  REGISTER.H  Register map include file
//

//#include "dramc_pi_api.h"

#define POS_BANK_NUM 12  // SW Virtaul base address position

#define Channel_A_DRAMC_NAO_BASE_ADDRESS    (IO_VIRT + 0x204000)//0x10204000
#define Channel_B_DRAMC_NAO_BASE_ADDRESS    (IO_VIRT + 0x20C000)//0x1020C000
#define Channel_C_DRAMC_NAO_BASE_ADDRESS    (IO_VIRT + 0x214000)//0x10214000
#define Channel_D_DRAMC_NAO_BASE_ADDRESS    (IO_VIRT + 0x21c000)//0x1021C000
#define Channel_A_DRAMC_AO_BASE_ADDRESS     (IO_VIRT + 0x202000)//0x10202000
#define Channel_B_DRAMC_AO_BASE_ADDRESS     (IO_VIRT + 0x20A000)//0x1020A000
#define Channel_C_DRAMC_AO_BASE_ADDRESS     (IO_VIRT + 0x212000)//0x10212000
#define Channel_D_DRAMC_AO_BASE_ADDRESS     (IO_VIRT + 0x21A000)//0x1021A000
#define Channel_A_PHY_BASE_ADDRESS          (IO_VIRT + 0x200000)//0x10200000
#define Channel_B_PHY_BASE_ADDRESS          (IO_VIRT + 0x208000)//0x10208000
#define Channel_C_PHY_BASE_ADDRESS          (IO_VIRT + 0x210000)//0x10210000
#define Channel_D_PHY_BASE_ADDRESS          (IO_VIRT + 0x218000)//0x10218000

//#define Channel_A_DMARB_BASE_ADDRESS          0x10060000

#define RG_FLD_FULL Fld(32,0,AC_FULLDW)//[31:0]


//#define A60501_BUILD_ERROR_TODO
#define DRAMC_NAO_BASE_ADDRESS Channel_A_DRAMC_NAO_BASE_ADDRESS

//Page DRAMC0_NAO_1
#define DRAMC_REG_TESTMODE (DRAMC_NAO_BASE_ADDRESS + 0x000)
    #define TESTMODE_TESTM_PAT0 Fld(8,24,AC_FULLB3)//[31:24]
#define DRAMC_REG_LBWDAT0 (DRAMC_NAO_BASE_ADDRESS + 0x004)
    #define LBWDAT0_LBWDATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_LBWDAT1 (DRAMC_NAO_BASE_ADDRESS + 0x008)
    #define LBWDAT1_LBWDATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_LBWDAT2 (DRAMC_NAO_BASE_ADDRESS + 0x00C)
    #define LBWDAT2_LBWDATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_LBWDAT3 (DRAMC_NAO_BASE_ADDRESS + 0x010)
    #define LBWDAT3_LBWDATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_CKPHCHK (DRAMC_NAO_BASE_ADDRESS + 0x020)
    #define CKPHCHK_CKPHCNTEN Fld(1,31,AC_MSKB3)//[31:31]
    #define CKPHCHK_CKPHCHKCYC Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_DMMONITOR (DRAMC_NAO_BASE_ADDRESS + 0x024)
    #define DMMONITOR_JMTRCNT Fld(16,16,AC_FULLW32)//[31:16]
    #define DMMONITOR_WDQ_MON_OPT Fld(1,4,AC_MSKB0)//[4:4]
    #define DMMONITOR_BUSMONEN_SW Fld(1,3,AC_MSKB0)//[3:3]
    #define DMMONITOR_MONPAUSE_SW Fld(1,2,AC_MSKB0)//[2:2]
    #define DMMONITOR_JMTR_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_TESTCHIP_DMA1 (DRAMC_NAO_BASE_ADDRESS + 0x030)
    #define TESTCHIP_DMA1_DMA_LP4MATAB_OPT Fld(1,12,AC_MSKB1)//[12:12]
    #define TESTCHIP_DMA1_DMAFIXPAT Fld(1,9,AC_MSKB1)//[9:9]
    #define TESTCHIP_DMA1_DMAEN_LOOP Fld(1,8,AC_MSKB1)//[8:8]
    #define TESTCHIP_DMA1_DMABURSTLEN Fld(3,4,AC_MSKB0)//[6:4]
    #define TESTCHIP_DMA1_DMA_MWR Fld(1,3,AC_MSKB0)//[3:3]
    #define TESTCHIP_DMA1_DMAPURERDEN Fld(1,2,AC_MSKB0)//[2:2]
    #define TESTCHIP_DMA1_DMAPUREWREN Fld(1,1,AC_MSKB0)//[1:1]
    #define TESTCHIP_DMA1_DMAEN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_MISC_STATUSA (DRAMC_NAO_BASE_ADDRESS + 0x080)
    #define MISC_STATUSA_DRAMC_IDLE_DCM Fld(1,31,AC_MSKB3)//[31:31]
    #define MISC_STATUSA_DRAMC_IDLE_STATUS Fld(1,30,AC_MSKB3)//[30:30]
    #define MISC_STATUSA_MANUTXUPD_DONE Fld(1,29,AC_MSKB3)//[29:29]
    #define MISC_STATUSA_REQDEPTH_UPD_DONE Fld(1,28,AC_MSKB3)//[28:28]
    #define MISC_STATUSA_REFRESH_QUEUE_CNT Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_STATUSA_REFRESH_OVER_CNT Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_STATUSA_SELFREF_SM Fld(3,17,AC_MSKB2)//[19:17]
    #define MISC_STATUSA_SREF_STATE Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_STATUSA_CKE1O_PRE Fld(1,14,AC_MSKB1)//[14:14]
    #define MISC_STATUSA_CKEO_PRE Fld(1,13,AC_MSKB1)//[13:13]
    #define MISC_STATUSA_DRAM_HWCFG Fld(1,12,AC_MSKB1)//[12:12]
    #define MISC_STATUSA_REFRESH_RATE Fld(3,8,AC_MSKB1)//[10:8]
    #define MISC_STATUSA_REQQUE_DEPTH Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_STATUSA_PG_VLD Fld(1,3,AC_MSKB0)//[3:3]
    #define MISC_STATUSA_REQQ_EMPTY Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_STATUSA_WRITE_DATA_BUFFER_EMPTY Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_STATUSA_WAIT_DLE Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SPECIAL_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x084)
    #define SPECIAL_STATUS_SREF_REQ Fld(1,31,AC_MSKB3)//[31:31]
    #define SPECIAL_STATUS_SREF_REQ_2Q Fld(1,30,AC_MSKB3)//[30:30]
    #define SPECIAL_STATUS_SC_DRAMC_QUEUE_ACK Fld(1,28,AC_MSKB3)//[28:28]
    #define SPECIAL_STATUS_SCARB_SM Fld(5,20,AC_MSKW32)//[24:20]
    #define SPECIAL_STATUS_SCSM Fld(5,12,AC_MSKW21)//[16:12]
    #define SPECIAL_STATUS_SPECIAL_STATUS Fld(1,11,AC_MSKB1)//[11:11]
    #define SPECIAL_STATUS_STBUPD_STOP Fld(1,8,AC_MSKB1)//[8:8]
    #define SPECIAL_STATUS_H_REFR_REQ Fld(1,7,AC_MSKB0)//[7:7]
    #define SPECIAL_STATUS_H_ZQCS_REQ Fld(1,6,AC_MSKB0)//[6:6]
    #define SPECIAL_STATUS_DQSOSCEN_PERIOD Fld(1,5,AC_MSKB0)//[5:5]
    #define SPECIAL_STATUS_H_DQSOSCEN_REQ Fld(1,4,AC_MSKB0)//[4:4]
    #define SPECIAL_STATUS_H_ZQLCAL_REQ Fld(1,2,AC_MSKB0)//[2:2]
    #define SPECIAL_STATUS_H_ZQLAT_REQ Fld(1,1,AC_MSKB0)//[1:1]
    #define SPECIAL_STATUS_SPECIAL_COMMAND_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SPCMDRESP (DRAMC_NAO_BASE_ADDRESS + 0x088)
    #define SPCMDRESP_WRFIFO_RESPONSE Fld(1,31,AC_MSKB3)//[31:31]
    #define SPCMDRESP_RDFIFO_RESPONSE Fld(1,30,AC_MSKB3)//[30:30]
    #define SPCMDRESP_DVFS_RESPONSE Fld(1,16,AC_MSKB2)//[16:16]
    #define SPCMDRESP_MPRW_RESPONSE Fld(1,13,AC_MSKB1)//[13:13]
    #define SPCMDRESP_ACT_RESPONSE Fld(1,12,AC_MSKB1)//[12:12]
    #define SPCMDRESP_DQSOSCDIS_RESPONSE Fld(1,11,AC_MSKB1)//[11:11]
    #define SPCMDRESP_DQSOSCEN_RESPONSE Fld(1,10,AC_MSKB1)//[10:10]
    #define SPCMDRESP_MPCMAN_RESPONSE Fld(1,9,AC_MSKB1)//[9:9]
    #define SPCMDRESP_STEST_RESPONSE Fld(1,8,AC_MSKB1)//[8:8]
    #define SPCMDRESP_RDDQC_RESPONSE Fld(1,7,AC_MSKB0)//[7:7]
    #define SPCMDRESP_ZQLAT_RESPONSE Fld(1,6,AC_MSKB0)//[6:6]
    #define SPCMDRESP_TCMD_RESPONSE Fld(1,5,AC_MSKB0)//[5:5]
    #define SPCMDRESP_ZQC_RESPONSE Fld(1,4,AC_MSKB0)//[4:4]
    #define SPCMDRESP_AREF_RESPONSE Fld(1,3,AC_MSKB0)//[3:3]
    #define SPCMDRESP_PREA_RESPONSE Fld(1,2,AC_MSKB0)//[2:2]
    #define SPCMDRESP_MRR_RESPONSE Fld(1,1,AC_MSKB0)//[1:1]
    #define SPCMDRESP_MRW_RESPONSE Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_MRR_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x08C)
    #define MRR_STATUS_MRR_SW_REG Fld(16,16,AC_FULLW32)//[31:16]
    #define MRR_STATUS_MRR_REG Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_MRR_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x090)
    #define MRR_STATUS2_MR4_REG Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_MRRDATA0 (DRAMC_NAO_BASE_ADDRESS + 0x094)
    #define MRRDATA0_MRR_DATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRRDATA1 (DRAMC_NAO_BASE_ADDRESS + 0x098)
    #define MRRDATA1_MRR_DATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRRDATA2 (DRAMC_NAO_BASE_ADDRESS + 0x09C)
    #define MRRDATA2_MRR_DATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRRDATA3 (DRAMC_NAO_BASE_ADDRESS + 0x0A0)
    #define MRRDATA3_MRR_DATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRR0DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0A4)
    #define MRR0DATA0_MRR_DATA00 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRR0DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0A8)
    #define MRR0DATA1_MRR_DATA01 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRR0DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x0AC)
    #define MRR0DATA2_MRR_DATA02 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_MRR0DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x0B0)
    #define MRR0DATA3_MRR_DATA03 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DRS_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0B4)
    #define DRS_STATUS_SELFREF_SM_RK1 Fld(3,24,AC_MSKB3)//[26:24]
    #define DRS_STATUS_RK1_DRS_STATUS Fld(1,21,AC_MSKB2)//[21:21]
    #define DRS_STATUS_RK1_DRS_ACK Fld(1,20,AC_MSKB2)//[20:20]
    #define DRS_STATUS_RK1_DRS_RDY Fld(1,19,AC_MSKB2)//[19:19]
    #define DRS_STATUS_RK1_DRSLY_REQ Fld(1,18,AC_MSKB2)//[18:18]
    #define DRS_STATUS_RK1_DRS_2Q Fld(1,17,AC_MSKB2)//[17:17]
    #define DRS_STATUS_RK1_DRS_REQ Fld(1,16,AC_MSKB2)//[16:16]
    #define DRS_STATUS_DRS_MONERR_REQ Fld(1,9,AC_MSKB1)//[9:9]
    #define DRS_STATUS_DRS_MONERR_ACK Fld(1,8,AC_MSKB1)//[8:8]
#define DRAMC_REG_JMETER_ST (DRAMC_NAO_BASE_ADDRESS + 0x0BC)
    #define JMETER_ST_JMTR_DONE Fld(1,31,AC_MSKB3)//[31:31]
    #define JMETER_ST_ONES_CNT Fld(15,16,AC_MSKW32)//[30:16]
    #define JMETER_ST_ZEROS_CNT Fld(15,0,AC_MSKW10)//[14:0]
#define DRAMC_REG_TCMDO1LAT (DRAMC_NAO_BASE_ADDRESS + 0x0C0)
    #define TCMDO1LAT_CATRAIN_CMP_CPT Fld(1,31,AC_MSKB3)//[31:31]
    #define TCMDO1LAT_CATRAIN_CMP_ERR Fld(6,24,AC_MSKB3)//[29:24]
    #define TCMDO1LAT_CATRAIN_CMP_ERR0 Fld(6,16,AC_MSKB2)//[21:16]
    #define TCMDO1LAT_TCMD_O1_LATCH_DATA1 Fld(6,8,AC_MSKB1)//[13:8]
    #define TCMDO1LAT_TCMD_O1_LATCH_DATA0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RDQC_CMP (DRAMC_NAO_BASE_ADDRESS + 0x0C4)
    #define RDQC_CMP_RDDQC_CMP1_ERR Fld(16,16,AC_FULLW32)//[31:16]
    #define RDQC_CMP_RDDQC_CMP0_ERR Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_CKPHCHK_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0C8)
    #define CKPHCHK_STATUS_CKPHCHK_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_HWMRR_PUSH2POP_CNT (DRAMC_NAO_BASE_ADDRESS + 0x10C)
    #define HWMRR_PUSH2POP_CNT_HWMRR_PUSH2POP_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_HWMRR_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x110)
    #define HWMRR_STATUS_MRR_CNT_OVER_FULL Fld(1,31,AC_MSKB3)//[31:31]
    #define HWMRR_STATUS_MRR_CNT_UNDER_FULL Fld(1,30,AC_MSKB3)//[30:30]
    #define HWMRR_STATUS_OV_P2P_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_TESTRPT (DRAMC_NAO_BASE_ADDRESS + 0x120)
    #define TESTRPT_CALI_DONE_MON Fld(1,28,AC_MSKB3)//[28:28]
    #define TESTRPT_LB_CMP_FAIL Fld(1,24,AC_MSKB3)//[24:24]
    #define TESTRPT_TESTSTAT Fld(3,20,AC_MSKB2)//[22:20]
    #define TESTRPT_DLE_CNT_OK_RK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define TESTRPT_DLE_CNT_OK_RK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define TESTRPT_DM_CMP_ERR_RK1 Fld(1,5,AC_MSKB0)//[5:5]
    #define TESTRPT_DM_CMP_ERR_RK0 Fld(1,4,AC_MSKB0)//[4:4]
    #define TESTRPT_DM_CMP_CPT_RK1 Fld(1,1,AC_MSKB0)//[1:1]
    #define TESTRPT_DM_CMP_CPT_RK0 Fld(1,0,AC_MSKB0)//[0:0]
    #define TESTRPT_CALI_RESULT Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_CMP_ERR (DRAMC_NAO_BASE_ADDRESS + 0x124)
    #define CMP_ERR_CMP_ERR Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TEST_ABIT_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x128)
    #define TEST_ABIT_STATUS1_TEST_ABIT_ERR1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TEST_ABIT_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x12C)
    #define TEST_ABIT_STATUS2_TEST_ABIT_ERR2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TEST_ABIT_STATUS3 (DRAMC_NAO_BASE_ADDRESS + 0x130)
    #define TEST_ABIT_STATUS3_TEST_ABIT_ERR3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TEST_ABIT_STATUS4 (DRAMC_NAO_BASE_ADDRESS + 0x134)
    #define TEST_ABIT_STATUS4_TEST_ABIT_ERR4 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQSDLY0 (DRAMC_NAO_BASE_ADDRESS + 0x150)
    #define DQSDLY0_DEL3DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define DQSDLY0_DEL2DLY Fld(7,16,AC_MSKB2)//[22:16]
    #define DQSDLY0_DEL1DLY Fld(7,8,AC_MSKB1)//[14:8]
    #define DQSDLY0_DEL0DLY Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_DQ_CAL_MAX_0 (DRAMC_NAO_BASE_ADDRESS + 0x154)
    #define DQ_CAL_MAX_0_DQ0_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_0_DQ0_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_0_DQ0_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_0_DQ0_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_1 (DRAMC_NAO_BASE_ADDRESS + 0x158)
    #define DQ_CAL_MAX_1_DQ0_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_1_DQ0_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_1_DQ0_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_1_DQ0_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_2 (DRAMC_NAO_BASE_ADDRESS + 0x15C)
    #define DQ_CAL_MAX_2_DQ1_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_2_DQ1_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_2_DQ1_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_2_DQ1_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_3 (DRAMC_NAO_BASE_ADDRESS + 0x160)
    #define DQ_CAL_MAX_3_DQ1_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_3_DQ1_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_3_DQ1_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_3_DQ1_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_4 (DRAMC_NAO_BASE_ADDRESS + 0x164)
    #define DQ_CAL_MAX_4_DQ2_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_4_DQ2_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_4_DQ2_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_4_DQ2_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_5 (DRAMC_NAO_BASE_ADDRESS + 0x168)
    #define DQ_CAL_MAX_5_DQ2_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_5_DQ2_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_5_DQ2_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_5_DQ2_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_6 (DRAMC_NAO_BASE_ADDRESS + 0x16C)
    #define DQ_CAL_MAX_6_DQ3_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_6_DQ3_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_6_DQ3_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_6_DQ3_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQ_CAL_MAX_7 (DRAMC_NAO_BASE_ADDRESS + 0x170)
    #define DQ_CAL_MAX_7_DQ3_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQ_CAL_MAX_7_DQ3_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQ_CAL_MAX_7_DQ3_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQ_CAL_MAX_7_DQ3_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_0 (DRAMC_NAO_BASE_ADDRESS + 0x174)
    #define DQS_CAL_MIN_0_DQS0_3_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_0_DQS0_2_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_0_DQS0_1_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_0_DQS0_0_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_1 (DRAMC_NAO_BASE_ADDRESS + 0x178)
    #define DQS_CAL_MIN_1_DQS0_7_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_1_DQS0_6_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_1_DQS0_5_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_1_DQS0_4_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_2 (DRAMC_NAO_BASE_ADDRESS + 0x17C)
    #define DQS_CAL_MIN_2_DQS1_3_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_2_DQS1_2_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_2_DQS1_1_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_2_DQS1_0_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_3 (DRAMC_NAO_BASE_ADDRESS + 0x180)
    #define DQS_CAL_MIN_3_DQS1_7_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_3_DQS1_6_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_3_DQS1_5_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_3_DQS1_4_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_4 (DRAMC_NAO_BASE_ADDRESS + 0x184)
    #define DQS_CAL_MIN_4_DQS2_3_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_4_DQS2_2_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_4_DQS2_1_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_4_DQS2_0_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_5 (DRAMC_NAO_BASE_ADDRESS + 0x188)
    #define DQS_CAL_MIN_5_DQS2_7_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_5_DQS2_6_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_5_DQS2_5_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_5_DQS2_4_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_6 (DRAMC_NAO_BASE_ADDRESS + 0x18C)
    #define DQS_CAL_MIN_6_DQS3_3_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_6_DQS3_2_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_6_DQS3_1_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_6_DQS3_0_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MIN_7 (DRAMC_NAO_BASE_ADDRESS + 0x190)
    #define DQS_CAL_MIN_7_DQS3_7_DLY_MIN Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MIN_7_DQS3_6_DLY_MIN Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MIN_7_DQS3_5_DLY_MIN Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MIN_7_DQS3_4_DLY_MIN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_0 (DRAMC_NAO_BASE_ADDRESS + 0x194)
    #define DQS_CAL_MAX_0_DQS0_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_0_DQS0_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_0_DQS0_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_0_DQS0_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_1 (DRAMC_NAO_BASE_ADDRESS + 0x198)
    #define DQS_CAL_MAX_1_DQS0_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_1_DQS0_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_1_DQS0_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_1_DQS0_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_2 (DRAMC_NAO_BASE_ADDRESS + 0x19C)
    #define DQS_CAL_MAX_2_DQS1_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_2_DQS1_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_2_DQS1_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_2_DQS1_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_3 (DRAMC_NAO_BASE_ADDRESS + 0x1A0)
    #define DQS_CAL_MAX_3_DQS1_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_3_DQS1_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_3_DQS1_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_3_DQS1_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_4 (DRAMC_NAO_BASE_ADDRESS + 0x1A4)
    #define DQS_CAL_MAX_4_DQS2_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_4_DQS2_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_4_DQS2_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_4_DQS2_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_5 (DRAMC_NAO_BASE_ADDRESS + 0x1A8)
    #define DQS_CAL_MAX_5_DQS2_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_5_DQS2_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_5_DQS2_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_5_DQS2_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_6 (DRAMC_NAO_BASE_ADDRESS + 0x1AC)
    #define DQS_CAL_MAX_6_DQS3_3_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_6_DQS3_2_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_6_DQS3_1_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_6_DQS3_0_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQS_CAL_MAX_7 (DRAMC_NAO_BASE_ADDRESS + 0x1B0)
    #define DQS_CAL_MAX_7_DQS3_7_DLY_MAX Fld(8,24,AC_FULLB3)//[31:24]
    #define DQS_CAL_MAX_7_DQS3_6_DLY_MAX Fld(8,16,AC_FULLB2)//[23:16]
    #define DQS_CAL_MAX_7_DQS3_5_DLY_MAX Fld(8,8,AC_FULLB1)//[15:8]
    #define DQS_CAL_MAX_7_DQS3_4_DLY_MAX Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQICAL0 (DRAMC_NAO_BASE_ADDRESS + 0x1B4)
    #define DQICAL0_DQ3_DLY_MAX Fld(7,24,AC_MSKB3)//[30:24]
    #define DQICAL0_DQ2_DLY_MAX Fld(7,16,AC_MSKB2)//[22:16]
    #define DQICAL0_DQ1_DLY_MAX Fld(7,8,AC_MSKB1)//[14:8]
    #define DQICAL0_DQ0_DLY_MAX Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_DQICAL1 (DRAMC_NAO_BASE_ADDRESS + 0x1B8)
    #define DQICAL1_DQS3_DLY_MIN Fld(7,24,AC_MSKB3)//[30:24]
    #define DQICAL1_DQS2_DLY_MIN Fld(7,16,AC_MSKB2)//[22:16]
    #define DQICAL1_DQS1_DLY_MIN Fld(7,8,AC_MSKB1)//[14:8]
    #define DQICAL1_DQS0_DLY_MIN Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_DQICAL2 (DRAMC_NAO_BASE_ADDRESS + 0x1BC)
    #define DQICAL2_DQS3_DLY_MAX Fld(7,24,AC_MSKB3)//[30:24]
    #define DQICAL2_DQS2_DLY_MAX Fld(7,16,AC_MSKB2)//[22:16]
    #define DQICAL2_DQS1_DLY_MAX Fld(7,8,AC_MSKB1)//[14:8]
    #define DQICAL2_DQS0_DLY_MAX Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_DQICAL3 (DRAMC_NAO_BASE_ADDRESS + 0x1C0)
    #define DQICAL3_DQS3_DLY_AVG Fld(7,24,AC_MSKB3)//[30:24]
    #define DQICAL3_DQS2_DLY_AVG Fld(7,16,AC_MSKB2)//[22:16]
    #define DQICAL3_DQS1_DLY_AVG Fld(7,8,AC_MSKB1)//[14:8]
    #define DQICAL3_DQS0_DLY_AVG Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x200)
    #define TESTCHIP_DMA_STATUS1_DMA_STATE Fld(4,4,AC_MSKB0)//[7:4]
    #define TESTCHIP_DMA_STATUS1_DMACMPERR Fld(1,3,AC_MSKB0)//[3:3]
    #define TESTCHIP_DMA_STATUS1_DMA_BUF_AVAIL Fld(1,2,AC_MSKB0)//[2:2]
    #define TESTCHIP_DMA_STATUS1_DMASTATUS Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x204)
    #define TESTCHIP_DMA_STATUS2_DMACMPERR_BIT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS3 (DRAMC_NAO_BASE_ADDRESS + 0x208)
    #define TESTCHIP_DMA_STATUS3_DMA_DATA_BUFFER0_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS4 (DRAMC_NAO_BASE_ADDRESS + 0x20C)
    #define TESTCHIP_DMA_STATUS4_DMA_DATA_BUFFER0_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS5 (DRAMC_NAO_BASE_ADDRESS + 0x210)
    #define TESTCHIP_DMA_STATUS5_DMA_DATA_BUFFER0_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS6 (DRAMC_NAO_BASE_ADDRESS + 0x214)
    #define TESTCHIP_DMA_STATUS6_DMA_DATA_BUFFER0_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS7 (DRAMC_NAO_BASE_ADDRESS + 0x218)
    #define TESTCHIP_DMA_STATUS7_DMA_DATA_BUFFER1_31_0_ Fld(32,0,AC_FULLDW)//[31:0]

//Page DRAMC_NAO_2
#define DRAMC_REG_TESTCHIP_DMA_STATUS8 (DRAMC_NAO_BASE_ADDRESS + 0x21C)
    #define TESTCHIP_DMA_STATUS8_DMA_DATA_BUFFER1_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS9 (DRAMC_NAO_BASE_ADDRESS + 0x220)
    #define TESTCHIP_DMA_STATUS9_DMA_DATA_BUFFER1_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS10 (DRAMC_NAO_BASE_ADDRESS + 0x224)
    #define TESTCHIP_DMA_STATUS10_DMA_DATA_BUFFE1_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS11 (DRAMC_NAO_BASE_ADDRESS + 0x228)
    #define TESTCHIP_DMA_STATUS11_DMA_DATA_BUFFER2_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS12 (DRAMC_NAO_BASE_ADDRESS + 0x22C)
    #define TESTCHIP_DMA_STATUS12_DMA_DATA_BUFFER2_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS13 (DRAMC_NAO_BASE_ADDRESS + 0x230)
    #define TESTCHIP_DMA_STATUS13_DMA_DATA_BUFFER2_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS14 (DRAMC_NAO_BASE_ADDRESS + 0x234)
    #define TESTCHIP_DMA_STATUS14_DMA_DATA_BUFFER2_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS15 (DRAMC_NAO_BASE_ADDRESS + 0x238)
    #define TESTCHIP_DMA_STATUS15_DMA_DATA_BUFFER3_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS16 (DRAMC_NAO_BASE_ADDRESS + 0x23C)
    #define TESTCHIP_DMA_STATUS16_DMA_DATA_BUFFER3_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS17 (DRAMC_NAO_BASE_ADDRESS + 0x240)
    #define TESTCHIP_DMA_STATUS17_DMA_DATA_BUFFER3_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS18 (DRAMC_NAO_BASE_ADDRESS + 0x244)
    #define TESTCHIP_DMA_STATUS18_DMA_DATA_BUFFER3_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS19 (DRAMC_NAO_BASE_ADDRESS + 0x248)
    #define TESTCHIP_DMA_STATUS19_DMA_DATA_BUFFER4_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS20 (DRAMC_NAO_BASE_ADDRESS + 0x24C)
    #define TESTCHIP_DMA_STATUS20_DMA_DATA_BUFFER4_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS21 (DRAMC_NAO_BASE_ADDRESS + 0x250)
    #define TESTCHIP_DMA_STATUS21_DMA_DATA_BUFFER4_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS22 (DRAMC_NAO_BASE_ADDRESS + 0x254)
    #define TESTCHIP_DMA_STATUS22_DMA_DATA_BUFFER4_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS23 (DRAMC_NAO_BASE_ADDRESS + 0x258)
    #define TESTCHIP_DMA_STATUS23_DMA_DATA_BUFFER5_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS24 (DRAMC_NAO_BASE_ADDRESS + 0x25C)
    #define TESTCHIP_DMA_STATUS24_DMA_DATA_BUFFER5_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS25 (DRAMC_NAO_BASE_ADDRESS + 0x260)
    #define TESTCHIP_DMA_STATUS25_DMA_DATA_BUFFER5_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS26 (DRAMC_NAO_BASE_ADDRESS + 0x264)
    #define TESTCHIP_DMA_STATUS26_DMA_DATA_BUFFER5_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS27 (DRAMC_NAO_BASE_ADDRESS + 0x268)
    #define TESTCHIP_DMA_STATUS27_DMA_DATA_BUFFER6_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS28 (DRAMC_NAO_BASE_ADDRESS + 0x26C)
    #define TESTCHIP_DMA_STATUS28_DMA_DATA_BUFFER6_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS29 (DRAMC_NAO_BASE_ADDRESS + 0x270)
    #define TESTCHIP_DMA_STATUS29_DMA_DATA_BUFFER6_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS30 (DRAMC_NAO_BASE_ADDRESS + 0x274)
    #define TESTCHIP_DMA_STATUS30_DMA_DATA_BUFFER6_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS31 (DRAMC_NAO_BASE_ADDRESS + 0x278)
    #define TESTCHIP_DMA_STATUS31_DMA_DATA_BUFFER7_31_0_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS32 (DRAMC_NAO_BASE_ADDRESS + 0x27C)
    #define TESTCHIP_DMA_STATUS32_DMA_DATA_BUFFER7_63_32_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS33 (DRAMC_NAO_BASE_ADDRESS + 0x280)
    #define TESTCHIP_DMA_STATUS33_DMA_DATA_BUFFER7_95_64_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_TESTCHIP_DMA_STATUS34 (DRAMC_NAO_BASE_ADDRESS + 0x284)
    #define TESTCHIP_DMA_STATUS34_DMA_DATA_BUFFER7_127_96_ Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_REFRESH_POP_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x300)
    #define REFRESH_POP_COUNTER_REFRESH_POP_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_FREERUN_26M_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x304)
    #define FREERUN_26M_COUNTER_FREERUN_26M_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DRAMC_IDLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x308)
    #define DRAMC_IDLE_COUNTER_DRAMC_IDLE_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_R2R_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x30C)
    #define R2R_PAGE_HIT_COUNTER_R2R_PAGE_HIT_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_R2R_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x310)
    #define R2R_PAGE_MISS_COUNTER_R2R_PAGE_MISS_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_R2R_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x314)
    #define R2R_INTERBANK_COUNTER_R2R_INTERBANK_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_R2W_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x318)
    #define R2W_PAGE_HIT_COUNTER_R2W_PAGE_HIT_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_R2W_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x31C)
    #define R2W_PAGE_MISS_COUNTER_R2W_PAGE_MISS_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_R2W_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x320)
    #define R2W_INTERBANK_COUNTER_R2W_INTERBANK_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_W2R_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x324)
    #define W2R_PAGE_HIT_COUNTER_W2R_PAGE_HIT_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_W2R_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x328)
    #define W2R_PAGE_MISS_COUNTER_W2R_PAGE_MISS_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_W2R_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x32C)
    #define W2R_INTERBANK_COUNTER_W2R_INTERBANK_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_W2W_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x330)
    #define W2W_PAGE_HIT_COUNTER_W2W_PAGE_HIT_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_W2W_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x334)
    #define W2W_PAGE_MISS_COUNTER_W2W_PAGE_MISS_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_W2W_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x338)
    #define W2W_INTERBANK_COUNTER_W2W_INTERBANK_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x33C)
    #define RK0_PRE_STANDBY_COUNTER_RK0_PRE_STANDBY_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x340)
    #define RK0_PRE_POWERDOWN_COUNTER_RK0_PRE_POWERDOWN_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x344)
    #define RK0_ACT_STANDBY_COUNTER_RK0_ACT_STANDBY_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x348)
    #define RK0_ACT_POWERDOWN_COUNTER_RK0_ACT_POWERDOWN_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x34C)
    #define RK1_PRE_STANDBY_COUNTER_RK1_PRE_STANDBY_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x350)
    #define RK1_PRE_POWERDOWN_COUNTER_RK1_PRE_POWERDOWN_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x354)
    #define RK1_ACT_STANDBY_COUNTER_RK1_ACT_STANDBY_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x358)
    #define RK1_ACT_POWERDOWN_COUNTER_RK1_ACT_POWERDOWN_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x35C)
    #define RK2_PRE_STANDBY_COUNTER_RK2_PRE_STANDBY_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x360)
    #define RK2_PRE_POWERDOWN_COUNTER_RK2_PRE_POWERDOWN_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x364)
    #define RK2_ACT_STANDBY_COUNTER_RK2_ACT_STANDBY_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x368)
    #define RK2_ACT_POWERDOWN_COUNTER_RK2_ACT_POWERDOWN_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ0_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x36C)
    #define DQ0_TOGGLE_COUNTER_DQ0_TOGGLE_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ1_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x370)
    #define DQ1_TOGGLE_COUNTER_DQ1_TOGGLE_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ2_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x374)
    #define DQ2_TOGGLE_COUNTER_DQ2_TOGGLE_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ3_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x378)
    #define DQ3_TOGGLE_COUNTER_DQ3_TOGGLE_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ0_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x37C)
    #define DQ0_TOGGLE_COUNTER_R_DQ0_TOGGLE_COUNTER_R Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ1_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x380)
    #define DQ1_TOGGLE_COUNTER_R_DQ1_TOGGLE_COUNTER_R Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ2_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x384)
    #define DQ2_TOGGLE_COUNTER_R_DQ2_TOGGLE_COUNTER_R Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ3_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x388)
    #define DQ3_TOGGLE_COUNTER_R_DQ3_TOGGLE_COUNTER_R Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_READ_BYTES_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x38C)
    #define READ_BYTES_COUNTER_READ_BYTES_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_WRITE_BYTES_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x390)
    #define WRITE_BYTES_COUNTER_WRITE_BYTES_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQSSAMPLEV (DRAMC_NAO_BASE_ADDRESS + 0x400)
    #define DQSSAMPLEV_PI_OVERFLOW Fld(4,12,AC_MSKB1)//[15:12]
    #define DQSSAMPLEV_SAMPLE_OUT1_DQS3 Fld(1,3,AC_MSKB0)//[3:3]
    #define DQSSAMPLEV_SAMPLE_OUT1_DQS2 Fld(1,2,AC_MSKB0)//[2:2]
    #define DQSSAMPLEV_SAMPLE_OUT1_DQS1 Fld(1,1,AC_MSKB0)//[1:1]
    #define DQSSAMPLEV_SAMPLE_OUT1_DQS0 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_DQSGNWCNT0 (DRAMC_NAO_BASE_ADDRESS + 0x408)
    #define DQSGNWCNT0_DQS1R_GATING_COUNTER Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSGNWCNT0_DQS1F_GATING_COUNTER Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSGNWCNT0_DQS0R_GATING_COUNTER Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSGNWCNT0_DQS0F_GATING_COUNTER Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQSGNWCNT1 (DRAMC_NAO_BASE_ADDRESS + 0x40C)
    #define DQSGNWCNT1_DQS3R_GATING_COUNTER Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSGNWCNT1_DQS3F_GATING_COUNTER Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSGNWCNT1_DQS2R_GATING_COUNTER Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSGNWCNT1_DQS2F_GATING_COUNTER Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQSGNWCNT2 (DRAMC_NAO_BASE_ADDRESS + 0x410)
    #define DQSGNWCNT2_DQS0R_PRE_GATING_COUNTER Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSGNWCNT2_DQS0F_PRE_GATING_COUNTER Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSGNWCNT2_DQS0R_POS_GATING_COUNTER Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSGNWCNT2_DQS0F_POS_GATING_COUNTER Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQSGNWCNT3 (DRAMC_NAO_BASE_ADDRESS + 0x414)
    #define DQSGNWCNT3_DQS1R_PRE_GATING_COUNTER Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSGNWCNT3_DQS1F_PRE_GATING_COUNTER Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSGNWCNT3_DQS1R_POS_GATING_COUNTER Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSGNWCNT3_DQS1F_POS_GATING_COUNTER Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQSGNWCNT4 (DRAMC_NAO_BASE_ADDRESS + 0x418)
    #define DQSGNWCNT4_DQS2R_PRE_GATING_COUNTER Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSGNWCNT4_DQS2F_PRE_GATING_COUNTER Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSGNWCNT4_DQS2R_POS_GATING_COUNTER Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSGNWCNT4_DQS2F_POS_GATING_COUNTER Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQSGNWCNT5 (DRAMC_NAO_BASE_ADDRESS + 0x41C)
    #define DQSGNWCNT5_DQS3R_PRE_GATING_COUNTER Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSGNWCNT5_DQS3F_PRE_GATING_COUNTER Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSGNWCNT5_DQS3R_POS_GATING_COUNTER Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSGNWCNT5_DQS3F_POS_GATING_COUNTER Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_TOGGLE_CNT (DRAMC_NAO_BASE_ADDRESS + 0x420)
    #define TOGGLE_CNT_TOGGLE_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQS0_ERR_CNT (DRAMC_NAO_BASE_ADDRESS + 0x424)
    #define DQS0_ERR_CNT_DQS0_ERR_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ_ERR_CNT0 (DRAMC_NAO_BASE_ADDRESS + 0x428)
    #define DQ_ERR_CNT0_DQ_ERR_CNT0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQS1_ERR_CNT (DRAMC_NAO_BASE_ADDRESS + 0x42C)
    #define DQS1_ERR_CNT_DQS1_ERR_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ_ERR_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x430)
    #define DQ_ERR_CNT1_DQ_ERR_CNT1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQS2_ERR_CNT (DRAMC_NAO_BASE_ADDRESS + 0x434)
    #define DQS2_ERR_CNT_DQS2_ERR_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ_ERR_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x438)
    #define DQ_ERR_CNT2_DQ_ERR_CNT2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQS3_ERR_CNT (DRAMC_NAO_BASE_ADDRESS + 0x43C)
    #define DQS3_ERR_CNT_DQS3_ERR_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_DQ_ERR_CNT3 (DRAMC_NAO_BASE_ADDRESS + 0x440)
    #define DQ_ERR_CNT3_DQ_ERR_CNT3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_IORGCNT (DRAMC_NAO_BASE_ADDRESS + 0x450)
    #define IORGCNT_IO_RING_COUNTER Fld(16,16,AC_FULLW32)//[31:16]
    #define IORGCNT_IO_RING_COUNTER_K Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_DQSG_RETRY_STATE (DRAMC_NAO_BASE_ADDRESS + 0x454)
    #define DQSG_RETRY_STATE_DQSG_RETRY_4TH_ST Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSG_RETRY_STATE_DQSG_RETRY_3RD_ST Fld(8,16,AC_FULLB2)//[23:16]
    #define DQSG_RETRY_STATE_DQSG_RETRY_2ND_ST Fld(8,8,AC_FULLB1)//[15:8]
    #define DQSG_RETRY_STATE_DQSG_RETRY_1ST_ST Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_DQSG_RETRY_STATE1 (DRAMC_NAO_BASE_ADDRESS + 0x458)
    #define DQSG_RETRY_STATE1_DQSG_RETRY_5TH_ST Fld(8,24,AC_FULLB3)//[31:24]
    #define DQSG_RETRY_STATE1_R_MPDIV_SHU_GP_GATING_ERR Fld(3,19,AC_MSKB2)//[21:19]
    #define DQSG_RETRY_STATE1_R_OTHER_SHU_GP_GATING_ERR Fld(2,17,AC_MSKB2)//[18:17]
    #define DQSG_RETRY_STATE1_STB_GATING_ERR Fld(1,16,AC_MSKB2)//[16:16]
    #define DQSG_RETRY_STATE1_IMPCAL_P_ERROR Fld(1,9,AC_MSKB1)//[9:9]
    #define DQSG_RETRY_STATE1_IMPCAL_N_ERROR Fld(1,8,AC_MSKB1)//[8:8]
    #define DQSG_RETRY_STATE1_TDQSCK_DONE Fld(1,4,AC_MSKB0)//[4:4]
    #define DQSG_RETRY_STATE1_SELPH_RODTEN_USABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define DQSG_RETRY_STATE1_RETRY_DONE_ALL Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_IMPCAL_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x460)
    #define IMPCAL_STATUS1_DRVPDQS_SAVE2 Fld(5,25,AC_MSKB3)//[29:25]
    #define IMPCAL_STATUS1_DRVNDQS_SAVE2 Fld(5,20,AC_MSKW32)//[24:20]
    #define IMPCAL_STATUS1_DRVPDQS_SAVE1 Fld(5,15,AC_MSKW21)//[19:15]
    #define IMPCAL_STATUS1_DRVNDQS_SAVE1 Fld(5,10,AC_MSKB1)//[14:10]
    #define IMPCAL_STATUS1_DRVPDQ_SAVE2 Fld(5,5,AC_MSKW10)//[9:5]
    #define IMPCAL_STATUS1_DRVNDQ_SAVE2 Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_IMPCAL_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x464)
    #define IMPCAL_STATUS2_DRVPDQ_SAVE1 Fld(5,25,AC_MSKB3)//[29:25]
    #define IMPCAL_STATUS2_DRVNDQ_SAVE1 Fld(5,20,AC_MSKW32)//[24:20]
    #define IMPCAL_STATUS2_DRVPCMD_SAVE2 Fld(5,15,AC_MSKW21)//[19:15]
    #define IMPCAL_STATUS2_DRVNCMD_SAVE2 Fld(5,10,AC_MSKB1)//[14:10]
    #define IMPCAL_STATUS2_DRVPCMD_SAVE1 Fld(5,5,AC_MSKW10)//[9:5]
    #define IMPCAL_STATUS2_DRVNCMD_SAVE1 Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_DQDRV_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x468)
    #define DQDRV_STATUS_DQDRV_STATUS Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_CMDDRV_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x46C)
    #define CMDDRV_STATUS_CMDDRV_STATUS Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_CMDDRV1 (DRAMC_NAO_BASE_ADDRESS + 0x470)
    #define CMDDRV1_CMDDRV1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_CMDDRV2 (DRAMC_NAO_BASE_ADDRESS + 0x474)
    #define CMDDRV2_CMDDRV2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x600)
    #define RK0_DQSOSC_STATUS_MR19_REG Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_DQSOSC_STATUS_MR18_REG Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x604)
    #define RK0_DQSOSC_DELTA_DQSOSC_INT_RK0 Fld(1,19,AC_MSKB2)//[19:19]
    #define RK0_DQSOSC_DELTA_H_DQSOSCLSBR_REQ Fld(1,18,AC_MSKB2)//[18:18]
    #define RK0_DQSOSC_DELTA_DQSOCSR_RESPONSE Fld(1,17,AC_MSKB2)//[17:17]
    #define RK0_DQSOSC_DELTA_SIGN_RK0_DQSOSC_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define RK0_DQSOSC_DELTA_ABS_RK0_DQSOSC_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x608)
    #define RK0_DQSOSC_DELTA2_SIGN_RK0_DQSOSC_B1_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define RK0_DQSOSC_DELTA2_ABS_RK0_DQSOSC_B1_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x610)
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK0_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x614)
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK0_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x618)
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK0_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x61C)
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK0_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x620)
    #define RK0_DUMMY_RD_DATA0_DUMMY_RD_RK0_DATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x624)
    #define RK0_DUMMY_RD_DATA1_DUMMY_RD_RK0_DATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x628)
    #define RK0_DUMMY_RD_DATA2_DUMMY_RD_RK0_DATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x62C)
    #define RK0_DUMMY_RD_DATA3_DUMMY_RD_RK0_DATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x630)
    #define RK0_B0_STB_MAX_MIN_DLY_RK0_B0_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK0_B0_STB_MAX_MIN_DLY_RK0_B0_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK0_B1_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x634)
    #define RK0_B1_STB_MAX_MIN_DLY_RK0_B1_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK0_B1_STB_MAX_MIN_DLY_RK0_B1_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK0_B2_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x638)
    #define RK0_B2_STB_MAX_MIN_DLY_RK0_B2_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK0_B2_STB_MAX_MIN_DLY_RK0_B2_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK0_B3_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x63C)
    #define RK0_B3_STB_MAX_MIN_DLY_RK0_B3_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK0_B3_STB_MAX_MIN_DLY_RK0_B3_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK0_DQSIENDLY (DRAMC_NAO_BASE_ADDRESS + 0x640)
    #define RK0_DQSIENDLY_R0DQS3IENDLY Fld(7,24,AC_MSKB3)//[30:24]
    #define RK0_DQSIENDLY_R0DQS2IENDLY Fld(7,16,AC_MSKB2)//[22:16]
    #define RK0_DQSIENDLY_R0DQS1IENDLY Fld(7,8,AC_MSKB1)//[14:8]
    #define RK0_DQSIENDLY_R0DQS0IENDLY Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_RK0_DQSIENUIDLY (DRAMC_NAO_BASE_ADDRESS + 0x644)
    #define RK0_DQSIENUIDLY_R0DQS3IENUIDLY Fld(6,24,AC_MSKB3)//[29:24]
    #define RK0_DQSIENUIDLY_R0DQS2IENUIDLY Fld(6,16,AC_MSKB2)//[21:16]
    #define RK0_DQSIENUIDLY_R0DQS1IENUIDLY Fld(6,8,AC_MSKB1)//[13:8]
    #define RK0_DQSIENUIDLY_R0DQS0IENUIDLY Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_DQSIENUIDLY_P1 (DRAMC_NAO_BASE_ADDRESS + 0x648)
    #define RK0_DQSIENUIDLY_P1_R0DQS3IENUIDLY_P1 Fld(6,24,AC_MSKB3)//[29:24]
    #define RK0_DQSIENUIDLY_P1_R0DQS2IENUIDLY_P1 Fld(6,16,AC_MSKB2)//[21:16]
    #define RK0_DQSIENUIDLY_P1_R0DQS1IENUIDLY_P1 Fld(6,8,AC_MSKB1)//[13:8]
    #define RK0_DQSIENUIDLY_P1_R0DQS0IENUIDLY_P1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_DQS_STBCALDEC_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x650)
    #define RK0_DQS_STBCALDEC_CNT1_RK0_DQS1_STBCALDEC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_DQS_STBCALDEC_CNT1_RK0_DQS0_STBCALDEC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_DQS_STBCALDEC_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x654)
    #define RK0_DQS_STBCALDEC_CNT2_RK0_DQS3_STBCALDEC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_DQS_STBCALDEC_CNT2_RK0_DQS2_STBCALDEC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_DQS_STBCALINC_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x658)
    #define RK0_DQS_STBCALINC_CNT1_RK0_DQS1_STBCALINC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_DQS_STBCALINC_CNT1_RK0_DQS0_STBCALINC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_DQS_STBCALINC_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x65C)
    #define RK0_DQS_STBCALINC_CNT2_RK0_DQS3_STBCALINC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_DQS_STBCALINC_CNT2_RK0_DQS2_STBCALINC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x660)
    #define RK0_PI_DQ_CAL_RK0_B1_PI_CHANGE_DBG Fld(1,31,AC_MSKB3)//[31:31]
    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1_OVERFLOW Fld(1,30,AC_MSKB3)//[30:30]
    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define RK0_PI_DQ_CAL_RK0_B0_PI_CHANGE_DBG Fld(1,23,AC_MSKB2)//[23:23]
    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_OVERFLOW Fld(1,22,AC_MSKB2)//[22:22]
    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0 Fld(6,16,AC_MSKB2)//[21:16]
    #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B1_CAL Fld(6,8,AC_MSKB1)//[13:8]
    #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B0_CAL Fld(6,0,AC_MSKB0)//[5:0]

//Page DRAMC_NAO_3
#define DRAMC_REG_RK0_DQSG_RETRY_FLAG (DRAMC_NAO_BASE_ADDRESS + 0x664)
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL3 Fld(1,19,AC_MSKB2)//[19:19]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL2 Fld(1,18,AC_MSKB2)//[18:18]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL1 Fld(1,17,AC_MSKB2)//[17:17]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL0 Fld(1,16,AC_MSKB2)//[16:16]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE3 Fld(1,3,AC_MSKB0)//[3:3]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE1 Fld(1,1,AC_MSKB0)//[1:1]
    #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE0 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_RK0_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x668)
    #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B1_CAL Fld(6,8,AC_MSKB1)//[13:8]
    #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B0_CAL Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_DQS0_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x670)
    #define RK0_DQS0_STBCAL_CNT_R0_DQS0_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK0_DQS1_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x674)
    #define RK0_DQS1_STBCAL_CNT_R0_DQS1_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK0_DQS2_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x678)
    #define RK0_DQS2_STBCAL_CNT_R0_DQS2_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK0_DQS3_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x67C)
    #define RK0_DQS3_STBCAL_CNT_R0_DQS3_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_00 (DRAMC_NAO_BASE_ADDRESS + 0x680)
    #define RK0_B01_STB_DBG_INFO_00_RK0_B1_STB_DBG_INFO_00 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_00_RK0_B0_STB_DBG_INFO_00 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_01 (DRAMC_NAO_BASE_ADDRESS + 0x684)
    #define RK0_B01_STB_DBG_INFO_01_RK0_B1_STB_DBG_INFO_01 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_01_RK0_B0_STB_DBG_INFO_01 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_02 (DRAMC_NAO_BASE_ADDRESS + 0x688)
    #define RK0_B01_STB_DBG_INFO_02_RK0_B1_STB_DBG_INFO_02 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_02_RK0_B0_STB_DBG_INFO_02 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_03 (DRAMC_NAO_BASE_ADDRESS + 0x68C)
    #define RK0_B01_STB_DBG_INFO_03_RK0_B1_STB_DBG_INFO_03 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_03_RK0_B0_STB_DBG_INFO_03 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_04 (DRAMC_NAO_BASE_ADDRESS + 0x690)
    #define RK0_B01_STB_DBG_INFO_04_RK0_B1_STB_DBG_INFO_04 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_04_RK0_B0_STB_DBG_INFO_04 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_05 (DRAMC_NAO_BASE_ADDRESS + 0x694)
    #define RK0_B01_STB_DBG_INFO_05_RK0_B1_STB_DBG_INFO_05 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_05_RK0_B0_STB_DBG_INFO_05 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_06 (DRAMC_NAO_BASE_ADDRESS + 0x698)
    #define RK0_B01_STB_DBG_INFO_06_RK0_B1_STB_DBG_INFO_06 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_06_RK0_B0_STB_DBG_INFO_06 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_07 (DRAMC_NAO_BASE_ADDRESS + 0x69C)
    #define RK0_B01_STB_DBG_INFO_07_RK0_B1_STB_DBG_INFO_07 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_07_RK0_B0_STB_DBG_INFO_07 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_08 (DRAMC_NAO_BASE_ADDRESS + 0x6A0)
    #define RK0_B01_STB_DBG_INFO_08_RK0_B1_STB_DBG_INFO_08 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_08_RK0_B0_STB_DBG_INFO_08 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_09 (DRAMC_NAO_BASE_ADDRESS + 0x6A4)
    #define RK0_B01_STB_DBG_INFO_09_RK0_B1_STB_DBG_INFO_09 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_09_RK0_B0_STB_DBG_INFO_09 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_10 (DRAMC_NAO_BASE_ADDRESS + 0x6A8)
    #define RK0_B01_STB_DBG_INFO_10_RK0_B1_STB_DBG_INFO_10 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_10_RK0_B0_STB_DBG_INFO_10 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_11 (DRAMC_NAO_BASE_ADDRESS + 0x6AC)
    #define RK0_B01_STB_DBG_INFO_11_RK0_B1_STB_DBG_INFO_11 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_11_RK0_B0_STB_DBG_INFO_11 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_12 (DRAMC_NAO_BASE_ADDRESS + 0x6B0)
    #define RK0_B01_STB_DBG_INFO_12_RK0_B1_STB_DBG_INFO_12 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_12_RK0_B0_STB_DBG_INFO_12 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_13 (DRAMC_NAO_BASE_ADDRESS + 0x6B4)
    #define RK0_B01_STB_DBG_INFO_13_RK0_B1_STB_DBG_INFO_13 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_13_RK0_B0_STB_DBG_INFO_13 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_14 (DRAMC_NAO_BASE_ADDRESS + 0x6B8)
    #define RK0_B01_STB_DBG_INFO_14_RK0_B1_STB_DBG_INFO_14 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_14_RK0_B0_STB_DBG_INFO_14 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B01_STB_DBG_INFO_15 (DRAMC_NAO_BASE_ADDRESS + 0x6BC)
    #define RK0_B01_STB_DBG_INFO_15_RK0_B1_STB_DBG_INFO_15 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B01_STB_DBG_INFO_15_RK0_B0_STB_DBG_INFO_15 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_00 (DRAMC_NAO_BASE_ADDRESS + 0x6C0)
    #define RK0_B23_STB_DBG_INFO_00_RK0_B3_STB_DBG_INFO_00 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_00_RK0_B2_STB_DBG_INFO_00 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_01 (DRAMC_NAO_BASE_ADDRESS + 0x6C4)
    #define RK0_B23_STB_DBG_INFO_01_RK0_B3_STB_DBG_INFO_01 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_01_RK0_B2_STB_DBG_INFO_01 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_02 (DRAMC_NAO_BASE_ADDRESS + 0x6C8)
    #define RK0_B23_STB_DBG_INFO_02_RK0_B3_STB_DBG_INFO_02 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_02_RK0_B2_STB_DBG_INFO_02 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_03 (DRAMC_NAO_BASE_ADDRESS + 0x6CC)
    #define RK0_B23_STB_DBG_INFO_03_RK0_B3_STB_DBG_INFO_03 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_03_RK0_B2_STB_DBG_INFO_03 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_04 (DRAMC_NAO_BASE_ADDRESS + 0x6D0)
    #define RK0_B23_STB_DBG_INFO_04_RK0_B3_STB_DBG_INFO_04 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_04_RK0_B2_STB_DBG_INFO_04 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_05 (DRAMC_NAO_BASE_ADDRESS + 0x6D4)
    #define RK0_B23_STB_DBG_INFO_05_RK0_B3_STB_DBG_INFO_05 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_05_RK0_B2_STB_DBG_INFO_05 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_06 (DRAMC_NAO_BASE_ADDRESS + 0x6D8)
    #define RK0_B23_STB_DBG_INFO_06_RK0_B3_STB_DBG_INFO_06 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_06_RK0_B2_STB_DBG_INFO_06 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_07 (DRAMC_NAO_BASE_ADDRESS + 0x6DC)
    #define RK0_B23_STB_DBG_INFO_07_RK0_B3_STB_DBG_INFO_07 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_07_RK0_B2_STB_DBG_INFO_07 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_08 (DRAMC_NAO_BASE_ADDRESS + 0x6E0)
    #define RK0_B23_STB_DBG_INFO_08_RK0_B3_STB_DBG_INFO_08 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_08_RK0_B2_STB_DBG_INFO_08 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_09 (DRAMC_NAO_BASE_ADDRESS + 0x6E4)
    #define RK0_B23_STB_DBG_INFO_09_RK0_B3_STB_DBG_INFO_09 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_09_RK0_B2_STB_DBG_INFO_09 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_10 (DRAMC_NAO_BASE_ADDRESS + 0x6E8)
    #define RK0_B23_STB_DBG_INFO_10_RK0_B3_STB_DBG_INFO_10 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_10_RK0_B2_STB_DBG_INFO_10 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_11 (DRAMC_NAO_BASE_ADDRESS + 0x6EC)
    #define RK0_B23_STB_DBG_INFO_11_RK0_B3_STB_DBG_INFO_11 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_11_RK0_B2_STB_DBG_INFO_11 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_12 (DRAMC_NAO_BASE_ADDRESS + 0x6F0)
    #define RK0_B23_STB_DBG_INFO_12_RK0_B3_STB_DBG_INFO_12 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_12_RK0_B2_STB_DBG_INFO_12 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_13 (DRAMC_NAO_BASE_ADDRESS + 0x6F4)
    #define RK0_B23_STB_DBG_INFO_13_RK0_B3_STB_DBG_INFO_13 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_13_RK0_B2_STB_DBG_INFO_13 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_14 (DRAMC_NAO_BASE_ADDRESS + 0x6F8)
    #define RK0_B23_STB_DBG_INFO_14_RK0_B3_STB_DBG_INFO_14 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_14_RK0_B2_STB_DBG_INFO_14 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_B23_STB_DBG_INFO_15 (DRAMC_NAO_BASE_ADDRESS + 0x6FC)
    #define RK0_B23_STB_DBG_INFO_15_RK0_B3_STB_DBG_INFO_15 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK0_B23_STB_DBG_INFO_15_RK0_B2_STB_DBG_INFO_15 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x700)
    #define RK1_DQSOSC_STATUS_MR19_REG_RK1 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_DQSOSC_STATUS_MR18_REG_RK1 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x704)
    #define RK1_DQSOSC_DELTA_DQSOSC_INT_RK1 Fld(1,19,AC_MSKB2)//[19:19]
    #define RK1_DQSOSC_DELTA_H_DQSOSCLSBR_RK1_REQ Fld(1,18,AC_MSKB2)//[18:18]
    #define RK1_DQSOSC_DELTA_DQSOSCR_RK1_RESPONSE Fld(1,17,AC_MSKB2)//[17:17]
    #define RK1_DQSOSC_DELTA_SIGN_RK1_DQSOSC_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define RK1_DQSOSC_DELTA_ABS_RK1_DQSOSC_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x708)
    #define RK1_DQSOSC_DELTA2_SIGN_RK1_DQSOSC_B1_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define RK1_DQSOSC_DELTA2_ABS_RK1_DQSOSC_B1_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x710)
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK1_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x714)
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK1_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x718)
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK1_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x71C)
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK1_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x720)
    #define RK1_DUMMY_RD_DATA0_DUMMY_RD_RK1_DATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x724)
    #define RK1_DUMMY_RD_DATA1_DUMMY_RD_RK1_DATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x728)
    #define RK1_DUMMY_RD_DATA2_DUMMY_RD_RK1_DATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x72C)
    #define RK1_DUMMY_RD_DATA3_DUMMY_RD_RK1_DATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_B0_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x730)
    #define RK1_B0_STB_MAX_MIN_DLY_RK1_B0_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK1_B0_STB_MAX_MIN_DLY_RK1_B0_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK1_B1_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x734)
    #define RK1_B1_STB_MAX_MIN_DLY_RK1_B1_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK1_B1_STB_MAX_MIN_DLY_RK1_B1_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK1_B2_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x738)
    #define RK1_B2_STB_MAX_MIN_DLY_RK1_B2_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK1_B2_STB_MAX_MIN_DLY_RK1_B2_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK1_B3_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x73C)
    #define RK1_B3_STB_MAX_MIN_DLY_RK1_B3_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK1_B3_STB_MAX_MIN_DLY_RK1_B3_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK1_DQSIENDLY (DRAMC_NAO_BASE_ADDRESS + 0x740)
    #define RK1_DQSIENDLY_R1DQS3IENDLY Fld(7,24,AC_MSKB3)//[30:24]
    #define RK1_DQSIENDLY_R1DQS2IENDLY Fld(7,16,AC_MSKB2)//[22:16]
    #define RK1_DQSIENDLY_R1DQS1IENDLY Fld(7,8,AC_MSKB1)//[14:8]
    #define RK1_DQSIENDLY_R1DQS0IENDLY Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_RK1_DQSIENUIDLY (DRAMC_NAO_BASE_ADDRESS + 0x744)
    #define RK1_DQSIENUIDLY_R1DQS3IENUIDLY Fld(6,24,AC_MSKB3)//[29:24]
    #define RK1_DQSIENUIDLY_R1DQS2IENUIDLY Fld(6,16,AC_MSKB2)//[21:16]
    #define RK1_DQSIENUIDLY_R1DQS1IENUIDLY Fld(6,8,AC_MSKB1)//[13:8]
    #define RK1_DQSIENUIDLY_R1DQS0IENUIDLY Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_DQSIENUIDLY_P1 (DRAMC_NAO_BASE_ADDRESS + 0x748)
    #define RK1_DQSIENUIDLY_P1_R1DQS3IENUIDLY_P1 Fld(6,24,AC_MSKB3)//[29:24]
    #define RK1_DQSIENUIDLY_P1_R1DQS2IENUIDLY_P1 Fld(6,16,AC_MSKB2)//[21:16]
    #define RK1_DQSIENUIDLY_P1_R1DQS1IENUIDLY_P1 Fld(6,8,AC_MSKB1)//[13:8]
    #define RK1_DQSIENUIDLY_P1_R1DQS0IENUIDLY_P1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_DQS_STBCALDEC_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x750)
    #define RK1_DQS_STBCALDEC_CNT1_RK1_DQS1_STBCALDEC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_DQS_STBCALDEC_CNT1_RK1_DQS0_STBCALDEC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_DQS_STBCALDEC_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x754)
    #define RK1_DQS_STBCALDEC_CNT2_RK1_DQS3_STBCALDEC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_DQS_STBCALDEC_CNT2_RK1_DQS2_STBCALDEC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_DQS_STBCALINC_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x758)
    #define RK1_DQS_STBCALINC_CNT1_RK1_DQS1_STBCALINC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_DQS_STBCALINC_CNT1_RK1_DQS0_STBCALINC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_DQS_STBCALINC_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x75C)
    #define RK1_DQS_STBCALINC_CNT2_RK1_DQS3_STBCALINC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_DQS_STBCALINC_CNT2_RK1_DQS2_STBCALINC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x760)
    #define RK1_PI_DQ_CAL_RK1_B1_PI_CHANGE_DBG Fld(1,31,AC_MSKB3)//[31:31]
    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1_FLOW Fld(1,30,AC_MSKB3)//[30:30]
    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define RK1_PI_DQ_CAL_RK1_B0_PI_CHANGE_DBG Fld(1,23,AC_MSKB2)//[23:23]
    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_FLOW Fld(1,22,AC_MSKB2)//[22:22]
    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1 Fld(6,16,AC_MSKB2)//[21:16]
    #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B1_CAL Fld(6,8,AC_MSKB1)//[13:8]
    #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B0_CAL Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_DQSG_RETRY_FLAG (DRAMC_NAO_BASE_ADDRESS + 0x764)
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL3 Fld(1,19,AC_MSKB2)//[19:19]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL2 Fld(1,18,AC_MSKB2)//[18:18]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL1 Fld(1,17,AC_MSKB2)//[17:17]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL0 Fld(1,16,AC_MSKB2)//[16:16]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE3 Fld(1,3,AC_MSKB0)//[3:3]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE1 Fld(1,1,AC_MSKB0)//[1:1]
    #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE0 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_RK1_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x768)
    #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B1_CAL Fld(6,8,AC_MSKB1)//[13:8]
    #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B0_CAL Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_DQS0_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x770)
    #define RK1_DQS0_STBCAL_CNT_R1_DQS0_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK1_DQS1_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x774)
    #define RK1_DQS1_STBCAL_CNT_R1_DQS1_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK1_DQS2_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x778)
    #define RK1_DQS2_STBCAL_CNT_R1_DQS2_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK1_DQS3_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x77C)
    #define RK1_DQS3_STBCAL_CNT_R1_DQS3_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_00 (DRAMC_NAO_BASE_ADDRESS + 0x780)
    #define RK1_B01_STB_DBG_INFO_00_RK1_B1_STB_DBG_INFO_00 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_00_RK1_B0_STB_DBG_INFO_00 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_01 (DRAMC_NAO_BASE_ADDRESS + 0x784)
    #define RK1_B01_STB_DBG_INFO_01_RK1_B1_STB_DBG_INFO_01 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_01_RK1_B0_STB_DBG_INFO_01 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_02 (DRAMC_NAO_BASE_ADDRESS + 0x788)
    #define RK1_B01_STB_DBG_INFO_02_RK1_B1_STB_DBG_INFO_02 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_02_RK1_B0_STB_DBG_INFO_02 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_03 (DRAMC_NAO_BASE_ADDRESS + 0x78C)
    #define RK1_B01_STB_DBG_INFO_03_RK1_B1_STB_DBG_INFO_03 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_03_RK1_B0_STB_DBG_INFO_03 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_04 (DRAMC_NAO_BASE_ADDRESS + 0x790)
    #define RK1_B01_STB_DBG_INFO_04_RK1_B1_STB_DBG_INFO_04 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_04_RK1_B0_STB_DBG_INFO_04 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_05 (DRAMC_NAO_BASE_ADDRESS + 0x794)
    #define RK1_B01_STB_DBG_INFO_05_RK1_B1_STB_DBG_INFO_05 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_05_RK1_B0_STB_DBG_INFO_05 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_06 (DRAMC_NAO_BASE_ADDRESS + 0x798)
    #define RK1_B01_STB_DBG_INFO_06_RK1_B1_STB_DBG_INFO_06 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_06_RK1_B0_STB_DBG_INFO_06 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_07 (DRAMC_NAO_BASE_ADDRESS + 0x79C)
    #define RK1_B01_STB_DBG_INFO_07_RK1_B1_STB_DBG_INFO_07 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_07_RK1_B0_STB_DBG_INFO_07 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_08 (DRAMC_NAO_BASE_ADDRESS + 0x7A0)
    #define RK1_B01_STB_DBG_INFO_08_RK1_B1_STB_DBG_INFO_08 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_08_RK1_B0_STB_DBG_INFO_08 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_09 (DRAMC_NAO_BASE_ADDRESS + 0x7A4)
    #define RK1_B01_STB_DBG_INFO_09_RK1_B1_STB_DBG_INFO_09 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_09_RK1_B0_STB_DBG_INFO_09 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_10 (DRAMC_NAO_BASE_ADDRESS + 0x7A8)
    #define RK1_B01_STB_DBG_INFO_10_RK1_B1_STB_DBG_INFO_10 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_10_RK1_B0_STB_DBG_INFO_10 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_11 (DRAMC_NAO_BASE_ADDRESS + 0x7AC)
    #define RK1_B01_STB_DBG_INFO_11_RK1_B1_STB_DBG_INFO_11 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_11_RK1_B0_STB_DBG_INFO_11 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_12 (DRAMC_NAO_BASE_ADDRESS + 0x7B0)
    #define RK1_B01_STB_DBG_INFO_12_RK1_B1_STB_DBG_INFO_12 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_12_RK1_B0_STB_DBG_INFO_12 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_13 (DRAMC_NAO_BASE_ADDRESS + 0x7B4)
    #define RK1_B01_STB_DBG_INFO_13_RK1_B1_STB_DBG_INFO_13 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_13_RK1_B0_STB_DBG_INFO_13 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_14 (DRAMC_NAO_BASE_ADDRESS + 0x7B8)
    #define RK1_B01_STB_DBG_INFO_14_RK1_B1_STB_DBG_INFO_14 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_14_RK1_B0_STB_DBG_INFO_14 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B01_STB_DBG_INFO_15 (DRAMC_NAO_BASE_ADDRESS + 0x7BC)
    #define RK1_B01_STB_DBG_INFO_15_RK1_B1_STB_DBG_INFO_15 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B01_STB_DBG_INFO_15_RK1_B0_STB_DBG_INFO_15 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_00 (DRAMC_NAO_BASE_ADDRESS + 0x7C0)
    #define RK1_B23_STB_DBG_INFO_00_RK1_B3_STB_DBG_INFO_00 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_00_RK1_B2_STB_DBG_INFO_00 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_01 (DRAMC_NAO_BASE_ADDRESS + 0x7C4)
    #define RK1_B23_STB_DBG_INFO_01_RK1_B3_STB_DBG_INFO_01 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_01_RK1_B2_STB_DBG_INFO_01 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_02 (DRAMC_NAO_BASE_ADDRESS + 0x7C8)
    #define RK1_B23_STB_DBG_INFO_02_RK1_B3_STB_DBG_INFO_02 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_02_RK1_B2_STB_DBG_INFO_02 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_03 (DRAMC_NAO_BASE_ADDRESS + 0x7CC)
    #define RK1_B23_STB_DBG_INFO_03_RK1_B3_STB_DBG_INFO_03 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_03_RK1_B2_STB_DBG_INFO_03 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_04 (DRAMC_NAO_BASE_ADDRESS + 0x7D0)
    #define RK1_B23_STB_DBG_INFO_04_RK1_B3_STB_DBG_INFO_04 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_04_RK1_B2_STB_DBG_INFO_04 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_05 (DRAMC_NAO_BASE_ADDRESS + 0x7D4)
    #define RK1_B23_STB_DBG_INFO_05_RK1_B3_STB_DBG_INFO_05 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_05_RK1_B2_STB_DBG_INFO_05 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_06 (DRAMC_NAO_BASE_ADDRESS + 0x7D8)
    #define RK1_B23_STB_DBG_INFO_06_RK1_B3_STB_DBG_INFO_06 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_06_RK1_B2_STB_DBG_INFO_06 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_07 (DRAMC_NAO_BASE_ADDRESS + 0x7DC)
    #define RK1_B23_STB_DBG_INFO_07_RK1_B3_STB_DBG_INFO_07 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_07_RK1_B2_STB_DBG_INFO_07 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_08 (DRAMC_NAO_BASE_ADDRESS + 0x7E0)
    #define RK1_B23_STB_DBG_INFO_08_RK1_B3_STB_DBG_INFO_08 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_08_RK1_B2_STB_DBG_INFO_08 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_09 (DRAMC_NAO_BASE_ADDRESS + 0x7E4)
    #define RK1_B23_STB_DBG_INFO_09_RK1_B3_STB_DBG_INFO_09 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_09_RK1_B2_STB_DBG_INFO_09 Fld(16,0,AC_FULLW10)//[15:0]

//Page DRAMC_NAO_4
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_10 (DRAMC_NAO_BASE_ADDRESS + 0x7E8)
    #define RK1_B23_STB_DBG_INFO_10_RK1_B3_STB_DBG_INFO_10 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_10_RK1_B2_STB_DBG_INFO_10 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_11 (DRAMC_NAO_BASE_ADDRESS + 0x7EC)
    #define RK1_B23_STB_DBG_INFO_11_RK1_B3_STB_DBG_INFO_11 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_11_RK1_B2_STB_DBG_INFO_11 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_12 (DRAMC_NAO_BASE_ADDRESS + 0x7F0)
    #define RK1_B23_STB_DBG_INFO_12_RK1_B3_STB_DBG_INFO_12 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_12_RK1_B2_STB_DBG_INFO_12 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_13 (DRAMC_NAO_BASE_ADDRESS + 0x7F4)
    #define RK1_B23_STB_DBG_INFO_13_RK1_B3_STB_DBG_INFO_13 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_13_RK1_B2_STB_DBG_INFO_13 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_14 (DRAMC_NAO_BASE_ADDRESS + 0x7F8)
    #define RK1_B23_STB_DBG_INFO_14_RK1_B3_STB_DBG_INFO_14 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_14_RK1_B2_STB_DBG_INFO_14 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK1_B23_STB_DBG_INFO_15 (DRAMC_NAO_BASE_ADDRESS + 0x7FC)
    #define RK1_B23_STB_DBG_INFO_15_RK1_B3_STB_DBG_INFO_15 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK1_B23_STB_DBG_INFO_15_RK1_B2_STB_DBG_INFO_15 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x800)
    #define RK2_DQSOSC_STATUS_MR19_REG_RK2 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_DQSOSC_STATUS_MR18_REG_RK2 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x804)
    #define RK2_DQSOSC_DELTA_DQSOSC_INT_RK2 Fld(1,19,AC_MSKB2)//[19:19]
    #define RK2_DQSOSC_DELTA_H_DQSOSCLSBR_RK2_REQ Fld(1,18,AC_MSKB2)//[18:18]
    #define RK2_DQSOSC_DELTA_DQSOSCR_RK2_RESPONSE Fld(1,17,AC_MSKB2)//[17:17]
    #define RK2_DQSOSC_DELTA_SIGN_RK2_DQSOSC_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define RK2_DQSOSC_DELTA_ABS_RK2_DQSOSC_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x808)
    #define RK2_DQSOSC_DELTA2_SIGN_RK2_DQSOSC_B1_DELTA Fld(1,16,AC_MSKB2)//[16:16]
    #define RK2_DQSOSC_DELTA2_ABS_RK2_DQSOSC_B1_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x810)
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK2_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x814)
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK2_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x818)
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK2_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x81C)
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM3_MOD Fld(3,28,AC_MSKB3)//[30:28]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM2_MOD Fld(3,24,AC_MSKB3)//[26:24]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM1_MOD Fld(3,20,AC_MSKB2)//[22:20]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM0_MOD Fld(3,16,AC_MSKB2)//[18:16]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ3_MOD Fld(3,12,AC_MSKB1)//[14:12]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ2_MOD Fld(3,8,AC_MSKB1)//[10:8]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ1_MOD Fld(3,4,AC_MSKB0)//[6:4]
    #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ0_MOD Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK2_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x820)
    #define RK2_DUMMY_RD_DATA0_DUMMY_RD_RK2_DATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x824)
    #define RK2_DUMMY_RD_DATA1_DUMMY_RD_RK2_DATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x828)
    #define RK2_DUMMY_RD_DATA2_DUMMY_RD_RK2_DATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x82C)
    #define RK2_DUMMY_RD_DATA3_DUMMY_RD_RK2_DATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_B0_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x830)
    #define RK2_B0_STB_MAX_MIN_DLY_RK2_B0_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK2_B0_STB_MAX_MIN_DLY_RK2_B0_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK2_B1_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x834)
    #define RK2_B1_STB_MAX_MIN_DLY_RK2_B1_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK2_B1_STB_MAX_MIN_DLY_RK2_B1_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK2_B2_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x838)
    #define RK2_B2_STB_MAX_MIN_DLY_RK2_B2_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK2_B2_STB_MAX_MIN_DLY_RK2_B2_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK2_B3_STB_MAX_MIN_DLY (DRAMC_NAO_BASE_ADDRESS + 0x83C)
    #define RK2_B3_STB_MAX_MIN_DLY_RK2_B3_STBEN_MAX_DLY Fld(12,16,AC_MSKW32)//[27:16]
    #define RK2_B3_STB_MAX_MIN_DLY_RK2_B3_STBEN_MIN_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define DRAMC_REG_RK2_DQSIENDLY (DRAMC_NAO_BASE_ADDRESS + 0x840)
    #define RK2_DQSIENDLY_R2DQS3IENDLY Fld(7,24,AC_MSKB3)//[30:24]
    #define RK2_DQSIENDLY_R2DQS2IENDLY Fld(7,16,AC_MSKB2)//[22:16]
    #define RK2_DQSIENDLY_R2DQS1IENDLY Fld(7,8,AC_MSKB1)//[14:8]
    #define RK2_DQSIENDLY_R2DQS0IENDLY Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_RK2_DQSIENUIDLY (DRAMC_NAO_BASE_ADDRESS + 0x844)
    #define RK2_DQSIENUIDLY_R2DQS3IENUIDLY Fld(6,24,AC_MSKB3)//[29:24]
    #define RK2_DQSIENUIDLY_R2DQS2IENUIDLY Fld(6,16,AC_MSKB2)//[21:16]
    #define RK2_DQSIENUIDLY_R2DQS1IENUIDLY Fld(6,8,AC_MSKB1)//[13:8]
    #define RK2_DQSIENUIDLY_R2DQS0IENUIDLY Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_DQSIENUIDLY_P1 (DRAMC_NAO_BASE_ADDRESS + 0x848)
    #define RK2_DQSIENUIDLY_P1_R2DQS3IENUIDLY_P1 Fld(6,24,AC_MSKB3)//[29:24]
    #define RK2_DQSIENUIDLY_P1_R2DQS2IENUIDLY_P1 Fld(6,16,AC_MSKB2)//[21:16]
    #define RK2_DQSIENUIDLY_P1_R2DQS1IENUIDLY_P1 Fld(6,8,AC_MSKB1)//[13:8]
    #define RK2_DQSIENUIDLY_P1_R2DQS0IENUIDLY_P1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_DQS_STBCALDEC_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x850)
    #define RK2_DQS_STBCALDEC_CNT1_RK2_DQS1_STBCALDEC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_DQS_STBCALDEC_CNT1_RK2_DQS0_STBCALDEC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_DQS_STBCALDEC_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x854)
    #define RK2_DQS_STBCALDEC_CNT2_RK2_DQS3_STBCALDEC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_DQS_STBCALDEC_CNT2_RK2_DQS2_STBCALDEC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_DQS_STBCALINC_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x858)
    #define RK2_DQS_STBCALINC_CNT1_RK2_DQS1_STBCALINC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_DQS_STBCALINC_CNT1_RK2_DQS0_STBCALINC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_DQS_STBCALINC_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x85C)
    #define RK2_DQS_STBCALINC_CNT2_RK2_DQS3_STBCALINC_CNT Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_DQS_STBCALINC_CNT2_RK2_DQS2_STBCALINC_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x860)
    #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_B1_OVERFLOW Fld(1,30,AC_MSKB3)//[30:30]
    #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_OVERFLOW Fld(1,22,AC_MSKB2)//[22:22]
    #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2 Fld(6,16,AC_MSKB2)//[21:16]
    #define RK2_PI_DQ_CAL_RK2_ARPI_DQ_B1_CAL Fld(6,8,AC_MSKB1)//[13:8]
    #define RK2_PI_DQ_CAL_RK2_ARPI_DQ_B0_CAL Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_DQSG_RETRY_FLAG (DRAMC_NAO_BASE_ADDRESS + 0x864)
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL3 Fld(1,19,AC_MSKB2)//[19:19]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL2 Fld(1,18,AC_MSKB2)//[18:18]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL1 Fld(1,17,AC_MSKB2)//[17:17]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL0 Fld(1,16,AC_MSKB2)//[16:16]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE3 Fld(1,3,AC_MSKB0)//[3:3]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE1 Fld(1,1,AC_MSKB0)//[1:1]
    #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE0 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_RK2_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x868)
    #define RK2_PI_DQM_CAL_RK2_ARPI_DQM_B1_CAL Fld(6,8,AC_MSKB1)//[13:8]
    #define RK2_PI_DQM_CAL_RK2_ARPI_DQM_B0_CAL Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_DQS0_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x870)
    #define RK2_DQS0_STBCAL_CNT_R2_DQS0_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK2_DQS1_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x874)
    #define RK2_DQS1_STBCAL_CNT_R2_DQS1_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK2_DQS2_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x878)
    #define RK2_DQS2_STBCAL_CNT_R2_DQS2_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK2_DQS3_STBCAL_CNT (DRAMC_NAO_BASE_ADDRESS + 0x87C)
    #define RK2_DQS3_STBCAL_CNT_R2_DQS3_STBCAL_CNT Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_00 (DRAMC_NAO_BASE_ADDRESS + 0x880)
    #define RK2_B01_STB_DBG_INFO_00_RK2_B1_STB_DBG_INFO_00 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_00_RK2_B0_STB_DBG_INFO_00 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_01 (DRAMC_NAO_BASE_ADDRESS + 0x884)
    #define RK2_B01_STB_DBG_INFO_01_RK2_B1_STB_DBG_INFO_01 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_01_RK2_B0_STB_DBG_INFO_01 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_02 (DRAMC_NAO_BASE_ADDRESS + 0x888)
    #define RK2_B01_STB_DBG_INFO_02_RK2_B1_STB_DBG_INFO_02 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_02_RK2_B0_STB_DBG_INFO_02 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_03 (DRAMC_NAO_BASE_ADDRESS + 0x88C)
    #define RK2_B01_STB_DBG_INFO_03_RK2_B1_STB_DBG_INFO_03 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_03_RK2_B0_STB_DBG_INFO_03 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_04 (DRAMC_NAO_BASE_ADDRESS + 0x890)
    #define RK2_B01_STB_DBG_INFO_04_RK2_B1_STB_DBG_INFO_04 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_04_RK2_B0_STB_DBG_INFO_04 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_05 (DRAMC_NAO_BASE_ADDRESS + 0x894)
    #define RK2_B01_STB_DBG_INFO_05_RK2_B1_STB_DBG_INFO_05 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_05_RK2_B0_STB_DBG_INFO_05 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_06 (DRAMC_NAO_BASE_ADDRESS + 0x898)
    #define RK2_B01_STB_DBG_INFO_06_RK2_B1_STB_DBG_INFO_06 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_06_RK2_B0_STB_DBG_INFO_06 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_07 (DRAMC_NAO_BASE_ADDRESS + 0x89C)
    #define RK2_B01_STB_DBG_INFO_07_RK2_B1_STB_DBG_INFO_07 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_07_RK2_B0_STB_DBG_INFO_07 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_08 (DRAMC_NAO_BASE_ADDRESS + 0x8A0)
    #define RK2_B01_STB_DBG_INFO_08_RK2_B1_STB_DBG_INFO_08 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_08_RK2_B0_STB_DBG_INFO_08 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_09 (DRAMC_NAO_BASE_ADDRESS + 0x8A4)
    #define RK2_B01_STB_DBG_INFO_09_RK2_B1_STB_DBG_INFO_09 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_09_RK2_B0_STB_DBG_INFO_09 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_10 (DRAMC_NAO_BASE_ADDRESS + 0x8A8)
    #define RK2_B01_STB_DBG_INFO_10_RK2_B1_STB_DBG_INFO_10 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_10_RK2_B0_STB_DBG_INFO_10 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_11 (DRAMC_NAO_BASE_ADDRESS + 0x8AC)
    #define RK2_B01_STB_DBG_INFO_11_RK2_B1_STB_DBG_INFO_11 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_11_RK2_B0_STB_DBG_INFO_11 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_12 (DRAMC_NAO_BASE_ADDRESS + 0x8B0)
    #define RK2_B01_STB_DBG_INFO_12_RK2_B1_STB_DBG_INFO_12 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_12_RK2_B0_STB_DBG_INFO_12 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_13 (DRAMC_NAO_BASE_ADDRESS + 0x8B4)
    #define RK2_B01_STB_DBG_INFO_13_RK2_B1_STB_DBG_INFO_13 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_13_RK2_B0_STB_DBG_INFO_13 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_14 (DRAMC_NAO_BASE_ADDRESS + 0x8B8)
    #define RK2_B01_STB_DBG_INFO_14_RK2_B1_STB_DBG_INFO_14 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_14_RK2_B0_STB_DBG_INFO_14 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B01_STB_DBG_INFO_15 (DRAMC_NAO_BASE_ADDRESS + 0x8BC)
    #define RK2_B01_STB_DBG_INFO_15_RK2_B1_STB_DBG_INFO_15 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B01_STB_DBG_INFO_15_RK2_B0_STB_DBG_INFO_15 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_00 (DRAMC_NAO_BASE_ADDRESS + 0x8C0)
    #define RK2_B23_STB_DBG_INFO_00_RK2_B3_STB_DBG_INFO_00 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_00_RK2_B2_STB_DBG_INFO_00 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_01 (DRAMC_NAO_BASE_ADDRESS + 0x8C4)
    #define RK2_B23_STB_DBG_INFO_01_RK2_B3_STB_DBG_INFO_01 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_01_RK2_B2_STB_DBG_INFO_01 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_02 (DRAMC_NAO_BASE_ADDRESS + 0x8C8)
    #define RK2_B23_STB_DBG_INFO_02_RK2_B3_STB_DBG_INFO_02 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_02_RK2_B2_STB_DBG_INFO_02 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_03 (DRAMC_NAO_BASE_ADDRESS + 0x8CC)
    #define RK2_B23_STB_DBG_INFO_03_RK2_B3_STB_DBG_INFO_03 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_03_RK2_B2_STB_DBG_INFO_03 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_04 (DRAMC_NAO_BASE_ADDRESS + 0x8D0)
    #define RK2_B23_STB_DBG_INFO_04_RK2_B3_STB_DBG_INFO_04 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_04_RK2_B2_STB_DBG_INFO_04 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_05 (DRAMC_NAO_BASE_ADDRESS + 0x8D4)
    #define RK2_B23_STB_DBG_INFO_05_RK2_B3_STB_DBG_INFO_05 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_05_RK2_B2_STB_DBG_INFO_05 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_06 (DRAMC_NAO_BASE_ADDRESS + 0x8D8)
    #define RK2_B23_STB_DBG_INFO_06_RK2_B3_STB_DBG_INFO_06 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_06_RK2_B2_STB_DBG_INFO_06 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_07 (DRAMC_NAO_BASE_ADDRESS + 0x8DC)
    #define RK2_B23_STB_DBG_INFO_07_RK2_B3_STB_DBG_INFO_07 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_07_RK2_B2_STB_DBG_INFO_07 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_08 (DRAMC_NAO_BASE_ADDRESS + 0x8E0)
    #define RK2_B23_STB_DBG_INFO_08_RK2_B3_STB_DBG_INFO_08 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_08_RK2_B2_STB_DBG_INFO_08 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_09 (DRAMC_NAO_BASE_ADDRESS + 0x8E4)
    #define RK2_B23_STB_DBG_INFO_09_RK2_B3_STB_DBG_INFO_09 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_09_RK2_B2_STB_DBG_INFO_09 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_10 (DRAMC_NAO_BASE_ADDRESS + 0x8E8)
    #define RK2_B23_STB_DBG_INFO_10_RK2_B3_STB_DBG_INFO_10 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_10_RK2_B2_STB_DBG_INFO_10 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_11 (DRAMC_NAO_BASE_ADDRESS + 0x8EC)
    #define RK2_B23_STB_DBG_INFO_11_RK2_B3_STB_DBG_INFO_11 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_11_RK2_B2_STB_DBG_INFO_11 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_12 (DRAMC_NAO_BASE_ADDRESS + 0x8F0)
    #define RK2_B23_STB_DBG_INFO_12_RK2_B3_STB_DBG_INFO_12 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_12_RK2_B2_STB_DBG_INFO_12 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_13 (DRAMC_NAO_BASE_ADDRESS + 0x8F4)
    #define RK2_B23_STB_DBG_INFO_13_RK2_B3_STB_DBG_INFO_13 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_13_RK2_B2_STB_DBG_INFO_13 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_14 (DRAMC_NAO_BASE_ADDRESS + 0x8F8)
    #define RK2_B23_STB_DBG_INFO_14_RK2_B3_STB_DBG_INFO_14 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_14_RK2_B2_STB_DBG_INFO_14 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK2_B23_STB_DBG_INFO_15 (DRAMC_NAO_BASE_ADDRESS + 0x8FC)
    #define RK2_B23_STB_DBG_INFO_15_RK2_B3_STB_DBG_INFO_15 Fld(16,16,AC_FULLW32)//[31:16]
    #define RK2_B23_STB_DBG_INFO_15_RK2_B2_STB_DBG_INFO_15 Fld(16,0,AC_FULLW10)//[15:0]







///////////////////////// DRAMC AO Registers ////////////////////////////////
#define DRAMC_AO_BASE_ADDRESS Channel_A_DRAMC_AO_BASE_ADDRESS
#define RG_FLD_FULL Fld(32,0,AC_FULLDW)//[31:0]

//Page DRAMC0_1
#define DRAMC_REG_DDRCONF0 (DRAMC_AO_BASE_ADDRESS + 0x000)
    #define DDRCONF0_DRAMC_SW_RST Fld(1,31,AC_MSKB3)//[31:31]
    #define DDRCONF0_DDR4EN Fld(1,30,AC_MSKB3)//[30:30]
    #define DDRCONF0_DDR3EN Fld(1,29,AC_MSKB3)//[29:29]
    #define DDRCONF0_DDR2EN Fld(1,28,AC_MSKB3)//[28:28]
    #define DDRCONF0_LPDDR2_NO_INT Fld(1,27,AC_MSKB3)//[27:27]
    #define DDRCONF0_LPDDR4EN Fld(1,26,AC_MSKB3)//[26:26]
    #define DDRCONF0_LPDDR3EN Fld(1,25,AC_MSKB3)//[25:25]
    #define DDRCONF0_LPDDR2EN Fld(1,24,AC_MSKB3)//[24:24]
    #define DDRCONF0_GDDR3EN Fld(1,23,AC_MSKB2)//[23:23]
    #define DDRCONF0_DM4TO1MODE Fld(1,22,AC_MSKB2)//[22:22]
    #define DDRCONF0_DM16BITFULL Fld(1,21,AC_MSKB2)//[21:21]
    #define DDRCONF0_DM64BITEN Fld(1,20,AC_MSKB2)//[20:20]
    #define DDRCONF0_DQ4BMUX Fld(1,19,AC_MSKB2)//[19:19]
    #define DDRCONF0_DM16BITSWAP Fld(1,18,AC_MSKB2)//[18:18]
    #define DDRCONF0_DM16BPHSEL Fld(1,17,AC_MSKB2)//[17:17]
    #define DDRCONF0_GDDR3RST Fld(1,16,AC_MSKB2)//[16:16]
    #define DDRCONF0_BC4OTF Fld(1,15,AC_MSKB1)//[15:15]
    #define DDRCONF0_AG0MWR Fld(1,14,AC_MSKB1)//[14:14]
    #define DDRCONF0_BC4OTF_OPT Fld(1,13,AC_MSKB1)//[13:13]
    #define DDRCONF0_BK8EN Fld(1,12,AC_MSKB1)//[12:12]
    #define DDRCONF0_BG4EN Fld(1,11,AC_MSKB1)//[11:11]
    #define DDRCONF0_APBL2 Fld(1,10,AC_MSKB1)//[10:10]
    #define DDRCONF0_DQSGCGM Fld(1,9,AC_MSKB1)//[9:9]
    #define DDRCONF0_RDQSIEN Fld(1,8,AC_MSKB1)//[8:8]
    #define DDRCONF0_DRAMEN Fld(1,7,AC_MSKB0)//[7:7]
    #define DDRCONF0_FIFOLEN Fld(2,4,AC_MSKB0)//[5:4]
    #define DDRCONF0_WDT_DBG_RST Fld(1,2,AC_MSKB0)//[2:2]
    #define DDRCONF0_DMSW_RST Fld(1,1,AC_MSKB0)//[1:1]
    #define DDRCONF0_RDATRST Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_DRAMCTRL (DRAMC_AO_BASE_ADDRESS + 0x004)
    #define DRAMCTRL_REQQUE_MAXCNT_CHG Fld(1,27,AC_MSKB3)//[27:27]
    #define DRAMCTRL_REQQUE_THD_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define DRAMCTRL_REQQUE_DEPTH_UPD Fld(1,25,AC_MSKB3)//[25:25]
    #define DRAMCTRL_FW2R Fld(1,24,AC_MSKB3)//[24:24]
    #define DRAMCTRL_TCMD Fld(3,20,AC_MSKB2)//[22:20]
    #define DRAMCTRL_PREALL_OPTION Fld(1,19,AC_MSKB2)//[19:19]
    #define DRAMCTRL_ZQCALL Fld(1,18,AC_MSKB2)//[18:18]
    #define DRAMCTRL_DMRCDRSV Fld(1,16,AC_MSKB2)//[16:16]
    #define DRAMCTRL_TMRRICHKDIS Fld(1,15,AC_MSKB1)//[15:15]
    #define DRAMCTRL_ALEBLOCK Fld(1,14,AC_MSKB1)//[14:14]
    #define DRAMCTRL_DYNMWREN Fld(1,13,AC_MSKB1)//[13:13]
    #define DRAMCTRL_ASYNCEN Fld(1,12,AC_MSKB1)//[12:12]
    #define DRAMCTRL_CHKFORPRE Fld(1,10,AC_MSKB1)//[10:10]
    #define DRAMCTRL_CLKWITRFC Fld(1,9,AC_MSKB1)//[9:9]
    #define DRAMCTRL_RANK_ASYM Fld(1,7,AC_MSKB0)//[7:7]
    #define DRAMCTRL_WDATRGO Fld(1,8,AC_MSKB1)//[8:8]
    #define DRAMCTRL_DPDRK_OPT Fld(1,5,AC_MSKB0)//[5:5]
    #define DRAMCTRL_TMRR2WDIS Fld(1,4,AC_MSKB0)//[4:4]
    #define DRAMCTRL_ADRBIT3DEC Fld(1,3,AC_MSKB0)//[3:3]
    #define DRAMCTRL_ADRDECEN Fld(1,2,AC_MSKB0)//[2:2]
    #define DRAMCTRL_ADRDECEN_TARKMODE Fld(1,1,AC_MSKB0)//[1:1]
    #define DRAMCTRL_CTOREQ_HPRI_OPT Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_MISCTL0 (DRAMC_AO_BASE_ADDRESS + 0x008)
    #define MISCTL0_REFP_ARB_EN2 Fld(1,31,AC_MSKB3)//[31:31]
    #define MISCTL0_EMIPREEN Fld(1,27,AC_MSKB3)//[27:27]
    #define MISCTL0_REFP_ARB_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define MISCTL0_REFA_ARB_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define MISCTL0_PBC_ARB_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define MISCTL0_PBC_ARB_E1T Fld(1,23,AC_MSKB2)//[23:23]
    #define MISCTL0_REORDER_MASK_E1T Fld(1,22,AC_MSKB2)//[22:22]
    #define MISCTL0_REFA_ARB_EN_OPTION Fld(1,21,AC_MSKB2)//[21:21]
    #define MISCTL0_REFA_ARB_EN2 Fld(1,19,AC_MSKB2)//[19:19]
    #define MISCTL0_PAGDIS Fld(1,17,AC_MSKB2)//[17:17]
    #define MISCTL0_IDLE_CNT_OPT Fld(1,16,AC_MSKB2)//[16:16]
    #define MISCTL0_R_DMCA_IDLE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_PERFCTL0 (DRAMC_AO_BASE_ADDRESS + 0x00C)
    #define PERFCTL0_WRFIFOEN Fld(1,31,AC_MSKB3)//[31:31]
    #define PERFCTL0_RDFIFOEN Fld(1,30,AC_MSKB3)//[30:30]
    #define PERFCTL0_WRFIO_MODE2 Fld(1,27,AC_MSKB3)//[27:27]
    #define PERFCTL0_TESTWRHIGH Fld(1,23,AC_MSKB2)//[23:23]
    #define PERFCTL0_MAFIXHIGH Fld(1,22,AC_MSKB2)//[22:22]
    #define PERFCTL0_SBR_MASK_OPT2 Fld(1,21,AC_MSKB2)//[21:21]
    #define PERFCTL0_SBR_MASK_OPT Fld(1,20,AC_MSKB2)//[20:20]
    #define PERFCTL0_REORDEREN Fld(1,19,AC_MSKB2)//[19:19]
    #define PERFCTL0_REORDER_MODE Fld(1,18,AC_MSKB2)//[18:18]
    #define PERFCTL0_MWHPRIEN Fld(1,17,AC_MSKB2)//[17:17]
    #define PERFCTL0_RWSPLIT Fld(1,15,AC_MSKB1)//[15:15]
    #define PERFCTL0_WFLUSHEN Fld(1,14,AC_MSKB1)//[14:14]
    #define PERFCTL0_RWHPRICTL Fld(1,13,AC_MSKB1)//[13:13]
    #define PERFCTL0_LASTCMDOPT Fld(1,12,AC_MSKB1)//[12:12]
    #define PERFCTL0_EMILLATEN Fld(1,11,AC_MSKB1)//[11:11]
    #define PERFCTL0_RWAGEEN Fld(1,10,AC_MSKB1)//[10:10]
    #define PERFCTL0_RWLLATEN Fld(1,9,AC_MSKB1)//[9:9]
    #define PERFCTL0_RWHPRIEN Fld(1,8,AC_MSKB1)//[8:8]
    #define PERFCTL0_RWOFOWNUM Fld(3,5,AC_MSKB0)//[7:5]
    #define PERFCTL0_RWOFOEN Fld(1,4,AC_MSKB0)//[4:4]
    #define PERFCTL0_AIDCHKEN Fld(1,3,AC_MSKB0)//[3:3]
    #define PERFCTL0_DISRDPHASE1 Fld(1,1,AC_MSKB0)//[1:1]
    #define PERFCTL0_DUALSCHEN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_ARBCTL (DRAMC_AO_BASE_ADDRESS + 0x010)
    #define ARBCTL_R_SCRAMBLE_REFRESH_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define ARBCTL_RSV_SA3 Fld(1,13,AC_MSKB1)//[13:13]
    #define ARBCTL_RSV_SA2 Fld(1,12,AC_MSKB1)//[12:12]
    #define ARBCTL_RSV_SA1 Fld(1,11,AC_MSKB1)//[11:11]
    #define ARBCTL_RSV_SA0 Fld(1,10,AC_MSKB1)//[10:10]
    #define ARBCTL_WDATACNTDIS Fld(1,9,AC_MSKB1)//[9:9]
    #define ARBCTL_RDATACNTDIS Fld(1,8,AC_MSKB1)//[8:8]
    #define ARBCTL_MAXPENDCNT Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_RSTMASK (DRAMC_AO_BASE_ADDRESS + 0x01C)
    #define RSTMASK_R_DMSHU_RDATRST_MASK Fld(1,31,AC_MSKB3)//[31:31]
    #define RSTMASK_PHY_SYNC_MASK Fld(1,30,AC_MSKB3)//[30:30]
    #define RSTMASK_DAT_SYNC_MASK Fld(1,29,AC_MSKB3)//[29:29]
    #define RSTMASK_GT_SYNC_MASK Fld(1,28,AC_MSKB3)//[28:28]
    #define RSTMASK_GTDMW_SYNC_MASK Fld(1,27,AC_MSKB3)//[27:27]
    #define RSTMASK_DVFS_SYNC_MASK Fld(1,26,AC_MSKB3)//[26:26]
    #define RSTMASK_GT_SYNC_MASK_FOR_PHY Fld(1,25,AC_MSKB3)//[25:25]
    #define RSTMASK_DVFS_SYNC_MASK_FOR_PHY Fld(1,24,AC_MSKB3)//[24:24]
    #define RSTMASK_RETRY_DATRST_MASK Fld(1,21,AC_MSKB2)//[21:21]
    #define RSTMASK_WDATITLV Fld(1,8,AC_MSKB1)//[8:8]
    #define RSTMASK_WDATKEY7 Fld(1,7,AC_MSKB0)//[7:7]
    #define RSTMASK_WDATKEY6 Fld(1,6,AC_MSKB0)//[6:6]
    #define RSTMASK_WDATKEY5 Fld(1,5,AC_MSKB0)//[5:5]
    #define RSTMASK_WDATKEY4 Fld(1,4,AC_MSKB0)//[4:4]
    #define RSTMASK_WDATKEY3 Fld(1,3,AC_MSKB0)//[3:3]
    #define RSTMASK_WDATKEY2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RSTMASK_WDATKEY1 Fld(1,1,AC_MSKB0)//[1:1]
    #define RSTMASK_WDATKEY0 Fld(1,0,AC_MSKB0)//[0:0]
    #define RSTMASK_WDATKEY0_7 Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_PADCTRL (DRAMC_AO_BASE_ADDRESS + 0x020)
    #define PADCTRL_PINMUX Fld(3,28,AC_MSKB3)//[30:28]
    #define PADCTRL_DISDQIEN Fld(4,20,AC_MSKB2)//[23:20]
    #define PADCTRL_FIXDQIEN Fld(4,16,AC_MSKB2)//[19:16]
    #define PADCTRL_DRAMOEN Fld(1,12,AC_MSKB1)//[12:12]
    #define PADCTRL_DISDMOEDIS Fld(1,8,AC_MSKB1)//[8:8]
    #define PADCTRL_DQIENLATEBEGIN Fld(1,3,AC_MSKB0)//[3:3]
    #define PADCTRL_DQIENQKEND Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x024)
    #define CKECTRL_CKEON Fld(1,31,AC_MSKB3)//[31:31]
    #define CKECTRL_CKE_H2L_OPT Fld(1,29,AC_MSKB3)//[29:29]
    #define CKECTRL_CKEWAKE_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define CKECTRL_FASTWAKE_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define CKECTRL_CKETIMER_SEL Fld(1,13,AC_MSKB1)//[13:13]
    #define CKECTRL_CKEEXTEND Fld(1,12,AC_MSKB1)//[12:12]
    #define CKECTRL_CKE2RANK_OPT8 Fld(1,11,AC_MSKB1)//[11:11]
    #define CKECTRL_CKE2RANK_OPT7 Fld(1,10,AC_MSKB1)//[10:10]
    #define CKECTRL_CKE2RANK_OPT6 Fld(1,9,AC_MSKB1)//[9:9]
    #define CKECTRL_CKE2RANK_OPT5 Fld(1,8,AC_MSKB1)//[8:8]
    #define CKECTRL_CKEFIXOFF Fld(1,7,AC_MSKB0)//[7:7]
    #define CKECTRL_CKEFIXON Fld(1,6,AC_MSKB0)//[6:6]
    #define CKECTRL_CKE1FIXOFF Fld(1,5,AC_MSKB0)//[5:5]
    #define CKECTRL_CKE1FIXON Fld(1,4,AC_MSKB0)//[4:4]
    #define CKECTRL_CKE2FIXOFF Fld(1,3,AC_MSKB0)//[3:3]
    #define CKECTRL_CKE2FIXON Fld(1,2,AC_MSKB0)//[2:2]
    #define CKECTRL_CKE2RANK_OPT3 Fld(1,1,AC_MSKB0)//[1:1]
    #define CKECTRL_CKEBYCTL Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_DRSCTRL (DRAMC_AO_BASE_ADDRESS + 0x028)
    #define DRSCTRL_DRS_SELFWAKE_DMYRD_DIS Fld(1,19,AC_MSKB2)//[19:19]
    #define DRSCTRL_DRS_CNTX Fld(7,12,AC_MSKW21)//[18:12]
    #define DRSCTRL_DRSDLY Fld(4,8,AC_MSKB1)//[11:8]
    #define DRSCTRL_DRSACKWAITREF Fld(1,6,AC_MSKB0)//[6:6]
    #define DRSCTRL_DRSCLR_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define DRSCTRL_DRSMON_CLR Fld(1,4,AC_MSKB0)//[4:4]
    #define DRSCTRL_DRSRK1_SW Fld(1,3,AC_MSKB0)//[3:3]
    #define DRSCTRL_DRSPB2AB_OPT Fld(1,2,AC_MSKB0)//[2:2]
    #define DRSCTRL_DRSBLOCKOPT Fld(1,1,AC_MSKB0)//[1:1]
    #define DRSCTRL_DRSDIS Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_RKCFG (DRAMC_AO_BASE_ADDRESS + 0x034)
    #define RKCFG_RK2DPDX Fld(1,30,AC_MSKB3)//[30:30]
    #define RKCFG_RK1DPDX Fld(1,29,AC_MSKB3)//[29:29]
    #define RKCFG_RK0DPDX Fld(1,28,AC_MSKB3)//[28:28]
    #define RKCFG_RK2DPD Fld(1,26,AC_MSKB3)//[26:26]
    #define RKCFG_RK1DPD Fld(1,25,AC_MSKB3)//[25:25]
    #define RKCFG_RK0DPD Fld(1,24,AC_MSKB3)//[24:24]
    #define RKCFG_SRF_ENTER_MASK_OPT Fld(1,23,AC_MSKB2)//[23:23]
    #define RKCFG_RK2SRF Fld(1,22,AC_MSKB2)//[22:22]
    #define RKCFG_RK1SRF Fld(1,21,AC_MSKB2)//[21:21]
    #define RKCFG_RK0SRF Fld(1,20,AC_MSKB2)//[20:20]
    #define RKCFG_DMCKEWAKE Fld(1,19,AC_MSKB2)//[19:19]
    #define RKCFG_RKSIZE Fld(3,16,AC_MSKB2)//[18:16]
    #define RKCFG_CKE2RANK_OPT Fld(1,15,AC_MSKB1)//[15:15]
    #define RKCFG_SHU2RKOPT Fld(1,14,AC_MSKB1)//[14:14]
    #define RKCFG_CS2RANK Fld(1,13,AC_MSKB1)//[13:13]
    #define RKCFG_CKE2RANK Fld(1,12,AC_MSKB1)//[12:12]
    #define RKCFG_DQSOSC2RK Fld(1,11,AC_MSKB1)//[11:11]
    #define RKCFG_MRS2RK Fld(1,10,AC_MSKB1)//[10:10]
    #define RKCFG_RANKRDY_OPT Fld(1,9,AC_MSKB1)//[9:9]
    #define RKCFG_DM3RANK Fld(1,8,AC_MSKB1)//[8:8]
    #define RKCFG_RKSWAP Fld(1,7,AC_MSKB0)//[7:7]
    #define RKCFG_RKMODE Fld(3,4,AC_MSKB0)//[6:4]
    #define RKCFG_TXRANKFIX Fld(1,3,AC_MSKB0)//[3:3]
    #define RKCFG_CKE2RANK_OPT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define RKCFG_TXRANK Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_DRAMC_PD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x038)
    #define DRAMC_PD_CTRL_COMBCLKCTRL Fld(1,31,AC_MSKB3)//[31:31]
    #define DRAMC_PD_CTRL_PHYCLKDYNGEN Fld(1,30,AC_MSKB3)//[30:30]
    #define DRAMC_PD_CTRL_DISSTOP26M Fld(1,27,AC_MSKB3)//[27:27]
    #define DRAMC_PD_CTRL_MIOCKCTRLOFF Fld(1,26,AC_MSKB3)//[26:26]
    #define DRAMC_PD_CTRL_DQIEN_BUFFEN_OPT Fld(2,20,AC_MSKB2)//[21:20]
    #define DRAMC_PD_CTRL_RDPERIODON Fld(1,19,AC_MSKB2)//[19:19]
    #define DRAMC_PD_CTRL_COMB_DCM Fld(1,10,AC_MSKB1)//[10:10]
    #define DRAMC_PD_CTRL_DCMREF_OPT Fld(1,8,AC_MSKB1)//[8:8]
    #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME Fld(1,5,AC_MSKB0)//[5:5]
    #define DRAMC_PD_CTRL_PHYCLK_REFWKEN Fld(1,4,AC_MSKB0)//[4:4]
    #define DRAMC_PD_CTRL_DCMENNOTRFC Fld(1,2,AC_MSKB0)//[2:2]
    #define DRAMC_PD_CTRL_DCMEN2 Fld(1,1,AC_MSKB0)//[1:1]
    #define DRAMC_PD_CTRL_DCMEN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_CLKAR (DRAMC_AO_BASE_ADDRESS + 0x03C)
    #define CLKAR_RDYCKAR Fld(1,31,AC_MSKB3)//[31:31]
    #define CLKAR_CMDCKAR Fld(1,30,AC_MSKB3)//[30:30]
    #define CLKAR_CALCKAR Fld(1,29,AC_MSKB3)//[29:29]
    #define CLKAR_SEQCLKRUN Fld(1,28,AC_MSKB3)//[28:28]
    #define CLKAR_REQQUECLKRUN Fld(1,27,AC_MSKB3)//[27:27]
    #define CLKAR_REFCLKRUN Fld(1,26,AC_MSKB3)//[26:26]
    #define CLKAR_DWCLKRUN Fld(1,25,AC_MSKB3)//[25:25]
    #define CLKAR_PHYGLUECLKRUN Fld(1,24,AC_MSKB3)//[24:24]
    #define CLKAR_TESTCLKRUN Fld(1,23,AC_MSKB2)//[23:23]
    #define CLKAR_SELPH_CG_DIS Fld(1,22,AC_MSKB2)//[22:22]
    #define CLKAR_SELPH_4LCG_DIS Fld(1,21,AC_MSKB2)//[21:21]
    #define CLKAR_BCLKAR Fld(1,20,AC_MSKB2)//[20:20]
    #define CLKAR_PSELAR Fld(1,19,AC_MSKB2)//[19:19]
    #define CLKAR_IDLE_OPT Fld(1,18,AC_MSKB2)//[18:18]
    #define CLKAR_SRF_CLKRUN Fld(1,17,AC_MSKB2)//[17:17]
    #define CLKAR_RDATCKAR Fld(1,16,AC_MSKB2)//[16:16]
    #define CLKAR_SEQCLKRUN2 Fld(1,1,AC_MSKB0)//[1:1]
    #define CLKAR_SEQCLKRUN1 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_CLKCTRL (DRAMC_AO_BASE_ADDRESS + 0x040)
    #define CLKCTRL_CLK_EN_1 Fld(1,29,AC_MSKB3)//[29:29]
    #define CLKCTRL_CLK_EN_0 Fld(1,28,AC_MSKB3)//[28:28]
    #define CLKCTRL_PSEL_CNT Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SELFREF_HWSAVE_FLAG (DRAMC_AO_BASE_ADDRESS + 0x044)
    #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SREFCTRL (DRAMC_AO_BASE_ADDRESS + 0x048)
    #define SREFCTRL_SELFREF Fld(1,31,AC_MSKB3)//[31:31]
    #define SREFCTRL_SREF_HW_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define SREFCTRL_SREFDLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SREFCTRL_SREF2_OPTION Fld(1,22,AC_MSKB2)//[22:22]
    #define SREFCTRL_SREF3_OPTION1 Fld(1,21,AC_MSKB2)//[21:21]
    #define SREFCTRL_SREF3_OPTION Fld(1,20,AC_MSKB2)//[20:20]
    #define SREFCTRL_DQSOSC_C2R_OPT Fld(1,18,AC_MSKB2)//[18:18]
    #define SREFCTRL_DQSOSC_THRD_OPT Fld(1,17,AC_MSKB2)//[17:17]
    #define SREFCTRL_SRFPD_DIS Fld(1,16,AC_MSKB2)//[16:16]
#define DRAMC_REG_REFCTRL0 (DRAMC_AO_BASE_ADDRESS + 0x04C)
    #define REFCTRL0_REFBW_FREN Fld(1,31,AC_MSKB3)//[31:31]
    #define REFCTRL0_REFFRERUN Fld(1,30,AC_MSKB3)//[30:30]
    #define REFCTRL0_REFDIS Fld(1,29,AC_MSKB3)//[29:29]
    #define REFCTRL0_REFNA_OPT Fld(1,28,AC_MSKB3)//[28:28]
    #define REFCTRL0_REF_PREGATE_CNT Fld(4,24,AC_MSKB3)//[27:24]
    #define REFCTRL0_ADVREF_CNT Fld(4,20,AC_MSKB2)//[23:20]
    #define REFCTRL0_PBREFEN Fld(1,18,AC_MSKB2)//[18:18]
    #define REFCTRL0_PBREF_DISBYRATE Fld(1,17,AC_MSKB2)//[17:17]
    #define REFCTRL0_PBREF_DISBYREFNUM Fld(1,16,AC_MSKB2)//[16:16]
    #define REFCTRL0_DISBYREFNUM Fld(3,12,AC_MSKB1)//[14:12]
    #define REFCTRL0_REFMODE_MANUAL_TRIG Fld(1,11,AC_MSKB1)//[11:11]
    #define REFCTRL0_REFMODE_MANUAL Fld(1,10,AC_MSKB1)//[10:10]
    #define REFCTRL0_DMPGVLD_IG Fld(1,8,AC_MSKB1)//[8:8]
    #define REFCTRL0_REFOVERCNT_RST Fld(1,7,AC_MSKB0)//[7:7]
    #define REFCTRL0_RFRINTEN Fld(1,6,AC_MSKB0)//[6:6]
    #define REFCTRL0_RFRINTCTL Fld(1,5,AC_MSKB0)//[5:5]
    #define REFCTRL0_DRVCGWREF Fld(1,2,AC_MSKB0)//[2:2]
    #define REFCTRL0_UPDBYWR Fld(1,1,AC_MSKB0)//[1:1]
    #define REFCTRL0_DLLFRZ Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_REFCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x050)
    #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG Fld(1,31,AC_MSKB3)//[31:31]
    #define REFCTRL1_REFRATE_MANUAL Fld(3,28,AC_MSKB3)//[30:28]
    #define REFCTRL1_MPENDREF_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define REFCTRL1_PSEL_OPT1 Fld(1,6,AC_MSKB0)//[6:6]
    #define REFCTRL1_REF_QUE_AUTOSAVE_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define REFCTRL1_PRE8REF Fld(1,4,AC_MSKB0)//[4:4]
    #define REFCTRL1_PSEL_OPT3 Fld(1,3,AC_MSKB0)//[3:3]
    #define REFCTRL1_PSEL_OPT2 Fld(1,2,AC_MSKB0)//[2:2]
    #define REFCTRL1_SREF_PRD_OPT Fld(1,1,AC_MSKB0)//[1:1]
    #define REFCTRL1_SLEFREF_AUTOSAVE_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_REFRATRE_FILTER (DRAMC_AO_BASE_ADDRESS + 0x054)
    #define REFRATRE_FILTER_REFRATE_FILEN Fld(1,31,AC_MSKB3)//[31:31]
    #define REFRATRE_FILTER_REFRATE_FIL7 Fld(3,28,AC_MSKB3)//[30:28]
    #define REFRATRE_FILTER_REFRATE_FIL6 Fld(3,24,AC_MSKB3)//[26:24]
    #define REFRATRE_FILTER_PB2AB_OPT1 Fld(1,23,AC_MSKB2)//[23:23]
    #define REFRATRE_FILTER_REFRATE_FIL5 Fld(3,20,AC_MSKB2)//[22:20]
    #define REFRATRE_FILTER_REFRATE_FIL4 Fld(3,16,AC_MSKB2)//[18:16]
    #define REFRATRE_FILTER_PB2AB_OPT Fld(1,15,AC_MSKB1)//[15:15]
    #define REFRATRE_FILTER_REFRATE_FIL3 Fld(3,12,AC_MSKB1)//[14:12]
    #define REFRATRE_FILTER_REFRATE_FIL2 Fld(3,8,AC_MSKB1)//[10:8]
    #define REFRATRE_FILTER_REFRATE_FIL1 Fld(3,4,AC_MSKB0)//[6:4]
    #define REFRATRE_FILTER_REFRATE_FIL0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_ZQCS (DRAMC_AO_BASE_ADDRESS + 0x058)
    #define ZQCS_ZQCSDUAL Fld(1,31,AC_MSKB3)//[31:31]
    #define ZQCS_ZQCSMASK Fld(1,30,AC_MSKB3)//[30:30]
    #define ZQCS_ZQCSMASK_OPT Fld(1,21,AC_MSKB2)//[21:21]
    #define ZQCS_ZQMASK_CGAR Fld(1,20,AC_MSKB2)//[20:20]
    #define ZQCS_ZQCS_MASK_SEL_CGAR Fld(1,19,AC_MSKB2)//[19:19]
    #define ZQCS_ZQCS_MASK_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define ZQCS_ZQCSAD Fld(8,8,AC_FULLB1)//[15:8]
    #define ZQCS_ZQCSOP Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_MRS (DRAMC_AO_BASE_ADDRESS + 0x05C)
    #define MRS_MRSBG Fld(2,30,AC_MSKB3)//[31:30]
    #define MRS_MPCRK Fld(2,28,AC_MSKB3)//[29:28]
    #define MRS_MRRRK Fld(2,26,AC_MSKB3)//[27:26]
    #define MRS_MRSRK Fld(2,24,AC_MSKB3)//[25:24]
    #define MRS_MRSBA Fld(3,21,AC_MSKB2)//[23:21]
    #define MRS_MRSMA Fld(13,8,AC_MSKW21)//[20:8]
    #define MRS_MRSOP Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_SPCMD (DRAMC_AO_BASE_ADDRESS + 0x060)
    #define SPCMD_MPRWEN Fld(1,13,AC_MSKB1)//[13:13]
    #define SPCMD_ACTEN Fld(1,12,AC_MSKB1)//[12:12]
    #define SPCMD_DQSOSCDISEN Fld(1,11,AC_MSKB1)//[11:11]
    #define SPCMD_DQSOSCENEN Fld(1,10,AC_MSKB1)//[10:10]
    #define SPCMD_DQSGCNTRST Fld(1,9,AC_MSKB1)//[9:9]
    #define SPCMD_DQSGCNTEN Fld(1,8,AC_MSKB1)//[8:8]
    #define SPCMD_RDDQCEN Fld(1,7,AC_MSKB0)//[7:7]
    #define SPCMD_ZQLATEN Fld(1,6,AC_MSKB0)//[6:6]
    #define SPCMD_TCMDEN Fld(1,5,AC_MSKB0)//[5:5]
    #define SPCMD_ZQCEN Fld(1,4,AC_MSKB0)//[4:4]
    #define SPCMD_AREFEN Fld(1,3,AC_MSKB0)//[3:3]
    #define SPCMD_PREAEN Fld(1,2,AC_MSKB0)//[2:2]
    #define SPCMD_MRREN Fld(1,1,AC_MSKB0)//[1:1]
    #define SPCMD_MRWEN Fld(1,0,AC_MSKB0)//[0:0]

//Page DRAMC_2
#define DRAMC_REG_SPCMDCTRL (DRAMC_AO_BASE_ADDRESS + 0x064)
    #define SPCMDCTRL_ZQCSDISB Fld(1,31,AC_MSKB3)//[31:31]
    #define SPCMDCTRL_ZQCALDISB Fld(1,30,AC_MSKB3)//[30:30]
    #define SPCMDCTRL_REFRDIS Fld(1,29,AC_MSKB3)//[29:29]
    #define SPCMDCTRL_REFR_BLOCKEN Fld(1,28,AC_MSKB3)//[28:28]
    #define SPCMDCTRL_MRRREFUPD_B Fld(1,27,AC_MSKB3)//[27:27]
    #define SPCMDCTRL_CLR_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define SPCMDCTRL_MRWWOPRA Fld(1,25,AC_MSKB3)//[25:25]
    #define SPCMDCTRL_SCPRE Fld(1,19,AC_MSKB2)//[19:19]
    #define SPCMDCTRL_RDDQCDIS Fld(1,11,AC_MSKB1)//[11:11]
    #define SPCMDCTRL_DPDWOSC Fld(1,7,AC_MSKB0)//[7:7]
    #define SPCMDCTRL_R_DMDVFSMRW_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define SPCMDCTRL_MRRSWUPD Fld(1,5,AC_MSKB0)//[5:5]
#define DRAMC_REG_PPR_CTRL (DRAMC_AO_BASE_ADDRESS + 0x068)
    #define PPR_CTRL_ACTEN_ROW Fld(16,16,AC_FULLW32)//[31:16]
    #define PPR_CTRL_ACTEN_BK Fld(3,12,AC_MSKB1)//[14:12]
#define DRAMC_REG_MPC_OPTION (DRAMC_AO_BASE_ADDRESS + 0x06C)
    #define MPC_OPTION_MPCRKEN Fld(1,17,AC_MSKB2)//[17:17]
    #define MPC_OPTION_MPCMAN_CAS2EN Fld(1,16,AC_MSKB2)//[16:16]
    #define MPC_OPTION_MPCMANEN Fld(1,15,AC_MSKB1)//[15:15]
    #define MPC_OPTION_MPCOP Fld(7,8,AC_MSKB1)//[14:8]
#define DRAMC_REG_REFQUE_CNT (DRAMC_AO_BASE_ADDRESS + 0x070)
    #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_HW_MRR_FUN (DRAMC_AO_BASE_ADDRESS + 0x074)
    #define HW_MRR_FUN_MRR_PUSH2POP_SEL Fld(3,20,AC_MSKB2)//[22:20]
    #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR Fld(1,18,AC_MSKB2)//[18:18]
    #define HW_MRR_FUN_MRR_PUSH2POP_CLR Fld(1,17,AC_MSKB2)//[17:17]
    #define HW_MRR_FUN_MRR_PUSH2POP_ENA Fld(1,16,AC_MSKB2)//[16:16]
    #define HW_MRR_FUN_TMRR_OE_OPT_DIS Fld(1,13,AC_MSKB1)//[13:13]
    #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS Fld(1,12,AC_MSKB1)//[12:12]
    #define HW_MRR_FUN_MRR_HW_HIPRI Fld(1,11,AC_MSKB1)//[11:11]
    #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS Fld(1,10,AC_MSKB1)//[10:10]
    #define HW_MRR_FUN_MRR_REQNOPUSH_DIS Fld(1,9,AC_MSKB1)//[9:9]
    #define HW_MRR_FUN_BUFEN_RFC_OPT Fld(1,8,AC_MSKB1)//[8:8]
    #define HW_MRR_FUN_MANTMRR Fld(4,4,AC_MSKB0)//[7:4]
    #define HW_MRR_FUN_MANTMRR_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define HW_MRR_FUN_TRPMRR_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define HW_MRR_FUN_TRCDMRR_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define HW_MRR_FUN_TMRR_ENA Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_MRR_BIT_MUX1 (DRAMC_AO_BASE_ADDRESS + 0x078)
    #define MRR_BIT_MUX1_MRR_BIT3_SEL Fld(5,24,AC_MSKB3)//[28:24]
    #define MRR_BIT_MUX1_MRR_BIT2_SEL Fld(5,16,AC_MSKB2)//[20:16]
    #define MRR_BIT_MUX1_MRR_BIT1_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define MRR_BIT_MUX1_MRR_BIT0_SEL Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_MRR_BIT_MUX2 (DRAMC_AO_BASE_ADDRESS + 0x07C)
    #define MRR_BIT_MUX2_MRR_BIT7_SEL Fld(5,24,AC_MSKB3)//[28:24]
    #define MRR_BIT_MUX2_MRR_BIT6_SEL Fld(5,16,AC_MSKB2)//[20:16]
    #define MRR_BIT_MUX2_MRR_BIT5_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define MRR_BIT_MUX2_MRR_BIT4_SEL Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_MRR_BIT_MUX3 (DRAMC_AO_BASE_ADDRESS + 0x080)
    #define MRR_BIT_MUX3_MRR_BIT11_SEL Fld(5,24,AC_MSKB3)//[28:24]
    #define MRR_BIT_MUX3_MRR_BIT10_SEL Fld(5,16,AC_MSKB2)//[20:16]
    #define MRR_BIT_MUX3_MRR_BIT9_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define MRR_BIT_MUX3_MRR_BIT8_SEL Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_MRR_BIT_MUX4 (DRAMC_AO_BASE_ADDRESS + 0x084)
    #define MRR_BIT_MUX4_MRR_BIT15_SEL Fld(5,24,AC_MSKB3)//[28:24]
    #define MRR_BIT_MUX4_MRR_BIT14_SEL Fld(5,16,AC_MSKB2)//[20:16]
    #define MRR_BIT_MUX4_MRR_BIT13_SEL Fld(5,8,AC_MSKB1)//[12:8]
    #define MRR_BIT_MUX4_MRR_BIT12_SEL Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_TEST2_5 (DRAMC_AO_BASE_ADDRESS + 0x08C)
    #define TEST2_5_TEST2_BASE_2 Fld(28,4,AC_MSKDW)//[31:4]
#define DRAMC_REG_TEST2_0 (DRAMC_AO_BASE_ADDRESS + 0x090)
    #define TEST2_0_TEST2_PAT0 Fld(8,8,AC_FULLB1)//[15:8]
    #define TEST2_0_TEST2_PAT1 Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_TEST2_1 (DRAMC_AO_BASE_ADDRESS + 0x094)
    #define TEST2_1_TEST2_BASE Fld(28,4,AC_MSKDW)//[31:4]
#define DRAMC_REG_TEST2_2 (DRAMC_AO_BASE_ADDRESS + 0x098)
    #define TEST2_2_TEST2_OFF Fld(28,4,AC_MSKDW)//[31:4]
#define DRAMC_REG_TEST2_3 (DRAMC_AO_BASE_ADDRESS + 0x09C)
    #define TEST2_3_TEST2W Fld(1,31,AC_MSKB3)//[31:31]
    #define TEST2_3_TEST2R Fld(1,30,AC_MSKB3)//[30:30]
    #define TEST2_3_TEST1 Fld(1,29,AC_MSKB3)//[29:29]
    #define TEST2_3_TEST2WREN2_HW_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define TEST2_3_TESTLP Fld(1,27,AC_MSKB3)//[27:27]
    #define TEST2_3_TAHPRI_B Fld(1,26,AC_MSKB3)//[26:26]
    #define TEST2_3_TESTADR_SHIFT Fld(1,25,AC_MSKB3)//[25:25]
    #define TEST2_3_DMPAT32 Fld(1,24,AC_MSKB3)//[24:24]
    #define TEST2_3_MDQS Fld(1,23,AC_MSKB2)//[23:23]
    #define TEST2_3_DRDELSWSEL Fld(3,20,AC_MSKB2)//[22:20]
    #define TEST2_3_DRDELSWEN Fld(1,19,AC_MSKB2)//[19:19]
    #define TEST2_3_DQSUPDMODE Fld(1,14,AC_MSKB1)//[14:14]
    #define TEST2_3_MANUDQSUPD Fld(1,13,AC_MSKB1)//[13:13]
    #define TEST2_3_MANUDLLFRZ Fld(1,12,AC_MSKB1)//[12:12]
    #define TEST2_3_DQDLYAUTO Fld(1,11,AC_MSKB1)//[11:11]
    #define TEST2_3_DQSICALSTP Fld(3,8,AC_MSKB1)//[10:8]
    #define TEST2_3_TESTAUDPAT Fld(1,7,AC_MSKB0)//[7:7]
    #define TEST2_3_PSTWR2 Fld(1,6,AC_MSKB0)//[6:6]
    #define TEST2_3_DQSICALUPD Fld(1,5,AC_MSKB0)//[5:5]
    #define TEST2_3_DQSICALEN Fld(1,4,AC_MSKB0)//[4:4]
    #define TEST2_3_TESTCNT Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_TEST2_4 (DRAMC_AO_BASE_ADDRESS + 0x0A0)
    #define TEST2_4_TESTAGENTRKSEL Fld(3,28,AC_MSKB3)//[30:28]
    #define TEST2_4_TESTAGENTRK Fld(2,24,AC_MSKB3)//[25:24]
    #define TEST2_4_NEGDQS Fld(1,23,AC_MSKB2)//[23:23]
    #define TEST2_4_DQCALDIS Fld(1,22,AC_MSKB2)//[22:22]
    #define TEST2_4_DISMASK Fld(1,20,AC_MSKB2)//[20:20]
    #define TEST2_4_TEST_REQ_LEN1 Fld(1,17,AC_MSKB2)//[17:17]
    #define TEST2_4_TESTXTALKPAT Fld(1,16,AC_MSKB2)//[16:16]
    #define TEST2_4_TESTAUDMODE Fld(1,15,AC_MSKB1)//[15:15]
    #define TEST2_4_TESTAUDBITINV Fld(1,14,AC_MSKB1)//[14:14]
    #define TEST2_4_TESTAUDINIT Fld(5,8,AC_MSKB1)//[12:8]
    #define TEST2_4_TESTSSOXTALKPAT Fld(1,7,AC_MSKB0)//[7:7]
    #define TEST2_4_TESTSSOPAT Fld(1,6,AC_MSKB0)//[6:6]
    #define TEST2_4_TEST2DISSCRAM Fld(1,5,AC_MSKB0)//[5:5]
    #define TEST2_4_TESTAUDINC Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_WDT_DBG_SIGNAL (DRAMC_AO_BASE_ADDRESS + 0x0A4)
    #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR Fld(1,14,AC_MSKB1)//[14:14]
    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1 Fld(1,13,AC_MSKB1)//[13:13]
    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0 Fld(1,12,AC_MSKB1)//[12:12]
    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1 Fld(1,11,AC_MSKB1)//[11:11]
    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0 Fld(1,10,AC_MSKB1)//[10:10]
    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1 Fld(1,9,AC_MSKB1)//[9:9]
    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0 Fld(1,8,AC_MSKB1)//[8:8]
    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1 Fld(1,5,AC_MSKB0)//[5:5]
    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0 Fld(1,4,AC_MSKB0)//[4:4]
    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1 Fld(1,3,AC_MSKB0)//[3:3]
    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0 Fld(1,2,AC_MSKB0)//[2:2]
    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1 Fld(1,1,AC_MSKB0)//[1:1]
    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_LBTEST (DRAMC_AO_BASE_ADDRESS + 0x0AC)
    #define LBTEST_RDTGDATA Fld(1,31,AC_MSKB3)//[31:31]
    #define LBTEST_RDWRDATA Fld(1,30,AC_MSKB3)//[30:30]
    #define LBTEST_RDCOLADR Fld(1,29,AC_MSKB3)//[29:29]
    #define LBTEST_OCDADJ Fld(1,24,AC_MSKB3)//[24:24]
    #define LBTEST_OCDPAT Fld(8,16,AC_FULLB2)//[23:16]
    #define LBTEST_R_EXTLB_DRAMC_CONF_I Fld(5,8,AC_MSKB1)//[12:8]
    #define LBTEST_LBTEST_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define LBTEST_LBTEST Fld(1,4,AC_MSKB0)//[4:4]
    #define LBTEST_LBTEST_IGB3 Fld(1,3,AC_MSKB0)//[3:3]
    #define LBTEST_LBTEST_IGB2 Fld(1,2,AC_MSKB0)//[2:2]
    #define LBTEST_LBTEST_IGB1 Fld(1,1,AC_MSKB0)//[1:1]
    #define LBTEST_LBTEST_IGB0 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_CATRAINING1 (DRAMC_AO_BASE_ADDRESS + 0x0B0)
    #define CATRAINING1_CATRAIN_INTV Fld(8,24,AC_FULLB3)//[31:24]
    #define CATRAINING1_CATRAINLAT Fld(5,19,AC_MSKB2)//[23:19]
    #define CATRAINING1_CATRAINCSEXT Fld(1,13,AC_MSKB1)//[13:13]
    #define CATRAINING1_CSTRAIN_OPTION Fld(1,6,AC_MSKB0)//[6:6]
    #define CATRAINING1_TESTCATRAIN Fld(1,5,AC_MSKB0)//[5:5]
    #define CATRAINING1_CATRAINMRS Fld(1,2,AC_MSKB0)//[2:2]
    #define CATRAINING1_CATRAINEN Fld(1,1,AC_MSKB0)//[1:1]
#define DRAMC_REG_CATRAINING2 (DRAMC_AO_BASE_ADDRESS + 0x0B4)
    #define CATRAINING2_CATRAINCA_Y Fld(16,16,AC_FULLW32)//[31:16]
    #define CATRAINING2_CATRAINCA Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_WRITE_LEV (DRAMC_AO_BASE_ADDRESS + 0x0BC)
    #define WRITE_LEV_DMVREFCA Fld(7,20,AC_MSKW32)//[26:20]
    #define WRITE_LEV_DQS_SEL Fld(4,16,AC_MSKB2)//[19:16]
    #define WRITE_LEV_DQSBY_G Fld(4,12,AC_MSKB1)//[15:12]
    #define WRITE_LEV_DQSBX_G Fld(4,8,AC_MSKB1)//[11:8]
    #define WRITE_LEV_DQS_WLEV Fld(1,7,AC_MSKB0)//[7:7]
    #define WRITE_LEV_DQS_OE_WLEV_OP Fld(1,6,AC_MSKB0)//[6:6]
    #define WRITE_LEV_CBTMASKDQSOE Fld(1,5,AC_MSKB0)//[5:5]
    #define WRITE_LEV_BTCBTFIXDQSOE Fld(1,4,AC_MSKB0)//[4:4]
    #define WRITE_LEV_BYTEMODECBTEN Fld(1,3,AC_MSKB0)//[3:3]
    #define WRITE_LEV_DDRPHY_COMB_CG_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define WRITE_LEV_WRITE_LEVEL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_MR_GOLDEN (DRAMC_AO_BASE_ADDRESS + 0x0C0)
    #define MR_GOLDEN_MR32_GOLDEN Fld(8,24,AC_FULLB3)//[31:24]
    #define MR_GOLDEN_MR40_GOLDEN Fld(8,16,AC_FULLB2)//[23:16]
    #define MR_GOLDEN_MR15_GOLDEN Fld(8,8,AC_FULLB1)//[15:8]
    #define MR_GOLDEN_MR20_GOLDEN Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_SLP4_TESTMODE (DRAMC_AO_BASE_ADDRESS + 0x0C4)
    #define SLP4_TESTMODE_SPEC_MODE Fld(1,25,AC_MSKB3)//[25:25]
    #define SLP4_TESTMODE_STESTEN Fld(1,24,AC_MSKB3)//[24:24]
    #define SLP4_TESTMODE_CA5_TEST Fld(4,20,AC_MSKB2)//[23:20]
    #define SLP4_TESTMODE_CA4_TEST Fld(4,16,AC_MSKB2)//[19:16]
    #define SLP4_TESTMODE_CA3_TEST Fld(4,12,AC_MSKB1)//[15:12]
    #define SLP4_TESTMODE_CA2_TEST Fld(4,8,AC_MSKB1)//[11:8]
    #define SLP4_TESTMODE_CA1_TEST Fld(4,4,AC_MSKB0)//[7:4]
    #define SLP4_TESTMODE_CA0_TEST Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x0C8)
    #define DQSOSCR_DQSOSC_CALEN Fld(1,31,AC_MSKB3)//[31:31]
    #define DQSOSCR_DQSOSCLOPAD Fld(1,30,AC_MSKB3)//[30:30]
    #define DQSOSCR_TXUPD_ABREF_OPT Fld(1,29,AC_MSKB3)//[29:29]
    #define DQSOSCR_EMPTY_WRITE_OPT Fld(1,28,AC_MSKB3)//[28:28]
    #define DQSOSCR_SREF_TXPI_RELOAD_OPT Fld(1,27,AC_MSKB3)//[27:27]
    #define DQSOSCR_RK0_BYTE_MODE Fld(1,26,AC_MSKB3)//[26:26]
    #define DQSOSCR_RK1_BYTE_MODE Fld(1,25,AC_MSKB3)//[25:25]
    #define DQSOSCR_DQSOSCRDIS Fld(1,24,AC_MSKB3)//[24:24]
    #define DQSOSCR_SREF_TXUI_RELOAD_OPT Fld(1,23,AC_MSKB2)//[23:23]
    #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS Fld(1,22,AC_MSKB2)//[22:22]
    #define DQSOSCR_TXUPD_IDLE_OPT Fld(1,21,AC_MSKB2)//[21:21]
    #define DQSOSCR_TXUPD_ABREF_SEL Fld(2,19,AC_MSKB2)//[20:19]
    #define DQSOSCR_TXUPD_IDLE_SEL Fld(2,17,AC_MSKB2)//[18:17]
    #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL Fld(2,15,AC_MSKW21)//[16:15]
    #define DQSOSCR_DQS2DQ_UPD_MON_OPT Fld(1,14,AC_MSKB1)//[14:14]
    #define DQSOSCR_TDQS2DQ_UPD_BLOCKING Fld(1,13,AC_MSKB1)//[13:13]
    #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT Fld(5,8,AC_MSKB1)//[12:8]
    #define DQSOSCR_ARUIDQ_SW Fld(1,7,AC_MSKB0)//[7:7]
    #define DQSOSCR_MANUTXUPD Fld(1,6,AC_MSKB0)//[6:6]
    #define DQSOSCR_TXUPDMODE Fld(1,5,AC_MSKB0)//[5:5]
    #define DQSOSCR_TXUPD_BLOCK_OPT Fld(1,4,AC_MSKB0)//[4:4]
    #define DQSOSCR_TXUPD_BLOCK_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define DQSOSCR_RK2_BYTE_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define DQSOSCR_DQSOSC_INTEN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_DUMMY_RD (DRAMC_AO_BASE_ADDRESS + 0x0D0)
    #define DUMMY_RD_DMYRD_REORDER_DIS Fld(1,27,AC_MSKB3)//[27:27]
    #define DUMMY_RD_DMYRD_HPRI_DIS Fld(1,26,AC_MSKB3)//[26:26]
    #define DUMMY_RD_DMY_RD_RX_TRACK Fld(1,25,AC_MSKB3)//[25:25]
    #define DUMMY_RD_DUMMY_RD_PA_OPT Fld(1,24,AC_MSKB3)//[24:24]
    #define DUMMY_RD_DQSG_DMYWR_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define DUMMY_RD_DQSG_DMYRD_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define DUMMY_RD_SREF_DMYRD_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define DUMMY_RD_DUMMY_RD_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define DUMMY_RD_RANK_NUM Fld(2,16,AC_MSKB2)//[17:16]
    #define DUMMY_RD_DUMMY_RD_CNT7 Fld(1,15,AC_MSKB1)//[15:15]
    #define DUMMY_RD_DUMMY_RD_CNT6 Fld(1,14,AC_MSKB1)//[14:14]
    #define DUMMY_RD_DUMMY_RD_CNT5 Fld(1,13,AC_MSKB1)//[13:13]
    #define DUMMY_RD_DUMMY_RD_CNT4 Fld(1,12,AC_MSKB1)//[12:12]
    #define DUMMY_RD_DUMMY_RD_CNT3 Fld(1,11,AC_MSKB1)//[11:11]
    #define DUMMY_RD_DUMMY_RD_CNT2 Fld(1,10,AC_MSKB1)//[10:10]
    #define DUMMY_RD_DUMMY_RD_CNT1 Fld(1,9,AC_MSKB1)//[9:9]
    #define DUMMY_RD_DUMMY_RD_CNT0 Fld(1,8,AC_MSKB1)//[8:8]
    #define DUMMY_RD_DMY_RD_DBG Fld(1,7,AC_MSKB0)//[7:7]
    #define DUMMY_RD_DMY_WR_DBG Fld(1,6,AC_MSKB0)//[6:6]
    #define DUMMY_RD_DMYWR_LPRI_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define DUMMY_RD_DUMMY_RD_SW Fld(1,4,AC_MSKB0)//[4:4]
    #define DUMMY_RD_DMYRDOFOEN Fld(1,1,AC_MSKB0)//[1:1]
    #define DUMMY_RD_SREF_DMYRD_MASK Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHUCTRL (DRAMC_AO_BASE_ADDRESS + 0x0D4)
    #define SHUCTRL_DMSHU_DRAMC Fld(1,31,AC_MSKB3)//[31:31]
    #define SHUCTRL_DMSHU_LOW Fld(1,29,AC_MSKB3)//[29:29]
    #define SHUCTRL_R_OTHER_SHU_GP Fld(2,24,AC_MSKB3)//[25:24]
    #define SHUCTRL_R_MPDIV_SHU_GP Fld(3,20,AC_MSKB2)//[22:20]
    #define SHUCTRL_R_NEW_SHU_MUX_SPM Fld(1,19,AC_MSKB2)//[19:19]
    #define SHUCTRL_R_DRAMC_CHA Fld(1,17,AC_MSKB2)//[17:17]
    #define SHUCTRL_LPSM_BYPASS_B Fld(1,16,AC_MSKB2)//[16:16]
    #define SHUCTRL_DMSHU_CNT Fld(6,8,AC_MSKB1)//[13:8]
    #define SHUCTRL_SHU_PHYRST_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define SHUCTRL_VRCG_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define SHUCTRL_R_SHUFFLE_BLOCK_OPT Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_SHUCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0D8)
    #define SHUCTRL1_VRCGEN_PRDCNT Fld(8,24,AC_FULLB3)//[31:24]
    #define SHUCTRL1_CKFSPX_PRDCNT Fld(8,16,AC_FULLB2)//[23:16]
    #define SHUCTRL1_CKFSPE_PRDCNT Fld(8,8,AC_FULLB1)//[15:8]
    #define SHUCTRL1_FC_PRDCNT Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_SHUCTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0DC)
    #define SHUCTRL2_DVFS_CKE_OPT Fld(1,30,AC_MSKB3)//[30:30]
    #define SHUCTRL2_SHU_CLK_MASK Fld(1,29,AC_MSKB3)//[29:29]
    #define SHUCTRL2_R_SHU_RESTORE Fld(1,28,AC_MSKB3)//[28:28]
    #define SHUCTRL2_MR13_SHU_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define SHUCTRL2_HWSET_WLRL Fld(1,24,AC_MSKB3)//[24:24]
    #define SHUCTRL2_SHU_PERIOD_GO_ZERO_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define SHUCTRL2_R_DVFS_OPTION Fld(1,15,AC_MSKB1)//[15:15]
    #define SHUCTRL2_R_DVFS_PARK_N Fld(1,14,AC_MSKB1)//[14:14]
    #define SHUCTRL2_R_GATE_SHU_AHEAD Fld(1,13,AC_MSKB1)//[13:13]
    #define SHUCTRL2_R_DVFS_DLL_CHA Fld(1,12,AC_MSKB1)//[12:12]
    #define SHUCTRL2_R_DVFS_SREF_OPT Fld(1,8,AC_MSKB1)//[8:8]
    #define SHUCTRL2_R_DVFS_FSM_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define SHUCTRL2_R_DLL_IDLE Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHUCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0E0)
    #define SHUCTRL3_VRCGDIS_PRDCNT Fld(8,24,AC_FULLB3)//[31:24]
    #define SHUCTRL3_VRCGDISOP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHUCTRL3_VRCGDIS_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_STBCAL (DRAMC_AO_BASE_ADDRESS + 0x200)
    #define STBCAL_DQSIENMODE Fld(1,31,AC_MSKB3)//[31:31]
    #define STBCAL_DQSIENMODE_SELPH Fld(1,30,AC_MSKB3)//[30:30]
    #define STBCAL_DQSIENCG_NORMAL_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define STBCAL_DQSIENCG_CHG_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define STBCAL_STB_DQIEN_IG Fld(1,27,AC_MSKB3)//[27:27]
    #define STBCAL_PICHGBLOCK_NORD Fld(1,26,AC_MSKB3)//[26:26]
    #define STBCAL_STBDLYOUT_OPT Fld(1,25,AC_MSKB3)//[25:25]
    #define STBCAL_STBCALEN Fld(1,24,AC_MSKB3)//[24:24]
    #define STBCAL_STBCAL2R Fld(1,23,AC_MSKB2)//[23:23]
    #define STBCAL_STB_SELPHYCALEN Fld(1,22,AC_MSKB2)//[22:22]
    #define STBCAL_REFUICHG Fld(1,21,AC_MSKB2)//[21:21]
    #define STBCAL_PICGEN Fld(1,20,AC_MSKB2)//[20:20]
    #define STBCAL_RKCHGMASKDIS Fld(1,19,AC_MSKB2)//[19:19]
    #define STBCAL_STBCNTRST Fld(1,18,AC_MSKB2)//[18:18]
    #define STBCAL_SREF_DQSGUPD Fld(1,17,AC_MSKB2)//[17:17]
    #define STBCAL_PHYVALID_IG Fld(1,16,AC_MSKB2)//[16:16]
    #define STBCAL_STBSTATE_OPT Fld(1,15,AC_MSKB1)//[15:15]
    #define STBCAL_CG_RKEN Fld(1,14,AC_MSKB1)//[14:14]
    #define STBCAL_STBUPDSTOP Fld(1,13,AC_MSKB1)//[13:13]
    #define STBCAL_STBDLELAST_FILTER Fld(1,12,AC_MSKB1)//[12:12]
    #define STBCAL_STBDLELAST_PULSE Fld(4,8,AC_MSKB1)//[11:8]
    #define STBCAL_FASTDQSGUPD Fld(1,7,AC_MSKB0)//[7:7]
    #define STBCAL_FASTDQSG2X Fld(1,6,AC_MSKB0)//[6:6]
    #define STBCAL_DLLFRZIDLE4XUPD Fld(1,5,AC_MSKB0)//[5:5]
    #define STBCAL_STBDLELAST_OPT Fld(1,4,AC_MSKB0)//[4:4]
    #define STBCAL_PIMASK_RKCHG_EXT Fld(3,1,AC_MSKB0)//[3:1]
    #define STBCAL_PIMASK_RKCHG_OPT Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_STBCAL1 (DRAMC_AO_BASE_ADDRESS + 0x204)
    #define STBCAL1_STBCAL_FILTER Fld(16,16,AC_FULLW32)//[31:16]
    #define STBCAL1_STBCNT_SW_RST Fld(1,15,AC_MSKB1)//[15:15]
    #define STBCAL1_DQSERRCNT_DIS Fld(1,14,AC_MSKB1)//[14:14]
    #define STBCAL1_DLLFRZ_BLOCKLONG Fld(1,13,AC_MSKB1)//[13:13]
    #define STBCAL1_DLLFRZ_MON_PBREF_OPT Fld(1,12,AC_MSKB1)//[12:12]
    #define STBCAL1_STBCNT_LATCH_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define STBCAL1_STBENCMPEN Fld(1,10,AC_MSKB1)//[10:10]
    #define STBCAL1_STB_DLLFRZ_IG Fld(1,9,AC_MSKB1)//[9:9]
    #define STBCAL1_STB_FLAGCLR Fld(1,8,AC_MSKB1)//[8:8]
    #define STBCAL1_INPUTRXTRACK_BLOCK Fld(1,7,AC_MSKB0)//[7:7]
    #define STBCAL1_STB_SHIFT_DTCOUT_IG Fld(1,6,AC_MSKB0)//[6:6]
    #define STBCAL1_DQSIEN_7UI_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define STBCAL1_STBCNT_MODESEL Fld(1,4,AC_MSKB0)//[4:4]
    #define STBCAL1_IORGTIM Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_STBCAL2 (DRAMC_AO_BASE_ADDRESS + 0x208)
    #define STBCAL2_STB_PICG_EARLY_1T_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define STBCAL2_STB_DRS_RK1_FLAG_SYNC_RK0_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define STBCAL2_STB_DRS_MASK_HW_SAVE Fld(1,12,AC_MSKB1)//[12:12]
    #define STBCAL2_DQSGCNT_BYP_REF Fld(1,10,AC_MSKB1)//[10:10]
    #define STBCAL2_STB_DBG_UIPI_UPD_OPT Fld(1,9,AC_MSKB1)//[9:9]
    #define STBCAL2_STB_DBG_CG_AO Fld(1,8,AC_MSKB1)//[8:8]
    #define STBCAL2_STB_DBG_EN Fld(4,4,AC_MSKB0)//[7:4]
    #define STBCAL2_STB_UIDLYCG_IG Fld(1,1,AC_MSKB0)//[1:1]
    #define STBCAL2_STB_PIDLYCG_IG Fld(1,0,AC_MSKB0)//[0:0]

//Page DRAMC_3
#define DRAMC_REG_EYESCAN (DRAMC_AO_BASE_ADDRESS + 0x20C)
    #define EYESCAN_STB_GERR_B23 Fld(1,31,AC_MSKB3)//[31:31]
    #define EYESCAN_STB_GERR_B01 Fld(1,30,AC_MSKB3)//[30:30]
    #define EYESCAN_STB_GERR_RST Fld(1,29,AC_MSKB3)//[29:29]
    #define EYESCAN_STB_GERRSTOP Fld(1,28,AC_MSKB3)//[28:28]
    #define EYESCAN_EYESCAN_DQS_SYNC_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define EYESCAN_EYESCAN_NEW_DQ_SYNC_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define EYESCAN_EYESCAN_DQ_SYNC_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define EYESCAN_RX_DQ_EYE_SEL Fld(4,16,AC_MSKB2)//[19:16]
    #define EYESCAN_DCBLNCINS Fld(1,13,AC_MSKB1)//[13:13]
    #define EYESCAN_DCBLNCEN Fld(1,12,AC_MSKB1)//[12:12]
    #define EYESCAN_EYESCAN_TOG_OPT Fld(1,7,AC_MSKB0)//[7:7]
    #define EYESCAN_EYESCAN_CHK_OPT Fld(1,6,AC_MSKB0)//[6:6]
    #define EYESCAN_EYESCAN_RD_SEL_OPT Fld(1,4,AC_MSKB0)//[4:4]
    #define EYESCAN_RG_RX_MIOCK_JIT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define EYESCAN_RG_EX_EYE_SCAN_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define EYESCAN_REG_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_DVFSDLL (DRAMC_AO_BASE_ADDRESS + 0x210)
    #define DVFSDLL_DLL_IDLE_SHU4 Fld(6,24,AC_MSKB3)//[29:24]
    #define DVFSDLL_DLL_IDLE_SHU3 Fld(6,16,AC_MSKB2)//[21:16]
    #define DVFSDLL_DLL_IDLE_SHU2 Fld(6,8,AC_MSKB1)//[13:8]
    #define DVFSDLL_RG_DLL_SHUFFLE Fld(1,7,AC_MSKB0)//[7:7]
    #define DVFSDLL_R_RETRY_SAV_MSK Fld(1,6,AC_MSKB0)//[6:6]
    #define DVFSDLL_R_BYPASS_1ST_DLL_SHU4 Fld(1,4,AC_MSKB0)//[4:4]
    #define DVFSDLL_R_BYPASS_1ST_DLL_SHU3 Fld(1,3,AC_MSKB0)//[3:3]
    #define DVFSDLL_R_BYPASS_1ST_DLL_SHU2 Fld(1,2,AC_MSKB0)//[2:2]
    #define DVFSDLL_R_BYPASS_1ST_DLL_SHU1 Fld(1,1,AC_MSKB0)//[1:1]
    #define DVFSDLL_DLL_LOCK_SHU_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_PRE_TDQSCK1 (DRAMC_AO_BASE_ADDRESS + 0x218)
    #define PRE_TDQSCK1_TDQSCK_PRECAL_START Fld(1,27,AC_MSKB3)//[27:27]
    #define PRE_TDQSCK1_TDQSCK_PRECAL_HW Fld(1,26,AC_MSKB3)//[26:26]
    #define PRE_TDQSCK1_TDQSCK_REG_DVFS Fld(1,25,AC_MSKB3)//[25:25]
    #define PRE_TDQSCK1_TDQSCK_SW_SAVE Fld(1,24,AC_MSKB3)//[24:24]
    #define PRE_TDQSCK1_TDQSCK_SW_UP_CASE Fld(1,23,AC_MSKB2)//[23:23]
    #define PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define PRE_TDQSCK1_SHU_PRELOAD_TX_HW Fld(1,19,AC_MSKB2)//[19:19]
    #define PRE_TDQSCK1_SHU_PRELOAD_TX_START Fld(1,18,AC_MSKB2)//[18:18]
    #define PRE_TDQSCK1_TXUIPI_CAL_CGAR Fld(1,17,AC_MSKB2)//[17:17]
    #define PRE_TDQSCK1_SW_UP_TX_NOW_CASE Fld(1,16,AC_MSKB2)//[16:16]
    #define PRE_TDQSCK1_FREQ_RATIO_TX_11 Fld(5,10,AC_MSKB1)//[14:10]
    #define PRE_TDQSCK1_FREQ_RATIO_TX_10 Fld(5,5,AC_MSKW10)//[9:5]
    #define PRE_TDQSCK1_FREQ_RATIO_TX_9 Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_PRE_TDQSCK2 (DRAMC_AO_BASE_ADDRESS + 0x21C)
    #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0 Fld(8,24,AC_FULLB3)//[31:24]
    #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1 Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2 Fld(8,8,AC_FULLB1)//[15:8]
    #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3 Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_PRE_TDQSCK3 (DRAMC_AO_BASE_ADDRESS + 0x220)
    #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4 Fld(8,24,AC_FULLB3)//[31:24]
    #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5 Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6 Fld(8,8,AC_FULLB1)//[15:8]
    #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7 Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_PRE_TDQSCK4 (DRAMC_AO_BASE_ADDRESS + 0x224)
    #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8 Fld(8,24,AC_FULLB3)//[31:24]
    #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9 Fld(8,16,AC_FULLB2)//[23:16]
    #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10 Fld(8,8,AC_FULLB1)//[15:8]
    #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11 Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_IMPCAL (DRAMC_AO_BASE_ADDRESS + 0x22C)
    #define IMPCAL_IMPCAL_HW Fld(1,31,AC_MSKB3)//[31:31]
    #define IMPCAL_IMPCAL_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define IMPCAL_IMPCAL_SWVALUE_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define IMPCAL_IMPCAL_CMP_DIREC Fld(2,27,AC_MSKB3)//[28:27]
    #define IMPCAL_IMPCAL_NEW_OLD_SL Fld(1,26,AC_MSKB3)//[26:26]
    #define IMPCAL_IMPCAL_IMPPDP Fld(1,25,AC_MSKB3)//[25:25]
    #define IMPCAL_IMPCAL_IMPPDN Fld(1,24,AC_MSKB3)//[24:24]
    #define IMPCAL_IMPCAL_CALI_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define IMPCAL_IMPCAL_CALI_ENP Fld(1,22,AC_MSKB2)//[22:22]
    #define IMPCAL_IMPCAL_CALI_ENN Fld(1,21,AC_MSKB2)//[21:21]
#define DRAMC_REG_IMPEDAMCE_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x230)
    #define IMPEDAMCE_CTRL1_DQS2_OFF_SUB Fld(2,30,AC_MSKB3)//[31:30]
    #define IMPEDAMCE_CTRL1_DQS1_OFF_SUB Fld(2,28,AC_MSKB3)//[29:28]
    #define IMPEDAMCE_CTRL1_DOS2_OFF Fld(10,10,AC_MSKW21)//[19:10]
    #define IMPEDAMCE_CTRL1_DQS1_OFF Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_IMPEDAMCE_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x234)
    #define IMPEDAMCE_CTRL2_DQ2_OFF_SUB Fld(2,30,AC_MSKB3)//[31:30]
    #define IMPEDAMCE_CTRL2_DQ1_OFF_SUB Fld(2,28,AC_MSKB3)//[29:28]
    #define IMPEDAMCE_CTRL2_DQ2_OFF Fld(10,10,AC_MSKW21)//[19:10]
    #define IMPEDAMCE_CTRL2_DQ1_OFF Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_IMPEDAMCE_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x238)
    #define IMPEDAMCE_CTRL3_CMD2_OFF_SUB Fld(2,30,AC_MSKB3)//[31:30]
    #define IMPEDAMCE_CTRL3_CMD1_OFF_SUB Fld(2,28,AC_MSKB3)//[29:28]
    #define IMPEDAMCE_CTRL3_CMD2_OFF Fld(10,10,AC_MSKW21)//[19:10]
    #define IMPEDAMCE_CTRL3_CMD1_OFF Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_IMPEDAMCE_CTRL4 (DRAMC_AO_BASE_ADDRESS + 0x23C)
    #define IMPEDAMCE_CTRL4_DQC2_OFF_SUB Fld(2,30,AC_MSKB3)//[31:30]
    #define IMPEDAMCE_CTRL4_DQC1_OFF_SUB Fld(2,28,AC_MSKB3)//[29:28]
    #define IMPEDAMCE_CTRL4_DQC2_OFF Fld(10,10,AC_MSKW21)//[19:10]
    #define IMPEDAMCE_CTRL4_DQC1_OFF Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_DRAMC_DBG_SEL1 (DRAMC_AO_BASE_ADDRESS + 0x240)
    #define DRAMC_DBG_SEL1_DEBUG_SEL_1 Fld(16,16,AC_FULLW32)//[31:16]
    #define DRAMC_DBG_SEL1_DEBUG_SEL_0 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_DRAMC_DBG_SEL2 (DRAMC_AO_BASE_ADDRESS + 0x244)
    #define DRAMC_DBG_SEL2_DEBUG_SEL_3 Fld(16,16,AC_FULLW32)//[31:16]
    #define DRAMC_DBG_SEL2_DEBUG_SEL_2 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_RK0_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x300)
    #define RK0_DQSOSC_DQSOSC_RK0INTCLR Fld(1,31,AC_MSKB3)//[31:31]
    #define RK0_DQSOSC_DQSOSCR_RK0EN Fld(1,30,AC_MSKB3)//[30:30]
    #define RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT Fld(1,29,AC_MSKB3)//[29:29]
#define DRAMC_REG_RK0_DUMMY_RD_WDATA0 (DRAMC_AO_BASE_ADDRESS + 0x318)
    #define RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_WDATA1 (DRAMC_AO_BASE_ADDRESS + 0x31C)
    #define RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_WDATA2 (DRAMC_AO_BASE_ADDRESS + 0x320)
    #define RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_WDATA3 (DRAMC_AO_BASE_ADDRESS + 0x324)
    #define RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK0_DUMMY_RD_ADR (DRAMC_AO_BASE_ADDRESS + 0x328)
    #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR Fld(11,17,AC_MSKW32)//[27:17]
    #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK0_DUMMY_RD_BK (DRAMC_AO_BASE_ADDRESS + 0x32C)
    #define RK0_DUMMY_RD_BK_DMY_RD_RK0_BK Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK0_PRE_TDQSCK1 (DRAMC_AO_BASE_ADDRESS + 0x330)
    #define RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK2 (DRAMC_AO_BASE_ADDRESS + 0x334)
    #define RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK3 (DRAMC_AO_BASE_ADDRESS + 0x338)
    #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK4 (DRAMC_AO_BASE_ADDRESS + 0x33C)
    #define RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK5 (DRAMC_AO_BASE_ADDRESS + 0x340)
    #define RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK6 (DRAMC_AO_BASE_ADDRESS + 0x344)
    #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK7 (DRAMC_AO_BASE_ADDRESS + 0x348)
    #define RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK8 (DRAMC_AO_BASE_ADDRESS + 0x34C)
    #define RK0_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK9 (DRAMC_AO_BASE_ADDRESS + 0x350)
    #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R0 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK10 (DRAMC_AO_BASE_ADDRESS + 0x354)
    #define RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK11 (DRAMC_AO_BASE_ADDRESS + 0x358)
    #define RK0_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R0 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK0_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R0 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK0_PRE_TDQSCK12 (DRAMC_AO_BASE_ADDRESS + 0x35C)
    #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R0 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x400)
    #define RK1_DQSOSC_DQSOSC_RK1INTCLR Fld(1,31,AC_MSKB3)//[31:31]
    #define RK1_DQSOSC_DQSOSCR_RK1EN Fld(1,30,AC_MSKB3)//[30:30]
#define DRAMC_REG_RK1_DUMMY_RD_WDATA0 (DRAMC_AO_BASE_ADDRESS + 0x418)
    #define RK1_DUMMY_RD_WDATA0_DMY_RD_RK1_WDATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_WDATA1 (DRAMC_AO_BASE_ADDRESS + 0x41C)
    #define RK1_DUMMY_RD_WDATA1_DMY_RD_RK1_WDATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_WDATA2 (DRAMC_AO_BASE_ADDRESS + 0x420)
    #define RK1_DUMMY_RD_WDATA2_DMY_RD_RK1_WDATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_WDATA3 (DRAMC_AO_BASE_ADDRESS + 0x424)
    #define RK1_DUMMY_RD_WDATA3_DMY_RD_RK1_WDATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK1_DUMMY_RD_ADR (DRAMC_AO_BASE_ADDRESS + 0x428)
    #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR Fld(11,17,AC_MSKW32)//[27:17]
    #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK1_DUMMY_RD_BK (DRAMC_AO_BASE_ADDRESS + 0x42C)
    #define RK1_DUMMY_RD_BK_DMY_RD_RK1_BK Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK1_PRE_TDQSCK1 (DRAMC_AO_BASE_ADDRESS + 0x430)
    #define RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK2 (DRAMC_AO_BASE_ADDRESS + 0x434)
    #define RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK3 (DRAMC_AO_BASE_ADDRESS + 0x438)
    #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK4 (DRAMC_AO_BASE_ADDRESS + 0x43C)
    #define RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK5 (DRAMC_AO_BASE_ADDRESS + 0x440)
    #define RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK6 (DRAMC_AO_BASE_ADDRESS + 0x444)
    #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK7 (DRAMC_AO_BASE_ADDRESS + 0x448)
    #define RK1_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK8 (DRAMC_AO_BASE_ADDRESS + 0x44C)
    #define RK1_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK9 (DRAMC_AO_BASE_ADDRESS + 0x450)
    #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R1 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R1 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R1 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK10 (DRAMC_AO_BASE_ADDRESS + 0x454)
    #define RK1_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK11 (DRAMC_AO_BASE_ADDRESS + 0x458)
    #define RK1_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R1 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK1_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R1 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK1_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R1 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK1_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK1_PRE_TDQSCK12 (DRAMC_AO_BASE_ADDRESS + 0x45C)
    #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R1 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R1 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R1 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x500)
    #define RK2_DQSOSC_DQSOSC_RK2INTCLR Fld(1,31,AC_MSKB3)//[31:31]
    #define RK2_DQSOSC_DQSOSCR_RK2EN Fld(1,30,AC_MSKB3)//[30:30]
    #define RK2_DQSOSC_FREQ_RATIO_TX_5 Fld(5,25,AC_MSKB3)//[29:25]
    #define RK2_DQSOSC_FREQ_RATIO_TX_4 Fld(5,20,AC_MSKW32)//[24:20]
    #define RK2_DQSOSC_FREQ_RATIO_TX_3 Fld(5,15,AC_MSKW21)//[19:15]
    #define RK2_DQSOSC_FREQ_RATIO_TX_2 Fld(5,10,AC_MSKB1)//[14:10]
    #define RK2_DQSOSC_FREQ_RATIO_TX_1 Fld(5,5,AC_MSKW10)//[9:5]
    #define RK2_DQSOSC_FREQ_RATIO_TX_0 Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_RK2_DUMMY_RD_WDATA0 (DRAMC_AO_BASE_ADDRESS + 0x518)
    #define RK2_DUMMY_RD_WDATA0_DMY_RD_RK2_WDATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_WDATA1 (DRAMC_AO_BASE_ADDRESS + 0x51C)
    #define RK2_DUMMY_RD_WDATA1_DMY_RD_RK2_WDATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_WDATA2 (DRAMC_AO_BASE_ADDRESS + 0x520)
    #define RK2_DUMMY_RD_WDATA2_DMY_RD_RK2_WDATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_WDATA3 (DRAMC_AO_BASE_ADDRESS + 0x524)
    #define RK2_DUMMY_RD_WDATA3_DMY_RD_RK2_WDATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_RK2_DUMMY_RD_ADR (DRAMC_AO_BASE_ADDRESS + 0x528)
    #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_LEN Fld(4,28,AC_MSKB3)//[31:28]
    #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_COL_ADR Fld(11,17,AC_MSKW32)//[27:17]
    #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_ROW_ADR Fld(17,0,AC_MSKDW)//[16:0]
#define DRAMC_REG_RK2_DUMMY_RD_BK (DRAMC_AO_BASE_ADDRESS + 0x52C)
    #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_8 Fld(5,13,AC_MSKW21)//[17:13]
    #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7 Fld(5,8,AC_MSKB1)//[12:8]
    #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6 Fld(5,3,AC_MSKB0)//[7:3]
    #define RK2_DUMMY_RD_BK_DMY_RD_RK2_BK Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_RK2_PRE_TDQSCK1 (DRAMC_AO_BASE_ADDRESS + 0x530)
    #define RK2_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK2 (DRAMC_AO_BASE_ADDRESS + 0x534)
    #define RK2_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK3 (DRAMC_AO_BASE_ADDRESS + 0x538)
    #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R2 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R2 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R2 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK4 (DRAMC_AO_BASE_ADDRESS + 0x53C)
    #define RK2_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK5 (DRAMC_AO_BASE_ADDRESS + 0x540)
    #define RK2_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK6 (DRAMC_AO_BASE_ADDRESS + 0x544)
    #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R2 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R2 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R2 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK7 (DRAMC_AO_BASE_ADDRESS + 0x548)
    #define RK2_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK8 (DRAMC_AO_BASE_ADDRESS + 0x54C)
    #define RK2_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R2 Fld(6,0,AC_MSKB0)//[5:0]

//Page DRAMC_4
#define DRAMC_REG_RK2_PRE_TDQSCK9 (DRAMC_AO_BASE_ADDRESS + 0x550)
    #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R2 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R2 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R2 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK10 (DRAMC_AO_BASE_ADDRESS + 0x554)
    #define RK2_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK11 (DRAMC_AO_BASE_ADDRESS + 0x558)
    #define RK2_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R2 Fld(7,19,AC_MSKW32)//[25:19]
    #define RK2_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R2 Fld(6,13,AC_MSKW21)//[18:13]
    #define RK2_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R2 Fld(7,6,AC_MSKW10)//[12:6]
    #define RK2_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_RK2_PRE_TDQSCK12 (DRAMC_AO_BASE_ADDRESS + 0x55C)
    #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R2 Fld(6,18,AC_MSKB2)//[23:18]
    #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R2 Fld(6,12,AC_MSKW21)//[17:12]
    #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R2 Fld(6,6,AC_MSKW10)//[11:6]
    #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R2 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU_ACTIM0 (DRAMC_AO_BASE_ADDRESS + 0x800)
    #define SHU_ACTIM0_TRCD Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU_ACTIM0_TRRD Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_ACTIM0_TWR Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU_ACTIM0_TWTR Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_SHU_ACTIM1 (DRAMC_AO_BASE_ADDRESS + 0x804)
    #define SHU_ACTIM1_TRC Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU_ACTIM1_TRAS Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU_ACTIM1_TRP Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU_ACTIM1_TRPAB Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_ACTIM2 (DRAMC_AO_BASE_ADDRESS + 0x808)
    #define SHU_ACTIM2_TFAW Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU_ACTIM2_TR2W Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU_ACTIM2_TRTP Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_ACTIM2_TXP Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_ACTIM3 (DRAMC_AO_BASE_ADDRESS + 0x80C)
    #define SHU_ACTIM3_REFCNT Fld(8,24,AC_FULLB3)//[31:24]
    #define SHU_ACTIM3_TRFC Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU_ACTIM3_TRFCPB Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_SHU_ACTIM4 (DRAMC_AO_BASE_ADDRESS + 0x810)
    #define SHU_ACTIM4_TZQCS Fld(8,24,AC_FULLB3)//[31:24]
    #define SHU_ACTIM4_REFCNT_FR_CLK Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU_ACTIM4_TXREFCNT Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU_ACTIM5 (DRAMC_AO_BASE_ADDRESS + 0x814)
    #define SHU_ACTIM5_TMRR2W Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU_ACTIM5_TWTPD Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU_ACTIM5_TR2PD Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_SHU_ACTIM6 (DRAMC_AO_BASE_ADDRESS + 0x818)
    #define SHU_ACTIM6_BGTRRD Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_ACTIM6_TWRMPR Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU_ACTIM6_BGTWTR Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU_ACTIM6_BGTCCD Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_SHU_ACTIM_XRT (DRAMC_AO_BASE_ADDRESS + 0x81C)
    #define SHU_ACTIM_XRT_XRTW2W Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU_ACTIM_XRT_XRTW2R Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_ACTIM_XRT_XRTR2W Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU_ACTIM_XRT_XRTR2R Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_SHU_AC_TIME_05T (DRAMC_AO_BASE_ADDRESS + 0x820)
    #define SHU_AC_TIME_05T_XRTW2R_M05T Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU_AC_TIME_05T_XRTR2W_05T Fld(1,26,AC_MSKB3)//[26:26]
    #define SHU_AC_TIME_05T_TWTR_M05T Fld(1,25,AC_MSKB3)//[25:25]
    #define SHU_AC_TIME_05T_TR2W_05T Fld(1,24,AC_MSKB3)//[24:24]
    #define SHU_AC_TIME_05T_BGTWTR_05T Fld(1,23,AC_MSKB2)//[23:23]
    #define SHU_AC_TIME_05T_BGTCCD_05T Fld(1,22,AC_MSKB2)//[22:22]
    #define SHU_AC_TIME_05T_BGTRRD_05T Fld(1,21,AC_MSKB2)//[21:21]
    #define SHU_AC_TIME_05T_TWTPD_M05T Fld(1,16,AC_MSKB2)//[16:16]
    #define SHU_AC_TIME_05T_TR2PD_05T Fld(1,15,AC_MSKB1)//[15:15]
    #define SHU_AC_TIME_05T_TFAW_05T Fld(1,13,AC_MSKB1)//[13:13]
    #define SHU_AC_TIME_05T_TRRD_05T Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU_AC_TIME_05T_TWR_M05T Fld(1,10,AC_MSKB1)//[10:10]
    #define SHU_AC_TIME_05T_TRAS_05T Fld(1,9,AC_MSKB1)//[9:9]
    #define SHU_AC_TIME_05T_TRPAB_05T Fld(1,8,AC_MSKB1)//[8:8]
    #define SHU_AC_TIME_05T_TRP_05T Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU_AC_TIME_05T_TRCD_05T Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU_AC_TIME_05T_TRTP_05T Fld(1,5,AC_MSKB0)//[5:5]
    #define SHU_AC_TIME_05T_TXP_05T Fld(1,4,AC_MSKB0)//[4:4]
    #define SHU_AC_TIME_05T_TRFC_05T Fld(1,2,AC_MSKB0)//[2:2]
    #define SHU_AC_TIME_05T_TRFCPB_05T Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU_AC_TIME_05T_TRC_05T Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_AC_DERATING0 (DRAMC_AO_BASE_ADDRESS + 0x824)
    #define SHU_AC_DERATING0_TRCD_DERATE Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU_AC_DERATING0_TRRD_DERATE Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_AC_DERATING0_ACDERATEEN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_AC_DERATING1 (DRAMC_AO_BASE_ADDRESS + 0x828)
    #define SHU_AC_DERATING1_TRC_DERATE Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU_AC_DERATING1_TRAS_DERATE Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU_AC_DERATING1_TRP_DERATE Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU_AC_DERATING1_TRPAB_DERATE Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_AC_DERATING_05T (DRAMC_AO_BASE_ADDRESS + 0x830)
    #define SHU_AC_DERATING_05T_TRRD_05T_DERATE Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU_AC_DERATING_05T_TRAS_05T_DERATE Fld(1,9,AC_MSKB1)//[9:9]
    #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE Fld(1,8,AC_MSKB1)//[8:8]
    #define SHU_AC_DERATING_05T_TRP_05T_DERATE Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU_AC_DERATING_05T_TRCD_05T_DERATE Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU_AC_DERATING_05T_TRC_05T_DERATE Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_CONF0 (DRAMC_AO_BASE_ADDRESS + 0x840)
    #define SHU_CONF0_MATYPE Fld(2,30,AC_MSKB3)//[31:30]
    #define SHU_CONF0_BL4 Fld(1,29,AC_MSKB3)//[29:29]
    #define SHU_CONF0_BL2 Fld(1,28,AC_MSKB3)//[28:28]
    #define SHU_CONF0_CL2 Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU_CONF0_FDIV2 Fld(1,25,AC_MSKB3)//[25:25]
    #define SHU_CONF0_FREQDIV4 Fld(1,24,AC_MSKB3)//[24:24]
    #define SHU_CONF0_REQQUE_DEPTH Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU_CONF0_REFTHD Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU_CONF0_TRFCPBIG Fld(1,9,AC_MSKB1)//[9:9]
    #define SHU_CONF0_ADVPREEN Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU_CONF0_ADVREFEN Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU_CONF0_DMPGTIM Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU_CONF1 (DRAMC_AO_BASE_ADDRESS + 0x844)
    #define SHU_CONF1_TREFBWIG Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU_CONF1_DATLAT_DSEL_PHY Fld(5,26,AC_MSKB3)//[30:26]
    #define SHU_CONF1_REFBW_FR Fld(10,16,AC_MSKW32)//[25:16]
    #define SHU_CONF1_DATLAT_DSEL Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU_CONF1_DATLAT Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_SHU_CONF2 (DRAMC_AO_BASE_ADDRESS + 0x848)
    #define SHU_CONF2_FASTWAKE Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU_CONF2_DAREFEN Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU_CONF2_FASTWAKE2 Fld(1,29,AC_MSKB3)//[29:29]
    #define SHU_CONF2_WPRE2T Fld(1,28,AC_MSKB3)//[28:28]
    #define SHU_CONF2_RA15TOCS1 Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU_CONF2_DQ16COM1 Fld(1,26,AC_MSKB3)//[26:26]
    #define SHU_CONF2_DQCMD Fld(1,25,AC_MSKB3)//[25:25]
    #define SHU_CONF2_DCMDLYREF Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_CONF2_FSPCHG_PRDCNT Fld(8,8,AC_FULLB1)//[15:8]
    #define SHU_CONF2_TCMDO1LAT Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_SHU_CONF3 (DRAMC_AO_BASE_ADDRESS + 0x84C)
    #define SHU_CONF3_REFRCNT Fld(9,16,AC_MSKW32)//[24:16]
    #define SHU_CONF3_ZQCSCNT Fld(9,0,AC_MSKW10)//[8:0]
#define DRAMC_REG_SHU_RANKCTL (DRAMC_AO_BASE_ADDRESS + 0x858)
    #define SHU_RANKCTL_RANKINCTL_PHY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU_RANKCTL_RANKINCTL_ROOT1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU_RANKCTL_RANKINCTL Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU_RANKCTL_TXRANKINCTL_ROOT Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU_RANKCTL_TXRANKINCTL Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU_RANKCTL_DQSG_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define SHU_RANKCTL_PICGLAT Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_RANKCTL_DMSTBLAT Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_SHU_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x85C)
    #define SHU_CKECTRL_SREF_CK_DLY Fld(2,28,AC_MSKB3)//[29:28]
    #define SHU_CKECTRL_TCKESRX Fld(2,24,AC_MSKB3)//[25:24]
    #define SHU_CKECTRL_CKEPRD Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_CKECTRL_CMDCKE Fld(3,16,AC_MSKB2)//[18:16]
#define DRAMC_REG_SHU_ODTCTRL (DRAMC_AO_BASE_ADDRESS + 0x860)
    #define SHU_ODTCTRL_RODTE Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU_ODTCTRL_RODTE2 Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU_ODTCTRL_FIXRODT Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU_ODTCTRL_TWODT Fld(7,16,AC_MSKB2)//[22:16]
    #define SHU_ODTCTRL_RODT Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU_ODTCTRL_WOEN Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU_ODTCTRL_ROEN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_IMPCAL1 (DRAMC_AO_BASE_ADDRESS + 0x864)
    #define SHU_IMPCAL1_IMPCAL_CALICNT Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU_IMPCAL1_IMPCALCNT Fld(8,20,AC_MSKW32)//[27:20]
    #define SHU_IMPCAL1_IMPCAL_CALEN_CYCLE Fld(3,17,AC_MSKB2)//[19:17]
    #define SHU_IMPCAL1_IMPDRVN Fld(5,11,AC_MSKB1)//[15:11]
    #define SHU_IMPCAL1_IMPDRVP Fld(5,4,AC_MSKW10)//[8:4]
    #define SHU_IMPCAL1_IMPCAL_CHKCYCLE Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU1_DQSOSC_PRD (DRAMC_AO_BASE_ADDRESS + 0x868)
    #define SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC Fld(8,24,AC_FULLB3)//[31:24]
    #define SHU1_DQSOSC_PRD_DQSOSCTHRD_INC Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU1_DQSOSC_PRD_DQSOSC_PRDCNT Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x86C)
    #define SHU_DQSOSCR_DQSOSC_DELTA Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU_DQSOSCR_DQSOSCRCNT Fld(8,0,AC_FULLB0)//[7:0]
#define DRAMC_REG_SHU_DQSOSCR2 (DRAMC_AO_BASE_ADDRESS + 0x870)
    #define SHU_DQSOSCR2_DQSOSC_DRS_ADV_SEL Fld(2,18,AC_MSKB2)//[19:18]
    #define SHU_DQSOSCR2_DQSOSC_ADV_SEL Fld(2,16,AC_MSKB2)//[17:16]
    #define SHU_DQSOSCR2_DQSOSCENCNT Fld(9,0,AC_MSKW10)//[8:0]
#define DRAMC_REG_SHU_RODTENSTB (DRAMC_AO_BASE_ADDRESS + 0x874)
    #define SHU_RODTENSTB_RODTENSTB_EXT Fld(8,8,AC_FULLB1)//[15:8]
    #define SHU_RODTENSTB_RODTENSTB_OFFSET Fld(6,2,AC_MSKB0)//[7:2]
    #define SHU_RODTENSTB_RODTEN_MCK_MODESEL Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_PIPE (DRAMC_AO_BASE_ADDRESS + 0x878)
    #define SHU_PIPE_READ_START_EXTEND1 Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU_PIPE_DLE_LAST_EXTEND1 Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU_PIPE_READ_START_EXTEND2 Fld(1,29,AC_MSKB3)//[29:29]
    #define SHU_PIPE_DLE_LAST_EXTEND2 Fld(1,28,AC_MSKB3)//[28:28]
    #define SHU_PIPE_READ_START_EXTEND3 Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU_PIPE_DLE_LAST_EXTEND3 Fld(1,26,AC_MSKB3)//[26:26]
    #define SHU_PIPE_PHYPIPE3EN Fld(1,10,AC_MSKB1)//[10:10]
    #define SHU_PIPE_PHYPIPE2EN Fld(1,9,AC_MSKB1)//[9:9]
    #define SHU_PIPE_PHYPIPE1EN Fld(1,8,AC_MSKB1)//[8:8]
    #define SHU_PIPE_PHYRXRDSLPIPE3 Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU_PIPE_PHYRXRDSLPIPE2 Fld(1,5,AC_MSKB0)//[5:5]
    #define SHU_PIPE_PHYRXRDSLPIPE1 Fld(1,4,AC_MSKB0)//[4:4]
    #define SHU_PIPE_PHYRXPIPE3 Fld(1,2,AC_MSKB0)//[2:2]
    #define SHU_PIPE_PHYRXPIPE2 Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU_PIPE_PHYRXPIPE1 Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_TEST1 (DRAMC_AO_BASE_ADDRESS + 0x87C)
    #define SHU_TEST1_DQSICALI_NEW Fld(1,23,AC_MSKB2)//[23:23]
    #define SHU_TEST1_DQSICALBLCOK_CNT Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_TEST1_LATNORMPOP Fld(5,8,AC_MSKB1)//[12:8]
#define DRAMC_REG_SHU_SELPH_CA1 (DRAMC_AO_BASE_ADDRESS + 0x880)
    #define SHU_SELPH_CA1_TXDLY_CS1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_CA1_TXDLY_RAS Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA1_TXDLY_CAS Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_CA1_TXDLY_WE Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA1_TXDLY_RESET Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_CA1_TXDLY_ODT Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA1_TXDLY_CKE Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA1_TXDLY_CS Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA2 (DRAMC_AO_BASE_ADDRESS + 0x884)
    #define SHU_SELPH_CA2_TXDLY_CKE1 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA2_TXDLY_CMD Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA2_TXDLY_BA2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA2_TXDLY_BA1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA2_TXDLY_BA0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA3 (DRAMC_AO_BASE_ADDRESS + 0x888)
    #define SHU_SELPH_CA3_TXDLY_RA7 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_CA3_TXDLY_RA6 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA3_TXDLY_RA5 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_CA3_TXDLY_RA4 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA3_TXDLY_RA3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_CA3_TXDLY_RA2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA3_TXDLY_RA1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA3_TXDLY_RA0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA4 (DRAMC_AO_BASE_ADDRESS + 0x88C)
    #define SHU_SELPH_CA4_TXDLY_RA15 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_CA4_TXDLY_RA14 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA4_TXDLY_RA13 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_CA4_TXDLY_RA12 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA4_TXDLY_RA11 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_CA4_TXDLY_RA10 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA4_TXDLY_RA9 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA4_TXDLY_RA8 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA5 (DRAMC_AO_BASE_ADDRESS + 0x890)
    #define SHU_SELPH_CA5_DLY_CS1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_CA5_DLY_RAS Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA5_DLY_CAS Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_CA5_DLY_WE Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA5_DLY_RESET Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_CA5_DLY_ODT Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA5_DLY_CKE Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA5_DLY_CS Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA6 (DRAMC_AO_BASE_ADDRESS + 0x894)
    #define SHU_SELPH_CA6_DLY_CKE1 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA6_DLY_BA2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA6_DLY_BA1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA6_DLY_BA0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA7 (DRAMC_AO_BASE_ADDRESS + 0x898)
    #define SHU_SELPH_CA7_DLY_RA7 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_CA7_DLY_RA6 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA7_DLY_RA5 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_CA7_DLY_RA4 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA7_DLY_RA3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_CA7_DLY_RA2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA7_DLY_RA1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA7_DLY_RA0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_CA8 (DRAMC_AO_BASE_ADDRESS + 0x89C)
    #define SHU_SELPH_CA8_DLY_RA15 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_CA8_DLY_RA14 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_CA8_DLY_RA13 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_CA8_DLY_RA12 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_CA8_DLY_RA11 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_CA8_DLY_RA10 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_CA8_DLY_RA9 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_CA8_DLY_RA8 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_DQS0 (DRAMC_AO_BASE_ADDRESS + 0x8A0)
    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_DQS0_TXDLY_DQS3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_DQS0_TXDLY_DQS2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_DQS0_TXDLY_DQS1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_DQS0_TXDLY_DQS0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU_SELPH_DQS1 (DRAMC_AO_BASE_ADDRESS + 0x8A4)
    #define SHU_SELPH_DQS1_DLY_OEN_DQS3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU_SELPH_DQS1_DLY_OEN_DQS2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU_SELPH_DQS1_DLY_OEN_DQS1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU_SELPH_DQS1_DLY_OEN_DQS0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU_SELPH_DQS1_DLY_DQS3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU_SELPH_DQS1_DLY_DQS2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_SELPH_DQS1_DLY_DQS1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHU_SELPH_DQS1_DLY_DQS0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU1_DRVING1 (DRAMC_AO_BASE_ADDRESS + 0x8A8)
    #define SHU1_DRVING1_DQSDRV2 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU1_RG_TX_ARDQS0_DRVP_B01 Fld(5,15,AC_MSKW21)//[19:15]
    #define SHU1_RG_TX_ARDQS0_DRVN_B01 Fld(5,10,AC_MSKB1)//[14:10]
    #define SHU1_DRVING1_DQDRV2 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU1_DRVING2 (DRAMC_AO_BASE_ADDRESS + 0x8AC)
    #define SHU1_RG_TX_ARDQ_DRVP_B01 Fld(5,25,AC_MSKB3)//[29:25]
    #define SHU1_RG_TX_ARDQ_DRVN_B01 Fld(5,20,AC_MSKW32)//[24:20]
    #define SHU1_RG_TX_ARCLK_DRVP Fld(5,15,AC_MSKW21)//[19:15]
    #define SHU1_RG_TX_ARCLK_DRVN Fld(5,10,AC_MSKB1)//[14:10]
    #define SHU1_RG_TX_ARCMD_DRVP Fld(5,5,AC_MSKW10)//[9:5]
    #define SHU1_RG_TX_ARCMD_DRVN Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_SHU1_DRVING3 (DRAMC_AO_BASE_ADDRESS + 0x8B0)
    #define SHU1_DRVING3_DQSODT2 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU1_RG_TX_ARDQS0_ODTP_B01 Fld(5,15,AC_MSKW21)//[19:15]
    #define SHU1_RG_TX_ARDQS0_ODTN_B01 Fld(5,10,AC_MSKB1)//[14:10]
    #define SHU1_DRVING3_DQODT2 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU1_DRVING4 (DRAMC_AO_BASE_ADDRESS + 0x8B4)
    #define SHU1_RG_TX_ARDQ_ODTP_B01 Fld(5,25,AC_MSKB3)//[29:25]
    #define SHU1_RG_TX_ARDQ_ODTN_B01 Fld(5,20,AC_MSKW32)//[24:20]
    #define SHU1_DRVING4_CMDODT2 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU1_DRVING4_CMDODT1 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU1_DRVING5 (DRAMC_AO_BASE_ADDRESS + 0x8B8)
    #define SHU1_DRVING5_DQCDRV2 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU1_DRVING5_DQCDRV1 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU1_DRVING5_DQCODT2 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU1_DRVING6 (DRAMC_AO_BASE_ADDRESS + 0x8BC)
    #define SHU1_DRVING6_DQCODT1 Fld(10,20,AC_MSKW32)//[29:20]
#define DRAMC_REG_SHU1_WODT (DRAMC_AO_BASE_ADDRESS + 0x8C0)
    #define SHU1_WODT_WPST2T Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU1_WODT_TWPSTEXT Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU1_WODT_DBIWR Fld(1,29,AC_MSKB3)//[29:29]
    #define SHU1_WODT_TXUPD_W2R_SEL Fld(3,14,AC_MSKW21)//[16:14]
    #define SHU1_WODT_TXUPD_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define SHU1_WODT_DQOE_OPT Fld(1,11,AC_MSKB1)//[11:11]
    #define SHU1_WODT_DQOE_CNT Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU1_WODT_WODTPDEN Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU1_WODT_DISWODTE2 Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU1_WODT_DISWODTE Fld(1,5,AC_MSKB0)//[5:5]
    #define SHU1_WODT_WODTFIXOFF Fld(1,4,AC_MSKB0)//[4:4]
    #define SHU1_WODT_WODTFIX Fld(1,3,AC_MSKB0)//[3:3]
    #define SHU1_WODT_DISWODT Fld(3,0,AC_MSKB0)//[2:0]

//Page DRAMC_5
#define DRAMC_REG_SHU1_DQSG (DRAMC_AO_BASE_ADDRESS + 0x8C4)
    #define SHU1_DQSG_DQSINCTL_PRE_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define SHU1_DQSG_STB_UPDMASKCYC Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_DQSG_STB_UPDMASK_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define SHU1_DQSG_R_RSTBCNT_LATCH_OPT Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU1_DQSG_DLLFRZWROPT Fld(2,4,AC_MSKB0)//[5:4]
    #define SHU1_DQSG_DLLFRZRFCOPT Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_SHU_SCINTV (DRAMC_AO_BASE_ADDRESS + 0x8C8)
    #define SHU_SCINTV_DQSOSCENDIS Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU_SCINTV_DQS2DQ_FILT_PITHRD Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU_SCINTV_DQS2DQ_SHU_PITHRD Fld(6,18,AC_MSKB2)//[23:18]
    #define SHU_SCINTV_MRW_INTV Fld(5,13,AC_MSKW21)//[17:13]
    #define SHU_SCINTV_RDDQC_INTV Fld(2,11,AC_MSKB1)//[12:11]
    #define SHU_SCINTV_SCINTV Fld(5,6,AC_MSKW10)//[10:6]
    #define SHU_SCINTV_TZQLAT Fld(5,1,AC_MSKB0)//[5:1]
    #define SHU_SCINTV_ODTREN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU_MISC (DRAMC_AO_BASE_ADDRESS + 0x8CC)
    #define SHU_MISC_PREA_INTV Fld(5,12,AC_MSKW21)//[16:12]
    #define SHU_MISC_NORMPOP_LEN Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU_MISC_CKEHCMD Fld(2,4,AC_MSKB0)//[5:4]
    #define SHU_MISC_REQQUE_MAXCNT Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_SHU_DQS2DQ_TX (DRAMC_AO_BASE_ADDRESS + 0x8D0)
    #define SHU_DQS2DQ_TX_OE2DQ_OFFSET Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_SHU_HWSET_MR2 (DRAMC_AO_BASE_ADDRESS + 0x8D4)
    #define SHU_HWSET_MR2_HWSET_MR2_OP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU_HWSET_MR2_HWSET_MR2_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_SHU_HWSET_MR13 (DRAMC_AO_BASE_ADDRESS + 0x8D8)
    #define SHU_HWSET_MR13_HWSET_MR13_OP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU_HWSET_MR13_HWSET_MR13_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_SHU_HWSET_VRCG (DRAMC_AO_BASE_ADDRESS + 0x8DC)
    #define SHU_HWSET_VRCG_HWSET_VRCG_OP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_SHURK0_DQSCTL (DRAMC_AO_BASE_ADDRESS + 0xA00)
    #define SHURK0_DQSCTL_DQSINCTL Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_SHURK0_DQSIEN (DRAMC_AO_BASE_ADDRESS + 0xA04)
    #define SHURK0_DQSIEN_R0DQS3IEN Fld(7,24,AC_MSKB3)//[30:24]
    #define SHURK0_DQSIEN_R0DQS2IEN Fld(7,16,AC_MSKB2)//[22:16]
    #define SHURK0_DQSIEN_R0DQS1IEN Fld(7,8,AC_MSKB1)//[14:8]
    #define SHURK0_DQSIEN_R0DQS0IEN Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_SHURK0_DQSCAL (DRAMC_AO_BASE_ADDRESS + 0xA08)
    #define SHURK0_DQSCAL_R0DQSIENHLMTEN Fld(1,15,AC_MSKB1)//[15:15]
    #define SHURK0_DQSCAL_R0DQSIENHLMT Fld(7,8,AC_MSKB1)//[14:8]
    #define SHURK0_DQSCAL_R0DQSIENLLMTEN Fld(1,7,AC_MSKB0)//[7:7]
    #define SHURK0_DQSCAL_R0DQSIENLLMT Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_SHU1RK0_PI (DRAMC_AO_BASE_ADDRESS + 0xA0C)
    #define SHU1RK0_PI_RK0_ARPI_DQM_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1RK0_PI_RK0_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1RK0_PI_RK0_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1RK0_PI_RK0_ARPI_DQ_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU1RK0_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0xA10)
    #define SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1RK0_DQSOSC_DQSOSC_BASE_RK0 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_SHURK0_SELPH_ODTEN0 (DRAMC_AO_BASE_ADDRESS + 0xA1C)
    #define SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_ODTEN1 (DRAMC_AO_BASE_ADDRESS + 0xA20)
    #define SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_DQSG0 (DRAMC_AO_BASE_ADDRESS + 0xA24)
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_DQSG1 (DRAMC_AO_BASE_ADDRESS + 0xA28)
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0xA2C)
    #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_DQ0_TXDLY_DQ3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_DQ0_TXDLY_DQ2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_DQ0_TXDLY_DQ1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_DQ0_TXDLY_DQ0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0xA30)
    #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_DQ1_TXDLY_DQM3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_DQ1_TXDLY_DQM2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_DQ1_TXDLY_DQM1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_DQ1_TXDLY_DQM0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0xA34)
    #define SHURK0_SELPH_DQ2_DLY_OEN_DQ3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_DQ2_DLY_OEN_DQ2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_DQ2_DLY_OEN_DQ1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_DQ2_DLY_OEN_DQ0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_DQ2_DLY_DQ3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_DQ2_DLY_DQ2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_DQ2_DLY_DQ1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_DQ2_DLY_DQ0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK0_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0xA38)
    #define SHURK0_SELPH_DQ3_DLY_OEN_DQM3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK0_SELPH_DQ3_DLY_OEN_DQM2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK0_SELPH_DQ3_DLY_OEN_DQM1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK0_SELPH_DQ3_DLY_OEN_DQM0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK0_SELPH_DQ3_DLY_DQM3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK0_SELPH_DQ3_DLY_DQM2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK0_SELPH_DQ3_DLY_DQM1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK0_SELPH_DQ3_DLY_DQM0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU1RK0_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0xA40)
    #define SHU1RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU1RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU1RK0_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0xA44)
    #define SHU1RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU1RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU1RK0_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0xA48)
    #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 Fld(5,17,AC_MSKB2)//[21:17]
    #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 Fld(5,12,AC_MSKW21)//[16:12]
    #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU1RK0_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0xA4C)
    #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 Fld(5,17,AC_MSKB2)//[21:17]
    #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 Fld(5,12,AC_MSKW21)//[16:12]
    #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU1RK0_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0xA50)
    #define SHU1RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU1RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHURK1_DQSCTL (DRAMC_AO_BASE_ADDRESS + 0xB00)
    #define SHURK1_DQSCTL_R1DQSINCTL Fld(4,0,AC_MSKB0)//[3:0]
#define DRAMC_REG_SHURK1_DQSIEN (DRAMC_AO_BASE_ADDRESS + 0xB04)
    #define SHURK1_DQSIEN_R1DQS3IEN Fld(7,24,AC_MSKB3)//[30:24]
    #define SHURK1_DQSIEN_R1DQS2IEN Fld(7,16,AC_MSKB2)//[22:16]
    #define SHURK1_DQSIEN_R1DQS1IEN Fld(7,8,AC_MSKB1)//[14:8]
    #define SHURK1_DQSIEN_R1DQS0IEN Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_SHURK1_DQSCAL (DRAMC_AO_BASE_ADDRESS + 0xB08)
    #define SHURK1_DQSCAL_R1DQSIENHLMTEN Fld(1,15,AC_MSKB1)//[15:15]
    #define SHURK1_DQSCAL_R1DQSIENHLMT Fld(7,8,AC_MSKB1)//[14:8]
    #define SHURK1_DQSCAL_R1DQSIENLLMTEN Fld(1,7,AC_MSKB0)//[7:7]
    #define SHURK1_DQSCAL_R1DQSIENLLMT Fld(7,0,AC_MSKB0)//[6:0]
#define DRAMC_REG_SHU1RK1_PI (DRAMC_AO_BASE_ADDRESS + 0xB0C)
    #define SHU1RK1_PI_RK1_ARPI_DQM_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1RK1_PI_RK1_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1RK1_PI_RK1_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1RK1_PI_RK1_ARPI_DQ_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU1RK1_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0xB10)
    #define SHU1RK1_DQSOSC_DQSOSC_BASE_RK1_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1RK1_DQSOSC_DQSOSC_BASE_RK1 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_SHURK1_SELPH_ODTEN0 (DRAMC_AO_BASE_ADDRESS + 0xB1C)
    #define SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_ODTEN1 (DRAMC_AO_BASE_ADDRESS + 0xB20)
    #define SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_DQSG0 (DRAMC_AO_BASE_ADDRESS + 0xB24)
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_DQSG1 (DRAMC_AO_BASE_ADDRESS + 0xB28)
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0xB2C)
    #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0xB30)
    #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0xB34)
    #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_DQ2_DLY_R1DQ3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_DQ2_DLY_R1DQ2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_DQ2_DLY_R1DQ1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_DQ2_DLY_R1DQ0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHURK1_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0xB38)
    #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHURK1_SELPH_DQ3_DLY_R1DQM3 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHURK1_SELPH_DQ3_DLY_R1DQM2 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHURK1_SELPH_DQ3_DLY_R1DQM1 Fld(3,4,AC_MSKB0)//[6:4]
    #define SHURK1_SELPH_DQ3_DLY_R1DQM0 Fld(3,0,AC_MSKB0)//[2:0]
#define DRAMC_REG_SHU1RK1_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0xB40)
    #define SHU1RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU1RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU1RK1_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0xB44)
    #define SHU1RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU1RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU1RK1_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0xB48)
    #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 Fld(5,17,AC_MSKB2)//[21:17]
    #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 Fld(5,12,AC_MSKW21)//[16:12]
    #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU1RK1_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0xB4C)
    #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 Fld(5,17,AC_MSKB2)//[21:17]
    #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 Fld(5,12,AC_MSKW21)//[16:12]
    #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU1RK1_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0xB50)
    #define SHU1RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU1RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU_DQSG_RETRY (DRAMC_AO_BASE_ADDRESS + 0xC54)
    #define SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY Fld(1,28,AC_MSKB3)//[28:28]
    #define SHU_DQSG_RETRY_R_RETRY_ROUND_NUM Fld(2,24,AC_MSKB3)//[25:24]
    #define SHU_DQSG_RETRY_R_RDY_SEL_DLE Fld(1,21,AC_MSKB2)//[21:21]
    #define SHU_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK Fld(1,20,AC_MSKB2)//[20:20]
    #define SHU_DQSG_RETRY_R_DQBUG_BYTE_SEL Fld(2,18,AC_MSKB2)//[19:18]
    #define SHU_DQSG_RETRY_R_DQBUG_RANK_SEL Fld(2,16,AC_MSKB2)//[17:16]
    #define SHU_DQSG_RETRY_R_RETRY_CMP_DATA Fld(1,15,AC_MSKB1)//[15:15]
    #define SHU_DQSG_RETRY_R_XSR_RETRY_SPM_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define SHU_DQSG_RETRY_R_XSR_DQSG_RETRY_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define SHU_DQSG_RETRY_R_STBENCMP_ALLBYTE Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU_DQSG_RETRY_R_DQSIENLAT Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU_DQSG_RETRY_R_DM4BYTE Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU_DQSG_RETRY_R_RETRY_SAV_MSK Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU_DQSG_RETRY_R_RETRY_1RANK Fld(1,5,AC_MSKB0)//[5:5]
    #define SHU_DQSG_RETRY_R_RETRY_3TIMES Fld(1,4,AC_MSKB0)//[4:4]
    #define SHU_DQSG_RETRY_R_RETRY_ONCE Fld(1,3,AC_MSKB0)//[3:3]
    #define SHU_DQSG_RETRY_R_DDR1866_PLUS Fld(1,2,AC_MSKB0)//[2:2]
    #define SHU_DQSG_RETRY_R_DQSG_RETRY_SW_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU_DQSG_RETRY_R_DQSGRETRY_SW_RESET Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU2_ACTIM0 (DRAMC_AO_BASE_ADDRESS + 0xE00)
    #define SHU2_ACTIM0_SHU2_ACTIM0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ACTIM1 (DRAMC_AO_BASE_ADDRESS + 0xE04)
    #define SHU2_ACTIM1_SHU2_ACTIM1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ACTIM2 (DRAMC_AO_BASE_ADDRESS + 0xE08)
    #define SHU2_ACTIM2_SHU2_ACTIM2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ACTIM3 (DRAMC_AO_BASE_ADDRESS + 0xE0C)
    #define SHU2_ACTIM3_SHU2_ACTIM3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ACTIM4 (DRAMC_AO_BASE_ADDRESS + 0xE10)
    #define SHU2_ACTIM4_SHU2_ACTIM4 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ACTIM5 (DRAMC_AO_BASE_ADDRESS + 0xE14)
    #define SHU2_ACTIM5_SHU2_ACTIM5 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ACTIM_XRT (DRAMC_AO_BASE_ADDRESS + 0xE1C)
    #define SHU2_ACTIM_XRT_SHU2_ACTIM_XRT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_AC_TIME_05T (DRAMC_AO_BASE_ADDRESS + 0xE20)
    #define SHU2_AC_TIME_05T_SHU2_AC_TIME_05T Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_AC_DERATING0 (DRAMC_AO_BASE_ADDRESS + 0xE24)
    #define SHU2_AC_DERATING0_SHU2_AC_DERATING0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_AC_DERATING1 (DRAMC_AO_BASE_ADDRESS + 0xE28)
    #define SHU2_AC_DERATING1_SHU2_AC_DERATING1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_AC_DERATING_05T (DRAMC_AO_BASE_ADDRESS + 0xE30)
    #define SHU2_AC_DERATING_05T_SHU2_AC_DERATING_05T Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_CONF0 (DRAMC_AO_BASE_ADDRESS + 0xE40)
    #define SHU2_CONF0_SHU2_CONF0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_CONF1 (DRAMC_AO_BASE_ADDRESS + 0xE44)
    #define SHU2_CONF1_SHU2_CONF1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_CONF2 (DRAMC_AO_BASE_ADDRESS + 0xE48)
    #define SHU2_CONF2_SHU2_CONF2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_CONF3 (DRAMC_AO_BASE_ADDRESS + 0xE4C)
    #define SHU2_CONF3_SHU2_CONF3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_RANKCTL (DRAMC_AO_BASE_ADDRESS + 0xE58)
    #define SHU2_RANKCTL_SHU2_RANKCTL Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0xE5C)
    #define SHU2_CKECTRL_SHU2_CKECTRL Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_ODTCTRL (DRAMC_AO_BASE_ADDRESS + 0xE60)
    #define SHU2_ODTCTRL_SHU2_ODTCTRL Fld(32,0,AC_FULLDW)//[31:0]

//Page DRAMC_6
#define DRAMC_REG_SHU2_IMPCAL1 (DRAMC_AO_BASE_ADDRESS + 0xE64)
    #define SHU2_IMPCAL1_SHU2_IMPCAL1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_DQSOSC_PRD (DRAMC_AO_BASE_ADDRESS + 0xE68)
    #define SHU2_DQSOSC_PRD_DQSOSCTHRD_DEC Fld(8,24,AC_FULLB3)//[31:24]
    #define SHU2_DQSOSC_PRD_DQSOSCTHRD_INC Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU2_DQSOSC_PRD_DQSOSC_PRDCNT Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU2_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0xE6C)
    #define SHU2_DQSOSCR_SHU2_DQSOSCR Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_DQSOSCR2 (DRAMC_AO_BASE_ADDRESS + 0xE70)
    #define SHU2_DQSOSCR2_SHU2_DQSOSCR2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_RODTENSTB (DRAMC_AO_BASE_ADDRESS + 0xE74)
    #define SHU2_RODTENSTB_SHU2_RODTENSTB Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_PIPE (DRAMC_AO_BASE_ADDRESS + 0xE78)
    #define SHU2_PIPE_SHU2_PIPE Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_TEST1 (DRAMC_AO_BASE_ADDRESS + 0xE7C)
    #define SHU2_TEST1_SHU2_TEST1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA1 (DRAMC_AO_BASE_ADDRESS + 0xE80)
    #define SHU2_SELPH_CA1_SHU2_SELPH_CA1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA2 (DRAMC_AO_BASE_ADDRESS + 0xE84)
    #define SHU2_SELPH_CA2_SHU2_SELPH_CA2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA3 (DRAMC_AO_BASE_ADDRESS + 0xE88)
    #define SHU2_SELPH_CA3_SHU2_SELPH_CA3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA4 (DRAMC_AO_BASE_ADDRESS + 0xE8C)
    #define SHU2_SELPH_CA4_SHU2_SELPH_CA4 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA5 (DRAMC_AO_BASE_ADDRESS + 0xE90)
    #define SHU2_SELPH_CA5_SHU2_SELPH_CA5 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA6 (DRAMC_AO_BASE_ADDRESS + 0xE94)
    #define SHU2_SELPH_CA6_SHU2_SELPH_CA6 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA7 (DRAMC_AO_BASE_ADDRESS + 0xE98)
    #define SHU2_SELPH_CA7_SHU2_SELPH_CA7 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_CA8 (DRAMC_AO_BASE_ADDRESS + 0xE9C)
    #define SHU2_SELPH_CA8_SHU2_SELPH_CA8 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_DQS0 (DRAMC_AO_BASE_ADDRESS + 0xEA0)
    #define SHU2_SELPH_DQS0_SHU2_SELPH_DQS0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_SELPH_DQS1 (DRAMC_AO_BASE_ADDRESS + 0xEA4)
    #define SHU2_SELPH_DQS1_SHU2_SELPH_DQS1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_DRVING1 (DRAMC_AO_BASE_ADDRESS + 0xEA8)
    #define SHU2_DRVING1_DQSDRV2 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU2_DRVING1_DQSDRV1 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU2_DRVING1_DQDRV2 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU2_DRVING2 (DRAMC_AO_BASE_ADDRESS + 0xEAC)
    #define SHU2_DRVING2_DQDRV1 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU2_DRVING2_CMDDRV2 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU2_DRVING2_CMDDRV1 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU2_DRVING3 (DRAMC_AO_BASE_ADDRESS + 0xEB0)
    #define SHU2_DRVING3_DQSODT2 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU2_DRVING3_DQSODT1 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU2_DRVING3_DQODT2 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU2_DRVING4 (DRAMC_AO_BASE_ADDRESS + 0xEB4)
    #define SHU2_DRVING4_DQODT1 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU2_DRVING4_CMDODT2 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU2_DRVING4_CMDODT1 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU2_DRVING5 (DRAMC_AO_BASE_ADDRESS + 0xEB8)
    #define SHU2_DRVING5_DQCDRV2 Fld(10,20,AC_MSKW32)//[29:20]
    #define SHU2_DRVING5_DQCDRV1 Fld(10,10,AC_MSKW21)//[19:10]
    #define SHU2_DRVING5_DQCODT2 Fld(10,0,AC_MSKW10)//[9:0]
#define DRAMC_REG_SHU2_DRVING6 (DRAMC_AO_BASE_ADDRESS + 0xEBC)
    #define SHU2_DRVING6_DQCODT1 Fld(10,20,AC_MSKW32)//[29:20]
#define DRAMC_REG_SHU2_WODT (DRAMC_AO_BASE_ADDRESS + 0xEC0)
    #define SHU2_WODT_SHU2_WODT Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_DQSG (DRAMC_AO_BASE_ADDRESS + 0xEC4)
    #define SHU2_DQSG_STB_UPDMASKCYC Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU2_DQSG_STB_UPDMASK_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define SHU2_DQSG_R_RSTBCNT_LATCH_OPT Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU2_DQSG_DLLFRZWROPT Fld(2,4,AC_MSKB0)//[5:4]
    #define SHU2_DQSG_DLLFRZRFCOPT Fld(2,0,AC_MSKB0)//[1:0]
#define DRAMC_REG_SHU2_SCINTV (DRAMC_AO_BASE_ADDRESS + 0xEC8)
    #define SHU2_SCINTV_DQS2DQ_SHU_PITHRD Fld(6,18,AC_MSKB2)//[23:18]
    #define SHU2_SCINTV_MRW_INTV Fld(5,13,AC_MSKW21)//[17:13]
    #define SHU2_SCINTV_RDDQC_INTV Fld(2,11,AC_MSKB1)//[12:11]
    #define SHU2_SCINTV_SCINTV Fld(5,6,AC_MSKW10)//[10:6]
    #define SHU2_SCINTV_TZQLAT Fld(5,1,AC_MSKB0)//[5:1]
    #define SHU2_SCINTV_ODTREN Fld(1,0,AC_MSKB0)//[0:0]
#define DRAMC_REG_SHU2_MISC (DRAMC_AO_BASE_ADDRESS + 0xECC)
    #define SHU2_MISC_SHU2_MISC Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2_DQS2DQ_TX (DRAMC_AO_BASE_ADDRESS + 0xED0)
    #define SHU2_DQS2DQ_TX_FREQ_RATIO_TX Fld(5,0,AC_MSKB0)//[4:0]
#define DRAMC_REG_SHU2_HWSET_MR2 (DRAMC_AO_BASE_ADDRESS + 0xED4)
    #define SHU2_HWSET_MR2_HWSET_MR2_OP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU2_HWSET_MR2_HWSET_MR2_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_SHU2_HWSET_MR13 (DRAMC_AO_BASE_ADDRESS + 0xED8)
    #define SHU2_HWSET_MR13_HWSET_MR13_OP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU2_HWSET_MR13_HWSET_MR13_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_SHU2_HWSET_VRCG (DRAMC_AO_BASE_ADDRESS + 0xEDC)
    #define SHU2_HWSET_VRCG_HWSET_VRCG_OP Fld(8,16,AC_FULLB2)//[23:16]
    #define SHU2_HWSET_VRCG_HWSET_VRCG_MRSMA Fld(13,0,AC_MSKW10)//[12:0]
#define DRAMC_REG_SHU2RK0_DQSCTL (DRAMC_AO_BASE_ADDRESS + 0x1000)
    #define SHU2RK0_DQSCTL_SHU2RK0_DQSCTL Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_DQSIEN (DRAMC_AO_BASE_ADDRESS + 0x1004)
    #define SHU2RK0_DQSIEN_SHU2RK0_DQSIEN Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_DQSCAL (DRAMC_AO_BASE_ADDRESS + 0x1008)
    #define SHU2RK0_DQSCAL_SHU2RK0_DQSCAL Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_PI (DRAMC_AO_BASE_ADDRESS + 0x100C)
    #define SHU2RK0_PI_RK0_ARPI_DQM_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU2RK0_PI_RK0_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU2RK0_PI_RK0_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU2RK0_PI_RK0_ARPI_DQ_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU2RK0_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x1010)
    #define SHU2RK0_DQSOSC_DQSOSC_BASE_RK0_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU2RK0_DQSOSC_DQSOSC_BASE_RK0 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_SHU2RK0_SELPH_ODTEN0 (DRAMC_AO_BASE_ADDRESS + 0x101C)
    #define SHU2RK0_SELPH_ODTEN0_SHU2RK0_SELPH_ODTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_ODTEN1 (DRAMC_AO_BASE_ADDRESS + 0x1020)
    #define SHU2RK0_SELPH_ODTEN1_SHU2RK0_SELPH_ODTEN1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_DQSG0 (DRAMC_AO_BASE_ADDRESS + 0x1024)
    #define SHU2RK0_SELPH_DQSG0_SHU2RK0_SELPH_DQSG0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_DQSG1 (DRAMC_AO_BASE_ADDRESS + 0x1028)
    #define SHU2RK0_SELPH_DQSG1_SHU2RK0_SELPH_DQSG1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0x102C)
    #define SHU2RK0_SELPH_DQ0_SHU2RK0_SELPH_DQ0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0x1030)
    #define SHU2RK0_SELPH_DQ1_SHU2RK0_SELPH_DQ1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0x1034)
    #define SHU2RK0_SELPH_DQ2_SHU2RK0_SELPH_DQ2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0x1038)
    #define SHU2RK0_SELPH_DQ3_SHU2RK0_SELPH_DQ3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK0_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0x1040)
    #define SHU2RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU2RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU2RK0_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0x1044)
    #define SHU2RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU2RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU2RK0_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0x1048)
    #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU2RK0_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0x104C)
    #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU2RK0_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0x1050)
    #define SHU2RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU2RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU2RK1_DQSCTL (DRAMC_AO_BASE_ADDRESS + 0x1100)
    #define SHU2RK1_DQSCTL_SHU2RK1_DQSCTL Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_DQSIEN (DRAMC_AO_BASE_ADDRESS + 0x1104)
    #define SHU2RK1_DQSIEN_SHU2RK1_DQSIEN Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_DQSCAL (DRAMC_AO_BASE_ADDRESS + 0x1108)
    #define SHU2RK1_DQSCAL_SHU2RK1_DQSCAL Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_PI (DRAMC_AO_BASE_ADDRESS + 0x110C)
    #define SHU2RK1_PI_RK1_ARPI_DQM_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU2RK1_PI_RK1_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU2RK1_PI_RK1_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU2RK1_PI_RK1_ARPI_DQ_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU2RK1_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x1110)
    #define SHU2RK1_DQSOSC_DQSOSC_BASE_RK1_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU2RK1_DQSOSC_DQSOSC_BASE_RK1 Fld(16,0,AC_FULLW10)//[15:0]
#define DRAMC_REG_SHU2RK1_SELPH_ODTEN0 (DRAMC_AO_BASE_ADDRESS + 0x111C)
    #define SHU2RK1_SELPH_ODTEN0_SHU2RK1_SELPH_ODTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_ODTEN1 (DRAMC_AO_BASE_ADDRESS + 0x1120)
    #define SHU2RK1_SELPH_ODTEN1_SHU2RK1_SELPH_ODTEN1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_DQSG0 (DRAMC_AO_BASE_ADDRESS + 0x1124)
    #define SHU2RK1_SELPH_DQSG0_SHU2RK1_SELPH_DQSG0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_DQSG1 (DRAMC_AO_BASE_ADDRESS + 0x1128)
    #define SHU2RK1_SELPH_DQSG1_SHU2RK1_SELPH_DQSG1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0x112C)
    #define SHU2RK1_SELPH_DQ0_SHU2RK1_SELPH_DQ0 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0x1130)
    #define SHU2RK1_SELPH_DQ1_SHU2RK1_SELPH_DQ1 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0x1134)
    #define SHU2RK1_SELPH_DQ2_SHU2RK1_SELPH_DQ2 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0x1138)
    #define SHU2RK1_SELPH_DQ3_SHU2RK1_SELPH_DQ3 Fld(32,0,AC_FULLDW)//[31:0]
#define DRAMC_REG_SHU2RK1_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0x1140)
    #define SHU2RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU2RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU2RK1_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0x1144)
    #define SHU2RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU2RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 Fld(11,0,AC_MSKW10)//[10:0]
#define DRAMC_REG_SHU2RK1_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0x1148)
    #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU2RK1_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0x114C)
    #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 Fld(6,6,AC_MSKW10)//[11:6]
    #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 Fld(6,0,AC_MSKB0)//[5:0]
#define DRAMC_REG_SHU2RK1_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0x1150)
    #define SHU2RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 Fld(11,16,AC_MSKW32)//[26:16]
    #define SHU2RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 Fld(11,0,AC_MSKW10)//[10:0]







///////////////////////// DDRPHY Registers ////////////////////////////////
////////////PLL only in cha

#define DDRPHY_BASE_ADDR Channel_A_PHY_BASE_ADDRESS

//Page DDRPHY_PLL
#define DDRPHY_PLL1 (DDRPHY_BASE_ADDR + 0x000)
    #define PLL1_RG_RPHYPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
#define DDRPHY_PLL2 (DDRPHY_BASE_ADDR + 0x004)
    #define PLL2_RG_RCLRPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
#define DDRPHY_PLL3 (DDRPHY_BASE_ADDR + 0x008)
    #define PLL3_RG_RPHYPLL_TST_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define PLL3_RG_RPHYPLL_TSTLVROD_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define PLL3_RG_RPHYPLL_TST_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define PLL3_RG_RPHYPLL_TSTCK_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define PLL3_RG_RPHYPLL_TSTFM_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define PLL3_RG_RPHYPLL_TSTOD_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define PLL3_RG_RPHYPLL_TSTOP_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_PLL4 (DDRPHY_BASE_ADDR + 0x00C)
    #define PLL4_RESERVED_0C Fld(1,24,AC_MSKB3)//[24:24]
    #define PLL4_RG_RPHYPLL_ADA_MCK8X_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define PLL4_RG_RPHYPLL_AD_MCK8X_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define PLL4_RG_RPHYPLL_SER_MODE Fld(1,20,AC_MSKB2)//[20:20]
    #define PLL4_RG_RPHYPLL_MCK8X_SEL Fld(1,18,AC_MSKB2)//[18:18]
    #define PLL4_RG_RPHYPLL_ATPG_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define PLL4_RG_RPHYPLL_RESETB Fld(1,16,AC_MSKB2)//[16:16]
#define DDRPHY_PLL5 (DDRPHY_BASE_ADDR + 0x010)
    #define PLL5_RG_RPHYPLL_SDM_SSC_EN Fld(1,2,AC_MSKB0)//[2:2]
#define DDRPHY_PLL7 (DDRPHY_BASE_ADDR + 0x018)
    #define PLL7_RG_RCLRPLL_SDM_SSC_EN Fld(1,2,AC_MSKB0)//[2:2]
#define DDRPHY_SHU1_PLL0 (DDRPHY_BASE_ADDR + 0xD80)
    #define SHU1_PLL0_RG_RPHYPLL_LOAD_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define SHU1_PLL0_RG_RPHYPLL_TOP_REV Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_SHU1_PLL1 (DDRPHY_BASE_ADDR + 0xD84)
    #define SHU1_PLL1_RESERVED_D84 Fld(27,5,AC_MSKDW)//[31:5]
    #define SHU1_PLL1_R_SHU_AUTO_PLL_MUX Fld(1,4,AC_MSKB0)//[4:4]
    #define SHU1_PLL1_RG_RPHYPLLGP_CK_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_SHU1_PLL2 (DDRPHY_BASE_ADDR + 0xD88)
    #define SHU1_PLL2_RG_RCLRPLL_LOAD_EN Fld(1,19,AC_MSKB2)//[19:19]
#define DDRPHY_SHU1_PLL3 (DDRPHY_BASE_ADDR + 0xD8C)
    #define SHU1_PLL3_RESERVED_D8C Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_SHU1_PLL4 (DDRPHY_BASE_ADDR + 0xD90)
    #define SHU1_PLL4_RG_RPHYPLL_BP Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU1_PLL4_RG_RPHYPLL_BR Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU1_PLL4_RG_RPHYPLL_BLP Fld(1,29,AC_MSKB3)//[29:29]
    #define SHU1_PLL4_RG_RPHYPLL_RESERVED Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_SHU1_PLL5 (DDRPHY_BASE_ADDR + 0xD94)
    #define SHU1_PLL5_RG_RPHYPLL_SDM_PCW Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_PLL5_RG_RPHYPLL_SDM_PCW_CHG Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU1_PLL5_RG_RPHYPLL_SDM_FRA_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_SHU1_PLL6 (DDRPHY_BASE_ADDR + 0xD98)
    #define SHU1_PLL6_RG_RCLRPLL_BP Fld(1,31,AC_MSKB3)//[31:31]
    #define SHU1_PLL6_RG_RCLRPLL_BR Fld(1,30,AC_MSKB3)//[30:30]
    #define SHU1_PLL6_RG_RCLRPLL_BLP Fld(1,29,AC_MSKB3)//[29:29]
    #define SHU1_PLL6_RG_RCLRPLL_RESERVED Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_SHU1_PLL7 (DDRPHY_BASE_ADDR + 0xD9C)
    #define SHU1_PLL7_RG_RCLRPLL_SDM_PCW Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_PLL7_RG_RCLRPLL_SDM_PCW_CHG Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU1_PLL7_RG_RCLRPLL_SDM_FRA_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_SHU1_PLL8 (DDRPHY_BASE_ADDR + 0xDA0)
    #define SHU1_PLL8_RG_RPHYPLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define SHU1_PLL8_RG_RPHYPLL_POSDIV Fld(3,0,AC_MSKB0)//[2:0]
#define DDRPHY_SHU1_PLL9 (DDRPHY_BASE_ADDR + 0xDA4)
    #define SHU1_PLL9_RG_RPHYPLL_MONCK_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define SHU1_PLL9_RG_RPHYPLL_MONVC_EN Fld(2,14,AC_MSKB1)//[15:14]
    #define SHU1_PLL9_RG_RPHYPLL_MONREF_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define SHU1_PLL9_RG_RPHYPLL_LVROD_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU1_PLL9_RG_RPHYPLL_RST_DLY Fld(2,8,AC_MSKB1)//[9:8]
#define DDRPHY_SHU1_PLL10 (DDRPHY_BASE_ADDR + 0xDA8)
    #define SHU1_PLL10_RG_RCLRPLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define SHU1_PLL10_RG_RCLRPLL_POSDIV Fld(3,0,AC_MSKB0)//[2:0]
#define DDRPHY_SHU1_PLL11 (DDRPHY_BASE_ADDR + 0xDAC)
    #define SHU1_PLL11_RG_RCLRPLL_MONCK_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define SHU1_PLL11_RG_RCLRPLL_MONVC_EN Fld(2,14,AC_MSKB1)//[15:14]
    #define SHU1_PLL11_RG_RCLRPLL_MONREF_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define SHU1_PLL11_RG_RCLRPLL_LVROD_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU1_PLL11_RG_RCLRPLL_RST_DLY Fld(2,8,AC_MSKB1)//[9:8]
#define DDRPHY_SHU1_PLL12 (DDRPHY_BASE_ADDR + 0xDB0)
    #define SHU1_PLL12_RG_RPHYPLL_EXTFBDIV_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define SHU1_PLL12_RG_RCLRPLL_EXTFBDIV_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define SHU1_PLL12_RG_RCLRPLL_EXTPODIV_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU1_PLL12_RG_RCLRPLL_BYPASS Fld(1,6,AC_MSKB0)//[6:6]
#define DDRPHY_SHU1_PLL14 (DDRPHY_BASE_ADDR + 0xDB8)
    #define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_RPD Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU1_PLL14_RG_RPHYPLL_SDM_HREN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_SHU1_PLL15 (DDRPHY_BASE_ADDR + 0xDBC)
    #define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_SHU1_PLL20 (DDRPHY_BASE_ADDR + 0xDD0)
    #define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PRD Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT Fld(1,1,AC_MSKB0)//[1:1]
    #define SHU1_PLL20_RG_RCLRPLL_SDM_HREN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_SHU1_PLL21 (DDRPHY_BASE_ADDR + 0xDD4)
    #define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA Fld(16,0,AC_FULLW10)//[15:0]
////////////PLL END
///////////////////////// DDRPHY Registers ////////////////////////////////

//Page DDRPHY_1
#define DDRPHY_B0_DLL_ARPI0 (DDRPHY_BASE_ADDR + 0x080)
    #define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0 Fld(1,5,AC_MSKB0)//[5:5]
    #define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0 Fld(1,4,AC_MSKB0)//[4:4]
    #define B0_DLL_ARPI0_RG_ARPI_RESETB_B0 Fld(1,3,AC_MSKB0)//[3:3]
    #define B0_DLL_ARPI0_RG_ARDLL_PD_CK_SEL_B0 Fld(1,2,AC_MSKB0)//[2:2]
    #define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0 Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_DLL_ARPI0_RG_ARDLL_FASTPJ_CK_SEL_B0 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B0_DLL_ARPI1 (DDRPHY_BASE_ADDR + 0x084)
    #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0 Fld(1,21,AC_MSKB2)//[21:21]
    #define B0_DLL_ARPI1_RG_ARPI_MCTL_PISM_EN_B0 Fld(1,19,AC_MSKB2)//[19:19]
    #define B0_DLL_ARPI1_RG_ARPI_FB_PISM_EN_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DLL_ARPI1_RG_ARPI_DQS_PISM_EN_B0 Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DLL_ARPI1_RG_ARPI_DQM_PISM_EN_B0 Fld(1,14,AC_MSKB1)//[14:14]
    #define B0_DLL_ARPI1_RG_ARPI_DQ_PISM_EN_B0 Fld(1,13,AC_MSKB1)//[13:13]
    #define B0_DLL_ARPI1_RG_ARPI_DQSIEN_PISM_EN_B0 Fld(1,11,AC_MSKB1)//[11:11]
    #define B0_DLL_ARPI1_RG_ARPI_OFFSET_DQSIEN_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_B0_DLL_ARPI2 (DDRPHY_BASE_ADDR + 0x088)
    #define B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0 Fld(1,31,AC_MSKB3)//[31:31]
    #define B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0 Fld(1,27,AC_MSKB3)//[27:27]
    #define B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0 Fld(1,19,AC_MSKB2)//[19:19]
    #define B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0 Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0 Fld(1,14,AC_MSKB1)//[14:14]
    #define B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0 Fld(1,13,AC_MSKB1)//[13:13]
    #define B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0 Fld(1,11,AC_MSKB1)//[11:11]
    #define B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 Fld(1,10,AC_MSKB1)//[10:10]
#define DDRPHY_B0_DLL_ARPI3 (DDRPHY_BASE_ADDR + 0x08C)
    #define B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0 Fld(1,19,AC_MSKB2)//[19:19]
    #define B0_DLL_ARPI3_RG_ARPI_FB_EN_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0 Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 Fld(1,14,AC_MSKB1)//[14:14]
    #define B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 Fld(1,13,AC_MSKB1)//[13:13]
    #define B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 Fld(1,11,AC_MSKB1)//[11:11]
#define DDRPHY_B0_DLL_ARPI4 (DDRPHY_BASE_ADDR + 0x090)
    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0 Fld(1,19,AC_MSKB2)//[19:19]
    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0 Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0 Fld(1,14,AC_MSKB1)//[14:14]
    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0 Fld(1,13,AC_MSKB1)//[13:13]
    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0 Fld(1,11,AC_MSKB1)//[11:11]
//    #define B0_DLL_ARPI4_RG_ARPI_ONLINE_CAL_B01 Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_DLL_ARPI4_RG_ARPI_EXT_CAP_SEL_B01 Fld(1,1,AC_MSKB0)//[1:1]
//    #define B0_DLL_ARPI4_RG_ARPI_EXT_CAP_SEL_B01 Fld(1,0,AC_MSKB0)//[0:0]
	#define B0_DLL_ARPI4_RG_ARPI_ONLINE_CAL_B01 Fld(1,0,AC_MSKB0)//[0:0]

#define DDRPHY_B0_DLL_ARPI5 (DDRPHY_BASE_ADDR + 0x094)
    #define B0_DLL_ARPI5_RG_ARDLL_PHDET_OUT_SEL_B0 Fld(1,31,AC_MSKB3)//[31:31]
    #define B0_DLL_ARPI5_RG_ARDLL_PHDET_IN_SWAP_B0 Fld(1,30,AC_MSKB3)//[30:30]
    #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0 Fld(1,26,AC_MSKB3)//[26:26]
    #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 Fld(1,25,AC_MSKB3)//[25:25]
    #define B0_DLL_ARPI5_RG_ARDLL_GAIN_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define B0_DLL_ARPI5_RG_ARDLL_IDLECNT_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define B0_DLL_ARPI5_RG_ARDLL_P_GAIN_B0 Fld(4,12,AC_MSKB1)//[15:12]
    #define B0_DLL_ARPI5_RG_ARDLL_PHDET_EN_B0 Fld(1,11,AC_MSKB1)//[11:11]
    #define B0_DLL_ARPI5_RG_ARDLL_PHJUMP_EN_B0 Fld(1,10,AC_MSKB1)//[10:10]
    #define B0_DLL_ARPI5_RG_ARDLL_PHDIV_B0 Fld(1,9,AC_MSKB1)//[9:9]
    #define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0 Fld(5,4,AC_MSKW10)//[8:4]
    #define B0_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B0 Fld(2,2,AC_MSKB0)//[3:2]
    #define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0 Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_DLL_ARPI5_RG_ARDLL_FAST_PSPJ_B01 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B0_DQ0 (DDRPHY_BASE_ADDR + 0x098)
    #define B0_DQ0_RG_RX_ARDQ7_OFFC_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define B0_DQ0_RG_RX_ARDQ6_OFFC_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define B0_DQ0_RG_RX_ARDQ5_OFFC_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define B0_DQ0_RG_RX_ARDQ4_OFFC_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define B0_DQ0_RG_RX_ARDQ3_OFFC_B0 Fld(4,12,AC_MSKB1)//[15:12]
    #define B0_DQ0_RG_RX_ARDQ2_OFFC_B0 Fld(4,8,AC_MSKB1)//[11:8]
    #define B0_DQ0_RG_RX_ARDQ1_OFFC_B0 Fld(4,4,AC_MSKB0)//[7:4]
    #define B0_DQ0_RG_RX_ARDQ0_OFFC_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_B0_DQ1 (DDRPHY_BASE_ADDR + 0x09C)
    #define B0_DQ1_RG_RX_ARDQM0_OFFC_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_B0_DQ2 (DDRPHY_BASE_ADDR + 0x0A0)
    #define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 Fld(1,21,AC_MSKB2)//[21:21]
    #define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 Fld(1,20,AC_MSKB2)//[20:20]
    #define B0_DQ2_RG_TX_ARDQM0_OE_DIS Fld(1,19,AC_MSKB2)//[19:19]
    #define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS Fld(1,18,AC_MSKB2)//[18:18]
    #define B0_DQ2_RG_TX_ARDQS0_OE_DIS Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define B0_DQ2_RG_TX_ARDQS0_OE_EXT_DIS Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DQ2_RG_TX_ARDQS0_ODTEN_EXT_DIS Fld(1,14,AC_MSKB1)//[14:14]
#define DDRPHY_B0_DQ3 (DDRPHY_BASE_ADDR + 0x0A4)
    #define B0_DQ3_RG_RX_ARDQSIEN_DIV_EXT_EN_B01 Fld(1,16,AC_MSKB2)//[16:16]
    #define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0 Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0 Fld(1,11,AC_MSKB1)//[11:11]
    #define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 Fld(1,10,AC_MSKB1)//[10:10]
    #define B0_DQ3_RG_RX_ARDQS0_DQSIENMODE Fld(1,9,AC_MSKB1)//[9:9]
    #define B0_DQ3_RG_RX_ARDQS0_STBEN_RESETB Fld(1,8,AC_MSKB1)//[8:8]
    #define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0 Fld(1,7,AC_MSKB0)//[7:7]
    #define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0 Fld(1,5,AC_MSKB0)//[5:5]
    #define B0_DQ3_RG_RX_ARDQ_STBEN_RESETB_B0 Fld(1,4,AC_MSKB0)//[4:4]
    #define B0_DQ3_RG_ARDQ_RESETB_B0 Fld(1,3,AC_MSKB0)//[3:3]
    #define B0_DQ3_RG_TX_ARDQ_EN_B0 Fld(1,2,AC_MSKB0)//[2:2]
    #define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_DQ3_RG_ARDQ_ATPG_EN_B0 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B0_DQ4 (DDRPHY_BASE_ADDR + 0x0A8)
    #define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0 Fld(7,8,AC_MSKB1)//[14:8]
    #define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0 Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_B0_DQ5 (DDRPHY_BASE_ADDR + 0x0AC)
    #define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 Fld(1,31,AC_MSKB3)//[31:31]
    #define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0 Fld(1,25,AC_MSKB3)//[25:25]
    #define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0 Fld(1,24,AC_MSKB3)//[24:24]
    #define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 Fld(1,16,AC_MSKB2)//[16:16]
    #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_B0_DQ6 (DDRPHY_BASE_ADDR + 0x0B0)
    #define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0 Fld(1,31,AC_MSKB3)//[31:31]
    #define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0 Fld(1,28,AC_MSKB3)//[28:28]
    #define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0 Fld(1,24,AC_MSKB3)//[24:24]
    #define B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0 Fld(1,19,AC_MSKB2)//[19:19]
    #define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0 Fld(1,16,AC_MSKB2)//[16:16]
    #define B0_DQ6_RG_RX_ARDQ_BURST_EN_B0 Fld(2,14,AC_MSKB1)//[15:14]
    #define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0 Fld(1,12,AC_MSKB1)//[12:12]
    #define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0 Fld(1,11,AC_MSKB1)//[11:11]
    #define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0 Fld(1,9,AC_MSKB1)//[9:9]
    #define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0 Fld(1,8,AC_MSKB1)//[8:8]
    #define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0 Fld(1,7,AC_MSKB0)//[7:7]
    #define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0 Fld(1,6,AC_MSKB0)//[6:6]
    #define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0 Fld(1,5,AC_MSKB0)//[5:5]
    #define B0_DQ6_RG_TX_ARDQ_SER_MODE_B0 Fld(1,4,AC_MSKB0)//[4:4]
    #define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0 Fld(1,3,AC_MSKB0)//[3:3]
    #define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0 Fld(1,2,AC_MSKB0)//[2:2]
    #define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0 Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_B0_DQ7 (DDRPHY_BASE_ADDR + 0x0B4)
    #define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 Fld(1,7,AC_MSKB0)//[7:7]
    #define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 Fld(1,6,AC_MSKB0)//[6:6]
    #define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 Fld(1,5,AC_MSKB0)//[5:5]
    #define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 Fld(1,4,AC_MSKB0)//[4:4]
    #define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 Fld(1,3,AC_MSKB0)//[3:3]
    #define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 Fld(1,2,AC_MSKB0)//[2:2]
    #define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B0_DQ8 (DDRPHY_BASE_ADDR + 0x0B8)
    #define B0_DQ8_DA_RX_ARDQSIEN_RB_DLY_B0 Fld(1,31,AC_MSKB3)//[31:31]
    #define B0_DQ8_RG_ARDQM_PMX_SEL_B0 Fld(1,24,AC_MSKB3)//[24:24]
    #define B0_DQ8_RG_ARDQ_PMX_SEL_B0 Fld(8,16,AC_FULLB2)//[23:16]
    #define B0_DQ8_RG_RX_ARDQ_EYE_DQSI_SEL_B01 Fld(1,15,AC_MSKB1)//[15:15]
    #define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE Fld(1,14,AC_MSKB1)//[14:14]
    #define B0_DQ8_DA_RX_ARDQSIEN_RB_DLY_B01 Fld(1,13,AC_MSKB1)//[13:13]
    #define B0_DQ8_RG_TX_ARDQ_EN_DSRP Fld(1,2,AC_MSKB0)//[2:2]
    #define B0_DQ8_RG_TX_ARDQ_EN_DSRN Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B0_CKGEN_DLL0 (DDRPHY_BASE_ADDR + 0x0BC)
    #define B0_CKGEN_DLL0_RG_ARCKGEN_DLL_RESERVE_B01 Fld(8,24,AC_FULLB3)//[31:24]
    #define B0_CKGEN_DLL0_RG_ARCKGEN_DLL_OUT_SEL_B01 Fld(2,20,AC_MSKB2)//[21:20]
    #define B0_CKGEN_DLL0_RG_ARCKGEN_DLL_MON_SEL_B01 Fld(4,16,AC_MSKB2)//[19:16]
    #define B0_CKGEN_DLL0_RG_ARCKGEN_DLL_P_GAIN_B01 Fld(4,12,AC_MSKB1)//[15:12]
    #define B0_CKGEN_DLL0_RG_ARCKGEN_DLL_IDLECNT_B01 Fld(4,8,AC_MSKB1)//[11:8]
    #define B0_CKGEN_DLL0_RG_ARCKGEN_DLL_DELAY_CODE_B01 Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_B0_CKGEN_DLL1 (DDRPHY_BASE_ADDR + 0x0C0)
    #define B0_CKGEN_DLL1_RG_ARCKGEN_DLL_FAST_PSPJ_B01 Fld(1,3,AC_MSKB0)//[3:3]
    #define B0_CKGEN_DLL1_RG_ARCKGEN_DLL_PD_SEL_B01 Fld(1,2,AC_MSKB0)//[2:2]
    #define B0_CKGEN_DLL1_RG_ARCKGEN_DLL_EN_B01 Fld(1,1,AC_MSKB0)//[1:1]
    #define B0_CKGEN_DLL1_RG_ARCKGEN_DLL_PHJUMP_EN_B01 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B0_TX_MCK (DDRPHY_BASE_ADDR + 0x0D0)
    #define B0_TX_MCK_R_DM_TX_MCK_FRUN_B0 Fld(10,0,AC_MSKW10)//[9:0]
#define DDRPHY_B1_DLL_ARPI0 (DDRPHY_BASE_ADDR + 0x100)
    #define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1 Fld(1,5,AC_MSKB0)//[5:5]
    #define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1 Fld(1,4,AC_MSKB0)//[4:4]
    #define B1_DLL_ARPI0_RG_ARPI_RESETB_B1 Fld(1,3,AC_MSKB0)//[3:3]
    #define B1_DLL_ARPI0_RG_ARDLL_PD_CK_SEL_B1 Fld(1,2,AC_MSKB0)//[2:2]
    #define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1 Fld(1,1,AC_MSKB0)//[1:1]
    #define B1_DLL_ARPI0_RG_ARDLL_FASTPJ_CK_SEL_B1 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B1_DLL_ARPI1 (DDRPHY_BASE_ADDR + 0x104)
    #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1 Fld(1,21,AC_MSKB2)//[21:21]
    #define B1_DLL_ARPI1_RG_ARPI_MCTL_PISM_EN_B1 Fld(1,19,AC_MSKB2)//[19:19]
    #define B1_DLL_ARPI1_RG_ARPI_FB_PISM_EN_B1 Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DLL_ARPI1_RG_ARPI_DQS_PISM_EN_B1 Fld(1,15,AC_MSKB1)//[15:15]
    #define B1_DLL_ARPI1_RG_ARPI_DQM_PISM_EN_B1 Fld(1,14,AC_MSKB1)//[14:14]
    #define B1_DLL_ARPI1_RG_ARPI_DQ_PISM_EN_B1 Fld(1,13,AC_MSKB1)//[13:13]
    #define B1_DLL_ARPI1_RG_ARPI_DQSIEN_PISM_EN_B1 Fld(1,11,AC_MSKB1)//[11:11]
    #define B1_DLL_ARPI1_RG_ARPI_OFFSET_DQSIEN_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_B1_DLL_ARPI2 (DDRPHY_BASE_ADDR + 0x108)
    #define B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1 Fld(1,31,AC_MSKB3)//[31:31]
    #define B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1 Fld(1,27,AC_MSKB3)//[27:27]
    #define B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1 Fld(1,19,AC_MSKB2)//[19:19]
    #define B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1 Fld(1,15,AC_MSKB1)//[15:15]
    #define B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1 Fld(1,14,AC_MSKB1)//[14:14]
    #define B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1 Fld(1,13,AC_MSKB1)//[13:13]
    #define B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1 Fld(1,11,AC_MSKB1)//[11:11]
    #define B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 Fld(1,10,AC_MSKB1)//[10:10]
#define DDRPHY_B1_DLL_ARPI3 (DDRPHY_BASE_ADDR + 0x10C)
    #define B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 Fld(1,19,AC_MSKB2)//[19:19]
    #define B1_DLL_ARPI3_RG_ARPI_FB_EN_B1 Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1 Fld(1,15,AC_MSKB1)//[15:15]
    #define B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 Fld(1,14,AC_MSKB1)//[14:14]
    #define B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 Fld(1,13,AC_MSKB1)//[13:13]
    #define B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 Fld(1,11,AC_MSKB1)//[11:11]
#define DDRPHY_B1_DLL_ARPI4 (DDRPHY_BASE_ADDR + 0x110)
    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1 Fld(1,19,AC_MSKB2)//[19:19]
    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1 Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1 Fld(1,15,AC_MSKB1)//[15:15]
    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1 Fld(1,14,AC_MSKB1)//[14:14]
    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1 Fld(1,13,AC_MSKB1)//[13:13]
    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1 Fld(1,11,AC_MSKB1)//[11:11]
#define DDRPHY_B1_DLL_ARPI5 (DDRPHY_BASE_ADDR + 0x114)
    #define B1_DLL_ARPI5_RG_ARDLL_PHDET_OUT_SEL_B1 Fld(1,31,AC_MSKB3)//[31:31]
    #define B1_DLL_ARPI5_RG_ARDLL_PHDET_IN_SWAP_B1 Fld(1,30,AC_MSKB3)//[30:30]
    #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1 Fld(1,26,AC_MSKB3)//[26:26]
    #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 Fld(1,25,AC_MSKB3)//[25:25]
    #define B1_DLL_ARPI5_RG_ARDLL_GAIN_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define B1_DLL_ARPI5_RG_ARDLL_IDLECNT_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define B1_DLL_ARPI5_RG_ARDLL_P_GAIN_B1 Fld(4,12,AC_MSKB1)//[15:12]
    #define B1_DLL_ARPI5_RG_ARDLL_PHDET_EN_B1 Fld(1,11,AC_MSKB1)//[11:11]
    #define B1_DLL_ARPI5_RG_ARDLL_PHJUMP_EN_B1 Fld(1,10,AC_MSKB1)//[10:10]
    #define B1_DLL_ARPI5_RG_ARDLL_PHDIV_B1 Fld(1,9,AC_MSKB1)//[9:9]
    #define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1 Fld(1,8,AC_MSKB1)//[8:8]
    #define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1 Fld(4,4,AC_MSKB0)//[7:4]
    #define B1_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B1 Fld(2,2,AC_MSKB0)//[3:2]
#define DDRPHY_B1_DQ0 (DDRPHY_BASE_ADDR + 0x118)
    #define B1_DQ0_RG_RX_ARDQ7_OFFC_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define B1_DQ0_RG_RX_ARDQ6_OFFC_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define B1_DQ0_RG_RX_ARDQ5_OFFC_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define B1_DQ0_RG_RX_ARDQ4_OFFC_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define B1_DQ0_RG_RX_ARDQ3_OFFC_B1 Fld(4,12,AC_MSKB1)//[15:12]
    #define B1_DQ0_RG_RX_ARDQ2_OFFC_B1 Fld(4,8,AC_MSKB1)//[11:8]
    #define B1_DQ0_RG_RX_ARDQ1_OFFC_B1 Fld(4,4,AC_MSKB0)//[7:4]
    #define B1_DQ0_RG_RX_ARDQ0_OFFC_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_B1_DQ1 (DDRPHY_BASE_ADDR + 0x11C)
    #define B1_DQ1_RG_RX_ARDQM0_OFFC_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_B1_DQ2 (DDRPHY_BASE_ADDR + 0x120)
    #define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1 Fld(1,21,AC_MSKB2)//[21:21]
    #define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1 Fld(1,20,AC_MSKB2)//[20:20]
    #define B1_DQ2_RG_TX_ARDQM1_OE_DIS Fld(1,19,AC_MSKB2)//[19:19]
    #define B1_DQ2_RG_TX_ARDQM1_ODTEN_DIS Fld(1,18,AC_MSKB2)//[18:18]
    #define B1_DQ2_RG_TX_ARDQS1_OE_DIS Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DQ2_RG_TX_ARDQS1_ODTEN_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define B1_DQ2_RG_TX_ARDQS1_OE_EXT_DIS Fld(1,15,AC_MSKB1)//[15:15]
    #define B1_DQ2_RG_TX_ARDQS1_ODTEN_EXT_DIS Fld(1,14,AC_MSKB1)//[14:14]
#define DDRPHY_B1_DQ3 (DDRPHY_BASE_ADDR + 0x124)
    #define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1 Fld(1,15,AC_MSKB1)//[15:15]
    #define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1 Fld(1,11,AC_MSKB1)//[11:11]
    #define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 Fld(1,10,AC_MSKB1)//[10:10]
    #define B1_DQ3_RG_RX_ARDQS1_DQSIENMODE Fld(1,9,AC_MSKB1)//[9:9]
    #define B1_DQ3_RG_RX_ARDQS1_STBEN_RESETB Fld(1,8,AC_MSKB1)//[8:8]
    #define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1 Fld(1,7,AC_MSKB0)//[7:7]
    #define B1_DQ3_RG_RX_ARDQM1_IN_BUFF_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define B1_DQ3_RG_RX_ARDQS1_IN_BUFF_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define B1_DQ3_RG_RX_ARDQ_STBEN_RESETB_B1 Fld(1,4,AC_MSKB0)//[4:4]
    #define B1_DQ3_RG_ARDQ_RESETB_B1 Fld(1,3,AC_MSKB0)//[3:3]
    #define B1_DQ3_RG_TX_ARDQ_EN_B1 Fld(1,2,AC_MSKB0)//[2:2]
    #define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 Fld(1,1,AC_MSKB0)//[1:1]
    #define B1_DQ3_RG_ARDQ_ATPG_EN_B1 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B1_DQ4 (DDRPHY_BASE_ADDR + 0x128)
    #define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1 Fld(7,8,AC_MSKB1)//[14:8]
    #define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1 Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_B1_DQ5 (DDRPHY_BASE_ADDR + 0x12C)
    #define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 Fld(1,31,AC_MSKB3)//[31:31]
    #define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1 Fld(1,25,AC_MSKB3)//[25:25]
    #define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1 Fld(1,24,AC_MSKB3)//[24:24]
    #define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1 Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 Fld(1,16,AC_MSKB2)//[16:16]
    #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_B1_DQ6 (DDRPHY_BASE_ADDR + 0x130)
    #define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1 Fld(1,31,AC_MSKB3)//[31:31]
    #define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1 Fld(1,28,AC_MSKB3)//[28:28]
    #define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1 Fld(1,24,AC_MSKB3)//[24:24]
    #define B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 Fld(1,19,AC_MSKB2)//[19:19]
    #define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 Fld(1,17,AC_MSKB2)//[17:17]
    #define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1 Fld(1,16,AC_MSKB2)//[16:16]
    #define B1_DQ6_RG_RX_ARDQ_BURST_EN_B1 Fld(2,14,AC_MSKB1)//[15:14]
    #define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1 Fld(1,12,AC_MSKB1)//[12:12]
    #define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1 Fld(1,11,AC_MSKB1)//[11:11]
    #define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1 Fld(1,9,AC_MSKB1)//[9:9]
    #define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1 Fld(1,8,AC_MSKB1)//[8:8]
    #define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1 Fld(1,7,AC_MSKB0)//[7:7]
    #define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1 Fld(1,6,AC_MSKB0)//[6:6]
    #define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1 Fld(1,5,AC_MSKB0)//[5:5]
    #define B1_DQ6_RG_TX_ARDQ_SER_MODE_B1 Fld(1,4,AC_MSKB0)//[4:4]
    #define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1 Fld(1,3,AC_MSKB0)//[3:3]
    #define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1 Fld(1,2,AC_MSKB0)//[2:2]
    #define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B1_DQ7 (DDRPHY_BASE_ADDR + 0x134)
    #define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 Fld(1,7,AC_MSKB0)//[7:7]
    #define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 Fld(1,6,AC_MSKB0)//[6:6]
    #define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 Fld(1,5,AC_MSKB0)//[5:5]
    #define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 Fld(1,4,AC_MSKB0)//[4:4]
    #define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 Fld(1,3,AC_MSKB0)//[3:3]
    #define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 Fld(1,2,AC_MSKB0)//[2:2]
    #define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 Fld(1,1,AC_MSKB0)//[1:1]
    #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B1_DQ8 (DDRPHY_BASE_ADDR + 0x138)
    #define B1_DQ8_DA_RX_ARDQSIEN_RB_DLY_B1 Fld(1,31,AC_MSKB3)//[31:31]
    #define B1_DQ8_RG_ARDQM_PMX_SEL_B1 Fld(1,24,AC_MSKB3)//[24:24]
    #define B1_DQ8_RG_ARDQ_PMX_SEL_B1 Fld(8,16,AC_FULLB2)//[23:16]
    #define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_B1_TX_MCK (DDRPHY_BASE_ADDR + 0x150)
    #define B1_TX_MCK_R_DM_TX_MCK_FRUN_B1 Fld(10,0,AC_MSKW10)//[9:0]
#define DDRPHY_CA_DLL_ARPI0 (DDRPHY_BASE_ADDR + 0x180)
    #define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA Fld(1,6,AC_MSKB0)//[6:6]
    #define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA Fld(1,5,AC_MSKB0)//[5:5]
    #define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA Fld(1,4,AC_MSKB0)//[4:4]
    #define CA_DLL_ARPI0_RG_ARPI_RESETB_CA Fld(1,3,AC_MSKB0)//[3:3]
    #define CA_DLL_ARPI0_RG_ARDLL_PD_CK_SEL_CA Fld(1,2,AC_MSKB0)//[2:2]
    #define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA Fld(1,1,AC_MSKB0)//[1:1]
    #define CA_DLL_ARPI0_RG_ARDLL_FASTPJ_CK_SEL_CA Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_CA_DLL_ARPI1 (DDRPHY_BASE_ADDR + 0x184)
    #define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA Fld(3,28,AC_MSKB3)//[30:28]
    #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA Fld(1,21,AC_MSKB2)//[21:21]
    #define CA_DLL_ARPI1_RG_ARPI_MCTL_PISM_EN_CA Fld(1,19,AC_MSKB2)//[19:19]
    #define CA_DLL_ARPI1_RG_ARPI_FB_PISM_EN_CA Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_DLL_ARPI1_RG_ARPI_CS_PISM_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_DLL_ARPI1_RG_ARPI_CLK_PISM_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define CA_DLL_ARPI1_RG_ARPI_CMD_PISM_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define CA_DLL_ARPI1_RG_ARPI_CLKIEN_PISM_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define CA_DLL_ARPI1_RG_ARPI_OFFSET_CLKIEN Fld(6,0,AC_MSKB0)//[5:0]

//Page DDRPHY_2
#define DDRPHY_CA_DLL_ARPI2 (DDRPHY_BASE_ADDR + 0x188)
    #define CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA Fld(1,31,AC_MSKB3)//[31:31]
    #define CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA Fld(1,27,AC_MSKB3)//[27:27]
    #define CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA Fld(1,19,AC_MSKB2)//[19:19]
    #define CA_DLL_ARPI2_RG_ARRPI_CG_FB_CA Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_DLL_ARPI2_RG_ARPI_CG_CS Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_DLL_ARPI2_RG_ARPI_CG_CLK Fld(1,15,AC_MSKB1)//[15:15]
    #define CA_DLL_ARPI2_RG_ARPI_CG_CMD Fld(1,13,AC_MSKB1)//[13:13]
    #define CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN Fld(1,11,AC_MSKB1)//[11:11]
    #define CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA Fld(1,10,AC_MSKB1)//[10:10]
#define DDRPHY_CA_DLL_ARPI3 (DDRPHY_BASE_ADDR + 0x18C)
    #define CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA Fld(1,19,AC_MSKB2)//[19:19]
    #define CA_DLL_ARPI3_RG_ARPI_FB_EN_CA Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_DLL_ARPI3_RG_ARPI_CS_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_DLL_ARPI3_RG_ARPI_CLK_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define CA_DLL_ARPI3_RG_ARPI_CMD_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN Fld(1,11,AC_MSKB1)//[11:11]
#define DDRPHY_CA_DLL_ARPI4 (DDRPHY_BASE_ADDR + 0x190)
    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA Fld(1,19,AC_MSKB2)//[19:19]
    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK Fld(1,15,AC_MSKB1)//[15:15]
    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD Fld(1,13,AC_MSKB1)//[13:13]
    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN Fld(1,11,AC_MSKB1)//[11:11]
    #define CA_DLL_ARPI4_RG_ARPI_ONLINE_CAL_CA Fld(1,1,AC_MSKB0)//[1:1]
    #define CA_DLL_ARPI4_RG_ARPI_EXT_CAP_SEL_CA Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_CA_DLL_ARPI5 (DDRPHY_BASE_ADDR + 0x194)
    #define CA_DLL_ARPI5_RG_ARDLL_PHDET_OUT_SEL_CA Fld(1,31,AC_MSKB3)//[31:31]
    #define CA_DLL_ARPI5_RG_ARDLL_PHDET_IN_SWAP_CA Fld(1,30,AC_MSKB3)//[30:30]
    #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA Fld(1,26,AC_MSKB3)//[26:26]
    #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA Fld(1,25,AC_MSKB3)//[25:25]
    #define CA_DLL_ARPI5_RG_ARDLL_GAIN_CA Fld(4,20,AC_MSKB2)//[23:20]
    #define CA_DLL_ARPI5_RG_ARDLL_IDLECNT_CA Fld(4,16,AC_MSKB2)//[19:16]
    #define CA_DLL_ARPI5_RG_ARDLL_P_GAIN_CA Fld(4,12,AC_MSKB1)//[15:12]
    #define CA_DLL_ARPI5_RG_ARDLL_PHDET_EN_CA Fld(1,11,AC_MSKB1)//[11:11]
    #define CA_DLL_ARPI5_RG_ARDLL_PHJUMP_EN_CA Fld(1,10,AC_MSKB1)//[10:10]
    #define CA_DLL_ARPI5_RG_ARDLL_PHDIV_CA Fld(1,9,AC_MSKB1)//[9:9]
    #define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA Fld(5,4,AC_MSKW10)//[8:4]
    #define CA_DLL_ARPI5_RG_ARDLL_DIV_MCTL_CA Fld(2,2,AC_MSKB0)//[3:2]
    #define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA Fld(1,1,AC_MSKB0)//[1:1]
    #define CA_DLL_ARPI5_RG_ARDLL_FAST_PSPJ_CA Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_CA_CMD0 (DDRPHY_BASE_ADDR + 0x198)
    #define CA_CMD0_RG_RX_ARCA5_OFFC Fld(4,20,AC_MSKB2)//[23:20]
    #define CA_CMD0_RG_RX_ARCA4_OFFC Fld(4,16,AC_MSKB2)//[19:16]
    #define CA_CMD0_RG_RX_ARCA3_OFFC Fld(4,12,AC_MSKB1)//[15:12]
    #define CA_CMD0_RG_RX_ARCA2_OFFC Fld(4,8,AC_MSKB1)//[11:8]
    #define CA_CMD0_RG_RX_ARCA1_OFFC Fld(4,4,AC_MSKB0)//[7:4]
    #define CA_CMD0_RG_RX_ARCA0_OFFC Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_CA_CMD1 (DDRPHY_BASE_ADDR + 0x19C)
    #define CA_CMD1_RG_RX_ARCKE2_OFFC Fld(4,20,AC_MSKB2)//[23:20]
    #define CA_CMD1_RG_RX_ARCKE1_OFFC Fld(4,16,AC_MSKB2)//[19:16]
    #define CA_CMD1_RG_RX_ARCKE0_OFFC Fld(4,12,AC_MSKB1)//[15:12]
    #define CA_CMD1_RG_RX_ARCS2_OFFC Fld(4,8,AC_MSKB1)//[11:8]
    #define CA_CMD1_RG_RX_ARCS1_OFFC Fld(4,4,AC_MSKB0)//[7:4]
    #define CA_CMD1_RG_RX_ARCS0_OFFC Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_CA_CMD2 (DDRPHY_BASE_ADDR + 0x1A0)
    #define CA_CMD2_RG_TX_ARCMD_OE_DIS Fld(1,21,AC_MSKB2)//[21:21]
    #define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS Fld(1,20,AC_MSKB2)//[20:20]
    #define CA_CMD2_RG_TX_ARCLK_OE_EXT_DIS Fld(1,18,AC_MSKB2)//[18:18]
    #define CA_CMD2_RG_TX_ARCLK_OE_DIS Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS Fld(1,16,AC_MSKB2)//[16:16]
#define DDRPHY_CA_CMD3 (DDRPHY_BASE_ADDR + 0x1A4)
    #define CA_CMD3_RG_RX_ARDQSIEN_DIV_EXT_EN_CA Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_CMD3_RG_RX_ARCLK_SWAP_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define CA_CMD3_RG_RX_ARCLK_DQSIENMODE Fld(1,9,AC_MSKB1)//[9:9]
    #define CA_CMD3_RG_RX_ARCLK_STBEN_RESETB Fld(1,8,AC_MSKB1)//[8:8]
    #define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define CA_CMD3_RG_RX_ARCMD_STBEN_RESETB Fld(1,4,AC_MSKB0)//[4:4]
    #define CA_CMD3_RG_ARCMD_RESETB Fld(1,3,AC_MSKB0)//[3:3]
    #define CA_CMD3_RG_TX_ARCMD_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define CA_CMD3_RG_RX_ARCMD_SMT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define CA_CMD3_RG_ARCMD_ATPG_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_CA_CMD4 (DDRPHY_BASE_ADDR + 0x1A8)
    #define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY Fld(7,8,AC_MSKB1)//[14:8]
    #define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_CA_CMD5 (DDRPHY_BASE_ADDR + 0x1AC)
    #define CA_CMD5_RG_RX_ARCLK_DVS_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB Fld(1,25,AC_MSKB3)//[25:25]
    #define CA_CMD5_RG_RX_ARCMD_EYE_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define CA_CMD5_RG_RX_ARCMD_EYE_SEL Fld(4,20,AC_MSKB2)//[23:20]
    #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_CMD5_RG_RX_ARCMD_VREF_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_CA_CMD6 (DDRPHY_BASE_ADDR + 0x1B0)
    #define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL Fld(1,31,AC_MSKB3)//[31:31]
    #define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS Fld(1,24,AC_MSKB3)//[24:24]
    #define CA_CMD6_RG_TX_ARCMD_LP4_SEL Fld(1,19,AC_MSKB2)//[19:19]
    #define CA_CMD6_RG_TX_ARCMD_DDR4_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_CMD6_RG_RX_ARCMD_BURST_EN Fld(2,14,AC_MSKB1)//[15:14]
    #define CA_CMD6_RG_RX_ARCMD_BIAS_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define CA_CMD6_RG_RX_ARCMD_JM_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define CA_CMD6_RG_RX_ARCMD_O1_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define CA_CMD6_RG_RX_ARCMD_LPBK_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define CA_CMD6_RG_TX_ARCMD_SER_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS Fld(1,3,AC_MSKB0)//[3:3]
    #define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS Fld(1,2,AC_MSKB0)//[2:2]
    #define CA_CMD6_RG_RX_ARCMD_BIAS_PS Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_CA_CMD7 (DDRPHY_BASE_ADDR + 0x1B4)
    #define CA_CMD7_RG_TX_ARCMD_PULL_UP Fld(1,7,AC_MSKB0)//[7:7]
    #define CA_CMD7_RG_TX_ARCMD_PULL_DN Fld(1,6,AC_MSKB0)//[6:6]
    #define CA_CMD7_RG_TX_ARCS_PULL_UP Fld(1,5,AC_MSKB0)//[5:5]
    #define CA_CMD7_RG_TX_ARCS_PULL_DN Fld(1,4,AC_MSKB0)//[4:4]
    #define CA_CMD7_RG_TX_ARCLK_PULL_UP Fld(1,3,AC_MSKB0)//[3:3]
    #define CA_CMD7_RG_TX_ARCLK_PULL_DN Fld(1,2,AC_MSKB0)//[2:2]
    #define CA_CMD7_RG_TX_ARCLKB_PULL_UP Fld(1,1,AC_MSKB0)//[1:1]
    #define CA_CMD7_RG_TX_ARCLKB_PULL_DN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_CA_CMD8 (DDRPHY_BASE_ADDR + 0x1B8)
    #define CA_CMD8_RG_TX_ARCMD_EN_DSRP Fld(1,31,AC_MSKB3)//[31:31]
    #define CA_CMD8_RG_TX_ARCMD_EN_DSRN Fld(1,30,AC_MSKB3)//[30:30]
    #define CA_CMD8_RG_TX_ARCMD_EN_LP4P Fld(1,29,AC_MSKB3)//[29:29]
    #define CA_CMD8_RG_TX_ARESETB_PULL_UP Fld(1,21,AC_MSKB2)//[21:21]
    #define CA_CMD8_RG_TX_ARESETB_PULL_DN Fld(1,20,AC_MSKB2)//[20:20]
    #define CA_CMD8_RG_TX_RRESETB_DDR3_SEL Fld(1,19,AC_MSKB2)//[19:19]
    #define CA_CMD8_RG_TX_RRESETB_DDR4_SEL Fld(1,18,AC_MSKB2)//[18:18]
    #define CA_CMD8_RG_TX_RRESETB_SCAN_IN_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define CA_CMD8_RG_RX_RRESETB_SMT_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define CA_CMD8_RG_RRESETB_DRVN Fld(5,8,AC_MSKB1)//[12:8]
    #define CA_CMD8_RG_RRESETB_DRVP Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_CA_CKGEN_DLL0 (DDRPHY_BASE_ADDR + 0x1BC)
    #define CA_CKGEN_DLL0_RG_ARCKGEN_DLL_RESERVE_CA Fld(8,24,AC_FULLB3)//[31:24]
    #define CA_CKGEN_DLL0_RG_ARCKGEN_DLL_OUT_SEL_CA Fld(2,20,AC_MSKB2)//[21:20]
    #define CA_CKGEN_DLL0_RG_ARCKGEN_DLL_MON_SEL_CA Fld(4,16,AC_MSKB2)//[19:16]
    #define CA_CKGEN_DLL0_RG_ARCKGEN_DLL_P_GAIN_CA Fld(4,12,AC_MSKB1)//[15:12]
    #define CA_CKGEN_DLL0_RG_ARCKGEN_DLL_IDLECNT_CA Fld(4,8,AC_MSKB1)//[11:8]
    #define CA_CKGEN_DLL0_RG_ARCKGEN_DLL_DELAY_CODE_CA Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_CA_CKGEN_DLL1 (DDRPHY_BASE_ADDR + 0x1C0)
    #define CA_CKGEN_DLL1_RG_ARCKGEN_DLL_FAST_PSPJ_CA Fld(1,3,AC_MSKB0)//[3:3]
    #define CA_CKGEN_DLL1_RG_ARCKGEN_DLL_PD_SEL_CA Fld(1,2,AC_MSKB0)//[2:2]
    #define CA_CKGEN_DLL1_RG_ARCKGEN_DLL_EN_CA Fld(1,1,AC_MSKB0)//[1:1]
    #define CA_CKGEN_DLL1_RG_ARCKGEN_DLL_PHJUMP_EN_CA Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_CA_TX_MCK (DDRPHY_BASE_ADDR + 0x1D0)
    #define CA_TX_MCK_R_DM_TX_MCK_FRUN_CA Fld(13,0,AC_MSKW10)//[12:0]
#define DDRPHY_MISC_EXTLB0 (DDRPHY_BASE_ADDR + 0x200)
    #define MISC_EXTLB0_STBERR_RK0_R Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB0_STBERR_RK0_F Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB1 (DDRPHY_BASE_ADDR + 0x204)
    #define MISC_EXTLB1_R_EXTLB_LFSR_INI_2 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB1_R_EXTLB_LFSR_INI_3 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB2 (DDRPHY_BASE_ADDR + 0x208)
    #define MISC_EXTLB2_R_EXTLB_LFSR_INI_4 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB2_R_EXTLB_LFSR_INI_5 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB3 (DDRPHY_BASE_ADDR + 0x20C)
    #define MISC_EXTLB3_R_EXTLB_LFSR_INI_6 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB3_R_EXTLB_LFSR_INI_7 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB4 (DDRPHY_BASE_ADDR + 0x210)
    #define MISC_EXTLB4_R_EXTLB_LFSR_INI_8 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB4_R_EXTLB_LFSR_INI_9 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB5 (DDRPHY_BASE_ADDR + 0x214)
    #define MISC_EXTLB5_R_EXTLB_LFSR_INI_10 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB5_R_EXTLB_LFSR_INI_11 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB6 (DDRPHY_BASE_ADDR + 0x218)
    #define MISC_EXTLB6_R_EXTLB_LFSR_INI_12 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB6_R_EXTLB_LFSR_INI_13 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB7 (DDRPHY_BASE_ADDR + 0x21C)
    #define MISC_EXTLB7_R_EXTLB_LFSR_INI_14 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB7_R_EXTLB_LFSR_INI_15 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB8 (DDRPHY_BASE_ADDR + 0x220)
    #define MISC_EXTLB8_R_EXTLB_LFSR_INI_16 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB8_R_EXTLB_LFSR_INI_17 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB9 (DDRPHY_BASE_ADDR + 0x224)
    #define MISC_EXTLB9_R_EXTLB_LFSR_INI_18 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB9_R_EXTLB_LFSR_INI_19 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB10 (DDRPHY_BASE_ADDR + 0x228)
    #define MISC_EXTLB10_R_EXTLB_LFSR_INI_20 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB10_R_EXTLB_LFSR_INI_21 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB11 (DDRPHY_BASE_ADDR + 0x22C)
    #define MISC_EXTLB11_R_EXTLB_LFSR_INI_22 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB11_R_EXTLB_LFSR_INI_23 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB12 (DDRPHY_BASE_ADDR + 0x230)
    #define MISC_EXTLB12_R_EXTLB_LFSR_INI_24 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB12_R_EXTLB_LFSR_INI_25 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB13 (DDRPHY_BASE_ADDR + 0x234)
    #define MISC_EXTLB13_R_EXTLB_LFSR_INI_26 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB13_R_EXTLB_LFSR_INI_27 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB14 (DDRPHY_BASE_ADDR + 0x238)
    #define MISC_EXTLB14_R_EXTLB_LFSR_INI_28 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB14_R_EXTLB_LFSR_INI_29 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB15 (DDRPHY_BASE_ADDR + 0x23C)
    #define MISC_EXTLB15_R_EXTLB_LFSR_INI_30 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB15_R_EXTLB_LFSR_INI_31 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB16 (DDRPHY_BASE_ADDR + 0x240)
    #define MISC_EXTLB16_R_EXTLB_LFSR_INI_32 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB16_R_EXTLB_LFSR_INI_33 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB17 (DDRPHY_BASE_ADDR + 0x244)
    #define MISC_EXTLB17_R_EXTLB_LFSR_INI_34 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB17_R_EXTLB_LFSR_INI_35 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB18 (DDRPHY_BASE_ADDR + 0x248)
    #define MISC_EXTLB18_R_EXTLB_LFSR_INI_36 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB18_R_EXTLB_LFSR_INI_37 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB19 (DDRPHY_BASE_ADDR + 0x24C)
    #define MISC_EXTLB19_R_EXTLB_LFSR_INI_38 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB19_R_EXTLB_LFSR_INI_39 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB20 (DDRPHY_BASE_ADDR + 0x250)
    #define MISC_EXTLB20_R_EXTLB_LFSR_INI_40 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB20_R_EXTLB_LFSR_INI_41 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB21 (DDRPHY_BASE_ADDR + 0x254)
    #define MISC_EXTLB21_R_EXTLB_LFSR_INI_42 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_EXTLB22 (DDRPHY_BASE_ADDR + 0x258)
    #define MISC_EXTLB22_R_XTALK_07_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB22_R_XTALK_06_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB22_R_XTALK_05_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB22_R_XTALK_04_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB22_R_XTALK_03_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB22_R_XTALK_02_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB22_R_XTALK_01_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB22_R_XTALK_00_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB23 (DDRPHY_BASE_ADDR + 0x25C)
    #define MISC_EXTLB23_R_XTALK_15_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB23_R_XTALK_14_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB23_R_XTALK_13_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB23_R_XTALK_12_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB23_R_XTALK_11_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB23_R_XTALK_10_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB23_R_XTALK_09_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB23_R_XTALK_08_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB24 (DDRPHY_BASE_ADDR + 0x260)
    #define MISC_EXTLB24_R_XTALK_23_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB24_R_XTALK_22_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB24_R_XTALK_21_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB24_R_XTALK_20_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB24_R_XTALK_19_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB24_R_XTALK_18_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB24_R_XTALK_17_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB24_R_XTALK_16_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB25 (DDRPHY_BASE_ADDR + 0x264)
    #define MISC_EXTLB25_R_XTALK_31_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB25_R_XTALK_30_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB25_R_XTALK_29_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB25_R_XTALK_28_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB25_R_XTALK_27_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB25_R_XTALK_26_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB25_R_XTALK_25_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB25_R_XTALK_24_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB26 (DDRPHY_BASE_ADDR + 0x268)
    #define MISC_EXTLB26_R_XTALK_39_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB26_R_XTALK_38_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB26_R_XTALK_37_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB26_R_XTALK_36_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB26_R_XTALK_35_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB26_R_XTALK_34_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB26_R_XTALK_33_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB26_R_XTALK_32_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB27 (DDRPHY_BASE_ADDR + 0x26C)
    #define MISC_EXTLB27_R_XTALK_42_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB27_R_XTALK_41_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB27_R_XTALK_40_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB28 (DDRPHY_BASE_ADDR + 0x270)
    #define MISC_EXTLB28_R_EXTLB_LFSR_TAP Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB28_R_EXTLB_OE_DQB0_ON Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_EXTLB28_R_EXTLB_OE_DQM0_ON Fld(1,17,AC_MSKB2)//[17:17]
    #define MISC_EXTLB28_R_EXTLB_OE_DQS0_ON Fld(1,18,AC_MSKB2)//[18:18]
    #define MISC_EXTLB28_R_EXTLB_OE_DQB1_ON Fld(1,19,AC_MSKB2)//[19:19]
    #define MISC_EXTLB28_R_EXTLB_OE_DQM1_ON Fld(1,20,AC_MSKB2)//[20:20]
    #define MISC_EXTLB28_R_EXTLB_OE_DQS1_ON Fld(1,21,AC_MSKB2)//[21:21]
    #define MISC_EXTLB28_R_EXTLB_ODTEN_DQB0_ON Fld(1,22,AC_MSKB2)//[22:22]
    #define MISC_EXTLB28_R_EXTLB_ODTEN_DQM0_ON Fld(1,23,AC_MSKB2)//[23:23]
    #define MISC_EXTLB28_R_EXTLB_ODTEN_DQS0_ON Fld(1,24,AC_MSKB3)//[24:24]
    #define MISC_EXTLB28_R_EXTLB_ODTEN_DQB1_ON Fld(1,25,AC_MSKB3)//[25:25]
    #define MISC_EXTLB28_R_EXTLB_ODTEN_DQM1_ON Fld(1,26,AC_MSKB3)//[26:26]
    #define MISC_EXTLB28_R_EXTLB_ODTEN_DQS1_ON Fld(1,27,AC_MSKB3)//[27:27]
#define DDRPHY_MISC_EXTLB29 (DDRPHY_BASE_ADDR + 0x274)
    #define MISC_EXTLB29_R_EXTLB Fld(1,0,AC_MSKB0)//[0:0]
    #define MISC_EXTLB29_R_EXTLB_RX_SWRST Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_EXTLB29_R_EXTLB_TX_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_EXTLB29_R_EXTLB_TX_EN_OTHERCH_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define MISC_EXTLB29_R_INTLB_ARCLK_MUXSEL Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_EXTLB29_R_INTLB_DRDF_CA_MUXSEL Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_EXTLB29_R_EXTLB_TX_PRE_ON Fld(1,7,AC_MSKB0)//[7:7]
    #define MISC_EXTLB29_R_EXTLB_RX_LENGTH_M1 Fld(24,8,AC_MSKDW)//[31:8]
#define DDRPHY_MISC_EXTLB30 (DDRPHY_BASE_ADDR + 0x278)
    #define MISC_EXTLB30_R_OTH_TX_TRIG_SRC_SEL Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB30_R_TX_TRIG_SRC_SEL Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB30_R_LPBK_CA_RX_MODE Fld(1,9,AC_MSKB1)//[9:9]
    #define MISC_EXTLB30_R_LPBK_DQ_RX_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_EXTLB30_R_LPBK_CA_TX_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_EXTLB30_R_LPBK_DQ_TX_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_EXTLB30_R_OTH_TX_EN_SRC_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_EXTLB30_R_TX_EN_SRC_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_EXTLB31 (DDRPHY_BASE_ADDR + 0x27C)
    #define MISC_EXTLB31_R_EXTLB_DBG_SEL Fld(5,16,AC_MSKB2)//[20:16]
    #define MISC_EXTLB31_R_EXTLB_XTALK_ENABLE Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_EXTLB31_R_EXTLB_SSO_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_EXTLB31_R_EXTLB_LFSR_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_VREF_CTRL (DDRPHY_BASE_ADDR + 0x290)
    #define MISC_VREF_CTRL_RG_RVREF_VREF_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define MISC_VREF_CTRL_RG_RVREF_SEL_CMD Fld(6,24,AC_MSKB3)//[29:24]
    #define MISC_VREF_CTRL_RG_RVREF_LP4_SEL Fld(1,23,AC_MSKB2)//[23:23]
    #define MISC_VREF_CTRL_RG_RVREF_DDR4_SEL Fld(1,22,AC_MSKB2)//[22:22]
    #define MISC_VREF_CTRL_RG_RVREF_SEL_DQ Fld(6,16,AC_MSKB2)//[21:16]
#define DDRPHY_MISC_IMP_CTRL0 (DDRPHY_BASE_ADDR + 0x294)
    #define MISC_IMP_CTRL0_RG_RIMP_VREF_SEL Fld(6,16,AC_MSKB2)//[21:16]
    #define MISC_IMP_CTRL0_RG_RIMP_LP4_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_IMP_CTRL0_RG_RIMP_DDR4_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_IMP_CTRL0_RG_IMP_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_IMP_CTRL0_RG_IMP_OCD_PUCMP_EN Fld(1,3,AC_MSKB0)//[3:3]
#define DDRPHY_MISC_IMP_CTRL1 (DDRPHY_BASE_ADDR + 0x298)
    #define MISC_IMP_CTRL1_RG_RIMP_DRVN Fld(5,24,AC_MSKB3)//[28:24]
    #define MISC_IMP_CTRL1_RG_RIMP_DRVP Fld(5,16,AC_MSKB2)//[20:16]
    #define MISC_IMP_CTRL1_RG_RIMP_REV Fld(8,8,AC_FULLB1)//[15:8]
    #define MISC_IMP_CTRL1_RG_RIMP_REV_1 Fld(1,9,AC_FULLB1)//[9:9]
    #define MISC_IMP_CTRL1_RG_RIMP_REV_0 Fld(1,8,AC_FULLB1)//[8:8]    
    #define MISC_IMP_CTRL1_RG_RIMP_VREF_EN Fld(1,7,AC_MSKB0)//[7:7]
    #define MISC_IMP_CTRL1_RG_RIMP_PRE_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_IMP_CTRL1_RG_RIMP_ODT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN Fld(1,4,AC_MSKB0)//[4:4]

//Page DDRPHY_3
#define DDRPHY_MISC_SHU_OPT (DDRPHY_BASE_ADDR + 0x29C)
    #define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN Fld(2,18,AC_MSKB2)//[19:18]
    #define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN Fld(2,10,AC_MSKB1)//[11:10]
    #define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN Fld(2,2,AC_MSKB0)//[3:2]
    #define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_SPM_CTRL0 (DDRPHY_BASE_ADDR + 0x2A0)
    #define MISC_SPM_CTRL0_PHY_SPM_CTL0 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_SPM_CTRL1 (DDRPHY_BASE_ADDR + 0x2A4)
    #define MISC_SPM_CTRL1_PHY_SPM_CTL1 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_SPM_CTRL2 (DDRPHY_BASE_ADDR + 0x2A8)
    #define MISC_SPM_CTRL2_PHY_SPM_CTL2 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_SPM_CTRL3 (DDRPHY_BASE_ADDR + 0x2AC)
    #define MISC_SPM_CTRL3_PHY_SPM_CTL3 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CG_CTRL0 (DDRPHY_BASE_ADDR + 0x2B0)
    #define MISC_CG_CTRL0_CLK_MEM_DFS_CFG Fld(32,0,AC_FULLDW)//[31:0]
    #define MISC_CG_CTRL0_CLK_MEM_FREERUN Fld(12,8,AC_MSKW21)//[19:8]
#define DDRPHY_MISC_CG_CTRL1 (DDRPHY_BASE_ADDR + 0x2B4)
    #define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CG_CTRL2 (DDRPHY_BASE_ADDR + 0x2B8)
    #define MISC_CG_CTRL2_RG_MEM_DCM_CTL Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CG_CTRL3 (DDRPHY_BASE_ADDR + 0x2BC)
    #define MISC_CG_CTRL3_R_LBK_CG_CTRL Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CG_CTRL4 (DDRPHY_BASE_ADDR + 0x2C0)
    #define MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CG_CTRL5 (DDRPHY_BASE_ADDR + 0x2C4)
    #define MISC_CG_CTRL5_PHY_CG_CTRL_TMP Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CTRL0 (DDRPHY_BASE_ADDR + 0x2C8)
    #define MISC_CTRL0_R_STBENCMP_DIV4CK_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL Fld(1,30,AC_MSKB3)//[30:30]
    #define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL Fld(1,29,AC_MSKB3)//[29:29]
    #define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL Fld(1,28,AC_MSKB3)//[28:28]
    #define MISC_CTRL0_R_DMSTBENCMP_RK_FIFO_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define MISC_CTRL0_R_DMSTBENCMP_FIFO_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define MISC_CTRL0_R_DMDQSIEN_FIFO_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define MISC_CTRL0_R_DMDQSIEN_VALID_LAT Fld(3,21,AC_MSKB2)//[23:21]
    #define MISC_CTRL0_R_DMDQSIEN_RDSEL_LAT Fld(3,18,AC_MSKB2)//[20:18]
    #define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_CTRL0_R_DMVALID_DLY Fld(3,13,AC_MSKB1)//[15:13]
    #define MISC_CTRL0_R_DMVALID_NARROW_IG Fld(1,12,AC_MSKB1)//[12:12]
    #define MISC_CTRL0_R_DMVALID_DLY_OPT Fld(1,11,AC_MSKB1)//[11:11]
    #define MISC_CTRL0_R_DMSTBEN_OUTSEL Fld(1,9,AC_MSKB1)//[9:9]
    #define MISC_CTRL0_R_DMSTBEN_SYNCOPT Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_CTRL0_R_DMDQSIEN_OUTSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_CTRL0_R_DMDQSIEN_SYNCOPT Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_CTRL1 (DDRPHY_BASE_ADDR + 0x2CC)
    #define MISC_CTRL1_R_DMDA_RRESETB_E Fld(1,31,AC_MSKB3)//[31:31]
    #define MISC_CTRL1_R_HWSAVE_MODE_ENA Fld(1,30,AC_MSKB3)//[30:30]
    #define MISC_CTRL1_R_DMODTDISOE_C Fld(1,29,AC_MSKB3)//[29:29]
    #define MISC_CTRL1_R_DMODTDISOE_B Fld(1,28,AC_MSKB3)//[28:28]
    #define MISC_CTRL1_R_DMODTDISOE_A Fld(1,27,AC_MSKB3)//[27:27]
    #define MISC_CTRL1_R_WL_DOWNSP Fld(1,26,AC_MSKB3)//[26:26]
    #define MISC_CTRL1_R_DMSTBENCMP_RK_OPT Fld(1,25,AC_MSKB3)//[25:25]
    #define MISC_CTRL1_R_DMDQSIENCG_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define MISC_CTRL1_R_DMDRAMCLKEN1 Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_CTRL1_R_DMDRAMCLKEN0 Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_CTRL1_R_DMMUXCA_SEC Fld(1,14,AC_MSKB1)//[14:14]
    #define MISC_CTRL1_R_DMMUXBYTE1_SEC Fld(1,13,AC_MSKB1)//[13:13]
    #define MISC_CTRL1_R_DMMUXBYTE0_SEC Fld(1,12,AC_MSKB1)//[12:12]
    #define MISC_CTRL1_CK_BFE_DCM_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define MISC_CTRL1_R_DMPINMUX Fld(2,8,AC_MSKB1)//[9:8]
    #define MISC_CTRL1_R_DMARPIDQ_SW Fld(1,7,AC_MSKB0)//[7:7]
    #define MISC_CTRL1_R_DMMUXCA Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_CTRL1_R_DMMCTLPLL_CKSEL Fld(2,4,AC_MSKB0)//[5:4]
    #define MISC_CTRL1_R_DM_TX_ARCMD_OE Fld(1,3,AC_MSKB0)//[3:3]
    #define MISC_CTRL1_R_DM_TX_ARCLK_OE Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_CTRL1_R_DMPHYRST Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_CTRL1_R_DMDQMDBI Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_CTRL2 (DDRPHY_BASE_ADDR + 0x2D0)
    #define MISC_CTRL2_PLL_SHU_GP Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_MISC_CTRL3 (DDRPHY_BASE_ADDR + 0x2D4)
    #define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL Fld(2,24,AC_MSKB3)//[25:24]
    #define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT Fld(1,22,AC_MSKB2)//[22:22]
    #define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT Fld(1,21,AC_MSKB2)//[21:21]
    #define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT Fld(1,20,AC_MSKB2)//[20:20]
    #define MISC_CTRL3_ARPI_CG_DQS_OPT Fld(2,18,AC_MSKB2)//[19:18]
    #define MISC_CTRL3_ARPI_CG_DQ_OPT Fld(2,16,AC_MSKB2)//[17:16]
    #define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_CTRL3_ARPI_CG_MCK_CA_OPT Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_CTRL3_ARPI_CG_CLK_OPT Fld(2,2,AC_MSKB0)//[3:2]
    #define MISC_CTRL3_ARPI_CG_CMD_OPT Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_MISC_CTRL4 (DDRPHY_BASE_ADDR + 0x2D8)
    #define MISC_CTRL4_RG_PW_CON_CHA_0 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CTRL5 (DDRPHY_BASE_ADDR + 0x2DC)
    #define MISC_CTRL5_RG_PW_CON_CHA_1 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_EXTLB_RX0 (DDRPHY_BASE_ADDR + 0x300)
    #define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_0 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_1 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX1 (DDRPHY_BASE_ADDR + 0x304)
    #define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_2 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_3 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX2 (DDRPHY_BASE_ADDR + 0x308)
    #define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_4 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_5 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX3 (DDRPHY_BASE_ADDR + 0x30C)
    #define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_6 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_7 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX4 (DDRPHY_BASE_ADDR + 0x310)
    #define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_8 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_9 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX5 (DDRPHY_BASE_ADDR + 0x314)
    #define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_10 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_11 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX6 (DDRPHY_BASE_ADDR + 0x318)
    #define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_12 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_13 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX7 (DDRPHY_BASE_ADDR + 0x31C)
    #define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_14 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_15 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX8 (DDRPHY_BASE_ADDR + 0x320)
    #define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_16 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_17 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX9 (DDRPHY_BASE_ADDR + 0x324)
    #define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_18 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_19 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX10 (DDRPHY_BASE_ADDR + 0x328)
    #define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_20 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_21 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX11 (DDRPHY_BASE_ADDR + 0x32C)
    #define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_22 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_23 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX12 (DDRPHY_BASE_ADDR + 0x330)
    #define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_24 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_25 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX13 (DDRPHY_BASE_ADDR + 0x334)
    #define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_26 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_27 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX14 (DDRPHY_BASE_ADDR + 0x338)
    #define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_28 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_29 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX15 (DDRPHY_BASE_ADDR + 0x33C)
    #define MISC_EXTLB_RX15_R_EXTLB_LFSR_RX_INI_30 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX15_R_EXTLB_LFSR_RX_INI_31 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX16 (DDRPHY_BASE_ADDR + 0x340)
    #define MISC_EXTLB_RX16_R_EXTLB_LFSR_RX_INI_32 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX16_R_EXTLB_LFSR_RX_INI_33 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX17 (DDRPHY_BASE_ADDR + 0x344)
    #define MISC_EXTLB_RX17_R_EXTLB_LFSR_RX_INI_34 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX17_R_EXTLB_LFSR_RX_INI_35 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX18 (DDRPHY_BASE_ADDR + 0x348)
    #define MISC_EXTLB_RX18_R_EXTLB_LFSR_RX_INI_36 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX18_R_EXTLB_LFSR_RX_INI_37 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX19 (DDRPHY_BASE_ADDR + 0x34C)
    #define MISC_EXTLB_RX19_R_EXTLB_LFSR_RX_INI_38 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX19_R_EXTLB_LFSR_RX_INI_39 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX20 (DDRPHY_BASE_ADDR + 0x350)
    #define MISC_EXTLB_RX20_R_EXTLB_LFSR_RX_INI_40 Fld(16,0,AC_FULLW10)//[15:0]
    #define MISC_EXTLB_RX20_R_EXTLB_LFSR_RX_INI_41 Fld(16,16,AC_FULLW32)//[31:16]
#define DDRPHY_MISC_EXTLB_RX21 (DDRPHY_BASE_ADDR + 0x354)
    #define MISC_EXTLB_RX21_R_EXTLB_LFSR_RX_INI_42 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_EXTLB_RX22 (DDRPHY_BASE_ADDR + 0x358)
    #define MISC_EXTLB_RX22_R_XTALK_RX_07_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB_RX22_R_XTALK_RX_06_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB_RX22_R_XTALK_RX_05_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB_RX22_R_XTALK_RX_04_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB_RX22_R_XTALK_RX_03_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB_RX22_R_XTALK_RX_02_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB_RX22_R_XTALK_RX_01_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB_RX22_R_XTALK_RX_00_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB_RX23 (DDRPHY_BASE_ADDR + 0x35C)
    #define MISC_EXTLB_RX23_R_XTALK_RX_15_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB_RX23_R_XTALK_RX_14_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB_RX23_R_XTALK_RX_13_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB_RX23_R_XTALK_RX_12_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB_RX23_R_XTALK_RX_11_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB_RX23_R_XTALK_RX_10_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB_RX23_R_XTALK_RX_09_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB_RX23_R_XTALK_RX_08_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB_RX24 (DDRPHY_BASE_ADDR + 0x360)
    #define MISC_EXTLB_RX24_R_XTALK_RX_23_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB_RX24_R_XTALK_RX_22_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB_RX24_R_XTALK_RX_21_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB_RX24_R_XTALK_RX_20_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB_RX24_R_XTALK_RX_19_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB_RX24_R_XTALK_RX_18_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB_RX24_R_XTALK_RX_17_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB_RX24_R_XTALK_RX_16_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB_RX25 (DDRPHY_BASE_ADDR + 0x364)
    #define MISC_EXTLB_RX25_R_XTALK_RX_31_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB_RX25_R_XTALK_RX_30_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB_RX25_R_XTALK_RX_29_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB_RX25_R_XTALK_RX_28_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB_RX25_R_XTALK_RX_27_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB_RX25_R_XTALK_RX_26_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB_RX25_R_XTALK_RX_25_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB_RX25_R_XTALK_RX_24_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB_RX26 (DDRPHY_BASE_ADDR + 0x368)
    #define MISC_EXTLB_RX26_R_XTALK_RX_39_TOG_CYCLE Fld(4,28,AC_MSKB3)//[31:28]
    #define MISC_EXTLB_RX26_R_XTALK_RX_38_TOG_CYCLE Fld(4,24,AC_MSKB3)//[27:24]
    #define MISC_EXTLB_RX26_R_XTALK_RX_37_TOG_CYCLE Fld(4,20,AC_MSKB2)//[23:20]
    #define MISC_EXTLB_RX26_R_XTALK_RX_36_TOG_CYCLE Fld(4,16,AC_MSKB2)//[19:16]
    #define MISC_EXTLB_RX26_R_XTALK_RX_35_TOG_CYCLE Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_EXTLB_RX26_R_XTALK_RX_34_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB_RX26_R_XTALK_RX_33_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB_RX26_R_XTALK_RX_32_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB_RX27 (DDRPHY_BASE_ADDR + 0x36C)
    #define MISC_EXTLB_RX27_R_XTALK_RX_42_TOG_CYCLE Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_EXTLB_RX27_R_XTALK_RX_41_TOG_CYCLE Fld(4,4,AC_MSKB0)//[7:4]
    #define MISC_EXTLB_RX27_R_XTALK_RX_40_TOG_CYCLE Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_MISC_EXTLB_RX28 (DDRPHY_BASE_ADDR + 0x370)
    #define MISC_EXTLB_RX28_R_EXTLB_RX_GATE_DELSEL_CA Fld(7,16,AC_MSKB2)//[22:16]
    #define MISC_EXTLB_RX28_R_EXTLB_RX_GATE_DELSEL_DQB1 Fld(7,8,AC_MSKB1)//[14:8]
    #define MISC_EXTLB_RX28_R_EXTLB_RX_GATE_DELSEL_DQB0 Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO0 (DDRPHY_BASE_ADDR + 0x400)
    #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO1 (DDRPHY_BASE_ADDR + 0x404)
    #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO2 (DDRPHY_BASE_ADDR + 0x408)
    #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO3 (DDRPHY_BASE_ADDR + 0x40C)
    #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO4 (DDRPHY_BASE_ADDR + 0x410)
    #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO5 (DDRPHY_BASE_ADDR + 0x414)
    #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO6 (DDRPHY_BASE_ADDR + 0x418)
    #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO7 (DDRPHY_BASE_ADDR + 0x41C)
    #define MISC_DQ_RXDLY_TRRO7_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO7_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO8 (DDRPHY_BASE_ADDR + 0x420)
    #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO9 (DDRPHY_BASE_ADDR + 0x424)
    #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO10 (DDRPHY_BASE_ADDR + 0x428)
    #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO11 (DDRPHY_BASE_ADDR + 0x42C)
    #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO12 (DDRPHY_BASE_ADDR + 0x430)
    #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO13 (DDRPHY_BASE_ADDR + 0x434)
    #define MISC_DQ_RXDLY_TRRO13_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO14 (DDRPHY_BASE_ADDR + 0x438)
    #define MISC_DQ_RXDLY_TRRO14_RESERVED_438 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO15 (DDRPHY_BASE_ADDR + 0x43C)
    #define MISC_DQ_RXDLY_TRRO15_PBYTE_LEADLAG_STUCK_CA Fld(1,27,AC_MSKB3)//[27:27]
    #define MISC_DQ_RXDLY_TRRO15_PBYTE_LEADLAG_STUCK_B1 Fld(1,25,AC_MSKB3)//[25:25]
    #define MISC_DQ_RXDLY_TRRO15_PBYTE_LEADLAG_STUCK_B0 Fld(1,24,AC_MSKB3)//[24:24]
    #define MISC_DQ_RXDLY_TRRO15_DVS_RK2_B1_SW_UP_DONE Fld(1,20,AC_MSKB2)//[20:20]
    #define MISC_DQ_RXDLY_TRRO15_DVS_RK2_B0_SW_UP_DONE Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_DQ_RXDLY_TRRO15_DVS_RK1_B1_SW_UP_DONE Fld(1,12,AC_MSKB1)//[12:12]
    #define MISC_DQ_RXDLY_TRRO15_DVS_RK1_B0_SW_UP_DONE Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_DQ_RXDLY_TRRO15_DVS_RK0_B1_SW_UP_DONE Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_DQ_RXDLY_TRRO15_DVS_RK0_B0_SW_UP_DONE Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO16 (DDRPHY_BASE_ADDR + 0x440)
    #define MISC_DQ_RXDLY_TRRO16_DVS_RKX_BX_TH_CNT_OUT_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO16_DVS_RKX_BX_TH_CNT_OUT_B0 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO17 (DDRPHY_BASE_ADDR + 0x444)
    #define MISC_DQ_RXDLY_TRRO17_DVS_RKX_BX_TH_CNT_OUT_B3 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO17_DVS_RKX_BX_TH_CNT_OUT_B2 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO18 (DDRPHY_BASE_ADDR + 0x448)
    #define MISC_DQ_RXDLY_TRRO18_DVS_RKX_BX_TH_CNT_OUT_B5 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO18_DVS_RKX_BX_TH_CNT_OUT_B4 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO19 (DDRPHY_BASE_ADDR + 0x44C)
    #define MISC_DQ_RXDLY_TRRO19_DVS_RKX_BX_TH_CNT_OUT_B7 Fld(16,16,AC_FULLW32)//[31:16]
    #define MISC_DQ_RXDLY_TRRO19_DVS_RKX_BX_TH_CNT_OUT_B6 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO20 (DDRPHY_BASE_ADDR + 0x450)
    #define MISC_DQ_RXDLY_TRRO20_DVS_RKX_BX_TH_CNT_OUT_DQM0 Fld(16,0,AC_FULLW10)//[15:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO21 (DDRPHY_BASE_ADDR + 0x454)
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_DQM0_16 Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B7_16 Fld(1,14,AC_MSKB1)//[14:14]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B6_16 Fld(1,12,AC_MSKB1)//[12:12]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B5_16 Fld(1,10,AC_MSKB1)//[10:10]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B4_16 Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B3_16 Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B2_16 Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B1_16 Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_DQ_RXDLY_TRRO21_DVS_RKX_BX_TH_CNT_OUT_B0_16 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO22 (DDRPHY_BASE_ADDR + 0x458)
    #define MISC_DQ_RXDLY_TRRO22_DA_RK0_DQS1_R_DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define MISC_DQ_RXDLY_TRRO22_DA_RK0_DQX_B1_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define MISC_DQ_RXDLY_TRRO22_DA_RK0_DQS0_R_DLY Fld(7,8,AC_MSKB1)//[14:8]
    #define MISC_DQ_RXDLY_TRRO22_DA_RK0_DQX_B0_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO23 (DDRPHY_BASE_ADDR + 0x45C)
    #define MISC_DQ_RXDLY_TRRO23_DA_RK1_DQS1_R_DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define MISC_DQ_RXDLY_TRRO23_DA_RK1_DQX_B1_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define MISC_DQ_RXDLY_TRRO23_DA_RK1_DQS0_R_DLY Fld(7,8,AC_MSKB1)//[14:8]
    #define MISC_DQ_RXDLY_TRRO23_DA_RK1_DQX_B0_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO24 (DDRPHY_BASE_ADDR + 0x460)
    #define MISC_DQ_RXDLY_TRRO24_DA_RK2_DQS1_R_DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define MISC_DQ_RXDLY_TRRO24_DA_RK2_DQX_B1_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define MISC_DQ_RXDLY_TRRO24_DA_RK2_DQS0_R_DLY Fld(7,8,AC_MSKB1)//[14:8]
    #define MISC_DQ_RXDLY_TRRO24_DA_RK2_DQX_B0_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO25 (DDRPHY_BASE_ADDR + 0x464)
    #define MISC_DQ_RXDLY_TRRO25_DVS_RXDLY_STS_ERR_CNT_ALL Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_DQ_RXDLY_TRRO26 (DDRPHY_BASE_ADDR + 0x468)
    #define MISC_DQ_RXDLY_TRRO26_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CA_RXDLY_TRRO27 (DDRPHY_BASE_ADDR + 0x46C)
    #define MISC_CA_RXDLY_TRRO27_RESERVED_46C Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CA_RXDLY_TRRO28 (DDRPHY_BASE_ADDR + 0x470)
    #define MISC_CA_RXDLY_TRRO28_RESERVED_470 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CA_RXDLY_TRRO29 (DDRPHY_BASE_ADDR + 0x474)
    #define MISC_CA_RXDLY_TRRO29_RESERVED_474 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CA_RXDLY_TRRO30 (DDRPHY_BASE_ADDR + 0x478)
    #define MISC_CA_RXDLY_TRRO30_RESERVED_478 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CA_RXDLY_TRRO31 (DDRPHY_BASE_ADDR + 0x47C)
    #define MISC_CA_RXDLY_TRRO31_RESERVED_47C Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_PHY_RGS0 (DDRPHY_BASE_ADDR + 0x500)
    #define MISC_PHY_RGS0_PHY_RO_1 Fld(12,20,AC_MSKW32)//[31:20]
    #define MISC_PHY_RGS0_RGS_RX_ARDQS0_DLY_RDY_EYE_B1 Fld(1,19,AC_MSKB2)//[19:19]
    #define MISC_PHY_RGS0_RGS_ARDQM0_OFFSET_FLAG_B1 Fld(1,18,AC_MSKB2)//[18:18]
    #define MISC_PHY_RGS0_RGS_RX_ARDQS0_DLY_RDY_EYE_B0 Fld(1,17,AC_MSKB2)//[17:17]
    #define MISC_PHY_RGS0_RGS_ARDQM0_OFFSET_FLAG_B0 Fld(1,16,AC_MSKB2)//[16:16]
    #define MISC_PHY_RGS0_RGS_ARDQ_OFFSET_FLAG_B1 Fld(8,8,AC_FULLB1)//[15:8]
    #define MISC_PHY_RGS0_RGS_ARDQ_OFFSET_FLAG_B0 Fld(8,0,AC_FULLB0)//[7:0]

//Page DDRPHY_4
#define DDRPHY_MISC_PHY_RGS1 (DDRPHY_BASE_ADDR + 0x504)
    #define MISC_PHY_RGS1_PHY_RO_2 Fld(18,14,AC_MSKDW)//[31:14]
    #define MISC_PHY_RGS1_RGS_RIMPCALOUT Fld(1,13,AC_MSKB1)//[13:13]
    #define MISC_PHY_RGS1_RGS_RX_ARCLK_DLY_RDY_EYE Fld(1,12,AC_MSKB1)//[12:12]
    #define MISC_PHY_RGS1_RGS_ARCS2_OFFSET_FLAG Fld(1,11,AC_MSKB1)//[11:11]
    #define MISC_PHY_RGS1_RGS_ARCS1_OFFSET_FLAG Fld(1,10,AC_MSKB1)//[10:10]
    #define MISC_PHY_RGS1_RGS_ARCS0_OFFSET_FLAG Fld(1,9,AC_MSKB1)//[9:9]
    #define MISC_PHY_RGS1_RGS_ARCKE2_OFFSET_FLAG Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_PHY_RGS1_RGS_ARCKE1_OFFSET_FLAG Fld(1,7,AC_MSKB0)//[7:7]
    #define MISC_PHY_RGS1_RGS_ARCKE0_OFFSET_FLAG Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_PHY_RGS1_RGS_ARCA5_OFFSET_FLAG Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_PHY_RGS1_RGS_ARCA4_OFFSET_FLAG Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_PHY_RGS1_RGS_ARCA3_OFFSET_FLAG Fld(1,3,AC_MSKB0)//[3:3]
    #define MISC_PHY_RGS1_RGS_ARCA2_OFFSET_FLAG Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_PHY_RGS1_RGS_ARCA1_OFFSET_FLAG Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_PHY_RGS1_RGS_ARCA0_OFFSET_FLAG Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_PHY_RGS2 (DDRPHY_BASE_ADDR + 0x508)
    #define MISC_PHY_RGS2_AD_RX_ARDQ4_STBEN Fld(8,16,AC_FULLB2)//[23:16]
    #define MISC_PHY_RGS2_AD_RX_ARDQS0_STBEN_LAG Fld(1,9,AC_MSKB1)//[9:9]
    #define MISC_PHY_RGS2_AD_RX_ARDQS0_STBEN_LEAD Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_PHY_RGS2_AD_RX_ARDQ0_STBEN Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_MISC_PHY_RGS3 (DDRPHY_BASE_ADDR + 0x50C)
    #define MISC_PHY_RGS3_AD_RX_ARDQ12_STBEN Fld(8,16,AC_FULLB2)//[23:16]
    #define MISC_PHY_RGS3_AD_RX_ARDQS1_STBEN_LAG Fld(1,9,AC_MSKB1)//[9:9]
    #define MISC_PHY_RGS3_AD_RX_ARDQS1_STBEN_LEAD Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_PHY_RGS3_AD_RX_ARDQ8_STBEN Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_MISC_DQO1 (DDRPHY_BASE_ADDR + 0x528)
    #define MISC_DQO1_DQO1_RO Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_CAO1 (DDRPHY_BASE_ADDR + 0x52C)
    #define MISC_CAO1_DQM0O1_RO Fld(1,14,AC_MSKB1)//[14:14]
    #define MISC_CAO1_DQM1O1_RO Fld(1,13,AC_MSKB1)//[13:13]
    #define MISC_CAO1_CKEO1_RO Fld(1,11,AC_MSKB1)//[11:11]
    #define MISC_CAO1_CKE1O1_RO Fld(1,10,AC_MSKB1)//[10:10]
    #define MISC_CAO1_CKE2O1_RO Fld(1,9,AC_MSKB1)//[9:9]
    #define MISC_CAO1_CSO1_RO Fld(1,8,AC_MSKB1)//[8:8]
    #define MISC_CAO1_CS1O1_RO Fld(1,7,AC_MSKB0)//[7:7]
    #define MISC_CAO1_CS2O1_RO Fld(1,6,AC_MSKB0)//[6:6]
    #define MISC_CAO1_RA0_O1 Fld(1,5,AC_MSKB0)//[5:5]
    #define MISC_CAO1_RA1_O1 Fld(1,4,AC_MSKB0)//[4:4]
    #define MISC_CAO1_RA2_O1 Fld(1,3,AC_MSKB0)//[3:3]
    #define MISC_CAO1_RA3_O1 Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_CAO1_RA4_O1 Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_CAO1_RA5_O1 Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_STA_EXTLB0 (DDRPHY_BASE_ADDR + 0x580)
    #define MISC_STA_EXTLB0_STA_EXTLB_DONE_31_0 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_STA_EXTLB1 (DDRPHY_BASE_ADDR + 0x584)
    #define MISC_STA_EXTLB1_STA_EXTLB_DONE_42_32 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_STA_EXTLB2 (DDRPHY_BASE_ADDR + 0x588)
    #define MISC_STA_EXTLB2_STA_EXTLB_FAIL_31_0 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_STA_EXTLB3 (DDRPHY_BASE_ADDR + 0x58C)
    #define MISC_STA_EXTLB3_STA_EXTLB_FAIL_42_32 Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_STA_EXTLB4 (DDRPHY_BASE_ADDR + 0x590)
    #define MISC_STA_EXTLB4_STA_EXTLB_DBG_INFO Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_APHY_PD_STATUS (DDRPHY_BASE_ADDR + 0x5A0)
    #define MISC_APHY_PD_STATUS_ARCKGEN_DLL_PD_EN_B01 Fld(1,3,AC_MSKB0)//[3:3]
    #define MISC_APHY_PD_STATUS_ARCKGEN_DLL_PD_EN_CA Fld(1,2,AC_MSKB0)//[2:2]
    #define MISC_APHY_PD_STATUS_ARDLL_PD_EN_B01 Fld(1,1,AC_MSKB0)//[1:1]
    #define MISC_APHY_PD_STATUS_ARDLL_PD_EN_CA Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_MISC_RXDVS0 (DDRPHY_BASE_ADDR + 0x5E0)
    #define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define DDRPHY_MISC_RXDVS1 (DDRPHY_BASE_ADDR + 0x5E4)
    #define MISC_RXDVS1_R_IN_GATE_EN_LOW_OPT Fld(32,0,AC_FULLDW)//[31:0]
#define DDRPHY_MISC_RXDVS2 (DDRPHY_BASE_ADDR + 0x5E8)
    #define MISC_RXDVS2_R_RXDVS_RDSEL_TOG_LAT Fld(3,5,AC_MSKB0)//[7:5]
    #define MISC_RXDVS2_R_RXDVS_RDSEL_BUS_LAT Fld(3,2,AC_MSKB0)//[4:2]
    #define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF Fld(1,0,AC_MSKB0)//[0:0]
#define DDRPHY_DVFS_EMI_CLK (DDRPHY_BASE_ADDR + 0x5EC)
    #define DVFS_EMI_CLK_RG_GATING_EMI_NEW_0 Fld(1,31,AC_MSKB3)//[31:31]
    #define DVFS_EMI_CLK_RG_GATING_EMI_NEW_1 Fld(1,30,AC_MSKB3)//[30:30]
    #define DVFS_EMI_CLK_RG_52M_104M_SEL Fld(1,29,AC_MSKB3)//[29:29]
#define DDRPHY_SHU1_B0_DQ0 (DDRPHY_BASE_ADDR + 0xC00)
    #define SHU1_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU1_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU1_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 Fld(1,20,AC_MSKB2)//[20:20]
    #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU1_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 Fld(1,4,AC_MSKB0)//[4:4]
#define DDRPHY_SHU1_B0_DQ1 (DDRPHY_BASE_ADDR + 0xC04)
    #define SHU1_B0_DQ1_RG_TX_ARDQ_ODTN_B0 Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU1_B0_DQ1_RG_TX_ARDQ_ODTP_B0 Fld(5,16,AC_MSKB2)//[20:16]
    #define SHU1_B0_DQ1_RG_TX_ARDQ_DRVN_B0 Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU1_B0_DQ1_RG_TX_ARDQ_DRVP_B0 Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_SHU1_B0_DQ2 (DDRPHY_BASE_ADDR + 0xC08)
    #define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 Fld(5,16,AC_MSKB2)//[20:16]
    #define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_SHU1_B0_DQ3 (DDRPHY_BASE_ADDR + 0xC0C)
    #define SHU1_B0_DQ3_RG_TX_ARDQS0B_DLYB_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_B0_DQ3_RG_TX_ARDQS0_DLYB_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 Fld(2,14,AC_MSKB1)//[15:14]
    #define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_B0 Fld(2,12,AC_MSKB1)//[13:12]
    #define SHU1_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 Fld(2,10,AC_MSKB1)//[11:10]
    #define SHU1_B0_DQ3_RG_TX_ARDQ_PU_B0 Fld(2,8,AC_MSKB1)//[9:8]
    #define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 Fld(2,6,AC_MSKB0)//[7:6]
    #define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_B0 Fld(2,4,AC_MSKB0)//[5:4]
    #define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 Fld(2,2,AC_MSKB0)//[3:2]
    #define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_B0 Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_SHU1_B0_DQ4 (DDRPHY_BASE_ADDR + 0xC10)
    #define SHU1_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_B0_DQ5 (DDRPHY_BASE_ADDR + 0xC14)
    #define SHU1_B0_DQ5_RG_ARPI_MCTL_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU1_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU1_B0_DQ5_RG_ARPI_FB_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_B0_DQ5_RX_RX_ARDQ_VREF_BYPASS_B0 Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_B0_DQ6 (DDRPHY_BASE_ADDR + 0xC18)
    #define SHU1_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0 Fld(1,26,AC_MSKB3)//[26:26]
    #define SHU1_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 Fld(2,24,AC_MSKB3)//[25:24]
    #define SHU1_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 Fld(2,22,AC_MSKB2)//[23:22]
    #define SHU1_B0_DQ6_RG_ARPI_RESERVE_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_B0_DQ6_RG_ARPI_CAP_SEL_B0 Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_SHU1_B0_DQ7 (DDRPHY_BASE_ADDR + 0xC1C)
    #define SHU1_B0_DQ7_RG_ARDQ_REV_B0 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 Fld(1,13,AC_MSKB1)//[13:13]
    #define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU1_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0 Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU1_B0_DQ7_R_DMDQMDBI_SHU_EYE_B0 Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU1_B0_DQ7_R_DMDQMDBI_INV_EN_B0 Fld(1,5,AC_MSKB0)//[5:5]
    #define SHU1_B0_DQ7_R_DMRANKRXDVS_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_B1_DQ0 (DDRPHY_BASE_ADDR + 0xC80)
    #define SHU1_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU1_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU1_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 Fld(1,20,AC_MSKB2)//[20:20]
    #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU1_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 Fld(1,4,AC_MSKB0)//[4:4]
#define DDRPHY_SHU1_B1_DQ1 (DDRPHY_BASE_ADDR + 0xC84)
    #define SHU1_B1_DQ1_RG_TX_ARDQ_ODTN_B1 Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU1_B1_DQ1_RG_TX_ARDQ_ODTP_B1 Fld(5,16,AC_MSKB2)//[20:16]
    #define SHU1_B1_DQ1_RG_TX_ARDQ_DRVN_B1 Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU1_B1_DQ1_RG_TX_ARDQ_DRVP_B1 Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_SHU1_B1_DQ2 (DDRPHY_BASE_ADDR + 0xC88)
    #define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 Fld(5,16,AC_MSKB2)//[20:16]
    #define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_SHU1_B1_DQ3 (DDRPHY_BASE_ADDR + 0xC8C)
    #define SHU1_B1_DQ3_RG_TX_ARDQS0B_DLYB_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_B1_DQ3_RG_TX_ARDQS0_DLYB_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 Fld(2,14,AC_MSKB1)//[15:14]
    #define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_B1 Fld(2,12,AC_MSKB1)//[13:12]
    #define SHU1_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 Fld(2,10,AC_MSKB1)//[11:10]
    #define SHU1_B1_DQ3_RG_TX_ARDQ_PU_B1 Fld(2,8,AC_MSKB1)//[9:8]
    #define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 Fld(2,6,AC_MSKB0)//[7:6]
    #define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_B1 Fld(2,4,AC_MSKB0)//[5:4]
    #define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 Fld(2,2,AC_MSKB0)//[3:2]
    #define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_B1 Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_SHU1_B1_DQ4 (DDRPHY_BASE_ADDR + 0xC90)
    #define SHU1_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_B1_DQ5 (DDRPHY_BASE_ADDR + 0xC94)
    #define SHU1_B1_DQ5_RG_ARPI_MCTL_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU1_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU1_B1_DQ5_RG_ARPI_FB_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_B1_DQ6 (DDRPHY_BASE_ADDR + 0xC98)
    #define SHU1_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1 Fld(1,26,AC_MSKB3)//[26:26]
    #define SHU1_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 Fld(2,24,AC_MSKB3)//[25:24]
    #define SHU1_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 Fld(2,22,AC_MSKB2)//[23:22]
    #define SHU1_B1_DQ6_RG_ARPI_RESERVE_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_B1_DQ6_RG_ARPI_CAP_SEL_B1 Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_SHU1_B1_DQ7 (DDRPHY_BASE_ADDR + 0xC9C)
    #define SHU1_B1_DQ7_RG_ARDQ_REV_B1 Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 Fld(1,13,AC_MSKB1)//[13:13]
    #define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU1_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_B1_DQ7_R_DMDQMDBI_SHU_B1 Fld(1,7,AC_MSKB0)//[7:7]
    #define SHU1_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU1_B1_DQ7_R_DMDQMDBI_INV_EN_B1 Fld(1,5,AC_MSKB0)//[5:5]
    #define SHU1_B1_DQ7_R_DMRANKRXDVS_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_CA_CMD0 (DDRPHY_BASE_ADDR + 0xD00)
    #define SHU1_CA_CMD0_RG_TX_ARCMD_DRVN_PRE Fld(3,28,AC_MSKB3)//[30:28]
    #define SHU1_CA_CMD0_RG_TX_ARCMD_DRVP_PRE Fld(3,24,AC_MSKB3)//[26:24]
    #define SHU1_CA_CMD0_RG_TX_ARCMD_PRE_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE Fld(3,12,AC_MSKB1)//[14:12]
    #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE Fld(3,8,AC_MSKB1)//[10:8]
    #define SHU1_CA_CMD0_RG_TX_ARCLK_PRE_EN Fld(1,4,AC_MSKB0)//[4:4]
#define DDRPHY_SHU1_CA_CMD1 (DDRPHY_BASE_ADDR + 0xD04)
    #define SHU1_CA_CMD1_RG_TX_ARCMD_ODTN Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU1_CA_CMD1_RG_TX_ARCMD_ODTP Fld(5,16,AC_MSKB2)//[20:16]
    #define SHU1_CA_CMD1_RG_TX_ARCMD_DRVN Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU1_CA_CMD1_RG_TX_ARCMD_DRVP Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_SHU1_CA_CMD2 (DDRPHY_BASE_ADDR + 0xD08)
    #define SHU1_CA_CMD2_RG_TX_ARCLK_ODTN Fld(5,24,AC_MSKB3)//[28:24]
    #define SHU1_CA_CMD2_RG_TX_ARCLK_ODTP Fld(5,16,AC_MSKB2)//[20:16]
    #define SHU1_CA_CMD2_RG_TX_ARCLK_DRVN Fld(5,8,AC_MSKB1)//[12:8]
    #define SHU1_CA_CMD2_RG_TX_ARCLK_DRVP Fld(5,0,AC_MSKB0)//[4:0]
#define DDRPHY_SHU1_CA_CMD3 (DDRPHY_BASE_ADDR + 0xD0C)
    #define SHU1_CA_CMD3_RG_TX_ARCLKB_DLYB Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_CA_CMD3_RG_TX_ARCLK_DLYB Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_CA_CMD3_RG_TX_ARCMD_PDB_PRE Fld(2,14,AC_MSKB1)//[15:14]
    #define SHU1_CA_CMD3_RG_TX_ARCMD_PDB Fld(2,12,AC_MSKB1)//[13:12]
    #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE Fld(2,10,AC_MSKB1)//[11:10]
    #define SHU1_CA_CMD3_RG_TX_ARCMD_PU Fld(2,8,AC_MSKB1)//[9:8]
    #define SHU1_CA_CMD3_RG_TX_ARCLK_PDB_PRE Fld(2,6,AC_MSKB0)//[7:6]
    #define SHU1_CA_CMD3_RG_TX_ARCLK_PDB Fld(2,4,AC_MSKB0)//[5:4]
    #define SHU1_CA_CMD3_RG_TX_ARCLK_PU_PRE Fld(2,2,AC_MSKB0)//[3:2]
    #define SHU1_CA_CMD3_RG_TX_ARCLK_PU Fld(2,0,AC_MSKB0)//[1:0]
#define DDRPHY_SHU1_CA_CMD4 (DDRPHY_BASE_ADDR + 0xD10)
    #define SHU1_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_CA_CMD4_RG_ARPI_AA_MCK_DL_CA Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_CA_CMD5 (DDRPHY_BASE_ADDR + 0xD14)
    #define SHU1_CA_CMD5_RG_ARPI_MCTL_CA Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_CA_CMD5_RG_RX_ARCLK_DVS_DLY Fld(3,20,AC_MSKB2)//[22:20]
    #define SHU1_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY Fld(3,16,AC_MSKB2)//[18:16]
    #define SHU1_CA_CMD5_RG_ARPI_FB_CA Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS Fld(1,6,AC_MSKB0)//[6:6]
    #define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_SEL Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_CA_CMD6 (DDRPHY_BASE_ADDR + 0xD18)
    #define SHU1_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA Fld(1,27,AC_MSKB3)//[27:27]
    #define SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA Fld(1,26,AC_MSKB3)//[26:26]
    #define SHU1_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA Fld(2,24,AC_MSKB3)//[25:24]
    #define SHU1_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA Fld(2,22,AC_MSKB2)//[23:22]
    #define SHU1_CA_CMD6_RG_ARPI_RESERVE_CA Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_CA_CMD6_RG_ARPI_CAP_SEL_CA Fld(8,0,AC_FULLB0)//[7:0]
#define DDRPHY_SHU1_CA_CMD7 (DDRPHY_BASE_ADDR + 0xD1C)
    #define SHU1_CA_CMD7_RG_ARCMD_REV Fld(16,16,AC_FULLW32)//[31:16]
    #define SHU1_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA Fld(1,12,AC_MSKB1)//[12:12]
    #define SHU1_CA_CMD7_R_DMRANKRXDVS_CA Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_B0_DQ0 (DDRPHY_BASE_ADDR + 0xE00)
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_B0_DQ1 (DDRPHY_BASE_ADDR + 0xE04)
    #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_B0_DQ2 (DDRPHY_BASE_ADDR + 0xE08)
    #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B0_DQ3 (DDRPHY_BASE_ADDR + 0xE0C)
    #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B0_DQ4 (DDRPHY_BASE_ADDR + 0xE10)
    #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B0_DQ5 (DDRPHY_BASE_ADDR + 0xE14)
    #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B0_DQ6 (DDRPHY_BASE_ADDR + 0xE18)
    #define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 Fld(7,16,AC_MSKB2)//[22:16]
    #define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B0_DQ7 (DDRPHY_BASE_ADDR + 0xE1C)
    #define SHU1_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_SHU1_R0_B1_DQ0 (DDRPHY_BASE_ADDR + 0xE50)
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_B1_DQ1 (DDRPHY_BASE_ADDR + 0xE54)
    #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_B1_DQ2 (DDRPHY_BASE_ADDR + 0xE58)
    #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B1_DQ3 (DDRPHY_BASE_ADDR + 0xE5C)
    #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B1_DQ4 (DDRPHY_BASE_ADDR + 0xE60)
    #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_B1_DQ5 (DDRPHY_BASE_ADDR + 0xE64)
    #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]

//Page DDRPHY_5
#define DDRPHY_SHU1_R0_B1_DQ6 (DDRPHY_BASE_ADDR + 0xE68)
    #define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 Fld(7,8,AC_MSKB1)//[14:8]
    #define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_SHU1_R0_B1_DQ7 (DDRPHY_BASE_ADDR + 0xE6C)
    #define SHU1_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_SHU1_R0_CA_CMD0 (DDRPHY_BASE_ADDR + 0xEA0)
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCLK_DLYB Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_CA_CMD1 (DDRPHY_BASE_ADDR + 0xEA4)
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCLKB_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCLK_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCS2_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCS1_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCS0_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE2_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE1_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE0_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_CA_CMD2 (DDRPHY_BASE_ADDR + 0xEA8)
    #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA3_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA2_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD3 (DDRPHY_BASE_ADDR + 0xEAC)
    #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA7_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA6_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA5_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA4_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD4 (DDRPHY_BASE_ADDR + 0xEB0)
    #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA11_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA10_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA9_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA8_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD5 (DDRPHY_BASE_ADDR + 0xEB4)
    #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCA15_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCA14_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCA13_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCA12_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD6 (DDRPHY_BASE_ADDR + 0xEB8)
    #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCA19_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCA18_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCA17_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCA16_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD7 (DDRPHY_BASE_ADDR + 0xEBC)
    #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCA20_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCKE1_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCKE0_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD8 (DDRPHY_BASE_ADDR + 0xEC0)
    #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARRESETB_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCS1_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCS0_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD9 (DDRPHY_BASE_ADDR + 0xEC4)
    #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R0_CA_CMD10 (DDRPHY_BASE_ADDR + 0xEC8)
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA13_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA12_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA11_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA10_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA9_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA8_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA7_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R0_CA_CMD10_RK0_TX_ARCA6_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R0_CA_CMD11 (DDRPHY_BASE_ADDR + 0xECC)
    #define SHU1_R0_CA_CMD11_RK0_TX_ARRESETB_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA20_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA19_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA18_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA17_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA16_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA15_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R0_CA_CMD11_RK0_TX_ARCA14_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_B0_DQ0 (DDRPHY_BASE_ADDR + 0xF00)
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_B0_DQ1 (DDRPHY_BASE_ADDR + 0xF04)
    #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_B0_DQ2 (DDRPHY_BASE_ADDR + 0xF08)
    #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B0_DQ3 (DDRPHY_BASE_ADDR + 0xF0C)
    #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B0_DQ4 (DDRPHY_BASE_ADDR + 0xF10)
    #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B0_DQ5 (DDRPHY_BASE_ADDR + 0xF14)
    #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B0_DQ6 (DDRPHY_BASE_ADDR + 0xF18)
    #define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 Fld(7,16,AC_MSKB2)//[22:16]
    #define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B0_DQ7 (DDRPHY_BASE_ADDR + 0xF1C)
    #define SHU1_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B0_DQ7_RK1_ARPI_DQM_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B0_DQ7_RK1_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_SHU1_R1_B1_DQ0 (DDRPHY_BASE_ADDR + 0xF50)
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_B1_DQ1 (DDRPHY_BASE_ADDR + 0xF54)
    #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_B1_DQ2 (DDRPHY_BASE_ADDR + 0xF58)
    #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B1_DQ3 (DDRPHY_BASE_ADDR + 0xF5C)
    #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B1_DQ4 (DDRPHY_BASE_ADDR + 0xF60)
    #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B1_DQ5 (DDRPHY_BASE_ADDR + 0xF64)
    #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_B1_DQ6 (DDRPHY_BASE_ADDR + 0xF68)
    #define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 Fld(7,8,AC_MSKB1)//[14:8]
    #define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_SHU1_R1_B1_DQ7 (DDRPHY_BASE_ADDR + 0xF6C)
    #define SHU1_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_B1_DQ7_RK1_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_B1_DQ7_RK1_ARPI_DQ_B1 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_SHU1_R1_CA_CMD0 (DDRPHY_BASE_ADDR + 0xFA0)
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCLK_DLYB Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCA5_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCA4_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCA3_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCA2_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCA1_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R1_CA_CMD0_RK1_TX_ARCA0_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_CA_CMD1 (DDRPHY_BASE_ADDR + 0xFA4)
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCLKB_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCLK_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCS2_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCS1_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCS0_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE2_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE1_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE0_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_CA_CMD2 (DDRPHY_BASE_ADDR + 0xFA8)
    #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA3_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA2_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD3 (DDRPHY_BASE_ADDR + 0xFAC)
    #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA7_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA6_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA5_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA4_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD4 (DDRPHY_BASE_ADDR + 0xFB0)
    #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA11_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA10_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA9_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA8_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD5 (DDRPHY_BASE_ADDR + 0xFB4)
    #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCA15_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCA14_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCA13_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCA12_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD6 (DDRPHY_BASE_ADDR + 0xFB8)
    #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCA19_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCA18_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCA17_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCA16_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD7 (DDRPHY_BASE_ADDR + 0xFBC)
    #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCA20_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCKE1_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCKE0_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD8 (DDRPHY_BASE_ADDR + 0xFC0)
    #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R1_CA_CMD8_RG_RK0_RX_ARRESETB_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCS1_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCS0_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD9 (DDRPHY_BASE_ADDR + 0xFC4)
    #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CLK Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CS Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R1_CA_CMD10 (DDRPHY_BASE_ADDR + 0xFC8)
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA13_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA12_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA11_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA10_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA9_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA8_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA7_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R1_CA_CMD10_RK1_TX_ARCA6_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R1_CA_CMD11 (DDRPHY_BASE_ADDR + 0xFCC)
    #define SHU1_R1_CA_CMD11_RK1_TX_ARRESETB_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA20_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA19_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA18_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA17_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA16_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA15_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R1_CA_CMD11_RK1_TX_ARCA14_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_B0_DQ0 (DDRPHY_BASE_ADDR + 0x1000)
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_B0_DQ1 (DDRPHY_BASE_ADDR + 0x1004)
    #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_B0_DQ2 (DDRPHY_BASE_ADDR + 0x1008)
    #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B0_DQ3 (DDRPHY_BASE_ADDR + 0x100C)
    #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B0_DQ4 (DDRPHY_BASE_ADDR + 0x1010)
    #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B0_DQ5 (DDRPHY_BASE_ADDR + 0x1014)
    #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B0_DQ6 (DDRPHY_BASE_ADDR + 0x1018)
    #define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 Fld(7,16,AC_MSKB2)//[22:16]
    #define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B0_DQ7 (DDRPHY_BASE_ADDR + 0x101C)
    #define SHU1_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B0_DQ7_RK2_ARPI_DQM_B0 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B0_DQ7_RK2_ARPI_DQ_B0 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_SHU1_R2_B1_DQ0 (DDRPHY_BASE_ADDR + 0x1050)
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_B1_DQ1 (DDRPHY_BASE_ADDR + 0x1054)
    #define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_B1_DQ2 (DDRPHY_BASE_ADDR + 0x1058)
    #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B1_DQ3 (DDRPHY_BASE_ADDR + 0x105C)
    #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]

//Page DDRPHY_6
#define DDRPHY_SHU1_R2_B1_DQ4 (DDRPHY_BASE_ADDR + 0x1060)
    #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B1_DQ5 (DDRPHY_BASE_ADDR + 0x1064)
    #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_B1_DQ6 (DDRPHY_BASE_ADDR + 0x1068)
    #define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 Fld(7,8,AC_MSKB1)//[14:8]
    #define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 Fld(7,0,AC_MSKB0)//[6:0]
#define DDRPHY_SHU1_R2_B1_DQ7 (DDRPHY_BASE_ADDR + 0x106C)
    #define SHU1_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_B1_DQ7_RK2_ARPI_DQM_B1 Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_B1_DQ7_RK2_ARPI_DQ_B1 Fld(6,8,AC_MSKB1)//[13:8]
#define DDRPHY_SHU1_R2_CA_CMD0 (DDRPHY_BASE_ADDR + 0x10A0)
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCLK_DLYB Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCA5_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCA4_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCA3_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCA2_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCA1_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R2_CA_CMD0_RK2_TX_ARCA0_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_CA_CMD1 (DDRPHY_BASE_ADDR + 0x10A4)
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCLKB_DLY Fld(4,28,AC_MSKB3)//[31:28]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCLK_DLY Fld(4,24,AC_MSKB3)//[27:24]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCS2_DLY Fld(4,20,AC_MSKB2)//[23:20]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCS1_DLY Fld(4,16,AC_MSKB2)//[19:16]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCS0_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE2_DLY Fld(4,8,AC_MSKB1)//[11:8]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE1_DLY Fld(4,4,AC_MSKB0)//[7:4]
    #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE0_DLY Fld(4,0,AC_MSKB0)//[3:0]
#define DDRPHY_SHU1_R2_CA_CMD2 (DDRPHY_BASE_ADDR + 0x10A8)
    #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_CA_CMD3 (DDRPHY_BASE_ADDR + 0x10AC)
    #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_CA_CMD4 (DDRPHY_BASE_ADDR + 0x10B0)
    #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_CA_CMD5 (DDRPHY_BASE_ADDR + 0x10B4)
    #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_CA_CMD6 (DDRPHY_BASE_ADDR + 0x10B8)
    #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_CA_CMD7 (DDRPHY_BASE_ADDR + 0x10BC)
    #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY Fld(6,16,AC_MSKB2)//[21:16]
    #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY Fld(6,0,AC_MSKB0)//[5:0]
#define DDRPHY_SHU1_R2_CA_CMD8 (DDRPHY_BASE_ADDR + 0x10C0)
    #define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY Fld(7,24,AC_MSKB3)//[30:24]
    #define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY Fld(7,16,AC_MSKB2)//[22:16]
#define DDRPHY_SHU1_R2_CA_CMD9 (DDRPHY_BASE_ADDR + 0x10C4)
    #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CLK Fld(6,24,AC_MSKB3)//[29:24]
    #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CMD Fld(6,8,AC_MSKB1)//[13:8]
    #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CS Fld(6,0,AC_MSKB0)//[5:0]






