#ifndef _HW_MJC_PRE_H_
#define _HW_MJC_PRE_H_
#include "x_hal_5381.h"

#ifndef CC_FPGA
#define IO_ADDR_OFST IO_VIRT
#else
#define IO_ADDR_OFST 0xf0000000
#endif

#define MEMC_PRE (IO_ADDR_OFST + 0x44000)

//Page MEMC_PRE
#define MEMC_PRE_RGB2YUV_0 (MEMC_PRE + 0x700)
    #define MEMC_PRE_C_RGB2YUV_3X3_BY_OUT_SEL Fld(1,9,AC_MSKB1)//[9:9]
    #define MEMC_PRE_C_INT_TABLE_SEL Fld(4,5,AC_MSKW10)//[8:5]
    #define MEMC_PRE_C_EXT_TABLE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_PRE_C_OUTPUT_SIGNED Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_PRE_C_INPUT_SIGNED Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_PRE_C_RGB2YUV_BYPASS Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_RGB2YUV_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_RGB2YUV_1 (MEMC_PRE + 0x704)
    #define MEMC_PRE_C_EXT_PRE_ADD_2 Fld(9,20,AC_MSKW32)//[28:20]
    #define MEMC_PRE_C_EXT_PRE_ADD_1 Fld(9,10,AC_MSKW21)//[18:10]
    #define MEMC_PRE_C_EXT_PRE_ADD_0 Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_PRE_RGB2YUV_2 (MEMC_PRE + 0x708)
    #define MEMC_PRE_C_EXT_POST_ADD_2 Fld(9,20,AC_MSKW32)//[28:20]
    #define MEMC_PRE_C_EXT_POST_ADD_1 Fld(9,10,AC_MSKW21)//[18:10]
    #define MEMC_PRE_C_EXT_POST_ADD_0 Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_PRE_RGB2YUV_3 (MEMC_PRE + 0x70C)
    #define MEMC_PRE_C_EXT_C01 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_PRE_C_EXT_C00 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_RGB2YUV_4 (MEMC_PRE + 0x710)
    #define MEMC_PRE_C_EXT_C10 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_PRE_C_EXT_C02 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_RGB2YUV_5 (MEMC_PRE + 0x714)
    #define MEMC_PRE_C_EXT_C12 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_PRE_C_EXT_C11 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_RGB2YUV_6 (MEMC_PRE + 0x718)
    #define MEMC_PRE_C_EXT_C21 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_PRE_C_EXT_C20 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_RGB2YUV_7 (MEMC_PRE + 0x71C)
    #define MEMC_PRE_C_EXT_C22 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_YC444_420 (MEMC_PRE + 0x720)
    #define MEMC_PRE_C_444_TO_420_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_PRE_C_YC_SEL444 Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_444_TO_422_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_WDMA_0 (MEMC_PRE + 0x728)
    #define MEMC_PRE_C_WDMA_THRESHOLD_C Fld(8,21,AC_MSKW32)//[28:21]
    #define MEMC_PRE_C_WDMA_THRESHOLD_Y Fld(8,13,AC_MSKW21)//[20:13]
    #define MEMC_PRE_C_STATUS_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define MEMC_PRE_C_VSYNC_RST_W Fld(1,8,AC_MSKB1)//[8:8]
    #define MEMC_PRE_C_DISP_R Fld(1,7,AC_MSKB0)//[7:7]
    #define MEMC_PRE_C_WBUF_ATPG_CT_C Fld(1,6,AC_MSKB0)//[6:6]
    #define MEMC_PRE_C_WBUF_ATPG_CT_Y Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_PRE_C_WFIFO_OVERFLOW_CLR_C Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_PRE_C_WFIFO_OVERFLOW_CLR_Y Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_PRE_C_WDMA_DRAM_WR_C_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_PRE_C_DATA_10B_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_WDMA_DRAM_WR_Y_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_WDMA_1 (MEMC_PRE + 0x72C)
    #define MEMC_PRE_C_WDMA_STR_ADR_Y Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_PRE_WDMA_2 (MEMC_PRE + 0x730)
    #define MEMC_PRE_C_WDMA_STR_ADR_C Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_PRE_WDMA_5 (MEMC_PRE + 0x73C)
    #define MEMC_PRE_C_STA_WDMA_STATE_C Fld(1,19,AC_MSKB2)//[19:19]
    #define MEMC_PRE_C_STA_WDMA_STATE_Y Fld(1,18,AC_MSKB2)//[18:18]
    #define MEMC_PRE_C_STA_WDMA_H_CNT_C Fld(8,10,AC_MSKW21)//[17:10]
    #define MEMC_PRE_C_STA_WDMA_H_CNT_Y Fld(8,2,AC_MSKW10)//[9:2]
    #define MEMC_PRE_C_STA_DRAM_REQ_C Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_STA_DRAM_REQ_Y Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_WDMA_6 (MEMC_PRE + 0x740)
    #define MEMC_PRE_C_STA_WFIFO_OVERFLOW_C Fld(1,23,AC_MSKB2)//[23:23]
    #define MEMC_PRE_C_STA_WFIFO_OVERFLOW_Y Fld(1,22,AC_MSKB2)//[22:22]
    #define MEMC_PRE_C_STA_WFIFO_UNDERFLOW_C Fld(1,21,AC_MSKB2)//[21:21]
    #define MEMC_PRE_C_STA_WFIFO_UNDERFLOW_Y Fld(1,20,AC_MSKB2)//[20:20]
    #define MEMC_PRE_C_STA_WDMA_LINE_CNT_C Fld(10,10,AC_MSKW21)//[19:10]
    #define MEMC_PRE_C_STA_WDMA_LINE_CNT_Y Fld(10,0,AC_MSKW10)//[9:0]
#define MEMC_PRE_WDMA_7 (MEMC_PRE + 0x744)
    #define MEMC_PRE_C_WDMA_DRAM_WR_EN_SEL Fld(1,26,AC_MSKB3)//[26:26]
    #define MEMC_PRE_C_WDMA_STR_ADR_C_SEL Fld(1,25,AC_MSKB3)//[25:25]
    #define MEMC_PRE_C_WDMA_STR_ADR_Y_SEL Fld(1,24,AC_MSKB3)//[24:24]
    #define MEMC_PRE_C_OVERFLOW_CLR_C Fld(1,23,AC_MSKB2)//[23:23]
    #define MEMC_PRE_C_OVERFLOW_CLR_Y Fld(1,22,AC_MSKB2)//[22:22]
    #define MEMC_PRE_C_UNDERFLOW_CLR_C Fld(1,21,AC_MSKB2)//[21:21]
    #define MEMC_PRE_C_UNDERFLOW_CLR_Y Fld(1,20,AC_MSKB2)//[20:20]
    #define MEMC_PRE_C_DRAM_FIFO_ULTRA_THR_C Fld(9,11,AC_MSKW21)//[19:11]
    #define MEMC_PRE_C_DRAM_FIFO_ULTRA_THR_Y Fld(9,2,AC_MSKW10)//[10:2]
    #define MEMC_PRE_C_DRAM_ULTRA_EN_C Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_DRAM_ULTRA_EN_Y Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_CRC_0 (MEMC_PRE + 0x748)
    #define MEMC_PRE_C_CRC_V Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_PRE_C_CRC_BOT_R_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_PRE_C_CRC_BOT_L_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_PRE_C_CRC_TOP_R_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_CRC_TOP_L_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_CRC_1 (MEMC_PRE + 0x74C)
    #define MEMC_PRE_C_CRC_V_START Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_PRE_C_CRC_H_START Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_CRC_2 (MEMC_PRE + 0x750)
    #define MEMC_PRE_C_CRC_V_END Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_PRE_C_CRC_H_END Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_CRC_3 (MEMC_PRE + 0x754)
    #define MEMC_PRE_C_CRC_OUT_READY_V Fld(1,31,AC_MSKB3)//[31:31]
    #define MEMC_PRE_C_CRC_OUT_READY_H Fld(1,30,AC_MSKB3)//[30:30]
    #define MEMC_PRE_C_CRC_V_MASK Fld(10,20,AC_MSKW32)//[29:20]
    #define MEMC_PRE_C_CRC_C_MASK Fld(10,10,AC_MSKW21)//[19:10]
    #define MEMC_PRE_C_CRC_Y_MASK Fld(10,0,AC_MSKW10)//[9:0]
#define MEMC_PRE_CRC_4 (MEMC_PRE + 0x758)
    #define MEMC_PRE_C_CRC_OUT_H Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_PRE_CRC_5 (MEMC_PRE + 0x75C)
    #define MEMC_PRE_C_CRC_OUT_V Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_PRE_CRC_6 (MEMC_PRE + 0x760)
    #define MEMC_PRE_C_CRC_CHECK_SUM_MODE Fld(1,1,AC_MSKB0)//[1:1]
#define MEMC_PRE_DUMP_0 (MEMC_PRE + 0x764)
    #define MEMC_PRE_C_STA_WDMA_HEAD_ADDR_Y Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_PRE_DUMP_1 (MEMC_PRE + 0x768)
    #define MEMC_PRE_C_STA_WDMA_HEAD_ADDR_C Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_PRE_PATGEN_0 (MEMC_PRE + 0x774)
    #define MEMC_PRE_C_PATGEN_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define MEMC_PRE_C_YPAT2 Fld(4,27,AC_MSKB3)//[30:27]
    #define MEMC_PRE_C_YPAT1 Fld(4,23,AC_MSKW32)//[26:23]
    #define MEMC_PRE_C_PAT_DUTY_CYCLE Fld(5,18,AC_MSKB2)//[22:18]
    #define MEMC_PRE_C_LEFT_SIDE Fld(1,17,AC_MSKB2)//[17:17]
    #define MEMC_PRE_C_ANGLE_SEL Fld(3,14,AC_MSKW21)//[16:14]
    #define MEMC_PRE_C_FREQ_SEL Fld(3,11,AC_MSKB1)//[13:11]
    #define MEMC_PRE_C_HOR_LINE_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define MEMC_PRE_C_COLOR_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define MEMC_PRE_C_PAT_MODE Fld(2,6,AC_MSKB0)//[7:6]
    #define MEMC_PRE_C_FREERUN_SPEED Fld(4,2,AC_MSKB0)//[5:2]
    #define MEMC_PRE_C_FREERUN_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_BND_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_PATGEN_1 (MEMC_PRE + 0x778)
    #define MEMC_PRE_C_BND_H Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_PRE_C_BND_W Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_PRE_PATGEN_2 (MEMC_PRE + 0x77C)
    #define MEMC_PRE_C_INPTG_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_PRE_C_3D_MODE Fld(2,1,AC_MSKB0)//[2:1]
    #define MEMC_PRE_C_3D_INV Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_INPUT_MEASURE_0 (MEMC_PRE + 0x780)
    #define MEMC_PRE_C_CLR_INPUT_MEASURE Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_PRE_INPUT_MEASURE_1 (MEMC_PRE + 0x784)
    #define MEMC_PRE_C_INPUT_HACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_PRE_C_INPUT_HTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_PRE_INPUT_MEASURE_2 (MEMC_PRE + 0x788)
    #define MEMC_PRE_C_INPUT_VACTIVE Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_PRE_C_INPUT_VTOTAL Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_PRE_PREULTRA_0 (MEMC_PRE + 0x790)
    #define DA_WR_PREULTRA_ASSERT_THR_Y Fld(9,0,AC_MSKW10)//[8:0]
    #define DA_WR_PREULTRA_RELEASE_THR_Y Fld(9,16,AC_MSKW32)//[24:16]
#define MEMC_PRE_PREULTRA_1 (MEMC_PRE + 0x798)
    #define DA_WR_PREULTRA_ASSERT_THR_C Fld(9,0,AC_MSKW10)//[8:0]
    #define DA_WR_PREULTRA_RELEASE_THR_C Fld(9,16,AC_MSKW32)//[24:16]
#define MEMC_PRE_ULTRA_0 (MEMC_PRE + 0x78C)
    #define DA_WR_ULTRA_ASSERT_THR_Y Fld(9,0,AC_MSKW10)//[8:0]
    #define DA_WR_ULTRA_RELEASE_THR_Y Fld(9,16,AC_MSKW32)//[24:16]
#define MEMC_PRE_ULTRA_1 (MEMC_PRE + 0x794)
    #define DA_WR_ULTRA_ASSERT_THR_C Fld(9,0,AC_MSKW10)//[8:0]
    #define DA_WR_ULTRA_RELEASE_THR_C Fld(9,16,AC_MSKW32)//[24:16]
   
#define MEMC_PRE_CTRL_00 (MEMC_PRE + 0x9EC)
    #define MEMC_PRE_C_IN_V_TOTAL Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_PRE_C_IN_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_CTRL_01 (MEMC_PRE + 0x9F0)
    #define MEMC_PRE_C_IN_V_ACTIVE Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_PRE_C_IN_H_ACTIVE Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_PRE_CTRL_02 (MEMC_PRE + 0x9F4)
    #define MEMC_PRE_C_CMQ_STR_SEL Fld(1,14,AC_MSKB1)//[14:14]
    #define MEMC_PRE_C_STA_PD_INFO Fld(3,11,AC_MSKB1)//[11:13]
    #define MEMC_PRE_C_SW_RST Fld(4,7,AC_MSKW10)//[10:7]
    #define MEMC_PRE_C_DB_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define MEMC_PRE_C_REPEAT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_PRE_C_REPEAT_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_PRE_C_REPEAT_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_PRE_C_DBG_SEL Fld(3,0,AC_MSKB0)//[2:0]
#define MEMC_PRE_RESERVED (MEMC_PRE + 0x9F8)
    #define MEMC_PRE_C_RESERVED Fld(32,0,AC_FULLDW)//[31:0]
    #define MEMC_PRE_C_VSYNC_R_CLR         Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_PRE_C_VYSNC_R_EN          Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_PRE_C_CMQ_STR_SEL_Phoenix Fld(1,1,AC_MSKB0)//[1:1]//ECO for WDMA triger cmq num + 1 0:write end 1:rise
    #define MEMC_PRE_ES1_SRAM_FIFO_SEL Fld(1,0,AC_MSKB0) //[0:0]
#define MEMC_PRE_ATPG (MEMC_PRE + 0x9FC)
    #define MEMC_PRE_C_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_PRE_C_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]



#endif