/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
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 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
 * are met:
 *
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/*****************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: drv_dsync.h $ 
 *
 * Project:
 * --------
 *   MT8205
 *
 * Description:
 * ------------
 *   Digital Sync Processor Driver
 *   
 * Author:
 * -------
 *   Ci wu
 *
 * Last changed:
 * ------------- 
 * $Author: brianpc.huang $ 
 *
 * $Modtime: 04/05/26 7:10p $  
 *
 * $Revision: #1 $
 ****************************************************************************/
#ifndef _DRV_DSYNC_H_
#define _DRV_DSYNC_H_

#include "typedef.h"
#include "hw_vdoin.h"
#include "hw_dsync.h"

// Macro declaration
#define fgDSHPol()  	(IO32ReadFldAlign(STA_SYNC1_03,HSYNC_P))
#define fgDSVPol()  	(IO32ReadFldAlign(STA_SYNC1_03,VSYNC_P))
#define fgDSHAct() 	 (IO32ReadFldAlign(STA_SYNC1_03,HSYNC_ACT))
#define fgDSCAct()  	(IO32ReadFldAlign(STA_SYNC1_03,CSYNC_ACT))
//#define fgDSDEAct() 	(bReadVDOIN(STA2_12,BANK0)&0x80)
#define fgDSVAct()	 (IO32ReadFldAlign(STA_SYNC1_03,VSYNC_ACT))
#define fgDSFldType() (IO32ReadFldAlign(STA_SYNC1_03,FIELD))

//#define vDSSetSSync()	vWriteVDOIN(DSYNC01,BANK3,VS_TO_VSOUT|HS_TO_HS|VS_TO_VS|HS_TO_CS)
//#define vDSSetCSync()	vWriteVDOIN(DSYNC01,BANK3,VSOUTX_TO_VSOUT|HS_TO_HS|VSOUT_TO_VS|HS_TO_CS)
//#define vDSSetSOGSync()	vWriteVDOIN(DSYNC01,BANK3,VSOUTX_TO_VSOUT|CS_TO_HS|VSOUT_TO_VS|CS_TO_CS)

#define vDSSetCLKMeasure() vIO32Write4BMsk(DSYNC_08, 0 ,Fld2Msk32(HLEN_STA_SELECT))
#define vDSSetPIXMeasure() vIO32Write4BMsk(DSYNC_08, Fld2Msk32(HLEN_STA_SELECT) ,Fld2Msk32(HLEN_STA_SELECT))

// Function declaration
extern UINT16 wDSHtotalMeasure(void) ;
extern UINT16 wDSVtotalMeasure(void) ;
//extern void vDrvDsyncSetFieldDet(void) ;
//extern void vDrvDsyncSetBDMask(UINT16 wVTOTAL, UINT8 bInterlace) ;

#endif
