#ifndef _HW_IFPLL_H_
#define _HW_IFPLL_H_

//Page HISTORY
#define IO_IFPLL_BASE (IO_VIRT + 0x61000)

//Page TABLE
// IFPLL
#define REG_IFPLL_CFG0 (IO_IFPLL_BASE + 0x500)
    #define FLD_RG_IFPLL_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_IFPLL_FBKDIV Fld(7,24,AC_MSKB3)//[30:24]
    #define FLD_RG_IFPLL_DDSFBK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_IFPLL_RLH_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_IFPLL_FBKSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_RG_IFPLL_PREDIV Fld(2,18,AC_MSKB2)//[19:18]
    #define FLD_RG_IFPLL_POSDIV Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_RG_IFPLL_IC Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_RG_IFPLL_IR Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_RG_IFPLL_BP Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_RG_IFPLL_BC Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_RG_IFPLL_BR Fld(2,0,AC_MSKB0)//[1:0]
#define REG_IFPLL_CFG1 (IO_IFPLL_BASE + 0x504)
    #define FLD_RG_IFPLL_AUTOK_LOAD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_IFPLL_DIVEN Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_IFPLL_AUTOK_KS Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_IFPLL_AUTOK_KF Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_RG_IFPLL_AUTOK_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_IFPLL_BAND Fld(7,16,AC_MSKB2)//[22:16]
    #define FLD_RG_IFPLL_MONCK_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_RG_IFPLL_MONVC_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_RG_IFPLL_MONREF_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RG_IFPLL_VOD_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_IFPLL_BIAS_LPF_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_RG_IFPLL_BIAS_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_RG_IFPLL_RESERVE Fld(10,0,AC_MSKW10)//[9:0]
#define RGS_IFPLL_CFG0 (IO_IFPLL_BASE + 0x508)
    #define FLD_RGS_PLL_AUTOK_BAND Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_RGS_PLL_AUTOK_PASS Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RGS_PLL_AUTOK_FAIL Fld(1,23,AC_MSKB2)//[23:23]

// IFTOP
#define REG_IFTOP_CFG0 (IO_IFPLL_BASE + 0x600)
    #define FLD_RG_DMOD_PWD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_DMOD_BIAS Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_RG_DMOD_INSEL Fld(4,0,AC_MSKB0)//[3:0]
#define REG_IFTOP_CFG1 (IO_IFPLL_BASE + 0x604)
    #define FLD_RG_DMTOP_BG_PWD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_DMTOP_XTAL_GATING Fld(8,0,AC_FULLB0)//[7:0]
#define REG_IFTOP_CFG2 (IO_IFPLL_BASE + 0x608)
    #define FLD_RG_DMTOP_REV1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_RG_DMTOP_REV0 Fld(16,0,AC_FULLW10)//[15:0]
    
#endif /* _HW_IFPLL_H_ */

