/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*-----------------------------------------------------------------------------
 * Copyright (c) 2005, MediaTek, Inc.
 * All rights reserved.
 *
 * Unauthorized use, practice, perform, copy, distribution, reproduction,
 * or disclosure of this information in whole or in part is prohibited.
 *-----------------------------------------------------------------------------
 *
 * $Author: binghe.li $
 * $Date: 2016/05/12 $
 * $RCSfile: drv_mjc_sys.h $
 * $Revision: #4 $
 *
 *----------------------------------------------------------------------------*/

#ifndef _DRV_MJC_SYS_H_
#define _DRV_MJC_SYS_H_

/*----------------------------------------------------------------------------*
 * Header Files
*----------------------------------------------------------------------------*/
#include "drv_mjc_hw.h"
#include "typedef.h"

/*====================End  Header Files ============================*/

/*----------------------------------------------------------------------------*
 * Definitions 
 *----------------------------------------------------------------------------*/
//#define MJC_FPGA_V7_ARM11_TEST                    (0)
#define MJC_REG_TBL_END 0xffffffff
#define MJC_BUFFER_NUM     9 //CMQ using total buffer numbers


// mjc align

#define MJC_ALIGN_MASK(VAL, MSK) (((VAL) + (MSK)) & (~(MSK)))
#define MJC_ALIGN_64BYTE(val) (((val) + 0x0000003f) & (~0x0000003f))
#define MJC_ALIGN_256_CEIL(val) ALIGN_MASK((val), 255)
#define MJC_ALIGN_128_CEIL(val) ALIGN_MASK((val), 127)
#define MJC_ALIGN_64_CEIL(val) ALIGN_MASK((val), 63)
#define MJC_ALIGN_32_CEIL(val) ALIGN_MASK((val), 31)
#define MJC_ALIGN_16_CEIL(val) ALIGN_MASK((val), 15)
#define MJC_ALIGN_8_CEIL(val) ALIGN_MASK((val), 7)
#define MJC_ALIGN_4_CEIL(val) ALIGN_MASK((val), 3)
#define MJC_ALIGN_2_CEIL(val) ALIGN_MASK((val), 1)

/*====================End  Definitions ============================*/


/*----------------------------------------------------------------------------*
 *  typedef Struct
 *----------------------------------------------------------------------------*/
typedef struct
{
    UINT8 	u1BufferNum;         // use total buffer number
    UINT8 	u18BitMode;         // dram in 8 bit or 10 bit mode
    UINT32	u4StartAddrY1;     // fbm allocate buffer start Physic address
    UINT32	u4SizeY1;    
    UINT32	u4StartAddrY2; 
    UINT32	u4SizeY2;
    UINT32	u4StartAddrY3; 
    UINT32	u4SizeY3;
    UINT32	u4StartAddrMV;
    UINT32	u4SizeMV;
    UINT32	u4StartAddrC1; 
    UINT32	u4SizeC1;
    UINT32	u4StartAddrC2; 
    UINT32	u4SizeC2;
    UINT32	u4StartAddrC3;
    UINT32	u4SizeC3;
    UINT32	u4Width;       // per buffer width
    UINT32	u4Height;     // per buffer heigh
} MJC_DRAM_CONFIG_T;

typedef struct
{
    UINT8 u1W10bitMode;         // set 10 bit or 8 bit mode
    UINT8 u1RepeatEn;          // WDMA repeat mode on off
    UINT8 u1RepeatMode;       // repeat mode select 
    UINT8 u1WAddrSelect;     // WDMA dram address from CMQ or register
    UINT8 u1WTriggerMode;   //Set WDMA trigger cmq signal
    UINT8 u1W420En;        // WDMA  444 to 420 on or off
    UINT8 u1WYUVEn;       //  WDMA  RGB to YUV on or off
    
}MJC_WDMA_T;

typedef struct
{
    UINT8 u1R10bitMode;   // set 10 bit or 8 bit mode
    UINT8 u1RAddrSelect; // RDMA dram address from CMQ or register
    UINT8 u1R444En;     // 420 to 444 enable
    UINT8 u1RGBEn;     // YUV to RGB enable
    UINT32 u4RVbp;    //vsync back proch 
    UINT32 u4RVDisp; // vsync back proch + v blanking
    
}MJC_RDMA_T;

typedef enum
{
    MJC_OUT_MODE_ORI = 0,
    MJC_OUT_MODE_MC,
    MJC_OUT_MODE_ORI_MC,
    MJC_OUT_MODE_DEBUG,
    MJC_OUT_MODE_MAX
}MJC_OUT_MODE;

typedef struct
{
    UINT8 u1BlkMode;
    UINT8 u1VsrchMode;
    UINT8  u1ActM3En;
    UINT8  u1ActM2En;
    UINT8  u1ActFilmMode;
    UINT8  u1ActIntpDen;
    UINT8  u1InitLoadMode;
    UINT8  u1ActPairFirst;
    UINT8  u1ActRescanEn;
    UINT8  u1ActBgmvKeep;
    UINT8  u1MvReadZeroPv;
    UINT8  u1MvReadZeroCu;
    UINT8  u1MvReadZeroBi;    
    UINT8  u1MvReadZeroTd;
    UINT8  u1Seq1stFrm;
    UINT32 u4PWidth;      
    UINT32 u4PHeight;     
    UINT32 u4RBlkPitch;
    UINT32 u4RYPitch;
    UINT32 u4RCbPitch;
    UINT32 u4RCrPitch;
    UINT32 u4WFrmPitch;
    UINT32 u4ActPbndDn;
    UINT32 u4ActPbndRt;
    UINT32 u4ActLpbDn;
    UINT32 u4ActLpbdRt;
}MJC_CORE_FS_T;

typedef struct
{
    UINT32 u1ActFbY1Addr       : 4; // LSB
    UINT32 u1ActFbC1Addr       : 4;
    UINT32 u1ActFbY2Addr       : 4;
    UINT32 u1ActFbC2Addr       : 4;
    UINT32 u1ActFbY3Addr       : 4;
    UINT32 u1PldFbY1Addr       : 4;
    UINT32 u1PldFbC1Addr       : 4;
    UINT32 u1PldFbY2Addr       : 4; // MSB
} MJC_CMQ_REG00_T;

typedef union
{
    UINT32 u4Cmq00Data;
    MJC_CMQ_REG00_T arCmq00;
} MJC_CMQ_REG00_U;

typedef struct
{
    UINT32 u1PldFbC2Addr       : 4; // LSB
    UINT32 u1PldFbY3Addr       : 4;
    UINT32 u1MvBiWrAddr        : 4;
    UINT32 u1MvBiRdAddr        : 4;
    UINT32 u1MvCuWrAddr        : 4;
    UINT32 u1MvCuRdAddr        : 4;
    UINT32 u1MvPvRdAddr        : 4;
    UINT32 u1MvTdWrAddr        : 4; // MSB
} MJC_CMQ_REG01_T;

typedef union
{
    UINT32 u4Cmq01Data;
    MJC_CMQ_REG01_T arCmq01;
} MJC_CMQ_REG01_U;

typedef struct
{
    UINT32 u1MvTdRdAddr        : 4; // LSB
    UINT32 u1MvReadZeroPv      : 1;
    UINT32 u1MvReadZeroCu      : 1;
    UINT32 u1MvReadZeroBi      : 1;
    UINT32 u1MvReadZeroTd      : 1;
    UINT32 u1ActMePairFirst    : 1;
    UINT32 u1ActMePosOthrSel   : 2;
    UINT32 u1ActMeIdxToggle    : 1;
    UINT32 u1ActMe2460PreBi    : 1;
    UINT32 u1ActMe2460PreBiDly : 1;
    UINT32 u1PldMe2460PreBi    : 1;
    UINT32 u1ActMvExpFlag      : 1;
    UINT32 u1ActBgMvKeep       : 1;
    UINT32 u1ActMe3En          : 1;
    UINT32 u1ActMe2En          : 1;
    UINT32 u1ActMc2xMode       : 1;
    UINT32 u1Fs02NoCtrl        : 12; // MSB    
} MJC_CMQ_REG02_T;

typedef union
{
    UINT32 u4Cmq02Data;
    MJC_CMQ_REG02_T arCmq02;
} MJC_CMQ_REG02_U;
typedef struct
{
    UINT32 u1ActIntpDen        : 4; // LSB
    UINT32 u1ActIntpNum1       : 5;
    UINT32 u1ActIntpNum2       : 5;
    UINT32 u1ActPairFirst      : 1;
    UINT32 u1ActPairFirstDly   : 1;
    UINT32 u1PldPairFirst      : 1;
    UINT32 u1ActRescanFrmEn    : 1;
    UINT32 u1PldRescanFrmEn    : 1;
    UINT32 u1ActMeOnlyFrm      : 1;
    UINT32 u1PldMeOnlyFrm      : 1;
    UINT32 u1ActMcOriEn        : 1;
    UINT32 u1Fs03NoCtrl        : 10; // MSB
} MJC_CMQ_REG03_T;

typedef union
{
    UINT32 u4Cmq03Data;
    MJC_CMQ_REG03_T arCmq03;
} MJC_CMQ_REG03_U;
typedef struct
{
    UINT32 u2ActMv1Num         : 8; // LSB
    UINT32 u2ActMc1NumRgn0     : 8;
    UINT32 u2ActMc2NumRgn0     : 8;
    UINT32 u2Fs04NoCtrl        : 8; // MSB
} MJC_CMQ_REG04_T;

typedef union
{
    UINT32 u4Cmq04Data;
    MJC_CMQ_REG04_T arCmq04;
} MJC_CMQ_REG04_U;

typedef struct
{
    UINT32 u2ActMc2NumRgn1     : 8; // LSB
    UINT32 u2ActMc2NumRgn2     : 8;
    UINT32 u2ActMv2Num         : 8; 
    UINT32 u2Fs05NoCtrl        : 8; // MSB
} MJC_CMQ_REG05_T;

typedef union
{
    UINT32 u4Cmq05Data;
    MJC_CMQ_REG05_T arCmq05;
} MJC_CMQ_REG05_U;

typedef struct
{
    UINT32 u2ActMc1NumRgn1     : 8; // LSB
    UINT32 u2ActMc1NumRgn2     : 8;
    UINT32 u2Fs06NoCtrl        : 16; // MSB
} MJC_CMQ_REG06_T;

typedef union
{
    UINT32 u4Cmq06Data;
    MJC_CMQ_REG06_T arCmq06;
} MJC_CMQ_REG06_U;
typedef struct
{
    UINT32 u1RdmaReadYAddr     : 4; // LSB
    UINT32 u1RdmaReadCAddr     : 4;
    UINT32 u1WdmaWriteYAddr    : 4; 
    UINT32 u1WdmaWriteCAddr    : 4;
    UINT32 u1RdmaReadEn        : 1;
    UINT32 u1WdmaWrite         : 1;
    UINT32 u2Fs07NoCtrl        : 14; // MSB
} MJC_CMQ_REG07_T;

typedef union
{
    UINT32 u4Cmq07Data;
    MJC_CMQ_REG07_T arCmq07;
} MJC_CMQ_REG07_U;

typedef struct
{
   MJC_CMQ_REG00_U unCmq00;
   MJC_CMQ_REG01_U unCmq01;
   MJC_CMQ_REG02_U unCmq02;
   MJC_CMQ_REG03_U unCmq03;
   MJC_CMQ_REG04_U unCmq04;
   MJC_CMQ_REG05_U unCmq05;
   MJC_CMQ_REG06_U unCmq06;
   MJC_CMQ_REG07_U unCmq07;
}MJC_CMQ_T;
typedef struct
{
    MJC_WDMA_T   rWdma;
    MJC_RDMA_T   rRdma;
    MJC_CMQ_T    rCmq;
    MJC_CORE_FS_T   rCoreFS;
    MJC_DRAM_CONFIG_T rMemory;
}MJC_DRV_HANDLE_T;

typedef enum
{
    FILM_DETECT_32322 = 0,
    FILM_DETECT_21111,
    FILM_DETECT_22,
    FILM_DETECT_32,
    FILM_DETECT_11,
    FILM_DETECT_MAX
}FILM_DETECT_MODE;

enum
{
    E_Y_ADDR = 0,
    E_C_ADDR = 1,
};
enum
{
    E_MV_BI_ADDR = 0,
    E_MV_TD_ADDR = 1,
	E_MV_CU_WR_ADDR = 2,
	E_MV_CU_RD_ADDR = 3,
    E_MV_PV_ADDR = 4    
};
// 0 : Y1 address 1: c1 address 2: v1 address 3:y2 address 4: c2 address 5 :v2 address  6: y3 address

enum
{
    E_CORE_ACT_Y1_ADDR = 0,
    E_CORE_ACT_C1_ADDR = 1,
	E_CORE_ACT_V1_ADDR = 2,
	E_CORE_ACT_Y2_ADDR = 3,
    E_CORE_ACT_C2_ADDR = 4,
	E_CORE_ACT_V2_ADDR = 5,
    E_CORE_ACT_Y3_ADDR = 6    
};
enum
{
    E_CORE_PLD_Y1_ADDR = 0,
    E_CORE_PLD_C1_ADDR = 1,
	E_CORE_PLD_V1_ADDR = 2,
	E_CORE_PLD_Y2_ADDR = 3,
    E_CORE_PLD_C2_ADDR = 4,
	E_CORE_PLD_V2_ADDR = 5,
    E_CORE_PLD_Y3_ADDR = 6    
};
typedef enum
{
    CMQ_NONE      = 0,
    CMQ_32322_TO_60,
    CMQ_21111_TO_60,
    CMQ_22_TO_60,
    CMQ_32_TO_60, 
    CMQ_24_TO_48  ,
    CMQ_24_TO_60  ,
    CMQ_25_TO_50  ,
    CMQ_25_TO_60  ,
    CMQ_30_TO_60  ,
    CMQ_50_TO_50  ,
    CMQ_50_TO_60  ,
    CMQ_60_TO_60  ,
    CMQ_22_TO_120 ,
    CMQ_32_TO_120 ,
    CMQ_24_TO_120 ,
    CMQ_25_TO_100 ,
    CMQ_25_TO_120 ,
    CMQ_30_TO_120 ,
    CMQ_48_TO_120 ,
    CMQ_50_TO_100 ,
    CMQ_50_TO_120 ,
    CMQ_60_TO_120 ,
    CMQ_120_TO_120,
    CMQ_DYNA_MAX
}CMQ_DYNA_MODE;

typedef enum
{
     BYP_MJC_BY_FBM        = 0,
     BYP_MJC_BY_CLI        = 1,
     BYP_MJC_BY_APP        = 2,
     BYP_MJC_BY_GAME_MODE  = 3,
     BYP_MJC_BY_MJC        = 4,
     BYP_MJC_BY_EFUSE      = 5,
     BYP_MJC_BY_DEFINE     = 6,
     BYP_MJC_BY_MAX        = 7
}BYP_MJC_MODULE;


typedef enum
{
    RESET_RDMA_DONE = 0,
    RESET_RDMA_DONE_2,
    RESET_RDMA_OFF,
    ENABLE_CORE_IP,
    RESET_RDMA_ON,
    RESET_RDMA_ON_2
}RESET_RDMA_FLOW;

/*====================typedef Struct=====================*/


/*----------------------------------------------------------------------------*
 * Global/Static variables
 *----------------------------------------------------------------------------*/
extern UINT8 fgIsMJCFlimMode ;
extern MJC_DRAM_CONFIG_T arMJCDramConfig;
extern UINT8 fgSetCmqForceChg;
extern FILM_DETECT_MODE eCurFlimMode;
extern FILM_DETECT_MODE ePreFlimMode;
extern CMQ_DYNA_MODE u1CMQDynType;
extern CMQ_DYNA_MODE u1MEMCModeStart;




/*====================End Global/Static variables =====================*/


/*----------------------------------------------------------------------------*
 * Function Members
 *----------------------------------------------------------------------------*/ 

void vDrvMJCSrmCb(UINT32 u4VdpId, UINT32 u4Mode, UINT32 u4PDSize, UINT32 u4SramMode);
UINT8 u1DrvMJCGetFrmDelay10x(void);
void vDrvMJCSetModeChangeTrig(void);
UINT8 u1DrvMJCIsOnOff(void);
UINT32 fgDrvMJCGetFlipMirror(void);
void vDrvMJCModeChangeDone(void);
void vDrvMJCInit(UINT8 bForceInit);
UINT8  u1MjcIsInit(void);
void MJC_SetFilmMode(BOOL fgOnOff);
UINT32 u4DrvMJCGetFilmModeStatus(void);
void vDrvMJCSetAllCMQSWStart(void);
void vDrvMJCMainloop(void);
UINT8 fgDrvMJCIsMEMCSupported(VOID);
void vDrvMJCDumpDramAllocate(void);
UINT8 vDrvMJCBufferInit(void);
void vDrvMJCBypassOnOff(BYP_MJC_MODULE eModule,UINT8 u1OnOff);
UINT8 vDrvMJCGetBypassVariable(BYP_MJC_MODULE eModule);
void vDrvMJCReSyncCMQ(void);
void eDrvMJCCheckRepeatInfo(void);
void vDrvMJCGameMode(UINT8 u1OnOff);
UINT8 u1DrvMJCInPipPopMode(void);
void vDrvMJCCmqDynSetConfig(UINT8 u1CmqNum, UINT8 u1BufferNum,UINT8 u1TotalCmqNum, UINT8 u1Reset,UINT8 u1WDMASet,UINT8 u1RDMASet);
void vDrvMJCCmqRDMA60to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA25to60Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA50to60Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA50to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA25to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA22to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA32to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA30to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA24to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA32to60Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA22to60Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA60to60Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqRDMA120to120Cal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1RDMASet,UINT8 u1Type);
void vDrvMJCCmqWDMACal(UINT8 u1CmqNum,UINT8 u1BufferNum,UINT8 u1TotalCmqNum,UINT8 u1Reset,UINT8 u1WDMASet,UINT8 u1Type);
void vDrvMJCChange10BitMode(UINT8 u1BitMode);
void vDrvMJCBufferConfig(MJC_DRAM_CONFIG_T * prDramcfg);
void vDrvMJCSetForceCmqChange( UINT8 u1chg);
UINT8 u1DrvMJCGetForceCmqChange(void);
void vDrvMJCSetOutputMode( UINT8 u1mode);
UINT8 vDrvMJCGetOutputMode(void);
void vDrvMJCFlimModeProc(void);
UINT8 vDrvMJCCmqConfig(UINT8 u1InputFr);
void vDrvMJCSetFilmDetEnable(UINT8 u1Onoff);
void vDrvMJCForceFilmDetMode(UINT8 u1FilmMode);
void vDrvMJCForceSetFilmMode(UINT8 u1FilmMode);
void vDrvMJCSetBypFbck(UINT8 u1Onoff);
void vDrvMJCSetBypDSR(UINT8 u1Onoff);
void vDrvMJCSetFreeze(UINT8 u1Onoff);
void vDrvMJCSetPatternGen(UINT32 u4InOut, UINT32 u4OnOff);
void vDrvMJCResetRDMA(void);
void vDrvMJCSetRstCoreCnt(UINT8 u1RstRDMA, UINT8 u1RstPost);
void vDrvMJCUpdateCMQInSOF(void);
void vDrvMJCCheckReadWriteCtrl(void);
void vDrvMJCRstCoreLoop(void);
UINT8 u1DrvIsBypassPathToMJCPost(void);
void vDrvPostSetBypassPostTimgen(void);
#ifdef CC_SUPPORT_STR
void vDrvMJCSuspend(void);
void vDrvMJCResume(void);
#endif

UINT8 vDrvMJCCmqGetRDMACnt(void);

void vDrvMJCSetSWCandenceEnable(UINT8 bEn);
UINT8 vDrvMJCGetSWCandenceEnable(void);


#ifdef DRAM_DUMP_INOUT
EXTERN INT32 NptvDumpOutfromMJC(const char *PathName);
EXTERN INT32 NptvDumpIntoMJC(const char *PathName);
EXTERN INT32 NptvMJCDumpExit(void);
#endif

/*====================End  Function Members =======================*/
#endif
