/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/


/*****************************************************************************
 *
 * Filename:
 * ---------
 *   $Workfile: hw_lc_bitplus.h $
 *
 * Project:
 * --------
 *   MT5893
 *
 * Description:
 * ------------
 *   local contrast&bitplus PQ register definition
 *
 * Author:
 * -------
 *   zhidan wu
 *
 * Last changed:
 * -------------
 * $Author: brianpc.huang $
 *
 * $Modtime: 19/01/2017 1:22p $
 *
 * $Revision: #1 $
****************************************************************************/

#ifndef _HW_LC_BITPLUS_H_
#define _HW_LC_BITPLUS_H_

#include "hw_vdoin.h"


#define IO_LCCTST_BASE (VDOIN_LCCSTS_BASE+0x6000)//0x10046000

//Page POSTPROC_AAL
#define LCC_DISP_AAL_EN (IO_LCCTST_BASE + 0x000)
    #define LCC_AAL_EN Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_RESET (IO_LCCTST_BASE + 0x004)
    #define LCC_AAL_RESET Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_INTEN (IO_LCCTST_BASE + 0x008)
    #define LCC_OF_END_INT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_IF_END_INT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_INTSTA (IO_LCCTST_BASE + 0x00C)
    #define LCC_OF_END_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_IF_END_INT Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_STATUS (IO_LCCTST_BASE + 0x010)
    #define LCC_HANDSHAKE Fld(26,4,AC_MSKDW)//[29:4]
    #define LCC_OF_UNFINISH Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_IF_UNFINISH Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_CFG (IO_LCCTST_BASE + 0x020)
    #define LCC_CHKSUM_SEL Fld(2,29,AC_MSKB3)//[30:29]
    #define LCC_CHKSUM_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define LCC_FRAME_DONE_DELAY Fld(8,16,AC_FULLB2)//[23:16]
    #define LCC_IGNORE_OUT_READY Fld(1,7,AC_MSKB0)//[7:7]
    #define LCC_BLK_HIST_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define LCC_AAL_CG_DISABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define LCC_AAL_ENGINE_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_RELAY_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_INPUT_COUNT (IO_LCCTST_BASE + 0x024)
    #define LCC_INP_LINE_CNT Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_INP_PIX_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_OUTPUT_COUNT (IO_LCCTST_BASE + 0x028)
    #define LCC_OUTP_LINE_CNT Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_OUTP_PIX_CNT Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_CHKSUM (IO_LCCTST_BASE + 0x02C)
    #define LCC_CHKSUM Fld(32,0,AC_FULLDW)//[31:0]
#define LCC_DISP_AAL_SIZE (IO_LCCTST_BASE + 0x030)
    #define LCC_HSIZE Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_VSIZE Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_DUMMY_REG (IO_LCCTST_BASE + 0x0C0)
    #define LCC_DUMMY_REG Fld(32,0,AC_FULLDW)//[31:0]
#define LCC_DISP_AAL_SRAM_CFG (IO_LCCTST_BASE + 0x0C4)
    #define LCC_SRAM_WREQ_EN Fld(2,20,AC_MSKB2)//[21:20]
    #define LCC_SRAM_RREQ_EN Fld(4,16,AC_MSKB2)//[19:16]
    #define LCC_FORCE_HIST_SRAM_INT Fld(1,6,AC_MSKB0)//[6:6]
    #define LCC_FORCE_HIST_SRAM_APB Fld(1,5,AC_MSKB0)//[5:5]
    #define LCC_FORCE_HIST_SRAM_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define LCC_HIST_SRAM_READ_DLY Fld(1,2,AC_MSKB0)//[2:2]
    #define LCC_HIST_SRAM_PP_HALT Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_HIST_BIN_TYPE Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_SRAM_STATUS (IO_LCCTST_BASE + 0x0C8)
    #define LCC_HIST_SRAM_RRDY Fld(1,17,AC_MSKB2)//[17:17]
    #define LCC_HIST_SRAM_WRDY Fld(1,16,AC_MSKB2)//[16:16]
    #define LCC_RB_SRAM_PD Fld(2,12,AC_MSKB1)//[13:12]
    #define LCC_RB_HIST_SRAM_RW_ERR Fld(1,8,AC_MSKB1)//[8:8]
    #define LCC_RB_HIST_SRAM_IDX Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_SRAM_RW_IF_0 (IO_LCCTST_BASE + 0x0CC)
    #define LCC_HIST_SRAM_WADDR Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_SRAM_RW_IF_1 (IO_LCCTST_BASE + 0x0D0)
    #define LCC_HIST_SRAM_WDATA Fld(32,0,AC_FULLDW)//[31:0]
#define LCC_DISP_AAL_SRAM_RW_IF_2 (IO_LCCTST_BASE + 0x0D4)
    #define LCC_HIST_SRAM_RADDR Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_SRAM_RW_IF_3 (IO_LCCTST_BASE + 0x0D8)
    #define LCC_HIST_SRAM_RDATA Fld(32,0,AC_FULLDW)//[31:0]
#define LCC_DISP_AAL_SHADOW_CTRL (IO_LCCTST_BASE + 0x0F0)
    #define LCC_READ_WRK_REG Fld(1,2,AC_MSKB0)//[2:2]
    #define LCC_FORCE_COMMIT Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_BYPASS_SHADOW Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_ATPG (IO_LCCTST_BASE + 0x0FC)
    #define LCC_AAL_ATPG_CT Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_AAL_ATPG_OB Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DREI_PAT_GEN_SET (IO_LCCTST_BASE + 0x100)
    #define LCC_DREI_REG_PAT_TYPE Fld(8,16,AC_FULLB2)//[23:16]
    #define LCC_DREI_REG_PAT_GEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DREI_PAT_GEN_COLOR0 (IO_LCCTST_BASE + 0x108)
    #define LCC_DREI_REG_COLOR_U Fld(11,16,AC_MSKW32)//[26:16]
    #define LCC_DREI_REG_COLOR_Y Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREI_PAT_GEN_COLOR1 (IO_LCCTST_BASE + 0x10C)
    #define LCC_DREI_REG_COLOR_V Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREO_PAT_GEN_SET (IO_LCCTST_BASE + 0x130)
    #define LCC_DREO_REG_PAT_TYPE Fld(8,16,AC_FULLB2)//[23:16]
    #define LCC_DREO_REG_RAMP_EN Fld(3,8,AC_MSKB1)//[10:8]
    #define LCC_DREO_REG_GRID_SIZE Fld(4,4,AC_MSKB0)//[7:4]
    #define LCC_DREO_REG_GRID_SHOW_EN Fld(2,2,AC_MSKB0)//[3:2]
    #define LCC_DREO_REG_CURSOR_SHOW Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_DREO_REG_PAT_GEN_EN Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DREO_PAT_GEN_COLOR0 (IO_LCCTST_BASE + 0x138)
    #define LCC_DREO_REG_COLOR_U Fld(11,16,AC_MSKW32)//[26:16]
    #define LCC_DREO_REG_COLOR_Y Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREO_PAT_GEN_COLOR1 (IO_LCCTST_BASE + 0x13C)
    #define LCC_DREO_REG_BG_COLOR_Y Fld(11,16,AC_MSKW32)//[26:16]
    #define LCC_DREO_REG_COLOR_V Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREO_PAT_GEN_COLOR2 (IO_LCCTST_BASE + 0x140)
    #define LCC_DREO_REG_BG_COLOR_V Fld(11,16,AC_MSKW32)//[26:16]
    #define LCC_DREO_REG_BG_COLOR_U Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREO_PAT_GEN_POS (IO_LCCTST_BASE + 0x144)
    #define LCC_DREO_REG_POS_Y Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_DREO_REG_POS_X Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DREO_PAT_GEN_CURSOR_RB0 (IO_LCCTST_BASE + 0x148)
    #define LCC_DREO_RB_CURSOR_U Fld(11,16,AC_MSKW32)//[26:16]
    #define LCC_DREO_RB_CURSOR_Y Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREO_PAT_GEN_CURSOR_RB1 (IO_LCCTST_BASE + 0x14C)
    #define LCC_DREO_RB_CURSOR_V Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DREO_PAT_GEN_RAMP (IO_LCCTST_BASE + 0x150)
    #define LCC_DREO_REG_RAMP_H_WIDTH Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_DREO_REG_RAMP_H_STEP Fld(11,0,AC_MSKW10)//[10:0]
#define LCC_DISP_AAL_CFG_MAIN (IO_LCCTST_BASE + 0x200)
    #define LCC_DRE_OUTPUT_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define LCC_DRE_MAX_HIST_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define LCC_DRE_MAX_DIFF_MODE Fld(1,2,AC_MSKB0)//[2:2]
#define LCC_DISP_AAL_MAX_HIST_CONFIG_00 (IO_LCCTST_BASE + 0x204)
    #define LCC_MAXHIST_RGB_WEIGHT Fld(4,16,AC_MSKB2)//[19:16]
#define LCC_DISP_AAL_DRE_MAPPING_00 (IO_LCCTST_BASE + 0x3B4)
    #define LCC_DRE_MAP_BYPASS Fld(1,4,AC_MSKB0)//[4:4]
    #define LCC_DRE_MAP_RGB_WEIGHT Fld(4,0,AC_MSKB0)//[3:0]
#define LCC_DISP_AAL_DBG_CFG_MAIN (IO_LCCTST_BASE + 0x45C)
    #define LCC_SPLIT_SWAP Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_SPLIT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_WIN_X_MAIN (IO_LCCTST_BASE + 0x460)
    #define LCC_WIN_X_END Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_WIN_X_START Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_WIN_Y_MAIN (IO_LCCTST_BASE + 0x464)
    #define LCC_WIN_Y_END Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_WIN_Y_START Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_00 (IO_LCCTST_BASE + 0x468)
    #define LCC_ACT_WIN_X_END Fld(13,13,AC_MSKDW)//[25:13]
    #define LCC_ACT_WIN_X_START Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_01 (IO_LCCTST_BASE + 0x46C)
    #define LCC_DRE_BLK_Y_NUM Fld(5,5,AC_MSKW10)//[9:5]
    #define LCC_DRE_BLK_X_NUM Fld(5,0,AC_MSKB0)//[4:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_02 (IO_LCCTST_BASE + 0x470)
    #define LCC_DRE_BLK_HEIGHT Fld(13,13,AC_MSKDW)//[25:13]
    #define LCC_DRE_BLK_WIDTH Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_03 (IO_LCCTST_BASE + 0x474)
    #define LCC_DRE_PXL_DIFF_SLOPE_FOR_FLAT_PXL Fld(8,24,AC_FULLB3)//[31:24]
    #define LCC_DRE_PXL_DIFF_TH_FOR_FLAT_PXL Fld(8,16,AC_FULLB2)//[23:16]
    #define LCC_DRE_PXL_DIFF_SLOPE Fld(8,8,AC_FULLB1)//[15:8]
    #define LCC_DRE_PXL_DIFF_TH Fld(8,0,AC_FULLB0)//[7:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_04 (IO_LCCTST_BASE + 0x478)
    #define LCC_DRE_FLAT_LENGTH_SLOPE Fld(10,13,AC_MSKW21)//[22:13]
    #define LCC_DRE_FLAT_LENGTH_TH Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_DRE_CHROMA_HIST_00 (IO_LCCTST_BASE + 0x480)
    #define LCC_DRE_S_UPPER Fld(8,24,AC_FULLB3)//[31:24]
    #define LCC_DRE_S_LOWER Fld(8,16,AC_FULLB2)//[23:16]
    #define LCC_DRE_Y_UPPER Fld(8,8,AC_FULLB1)//[15:8]
    #define LCC_DRE_Y_LOWER Fld(8,0,AC_FULLB0)//[7:0]
#define LCC_DISP_AAL_DRE_CHROMA_HIST_01 (IO_LCCTST_BASE + 0x484)
    #define LCC_DRE_CHROMA_HIST_INK_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define LCC_DRE_H_SLOPE Fld(4,24,AC_MSKB3)//[27:24]
    #define LCC_DRE_S_SLOPE Fld(4,20,AC_MSKB2)//[23:20]
    #define LCC_DRE_Y_SLOPE Fld(4,16,AC_MSKB2)//[19:16]
    #define LCC_DRE_H_UPPER Fld(8,8,AC_FULLB1)//[15:8]
    #define LCC_DRE_H_LOWER Fld(8,0,AC_FULLB0)//[7:0]
#define LCC_DISP_AAL_DRE_ALPHA_BLEND_00 (IO_LCCTST_BASE + 0x488)
    #define LCC_DRE_Y_ALPHA_SHIFT_BIT Fld(4,25,AC_MSKB3)//[28:25]
    #define LCC_DRE_Y_ALPHA_BASE Fld(9,16,AC_MSKW32)//[24:16]
    #define LCC_DRE_X_ALPHA_SHIFT_BIT Fld(4,9,AC_MSKB1)//[12:9]
    #define LCC_DRE_X_ALPHA_BASE Fld(9,0,AC_MSKW10)//[8:0]
#define LCC_DISP_AAL_DRE_BITPLUS_00 (IO_LCCTST_BASE + 0x48C)
    #define LCC_DRE_BITPLUS_INK_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define LCC_DRE_BITPLUS_AVG_FLT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define LCC_DRE_BITPLUS_DETECT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_DRE_BITPLUS_03 (IO_LCCTST_BASE + 0x498)
    #define LCC_DRE_BITPLUS_HIGH_LVL_OUT_OFT Fld(4,16,AC_MSKB2)//[19:16]
    #define LCC_DRE_BITPLUS_HIGH_LVL_PXL_SLOPE Fld(8,8,AC_FULLB1)//[15:8]
    #define LCC_DRE_BITPLUS_HIGH_LVL_PXL_TH Fld(8,0,AC_FULLB0)//[7:0]
#define LCC_DISP_AAL_DRE_BITPLUS_04 (IO_LCCTST_BASE + 0x49C)
    #define LCC_DRE_BITPLUS_TO_ALI_WGT Fld(4,20,AC_MSKB2)//[23:20]
#define LCC_DISP_AAL_DRE_BITPLUS_10 (IO_LCCTST_BASE + 0x4B4)
    #define LCC_DRE_DIFF_SLOPE Fld(4,13,AC_MSKW21)//[16:13]
    #define LCC_DRE_DIFF_TH Fld(4,9,AC_MSKB1)//[12:9]
    #define LCC_DRE_DIFF_WGT Fld(6,3,AC_MSKW10)//[8:3]
#define LCC_DISP_AAL_DRE_BITPLUS_11 (IO_LCCTST_BASE + 0x4B8)
    #define LCC_DRE_BITPLUS_CHROMA_SLOPE Fld(3,9,AC_MSKB1)//[11:9]
    #define LCC_DRE_BITPLUS_CHROMA_TH2 Fld(4,5,AC_MSKW10)//[8:5]
    #define LCC_DRE_BITPLUS_CHROMA_TH1 Fld(4,1,AC_MSKB0)//[4:1]
    #define LCC_DRE_BITPLUS_CHROMA_VWIN_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define LCC_DISP_AAL_DRE_BITPLUS_12 (IO_LCCTST_BASE + 0x4BC)
    #define LCC_DRE_CONTOUR_RANGE_SLOPE1 Fld(6,22,AC_MSKW32)//[27:22]
    #define LCC_DRE_CONTOUR_RANGE_TH1 Fld(8,14,AC_MSKW21)//[21:14]
    #define LCC_DRE_DIFFCOUNT_SLOPE1 Fld(6,8,AC_MSKB1)//[13:8]
    #define LCC_DRE_DIFFCOUNT_TH1 Fld(8,0,AC_FULLB0)//[7:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_05 (IO_LCCTST_BASE + 0x4C0)
    #define LCC_DRE_BLK_AREA Fld(24,0,AC_MSKDW)//[23:0]
#define LCC_DISP_AAL_DRE_BLOCK_INFO_06 (IO_LCCTST_BASE + 0x4C4)
    #define LCC_DRE_BLK_AREA_MIN Fld(27,0,AC_MSKDW)//[26:0]
#define LCC_DISP_AAL_Y2R_00 (IO_LCCTST_BASE + 0x4C8)
    #define LCC_Y2R_PRE_ADD_1_S Fld(12,16,AC_MSKW32)//[27:16]
    #define LCC_Y2R_PRE_ADD_0_S Fld(12,0,AC_MSKW10)//[11:0]
#define LCC_DISP_AAL_Y2R_01 (IO_LCCTST_BASE + 0x4CC)
    #define LCC_Y2R_C00_S Fld(15,16,AC_MSKW32)//[30:16]
    #define LCC_Y2R_PRE_ADD_2_S Fld(12,0,AC_MSKW10)//[11:0]
#define LCC_DISP_AAL_Y2R_02 (IO_LCCTST_BASE + 0x4D0)
    #define LCC_Y2R_C02_S Fld(15,16,AC_MSKW32)//[30:16]
    #define LCC_Y2R_C01_S Fld(15,0,AC_MSKW10)//[14:0]
#define LCC_DISP_AAL_Y2R_03 (IO_LCCTST_BASE + 0x4D4)
    #define LCC_Y2R_C11_S Fld(15,16,AC_MSKW32)//[30:16]
    #define LCC_Y2R_C10_S Fld(15,0,AC_MSKW10)//[14:0]
#define LCC_DISP_AAL_Y2R_04 (IO_LCCTST_BASE + 0x4D8)
    #define LCC_Y2R_C20_S Fld(15,16,AC_MSKW32)//[30:16]
    #define LCC_Y2R_C12_S Fld(15,0,AC_MSKW10)//[14:0]
#define LCC_DISP_AAL_Y2R_05 (IO_LCCTST_BASE + 0x4DC)
    #define LCC_Y2R_C22_S Fld(15,16,AC_MSKW32)//[30:16]
    #define LCC_Y2R_C21_S Fld(15,0,AC_MSKW10)//[14:0]
#define LCC_DISP_AAL_R2Y_00 (IO_LCCTST_BASE + 0x4E0)
    #define LCC_R2Y_POST_ADD_1_S Fld(12,16,AC_MSKW32)//[27:16]
    #define LCC_R2Y_POST_ADD_0_S Fld(12,0,AC_MSKW10)//[11:0]
#define LCC_DISP_AAL_R2Y_01 (IO_LCCTST_BASE + 0x4E4)
    #define LCC_R2Y_C00_S Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_R2Y_POST_ADD_2_S Fld(12,0,AC_MSKW10)//[11:0]
#define LCC_DISP_AAL_R2Y_02 (IO_LCCTST_BASE + 0x4E8)
    #define LCC_R2Y_C02_S Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_R2Y_C01_S Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_R2Y_03 (IO_LCCTST_BASE + 0x4EC)
    #define LCC_R2Y_C11_S Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_R2Y_C10_S Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_R2Y_04 (IO_LCCTST_BASE + 0x4F0)
    #define LCC_R2Y_C20_S Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_R2Y_C12_S Fld(13,0,AC_MSKW10)//[12:0]
#define LCC_DISP_AAL_R2Y_05 (IO_LCCTST_BASE + 0x4F4)
    #define LCC_R2Y_C22_S Fld(13,16,AC_MSKW32)//[28:16]
    #define LCC_R2Y_C21_S Fld(13,0,AC_MSKW10)//[12:0]

#endif

