/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
 * distribute this software, you may choose to be licensed under
 * version 2.1 of the GNU Lesser General Public License
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

#include"x_hal_5381.h"

#ifndef _HW_PDWNC_H_
#define _HW_PDWNC_H_
#define PDWNC_IO_BASE (IO_VIRT + 0x20000 + 0x8000)

//Page VDOIN_SYS_1
#define PDWNC_CLKPDN (PDWNC_IO_BASE + 0x000)
    #define FLD_CEC1_PDN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_SCDCS3_PDN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_SCDCS2_PDN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_SCDCS1_PDN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_SCDCS_PDN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID3_PDN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_EDID2_PDN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_UART_HT_PDN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_UART_BT_PDN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_IOEXT_PDN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_CBUSCLKPD Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_MT8193CLKPD Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_HDMIEDIDPD Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_VGADDCPD Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_SIFPD Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_T8032PD Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RTCPD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_VGAPD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SRVPD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_IRRXPD Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_CECPD Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_IRCKSEL (PDWNC_IO_BASE + 0x004)
    #define FLD_IR_CHK_CLKSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_IRCLKSEL Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_PDMISC (PDWNC_IO_BASE + 0x008)
    #define FLD_ETH_RST_B_SW Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_ETH_RST_B Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_ETHERNET_DEBUG_MODE Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_PDWNC_DEBUG_MODE Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_SET_WAKECNT Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_DIS_RS232_UART Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_DIS_RS232_HDMI_2 Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_DIS_RS232_HDMI_1 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_NO_USED Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_SYNC_RTC Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_PDWN_POL Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_DIS_RS232_U0RX Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DIS_RS232_VGA Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_VGA_SYNC_DIS Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_PDWN_EN Fld(1,10,AC_MSKB1)//[10:10]
#define PDWNC_PDMODE (PDWNC_IO_BASE + 0x010)
    #define FLD_DEEP_SLEEP Fld(1,5,AC_MSKB0)//[5:5]
#define PDWNC_MEMPD (PDWNC_IO_BASE + 0x014)
    #define FLD_MEMPD Fld(22,0,AC_MSKDW)//[21:0]
#define PDWNC_PWROPT (PDWNC_IO_BASE + 0x018)
    #define FLD_ADC_SELECT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_TIMER_COUNTER_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_PWR_CTL_OPT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PD_MON_CFG (PDWNC_IO_BASE + 0x01C)
    #define FLD_PD_MON_CFG Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_WAKE_STONLY0 (PDWNC_IO_BASE + 0x020)
    #define FLD_WAK_STA_MUL Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_WAK_STON0_EN Fld(31,0,AC_MSKDW)//[30:0]
    #define FLD_EXTIO_WAK_STON0_EN Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_TOUT_RSTCNT (PDWNC_IO_BASE + 0x024)
    #define FLD_TOUT_RSTCNT Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_TOUT_CNT_MON (PDWNC_IO_BASE + 0x028)
    #define FLD_TOUT_CNT_MON Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_MT8193_CLK_SEL (PDWNC_IO_BASE + 0x02C)
    #define FLD_MT8193_CLK_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_INTSTA (PDWNC_IO_BASE + 0x040)
    #define FLD_USB20_1P_INT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_CBUS_INT_STA Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_ETHERNET_INT_STA Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_HDMI2_DEV2_DET_INT Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_HDMI_DEV_DET_INT Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GSPI_INT_STA Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_CEC_INT1_STA Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_CEC2_INT1_STA Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_DDCCI_INT_STA Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_SIFM1_INT_STA Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_AUX_INT_STA Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_ARM_INT_STA Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_IR_INT_STA Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RTC_INT_STA Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_CEC_INT0_STA Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_CEC2_INT0_STA Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_UART_DBG_INT_STA Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_SIFM0_INT_STA Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_PWERT_RDY_INT_STA Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RS232_INT_BT_STA Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RS232_INT_HT_STA Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_USB20_1P_CDS1_INT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_USB20_1P_CDS0_INT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_USB30_SPM_INT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_USB30_XHCI_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_WAKEUP_INT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_ARM_INTEN (PDWNC_IO_BASE + 0x044)
    #define FLD_SIFM2_INTEN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_CBUS_INTEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_HDMI_3_DEV3_DET_INTEN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_HDMI_2_DEV2_DET_INTEN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_DEV_DET_INTEN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_GSPI_INTEN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_CEC_INT1EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_AVLINK_INT1EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_DDCCI_INT_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_SIFM1_INTEN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_AUX_INTEN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_ARM_INTEN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_IR_INTEN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RTC_INTEN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_CEC_INT0EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_AVLINK_INT0EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_UART_DBG_INTEN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_SIFM0_INTEN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_PWERT_RDY_INT Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RS232_INT_BT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RS232_INT_HT Fld(1,5,AC_MSKB0)//[5:5]
#define PDWNC_INTCLR (PDWNC_IO_BASE + 0x048)
    #define FLD_SIFM2_INTCLR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_CBUS_INTCLR Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_CEC_INT1CLR Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_AVLINK_INT1CLR Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_SIFM1_INTCLR Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_AUX_INTCLR Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_ARM_INTCLR Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_IR_INTCLR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RTC_INTCLR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_CEC_INT0CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_AVLINK_INT0CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_UART_DBG_INTCLR Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_SIFM0_INTCLR Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_PWERT_RDY_INTCLR Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_USB20_1P_CDS1_INTCLR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_USB20_1P_CDS0_INTCLR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDWN_WAKE_INTCLR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_T8032_INTEN (PDWNC_IO_BASE + 0x04C)
    #define FLD_T8032_USB20_1P_INT Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_T8032_CBUS_INTEN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_T8032_ETHERNET_INTEN Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_T8032_DEV2_DET_INTEN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_T8032_DEV_DET_INTEN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_T8032_GSPI_INTEN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_T8032_CEC_INT1EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_T8032_AVLINK_INT1EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_T8032_DDCCI_INT_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_T8032_SIFM1_INTEN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_T8032_AUX_INTEN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_T8032_ARM_INTEN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_T8032_IR_INTEN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_T8032_RTC_INTEN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_T8032_CEC_INT0EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_T8032_AVLINK_INT0EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_T8032_UART_DBG_INTEN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_T8032_SIFM0_INTEN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_PWERT_RDY_INTEN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RS232_INT_BT_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RS232_INT_HT_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_T8032_USB20_1P_CDS1_INT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_T8032_USB30_DEV_INT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_T8032_USB30_SPM_INT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_T8032_USB30_XHCI_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_T8032_WAKEUP_INT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_WDTINT_STA (PDWNC_IO_BASE + 0x050)
    #define FLD_WDT_INT_STA Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WDTINT_EN (PDWNC_IO_BASE + 0x054)
    #define FLD_WDT_INT_EN Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WDTINT_CLR (PDWNC_IO_BASE + 0x058)
    #define FLD_WDT_INT_CLR Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_EXT_INTSTA_0 (PDWNC_IO_BASE + 0x05C)
    #define FLD_GPIO_INT_STA0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXT_INTSTA_1 (PDWNC_IO_BASE + 0x060)
    #define FLD_TIMER_INT_STA Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO_INT_STA1 Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_ARM_INTEN_0 (PDWNC_IO_BASE + 0x064)
    #define FLD_ARM_GPIO_INTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_ARM_INTEN_1 (PDWNC_IO_BASE + 0x068)
    #define FLD_TIMER_INTEN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_ARM_GPIO_INTEN1 Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_EXT_INTCLR_0 (PDWNC_IO_BASE + 0x06C)
    #define FLD_GPIO_INTCLR0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXT_INTCLR_1 (PDWNC_IO_BASE + 0x070)
    #define FLD_TIMER_INTCLR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_GPIO_INTCLR1 Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_T8032_EXT_INTEN_0 (PDWNC_IO_BASE + 0x074)
    #define FLD_T8032_GPIO_INTEN0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_T8032_EXT_INTEN_1 (PDWNC_IO_BASE + 0x078)
    #define FLD_T8032_GPIO_INTEN1 Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_POWER_ON_COUNTER (PDWNC_IO_BASE + 0x07C)
    #define FLD_POWER_ON_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_WAKEN1 (PDWNC_IO_BASE + 0x080)
    #define FLD_EXTIO_WAKEN1 Fld(30,0,AC_MSKDW)//[29:0]
#define PDWNC_WAKE_STONLY1 (PDWNC_IO_BASE + 0x084)
    #define FLD_WAK_STON1_EN Fld(30,0,AC_MSKDW)//[29:0]
#define PDWNC_PDSTAT1 (PDWNC_IO_BASE + 0x088)
    #define FLD_PDSTAT1 Fld(30,0,AC_MSKDW)//[29:0]
#define PDWNC_ETH_PWR_CHAIN_CTL (PDWNC_IO_BASE + 0x090)
    #define FLD_ETH_PWR_ACK Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_ETH_PWR_CTL Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_ETH_PWR_CTL (PDWNC_IO_BASE + 0x094)
    #define FLD_ETH_PWR_SRAM_PD Fld(5,4,AC_MSKW10)//[8:4]
    #define FLD_ETH_PWR_ISO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_ETH_PWR_CLK_DIS Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_ETH_PWR_ON_RSTB Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PD_MONA_CFG (PDWNC_IO_BASE + 0x09C)
    #define FLD_PDWNC_MONITOR_A_CFG Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DRAMC_SREF_HW_CTL (PDWNC_IO_BASE + 0x0A0)
    #define FLD_DRAMC_SREF_HW_CTL Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_DRAMC_C_SREF_HW_CTL     Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_DRAMC_B_SREF_HW_CTL     Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_DRAMC_A_SREF_HW_CTL     Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_DRAMC_SREF_STATUS (PDWNC_IO_BASE + 0x0A4)
	#define FLD_DRAMC_SREF_STATUS Fld(32,0,AC_FULLDW)//[31:0]
	#define FLD_DRAMC_A_SELFREF_SM	Fld(3,0,AC_MSKB0)//[0:2]
    #define FLD_DRAMC_SREF_STATUS_CHA	Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DRAMC_SREF_STATUS_CHB	Fld(1,0,AC_MSKB0)//[0:0]		
#define PDWNC_DRAMC_B_SREF_STATUS (PDWNC_IO_BASE + 0x6D0)
    #define FLD_DRAMC_B_SREF_STATUS Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_DRAMC_B_SELFREF_SM     Fld(3,0,AC_MSKB0)//[0:2]
    #define FLD_DRAMC_SREF_STATUS_CHC 	Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DRAMC_SREF_STATUS_CHD 	Fld(1,0,AC_MSKB0)//[0:0]    
#define PDWNC_DRAMC_C_SREF_STATUS (PDWNC_IO_BASE + 0x0AC)
//    #define FLD_DRAMC_C_SREF_STATUS Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_DRAMC_C_SELFREF_SM     Fld(3,0,AC_MSKB0)//[0:2]
#define PDWNC_DRAMB_FLUSH_WR_CTL (PDWNC_IO_BASE + 0x0B0)
//    #define FLD_DRAMB_FLUSH_WR_CTL Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_DRAMB_C_FLUSH_ARB         Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_DRAMB_C_FLUSH_WR_ARB     Fld(2,8,AC_MSKB1)//[8:9]
    #define FLD_DRAMB_B_FLUSH_ARB         Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_DRAMB_B_FLUSH_WR_ARB     Fld(2,4,AC_MSKB0)//[4:5]
    #define FLD_DRAMB_A_FLUSH_ARB         Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_DRAMB_A_FLUSH_WR_ARB     Fld(2,0,AC_MSKB0)//[0:1]
#define PDWNC_DRAMB_AGENT_REQ_MON (PDWNC_IO_BASE + 0x0B4)
    #define FLD_DRAMB_AGENT_REQ_MON Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DRAMB_B_AGENT_REQ_MON (PDWNC_IO_BASE + 0x0B8)
    #define FLD_DRAMB_B_AGENT_REQ_MON Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DRAMB_C_AGENT_REQ_MON (PDWNC_IO_BASE + 0x0BC)
    #define FLD_DRAMB_C_AGENT_REQ_MON Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DRAMB_POSTED_W_EMPTY (PDWNC_IO_BASE + 0x0C0)
    #define FLD_DRAMB_POSTED_W_EMPTY Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_CPU_STANDBYWFI_STATUS (PDWNC_IO_BASE + 0x0D0)
    #define FLD_CPU_STANDBYWFI_STATUS Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SREF_CONTROL_BY8032 (PDWNC_IO_BASE + 0x0D4)
    #define FLD_SREF_CONTROL_BY8032 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_USB30_RG_SPM (PDWNC_IO_BASE + 0x0DC)
    #define FLD_USB30_RST_SEL Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_USB30_LOCAL_ARB_RST_SW Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_USB30_RG_U2PHY_MUX_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_USB30_MON_SEL Fld(3,14,AC_MSKW21)//[16:14]
    #define FLD_USB30_SPM_RESTVE Fld(14,0,AC_MSKW10)//[13:0]
#define PDWNC_USB30_RG_RESEVED (PDWNC_IO_BASE + 0x0E0)
    #define FLD_USB20_RG_RESEVED Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_USB30_USB_SRAM_PD (PDWNC_IO_BASE + 0x0E4)
    #define FLD_USB20_1P_SRAM_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_USB30_USB_SRAM_PD Fld(9,0,AC_MSKW10)//[8:0]
#define PDWNC_USB_PWR_CTL (PDWNC_IO_BASE + 0x0E8)
    #define FLD_USB20_1P_ISO_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_USB20_1P_PWR_CTL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_USB30_ISO_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_USB30_PWR_CTL Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_USB_PWR_ACK (PDWNC_IO_BASE + 0x0EC)
    #define FLD_USB20_1P_PWR_ACK Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_USB30_PWR_ACK Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_USB_MTCMOS_CTRL (PDWNC_IO_BASE + 0x0F0)
    #define FLD_USB20_PWR_RST Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_USB30_SW_RST Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_USB30_PWR_CLK_DIS Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_USB30_PWR_RST Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_USB30_CPU_BY_8032 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_STB_WAKUP_DELAY_CNT (PDWNC_IO_BASE + 0x0F4)
    #define FLD_STB_WAKUP_DELAY_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_STB_WAKUP_DELAY_SEL (PDWNC_IO_BASE + 0x0F8)
    #define FLD_WAKUP_DELAY_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_PDWN_MODE_HOLD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_PDWN_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_STB_WAKUP_DELAY_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_DFD_DELAY_CNT (PDWNC_IO_BASE + 0x0FC)
    #define FLD_DFD_DELAY_CNT Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_WDTCTL (PDWNC_IO_BASE + 0x100)
    #define FLD_DFD_CNT_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_WDT2RST Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_WDT1RST Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_WDT0RST Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_WDT2E Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_WDT1E Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_WDT0E Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_WDT0 (PDWNC_IO_BASE + 0x104)
    #define FLD_PWR_RDY Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_WDT0 Fld(31,0,AC_MSKDW)//[30:0]
#define PDWNC_WKRSC (PDWNC_IO_BASE + 0x108)
    #define FLD_WKRSC Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_WDT1 (PDWNC_IO_BASE + 0x10C)
    #define FLD_PDWNC_STATUS_0 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_WDT1 Fld(31,0,AC_MSKDW)//[30:0]
#define PDWNC_WDT2 (PDWNC_IO_BASE + 0x110)
    #define FLD_PDWNC_STATUS_1 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_WDT2 Fld(31,0,AC_MSKDW)//[30:0]
#define PDWNC_WDTRST0 (PDWNC_IO_BASE + 0x114)
    #define FLD_WDTRST0 Fld(28,0,AC_MSKDW)//[27:0]
#define PDWNC_WDTRST1 (PDWNC_IO_BASE + 0x118)
    #define FLD_WDTRST1 Fld(28,0,AC_MSKDW)//[27:0]
#define PDWNC_WDTRST2 (PDWNC_IO_BASE + 0x11C)
    #define FLD_WDTRST2 Fld(28,0,AC_MSKDW)//[27:0]
#define PDWNC_WAKEN (PDWNC_IO_BASE + 0x120)
    #define FLD_SRVAD_WAKEN Fld(10,20,AC_MSKW32)//[29:20]
    #define FLD_UNOR_WAKEN Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_T8032_WAKEN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RTC_WAKEN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_BT_RS232_WAKEN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_HT_RS232_WAKEN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_VGA_WAKEN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_IR_WAKEN Fld(1,8,AC_MSKB1)//[8:8]

//Page VDOIN_SYS_2
#define PDWNC_PDCODE (PDWNC_IO_BASE + 0x124)
    #define FLD_PDCODE Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_PDSTAT0 (PDWNC_IO_BASE + 0x128)
    #define FLD_SRVAD_WAK Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_UNOR_WAK Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_T8032_WAK Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_UART_WAK Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RTC_WAK Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_BT_RS232_WAK Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_HT_RS232_WAK Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_VGA_WAK Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_IR_WAK Fld(1,8,AC_MSKB1)//[8:8]
#define PDWNC_PDSTCLR (PDWNC_IO_BASE + 0x12C)
    #define FLD_STCLR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_UPWAK (PDWNC_IO_BASE + 0x130)
    #define FLD_WAKCODE Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_OPDELAY (PDWNC_IO_BASE + 0x134)
    #define FLD_WDT_RST_CLR_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_OPWRSB_DELAY Fld(28,0,AC_MSKDW)//[27:0]
#define PDWNC_PD_PWM0C0 (PDWNC_IO_BASE + 0x138)
    #define FLD_PWM0RSN Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_PWM0H Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_PWM0CYC Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_PWM0AUTO Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_PWM0FLAG Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PWM0E Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PD_PWM0C1 (PDWNC_IO_BASE + 0x13C)
    #define FLD_PWM0P Fld(25,0,AC_MSKDW)//[24:0]
#define PDWNC_RESRV0 (PDWNC_IO_BASE + 0x140)
    #define FLD_RESRV0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV1 (PDWNC_IO_BASE + 0x144)
    #define FLD_RESRV1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV2 (PDWNC_IO_BASE + 0x148)
    #define FLD_RESRV2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV3 (PDWNC_IO_BASE + 0x14C)
    #define FLD_RESRV3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_AC_TIMER (PDWNC_IO_BASE + 0x154)
    #define FLD_TIME Fld(20,0,AC_MSKDW)//[19:0]
#define PDWNC_PD_PWM1C0 (PDWNC_IO_BASE + 0x158)
    #define FLD_PWM1RSN Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_PWM1H Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_PWM1CYC Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_PWM1AUTO Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_PWM1FLAG Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PWM1E Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PD_PWM1C1 (PDWNC_IO_BASE + 0x15C)
    #define FLD_PWM1P Fld(25,0,AC_MSKDW)//[24:0]
#define PDWNC_SM1CTL0 (PDWNC_IO_BASE + 0x160)
    #define FLD_SIFM1_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SIFM1_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SIFM1_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SIFM1_DE_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SIFM1_DEGLITCH_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SIFM1_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SIFM1_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SIFM1_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SIFM1_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SIFM1_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM1CTL1 (PDWNC_IO_BASE + 0x164)
    #define FLD_SIFM1_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SIFM1_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SIFM1_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SIFM1_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM1D0 (PDWNC_IO_BASE + 0x168)
    #define FLD_SIFM1_DATA3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D1 (PDWNC_IO_BASE + 0x16C)
    #define FLD_SIFM1_DATA7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA4 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_UP_ADDR (PDWNC_IO_BASE + 0x170)
    #define FLD_UP_ADDR Fld(17,0,AC_MSKDW)//[16:0]
#define PDWNC_UP_DATA (PDWNC_IO_BASE + 0x174)
    #define FLD_UP_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_UP_CFG (PDWNC_IO_BASE + 0x178)
    #define FLD_T8032_ON Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_HDMI_D_EDID_SEL Fld(1,27,AC_MSKB3) //[27:27]
    #define FLD_HDMI_C_EDID_SEL Fld(1,26,AC_MSKB3) //[26:26]
    #define FLD_HDMI_B_EDID_SEL Fld(1,25,AC_MSKB3) //[25:25]
    #define FLD_HDMI_A_EDID_SEL Fld(1,24,AC_MSKB3) //[24:24]
    #define FLD_UART_BT_RAM_SPL_SEL Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_ICACHE_RAM_SP_SEL Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_HDMI_RAM_SPL_SEL Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_VGA_RAM_SP_SEL Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_BLOCK_GPIO_ACC Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_XDATA_ACC Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_VIR_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_T8032_RST Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SHREG0 (PDWNC_IO_BASE + 0x180)
    #define FLD_SHREG0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SHREG1 (PDWNC_IO_BASE + 0x184)
    #define FLD_SHREG1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SHREG2 (PDWNC_IO_BASE + 0x188)
    #define FLD_SHREG2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SHREG3 (PDWNC_IO_BASE + 0x18C)
    #define FLD_SHREG3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SM0CTL0 (PDWNC_IO_BASE + 0x1C0)
    #define FLD_SIFM0_ODRAIN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SIFM0_VSYNC_MODE Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_SIFM0_CLK_DIV Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SIFM0_DE_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_WAIT_LEVEL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SIFM0_DEGLITCH_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SIFM0_CS_STATUS Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SIFM0_SCL_STATE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SIFM0_SDA_STATE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SIFM0_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SIFM0_SCL_STRECH Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM0CTL1 (PDWNC_IO_BASE + 0x1C4)
    #define FLD_SIFM0_ACK0 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SIFM0_PGLEN Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_SIFM0_MODE Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SIFM0_TRI Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM0D0 (PDWNC_IO_BASE + 0x1C8)
    #define FLD_SIFM0_DATA3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D1 (PDWNC_IO_BASE + 0x1CC)
    #define FLD_SIFM0_DATA7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA4 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_VGA_DEV (PDWNC_IO_BASE + 0x1D0)
    #define FLD_DE_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_DEGLITCH_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_VGA_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_DEV_ADDR Fld(6,2,AC_MSKB0)//[7:2]
#define PDWNC_VGA_ADDR (PDWNC_IO_BASE + 0x1D4)
    #define FLD_VGA_ADDR Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_VGA_DATA (PDWNC_IO_BASE + 0x1D8)
    #define FLD_VGA_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_AC_TIMIER_0 (PDWNC_IO_BASE + 0x1E0)
    #define FLD_AC_TIMIER_LOW_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_AC_TIMIER_1 (PDWNC_IO_BASE + 0x1E4)
    #define FLD_AC_TIMIER_HIGH_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_ARM_INT (PDWNC_IO_BASE + 0x1E8)
    #define FLD_ARM_INT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_AUX_INT (PDWNC_IO_BASE + 0x1F4)
    #define FLD_AUX_INT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_AC_TIMIER_0_SW (PDWNC_IO_BASE + 0x1F8)
    #define FLD_AC_TIMIER_SW_LOW_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_AC_TIMIER_1_SW (PDWNC_IO_BASE + 0x1FC)
    #define FLD_AC_TIMIER_SW_HIGH_COUNTER Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_IRCNT (PDWNC_IO_BASE + 0x200)
    #define FLD_RES_ONE Fld(13,8,AC_MSKW21)//[20:8]
    #define FLD_BIT_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IRDATA0 (PDWNC_IO_BASE + 0x204)
    #define FLD_BIT_REG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_BIT_REG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_BIT_REG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_BIT_REG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IRDATA1 (PDWNC_IO_BASE + 0x208)
    #define FLD_BIT_REG7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_BIT_REG6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_BIT_REG5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_BIT_REG4 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IRCFGH (PDWNC_IO_BASE + 0x20C)
    #define FLD_USB2UART_SW Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_USB2UART_HW_DIS Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_IREND Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_DISPD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_IGB0 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_CHK_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_DISCH Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_DISCL Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_IGSYN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_ORDINV Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RC5_1ST Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RC5 Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_IRI Fld(1,1,AC_MSKB0)//[1:1]
#define PDWNC_IRCFGL (PDWNC_IO_BASE + 0x210)
    #define FLD_CHK_SAPERIOD Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_SAPERIOD Fld(16,0,AC_FULLW10)//[15:0]
#define PDWNC_IRTHD (PDWNC_IO_BASE + 0x214)
    #define FLD_ICLR Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_DG_DEL Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_IRTHD Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_IRCLR (PDWNC_IO_BASE + 0x218)
    #define FLD_IRCLR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_IREXP_EN (PDWNC_IO_BASE + 0x21C)
    #define FLD_CMP_DATA_SEL Fld(3,20,AC_MSKB2)//[22:20]
    #define FLD_BCEPEN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_IREXPEN Fld(16,0,AC_FULLW10)//[15:0]
#define PDWNC_ENEXP_IRM (PDWNC_IO_BASE + 0x220)
    #define FLD_ENEXP_BIT_REG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_ENEXP_BIT_REG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_ENEXP_BIT_REG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_ENEXP_BIT_REG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR0 (PDWNC_IO_BASE + 0x228)
    #define FLD_EXP0_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP0_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP0_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP0_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR1 (PDWNC_IO_BASE + 0x22C)
    #define FLD_EXP1_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP1_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP1_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP1_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR2 (PDWNC_IO_BASE + 0x230)
    #define FLD_EXP2_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP2_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP2_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP2_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR3 (PDWNC_IO_BASE + 0x234)
    #define FLD_EXP3_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP3_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP3_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP3_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR4 (PDWNC_IO_BASE + 0x238)
    #define FLD_EXP4_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP4_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP4_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP4_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR5 (PDWNC_IO_BASE + 0x23C)
    #define FLD_EXP5_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP5_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP5_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP5_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR6 (PDWNC_IO_BASE + 0x240)
    #define FLD_EXP6_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP6_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP6_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP6_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR7 (PDWNC_IO_BASE + 0x244)
    #define FLD_EXP7_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP7_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP7_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP7_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]

//Page VDOIN_SYS_3
#define PDWNC_EXP_IR8 (PDWNC_IO_BASE + 0x248)
    #define FLD_EXP8_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP8_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP8_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP8_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR9 (PDWNC_IO_BASE + 0x24C)
    #define FLD_EXP9_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP9_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP9_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP9_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR10 (PDWNC_IO_BASE + 0x250)
    #define FLD_EXP10_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP10_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP10_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP10_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR11 (PDWNC_IO_BASE + 0x254)
    #define FLD_EXP11_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP11_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP11_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP11_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR12 (PDWNC_IO_BASE + 0x258)
    #define FLD_EXP12_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP12_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP12_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP12_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR13 (PDWNC_IO_BASE + 0x25C)
    #define FLD_EXP13_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP13_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP13_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP13_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR14 (PDWNC_IO_BASE + 0x260)
    #define FLD_EXP14_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP14_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP14_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP14_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_IR15 (PDWNC_IO_BASE + 0x264)
    #define FLD_EXP15_BITREG3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_EXP15_BITREG2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_EXP15_BITREG1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EXP15_BITREG0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EXP_BCNT (PDWNC_IO_BASE + 0x268)
    #define FLD_EXP_BITCNT Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_RCMM_THD0 (PDWNC_IO_BASE + 0x26C)
    #define FLD_RCMM_ENABLE Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RCMM_THD01 Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_RCMM_THD00 Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_RCMM_THD1 (PDWNC_IO_BASE + 0x270)
    #define FLD_RCMM_THD11 Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_RCMM_THD10 Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_IRCNT_H (PDWNC_IO_BASE + 0x274)
    #define FLD_RES_THREE Fld(13,13,AC_MSKDW)//[25:13]
    #define FLD_RES_TWO Fld(13,0,AC_MSKW10)//[12:0]
#define PDWNC_IR_WAK_STATUS (PDWNC_IO_BASE + 0x280)
    #define FLD_IR_WAK_STATUS Fld(16,0,AC_FULLW10)//[15:0]
#define PDWNC_IR_HW_CLR_TIMER0 (PDWNC_IO_BASE + 0x284)
    #define FLD_IR_HW_CLR_TIMER0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_IR_HW_CLR_TIMER1 (PDWNC_IO_BASE + 0x288)
    #define FLD_IR_HW_CLR_TIMER1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_IR_HW_KEY_MATCH (PDWNC_IO_BASE + 0x28C)
    #define FLD_IR_HW_KEY_MATCH Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_IRDATA2 (PDWNC_IO_BASE + 0x290)
    #define FLD_BIT_REG11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_BIT_REG10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_BIT_REG9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_BIT_REG8 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IRDATA3 (PDWNC_IO_BASE + 0x294)
    #define FLD_BIT_REG15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_BIT_REG14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_BIT_REG13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_BIT_REG12 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IR_KEY_DATA_MASK (PDWNC_IO_BASE + 0x298)
    #define FLD_IR_KEY_DATA_MASK Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PD_PWM2C0 (PDWNC_IO_BASE + 0x2A0)
    #define FLD_PWM2RSN Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_PWM2H Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_PWM2CYC Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_PWM2AUTO Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_PWM2FLAG Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PWM2E Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PD_PWM2C1 (PDWNC_IO_BASE + 0x2A4)
    #define FLD_PWM2P Fld(25,0,AC_MSKDW)//[24:0]
#define PDWNC_PD_PWM3C0 (PDWNC_IO_BASE + 0x2A8)
    #define FLD_PWM3RSN Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_PWM3H Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_PWM3CYC Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_PWM3AUTO Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_PWM3FLAG Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_PWM3E Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PD_PWM3C1 (PDWNC_IO_BASE + 0x2AC)
    #define FLD_PWM3P Fld(25,0,AC_MSKDW)//[24:0]
#define PDWNC_CHKDATA0 (PDWNC_IO_BASE + 0x2BC)
    #define FLD_CHK_BYTE3 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE2 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE0 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA1 (PDWNC_IO_BASE + 0x2C0)
    #define FLD_CHK_BYTE7 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE6 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE5 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE4 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA2 (PDWNC_IO_BASE + 0x2C4)
    #define FLD_CHK_BYTE11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE8 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA3 (PDWNC_IO_BASE + 0x2C8)
    #define FLD_CHK_BYTE15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE12 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA4 (PDWNC_IO_BASE + 0x2CC)
    #define FLD_CHK_BYTE19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE16 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA5 (PDWNC_IO_BASE + 0x2D0)
    #define FLD_CHK_BYTE23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE20 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA6 (PDWNC_IO_BASE + 0x2D4)
    #define FLD_CHK_BYTE27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE24 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA7 (PDWNC_IO_BASE + 0x2D8)
    #define FLD_CHK_BYTE31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE28 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA8 (PDWNC_IO_BASE + 0x2DC)
    #define FLD_CHK_BYTE35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE32 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA9 (PDWNC_IO_BASE + 0x2E0)
    #define FLD_CHK_BYTE39 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE38 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE37 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE36 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA10 (PDWNC_IO_BASE + 0x2E4)
    #define FLD_CHK_BYTE43 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE42 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE41 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE40 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA11 (PDWNC_IO_BASE + 0x2E8)
    #define FLD_CHK_BYTE47 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE46 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE45 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE44 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA12 (PDWNC_IO_BASE + 0x2EC)
    #define FLD_CHK_BYTE51 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE50 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE49 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE48 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA13 (PDWNC_IO_BASE + 0x2F0)
    #define FLD_CHK_BYTE55 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE54 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE53 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE52 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA14 (PDWNC_IO_BASE + 0x2F4)
    #define FLD_CHK_BYTE59 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE58 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE57 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE56 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHKDATA15 (PDWNC_IO_BASE + 0x2F8)
    #define FLD_CHK_BYTE63 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_CHK_BYTE62 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_CHK_BYTE61 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CHK_BYTE60 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CHK_SEL (PDWNC_IO_BASE + 0x2FC)
    #define FLD_CHK_DATA_SEL Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SRVCFG0 (PDWNC_IO_BASE + 0x300)
    #define FLD_SRVCH_SEL Fld(5,4,AC_MSKW10)//[8:4]
    #define FLD_ABIST_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SRVWAK_HD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SWEN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_HWEN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SRVCFG1 (PDWNC_IO_BASE + 0x304)
    #define FLD_SRVCH_EN Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SRVSWT (PDWNC_IO_BASE + 0x308)
    #define FLD_SWTRG Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SRVCLR (PDWNC_IO_BASE + 0x30C)
    #define FLD_ADCLR Fld(1,1,AC_MSKB0)//[1:1]
#define PDWNC_SRVRAT (PDWNC_IO_BASE + 0x310)
    #define FLD_SMP_RATE Fld(16,0,AC_FULLW10)//[15:0]
#define PDWNC_SRVTOTEN (PDWNC_IO_BASE + 0x314)
    #define FLD_TOUT_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SRVHD_ST Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_DATA_RDST Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_TOUT_ST Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TOUT_EN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_WAKTOP0 (PDWNC_IO_BASE + 0x318)
    #define FLD_CH0TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM0 (PDWNC_IO_BASE + 0x31C)
    #define FLD_CH0BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG0 (PDWNC_IO_BASE + 0x320)
    #define FLD_CH0WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP1 (PDWNC_IO_BASE + 0x324)
    #define FLD_CH1TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM1 (PDWNC_IO_BASE + 0x328)
    #define FLD_CH1BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG1 (PDWNC_IO_BASE + 0x32C)
    #define FLD_CH1WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP2 (PDWNC_IO_BASE + 0x330)
    #define FLD_CH2TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM2 (PDWNC_IO_BASE + 0x334)
    #define FLD_CH2BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG2 (PDWNC_IO_BASE + 0x338)
    #define FLD_CH2WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP3 (PDWNC_IO_BASE + 0x33C)
    #define FLD_CH3TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM3 (PDWNC_IO_BASE + 0x340)
    #define FLD_CH3BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG3 (PDWNC_IO_BASE + 0x344)
    #define FLD_CH3WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP4 (PDWNC_IO_BASE + 0x348)
    #define FLD_CH4TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM4 (PDWNC_IO_BASE + 0x34C)
    #define FLD_CH4BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG4 (PDWNC_IO_BASE + 0x350)
    #define FLD_CH4WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP5 (PDWNC_IO_BASE + 0x354)
    #define FLD_CH5TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM5 (PDWNC_IO_BASE + 0x358)
    #define FLD_CH5BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG5 (PDWNC_IO_BASE + 0x35C)
    #define FLD_CH5WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP6 (PDWNC_IO_BASE + 0x360)
    #define FLD_CH6TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM6 (PDWNC_IO_BASE + 0x364)
    #define FLD_CH6BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG6 (PDWNC_IO_BASE + 0x368)
    #define FLD_CH6WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP7 (PDWNC_IO_BASE + 0x36C)
    #define FLD_CH7TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM7 (PDWNC_IO_BASE + 0x370)
    #define FLD_CH7BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG7 (PDWNC_IO_BASE + 0x374)
    #define FLD_CH7WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP8 (PDWNC_IO_BASE + 0x378)
    #define FLD_CH8TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM8 (PDWNC_IO_BASE + 0x37C)
    #define FLD_CH8BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG8 (PDWNC_IO_BASE + 0x380)
    #define FLD_CH8WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_WAKTOP9 (PDWNC_IO_BASE + 0x384)
    #define FLD_CH9TOP Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_WAKBTM9 (PDWNC_IO_BASE + 0x388)
    #define FLD_CH9BTM Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_CHCFG9 (PDWNC_IO_BASE + 0x38C)
    #define FLD_CH9WKC Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_SRVCST (PDWNC_IO_BASE + 0x390)
    #define FLD_SRVCST Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_ADOUT0 (PDWNC_IO_BASE + 0x394)
    #define FLD_ADOUT0 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1 (PDWNC_IO_BASE + 0x398)
    #define FLD_ADOUT1 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT2 (PDWNC_IO_BASE + 0x39C)
    #define FLD_ADOUT2 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT3 (PDWNC_IO_BASE + 0x3A0)
    #define FLD_ADOUT3 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT4 (PDWNC_IO_BASE + 0x3A4)
    #define FLD_ADOUT4 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT5 (PDWNC_IO_BASE + 0x3A8)
    #define FLD_ADOUT5 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT6 (PDWNC_IO_BASE + 0x3AC)
    #define FLD_ADOUT6 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT7 (PDWNC_IO_BASE + 0x3B0)
    #define FLD_ADOUT7 Fld(10,2,AC_MSKW10)//[11:2]

//Page VDOIN_SYS_4
#define PDWNC_ADOUT8 (PDWNC_IO_BASE + 0x3B4)
    #define FLD_ADOUT8 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT9 (PDWNC_IO_BASE + 0x3B8)
    #define FLD_ADOUT9 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUTA (PDWNC_IO_BASE + 0x3BC)
    #define FLD_ADOUTA Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUTB (PDWNC_IO_BASE + 0x3C0)
    #define FLD_ADOUTB Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUTC (PDWNC_IO_BASE + 0x3C4)
    #define FLD_ADOUTC Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUTD (PDWNC_IO_BASE + 0x3C8)
    #define FLD_ADOUTD Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUTE (PDWNC_IO_BASE + 0x3CC)
    #define FLD_ADOUTE Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUTF (PDWNC_IO_BASE + 0x3D0)
    #define FLD_ADOUTF Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT10 (PDWNC_IO_BASE + 0x3D4)
    #define FLD_ADOUT10 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT11 (PDWNC_IO_BASE + 0x3D8)
    #define FLD_ADOUT11 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT12 (PDWNC_IO_BASE + 0x3DC)
    #define FLD_ADOUT12 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_PRST (PDWNC_IO_BASE + 0x3E0)
    #define FLD_PRST_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_VOLTAGE_CHC Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_VOLTAGE_CHB Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_PRST_1 (PDWNC_IO_BASE + 0x3E4)
    #define FLD_VOLTAGE_CHE Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_VOLTAGE_CHD Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_PRST_2 (PDWNC_IO_BASE + 0x3E8)
    #define FLD_CH11_FILTER Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_CH10_FILTER Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_CHF_FILTER Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_CHE_FILTER Fld(4,12,AC_MSKB1)//[15:12]
    #define FLD_CHD_FILTER Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_CHC_FILTER Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_CHB_FILTER Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_PRST_3 (PDWNC_IO_BASE + 0x3EC)
    #define FLD_VOLTAGE_CH10 Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_VOLTAGE_CHF Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_0_REGISTER (PDWNC_IO_BASE + 0x400)
    #define FLD_DBG_SEL Fld(4,28,AC_MSKB3)//[31:28]
    #define FLD_AUTO_SWITCH_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_C_DGLITCH_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_V_DGLITCH_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_H_DGLITCH_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_HRANGE_L Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_HRANGE_U Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_1_REGISTER (PDWNC_IO_BASE + 0x404)
    #define FLD_SOG_WAK_DIS Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_C_SYNC_WAK_DIS Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_S_SYNC_WAK_DIS Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_STABLE_RESET Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_HLEN_VLEN_RESET Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RESERVE_VGA01 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_WAKEUP_INT_EN Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_VRANGE_L Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_VRANGE_U Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_2_REGISTER (PDWNC_IO_BASE + 0x408)
    #define FLD_VSYNC_SEL Fld(2,30,AC_MSKB3)//[31:30]
    #define FLD_HSYNC_SEL Fld(2,28,AC_MSKB3)//[29:28]
    #define FLD_CSYNC_SOG_SEL Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_C_ACTEN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_V_ACTEN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_H_ACTEN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_VWIDTH_POL Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_VWIDTH_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_VWIDTH_DIFF_TH Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_VWIDTH_SEL Fld(2,14,AC_MSKB1)//[15:14]
    #define FLD_VWIDTH_STABLE_TH Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_VWIDTH_U Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_3_REGISTER (PDWNC_IO_BASE + 0x40C)
    #define FLD_RESERVE_VGA03 Fld(2,30,AC_MSKB3)//[31:30]
    #define FLD_H_DIFF_TH Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_V_STABLE_TH Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_H_STABLE_TH Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_4_REGISTER (PDWNC_IO_BASE + 0x410)
    #define FLD_STATUS_HOLD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RESERVE_VGA04 Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_V_DIFF_TH Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_VACT_MP_TH Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_C_STABLE_TH Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_5_REGISTER (PDWNC_IO_BASE + 0x414)
    #define FLD_RESERVE_VGA05 Fld(12,20,AC_MSKW32)//[31:20]
    #define FLD_CSYNC_CT_THU Fld(2,18,AC_MSKB2)//[19:18]
    #define FLD_CYSNC_CT_THL Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_CSYNC_CONT_THU Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CSYNC_CONT_THL Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_6_REGISTER (PDWNC_IO_BASE + 0x418)
    #define FLD_RESERVE_VGA06 Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_HLEN_USE_VMASKX Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_VMASK_S Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_VMASK_E Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_7_REGISTER (PDWNC_IO_BASE + 0x41C)
    #define FLD_CSYNC_CONT_SLICE_THH Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_V_IIR_INIT Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_H_IIR_INIT Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_8_REGISTER (PDWNC_IO_BASE + 0x420)
    #define FLD_RESERVE_VGA08 Fld(5,27,AC_MSKB3)//[31:27]
    #define FLD_FREERUN_CNT_UNLOCK Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_CSYNC_CONT_THH Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_FREERUN_CNT_TH Fld(24,0,AC_MSKDW)//[23:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_9_REGISTER (PDWNC_IO_BASE + 0x424)
    #define FLD_RESERVE_VGA09 Fld(5,27,AC_MSKB3)//[31:27]
    #define FLD_HVLEN_BND_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_HVLEN_BND_TYPE Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_HLEN_LOBND Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_HLEN_UPBND Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_CONTROL_A_REGISTER (PDWNC_IO_BASE + 0x428)
    #define FLD_RESERVE_VGA0A Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_VLEN_LOBOND Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_VLEN_UPBOND Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_STATUS_0_REGISTER (PDWNC_IO_BASE + 0x430)
    #define FLD_SYNC_STABLE Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_H_STABLE Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_V_STABLE Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_CV_STABLE Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_SOGH_STABLE Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_CSYNC_ACT Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_HSYNC_ACT Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_VSYNC_ACT Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_H_LEN Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_V_LEN Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_STATUS_1_REGISTER (PDWNC_IO_BASE + 0x434)
    #define FLD_VWIDTH_MEAS_7_0 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_H_LEN_AVG Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_V_LEN_AVG Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_STATUS_2_REGISTER (PDWNC_IO_BASE + 0x438)
    #define FLD_SEP_STABLE Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_CSYNC_STABLE Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SOG_STABLE Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SOGV_STABLE Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_VWIDTH_MEAS_11_8 Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_CV_LEN_AVG Fld(12,12,AC_MSKW21)//[23:12]
    #define FLD_CV_LEN Fld(12,0,AC_MSKW10)//[11:0]
#define PDWNC_VGA_WAKE_UP_STATUS_3_REGISTER (PDWNC_IO_BASE + 0x43C)
    #define FLD_VSYNC_SEL_REG_W Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HSYNC_SEL_REG_W Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_STATE Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_IOEXT_INCFG (PDWNC_IO_BASE + 0x600)
    #define FLD_IOEXT_IN_CLOCK_DIVIDER Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_IOEXT_IN_DATA_LENGTH Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_IOEXT_IN_LOAD_LENGTH Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_IOEXT_IN_WAIT_LENGTH Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IOEXT_INTRIG (PDWNC_IO_BASE + 0x604)
    #define FLD_IOEXT_IN_IOEXT_IN_TRIG Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_IOEXT_DATAIN (PDWNC_IO_BASE + 0x608)
    #define FLD_IOEXT_IN_INPUT_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_IOEXT_OUTCFG0 (PDWNC_IO_BASE + 0x60C)
    #define FLD_IOEXT_OUT_CLOCK_DIVIDER Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_IOEXT_OUT_DATA_LENGTH Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_IOEXT_OUT_LATCHUP_LENGTH Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_IOEXT_OUT_WAIT_LENGTH Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_IOEXT_OUTCFG1 (PDWNC_IO_BASE + 0x610)
    #define FLD_AUTO_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_IOEXT_OUTTRIG (PDWNC_IO_BASE + 0x614)
    #define FLD_IOEXT_OUT_TRIG Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_IOEXT_DATAOUT_EN (PDWNC_IO_BASE + 0x618)
    #define FLD_OUTPUT_DATA_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_IOEXT_DATAOUT (PDWNC_IO_BASE + 0x61C)
    #define FLD_OUTPUT_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV4 (PDWNC_IO_BASE + 0x620)
    #define FLD_RESRV4 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV5 (PDWNC_IO_BASE + 0x624)         /*note: Byte0 Save RebootReason.*/
    #define FLD_RESRV5 Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_RG_WDT_DRAMSR Fld(1,8,AC_MSKB1)//[8:8]
#define PDWNC_RESRV6 (PDWNC_IO_BASE + 0x628)         /*note: Save DRAM PLL BAND.*/
    #define FLD_RESRV6 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV7 (PDWNC_IO_BASE + 0x62C)         /*note: Save DRAM PLL BAND.*/
    #define FLD_RESRV7 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_RESRV8 (PDWNC_IO_BASE + 0x630)   /*note: use for recover PTP initial value.*/
    #define FLD_RESRV8 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_TZ_RESERVED_0 (PDWNC_IO_BASE + 0x634)
    #define FLD_TZ_RESERVED0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_TZ_RESERVED_1 (PDWNC_IO_BASE + 0x638)
    #define FLD_TZ_RESERVED1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_TZ_RESERVED_2 (PDWNC_IO_BASE + 0x63C)
    #define FLD_TZ_RESERVED2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOOUT0 (PDWNC_IO_BASE + 0x640)
    #define FLD_PD_GPIO_OUT0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOOUT1 (PDWNC_IO_BASE + 0x644)
    #define FLD_PD_GPIO_OUT1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOOUT2 (PDWNC_IO_BASE + 0x648)
    #define FLD_PD_GPIO_OUT2 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_GPIOEN0 (PDWNC_IO_BASE + 0x64C)
    #define FLD_PD_GPIO_EN0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOEN1 (PDWNC_IO_BASE + 0x650)
    #define FLD_PD_GPIO_EN1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOEN2 (PDWNC_IO_BASE + 0x654)
    #define FLD_CPU_URTX_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_PD_GPIO_EN2 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_GPIOIN0 (PDWNC_IO_BASE + 0x658)
    #define FLD_PD_GPIO_IN0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOIN1 (PDWNC_IO_BASE + 0x65C)
    #define FLD_PD_GPIO_IN1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_GPIOIN2 (PDWNC_IO_BASE + 0x660)
    #define FLD_PD_GPIO_IN2 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_PDIO_CFG0 (PDWNC_IO_BASE + 0x664)
    #define FLD_DEGCNT Fld(8,16,AC_FULLB2)//[23:16]
#define PDWNC_PDIO_CFG1 (PDWNC_IO_BASE + 0x668)
    #define FLD_EXTIO_POL1 Fld(30,0,AC_MSKDW)//[29:0]
#define PDWNC_EXINT2ED0 (PDWNC_IO_BASE + 0x66C)
    #define FLD_EXINT_2ED0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXINTLEV0 (PDWNC_IO_BASE + 0x670)
    #define FLD_EXINT_LEV0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXINTPOL0 (PDWNC_IO_BASE + 0x674)
    #define FLD_EXINT_POL0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXINT2ED1 (PDWNC_IO_BASE + 0x678)
    #define FLD_EXINT_2ED1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXINTLEV1 (PDWNC_IO_BASE + 0x67C)
    #define FLD_EXINT_LEV1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_EXINTPOL1 (PDWNC_IO_BASE + 0x680)
    #define FLD_EXINT_POL1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PINMUX0 (PDWNC_IO_BASE + 0x684)
    #define FLD_PDMUX0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PINMUX1 (PDWNC_IO_BASE + 0x688)
    #define FLD_PDMUX1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PINMUX2 (PDWNC_IO_BASE + 0x68C)
    #define FLD_PDMUX2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PINMUX3 (PDWNC_IO_BASE + 0x690)
    #define FLD_PDMUX3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PADCFG0 (PDWNC_IO_BASE + 0x694)
    #define FLD_HDMI_0_SDA Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_MHL_SENCE Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_MHL_SENCE_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_HDMI_CEC_1 Fld(6,0,AC_MSKB0)//[5:0]
    #define FLD_HDMI_CEC_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HDMI_CEC_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_HDMI_CEC_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDMI_CEC_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_HDMI_CEC_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_HDMI_CEC_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PADCFG1 (PDWNC_IO_BASE + 0x698)
    #define FLD_HDMI_1_SDA_SR Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_HDMI_1_HPD Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_HDMI_1_PWR5V Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_HDMI_0_SCL_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HDMI_0_SCL_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_HDMI_0_SCL_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDMI_0_SCL_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_HDMI_0_SCL_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_HDMI_0_SCL_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PADCFG2 (PDWNC_IO_BASE + 0x69C)
    #define FLD_HDMI_2_SDA_SR Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_HDMI_2_HPD Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_HDMI_2_PWR5V Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_HDMI_1_SCL_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HDMI_1_SCL_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_HDMI_1_SCL_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDMI_1_SCL_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_HDMI_1_SCL_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_HDMI_1_SCL_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PADCFG3 (PDWNC_IO_BASE + 0x6A0)
    #define FLD_HDMI_3_SDA Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_HDMI_3_HPD Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_HDMI_3_PWR5V Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_HDMI_2_SCL_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HDMI_2_SCL_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_HDMI_2_SCL_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDMI_2_SCL_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_HDMI_2_SCL_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_HDMI_2_SCL_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PADCFG4 (PDWNC_IO_BASE + 0x6A4)
    #define FLD_LED_PWM2_SMT Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_LED_PWM2_PD Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_LED_PWM2_PU Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_LED_PWM2_SR Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_LED_PWM2_E4 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_LED_PWM2_E2 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_LED_PWM1_SMT Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_LED_PWM1_PD Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_LED_PWM1_PU Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_LED_PWM1_SR Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_LED_PWM1_E4 Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_LED_PWM1_E2 Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_LED_PWM0_SMT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_LED_PWM0_PD Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_LED_PWM0_PU Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_LED_PWM0_SR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_LED_PWM0_E4 Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_LED_PWM0_E2 Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_HDMI_3_SCL_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_HDMI_3_SCL_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_HDMI_3_SCL_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_HDMI_3_SCL_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_HDMI_3_SCL_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_HDMI_3_SCL_E2 Fld(1,0,AC_MSKB0)//[0:0]

//Page VDOIN_SYS_5
#define PDWNC_PADCFG5 (PDWNC_IO_BASE + 0x6A8)
    #define FLD_U0RX Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPWRSTB Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_IR Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_LED_PWM3_SMT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_LED_PWM3_PD Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_LED_PWM3_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_LED_PWM3_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_LED_PWM3_E4 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_LED_PWM3_E2 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_PADCFG6 (PDWNC_IO_BASE + 0x6AC)
    #define FLD_STB_SCL Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_VGA_SDA Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_VGA_SCL Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_U0TX Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG7 (PDWNC_IO_BASE + 0x6B0)
    #define FLD_SRVAD Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_PHY_LED1 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_PHY_LED0 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_STB_SDA Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG8 (PDWNC_IO_BASE + 0x6B4)
    #define FLD_OPCTRL3 Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPCTRL2 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_OPCTRL1 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL0 Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG9 (PDWNC_IO_BASE + 0x6B8)
    #define FLD_OPCTRL7 Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPCTRL6 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_OPCTRL5 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL4 Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG10 (PDWNC_IO_BASE + 0x6BC)
    #define FLD_OPCTRL11 Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPCTRL10 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_OPCTRL9 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL8 Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG11 (PDWNC_IO_BASE + 0x6C0)
    #define FLD_OPCTRL15 Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPCTRL14 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_OPCTRL13 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL12 Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG12 (PDWNC_IO_BASE + 0x6C4)
    #define FLD_OPCTRL19 Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPCTRL18 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_OPCTRL17 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL16 Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG13 (PDWNC_IO_BASE + 0x6C8)
    #define FLD_OPCTRL23 Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_OPCTRL22 Fld(6,16,AC_MSKB2)//[21:16]
    #define FLD_OPCTRL21 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL20 Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_PADCFG14 (PDWNC_IO_BASE + 0x6CC)
    #define FLD_HDMI_CEC_2 Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_OPCTRL24 Fld(6,0,AC_MSKB0)//[5:0]
    #define FLD_HDMI_CEC2_SMT Fld(1,13,AC_MSKB1)//[5:5]
    #define FLD_HDMI_CEC2_PD Fld(1,12,AC_MSKB1)//[4:4]
    #define FLD_HDMI_CEC2_PU Fld(1,11,AC_MSKB1)//[3:3]
    #define FLD_HDMI_CEC2_SR Fld(1,10,AC_MSKB1)//[2:2]
    #define FLD_HDMI_CEC2_E4 Fld(1,9,AC_MSKB1)//[1:1]
    #define FLD_HDMI_CEC2_E2 Fld(1,8,AC_MSKB1)//[0:0]
#define PDWNC_PADCFG15 (PDWNC_IO_BASE + 0x6D0)
    #define FLD_HDMI_1KIO_CTL Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PADRDSEL0 (PDWNC_IO_BASE + 0x6DC)
    #define FLD_RDSEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PADRDSEL1 (PDWNC_IO_BASE + 0x6E0)
    #define FLD_RDSEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PADTDSEL0 (PDWNC_IO_BASE + 0x6E4)
    #define FLD_TDSEL0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PADTDSEL1 (PDWNC_IO_BASE + 0x6E8)
    #define FLD_TDSEL1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_PINMUX4 (PDWNC_IO_BASE + 0x6F0)
    #define FLD_PDMUX4 Fld(32,0,AC_FULLDW)//[31:0]

//Page PDWNC_4
#define PDWNC_PINMUX5 (PDWNC_IO_BASE + 0x6F4)
    #define FLD_PDMUX5 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_TZ_CFG (PDWNC_IO_BASE + 0x6FC)
    #define FLD_SHARE_SRAM_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SHARE_SRAM_ENABLE_1 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_YEAR (PDWNC_IO_BASE + 0x700)
    #define FLD_YEAR_HI Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_YEAR_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_MONTH (PDWNC_IO_BASE + 0x704)
    #define FLD_MN_HI Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_MN_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_DAY (PDWNC_IO_BASE + 0x708)
    #define FLD_DAY_HI Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_DAY_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_WEEK (PDWNC_IO_BASE + 0x70C)
    #define FLD_WEEK Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_HOUR (PDWNC_IO_BASE + 0x710)
    #define FLD_HR_HI Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_HR_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_MINUTE (PDWNC_IO_BASE + 0x714)
    #define FLD_MIN_HI Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_MIN_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_SECOND (PDWNC_IO_BASE + 0x718)
    #define FLD_SEC_HI Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_SEC_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_AYEAR (PDWNC_IO_BASE + 0x71C)
    #define FLD_AYEAR_HI Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_AYEAR_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_AMONTH (PDWNC_IO_BASE + 0x720)
    #define FLD_AMN_HI Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_AMN_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_ADAY (PDWNC_IO_BASE + 0x724)
    #define FLD_ADAY_HI Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_ADAY_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_AWEEK (PDWNC_IO_BASE + 0x728)
    #define FLD_AWEEK Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AHOUR (PDWNC_IO_BASE + 0x72C)
    #define FLD_AHR_HI Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_AHR_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_AMINUTE (PDWNC_IO_BASE + 0x730)
    #define FLD_AMIN_HI Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_AMIN_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_ASECOND (PDWNC_IO_BASE + 0x734)
    #define FLD_ASEC_HI Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_ASEC_LO Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_ALMINT (PDWNC_IO_BASE + 0x738)
    #define FLD_ACMP_EN Fld(7,1,AC_MSKB0)//[7:1]
    #define FLD_AI_EN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_RTCCTL (PDWNC_IO_BASE + 0x73C)
    #define FLD_FLAG Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_PASS Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RTCSIM Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_H24 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_STOP Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_LEAPYEAR (PDWNC_IO_BASE + 0x744)
    #define FLD_LY_REG Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_PROT (PDWNC_IO_BASE + 0x748)
    #define FLD_PROT Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_AWEEK2 (PDWNC_IO_BASE + 0x750)
    #define FLD_AWEEK_2 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AWEEK3 (PDWNC_IO_BASE + 0x754)
    #define FLD_AWEEK_3 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AWEEK4 (PDWNC_IO_BASE + 0x758)
    #define FLD_AWEEK_4 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AWEEK5 (PDWNC_IO_BASE + 0x75C)
    #define FLD_AWEEK_5 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AWEEK6 (PDWNC_IO_BASE + 0x760)
    #define FLD_AWEEK_6 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AWEEK7 (PDWNC_IO_BASE + 0x764)
    #define FLD_AWEEK_7 Fld(3,0,AC_MSKB0)//[2:0]
#define PDWNC_AWEEK_ENABLE (PDWNC_IO_BASE + 0x768)
    #define FLD_AWEEK_ENABLE Fld(7,0,AC_MSKB0)//[6:0]

//Page RS232_PD_RISC
#define PDWNC_DATAW (PDWNC_IO_BASE + 0x800)
    #define FLD_DATA Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_STAB (PDWNC_IO_BASE + 0x804)
    #define FLD_TRANS_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_P_ERR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_END_ERR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_WR_ALLOW Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RD_ALLOW Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_UART_PD_INT_EN (PDWNC_IO_BASE + 0x80C)
    #define FLD_T8032DATAE Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RISCDATAE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OVRUN_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_TBUFE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_TOUTE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RBUFE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RXD_ERRE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_INT_ID (PDWNC_IO_BASE + 0x810)
    #define FLD_T8032DATA Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RISCDATA Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_OVRUN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_MRI Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_TBUF Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_TOUT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RBUF Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RXD_ERR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_RS232_MODE (PDWNC_IO_BASE + 0x818)
    #define FLD_RS232_MODE Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_BUFFER_SIZE (PDWNC_IO_BASE + 0x81C)
    #define FLD_BUFFER_SIZE Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_CCR (PDWNC_IO_BASE + 0x830)
    #define FLD_BAUD_RATE Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_BREAK Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_P_STICK Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_P_EVEN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_CHECK_PARITY Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_DIS_RX_ZERO Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_STOP_BIT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_BIT_LENGTH Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_UART_PD_STATUS (PDWNC_IO_BASE + 0x834)
    #define FLD_BREAK_IN4 Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_END_ERR4 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_P_ERR4 Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_TXD_BUF_STATE Fld(5,8,AC_MSKB1)//[12:8]
    #define FLD_BREAK_IN Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_END_ERR1 Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_P_ERR1 Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RXD_BUF_STATE Fld(5,0,AC_MSKB0)//[4:0]
#define PDWNC_BCR (PDWNC_IO_BASE + 0x838)
    #define FLD_TIME_OUT_CYCLE Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_CLEAR_TBUF Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_CLEAR_RBUF Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RXD_BUF_TRIG_LEVEL Fld(5,0,AC_MSKB0)//[4:0]

#define PDWNC_CONCFG0 (PDWNC_IO_BASE + 0x900)
    #define FLD_RG_CON_NOR_RSTB_CONTRL_I Fld(2,16,AC_MSKB2)//[17:16]
    #define FLD_RG_CON_DCMETER_SEL_I Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_CONCFG1 (PDWNC_IO_BASE + 0x904)
    #define FLD_RG_CON_RESERVED_1 Fld(8,8,AC_FULLB1)//[15:8]
    //#define FLD_RG_CON_RESERVED_0 Fld(7,1,AC_MSKB0)//[7:1]
    #define FLD_RG_HOTBOOT_LOG      Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_DIS_SUSPEND_WDT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_DIS_HOTBOOT_WDT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_DMSUS_RESERVED Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CONCFG2 (PDWNC_IO_BASE + 0x908)
    #define FLD_RG_DMSUS Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_LDOCFG0 (PDWNC_IO_BASE + 0x90C)
    #define FLD_RG_LDO_ABIST_PWD Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SADCCFG0 (PDWNC_IO_BASE + 0x914)
    #define FLD_RG_SRV_BIAS_OPTION Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_SRV_MODE_SEL Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_BUFIN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_SRV_INBUFF_BP Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_SRV_UGB Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_SRV_PWD_B Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_SRV_RES Fld(8,16,AC_FULLB2)//[23:16]
#define PDWNC_VGACFG0 (PDWNC_IO_BASE + 0x918)
    #define FLD_RG_VMUX_PWD Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_RGB_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_HDTV1_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_HDTV0_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RGBHDTV01_EN Fld(3, 28, AC_MSKB3)  //[30:28]
    #define FLD_RG_SC_SCART Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_DESPIKE Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_AUTOBIAS_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_CVBSINVGA Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_RG_RGB_REVERSE Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_HDTV1_REVERSE Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_HDTV0_REVERSE Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_HDMIIB_PWD Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_VDACIB_PWD Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_HSYNC_GPI_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_VSYNC_GPI_EN Fld(1,0,AC_MSKB0)//[0:0]
	#define VGAMUX_RGB_EN 4
	#define VGAMUX_HDTV1_EN 2
	#define VGAMUX_HDTV0_EN 1
#define PDWNC_VGACFG1 (PDWNC_IO_BASE + 0x91C)
    #define FLD_RG_VSYNC_EN Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_HSYNC_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_CVBS_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_SCART_EN Fld(3,24,AC_MSKB3)//[26:24]
    #define FLD_RG_SOY1_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_SOY0_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_SOY1_SOY0_EN Fld(2, 21, AC_MSKB2) //[22:21]
    #define FLD_RG_SOG_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_SYNC_PWD Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RG_SYNC_DESPK_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_FB_AB_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_BYPS_SYNCPROSR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RG_BYPS_SOGYPGA Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_VGA_TEST_EN Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_RG_SYNC_TESTO_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_RG_TSOGY_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_RG_DIG_TST_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_SYNC_TSTSEL Fld(4,4,AC_MSKB0)//[7:4]
#define PDWNC_VGACFG2 (PDWNC_IO_BASE + 0x920)
    #define FLD_RG_VREFMON Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_RG_FEOUT_MONEN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_CLAMP_MONEN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_VGAVREF_MONEN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_VGA_TESTBUF_PWD Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_VREF_CVBS Fld(3,17,AC_MSKB2)//[19:17]
    #define FLD_RG_SHIFT_PWD Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_OFFCUR_PWD Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_RG_OFFCUR Fld(3,12,AC_MSKB1)//[14:12]
    #define FLD_RG_PSAV_REV Fld(12,0,AC_MSKW10)//[11:0]
    #define FLD_RG_PSAV_REV_BG Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_RG_PSAV_REV_INPUT_PORT Fld(1,4,AC_MSKB0)//[4:4]
#define PDWNC_VGACFG3 (PDWNC_IO_BASE + 0x924)
    #define FLD_RG_SOGY_SINK Fld(6,24,AC_MSKB3)//[29:24]
    #define FLD_RG_SOGY_SOURCE Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_RG_SOGY_SINK_PWD Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_RG_SOGY_SORS_PWD Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RG_SOGY_RGAIN Fld(2,12,AC_MSKB1)//[13:12]
    #define FLD_RG_SOGY_BW Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_CLAMPREFSEL Fld(2,4,AC_MSKB0)//[5:4]
#define PDWNC_VGACFG4 (PDWNC_IO_BASE + 0x928)
    #define FLD_RG_SYNCREV Fld(8,12,AC_MSKW21)//[19:12]
    #define FLD_RG_SYNC1_VTH Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_RG_SYNC1_VTL Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_RG_SYNC2_VTH Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_VGACFG5 (PDWNC_IO_BASE + 0x92C)
    #define FLD_RG_SYNC2_VTL Fld(4,28,AC_MSKB3)//[31:28]
#define PDWNC_VGACFG6 (PDWNC_IO_BASE + 0x930)
    #define FLD_RG_SYNCREV2 Fld(8,24,AC_FULLB3)//[31:24]

#define PDWNC_XTALCFG0 (PDWNC_IO_BASE + 0x934)
    #define FLD_RG_XTAL_AAC_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_RG_XTAL_AAC_AMP_VSEL Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_XTAL_GM Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_RG_XTAL_RC_BYPASS Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RG_XTAL_TMEN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_XTAL_RESERVED Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_TSENSE_CFG0 (PDWNC_IO_BASE + 0x93C)
    #define FLD_RG_BGR_UNCHOP Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_BGR_UNCHOP_PH Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_BGR_FSETUP Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_BGR_RSEL Fld(4,24,AC_MSKB3)//[27:24]
    #define FLD_RG_BGR_TS_PD Fld(4,20,AC_MSKB2)//[23:20]
    #define FLD_RG_BGR_TCTRL Fld(6,14,AC_MSKW21)//[19:14]
    #define FLD_RG_BGR_TEST_OSEL Fld(2,12,AC_MSKB1)//[13:12]
    #define FLD_RG_BGR_RSV Fld(8,4,AC_MSKW10)//[11:4]
    #define FLD_RG_TS2SRVDC Fld(2,0,AC_MSKB0)//[1:0]
#define PDWNC_ECBUS_CFG0 (PDWNC_IO_BASE + 0x940)
    #define FLD_RG_CBUS_0_LDO_IBIAS Fld(2,13,AC_MSKB1)//[14:13]
    #define FLD_RG_CBUS_0_LDO_IBIAS_SEL Fld(2,11,AC_MSKB1)//[12:11]
    #define FLD_RG_CBUS_0_LDO_VREF Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_RG_CBUS_0_LDO_VREF_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_CBUS_0_LDO_RESETVE Fld(7,0,AC_MSKB0)//[6:0]
#define PDWNC_ECBUS_CFG1 (PDWNC_IO_BASE + 0x944)
    #define FLD_RG_CBUS_0_PWD Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_RG_CBUS_0_PD0A Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_RG_CBUS_0_PD0B Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_CBUS_0_PD3 Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_RG_CBUS_0_PD2 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_CBUS_0_PD1 Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_CBUS_0_RDSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_RG_CBUS_0_TDSEL Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_RG_CBUS_0_EX1KAB Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_CBUS_0_EX1KB Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_RG_CBUS_0_EX1KA Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_CBUS_0_EX1K Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_RG_CBUS_0_SMT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_CBUS_0_PUPD Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_CBUS_0_IES Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_CBUS_0_PU Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_CBUS_0_SR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_CBUS_0_E8 Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_CBUS_0_E4 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_ECBUS_CFG2 (PDWNC_IO_BASE + 0x948)
    #define FLD_RG_CBUS_0_RESERVE Fld(32,0,AC_FULLDW)//[31:0]
    #define FLD_RG_HDMI_3_PWR5V_1KE Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_RG_HDMI_3_PWR5V_1KAB Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_HDMI_3_PWR5V_1KB Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_RG_HDMI_3_PWR5V_1KA Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_RG_HDMI_2_PWR5V_1KE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RG_HDMI_2_PWR5V_1KAB Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_RG_HDMI_2_PWR5V_1KB Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_RG_HDMI_2_PWR5V_1KA Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_RG_HDMI_1_PWR5V_1KE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_HDMI_1_PWR5V_1KAB Fld(2,0,AC_MSKB0)//[1:0]
    #define FLD_RG_HDMI_1_PWR5V_1KB Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_HDMI_1_PWR5V_1KA Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_ECBUS_CFG3 (PDWNC_IO_BASE + 0x94C)
    #define FLD_RG_HDMI_0PWR5V_RDSEL Fld(2,20,AC_MSKB2)//[21:20]
    #define FLD_RG_HDMI_0PWR5V_TDSEL Fld(4,16,AC_MSKB2)//[19:16]
    #define FLD_RG_HDMI_PWR5V_PD Fld(2,3,AC_MSKB0)//[4:3]
    #define FLD_RG_HDMI_0PWR5V Fld(6,0,AC_MSKB0)//[5:0]
#define PDWNC_ADOUT13 (PDWNC_IO_BASE + 0x950)
    #define FLD_ADOUT13 Fld(12,0,AC_MSKW10)//[11:0]

//Page VDOIN_SYS_6
#define PDWNC_ADOUT14 (PDWNC_IO_BASE + 0x954)
    #define FLD_ADOUT14 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT15 (PDWNC_IO_BASE + 0x958)
    #define FLD_ADOUT15 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT16 (PDWNC_IO_BASE + 0x95C)
    #define FLD_ADOUT16 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT17 (PDWNC_IO_BASE + 0x960)
    #define FLD_ADOUT17 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT18 (PDWNC_IO_BASE + 0x964)
    #define FLD_ADOUT18 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT19 (PDWNC_IO_BASE + 0x968)
    #define FLD_ADOUT19 Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1A (PDWNC_IO_BASE + 0x96C)
    #define FLD_ADOUT1A Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1B (PDWNC_IO_BASE + 0x970)
    #define FLD_ADOUT1B Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1C (PDWNC_IO_BASE + 0x974)
    #define FLD_ADOUT1C Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1D (PDWNC_IO_BASE + 0x978)
    #define FLD_ADOUT1D Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1E (PDWNC_IO_BASE + 0x97C)
    #define FLD_ADOUT1E Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_ADOUT1F (PDWNC_IO_BASE + 0x980)
    #define FLD_ADOUT1F Fld(10,2,AC_MSKW10)//[11:2]
#define PDWNC_XPLL_CFG0 (PDWNC_IO_BASE + 0x9B0)
    #define FLD_RG_XPLL_POSDIV Fld(3,28,AC_MSKB3)//[30:28]
    #define FLD_RG_XPLL_PREDIV Fld(2,26,AC_MSKB3)//[27:26]
    #define FLD_RG_XPLL_LVRD_EN Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_RG_XPLL_MONCK_EN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_RG_XPLL_MONVC_EN Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_RG_XPLL_MONREF_EN Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_RG_XPLL_SDM_FRA_EN Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_RG_XPLL_SDM_PCW_CHG Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_RG_XPLL_SDM_PCW Fld(7,13,AC_MSKW21)//[19:13]
    #define FLD_RG_XPLL_DET_EN Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_RG_XPLL_BS Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_RG_XPLL_RESERVE Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_XPLL_CFG1 (PDWNC_IO_BASE + 0x9B4)
    #define FLD_RG_XPLL_CKSEL_MON Fld(3,29,AC_MSKB3)//[31:29]
    #define FLD_RG_XPLL_REFCK_MON_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_RG_XPLL_25M_MON_EN Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_RG_XPLL_25M_DIV Fld(2,24,AC_MSKB3)//[25:24]
    #define FLD_RG_XPLL_DIV2_SEL Fld(3,21,AC_MSKB2)//[23:21]
    #define FLD_RG_XPLL_XPLL_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_XPLL_SDM_ISO_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_XPLL_SDM_PWR_ON Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_XPLL_CFG2 (PDWNC_IO_BASE + 0x9B8)
    #define FLD_RG_ETHPLL_EN_SW_CTRL Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_RG_ETHPLL_EN_SW_CTRL_SEL Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_XPLL_SW_CTRL_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_XPLL_CTRL_SW_RST Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_DDCCI_CFG (PDWNC_IO_BASE + 0xA00)
    #define FLD_DDCCI_DE_CNT Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_DDCCI_CNT_RST Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_DDCCI_ODRAIN Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_DDCCI_DEG_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_DDCCI_OFF Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_DDCCI_DATALEN Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_DDCCI_DEV_ADDR Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_DDCCI_INTEN (PDWNC_IO_BASE + 0xA04)
    #define FLD_INT_R16_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_INT_R8_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_INT_RDONE_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_INT_W16_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_INT_W8_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_INT_WDONE_EN Fld(1,0,AC_MSKB0)//[0:0]
#if 1 
	#define FLD_INT_ALL_EN Fld(6, 0, AC_MSKB0) //[5:0]
#endif
#define PDWNC_DDCCI_INTCLR (PDWNC_IO_BASE + 0xA08)
    #define FLD_INT_R16_CLR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_INT_R8_CLR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_INT_RDONE_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_INT_W16_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_INT_W8_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_INT_WDONE_CLR Fld(1,0,AC_MSKB0)//[0:0]
#if 1
	#define FLD_INT_ALL_CLR Fld(6, 0, AC_MSKB0) //[5:0]
#endif
#define PDWNC_DDCCI_INTST (PDWNC_IO_BASE + 0xA0C)
    #define FLD_INT_R16_ST Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_INT_R8_ST Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_INT_RDONE_ST Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_INT_W16_ST Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_INT_W8_ST Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_INT_WDONE_ST Fld(1,0,AC_MSKB0)//[0:0]
#if 1 
	#define FLD_INT_ALL_ST Fld(6, 0, AC_MSKB0) //[5:0]
#endif   
#define PDWNC_DDCCI_WDATA0 (PDWNC_IO_BASE + 0xA10)
    #define FLD_WDATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_WDATA1 (PDWNC_IO_BASE + 0xA14)
    #define FLD_WDATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_WDATA2 (PDWNC_IO_BASE + 0xA18)
    #define FLD_WDATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_WDATA3 (PDWNC_IO_BASE + 0xA1C)
    #define FLD_WDATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_RDATA0 (PDWNC_IO_BASE + 0xA20)
    #define FLD_RDATA0 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_RDATA1 (PDWNC_IO_BASE + 0xA24)
    #define FLD_RDATA1 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_RDATA2 (PDWNC_IO_BASE + 0xA28)
    #define FLD_RDATA2 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_DDCCI_RDATA3 (PDWNC_IO_BASE + 0xA2C)
    #define FLD_RDATA3 Fld(32,0,AC_FULLDW)//[31:0]
#define PDWNC_SM0CTL2 (PDWNC_IO_BASE + 0xC00)
    #define FLD_SIFM0_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SIFM0_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM0CTL3 (PDWNC_IO_BASE + 0xC04)
	#define FLD_SIFM0_ACK1_DEVADDR_ACK Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SIFM0_ACK1 Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SIFM0_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SIFM0_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SIFM0_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SIFM0_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SIFM0_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SIFM0_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SIFM0_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM0D2 (PDWNC_IO_BASE + 0xC08)
    #define FLD_SIFM0_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D3 (PDWNC_IO_BASE + 0xC0C)
    #define FLD_SIFM0_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D4 (PDWNC_IO_BASE + 0xC10)
    #define FLD_SIFM0_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D5 (PDWNC_IO_BASE + 0xC14)
    #define FLD_SIFM0_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D6 (PDWNC_IO_BASE + 0xC18)
    #define FLD_SIFM0_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D7 (PDWNC_IO_BASE + 0xC1C)
    #define FLD_SIFM0_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0D8 (PDWNC_IO_BASE + 0xC20)
    #define FLD_SIFM0_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM0_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM0_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM0_DATA32 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM0SDEV (PDWNC_IO_BASE + 0xC24)
    #define FLD_SIFM0_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1CTL2 (PDWNC_IO_BASE + 0xC28)
    #define FLD_SIFM1_SCL_RISE_VALUE Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SIFM1_SCL_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM1CTL3 (PDWNC_IO_BASE + 0xC2C)
	#define FLD_SIFM1_ACK1_DEVADDR_ACK Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SIFM1_ACK1 Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SIFM1_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SIFM1_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SIFM1_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SIFM1_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SIFM1_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SIFM1_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SIFM1_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM1D2 (PDWNC_IO_BASE + 0xC30)
    #define FLD_SIFM1_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D3 (PDWNC_IO_BASE + 0xC34)
    #define FLD_SIFM1_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D4 (PDWNC_IO_BASE + 0xC38)
    #define FLD_SIFM1_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D5 (PDWNC_IO_BASE + 0xC3C)
    #define FLD_SIFM1_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D6 (PDWNC_IO_BASE + 0xC40)
    #define FLD_SIFM1_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D7 (PDWNC_IO_BASE + 0xC44)
    #define FLD_SIFM1_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1D8 (PDWNC_IO_BASE + 0xC48)
    #define FLD_SIFM1_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM1_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM1_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM1_DATA32 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM1SDEV (PDWNC_IO_BASE + 0xC4C)
    #define FLD_SIFM1_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2CTL2 (PDWNC_IO_BASE + 0xC50)
    #define FLD_SIFM1_SCL_RISE_VALUE_2 Fld(12,16,AC_MSKW32)//[27:16]
    #define FLD_SIFM1_SCL_MODE_2 Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM2CTL3 (PDWNC_IO_BASE + 0xC54)
    #define FLD_SIFM2_ACK Fld(21,11,AC_MSKDW)//[31:11]
    #define FLD_SIFM2_WD_STOP_MODE Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_SIFM2_STR_WD_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_SIFM2_STR_WD_STOP_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_SIFM2_RDNACK_STOP_MODE Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_SIFM2_STR_RDACK_MODE Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_SIFM2_STR_RDNACK_STOP_MODE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_SIFM2_SDEV_MODE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_SM2D2 (PDWNC_IO_BASE + 0xC58)
    #define FLD_SIFM2_DATA11 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA10 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA9 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA8 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2D3 (PDWNC_IO_BASE + 0xC5C)
    #define FLD_SIFM2_DATA15 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA14 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA13 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA12 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2D4 (PDWNC_IO_BASE + 0xC60)
    #define FLD_SIFM2_DATA19 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA18 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA17 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA16 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2D5 (PDWNC_IO_BASE + 0xC64)
    #define FLD_SIFM2_DATA23 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA22 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA21 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA20 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2D6 (PDWNC_IO_BASE + 0xC68)
    #define FLD_SIFM2_DATA27 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA26 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA25 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA24 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2D7 (PDWNC_IO_BASE + 0xC6C)
    #define FLD_SIFM2_DATA31 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA30 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA29 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA28 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_SM2D8 (PDWNC_IO_BASE + 0xC70)
    #define FLD_SIFM2_DATA35 Fld(8,24,AC_FULLB3)//[31:24]
    #define FLD_SIFM2_DATA34 Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_SIFM2_DATA33 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_SIFM2_DATA32 Fld(8,0,AC_FULLB0)//[7:0]

//Page VDOIN_SYS_7
#define PDWNC_SM2SDEV (PDWNC_IO_BASE + 0xC74)
    #define FLD_SIFM2_DEV_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CBUS_WBUF0 (PDWNC_IO_BASE + 0xD00)
    #define FLD_CBUS_WBUF0 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF1 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF2 (PDWNC_IO_BASE + 0xD04)
    #define FLD_CBUS_WBUF2 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF3 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF4 (PDWNC_IO_BASE + 0xD08)
    #define FLD_CBUS_WBUF4 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF5 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF6 (PDWNC_IO_BASE + 0xD0C)
    #define FLD_CBUS_WBUF6 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF7 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF8 (PDWNC_IO_BASE + 0xD10)
    #define FLD_CBUS_WBUF8 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF9 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF10 (PDWNC_IO_BASE + 0xD14)
    #define FLD_CBUS_WBUF10 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF11 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF12 (PDWNC_IO_BASE + 0xD18)
    #define FLD_CBUS_WBUF12 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF13 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF14 (PDWNC_IO_BASE + 0xD1C)
    #define FLD_CBUS_WBUF14 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF15 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF16 (PDWNC_IO_BASE + 0xD20)
    #define FLD_CBUS_WBUF16 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF17 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF18 (PDWNC_IO_BASE + 0xD24)
    #define FLD_CBUS_WBUF18 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF19 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF20 (PDWNC_IO_BASE + 0xD28)
    #define FLD_CBUS_WBUF20 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF21 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_WBUF22 (PDWNC_IO_BASE + 0xD2C)
    #define FLD_CBUS_WBUF22 Fld(11,0,AC_MSKW10)//[10:0]
    #define FLD_CBUS_WBUF23 Fld(11,16,AC_MSKW32)//[26:16]
#define PDWNC_CBUS_RBUF (PDWNC_IO_BASE + 0xD30)
    #define FLD_CBUS_RBUF Fld(11,0,AC_MSKW10)//[10:0]
#define PDWNC_CBUS_LINK_00 (PDWNC_IO_BASE + 0xD34)
    #define FLD_RBUF_LVL_THR Fld(5,27,AC_MSKB3)//[31:27]
    #define FLD_IGNORE_PAR Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_DUPLEX Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_NRETRY Fld(6,18,AC_MSKB2)//[23:18]
    #define FLD_TRESP_HOLD Fld(4,14,AC_MSKW21)//[17:14]
    #define FLD_TWAIT Fld(4,10,AC_MSKB1)//[13:10]
    #define FLD_TREQ_HOLD Fld(4,6,AC_MSKW10)//[9:6]
    #define FLD_TX_NUM Fld(5,1,AC_MSKB0)//[5:1]
    #define FLD_TX_TRIG Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_LINK_01 (PDWNC_IO_BASE + 0xD38)
    #define FLD_ADP_BITIME_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_ADP_BITIME_RST Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_ADP_CONFIG1 Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_ADP_CONFIG2 Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_LINKTX_BITIME Fld(7,21,AC_MSKW32)//[27:21]
    #define FLD_CBUS_ACK_0_MIN Fld(7,14,AC_MSKW21)//[20:14]
    #define FLD_CBUS_ACK_0_MAX Fld(7,7,AC_MSKW10)//[13:7]
    #define FLD_CBUS_ACK_FALL_MAX Fld(7,0,AC_MSKB0)//[6:0]

//Page VDOIN_SYS_7
#define PDWNC_CBUS_LINK_02 (PDWNC_IO_BASE + 0xD3C)
    #define FLD_LINKRX_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_FAKE_SOURCE Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_TREQ_ACK_CONT Fld(7,21,AC_MSKW32)//[27:21]
    #define FLD_LINK_TXDECISION Fld(7,14,AC_MSKW21)//[20:14]
    #define FLD_LINK_HALFTRAN_MAX Fld(7,7,AC_MSKW10)//[13:7]
    #define FLD_LINK_HALFTRAN_MIN Fld(7,0,AC_MSKB0)//[6:0]
#define PDWNC_CBUS_LINK_03 (PDWNC_IO_BASE + 0xD40)
    #define FLD_SW_RESET_MISC Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_SW_RESET_WAKE Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_SW_RESET_RX Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_SW_RESET_TX Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_LINK_BITIME_MAX Fld(7,21,AC_MSKW32)//[27:21]
    #define FLD_LINK_BITIME_MIN Fld(7,14,AC_MSKW21)//[20:14]
    #define FLD_LINK_SYNCDUTY_MAX Fld(7,7,AC_MSKW10)//[13:7]
    #define FLD_LINK_SYNCDUTY_MIN Fld(7,0,AC_MSKB0)//[6:0]
#define PDWNC_CBUS_LINK_04 (PDWNC_IO_BASE + 0xD44)
    #define FLD_LINK_ACK_MANU_EN Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_LINK_ACK_WIDTH Fld(7,21,AC_MSKW32)//[27:21]
    #define FLD_LINK_BITIME_MID Fld(7,14,AC_MSKW21)//[20:14]
    #define FLD_LINK_RXDECISION Fld(7,7,AC_MSKW10)//[13:7]
    #define FLD_RX_BT_TIMEOUT Fld(7,0,AC_MSKB0)//[6:0]
#define PDWNC_CBUS_LINK_05 (PDWNC_IO_BASE + 0xD48)
    #define FLD_DISCOVERY_EN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_WAKEUP_EN Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_WAKE_PUL_WID2_MAX Fld(10,20,AC_MSKW32)//[29:20]
    #define FLD_WAKE_PUL_WID1_MIN Fld(10,10,AC_MSKW21)//[19:10]
    #define FLD_WAKE_PUL_WID1_MAX Fld(10,0,AC_MSKW10)//[9:0]
#define PDWNC_CBUS_LINK_06 (PDWNC_IO_BASE + 0xD4C)
    #define FLD_WAKE_PUL_WID2_MIN Fld(10,22,AC_MSKW32)//[31:22]
    #define FLD_WAKE_TO_DISC_MIN Fld(11,11,AC_MSKW21)//[21:11]
    #define FLD_WAKE_TO_DISC_MAX Fld(11,0,AC_MSKW10)//[10:0]
#define PDWNC_CBUS_LINK_07 (PDWNC_IO_BASE + 0xD50)
    #define FLD_CBUS_OE Fld(1,29,AC_MSKB3)//[29:29]
    #define FLD_CBUS_DO Fld(1,28,AC_MSKB3)//[28:28]
    #define FLD_CBUS_DOE_SW Fld(1,27,AC_MSKB3)//[27:27]
    #define FLD_ZCBUS_DISCOVER_EN Fld(1,26,AC_MSKB3)//[26:26]
    #define FLD_ZCBUS_SINK_ON_CTRL Fld(3,23,AC_MSKW32)//[25:23]
    #define FLD_ZCBUS_HW Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_LDO_SWITCH Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_LDO_SWITCH_HW Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_DISC_PUL_WID_MIN Fld(10,10,AC_MSKW21)//[19:10]
    #define FLD_DISC_PUL_WID_MAX Fld(10,0,AC_MSKW10)//[9:0]
#define PDWNC_CBUS_LINK_08 (PDWNC_IO_BASE + 0xD54)
    #define FLD_LINKRX_TIMEOUT_INT_CLR Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_WBUF_TRIG_INT_CLR Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RBUF_TRIG_INT_CLR Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_CBUS_LOW_DISCONN_INT_CLR Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_CBUS_NEG_INT_CLR Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_CBUS_POS_INT_CLR Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_MONITOR_CMP_INT_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_CABLE_DISCONNECT_INT_CLR Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_CABLE_DETECT_INT_CLR Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_TX_ARB_FAIL_INT_CLR Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_TX_OK_INT_CLR Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TX_RETRY_TO_INT_CLR Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RBUF_LVL_THR_INT_CLR Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_WK_TIMEOUT_ST_INT_CLR Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_WAKEUP_ILL_WID_INT_CLR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_ILL_WAKE2DISC_INT_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_WAKEUP_DET_INT_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_DISC_DET_INT_CLR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_LINK_09 (PDWNC_IO_BASE + 0xD58)
    #define FLD_TREQ_ARB_CONT Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_CBUS_DRV_H_PRD Fld(5,20,AC_MSKW32)//[24:20]
    #define FLD_DISC_WID_CNT_TIMEOUT Fld(10,10,AC_MSKW21)//[19:10]
    #define FLD_WAKE_CNT_TIMEOUT Fld(10,0,AC_MSKW10)//[9:0]
#define PDWNC_CBUS_LINK_0A (PDWNC_IO_BASE + 0xD5C)
    #define FLD_LINKRX_ACK1_SYNC Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_LINKRX_DIS_TO Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_TX_ARB_BYPASS Fld(1,18,AC_MSKB2)//[18:18]
    #define FLD_RX_ARB_BYPASS Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_FORCE_NAK_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_FORCE_NAK_CNT Fld(5,11,AC_MSKB1)//[15:11]
    #define FLD_MON_CMP_SEL Fld(3,8,AC_MSKB1)//[10:8]
    #define FLD_MON_CMP_DATA Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_CBUS_LINK_0B (PDWNC_IO_BASE + 0xD60)
    #define FLD_INT_STA_MASK Fld(18,14,AC_MSKDW)//[31:14]
    #define FLD_CBUS_DISCONN_CNT_EN Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_RETRY_DISCONN_THR Fld(6,7,AC_MSKW10)//[12:7]
    #define FLD_CBUS_DISCONN_THR Fld(7,0,AC_MSKB0)//[6:0]
#define PDWNC_CBUS_LINK_0C (PDWNC_IO_BASE + 0xD64)
    #define FLD_CBUS_1K_CTRL Fld(2,30,AC_MSKB3)
    #define FLD_CDSENSE_FORCE1 Fld(1,25,AC_MSKB3)//[25:25]
    #define FLD_CDSENSE_GATED Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_CDSENSE_OFF_DEGLITCH Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_CDSENSE_ON_DEGLITCH Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_CDSENSE_P_DEGLITCH Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_LINKRX_BITIME Fld(7,14,AC_MSKW21)//[20:14]
    #define FLD_ADP_BITIME_MIN Fld(7,7,AC_MSKW10)//[13:7]
    #define FLD_ADP_BITIME_MAX Fld(7,0,AC_MSKB0)//[6:0]
#define PDWNC_CBUS_LINK_0D (PDWNC_IO_BASE + 0xD68)
    #define FLD_INT_MASK Fld(17,0,AC_MSKDW)//[16:0]
#define PDWNC_CBUS_STA_00 (PDWNC_IO_BASE + 0xD6C)
    #define FLD_LINK_BITIME Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_RBUF_LVL_LAT Fld(5,20,AC_MSKW32)//[24:20]
    #define FLD_LINKRX_TIMEOUT_INT Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_WBUF_PULS1_INT Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_RBUF_PULS1_INT Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_CBUS_LOW_DISCONN_INT Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_CBUS_NEG_INT Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_CBUS_POS_INT Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_MONITOR_CMP_INT Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_CABLE_DISCONNECT_INT Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_CABLE_DETECT_INT Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_TX_ARB_FAIL_INT Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_TX_OK_INT Fld(1,7,AC_MSKB0)//[7:7]
    #define FLD_TX_RETRY_TO_INT Fld(1,6,AC_MSKB0)//[6:6]
    #define FLD_RBUF_LVL_THR_INT Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_WK_TIMEOUT_ST_INT Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_WAKEUP_ILL_WID_INT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_ILL_WAKE2DISC_INT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_WAKEUP_DET_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_DISC_DET_INT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_STA_01 (PDWNC_IO_BASE + 0xD70)
    #define FLD_CBUS_IN Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_CBUS_CDSENSE Fld(1,30,AC_MSKB3)//[30:30]
    #define FLD_LINKRX_FSM Fld(5,12,AC_MSKW21)//[16:12]
    #define FLD_LINKTX_FSM Fld(5,7,AC_MSKW10)//[11:7]
    #define FLD_DISC_FSM Fld(3,4,AC_MSKB0)//[6:4]
    #define FLD_WAKEUP_FSM Fld(4,0,AC_MSKB0)//[3:0]
#define PDWNC_CBUS_LINK_BAK (PDWNC_IO_BASE + 0xD74)
    #define FLD_CBUS_DRV_H_PRD_ARB Fld(5,16,AC_MSKB2)//[20:16]
    #define FLD_CBUS_DRV_H_SEL Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_CBUS_OE_FAST1 Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_ADP_SYNC Fld(1,13,AC_MSKB1)//[13:13]
    #define FLD_CBUS_OE_FAST Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_CBUS_DEGLITCH Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_LINKRX_DIS_TO_ARB23 Fld(1,10,AC_MSKB1)//[10:10]
    #define FLD_LINK_ACK_WIDTH_UPPER Fld(7,3,AC_MSKW10)//[9:3]
    #define FLD_ARB_DRIVEH Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_TX_ARB2_DIS_CHK Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_TX_ARB1_DIS_CHK Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_LINK_BAK1 (PDWNC_IO_BASE + 0xD78)
    #define RG_PAD_CTRL_BY_ECBUS Fld(1,12,AC_MSKB1)//[12:12]
    #define RG_PU_ENABLE Fld(1,11,AC_MSKB1)//[11:11]
    #define RG_PU_ENABLE_SEL Fld(1,10,AC_MSKB1)//[10:10]
    #define RG_PUPD Fld(1,9,AC_MSKB1)//[9:9]
    #define RG_PUPD_SEL Fld(1,8,AC_MSKB1)//[8:8]
    #define RG_MHL_CABLE_CON Fld(1,7,AC_MSKB0)//[7:7]
    #define RG_MHL_CABLE_CON_SEL Fld(1,6,AC_MSKB0)//[6:6]
    #define RG_PWR_5V Fld(1,5,AC_MSKB0)//[5:5]
    #define RG_PWR_5V_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define RG_ECBUS_CTRL Fld(1,1,AC_MSKB0)//[1:1]
    #define RG_CBUS_CTRL_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_TRAN_00 (IO_PDWNC_BASE + 0xD80)
    #define FLD_RG_TRAN_TIMEOUT Fld(16,16,AC_MSKW32)//[11:11]
    #define FLD_RG_SCLK_DIV Fld(12,4,AC_MSKW10)//[10:10]
    #define FLD_RG_WAIT_LEVEL Fld(1,3,AC_MSKB0)//[9:3]
    #define FLD_RG_TRAN_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_TRAN_SPEED Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_CBUS_TRAN_HW_EN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_TRAN_01 (IO_PDWNC_BASE + 0xD84)
    #define FLD_RG_TRAN_INIT_STA_MASK Fld(13,16,AC_MSKW32)//[11:11]
    #define FLD_RG_CBUS_HW_SEL Fld(1,4,AC_MSKB0)//[04:04]
    #define FLD_RG_HW_TX_STOP Fld(1,3,AC_MSKB0)//[9:3]
    #define FLD_RG_SW_RESET_TRAN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_I2C_FORCE_OK Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_CBUS_MON_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_TRAN_02 (IO_PDWNC_BASE + 0xD88)
    #define FLD_RG_INT_MASK Fld(13,16,AC_MSKW32)//[28:16]
    #define FLD_RG_DDC_ERR_4_INT_CLR Fld(1,12,AC_MSKB1)//[11:11]
    #define FLD_RG_DDC_ERR_2_INT_CLR Fld(1,11,AC_MSKB1)//[11:11]
    #define FLD_RG_DDC_ERR_1_INT_CLR Fld(1,10,AC_MSKB1)//[11:11]
    #define FLD_RG_I2C_WR_START_INT_CLR Fld(1,9,AC_MSKB1)//[11:11]
    #define FLD_RG_I2C_WR_STOP_INT_CLR Fld(1,8,AC_MSKB1)//[11:11]
    #define FLD_RG_I2C_WR_DATA_INT_CLR Fld(1,7,AC_MSKB0)//[11:11]
    #define FLD_RG_I2C_RD_DATA_INT_CLR Fld(1,6,AC_MSKB0)//[11:11]
    #define FLD_RG_DATA_SEND_DONE_INT_CLR Fld(1,5,AC_MSKB0)//[11:11]
    #define FLD_RG_DATA_SEND_FAIL_INT_CLR Fld(1,4,AC_MSKB0)//[10:10]
    #define FLD_RG_HW_TRAN_SEND_TRIG_INT_CLR Fld(1,3,AC_MSKB0)//[9:3]
    #define FLD_RG_CBUS_DDC_WR_INT_CLR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_RG_HW_TRAN_SEND_OK_INT_CLR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_RG_HW_TRAN_SEND_FAIL_INT_CLR Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_CBUS_TRAN_STA (IO_PDWNC_BASE + 0xD8C)
    #define FLD_DDC_ERR_1_INT Fld(1,28,AC_MSKB3)//[11:11]
    #define FLD_DDC_ERR_2_INT Fld(1,27,AC_MSKB3)//[11:11]
    #define FLD_DDC_ERR_4_INT Fld(1,26,AC_MSKB3)//[11:11]
    #define FLD_I2C_STAR_INT Fld(1,25,AC_MSKB3)//[11:11]
    #define FLD_I2C_STOP_INT Fld(1,24,AC_MSKB3)//[11:11]
    #define FLD_I2C_WR_DATA_INT Fld(1,23,AC_MSKB2)//[11:11]
    #define FLD_I2C_RD_DATA_INT Fld(1,22,AC_MSKB2)//[11:11]
    #define FLD_DATA_END_DONE_INT Fld(1,21,AC_MSKB2)//[11:11]
    #define FLD_DATA_END_FAIL_INT Fld(1,20,AC_MSKB2)//[11:11]
    #define FLD_HW_TRAN_SEND_TRIG_INT Fld(1,19,AC_MSKB2)//[11:11]
    #define FLD_CBUS_DDC_WR_INT Fld(1,18,AC_MSKB2)//[11:11]
    #define FLD_HW_TRAN_SEND_OK_INT Fld(1,17,AC_MSKB2)//[10:10]
    #define FLD_HW_TRAN_SEND_FAIL_INT Fld(1,16,AC_MSKB2)//[9:3]
    #define FLD_TRAN_FSM Fld(5,11,AC_MSKB1)//[2:2]
    #define FLD_SIFM_FSM Fld(3,8,AC_MSKB1)//[1:1]
    #define FLD_EDID_OFFSET Fld(8,0,AC_MSKW10)//[0:0]

//HDMI1 edid
#define PDWNC_EDID1_DEV0 (PDWNC_IO_BASE + 0xE00)
    #define FLD_EDID1_SW_RST0 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID1_DE_CNT0 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID1_DEGLITCH0_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID1_EDID0_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID1_DEVICE_ADDR0 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID1_DEV1 (PDWNC_IO_BASE + 0xE04)
    #define FLD_EDID1_SW_RST1 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID1_DE_CNT1 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID1_DEGLITCH1_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID1_EDID1_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID1_DEVICE_ADDR1 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID1_DEV2 (PDWNC_IO_BASE + 0xE08)
    #define FLD_EDID1_SW_RST2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID1_DE_CNT2 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID1_DEGLITCH2_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID1_EDID2_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID1_DEVICE_ADDR2 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID1_DEV3 (PDWNC_IO_BASE + 0xE0C)
    #define FLD_EDID1_SW_RST3 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID1_DE_CNT3 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID1_DEGLITCH3_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID1_EDID3_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID1_DEVICE_ADDR3 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID1_CTL1 (PDWNC_IO_BASE + 0xE10)
    #define FLD_EDID1_PHY_ADDR1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_EDID1_OFFSET1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EDID1_CHKSUM1 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID1_CTL2 (PDWNC_IO_BASE + 0xE14)
    #define FLD_EDID1_PHY_ADDR2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_EDID1_OFFSET2 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EDID1_CHKSUM2 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID1_CTL3 (PDWNC_IO_BASE + 0xE18)
    #define FLD_EDID1_PHY_ADDR3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_EDID1_OFFSET3 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EDID1_CHKSUM3 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID1_ADDR (PDWNC_IO_BASE + 0xE1C)
    #define FLD_EDID1_ADDR_FIX Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_EDID1_EDID_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID1_DATA (PDWNC_IO_BASE + 0xE20)
    #define FLD_EDID1_EDID_DATA Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID1_SDA_SEL (PDWNC_IO_BASE + 0xE24)
    #define FLD_EDID1_STOP_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID1_START_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_HDMI1_EDID2_DET (PDWNC_IO_BASE + 0xE30)
    #define FLD_EDID1_DEV3 Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_EDID1_DEV2 Fld(7,17,AC_MSKB2)//[23:17]
    #define FLD_EDID1_DEV1 Fld(7,9,AC_MSKB1)//[15:9]
    #define FLD_EDID1_DEV0 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_HDMI2_EDID1_DET_INTSTA (PDWNC_IO_BASE + 0xE34)
    #define FLD_EDID1_DEV3_DET_INT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_EDID1_DEV2_DET_INT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_EDID1_DEV1_DET_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID1_DEV0_DET_INT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_HDMI2_EDID1_DET_INTEN (PDWNC_IO_BASE + 0xE38)
    #define FLD_EDID1_DEV3_DET_INTEN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_EDID1_DEV2_DET_INTEN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_EDID1_DEV1_DET_INTEN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID1_DEV0_DET_INTEN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_HDMI2_EDID1_DET_INTCLR (PDWNC_IO_BASE + 0xE3C)
    #define FLD_EDID1_DEV3_DET_INTCLR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_EDID1_DEV2_DET_INTCLR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_EDID1_DEV1_DET_INTCLR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID1_DEV0_DET_INTCLR Fld(1,0,AC_MSKB0)//[0:0]
    //HDMI2 edid
#define PDWNC_EDID2_DEV0 (PDWNC_IO_BASE + 0xE40)
    #define FLD_EDID2_SW_RST0 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID2_DE_CNT0 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID2_DEGLITCH0_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID2_EDID0_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID2_DEVICE_ADDR0 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID2_DEV1 (PDWNC_IO_BASE + 0xE44)
    #define FLD_EDID2_SW_RST1 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID2_DE_CNT1 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID2_DEGLITCH1_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID2_EDID1_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID2_DEVICE_ADDR1 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID2_DEV2 (PDWNC_IO_BASE + 0xE48)
    #define FLD_EDID2_SW_RST2 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID2_DE_CNT2 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID2_DEGLITCH2_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID2_EDID2_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID2_DEVICE_ADDR2 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID2_DEV3 (PDWNC_IO_BASE + 0xE4C)
    #define FLD_EDID2_SW_RST3 Fld(1,31,AC_MSKB3)//[31:31]
    #define FLD_EDID2_DE_CNT3 Fld(8,20,AC_MSKW32)//[27:20]
    #define FLD_EDID2_DEGLITCH3_EN Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_EDID2_EDID3_DIS Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_EDID2_DEVICE_ADDR3 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_EDID2_CTL1 (PDWNC_IO_BASE + 0xE50)
    #define FLD_EDID2_PHY_ADDR1 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_EDID2_OFFSET1 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EDID2_CHKSUM1 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID2_CTL2 (PDWNC_IO_BASE + 0xE54)
    #define FLD_EDID2_PHY_ADDR2 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_EDID2_OFFSET2 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EDID2_CHKSUM2 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID2_CTL3 (PDWNC_IO_BASE + 0xE58)
    #define FLD_EDID2_PHY_ADDR3 Fld(16,16,AC_FULLW32)//[31:16]
    #define FLD_EDID2_OFFSET3 Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_EDID2_CHKSUM3 Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID2_ADDR (PDWNC_IO_BASE + 0xE5C)
    #define FLD_EDID2_ADDR_FIX Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_EDID2_EDID_ADDR Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID2_DATA (PDWNC_IO_BASE + 0xE60)
    #define FLD_EDID2_EDID_DATA Fld(8,0,AC_FULLB0)//[7:0]
#define PDWNC_EDID2_SDA_SEL (PDWNC_IO_BASE + 0xE64)
    #define FLD_EDID2_STOP_ENABLE Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID2_START_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_HDMI2_EDID2_DET (PDWNC_IO_BASE + 0xE70)
    #define FLD_EDID2_DEV3 Fld(7,25,AC_MSKB3)//[31:25]
    #define FLD_EDID2_DEV2 Fld(7,17,AC_MSKB2)//[23:17]
    #define FLD_EDID2_DEV1 Fld(7,9,AC_MSKB1)//[15:9]
    #define FLD_EDID2_DEV0 Fld(7,1,AC_MSKB0)//[7:1]
#define PDWNC_HDMI2_EDID2_DET_INTSTA (PDWNC_IO_BASE + 0xE74)
    #define FLD_EDID2_DEV3_DET_INT Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_EDID2_DEV2_DET_INT Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_EDID2_DEV1_DET_INT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID2_DEV0_DET_INT Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_HDMI2_EDID2_DET_INTEN (PDWNC_IO_BASE + 0xE78)
    #define FLD_EDID2_DEV3_DET_INTEN Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_EDID2_DEV2_DET_INTEN Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_EDID2_DEV1_DET_INTEN Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID2_DEV0_DET_INTEN Fld(1,0,AC_MSKB0)//[0:0]
#define PDWNC_HDMI2_EDID2_DET_INTCLR (PDWNC_IO_BASE + 0xE7C)
    #define FLD_EDID2_DEV3_DET_INTCLR Fld(1,3,AC_MSKB0)//[3:3]
    #define FLD_EDID2_DEV2_DET_INTCLR Fld(1,2,AC_MSKB0)//[2:2]
    #define FLD_EDID2_DEV1_DET_INTCLR Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_EDID2_DEV0_DET_INTCLR Fld(1,0,AC_MSKB0)//[0:0]

    //SCDC
#define SCDC_REG00 (PDWNC_IO_BASE + 0xc80)
    #define REG_SCDCS_MFG_SPFC_SW_SEL Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_RRGEN_FSM_STATE Fld(3,17,AC_MSKB2)//[19:17]
    #define REG_RRGEN_FSM_SET Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_CHR_ERRCNT_MAX_W Fld(1,14,AC_MSKB1)//[14:14]
    #define REG_1S_IN_20MS_CNT_W Fld(1,13,AC_MSKB1)//[13:13]
    #define REG_100MS_IN_1MS_CNT_W Fld(1,12,AC_MSKB1)//[12:12]
    #define REG_20MS_IN_1MS_CNT_W Fld(1,11,AC_MSKB1)//[11:11]
    #define REG_1MS_IN_500NS_CNT_W Fld(1,10,AC_MSKB1)//[10:10]
    #define REG_4P7US_IN_500NS_CNT_W Fld(1,9,AC_MSKB1)//[9:9]
    #define REG_500NS_CALIB_CNT_W Fld(1,8,AC_MSKB1)//[8:8]
    #define REG_REG_SCDC_RST_B Fld(1,2,AC_MSKB0)//[2:2]
    #define REG_DDCS_RST_B Fld(1,1,AC_MSKB0)//[1:1]
    #define REG_SCDC_DDC_EN Fld(1,0,AC_MSKB0)//[0:0]
#define SCDC_REG01 (PDWNC_IO_BASE + 0xc84)
    #define REG_100MS_IN_1MS_CNT_ Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_20MS_IN_1MS_CNT_ Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_4P7US_IN_500NS_CNT_ Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_500NS_CALIB_CNT_ Fld(8,0,AC_FULLB0)//[7:0]
#define SCDC_REG02 (PDWNC_IO_BASE + 0xc88)
    #define REG_CHR_ERRCNT_MAX_ Fld(15,16,AC_MSKW32)//[30:16]
    #define REG_1MS_IN_500NS_CNT_ Fld(11,0,AC_MSKW10)//[10:0]
#define SCDC_REG03 (PDWNC_IO_BASE + 0xc8C)
    #define REG_SCDCS_MFG_OUI3 Fld(8,24,AC_FULLB3)//[31:24]
    #define REG_SCDCS_MFG_OUI2 Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_SCDCS_MFG_OUI1 Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_1S_IN_20MS_CNT_ Fld(8,0,AC_FULLB0)//[7:0]
#define SCDC_REG04 (PDWNC_IO_BASE + 0xc90)
    #define REG_1S_IN_20MS_CNT_ Fld(8,0,AC_FULLB0)//[7:0]
#define SCDC_REG05 (PDWNC_IO_BASE + 0xc94)
    #define REG_1S_IN_20MS_CNT_ Fld(8,0,AC_FULLB0)//[7:0]
#define SCDC_REG06 (PDWNC_IO_BASE + 0xc98)
    #define REG_SCDCS_SW_MNR_REV Fld(8,16,AC_FULLB2)//[23:16]
    #define REG_SCDCS_SW_MJR_REV Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_SCDCS_HW_MJR_REV Fld(4,4,AC_MSKB0)//[7:4]
    #define REG_SCDCS_HW_MNR_REV Fld(4,0,AC_MSKB0)//[3:0]
#define SCDC_REG07 (PDWNC_IO_BASE + 0xc9C)
    #define REG_SCDCS_MFCTR_SPCF31_0 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG08 (PDWNC_IO_BASE + 0xca0)
    #define REG_SCDCS_MFCTR_SPCF63_32 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG09 (PDWNC_IO_BASE + 0xca4)
    #define REG_SCDCS_MFCTR_SPCF95_64 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG0A (PDWNC_IO_BASE + 0xca8)
    #define REG_SCDCS_MFCTR_SPCF127_96 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG0B (PDWNC_IO_BASE + 0xcaC)
    #define REG_SCDCS_MFCTR_SPCF159_128 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG0C (PDWNC_IO_BASE + 0xcb0)
    #define REG_SCDCS_MFCTR_SPCF191_160 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG0D (PDWNC_IO_BASE + 0xcb4)
    #define REG_SCDCS_MFCTR_SPCF223_192 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG0E (PDWNC_IO_BASE + 0xcb8)
    #define REG_SCDCS_MFCTR_SPCF255_224 Fld(32,0,AC_FULLDW)//[31:0]
#define SCDC_REG0F (PDWNC_IO_BASE + 0xcbC)
    #define REG_SCDCS_MFCTR_SPCF271_256 Fld(16,0,AC_FULLW10)//[15:0]
#define SCDC_REG10 (PDWNC_IO_BASE + 0xcc0)
    #define REG_SW_HDMI2_SEL Fld(1,24,AC_MSKB3)//[24:24]
    #define REG_HDMI2_ON Fld(1,23,AC_MSKB2)//[23:23]
    #define REG_SCRAMBLE_ON Fld(1,22,AC_MSKB2)//[22:22]
    #define REG_SCDCS_DISABLED Fld(1,21,AC_MSKB2)//[21:21]
    #define REG_RETENTION_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define REG_HPD_IN Fld(1,19,AC_MSKB2)//[19:19]
    #define REG_PWR5V Fld(1,18,AC_MSKB2)//[18:18]
    #define REG_SCLN_SEL Fld(1,17,AC_MSKB2)//[17:17]
    #define REG_SCL_SEL Fld(1,16,AC_MSKB2)//[16:16]
    #define REG_SDA_DE_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define REG_SCL_DE_CNT Fld(8,0,AC_FULLB0)//[7:0]
#define SCDC_REG11 (PDWNC_IO_BASE + 0xcc4)
    #define SCDCS_TMDS_BCLK_RATIO Fld(1,24,AC_MSKB3)//[24:24]
    #define SCDCS_SCRBL_ENABLE Fld(1,23,AC_MSKB2)//[23:23]
    #define SCDCS_RR_ENABLE Fld(1,22,AC_MSKB2)//[22:22]
    #define SCDCS_CH2_LOCKED Fld(1,21,AC_MSKB2)//[21:21]
    #define SCDCS_CH1_LOCKED Fld(1,20,AC_MSKB2)//[20:20]
    #define SCDCS_CH0_LOCKED Fld(1,19,AC_MSKB2)//[19:19]
    #define SCDCS_CLK_DETECTED Fld(1,18,AC_MSKB2)//[18:18]
    #define SCDCS_SCRBL_STATUS Fld(1,17,AC_MSKB2)//[17:17]
    #define SCDCS_RR_TEST Fld(1,16,AC_MSKB2)//[16:16]
    #define SCDCS_CED_UPD Fld(1,15,AC_MSKB1)//[15:15]
    #define SCDCS_STS_UPD Fld(1,14,AC_MSKB1)//[14:14]
    #define CH_LOCKED_CLR Fld(3,11,AC_MSKB1)//[13:11]
    #define CHR_ERRDET_CNT_CLR Fld(3,8,AC_MSKB1)//[10:8]
    #define SCDCS_SRC_VER Fld(8,0,AC_FULLB0)//[7:0]
#define SCDC_REG12 (PDWNC_IO_BASE + 0xcc8)
    #define SCDCS_CED_CHKSUM Fld(8,24,AC_FULLB3)//[31:24]
    #define SCDCS_TEST_RD_REQ Fld(1,23,AC_MSKB2)//[23:23]
    #define SCDCS_TEST_RD_REQ_DLY Fld(7,16,AC_MSKB2)//[22:16]
    #define SCDCS_CH0_VALID Fld(1,15,AC_MSKB1)//[15:15]
    #define SCDCS_CH0_CED_CNT Fld(15,0,AC_MSKW10)//[14:0]
#define SCDC_REG13 (PDWNC_IO_BASE + 0xccC)
    #define SCDCS_CH2_VALID Fld(1,31,AC_MSKB3)//[31:31]
    #define SCDCS_CH2_CED_CNT Fld(15,16,AC_MSKW32)//[30:16]
    #define SCDCS_CH1_VALID Fld(1,15,AC_MSKB1)//[15:15]
    #define SCDCS_CH1_CED_CNT Fld(15,0,AC_MSKW10)//[14:0]



/*note: Save DRAM PLL BAND for suspend mode.*/
#define TCM_DRAM_BAND1          (*((volatile UINT32 *)PDWNC_RESRV6))
#define TCM_DRAM_BAND2            (*((volatile UINT32 *)PDWNC_RESRV7))
// Save RGS_MCTLPLL_AUTOK_BAND ([31:25])
#define TCMSET_MCTLPLL_AUTOK_BAND(pll_band)  (TCM_DRAM_BAND1=(TCM_DRAM_BAND1&0xff80ffff)|((pll_band)<<16))
#define TCMGET_MCTLPLL_AUTOK_BAND            (((TCM_DRAM_BAND1&0x007f0000))>>16)
// Save RGS_PHYPLL_A1_AUTOK_BAND ([31:25])
#define TCMSET_A1PHYPLL_AUTOK_BAND(pll_band) (TCM_DRAM_BAND2=(TCM_DRAM_BAND2&0xffffff80)|(pll_band))
#define TCMGET_A1PHYPLL_AUTOK_BAND           ((TCM_DRAM_BAND2&0x0000007f))
// Save RGS_PHYPLL_AB_AUTOK_BAND ([31:25])
#define TCMSET_ABPHYPLL_AUTOK_BAND(pll_band) (TCM_DRAM_BAND2=(TCM_DRAM_BAND2&0xffff80ff)|((pll_band)<<8))
#define TCMGET_ABPHYPLL_AUTOK_BAND           ((TCM_DRAM_BAND2&0x00007f00)>>8)
// Save RGS_PHYPLL_B2_AUTOK_BAND ([31:25])
#define TCMSET_B2PHYPLL_AUTOK_BAND(pll_band) (TCM_DRAM_BAND2=(TCM_DRAM_BAND2&0xff80ffff)|((pll_band)<<16))
#define TCMGET_B2PHYPLL_AUTOK_BAND           ((TCM_DRAM_BAND2&0x007f0000)>>16)
// Save RGS_PHYPLL_C1_AUTOK_BAND ([31:25])
#define TCMSET_C1PHYPLL_AUTOK_BAND(pll_band) (TCM_DRAM_BAND2=(TCM_DRAM_BAND2&0x80ffffff)|((pll_band)<<24))
#define TCMGET_C1PHYPLL_AUTOK_BAND           ((TCM_DRAM_BAND2&0x7f000000)>>24)

#endif //_HW_PDWNC_H_



