#ifndef _HW_GPU_MFG_TOP_H_
#define _HW_GPU_MFG_TOP_H_

#define GPU_MFG_TOP (IO_VIRT+0x3000000)

//Page MFG_TOP_1
#define GPU_MFG_CG_CON (GPU_MFG_TOP + 0x000)
    #define FLD_GPU_MFG_BG3D_PDN Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_CG_SET (GPU_MFG_TOP + 0x004)
    #define FLD_GPU_MFG_BG3D_SET Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_CG_CLR (GPU_MFG_TOP + 0x008)
    #define FLD_GPU_MFG_BG3D_CLR Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_RESET (GPU_MFG_TOP + 0x00C)
    #define FLD_GPU_MFG_G3D_RESET Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_MEM_RESET Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPU_MFG_AXI_RESET Fld(1,2,AC_MSKB0)//[2:2]
#define GPU_MFG_DCM_CON_0 (GPU_MFG_TOP + 0x010)
    #define FLD_GPU_MFG_BG3D_DCM_ALL_IDLE_OPT Fld(1,17,AC_MSKB2)//[17:17]
    #define FLD_GPU_MFG_BG3D_ASYNC_FREE_RUN Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPU_MFG_BG3D_DCM_EN Fld(1,15,AC_MSKB1)//[15:15]
    #define FLD_GPU_MFG_BG3D_DBC_EN Fld(1,14,AC_MSKB1)//[14:14]
    #define FLD_GPU_MFG_BG3D_FSEL Fld(6,8,AC_MSKB1)//[13:8]
    #define FLD_GPU_MFG_BG3D_DBC_CNT Fld(7,0,AC_MSKB0)//[6:0]
#define GPU_MFG_APB_DEBUG (GPU_MFG_TOP + 0x014)
    #define FLD_GPU_MFG_DFD_APB_ERR_ADDR Fld(18,12,AC_MSKDW)//[29:12]
    #define FLD_GPU_MFG_DFD_APB_ERR_TIMEOUT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPU_MFG_DFD_APB_ERR_FLAG_EN Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_ASYNC_CON (GPU_MFG_TOP + 0x020)
    #define FLD_GPU_MFG_SOCIF_SLV_SEL Fld(2,10,AC_MSKB1)//[11:10]
    #define FLD_GPU_MFG_SOCIF_MST_SEL Fld(2,8,AC_MSKB1)//[9:8]
    #define FLD_GPU_MFG_MEM1_SLV_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define FLD_GPU_MFG_MEM0_SLV_SEL Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_GPU_MFG_MEM1_MST_SEL Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_GPU_MFG_MEM0_MST_SEL Fld(2,0,AC_MSKB0)//[1:0]
#define GPU_MFG_SRAM_DELSEL_00 (GPU_MFG_TOP + 0x030)
    #define FLD_GPU_MFG_TXMHRSD_DELSEL Fld(4,0,AC_MSKB0)//[3:0]
    #define FLD_GPU_MFG_TXMRHSD_DELSEL Fld(4,4,AC_MSKB0)//[7:4]
    #define FLD_GPU_MFG_TXMHRPTYD_DELSEL Fld(4,8,AC_MSKB1)//[11:8]
#define GPU_MFG_MBIST_DBG_CON (GPU_MFG_TOP + 0x0A8)
    #define FLD_GPU_MFG_MBIST_DONE_SEL Fld(6,0,AC_MSKB0)//[5:0]
    #define FLD_GPU_MFG_MBIST_FAIL_SEL Fld(9,16,AC_MSKW32)//[24:16]
#define GPU_MFG_GLOBAL_CON (GPU_MFG_TOP + 0x0B0)
    #define FLD_GPU_MFG_PSEL_M_GLOBAL_CON_OPT Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPU_MFG_PSEL_S_GLOBAL_CON_OPT Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_QCHANNEL_CON (GPU_MFG_TOP + 0x0B4)
    #define FLD_GPU_MFG_ACTIVE_SEL Fld(2,0,AC_MSKB0)//[1:0]
    #define FLD_GPU_MFG_QCHANNEL_ENABLE Fld(1,4,AC_MSKB0)//[4:4]
#define GPU_MFG_MBIST_DONE_FAIL (GPU_MFG_TOP + 0x124)
    #define FLD_GPU_MFG_MBIST_FAIL_OR_ALL_X Fld(1,1,AC_MSKB0)//[1:1]
    #define FLD_GPU_MFG_MBIST_DONE_AND_ALL_X1 Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_TIMESTAMP (GPU_MFG_TOP + 0x130)
    #define FLD_GPU_MFG_TOP_TSVALUEB_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_TIMER_SEL Fld(1,1,AC_MSKB0)//[1:1]
#define GPU_MFG_COHERENCYFEATURES (GPU_MFG_TOP + 0x134)
    #define FLD_GPU_MFG_COHERENCY Fld(2,0,AC_MSKB0)//[1:0]
#define GPU_MFG_DEBUG_SEL (GPU_MFG_TOP + 0x180)
    #define FLD_GPU_MFG_DEBUG_SEL Fld(5,0,AC_MSKB0)//[4:0]
#define GPU_MFG_DEBUG_A (GPU_MFG_TOP + 0x184)
    #define FLD_GPU_MFG_DEBUG_A Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DEBUG_B (GPU_MFG_TOP + 0x188)
    #define FLD_GPU_MFG_DEBUG_B Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_00 (GPU_MFG_TOP + 0x1C0)
    #define FLD_GPU_MFG_LAT_MEM_CON_00 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_01 (GPU_MFG_TOP + 0x1C4)
    #define FLD_GPU_MFG_LAT_MEM_CON_01 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_02 (GPU_MFG_TOP + 0x1C8)
    #define FLD_GPU_MFG_LAT_MEM_CON_02 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_03 (GPU_MFG_TOP + 0x1CC)
    #define FLD_GPU_MFG_LAT_MEM_CON_03 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_04 (GPU_MFG_TOP + 0x1D0)
    #define FLD_GPU_MFG_LAT_MEM_CON_04 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_05 (GPU_MFG_TOP + 0x1D4)
    #define FLD_GPU_MFG_LAT_MEM_CON_05 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_06 (GPU_MFG_TOP + 0x1D8)
    #define FLD_GPU_MFG_LAT_MEM_CON_06 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_07 (GPU_MFG_TOP + 0x1DC)
    #define FLD_GPU_MFG_LAT_MEM_CON_07 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_08 (GPU_MFG_TOP + 0x1E0)
    #define FLD_GPU_MFG_LAT_MEM_CON_08 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_09 (GPU_MFG_TOP + 0x1E4)
    #define FLD_GPU_MFG_LAT_MEM_CON_09 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_10 (GPU_MFG_TOP + 0x1E8)
    #define FLD_GPU_MFG_LAT_MEM_CON_10 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_11 (GPU_MFG_TOP + 0x1EC)
    #define FLD_GPU_MFG_LAT_MEM_CON_11 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_MEM_CON_12 (GPU_MFG_TOP + 0x1F0)
    #define FLD_GPU_MFG_LAT_MEM_CON_12 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_00 (GPU_MFG_TOP + 0x1F4)
    #define FLD_GPU_MFG_LAT_CORE_CON_00 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_01 (GPU_MFG_TOP + 0x1F8)
    #define FLD_GPU_MFG_LAT_CORE_CON_01 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_02 (GPU_MFG_TOP + 0x1FC)
    #define FLD_GPU_MFG_LAT_CORE_CON_02 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_03 (GPU_MFG_TOP + 0x200)
    #define FLD_GPU_MFG_LAT_CORE_CON_03 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_04 (GPU_MFG_TOP + 0x204)
    #define FLD_GPU_MFG_LAT_CORE_CON_04 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_05 (GPU_MFG_TOP + 0x208)
    #define FLD_GPU_MFG_LAT_CORE_CON_05 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_06 (GPU_MFG_TOP + 0x20C)
    #define FLD_GPU_MFG_LAT_CORE_CON_06 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_07 (GPU_MFG_TOP + 0x210)
    #define FLD_GPU_MFG_LAT_CORE_CON_07 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_08 (GPU_MFG_TOP + 0x214)
    #define FLD_GPU_MFG_LAT_CORE_CON_08 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_09 (GPU_MFG_TOP + 0x218)
    #define FLD_GPU_MFG_LAT_CORE_CON_09 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_10 (GPU_MFG_TOP + 0x21C)
    #define FLD_GPU_MFG_LAT_CORE_CON_10 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_11 (GPU_MFG_TOP + 0x220)
    #define FLD_GPU_MFG_LAT_CORE_CON_11 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_12 (GPU_MFG_TOP + 0x224)
    #define FLD_GPU_MFG_LAT_CORE_CON_12 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_13 (GPU_MFG_TOP + 0x228)
    #define FLD_GPU_MFG_LAT_CORE_CON_13 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_14 (GPU_MFG_TOP + 0x22C)
    #define FLD_GPU_MFG_LAT_CORE_CON_14 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_15 (GPU_MFG_TOP + 0x230)
    #define FLD_GPU_MFG_LAT_CORE_CON_15 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_16 (GPU_MFG_TOP + 0x234)
    #define FLD_GPU_MFG_LAT_CORE_CON_16 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_17 (GPU_MFG_TOP + 0x238)
    #define FLD_GPU_MFG_LAT_CORE_CON_17 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CON_18 (GPU_MFG_TOP + 0x23C)
    #define FLD_GPU_MFG_LAT_CORE_CON_18 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_CLK_CNT (GPU_MFG_TOP + 0x240)
    #define FLD_GPU_MFG_CORE_CLK_CNT_LATCH Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_CORE_GATED_CLK_CNT (GPU_MFG_TOP + 0x244)
    #define FLD_GPU_MFG_GATED_CORE_CLK_CNT_LATCH Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_DCM_CON (GPU_MFG_TOP + 0x248)
    #define FLD_GPU_MFG_LAT_DCM_ENABLE Fld(1,0,AC_MSKB0)//[0:0]
#define GPU_MFG_LAT_DEBUG (GPU_MFG_TOP + 0x24C)
    #define FLD_GPU_MFG_LAT_VCORE_DEBUG Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_DEBUG1 (GPU_MFG_TOP + 0x250)
    #define FLD_GPU_MFG_LAT_VGPU_DEBUG Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_LAT_DEBUG2 (GPU_MFG_TOP + 0x254)
    #define FLD_GPU_MFG_LAT_VGPU_DEBUG_NEW Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_CFG_00 (GPU_MFG_TOP + 0x25C)
    #define FLD_GPU_MFG_MBIST_BSEL Fld(16,0,AC_FULLW10)//[15:0]
    #define FLD_GPU_MFG_MBIST_HOLDB Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPU_MFG_MBIST_DIAG_CLKEN Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPU_MFG_MBIST_RSTB Fld(1,31,AC_MSKB3)//[31:31]
#define GPU_MFG_MBIST_CFG_01 (GPU_MFG_TOP + 0x260)
    #define FLD_GPU_MFG_MBIST_BG Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_MBIST_MODE_00 (GPU_MFG_TOP + 0x264)
    #define FLD_GPU_MFG_MBIST_MODE_00 Fld(14,0,AC_MSKW10)//[13:0]
#define GPU_MFG_MBIST_MODE_01 (GPU_MFG_TOP + 0x268)
    #define FLD_GPU_MFG_MBIST_MODE_01 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_MODE_02 (GPU_MFG_TOP + 0x26C)
    #define FLD_GPU_MFG_MBIST_MODE_02 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_MODE_03 (GPU_MFG_TOP + 0x270)
    #define FLD_GPU_MFG_MBIST_MODE_03 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_DONE_00 (GPU_MFG_TOP + 0x2D0)
    #define FLD_GPU_MFG_MBIST_DONE_00 Fld(14,0,AC_MSKW10)//[13:0]
#define GPU_MFG_MBIST_DONE_01 (GPU_MFG_TOP + 0x2D4)
    #define FLD_GPU_MFG_MBIST_DONE_01 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_DONE_02 (GPU_MFG_TOP + 0x2D8)
    #define FLD_GPU_MFG_MBIST_DONE_02 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_DONE_03 (GPU_MFG_TOP + 0x2DC)
    #define FLD_GPU_MFG_MBIST_DONE_03 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_FAIL_00 (GPU_MFG_TOP + 0x350)
    #define FLD_GPU_MFG_MBIST_FAIL_00 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_01 (GPU_MFG_TOP + 0x354)
    #define FLD_GPU_MFG_MBIST_FAIL_01 Fld(13,0,AC_MSKW10)//[12:0]
#define GPU_MFG_MBIST_FAIL_02 (GPU_MFG_TOP + 0x358)
    #define FLD_GPU_MFG_MBIST_FAIL_02 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_03 (GPU_MFG_TOP + 0x35C)
    #define FLD_GPU_MFG_MBIST_FAIL_03 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_04 (GPU_MFG_TOP + 0x360)
    #define FLD_GPU_MFG_MBIST_FAIL_04 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_05 (GPU_MFG_TOP + 0x364)
    #define FLD_GPU_MFG_MBIST_FAIL_05 Fld(22,0,AC_MSKDW)//[21:0]
#define GPU_MFG_MBIST_FAIL_06 (GPU_MFG_TOP + 0x368)
    #define FLD_GPU_MFG_MBIST_FAIL_06 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_07 (GPU_MFG_TOP + 0x36C)
    #define FLD_GPU_MFG_MBIST_FAIL_07 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_08 (GPU_MFG_TOP + 0x370)
    #define FLD_GPU_MFG_MBIST_FAIL_08 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_09 (GPU_MFG_TOP + 0x374)
    #define FLD_GPU_MFG_MBIST_FAIL_09 Fld(22,0,AC_MSKDW)//[21:0]
#define GPU_MFG_MBIST_FAIL_10 (GPU_MFG_TOP + 0x378)
    #define FLD_GPU_MFG_MBIST_FAIL_10 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_11 (GPU_MFG_TOP + 0x37C)
    #define FLD_GPU_MFG_MBIST_FAIL_11 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_12 (GPU_MFG_TOP + 0x380)
    #define FLD_GPU_MFG_MBIST_FAIL_12 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_MBIST_FAIL_13 (GPU_MFG_TOP + 0x384)
    #define FLD_GPU_MFG_MBIST_FAIL_13 Fld(22,0,AC_MSKDW)//[21:0]
#define GPU_MFG_PERF_EN_00 (GPU_MFG_TOP + 0x3C0)
    #define FLD_GPU_MFG_PERF_EN_00 Fld(12,0,AC_MSKW10)//[11:0]
#define GPU_MFG_PERF_EN_01 (GPU_MFG_TOP + 0x3C4)
    #define FLD_GPU_MFG_PERF_EN_01 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_PERF_EN_02 (GPU_MFG_TOP + 0x3C8)
    #define FLD_GPU_MFG_PERF_EN_02 Fld(8,0,AC_FULLB0)//[7:0]
#define GPU_MFG_PERF_EN_03 (GPU_MFG_TOP + 0x3CC)
    #define FLD_GPU_MFG_PERF_EN_03 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_PERF_EN_04 (GPU_MFG_TOP + 0x3D0)
    #define FLD_GPU_MFG_PERF_EN_04 Fld(8,0,AC_FULLB0)//[7:0]
#define GPU_MFG_PERF_EN_05 (GPU_MFG_TOP + 0x3D4)
    #define FLD_GPU_MFG_PERF_EN_05 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_PERF_EN_06 (GPU_MFG_TOP + 0x3D8)
    #define FLD_GPU_MFG_PERF_EN_06 Fld(8,0,AC_FULLB0)//[7:0]
#define GPU_MFG_ACTIVE_POWER_CON_00 (GPU_MFG_TOP + 0x400)
    #define FLD_GPU_MFG_RG_SC0_ACTIVE_PWRCTL_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_RG_SC0_FORCE_ABORT_OFF2ON Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_RG_SC0_FORCE_ABORT_ON2OFF Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPU_MFG_RG_SC0_APM_SW_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPU_MFG_RG_SC0_APM_SW_STEP Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPU_MFG_SC0_APM_COUNTER Fld(10,16,AC_MSKW32)//[25:16]
#define GPU_MFG_ACTIVE_POWER_CON_01 (GPU_MFG_TOP + 0x404)
    #define FLD_GPU_MFG_RG_SC0_MEM_PD_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC0_ACTIVE_PWRCTL_RSV Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_02 (GPU_MFG_TOP + 0x408)
    #define FLD_GPU_MFG_RG_SC0_PWR_ON_CNT_START Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC0_PWR_ON_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC0_PWR_ON_S_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_GPU_MFG_RG_SC0_CLK_EN_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_03 (GPU_MFG_TOP + 0x40C)
    #define FLD_GPU_MFG_RG_SC0_PWR_ISOOFF_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC0_PWR_ON_RST_B_0_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC0_PWR_ON_RST_B_1_CNT Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_ACTIVE_POWER_CON_04 (GPU_MFG_TOP + 0x410)
    #define FLD_GPU_MFG_RG_SC0_PWR_OFF_CNT_START Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC0_PWR_OFF_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC0_PWR_OFF_S_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_GPU_MFG_RG_SC0_CLK_DIS_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_05 (GPU_MFG_TOP + 0x414)
    #define FLD_GPU_MFG_RG_SC0_PWR_ISO_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC0_PWR_OFF_RST_B_0_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC0_PWR_OFF_RST_B_1_CNT Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_ACTIVE_POWER_CON_06 (GPU_MFG_TOP + 0x418)
    #define FLD_GPU_MFG_RG_SC1_ACTIVE_PWRCTL_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_RG_SC1_FORCE_ABORT_OFF2ON Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_RG_SC1_FORCE_ABORT_ON2OFF Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPU_MFG_RG_SC1_APM_SW_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPU_MFG_RG_SC1_APM_SW_STEP Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPU_MFG_SC1_APM_COUNTER Fld(10,16,AC_MSKW32)//[25:16]
#define GPU_MFG_ACTIVE_POWER_CON_07 (GPU_MFG_TOP + 0x41C)
    #define FLD_GPU_MFG_RG_SC1_MEM_PD_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC1_ACTIVE_PWRCTL_RSV Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_08 (GPU_MFG_TOP + 0x420)
    #define FLD_GPU_MFG_RG_SC1_PWR_ON_CNT_START Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC1_PWR_ON_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC1_PWR_ON_S_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_GPU_MFG_RG_SC1_CLK_EN_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_09 (GPU_MFG_TOP + 0x424)
    #define FLD_GPU_MFG_RG_SC1_PWR_ISOOFF_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC1_PWR_ON_RST_B_0_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC1_PWR_ON_RST_B_1_CNT Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_ACTIVE_POWER_CON_10 (GPU_MFG_TOP + 0x428)
    #define FLD_GPU_MFG_RG_SC1_PWR_OFF_CNT_START Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC1_PWR_OFF_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC1_PWR_OFF_S_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_GPU_MFG_RG_SC1_CLK_DIS_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_11 (GPU_MFG_TOP + 0x42C)
    #define FLD_GPU_MFG_RG_SC1_PWR_ISO_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC1_PWR_OFF_RST_B_0_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC1_PWR_OFF_RST_B_1_CNT Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_ACTIVE_POWER_CON_12 (GPU_MFG_TOP + 0x430)
    #define FLD_GPU_MFG_RG_SC2_ACTIVE_PWRCTL_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_RG_SC2_FORCE_ABORT_OFF2ON Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_RG_SC2_FORCE_ABORT_ON2OFF Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPU_MFG_RG_SC2_APM_SW_MODE Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPU_MFG_RG_SC2_APM_SW_STEP Fld(1,9,AC_MSKB1)//[9:9]
    #define FLD_GPU_MFG_SC2_APM_COUNTER Fld(10,16,AC_MSKW32)//[25:16]
#define GPU_MFG_ACTIVE_POWER_CON_13 (GPU_MFG_TOP + 0x434)
    #define FLD_GPU_MFG_RG_SC2_MEM_PD_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC2_ACTIVE_PWRCTL_RSV Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_14 (GPU_MFG_TOP + 0x438)
    #define FLD_GPU_MFG_RG_SC2_PWR_ON_CNT_START Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC2_PWR_ON_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC2_PWR_ON_S_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_GPU_MFG_RG_SC2_CLK_EN_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_15 (GPU_MFG_TOP + 0x43C)
    #define FLD_GPU_MFG_RG_SC2_PWR_ISOOFF_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC2_PWR_ON_RST_B_0_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC2_PWR_ON_RST_B_1_CNT Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_ACTIVE_POWER_CON_16 (GPU_MFG_TOP + 0x440)
    #define FLD_GPU_MFG_RG_SC2_PWR_OFF_CNT_START Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC2_PWR_OFF_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC2_PWR_OFF_S_CNT Fld(8,16,AC_FULLB2)//[23:16]
    #define FLD_GPU_MFG_RG_SC2_CLK_DIS_CNT Fld(8,24,AC_FULLB3)//[31:24]
#define GPU_MFG_ACTIVE_POWER_CON_17 (GPU_MFG_TOP + 0x444)
    #define FLD_GPU_MFG_RG_SC2_PWR_ISO_CNT Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_RG_SC2_PWR_OFF_RST_B_0_CNT Fld(8,8,AC_FULLB1)//[15:8]
    #define FLD_GPU_MFG_RG_SC2_PWR_OFF_RST_B_1_CNT Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_SRAM_DELSEL_01 (GPU_MFG_TOP + 0x500)
    #define FLD_GPU_MFG_TXMHRSD_M4_DELSEL Fld(4,0,AC_MSKB0)//[3:0]
#define GPU_MFG_AXI_SI0_CTL (GPU_MFG_TOP + 0x600)
    #define FLD_GPU_MFG_SI0_WAY_INTERLEAVE_EN Fld(2,0,AC_MSKB0)//[1:0]
    #define FLD_GPU_MFG_SI0_WAY_EN Fld(2,2,AC_MSKB0)//[3:2]
    #define FLD_GPU_MFG_SI0_OUTSTANDING_DISABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_SI0_CTRL_UPDATED Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPU_MFG_SI0_CTRL_BYPASS Fld(1,12,AC_MSKB1)//[12:12]
    #define FLD_GPU_MFG_SI0_B_CHNL_SEL Fld(3,13,AC_MSKB1)//[15:13]
    #define FLD_GPU_MFG_SI0_R_CHNL_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define FLD_GPU_MFG_SI0_DFSLV_SET_RIRQ Fld(1,19,AC_MSKB2)//[19:19]
    #define FLD_GPU_MFG_SI0_DFSLV_SET_WIRQ Fld(1,20,AC_MSKB2)//[20:20]
    #define FLD_GPU_MFG_SI0_SET_BID_MISS Fld(1,21,AC_MSKB2)//[21:21]
    #define FLD_GPU_MFG_SI0_SET_RID_MISS Fld(1,22,AC_MSKB2)//[22:22]
    #define FLD_GPU_MFG_SI0_RD_OT_BUSY Fld(1,23,AC_MSKB2)//[23:23]
    #define FLD_GPU_MFG_SI0_WR_OT_BUSY Fld(1,24,AC_MSKB3)//[24:24]
    #define FLD_GPU_MFG_CG_DISABLE Fld(1,31,AC_MSKB3)//[31:31]
#define GPU_MFG_AXI_SI0_DEC_ERR_IF_0 (GPU_MFG_TOP + 0x604)
    #define FLD_GPU_MFG_SI0_DEC_ERR_ID Fld(14,0,AC_MSKW10)//[13:0]
    #define FLD_GPU_MFG_SI0_DEC_ERR_R Fld(1,16,AC_MSKB2)//[16:16]
    #define FLD_GPU_MFG_SI0_DEC_ERR_W Fld(1,17,AC_MSKB2)//[17:17]
#define GPU_MFG_AXI_SI0_DEC_ERR_IF_1 (GPU_MFG_TOP + 0x608)
    #define FLD_GPU_MFG_SI0_DEC_ERR_ADDR Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_AXI_AXI2APB_CTL (GPU_MFG_TOP + 0x620)
    #define FLD_GPU_MFG_FORCE_PREADY_HIGH_S Fld(4,0,AC_MSKB0)//[3:0]
#define GPU_MFG_LATCTRL_CON_00 (GPU_MFG_TOP + 0x840)
    #define FLD_GPU_MFG_ULTRA_PR_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_ULTRA_LL_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_ULTRA_WR_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define FLD_GPU_MFG_LATENCY_THR Fld(12,16,AC_MSKW32)//[27:16]
#define GPU_MFG_LATCTRL_CON_01 (GPU_MFG_TOP + 0x844)
    #define FLD_GPU_MFG_MONITOR_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_TXN_PERIOD Fld(16,16,AC_FULLW32)//[31:16]
#define GPU_MFG_LATCTRL_CON_02 (GPU_MFG_TOP + 0x848)
    #define FLD_GPU_MFG_LAT_HIST_LV0 Fld(12,0,AC_MSKW10)//[11:0]
    #define FLD_GPU_MFG_LAT_HIST_LV1 Fld(12,16,AC_MSKW32)//[27:16]
#define GPU_MFG_LATCTRL_CON_03 (GPU_MFG_TOP + 0x84C)
    #define FLD_GPU_MFG_LAT_HIST_LV2 Fld(12,0,AC_MSKW10)//[11:0]
    #define FLD_GPU_MFG_LAT_HIST_LV3 Fld(12,16,AC_MSKW32)//[27:16]

//Page MFG_TOP_2
#define GPU_MFG_LATCTRL_CON_04 (GPU_MFG_TOP + 0x850)
    #define FLD_GPU_MFG_LAT_HIST_LV4 Fld(12,0,AC_MSKW10)//[11:0]
    #define FLD_GPU_MFG_LAT_HIST_LV5 Fld(12,16,AC_MSKW32)//[27:16]
#define GPU_MFG_LATCTRL_CON_05 (GPU_MFG_TOP + 0x854)
    #define FLD_GPU_MFG_LAT_HIST_LV6 Fld(12,0,AC_MSKW10)//[11:0]
#define GPU_MFG_LATCTRL_CON_UC (GPU_MFG_TOP + 0x860)
    #define FLD_GPU_MFG_MON_ULTRA_COUNT Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H0 (GPU_MFG_TOP + 0x864)
    #define FLD_GPU_MFG_MON_LAT_HIST_0 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H1 (GPU_MFG_TOP + 0x868)
    #define FLD_GPU_MFG_MON_LAT_HIST_1 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H2 (GPU_MFG_TOP + 0x86C)
    #define FLD_GPU_MFG_MON_LAT_HIST_2 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H3 (GPU_MFG_TOP + 0x870)
    #define FLD_GPU_MFG_MON_LAT_HIST_3 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H4 (GPU_MFG_TOP + 0x874)
    #define FLD_GPU_MFG_MON_LAT_HIST_4 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H5 (GPU_MFG_TOP + 0x878)
    #define FLD_GPU_MFG_MON_LAT_HIST_5 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H6 (GPU_MFG_TOP + 0x87C)
    #define FLD_GPU_MFG_MON_LAT_HIST_6 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_LATCTRL_MON_H7 (GPU_MFG_TOP + 0x880)
    #define FLD_GPU_MFG_MON_LAT_HIST_7 Fld(16,0,AC_FULLW10)//[15:0]
#define GPU_MFG_MERGE_R_CON_00 (GPU_MFG_TOP + 0x8A0)
    #define FLD_GPU_MFG_MERGE_R_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_MERGE_RSHAREABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_MERGE_RNONMODIFIABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPU_MFG_MERGE_RMAXLEN Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_GPU_MFG_MIN_A2R_LATENCY Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_MERGE_R_CON_01 (GPU_MFG_TOP + 0x8A4)
    #define FLD_GPU_MFG_MERGE_RWINDOW_MIN Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_MERGE_RWINDOW_MAX Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_MERGE_W_CON_00 (GPU_MFG_TOP + 0x8B0)
    #define FLD_GPU_MFG_MERGE_W_EN Fld(1,0,AC_MSKB0)//[0:0]
    #define FLD_GPU_MFG_MERGE_WSHAREABLE Fld(1,4,AC_MSKB0)//[4:4]
    #define FLD_GPU_MFG_MERGE_WNONMODIFIABLE Fld(1,5,AC_MSKB0)//[5:5]
    #define FLD_GPU_MFG_MERGE_WMAXLEN Fld(4,8,AC_MSKB1)//[11:8]
    #define FLD_GPU_MFG_MIN_A2W_LATENCY Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_MERGE_W_CON_01 (GPU_MFG_TOP + 0x8B4)
    #define FLD_GPU_MFG_MERGE_WWINDOW_MIN Fld(8,0,AC_FULLB0)//[7:0]
    #define FLD_GPU_MFG_MERGE_WWINDOW_MAX Fld(8,16,AC_FULLB2)//[23:16]
#define GPU_MFG_1TO2_CFG_CON_00 (GPU_MFG_TOP + 0x8F0)
    #define FLD_GPU_MFG_R_DISPATCH_MODE Fld(2,0,AC_MSKB0)//[1:0]
    #define FLD_GPU_MFG_W_DISPATCH_MODE Fld(2,4,AC_MSKB0)//[5:4]
    #define FLD_GPU_MFG_ADDR_HASHING_BIT Fld(2,16,AC_MSKB2)//[17:16]
#define GPU_MFG_1TO2_CFG_CON_01 (GPU_MFG_TOP + 0x8F4)
    #define FLD_GPU_MFG_R_SCRAMBLE_TABLE Fld(16,0,AC_FULLW10)//[15:0]
    #define FLD_GPU_MFG_W_SCRAMBLE_TABLE Fld(16,16,AC_FULLW32)//[31:16]
#define GPU_MFG_DFD_CON_00 (GPU_MFG_TOP + 0xA00)
    #define FLD_GPU_MFG_DFD_CON_00 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_01 (GPU_MFG_TOP + 0xA04)
    #define FLD_GPU_MFG_DFD_CON_01 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_10 (GPU_MFG_TOP + 0xA10)
    #define FLD_GPU_MFG_DFD_CON_10 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_11 (GPU_MFG_TOP + 0xA14)
    #define FLD_GPU_MFG_DFD_CON_11 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_12 (GPU_MFG_TOP + 0xA18)
    #define FLD_GPU_MFG_DFD_CON_12 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_13 (GPU_MFG_TOP + 0xA1C)
    #define FLD_GPU_MFG_DFD_CON_13 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_20 (GPU_MFG_TOP + 0xA20)
    #define FLD_GPU_MFG_DFD_CON_20 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_21 (GPU_MFG_TOP + 0xA24)
    #define FLD_GPU_MFG_DFD_CON_21 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_30 (GPU_MFG_TOP + 0xA30)
    #define FLD_GPU_MFG_DFD_CON_30 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_31 (GPU_MFG_TOP + 0xA34)
    #define FLD_GPU_MFG_DFD_CON_31 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_40 (GPU_MFG_TOP + 0xA40)
    #define FLD_GPU_MFG_DFD_CON_40 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_41 (GPU_MFG_TOP + 0xA44)
    #define FLD_GPU_MFG_DFD_CON_41 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_50 (GPU_MFG_TOP + 0xA50)
    #define FLD_GPU_MFG_DFD_CON_50 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_51 (GPU_MFG_TOP + 0xA54)
    #define FLD_GPU_MFG_DFD_CON_51 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_52 (GPU_MFG_TOP + 0xA58)
    #define FLD_GPU_MFG_DFD_CON_52 Fld(32,0,AC_FULLDW)//[31:0]
#define GPU_MFG_DFD_CON_53 (GPU_MFG_TOP + 0xA5C)
    #define FLD_GPU_MFG_DFD_CON_53 Fld(32,0,AC_FULLDW)//[31:0]

#endif //_HW_GPU_MFG_TOP_H_
