#ifndef _HW_MJC_POST_H_
#define _HW_MJC_POST_H_
#include "x_hal_5381.h"

#ifndef CC_FPGA
#define IO_ADDR_OFST IO_VIRT
#else
#define IO_ADDR_OFST 0xf0000000
#endif

#define MEMC_POST (IO_ADDR_OFST + 0x44000)

//Page MEMC_POST
#define MEMC_POST_B2R_0 (MEMC_POST + 0xA00)
    #define MEMC_POST_STA_PROC_UNDER_C0 Fld(1,29,AC_MSKB3)//[29:29]
    #define MEMC_POST_STA_PROC_UNDER_Y1 Fld(1,28,AC_MSKB3)//[28:28]
    #define MEMC_POST_STA_PROC_UNDER_Y0 Fld(1,27,AC_MSKB3)//[27:27]
    #define MEMC_POST_STA_INIT_UNDER_C0 Fld(1,26,AC_MSKB3)//[26:26]
    #define MEMC_POST_STA_INIT_UNDER_Y1 Fld(1,25,AC_MSKB3)//[25:25]
    #define MEMC_POST_STA_INIT_UNDER_Y0 Fld(1,24,AC_MSKB3)//[24:24]
    #define MEMC_POST_C_B2R_WIDTH Fld(12,10,AC_MSKW21)//[21:10]
    #define MEMC_POST_C_MJC_B2R_READY_SEL Fld(2,6,AC_MSKB0)//[7:6]
    #define MEMC_POST_C_4K120_MODE Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_POST_C_BLK16_MODE Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_POST_C_B2R_INIT_FAST Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_B2R_PAT_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_B2R_RPT_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_RD_UNDER_RST Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_CTRL_00 (MEMC_POST + 0xA04)
    #define MEMC_POST_C_OUT_HEIGHT Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_OUT_WIDTH Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_CTRL_01 (MEMC_POST + 0xA08)
    #define MEMC_POST_C_OUT_V_TOTAL Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_OUT_H_TOTAL Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_CTRL_02 (MEMC_POST + 0xA0C)
    #define MEMC_POST_C_MJC_VSYNC_DLY Fld(5,26,AC_MSKB3)//[30:26]
    #define MEMC_POST_C_DISP_MODE Fld(1,25,AC_MSKB3)//[25:25]
    #define MEMC_POST_C_OUT_VSYNC_DIV Fld(1,24,AC_MSKB3)//[24:24]
    #define MEMC_POST_C_OUT_FRM_NO Fld(4,20,AC_MSKB2)//[23:20]
    #define MEMC_POST_C_OUT_RATE Fld(2,18,AC_MSKB2)//[19:18]
    #define MEMC_POST_C_3D_NFS Fld(1,17,AC_MSKB2)//[17:17]
    #define MEMC_POST_C_TEST_HSYNC_RST Fld(1,16,AC_MSKB2)//[16:16]
    #define MEMC_POST_C_MEMC_POST_SW_RST Fld(5,11,AC_MSKB1)//[15:11]
#define MEMC_POST_CTRL_03 (MEMC_POST + 0xA10)
    #define MEMC_POST_C_FRM_TRK_LINE Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_FRM_TRK_STEP Fld(4,9,AC_MSKB1)//[12:9]
    #define MEMC_POST_C_DDDS_TRK_INV Fld(1,8,AC_MSKB1)//[8:8]
    #define MEMC_POST_C_DISP_VPOS Fld(8,0,AC_FULLB0)//[7:0]
#define MEMC_POST_CTRL_04 (MEMC_POST + 0xA14)
    #define MEMC_POST_C_OUT_V_START Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_OUT_H_START Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_CTRL_05 (MEMC_POST + 0xA18)
    #define MEMC_POST_C_DISP_SYNC_SELF Fld(1,23,AC_MSKB2)//[23:23]
    #define MEMC_POST_C_OUT_FREE_VSYNC Fld(1,22,AC_MSKB2)//[22:22]
    #define MEMC_POST_C_SEE_READ_IN Fld(1,21,AC_MSKB2)//[21:21]
    #define MEMC_POST_C_OUT_PROG_V_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define MEMC_POST_C_OUT_PROG_H_EN Fld(1,19,AC_MSKB2)//[19:19]
    #define MEMC_POST_C_OUT_SET_END_EN Fld(1,18,AC_MSKB2)//[18:18]
    #define MEMC_POST_C_OUT_VSYNC_INV Fld(1,17,AC_MSKB2)//[17:17]
    #define MEMC_POST_C_OUT_HSYNC_INV Fld(1,16,AC_MSKB2)//[16:16]
    #define MEMC_POST_C_MEMC_POST_DEBUG_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define MEMC_POST_C_MEMC_DBG_SEL Fld(2,10,AC_MSKB1)//[11:10]
#define MEMC_POST_CTRL_06 (MEMC_POST + 0xA1C)
    #define MEMC_POST_C_OUT_V_END Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_OUT_H_END Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_CTRL_07 (MEMC_POST + 0xA20)
    #define MEMC_POST_C_OUT_PROG_V_START Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_OUT_PROG_H_START Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_CTRL_08 (MEMC_POST + 0xA24)
    #define MEMC_POST_C_OUT_PROG_V_END Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_OUT_PROG_H_END Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_CTRL_09 (MEMC_POST + 0xA28)
    #define MEMC_POST_C_DISP_VSYNC_DLY Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_CTRL_10 (MEMC_POST + 0xA2C)
    #define MEMC_POST_C_CEN_SEED Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_CTRL_11 (MEMC_POST + 0xA30)
    #define MEMC_POST_C_VS_FP Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_VS_BNK_BP Fld(12,8,AC_MSKW21)//[19:8]
    #define MEMC_POST_C_MEMC_POST_DB_EN Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_POST_C_VSYNC_RDMA_SEL Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_POST_C_VSYNC_ADJ_SEL Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_VSYNC_RDMA_INV Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_VSYNC_ADJ_INV Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_VSGEN_INV Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_CTRL_12 (MEMC_POST + 0xA34)
    #define MEMC_POST_C_VSYNC_MJC_LINE_END Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_VSYNC_MJC_LINE_STR Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_CTRL_13 (MEMC_POST + 0xA38)
    #define C_B2R_BYPASS_PATH_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define C_SRC_SYNC_SEL Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_PTG_0 (MEMC_POST + 0xA40)
    #define MEMC_POST_C_PTG2_YPAT2 Fld(4,28,AC_MSKB3)//[31:28]
    #define MEMC_POST_C_PTG2_YPAT1 Fld(4,24,AC_MSKB3)//[27:24]
    #define MEMC_POST_C_PTG2_PAT_DUTY_CYCLE Fld(5,19,AC_MSKB2)//[23:19]
    #define MEMC_POST_C_PTG2_FREQ_SEL Fld(3,16,AC_MSKB2)//[18:16]
    #define MEMC_POST_C_PTG2_LEFT_SIDE Fld(1,15,AC_MSKB1)//[15:15]
    #define MEMC_POST_C_PTG2_ANGLE_SEL Fld(3,12,AC_MSKB1)//[14:12]
    #define MEMC_POST_C_PTG2_COLOR_MODE Fld(2,10,AC_MSKB1)//[11:10]
    #define MEMC_POST_C_PTG2_PAT_MODE Fld(2,8,AC_MSKB1)//[9:8]
    #define MEMC_POST_C_PTG2_FREERUN_SPEED Fld(4,4,AC_MSKB0)//[7:4]
    #define MEMC_POST_C_PTG2_PAT_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_PTG2_HOR_LINE_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_PTG2_FREERUN_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_PTG_BND_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_PTG_1 (MEMC_POST + 0xA44)
    #define MEMC_POST_C_PTG_BND_W Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_PTG_BND_H Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_STA_0 (MEMC_POST + 0xA48)
    #define MEMC_POST_STA_DISP_V_TOTAL Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_POST_STA_DISP_H_TOTAL Fld(16,0,AC_FULLW10)//[15:0]
    #define MEMC_CMQ_CQ_WDMA_NUM       Fld(4,12,AC_MSKB1)//[15:12]
#define MEMC_POST_RDMA_0 (MEMC_POST + 0xA50)
    #define MEMC_POST_C_DRAM_BURST_LEN_C Fld(5,24,AC_MSKB3)//[28:24]
    #define MEMC_POST_C_DRAM_BURST_LEN_Y Fld(5,19,AC_MSKB2)//[23:19]
    #define MEMC_POST_C_READ_DATA_UNIT_C Fld(5,14,AC_MSKW21)//[18:14]
    #define MEMC_POST_C_READ_DATA_UNIT_Y Fld(5,9,AC_MSKB1)//[13:9]
    #define MEMC_POST_C_RDMA_DB_EN Fld(1,8,AC_MSKB1)//[8:8]
    #define MEMC_POST_STA_MC_RDMA_SEL Fld(1,7,AC_MSKB0)//[7:7]
    #define MEMC_POST_C_DAT_SEL_R2_CMQ Fld(1,6,AC_MSKB0)//[6:6]
    #define MEMC_POST_C_MC_RDMA_DATA_SEL Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_POST_C_SRAM_USE_ONE_EN_C Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_POST_C_SRAM_USE_ONE_EN_Y Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_DATA_8B_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_RDMA_DRAM_RD_C_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_RDMA_DRAM_RD_Y_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_RDMA_1 (MEMC_POST + 0xA54)
    #define MEMC_POST_C_RDMA_STR_ADR_SEL_Y Fld(1,28,AC_MSKB3)//[28:28]
    #define MEMC_POST_C_RDMA_STR_ADR_Y Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_POST_RDMA_2 (MEMC_POST + 0xA58)
    #define MEMC_POST_C_RDMA_STR_ADR_SEL_C Fld(1,28,AC_MSKB3)//[28:28]
    #define MEMC_POST_C_RDMA_STR_ADR_C Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_POST_RDMA_3 (MEMC_POST + 0xA5C)
    #define MEMC_POST_C_BURST_8_EN_C Fld(1,19,AC_MSKB2)//[19:19]
    #define MEMC_POST_C_BURST_8_EN_Y Fld(1,18,AC_MSKB2)//[18:18]
    #define MEMC_POST_C_DRAM_BURST_DATA_C Fld(7,11,AC_MSKW21)//[17:11]
    #define MEMC_POST_C_DRAM_BURST_DATA_Y Fld(7,4,AC_MSKW10)//[10:4]
    #define MEMC_POST_C_READ_PAIR_CNT_C Fld(2,2,AC_MSKB0)//[3:2]
    #define MEMC_POST_C_READ_PAIR_CNT_Y Fld(2,0,AC_MSKB0)//[1:0]
#define MEMC_POST_RDMA_4 (MEMC_POST + 0xA60)
    #define MEMC_POST_C_LAST_TOTAL_C Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_POST_C_LAST_TOTAL_Y Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_POST_RDMA_5 (MEMC_POST + 0xA64)
    #define MEMC_POST_STA_RDMA_B2R_START_CNT_Y Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_POST_STA_RDMA_B2R_VS_START_CNT_Y Fld(8,8,AC_FULLB1)//[15:8]
    #define MEMC_POST_STA_RFIFO_OVERFLOW_C Fld(1,7,AC_MSKB0)//[7:7]
    #define MEMC_POST_STA_RFIFO_OVERFLOW_Y Fld(1,6,AC_MSKB0)//[6:6]
    #define MEMC_POST_STA_RFIFO_UNDERFLOW_C Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_POST_STA_RFIFO_UNDERFLOW_Y Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_POST_C_OVERFLOW_CLR_C Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_OVERFLOW_CLR_Y Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_UNDERFLOW_CLR_C Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_UNDERFLOW_CLR_Y Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_RDMA_6 (MEMC_POST + 0xA68)
    #define MEMC_POST_C_DRAM_FIFO_ULTRA_THR_C Fld(9,11,AC_MSKW21)//[19:11]
    #define MEMC_POST_C_DRAM_FIFO_ULTRA_THR_Y Fld(9,2,AC_MSKW10)//[10:2]
    #define MEMC_POST_C_DRAM_ULTRA_EN_C Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_DRAM_ULTRA_EN_Y Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_RDMA_7 (MEMC_POST + 0xA6C)
    #define MEMC_POST_STA_RDMA_B2R_START_CNT_C Fld(16,16,AC_FULLW32)//[31:16]
    #define MEMC_POST_STA_RDMA_B2R_VS_START_CNT_C Fld(8,8,AC_FULLB1)//[15:8]
#define MEMC_POST_RDMA_8 (MEMC_POST + 0xA70)
    #define MEMC_POST_STA_DLE_TOT_Y Fld(20,0,AC_MSKDW)//[19:0]
#define MEMC_POST_RDMA_9 (MEMC_POST + 0xA74)
    #define MEMC_POST_STA_DLE_TOT_C Fld(20,0,AC_MSKDW)//[19:0]
#define MEMC_POST_RDMA_10 (MEMC_POST + 0xA78)
    #define MEMC_POST_STA_DRAM_LAST_VS_TOT_Y Fld(9,16,AC_MSKW32)//[24:16]
    #define MEMC_POST_STA_DRAM_LAST_TOT_Y Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_POST_RDMA_11 (MEMC_POST + 0xA7C)
    #define MEMC_POST_STA_DRAM_LAST_VS_TOT_C Fld(9,16,AC_MSKW32)//[24:16]
    #define MEMC_POST_STA_DRAM_LAST_TOT_C Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_POST_RDMA_12 (MEMC_POST + 0xA80)
    #define MEMC_POST_STA_SRAM_RADR_V_START_C Fld(9,20,AC_MSKW32)//[28:20]
    #define MEMC_POST_STA_SRAM_RADR_V_START_Y Fld(9,10,AC_MSKW21)//[18:10]
    #define MEMC_POST_STA_SRAM_WADR_V_START_Y Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_POST_RDMA_13 (MEMC_POST + 0xA84)
    #define MEMC_POST_STA_SRAM_WADR_V_START_C Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_POST_RDMA_14 (MEMC_POST + 0xA88)
    #define MEMC_POST_STA_DLE_TOT_VS_Y Fld(20,0,AC_MSKDW)//[19:0]
#define MEMC_POST_RDMA_15 (MEMC_POST + 0xA8C)
    #define MEMC_POST_STA_DLE_TOT_VS_C Fld(20,0,AC_MSKDW)//[19:0]
#define MEMC_POST_RDMA_16 (MEMC_POST + 0xA90)
    #define MEMC_POST_STA_FIFO_SPACE_VS_C Fld(10,12,AC_MSKW21)//[21:12]
    #define MEMC_POST_STA_FIFO_SPACE_VS_Y Fld(10,2,AC_MSKW10)//[11:2]
    #define MEMC_POST_STA_FIFO_FULL_IN_VS_C Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_STA_FIFO_FULL_IN_VS_Y Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_RDMA_17 (MEMC_POST + 0xA94)
    #define MEMC_POST_C_DRAM_DAT_CNT_Y Fld(20,0,AC_MSKDW)//[19:0]
#define MEMC_POST_RDMA_18 (MEMC_POST + 0xA98)
    #define MEMC_POST_C_DRAM_DAT_CNT_C Fld(20,0,AC_MSKDW)//[19:0]
#define MEMC_POST_RDMA_19 (MEMC_POST + 0xA9C)
    #define MEMC_POST_STA_DRAM_DAT_0_Y Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_20 (MEMC_POST + 0xAA0)
    #define MEMC_POST_STA_DRAM_DAT_1_Y Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_21 (MEMC_POST + 0xAA4)
    #define MEMC_POST_STA_DRAM_DAT_2_Y Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_22 (MEMC_POST + 0xAA8)
    #define MEMC_POST_STA_DRAM_DAT_3_Y Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_23 (MEMC_POST + 0xAAC)
    #define MEMC_POST_STA_DRAM_DAT_0_C Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_24 (MEMC_POST + 0xAB0)
    #define MEMC_POST_STA_DRAM_DAT_1_C Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_25 (MEMC_POST + 0xAB4)
    #define MEMC_POST_STA_DRAM_DAT_2_C Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_26 (MEMC_POST + 0xAB8)
    #define MEMC_POST_STA_DRAM_DAT_3_C Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RDMA_27 (MEMC_POST + 0xABC)
    #define C_DRAM_PREULTRA_EN_C Fld(1,1,AC_MSKB0)//[1:1]
    #define C_DRAM_PREULTRA_EN_Y Fld(1,0,AC_MSKB0)//[0:0]
    #define C_DRAM_PREULTRA_RELEASE_C Fld(9,11,AC_MSKW21)//[19:11]
    #define C_DRAM_PREULTRA_RELEASE_Y Fld(9,2,AC_MSKW10)//[10:2]
#define MEMC_POST_RDMA_28 (MEMC_POST + 0xAC0)
    #define C_DRAM_PREULTRA_THR_C Fld(9,10,AC_MSKW21)//[18:10]
    #define C_DRAM_PREULTRA_THR_Y Fld(9,0,AC_MSKW10)//[8:0]
    #define STA_DRAM_PREULTRA_C Fld(1,26,AC_MSKB3)//[26:26]
    #define STA_DRAM_PREULTRA_Y Fld(1,25,AC_MSKB3)//[25:25]
    #define STA_DRAM_ULTRA_C Fld(1,24,AC_MSKB3)//[24:24]
    #define STA_DRAM_ULTRA_Y Fld(1,23,AC_MSKB2)//[23:23]
#define MEMC_POST_RDMA_29 (MEMC_POST + 0xAC4)
    #define C_DRAM_LARB6_PORT_SEL Fld(2,30,AC_MSKB3)//[31:30]
    #define C_DRAM_ULTRA_PREFETCH_EN Fld(1,20,AC_MSKB2)//[20:20]
    #define C_DRAM_ULTRA_RELEASE_C Fld(9,10,AC_MSKW21)//[18:10]
    #define C_DRAM_ULTRA_RELEASE_Y Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_POST_YUV2RGB_0 (MEMC_POST + 0xB00)
    #define MEMC_POST_C_OUT_U10_EN Fld(1,10,AC_MSKB1)//[10:10]
    #define MEMC_POST_C_BYPASS_IDAT_LSB_0_EN Fld(1,9,AC_MSKB1)//[9:9]
    #define MEMC_POST_C_INT_TABLE_SEL Fld(4,5,AC_MSKW10)//[8:5]
    #define MEMC_POST_C_EXT_TABLE_EN Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_POST_C_OUTPUT_SIGNED Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_INPUT_SIGNED Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_YUV2RGB_BYPASS Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_YUV2RGB_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_YUV2RGB_1 (MEMC_POST + 0xB04)
    #define MEMC_POST_C_EXT_PRE_ADD_2 Fld(9,20,AC_MSKW32)//[28:20]
    #define MEMC_POST_C_EXT_PRE_ADD_1 Fld(9,10,AC_MSKW21)//[18:10]
    #define MEMC_POST_C_EXT_PRE_ADD_0 Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_POST_YUV2RGB_2 (MEMC_POST + 0xB08)
    #define MEMC_POST_C_EXT_POST_ADD_2 Fld(9,20,AC_MSKW32)//[28:20]
    #define MEMC_POST_C_EXT_POST_ADD_1 Fld(9,10,AC_MSKW21)//[18:10]
    #define MEMC_POST_C_EXT_POST_ADD_0 Fld(9,0,AC_MSKW10)//[8:0]
#define MEMC_POST_YUV2RGB_3 (MEMC_POST + 0xB0C)
    #define MEMC_POST_C_EXT_C01 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_POST_C_EXT_C00 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_YUV2RGB_4 (MEMC_POST + 0xB10)
    #define MEMC_POST_C_EXT_C10 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_POST_C_EXT_C02 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_YUV2RGB_5 (MEMC_POST + 0xB14)
    #define MEMC_POST_C_EXT_C12 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_POST_C_EXT_C11 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_YUV2RGB_6 (MEMC_POST + 0xB18)
    #define MEMC_POST_C_EXT_C21 Fld(13,16,AC_MSKW32)//[28:16]
    #define MEMC_POST_C_EXT_C20 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_YUV2RGB_7 (MEMC_POST + 0xB1C)
    #define MEMC_POST_C_EXT_C22 Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_YC420_444 (MEMC_POST + 0xB20)
    #define C_420_TO_422_SRAM_DEPTH Fld(10,10,AC_MSKW21)//[19:10]
    #define C_420_TO_444_VSYNC_INV Fld(1,4,AC_MSKB0)//[4:4]
    #define C_420_TO_422_ARIB_EN Fld(1,3,AC_MSKB0)//[3:3]  
    #define MEMC_POST_C_420_TO_422_BYPASS Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_420_TO_444_BYPASS Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_422_TO_444_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_CRC_0 (MEMC_POST + 0xC00)
    #define MEMC_POST_C_CRC_V Fld(1,4,AC_MSKB0)//[4:4]
    #define MEMC_POST_C_CRC_BOT_R_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_CRC_BOT_L_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_CRC_TOP_R_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_CRC_TOP_L_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_CRC_1 (MEMC_POST + 0xC04)
    #define MEMC_POST_C_CRC_V_START Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_CRC_H_START Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_CRC_2 (MEMC_POST + 0xC08)
    #define MEMC_POST_C_CRC_V_END Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_CRC_H_END Fld(13,0,AC_MSKW10)//[12:0]
#define MEMC_POST_CRC_3 (MEMC_POST + 0xC0C)
    #define MEMC_POST_C_CRC_V_MASK Fld(10,20,AC_MSKW32)//[29:20]
    #define MEMC_POST_C_CRC_C_MASK Fld(10,10,AC_MSKW21)//[19:10]
    #define MEMC_POST_C_CRC_Y_MASK Fld(10,0,AC_MSKW10)//[9:0]
#define MEMC_POST_CRC_4 (MEMC_POST + 0xC10)
    #define MEMC_POST_STA_CRC_OUT Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_CRC_5 (MEMC_POST + 0xC14)
    #define MEMC_POST_STA_CRC_OUT_2 Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_DUMP_0 (MEMC_POST + 0xC20)
    #define MEMC_POST_C_POS_Y Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_VSYNC_MEAS_INV Fld(1,15,AC_MSKB1)//[15:15]
    #define MEMC_POST_C_VSYNC_MEAS_DISP Fld(1,14,AC_MSKB1)//[14:14]
    #define MEMC_POST_C_SYNC_SEL Fld(2,12,AC_MSKB1)//[13:12]
    #define MEMC_POST_C_POS_X Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_DUMP_1 (MEMC_POST + 0xC24)
    #define MEMC_POST_STA_HEIGHT Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_STA_WIDTH Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_DUMP_2 (MEMC_POST + 0xC28)
    #define MEMC_POST_STA_DUMP_G Fld(12,16,AC_MSKW32)//[27:16]
    #define MEMC_POST_STA_DUMP_R Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_DUMP_3 (MEMC_POST + 0xC2C)
    #define MEMC_POST_STA_IO_DE_NO_MATCH Fld(1,31,AC_MSKB3)//[31:31]
    #define MEMC_POST_STA_DUMP_B Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_DUMP_4 (MEMC_POST + 0xC30)
    #define MEMC_POST_C_READ_DONE_HEIGHT Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_MUTE_0 (MEMC_POST + 0xC40)
    #define MEMC_POST_C_MUTE_G Fld(12,20,AC_MSKW32)//[31:20]
    #define MEMC_POST_C_MUTE_R Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_MUTE_1 (MEMC_POST + 0xC44)
    #define MEMC_POST_C_MUTE_EN Fld(1,16,AC_MSKB2)//[16:16]
    #define MEMC_POST_C_MUTE_B Fld(12,0,AC_MSKW10)//[11:0]
#define MEMC_POST_STA_1 (MEMC_POST + 0xD00)
    #define MEMC_POST_STA_MJC_B2R_START_CNT_VS_ERR Fld(1,24,AC_MSKB3)//[24:24]
    #define MEMC_POST_STA_MJC_B2R_START_CNT_VS Fld(8,16,AC_FULLB2)//[23:16]
    #define MEMC_POST_STA_MJC_B2R_START_CNT Fld(16,0,AC_FULLW10)//[15:0]
#define MEMC_POST_STA_2 (MEMC_POST + 0xD04)
    #define MEMC_POST_C_B2R_DAT_SEL Fld(4,18,AC_MSKB2)//[21:18]
    #define MEMC_POST_C_B2R_RDY_CNT Fld(18,0,AC_MSKDW)//[17:0]
#define MEMC_POST_STA_3 (MEMC_POST + 0xD0C)
    #define MEMC_POST_STA_B2R_C0 Fld(10,20,AC_MSKW32)//[29:20]
    #define MEMC_POST_STA_B2R_Y1 Fld(10,10,AC_MSKW21)//[19:10]
    #define MEMC_POST_STA_B2R_Y0 Fld(10,0,AC_MSKW10)//[9:0]
#define MEMC_POST_STA_4 (MEMC_POST + 0xD10)
    #define MEMC_POST_STA_DRAM_ADR_Y Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_POST_STA_5 (MEMC_POST + 0xD14)
    #define MEMC_POST_STA_DRAM_ADR_C Fld(28,0,AC_MSKDW)//[27:0]
#define MEMC_POST_MISC_CTRL (MEMC_POST + 0xE00)
    #define C_CRC_VSYNC_INV Fld(1,30,AC_MSKB3)//[30:30]
    #define C_FRM_SAMPLE_LINE Fld(12,16,AC_MSKW32)//[27:16]
    #define C_IMPORT_EN Fld(1,6,AC_MSKB0)//[6:6]
    #define C_LR_FRM_DLY Fld(4,2,AC_MSKB0)//[5:2]
    #define C_LR_OUT_VSAMPLE_SEL Fld(1,1,AC_MSKB0)//[1:1]
    #define C_SETDAT_FRM_DLY Fld(4,12,AC_MSKB1)//[15:12]
    #define C_SETDAT_OUT_VSAMPLE_SEL Fld(1,11,AC_MSKB1)//[11:11]
    #define STA_LR_IN Fld(1,7,AC_MSKB0)//[7:7]
    #define STA_LR_OUT Fld(1,8,AC_MSKB1)//[8:8]
    #define STA_SETDATA_IN Fld(1,28,AC_MSKB3)//[28:28]
    #define STA_SETDATA_OUT Fld(1,29,AC_MSKB3)//[29:29]
#define MEMC_POST_B2R_1 (MEMC_POST + 0xE04)  
    #define C_LINE1TO2_W1_ADR_START Fld(7,24,AC_MSKB3)//[30:24]
    #define C_LINE1TO2_W_ADR_END Fld(7,16,AC_MSKB2)//[22:16]
    #define C_LINE1TO2_R_ADR_END Fld(7,8,AC_MSKB1)//[14:8]
    #define C_LINE1TO2_W_TOT_ADR_END Fld(8,0,AC_FULLB0)//[7:0]
#define MEMC_CLK_EN (MEMC_POST + 0xF00)
    #define MEMC_POST_C_CLK_MJC_EN Fld(1,3,AC_MSKB0)//[3:3]
    #define MEMC_POST_C_CLK_DRAM_EN Fld(1,2,AC_MSKB0)//[2:2]
    #define MEMC_POST_C_CLK_OCLK_EN Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_C_CLK_POCLK_EN Fld(1,0,AC_MSKB0)//[0:0]
#define MEMC_POST_RESERVED_0 (MEMC_POST + 0xFF4)
    #define MEMC_POST_C_MUTE_COLOR_LFT_SHIFT_4BIT Fld(1,5,AC_MSKB0)//[5:5]
    #define MEMC_POST_C_RESERVED_0 Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_RESERVED_1 (MEMC_POST + 0xFF8)
    #define MEMC_POST_C_RESERVED_1 Fld(32,0,AC_FULLDW)//[31:0]
#define MEMC_POST_ATPG (MEMC_POST + 0xFFC)
    #define MEMC_POST_ATPG_OB Fld(1,1,AC_MSKB0)//[1:1]
    #define MEMC_POST_ATPG_CT Fld(1,0,AC_MSKB0)//[0:0]

#endif