/* SPDX-License-Identifier: LGPL-2.1-only OR BSD-3-Clause */
/******************************************************************************
 *
 * This file is provided under a dual license.  When you use or
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 * version 2.1 of the GNU Lesser General Public License 
 * ("LGPLv2.1 License") or BSD License.
 *
 * LGPLv2.1 License
 *
 * Copyright(C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public 
 * License as published by the Free Software Foundation.
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 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html for more
 * details.
 *
 * BSD LICENSE
 *
 * Copyright(C) 2019 MediaTek Inc.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
 * are met:
 *
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/*-----------------------------------------------------------------------------
 *
 * $Author: brianpc.huang $
 * $Date: 2015/05/29 $
 * $RCSfile: gfx_dif.h,v $
 * $Revision: #1 $
 *
 *---------------------------------------------------------------------------*/

/** @file gfx_dif.h
 *  gfx driver data interface
 *  include common interface of hardware and software engine
 *  get/set register base address
 *  get/set idle state
 *  init modules
 */

#ifndef GFX_DIF_H
#define GFX_DIF_H

//---------------------------------------------------------------------------
// Include files
//---------------------------------------------------------------------------

#include "gfx_dif_reg.h"

//---------------------------------------------------------------------------
// Configurations
//---------------------------------------------------------------------------


//---------------------------------------------------------------------------
// Constant definitions
//---------------------------------------------------------------------------

// u4Config
#define MA_DIF_HAVE_GFX_SW              \
    (GFX_DifGetData()->u4Config & GFX_HAVE_SW_MOD)

#define MA_DIF_HAVE_GFX_HW          \
    (GFX_DifGetData()->u4Config & GFX_HAVE_HW_MOD)

#define MA_DIF_HAVE_GFX_FB              \
    (GFX_DifGetData()->u4Config & GFX_HAVE_FB_MOD)

// u4ModInit
#define MA_DIF_GFX_SW_MOD_OK()          \
    (GFX_DifGetData()->u4ModInit |= GFX_HAVE_SW_MOD)

#define MA_DIF_GFX_HW_MOD_OK()      \
    (GFX_DifGetData()->u4ModInit |= GFX_HAVE_HW_MOD)

#define MA_DIF_GFX_FB_MOD_OK()          \
    (GFX_DifGetData()->u4ModInit |= GFX_HAVE_FB_MOD)

//---------------------------------------------------------------------------
// Type definitions
//---------------------------------------------------------------------------

// gfx system capabilities
//  uiConfig - SW_MOD, HW_MOD, etc
//  uiModInit - init bit flag
typedef struct _MI_DIF_T
{
    UINT32 u4Config; // configuration bits, modules
    UINT32 u4GfxMode; // operation mode / module
    UINT32 u4ModInit; // configuration bits, modules status
    UINT32 *pu4CrBase; // control register base address
} MI_DIF_T;

//---------------------------------------------------------------------------
// Inter-file functions
//---------------------------------------------------------------------------


//---------------------------------------------------------------------------
// Public functions
//---------------------------------------------------------------------------

extern void GFX_DifInit(void);

extern void GFX_DifSetRegBase(UINT32 *pu4Base);

extern void GFX_DifGetRegBase(UINT32 *pu4Base);

extern void GFX_DifReset(void);

extern void GFX_DifSetMode(UINT32 u4GfxMode);

extern void GFX_DifSetNotify(void(*pfnNotify)(UINT32));

extern MI_DIF_T *GFX_DifGetData(void);

extern void (*pfnGFX_DifAction)(void);

extern void (*pfnGFX_DifFinNotify)(UINT32);

#endif // GFX_DIF_H
