/*
 * Realtek Semiconductor Corp.
 *
 * bsp.h
 * Board Support Package header file
 *
 * Tony Wu (tonywu@realtek.com.tw)
 * Dec. 07, 2007
 */

#ifndef _BSPCHIP_H_
#define _BSPCHIP_H_

/*
 ******************************
 * DEFINITIONS AND TYPES
 ******************************
 */

/* Register Macro */
#ifndef REG64
#define REG64(reg)      (*(volatile u64 *)(reg))
#endif
#ifndef REG32
#define REG32(reg)      (*(volatile u32 *)(reg))
#endif
#ifndef REG16
#define REG16(reg)      (*(volatile u16 *)(reg))
#endif
#ifndef REG8
#define REG8(reg)       (*(volatile u8  *)(reg))
#endif

/*Memory Macro*/
#ifndef MEM32
#define MEM32(addr)	(*(volatile u32 *)(addr))
#endif

/*
 * Arbiter controller
 */
#define BSP_ARBITER_VADDR	0xB8000200
#define BSP_ARBITER_REG(x) ((x) + BSP_ARBITER_VADDR)
#define BSP_ARBITER_CTRL0	BSP_ARBITER_REG(0)
#define BSP_ARBITER_CTRL1	BSP_ARBITER_REG(0x04)
#define BSP_ARBITER_CTRL2	BSP_ARBITER_REG(0x08)
#define BSP_ARBITER_CTRL3	BSP_ARBITER_REG(0x0c)
#define BSP_ARBITER_CTRL4	BSP_ARBITER_REG(0x10)
#define BSP_ARBITER_CTRL5	BSP_ARBITER_REG(0x14)
#define BSP_ARBITER_CTRL6	BSP_ARBITER_REG(0x18)
#define BSP_ARBITER_CTRL7	BSP_ARBITER_REG(0x1c)
#define BSP_ARBITER_CTRL11	BSP_ARBITER_REG(0x24c)
/*
 ******************************
 * Timer
 ******************************
 */
/* Timer0 register base address mapping */
#define TIMER0_IOBASE		0xB8810000
/*The frequency of timer module*/
#define TIMER0_FREQ		25000000

/* Register offset from TIMERx_IOBASE */
#define TIMER_TLCR1		0x00
#define TIMER_TCV		0x04
#define TIMER_TCR		0x08
#define TIMER_EOIA		0x0c

/*
 ******************************
 * Uart
 ******************************
 */
/* Uart1 register base address mapping */
#define UART1_IOBASE		0xB8810100
/* Serial Clock	*/
#define UART1_FREQ			24000000
#define XB2_UART1_PULL_UP_CTRL 0xb887003c
#define XB2_UART1_PULL_DOWN_CTRL 0xb8870030

#define XB2_UART2_PULL_CTRL 0xb8870048
#define NO_PULL 0
#define PULL_DOWN 1
#define PULL_UP 2
#define UART_RX_PULL_UP (PULL_UP << 2)
#define UART_RX_PULL_DOWN (PULL_DOWN << 2)

/* Register offset from UARTx_IOBASE */
#define UART_RBR		0x00
#define UART_THR		0x00
#define UART_IER		0x04
#define UART_IIR		0x08
#define UART_LCR		0x0C
#define UART_LSR		0x14
#define UART_DLL		0x00
#define UART_DLH		0x04
#define UART_CTR		0xFC

/* uart LCR register bits */
#define UART_LCR_PEN		0x00000008	/* parity enable bit */
#define UART_LCR_EPS		0X00000010
#define UART_LCR_PARITY		(UART_LCR_PEN | UART_LCR_EPS)
#define UART_LCR_STOP		0x00000004	/* stop bit          */
#define UART_LCR_DLS		0x00000003	/* 8 bits mode       */
#define UART_LCR_DLAB		0x00000080	/* DLAB bit          */

#define UART_DL_BAUD_9600		(UART_BAUD_BASE / 9600)
#define UART_DL_BAUD_19200		(UART_BAUD_BASE / 19200)
#define UART_DL_BAUD_38400		(UART_BAUD_BASE / 38400)
#define UART_DL_BAUD_57600		(UART_BAUD_BASE / 57600)
#define UART_DL_BAUD_115200		(UART_BAUD_BASE / 115200)

/* baudrate platform specific setting */
#define UART_BAUD_BASE			(UART1_FREQ >> 4)

#ifdef CONFIG_BAUDRATE_57600
#define UART_BAUD_DEFAULT		UART_DL_BAUD_57600
#endif
#ifdef CONFIG_BAUDRATE_115200
#define UART_BAUD_DEFAULT		UART_DL_BAUD_115200
#endif

#define SYSBASE_VA 0xb8860000
#define SYSBASE_REG(x) ((x) + SYSBASE_VA)

#define CLK_CHANGE		SYSBASE_REG(0x1000)
#define BUS_CLK_CHANGE			0x80
#define XB2_CLK_CHANGE			0x40
#define CPU_CLK_CHANGE			0x20
#define DRAM_CLK_CHANGE		0x10

#define UART_CLK_CFG_REG		SYSBASE_REG(0x1028)
#define CLK_ENABLE 0x1000000

#define CLOCK_SELECT_DIV2	(0x1 << 2)
#define CLOCK_SELECT_DIV4	(0x2 << 2)
#define CLOCK_SELECT_DIV6	(0x3 << 2)
#define CLOCK_SELECT_DIV8	(0x4 << 2)
#define CLOCK_SELECT_DIV10	(0x5 << 2)
#define CLOCK_SELECT_DIV12	(0x6 << 2)
#define CLOCK_SELECT_DIV14	(0x7 << 2)

#define DRAM_OCP_BUS_CLK_CFG_REG		SYSBASE_REG(0x100C)
#define DRAMC_SELECT_USBPLL_2	0
#define DRAMC_SELECT_PLL0_3	0x01
#define DRAMC_SELECT_PLL1_5	0x02
#define DRAMC_SELECT_PLL1_2	0x03

#define CPU_CLK_CFG_REG		SYSBASE_REG(0x1010)
#define CPU_SELECT_USBPLL_3	0
#define CPU_SELECT_PLL0_3	0x01
#define CPU_SELECT_PLL0_2	0x02
#define CPU_SELECT_PLL1_2	0x03

#define XB2_CLK_CFG_REG		SYSBASE_REG(0x1014)
#define XB2_SELECT_USBPLL_2	0
#define XB2_SELECT_PLL0_3	0x01
#define XB2_SELECT_PLL1_2	0x02

#define BUS_CLK_CFG_REG		SYSBASE_REG(0x1018)
#define BUS_SELECT_USBPLL_2	0
#define BUS_SELECT_PLL0_5	0x01
#define BUS_SELECT_PLL1_2	0x02

#define ETHERNET_CLK_CFG_REG		SYSBASE_REG(0x1024)

#define UART_CLK_CFG_REG		SYSBASE_REG(0x1028)
#define UART_SELECT_USBPLL_5    0x0
#define UART_SELECT_PLL0_3    0x01
#define UART_SELECT_PLL1_5    0x02

#define H265_ACLK_CFG_REG		SYSBASE_REG(0x1080)
#define H265_ACLK_ENABLE		0x1000000

#define SYS_PLL0_CTRL			SYSBASE_REG(0x4100)
#define SYS_PLL0_CFG			SYSBASE_REG(0x4104)
#define SYS_PLL0_SSCG_CFG0		SYSBASE_REG(0x4108)
#define SYS_PLL0_SSCG_CFG1		SYSBASE_REG(0x410c)
#define SYS_PLL0_WDOG			SYSBASE_REG(0x4110)
#define SYS_PLL0_STATUS		SYSBASE_REG(0x4114)

#define SYS_PLL1_CTRL			SYSBASE_REG(0x4200)
#define SYS_PLL1_CFG			SYSBASE_REG(0x4204)
#define SYS_PLL1_SSCG_CFG0		SYSBASE_REG(0x4208)
#define SYS_PLL1_SSCG_CFG1		SYSBASE_REG(0x420c)
#define SYS_PLL1_WDOG			SYSBASE_REG(0x4210)
#define SYS_PLL1_STATUS		SYSBASE_REG(0x4214)

#define SYS_PLL2_CTRL			SYSBASE_REG(0x4300)
#define SYS_PLL2_CFG			SYSBASE_REG(0x4304)
#define SYS_PLL2_SSCG_CFG0		SYSBASE_REG(0x4308)
#define SYS_PLL2_SSCG_CFG1		SYSBASE_REG(0x430c)
#define SYS_PLL2_WDOG			SYSBASE_REG(0x4310)
#define SYS_PLL2_STATUS		SYSBASE_REG(0x4314)
#define SYS_PLL_STABLE			0x01

#define PLL_EN_WD_PLL		0x01
#define CMU_EN_CKOOBS_PLL 0x02
#define LDO_EN_PLL			0x04
#define CMU_EN_PLL			0x08
#define PLL_SETP1			0x03
#define PLL_SETP2			0x07

#define	XB2_VA	0xB8870000
#define	XB2BASE_REG(x)	((x) + XB2_VA)
#define	UART_TX_EN_REG		XB2BASE_REG(0x54)
#define   UART0_TX_EN			0x01
#define   UART1_TX_EN			(0x01<<8)
#define   UART2_TX_EN			(0x01<<16)

#define	SPIC_VA	0xB8030000
#define	SPICBASE_REG(x)	((x) + SPIC_VA)
#define	SPIC_BAUD_REG	SPICBASE_REG(0x14)

#define SPIC_BAUDR	0x14
#define SPIC_READ_DUAL_DATA	0xE4
#define SPIC_AUTO_LENGTH	0x11C
#define	SPIC_VALID_CMD	0x120


/* some register about GPIO */
#define GPIO_BASE_ADDR	0xb8800000
#define XB2_GPIO_OE	(GPIO_BASE_ADDR + 0)
#define XB2_GPIO_O	(GPIO_BASE_ADDR + 0x8)
#define XB2_SPI_PULLCTRL	(GPIO_BASE_ADDR + 0x28)
#define XB2_SHARE_GPIO_SELECT	(GPIO_BASE_ADDR + 0x4C)
#define XB2_SHARE_GPIO_OE	(GPIO_BASE_ADDR + 0x50)
#define XB2_SHARE_GPIO_O	(GPIO_BASE_ADDR + 0x58)
#define ALL_SPI_NOPULL	0
#define GPIO_ETN_LED_SEL_REG	(GPIO_BASE_ADDR + 0x006c)
#define GPIO_ETN_LED_SEL_PWM	0
#define XB2_VIDEO_SHARE_GPIO_SELECT	(GPIO_BASE_ADDR + 0x007C)
#define XB2_VIDEO_SHARE_GPIO_OE	(GPIO_BASE_ADDR + 0x0080)
#define XB2_VIDEO_SHARE_GPIO_O	(GPIO_BASE_ADDR + 0x0088)
/*rom download use GPIO4 and GPIO5*/
#define XB2_GPIO_SEL_MASK_4_5 0x30

/* some register about PWM */
#define PWM_BASE_ADDR		0xb8820040
#define PWM_EN_REG		(PWM_BASE_ADDR + 0)
#define PWM_KEEP_REG		(PWM_BASE_ADDR +	0x04)
#define PWM_HIGH_REG		(PWM_BASE_ADDR + 0x08)
#define PWM_LOW_REG		(PWM_BASE_ADDR + 0x0c)
#define PWM_NUM_REG		(PWM_BASE_ADDR + 0x14)
#define PWM_INV_REG		(PWM_BASE_ADDR + 0x18)

/* some register about reset */
#define SYS_RESET_BASE	0xb8860000
#define SYSRESET_REG(x) ((x) + SYS_RESET_BASE)

#define FORCE_REG_RST_FWC	SYSRESET_REG(0x4)
#define FORCE_FEPHY_RST	(1 << 5)

#define FORCE_REG_ASYNC_RST	SYSRESET_REG(0x8)
#define FORCE_ETHERNET_RST	(1 << 6)
#define FORCE_EFUSE_RST	BIT(17)

#define WATCHDOG_CFG_REG SYSRESET_REG(0x2000)
#define WATCHDOG_CTL	SYSRESET_REG(0x2004)
#define WATCHDOG_INT_EN	SYSRESET_REG(0x2008)
#define WATCHDOG_INT_FLAG	SYSRESET_REG(0x200c)

/* some register about watchdog */
#define WATCH_DOG_BASEADDR		0xb8862000
#define WATCH_DOG_CFG_REG		(WATCH_DOG_BASEADDR + 0x0000)
#define WATCH_DOG_CTL_REG		(WATCH_DOG_BASEADDR + 0x0004)
#define WATCH_DOG_INT_ENABLE_REG	(WATCH_DOG_BASEADDR + 0x0008)
#define WATCH_DOG_INT_FLAG_REG		(WATCH_DOG_BASEADDR + 0x000c)

#define WATCH_DOG_PAD_PULLDOWN		0x1
#define WATCH_DOG_TIMEOUT_1S		0x0
#define WATCH_DOG_TIMEOUT_2S		0x1
#define WATCH_DOG_TIMEOUT_4S		0x2
#define WATCH_DOG_TIMEOUT_8S		0x3
#define WATCH_DOG_TIMEOUT_16S		0x4
#define WATCH_DOG_TIMEOUT_32S		0x5
#define WATCH_DOG_TIMEOUT_64S		0x6

#define WATCH_DOG_RESET_SYSTEM		0x1
#define WATCH_DOG_ENABLE		0x1
#define WATCH_DOG_CFG_DATA		((WATCH_DOG_PAD_PULLDOWN << 9) \
					| (WATCH_DOG_TIMEOUT_1S << 16) \
					| (WATCH_DOG_RESET_SYSTEM << 1) \
					| (WATCH_DOG_ENABLE << 0))

/*set UART2 RX to GPIO for WP#*/
#define GPIO_UART2_RXD_BIT	5
#define GPIO_SELECT	1
#define GPIO_OUTPUT_ENABLE	1
#define GPIO_OUTPUT_VALUE	1

#define UART1_SELECT	0xffffff3f

#define SYS_EFUSE_CFG		0xb8865000
#define SYS_EFUSE_CTL		0xb8865004
#define EFUSE_DONE	(1 << 0)
#define SYS_EFUSE_CNT		0xb8865008
#define SYS_EFUSE_RDATA 0xb886500c

#define SYS_EFUSE_OUT0 0xb8865010
#define SYS_EFUSE_OUT1 0xb8865014
#define SYS_EFUSE_OUT2 0xb8865018
#define SYS_EFUSE_OUT3 0xb886501c
#define SYS_EFUSE_OUT4 0xb8865020
#define SYS_EFUSE_OUT5 0xb8865024
#define SYS_EFUSE_OUT6 0xb8865028
#define LOAD_AES_KEY	17
#define EFUSE_POW33	16
#define PROGRAM_POW	14
#define EFUSE_PD	13
#define EFUSE_PS	12
#define EFUSE_CSB	11
#define EFUSE_PGENB	10
#define EFUSE_LOAD	9
#define	EFUSE_STROBE	8

#define SYS_MEM_SD		0xb8866048
#define NAND_MEM_SD			0x300
#define ETH_MEM_SD			0x80
#define CIPHER_MEM_SD			0x40
#define AUDIO_MEM_SD			0x20
#define H264_MEM_SD			0x18
#define U2DEV_MEM_SD			0x04
#define SDIO_MEM_SD			0x03


/*platform configuration*/
#define PLATFORM_CON	0xb8861064
#define ROM_SEL_NOR		(1 << 3)
#define ROM_SEL_NAND	(1 << 2)

/* Values for SPIC_CTRL before relocate */
#define SPICCTRL_DDR_ADDR_BASE	0x82000000
#define SPICCTRL_DDR_ADDR_END	0x820000a0

#define SCKDV			0x1
#define SPIC_BAUD_VALUE		(SCKDV << 0)

#define RD_DUAL_O_CMD		0x3B

#define CS_H_WR_DUM_LEN		0x5
#define CS_H_RD_DUM_LEN		0x0
#define AUCK_DUM_LEN		0x0
#define AUTO_ADDR_LENGTH	0x3
#define RD_DUMMY_LENGTH		0x11
#define SPIC_AUTO_LENGTH_VALUE	((CS_H_WR_DUM_LEN << 28) \
		| (CS_H_RD_DUM_LEN << 26) | (AUCK_DUM_LEN << 18) \
		| (AUTO_ADDR_LENGTH << 16) | RD_DUMMY_LENGTH)

#define WR_BLOCKING		(1 << 9)
#define RD_DUAL_I		(1 << 1)
#define SPIC_VALID_CMD_VALUE	(WR_BLOCKING | RD_DUAL_I)

#define RST_LOAD_MODE_REG			0xb8860028
#define WORK1_MODE_SEL_MASK 0x4
#define WORK2_MODE_SEL_MASK 0x2
#define NOR	0x0
#define NOR_JTAG	0x0
#define	NOR_DOWNLOAD	0x1

#endif

