/*
 * Realtek Semiconductor Corp.
 *
 * Copyright 2012  Jethro Hsu (jethro@realtek.com)
 * Copyright 2012  Tony Wu (tonywu@realtek.com)
 */

#ifndef _SHEIPA_H_
#define _SHEIPA_H_

#include <generated/mtd_mapping_config.h>
#include <generated/autoconf.h>
#include "bspchip.h"

#define NOR_MODE	0x00
#define NAND_MODE	0x01
#define NOR_RES_MODE	0x02
#define NAND_RES_MODE	0x03
#define NOR_SEC_MODE	0x04
#define NAND_SEC_MODE	0x05
#define EMMC_MODE		0x06

#define RESCUE_LOAD_ADDR	0x81000000
#ifdef MTD_MAPPING_CONFIG
#define RESCUE_BIN_LENGTH	RTS_MTD_BOOT_SIZE
#else
#define RESCUE_BIN_LENGTH	0x60000
#endif
#define RESCUE_FLASH_OFFSET	0x0

/*#define CONFIG_ETHADDR	DE:AD:BE:EF:01:01 */  /* Ethernet address */
#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
/*#define CONFIG_IPADDR		192.168.1.26*/

#ifdef CONFIG_BAUDRATE_57600
#define CONFIG_BAUDRATE		57600
#endif
#ifdef CONFIG_BAUDRATE_115200
#define CONFIG_BAUDRATE		115200
#endif
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define FLASHBASEADDR	0xBC000000

#define NO_FW_PARTITION	0xF00000

#ifdef MTD_MAPPING_CONFIG
#define SPI_SECTOR_SIZE		RTS_MTD_FLASH_SECTOR_SIZE
#define SPI_UBOOT_OFFSET	RTS_MTD_BOOT_OFFSET
#define SPI_LOGO_OFFSET	RTS_MTD_LOGO_OFFSET
#define SPI_ROOTFS_SIZE		RTS_MTD_ROOTFS_SIZE
#define SPI_UBOOT_SIZE		RTS_MTD_BOOT_SIZE

#ifdef RTS_MTD_MCU_FW_OFFSET
#define SPI_FW_OFFSET		RTS_MTD_MCU_FW_OFFSET
#else
#define SPI_FW_OFFSET		0x40000
#endif

#ifdef RTS_MTD_HCONF_OFFSET
#define SPI_HW_OFFSET	RTS_MTD_HCONF_OFFSET
#else
#define SPI_HW_OFFSET 0x60000
#endif

#ifdef RTS_MTD_USERDATA_OFFSET
#define SPI_SW_OFFSET	RTS_MTD_USERDATA_OFFSET
#else
#define SPI_SW_OFFSET	0xa0000
#endif

#define SPI_KERNEL_OFFSET	RTS_MTD_KERNEL_OFFSET

#ifdef RTS_MTD_ROOTFS_OFFSET
#define SPI_ROOTFS_OFFSET	RTS_MTD_ROOTFS_OFFSET
#else
#define SPI_ROOTFS_OFFSET	0x520000
#endif

#ifdef RTS_MTD_LDC_OFFSET
#define SPI_LDC_OFFSET	RTS_MTD_LDC_OFFSET
#else
#define SPI_LDC_OFFSET	0xd20000
#endif
#else

#define SPI_SECTOR_SIZE		0x10000
#define SPI_UBOOT_OFFSET	0
#define SPI_FW_OFFSET		0x40000
#define SPI_HW_OFFSET		0x60000
#define SPI_SW_OFFSET		0xa0000
#define SPI_KERNEL_OFFSET	0x120000
#define SPI_ROOTFS_OFFSET	0x520000
#define SPI_LDC_OFFSET	0xd20000
#endif

/*enable prm mode,
 *notice flash must support prm mode,
 *when you enable prm mode, you need
 *modify flash read command and read
 *dummy in parameter table according
 *to flash spec.Now spic only support
 *QUAD_IO prm mode.
 */
//#define SPI_NOR_PRM_MODE
#ifdef CONFIG_RTS_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define HAVE_BLOCK_DEVICE
#endif

#ifdef CONFIG_FS_FAT
#define CONFIG_DOS_PARTITION
#endif

#ifdef CONFIG_RTS_EMMC_BOOT
#define CONFIG_SYS_MMC_ENV_PART	1
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_GPT
#define CONFIG_RANDOM_UUID
#define CONFIG_PARTITION_UUIDS
#define CONFIG_SUPPORT_EMMC_BOOT
#endif

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define CONFIG_BOOTARGS				\
	CONFIG_EXTRA_BOOTARGS			\
	" "					\
	RTS_CMDLINE

/*
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"addmisc=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate} "				\
		"panic=1\0"						\
	"bootfile=/vmlinux.elf\0"					\
	"load=tftp 80500000 ${u-boot}\0"				\
	""
*/

#ifdef CONFIG_KERNEL_ADDR
#define KERNEL_ADDR			CONFIG_KERNEL_ADDR
#else
#define KERNEL_ADDR			"-"
#endif

#ifdef CONFIG_RAMDISK_ADDR
#define RAMDISK_ADDR			CONFIG_RAMDISK_ADDR
#else
#define RAMDISK_ADDR			"-"
#endif

#ifdef CONFIG_FDT_ADDR
#define FDT_ADDR			CONFIG_FDT_ADDR
#else
#define FDT_ADDR			"-"
#endif

/*#if defined(CONFIG_SHEIPA_SPI) && defined(CONFIG_CMD_SF)
 *#define _BOOTCOMMAND(a, b, c)		"sf probe 0:0;"			\
 *					"sf read "a" 0x100000 0x200000;"\
 *					"sf read "c" 0x500000 0x10000;"	\
 *					"bootm "a" "b" "c
 *#else
 *#define _BOOTCOMMAND(a, b, c)		"bootm "a" "b" "c
 *#endif
 *#define CONFIG_BOOTCOMMAND		_BOOTCOMMAND(			\
 *						KERNEL_ADDR,		\
 *						RAMDISK_ADDR,		\
 *						FDT_ADDR)
 */

#ifdef CONFIG_RTS_EMMC_BOOT
#define BOOTADDR	SPI_KERNEL_OFFSET
#else
#define BOOTADDR	FLASHBASEADDR + SPI_KERNEL_OFFSET
#endif

#define CONFIG_BOOTCOMMAND	RTS_BOOTCMD

/*
 * Miscellaneous configurable options
 */
/* undef to save memory */
#undef CONFIG_SYS_LONGHELP

/* Console I/O Buffer Size */
#define	CONFIG_SYS_CBSIZE		512

/* Print Buffer Size */
#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS		17	/* max number of command args*/

#define CONFIG_SYS_MALLOC_LEN		(8 << 20)
#define CONFIG_SYS_BOOTPARAMS_LEN	(32 << 10)
/*#define CONFIG_SYS_MIPS_TIMER_FREQ	25000000*/

#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
#define CONFIG_SYS_SDRAM_SIZE		(64 << 20)

/* default load address */
#define	CONFIG_SYS_LOAD_ADDR		0x80010000

#define	CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START	0x80400000
#define CONFIG_SYS_MEMTEST_END		0x80500000

/*#define CONFIG_RESCUE_LOAD_ADDR		0x81000000
 *#define CONFIG_RESCUE_BIN_LENGTH	0x60000
 *#define CONFIG_RESCUE_FLASH_OFFSET	0x0
 */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	(128)

/* The following #defines are needed to get flash environment right */
#define	CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)

#define CONFIG_SYS_INIT_SP_OFFSET	0x2000000

/* We boot from this flash, selected with dip switch */
#ifdef ATF_BOOT
#ifdef UBOOT_AS_BL33
#define CONFIG_SYS_FLASH_BASE		0xbc000128
#else
#define CONFIG_SYS_FLASH_BASE		0xbc000088
#endif
#else
#define CONFIG_SYS_FLASH_BASE		0xbfc00000
#endif
/* timeout values are in ticks */

/* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ)
 /* Timeout for Flash Write */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ)

/*environment variables setting*/
#ifdef CONFIG_ENV_IN_RAM
#define	CONFIG_ENV_IS_NOWHERE		1
#endif

#if (defined CONFIG_RTS_NOR_BOOT) && (defined CONFIG_ENV_IN_FLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH	1
#endif

#if (defined CONFIG_RTS_NAND_BOOT) && (defined CONFIG_ENV_IN_FLASH)
#define CONFIG_ENV_IS_IN_NAND	1
#endif

#if (defined CONFIG_RTS_EMMC_BOOT) && (defined CONFIG_ENV_IN_MMC)
#define CONFIG_ENV_IS_IN_MMC	1
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif

#define	CONFIG_ENV_OVERWRITE			1

/* Address and size of Primary Environment Sector	*/
#define CONFIG_ENV_ADDR			0xB0030000
#define CONFIG_ENV_SIZE			0x40000
#define CONFIG_FLASH_16BIT
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_NET_MULTI
#define CONFIG_MEMSIZE_IN_BYTES	1

#ifdef CONFIG_ENV_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	SPI_SECTOR_SIZE
#ifdef CONFIG_RTS_NAND_BOOT
#define CONFIG_ENV_OFFSET	0x80000
#elif CONFIG_RTS_NOR_BOOT
#define CONFIG_ENV_OFFSET	0x60000
#endif
#endif

#ifdef CONFIG_ENV_IN_MMC
#define CONFIG_ENV_SECT_SIZE	512
#define CONFIG_ENV_OFFSET	0x80000
#endif

#ifdef CONFIG_ENV_IN_RAM
#define CONFIG_ENV_OFFSET	0
#endif

/*nand flash config*/
#define CONFIG_SYS_NAND_BASE		0xbfc00000
#define CONFIG_SYS_MAX_NAND_DEVICE	1
/*uboot Configuration*/

#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define	CONFIG_AUTO_COMPLETE
#define	CONFIG_CMDLINE_EDITING

#ifdef CONFIG_SELF_EXTRACTING
#define CONFIG_LZMA
#endif

#define DDR_CTL_V2

/*cpu frequency setting*/
#ifdef CONFIG_TARGET_ASIC
#ifdef CONFIG_NPU_650M
/*650M, PLL0 output = (N+2)*25000000 */
#define PLL0_N_SETTING			0x18
#else
/*500M, PLL0 output = (N+2)*25000000 */
#define PLL0_N_SETTING			0x12
#endif

/*800M, PLL0 output = (N+2)*25000000 */
#define PLL1_N_SETTING			0x1E

#ifdef CONFIG_CPU_800M
#define CPU_FREQUCNCY			800000000 /*GPLL1/1*/
#endif
#ifdef CONFIG_CPU_500M
#define CPU_FREQUCNCY			500000000 /*GPLL0/1*/
#endif
#ifdef CONFIG_CPU_400M
#define CPU_FREQUCNCY			400000000 /*PLL1/2/(1-13/64),398437500*/
#endif
#ifdef CONFIG_CPU_333M
#define CPU_FREQUCNCY			333333333 /*PLL0/3*/
#endif
#ifdef CONFIG_CPU_300M
#define CPU_FREQUCNCY			300000000 /*PLL1/2/(1-26/64),296875000*/
#endif
#ifdef CONFIG_CPU_250M
#define CPU_FREQUCNCY			250000000 /*PLL0/4*/
#endif
#ifdef CONFIG_CPU_240M
#define CPU_FREQUCNCY			240000000 /*PLL2/5*/
#endif
#ifdef CONFIG_CPU_200M
#define CPU_FREQUCNCY			200000000 /*PLL0/5*/
#endif
#endif
#ifdef CONFIG_TARGET_FPGA
#define CPU_FREQUCNCY			50000000
#endif

#define CONFIG_SYS_MIPS_TIMER_FREQ	CPU_FREQUCNCY
#define CONFIG_SYS_HZ			1000

/*DDR option*/
#ifdef CONFIG_TARGET_ASIC
#ifdef CONFIG_RTS3915_DDR_H5TQ2G
/*#define CONFIG_DDR_H5TQ2G_112M*/
/*#define CONFIG_DDR_H5TQ2G_200M*/
/*#define CONFIG_DDR_H5TQ2G_400M*/
/*#define CONFIG_DDR_H5TQ2G_667M*/
#define CONFIG_DDR_H5TQ2G_800M
#endif

#ifdef CONFIG_DDR_W975116KG
#define CONFIG_DDR_MCM
#define CONFIG_DDR_W9751V6KG_400M
/*#define CONFIG_DDR_W9751V6KG_533M*/
#endif

#ifdef CONFIG_DDR_NT5CC128M16IP
#define CONFIG_DDR_NT5CC128M16IP_800M
#endif

#ifdef CONFIG_DDR_M15F2G16128A
#define CONFIG_DDR_M15F2G16128A_800M
#endif

#ifdef CONFIG_DDR_W632GG6KB
/*#define CONFIG_DDR_W632GG6KB_667M*/
#define CONFIG_DDR_W632GG6KB_800M
#endif

#ifdef CONFIG_DDR_W631GG6KB
#define CONFIG_DDR_W631GG6KB_800M
#endif

#ifdef CONFIG_DDR_NT5CC64M16IP
#define CONFIG_DDR_NT5CC64M16IP_800M
#endif

#ifdef CONFIG_DDR_M15F1G1664A
#define CONFIG_DDR_M15F1G1664A_800M
#endif

/*When select ddr3,default select 1Gbit ddr.*/
#if defined CONFIG_RTS3915_BGA325_DDR3_GENERAL || \
	defined CONFIG_RTS3915_QFN88_DDR3_1GBIT  || \
	defined CONFIG_RTS3915_QFN128_DDR3_2GBIT || \
	defined CONFIG_RTS3915_BGA325_DDR3_K525 || \
	defined CONFIG_RTS3915_BGA325_DDR3_K525A1
#define DDR3_1GBIT_DEMOBOARD
#endif

#ifdef CONFIG_RTS3915_QFN88_DDR2_512MBIT
#define DDR2_MCM
#endif

/*#define RXSETTING_PER_BYTE*/
#ifndef RXSETTING_PER_BYTE
#define RXSETTING_PER_BIT
#endif

#ifdef CONFIG_DDR3_2GBIT_QABOARD_V11
#define CONFIG_DDR3_2GBIT_QABOARD_V11_800M
#endif
#endif

#ifdef CONFIG_TARGET_FPGA
#ifdef CONFIG_RTS3915_DDR_H5TQ2G
#define DDR_H5TQ2G_112M
#endif
#endif

#define _SYS_PLL_INIT_
#define CONFIG_SKIP_LOWLEVEL_INIT
/*MP configuration*/
#undef CONFIG_DDR_BIST	/*DDR bist test*/

/* init spi flash in board_early_init_r() */
#define CONFIG_BOARD_EARLY_INIT_R

/* LCD */
#ifdef CONFIG_LCD
#define CONFIG_LCD_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_24BMP
#endif

#ifdef CONFIG_RTS_WATCHDOG
#define CONFIG_HW_WATCHDOG
#endif
/*******************for test********************/
/*#define THERMAL_SENSOR_TEST*/
/*#define DMEM_ALL_MEM_TEST*/
/*define SPI_NAND_TEST*/
/*#define ASIC_TEST_CPU*/
#ifdef ASIC_TEST_CPU
/*#define INTERRUPT_TEST_SPIC*/
/*#define INTERRUPT_TEST_TIMER*/
#endif
#endif	/* _SHEIPA_H_ */
